| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* * XCore Disassembler *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | |
| 10 | #include "llvm/MC/MCInst.h" |
| 11 | #include "llvm/MC/MCSubtargetInfo.h" |
| 12 | #include "llvm/Support/DataTypes.h" |
| 13 | #include "llvm/Support/Debug.h" |
| 14 | #include "llvm/Support/LEB128.h" |
| 15 | #include "llvm/Support/raw_ostream.h" |
| 16 | #include "llvm/TargetParser/SubtargetFeature.h" |
| 17 | #include <assert.h> |
| 18 | |
| 19 | namespace { |
| 20 | |
| 21 | // InsnBitWidth is essentially a type trait used by the decoder emitter to query |
| 22 | // the supported bitwidth for a given type. But default, the value is 0, making |
| 23 | // it an invalid type for use as `InsnType` when instantiating the decoder. |
| 24 | // Individual targets are expected to provide specializations for these based |
| 25 | // on their usage. |
| 26 | template <typename T> constexpr uint32_t InsnBitWidth = 0; |
| 27 | |
| 28 | static const uint8_t DecoderTable16[1069] = { |
| 29 | OPC_SwitchField, 11, 5, // 0: switch Inst[15:11] { |
| 30 | 0, 99, // 3: case 0x0: { |
| 31 | OPC_Scope, 59, // 5: try { |
| 32 | OPC_SwitchField, 0, 11, // 7: switch Inst[10:0] { |
| 33 | 236, 15, 4, // 10: case 0x7ec: { |
| 34 | OPC_Decode, 159, 4, 0, // 13: decode to WAITEU_0R using decoder 0 |
| 35 | // 13: } |
| 36 | 237, 15, 4, // 17: case 0x7ed: { |
| 37 | OPC_Decode, 238, 2, 0, // 20: decode to CLRE_0R using decoder 0 |
| 38 | // 20: } |
| 39 | 238, 15, 4, // 24: case 0x7ee: { |
| 40 | OPC_Decode, 135, 4, 0, // 27: decode to SSYNC_0r using decoder 0 |
| 41 | // 27: } |
| 42 | 239, 15, 4, // 31: case 0x7ef: { |
| 43 | OPC_Decode, 142, 3, 0, // 34: decode to FREET_0R using decoder 0 |
| 44 | // 34: } |
| 45 | 252, 15, 4, // 38: case 0x7fc: { |
| 46 | OPC_Decode, 247, 2, 0, // 41: decode to DCALL_0R using decoder 0 |
| 47 | // 41: } |
| 48 | 253, 15, 4, // 45: case 0x7fd: { |
| 49 | OPC_Decode, 173, 3, 0, // 48: decode to KRET_0R using decoder 0 |
| 50 | // 48: } |
| 51 | 254, 15, 4, // 52: case 0x7fe: { |
| 52 | OPC_Decode, 253, 2, 0, // 55: decode to DRET_0R using decoder 0 |
| 53 | // 55: } |
| 54 | 255, 15, 0, // 59: case 0x7ff: { |
| 55 | OPC_Decode, 244, 3, 0, // 62: decode to SETKEP_0R using decoder 0 |
| 56 | // 62: } |
| 57 | // 62: } // switch Inst[10:0] |
| 58 | OPC_Scope, 15, // 66: } else try { |
| 59 | OPC_SwitchField, 4, 7, // 68: switch Inst[10:4] { |
| 60 | 126, 4, // 71: case 0x7e: { |
| 61 | OPC_Decode, 128, 3, 1, // 73: decode to EDU_1r using decoder 1 |
| 62 | // 73: } |
| 63 | 127, 0, // 77: case 0x7f: { |
| 64 | OPC_Decode, 131, 3, 1, // 79: decode to EEU_1r using decoder 1 |
| 65 | // 79: } |
| 66 | // 79: } // switch Inst[10:4] |
| 67 | OPC_Scope, 15, // 83: } else try { |
| 68 | OPC_SwitchField, 4, 1, // 85: switch Inst[4] { |
| 69 | 0, 4, // 88: case 0x0: { |
| 70 | OPC_Decode, 160, 3, 2, // 90: decode to INITPC_2r using decoder 2 |
| 71 | // 90: } |
| 72 | 1, 0, // 94: case 0x1: { |
| 73 | OPC_Decode, 154, 3, 2, // 96: decode to GETST_2r using decoder 2 |
| 74 | // 96: } |
| 75 | // 96: } // switch Inst[4] |
| 76 | // 96: } else try { |
| 77 | OPC_Decode, 146, 4, 3, // 100: decode to STW_2rus using decoder 3 |
| 78 | // 100: } |
| 79 | // 100: } |
| 80 | 1, 99, // 104: case 0x1: { |
| 81 | OPC_Scope, 59, // 106: try { |
| 82 | OPC_SwitchField, 0, 11, // 108: switch Inst[10:0] { |
| 83 | 236, 15, 4, // 111: case 0x7ec: { |
| 84 | OPC_Decode, 199, 3, 0, // 114: decode to LDSPC_0R using decoder 0 |
| 85 | // 114: } |
| 86 | 237, 15, 4, // 118: case 0x7ed: { |
| 87 | OPC_Decode, 140, 4, 0, // 121: decode to STSPC_0R using decoder 0 |
| 88 | // 121: } |
| 89 | 238, 15, 4, // 125: case 0x7ee: { |
| 90 | OPC_Decode, 200, 3, 0, // 128: decode to LDSSR_0R using decoder 0 |
| 91 | // 128: } |
| 92 | 239, 15, 4, // 132: case 0x7ef: { |
| 93 | OPC_Decode, 141, 4, 0, // 135: decode to STSSR_0R using decoder 0 |
| 94 | // 135: } |
| 95 | 252, 15, 4, // 139: case 0x7fc: { |
| 96 | OPC_Decode, 139, 4, 0, // 142: decode to STSED_0R using decoder 0 |
| 97 | // 142: } |
| 98 | 253, 15, 4, // 146: case 0x7fd: { |
| 99 | OPC_Decode, 138, 4, 0, // 149: decode to STET_0R using decoder 0 |
| 100 | // 149: } |
| 101 | 254, 15, 4, // 153: case 0x7fe: { |
| 102 | OPC_Decode, 144, 3, 0, // 156: decode to GETED_0R using decoder 0 |
| 103 | // 156: } |
| 104 | 255, 15, 0, // 160: case 0x7ff: { |
| 105 | OPC_Decode, 145, 3, 0, // 163: decode to GETET_0R using decoder 0 |
| 106 | // 163: } |
| 107 | // 163: } // switch Inst[10:0] |
| 108 | OPC_Scope, 15, // 167: } else try { |
| 109 | OPC_SwitchField, 4, 7, // 169: switch Inst[10:4] { |
| 110 | 126, 4, // 172: case 0x7e: { |
| 111 | OPC_Decode, 158, 4, 1, // 174: decode to WAITET_1R using decoder 1 |
| 112 | // 174: } |
| 113 | 127, 0, // 178: case 0x7f: { |
| 114 | OPC_Decode, 157, 4, 1, // 180: decode to WAITEF_1R using decoder 1 |
| 115 | // 180: } |
| 116 | // 180: } // switch Inst[10:4] |
| 117 | OPC_Scope, 15, // 184: } else try { |
| 118 | OPC_SwitchField, 4, 1, // 186: switch Inst[4] { |
| 119 | 0, 4, // 189: case 0x0: { |
| 120 | OPC_Decode, 158, 3, 2, // 191: decode to INITDP_2r using decoder 2 |
| 121 | // 191: } |
| 122 | 1, 0, // 195: case 0x1: { |
| 123 | OPC_Decode, 229, 3, 4, // 197: decode to OUTT_2r using decoder 4 |
| 124 | // 197: } |
| 125 | // 197: } // switch Inst[4] |
| 126 | // 197: } else try { |
| 127 | OPC_Decode, 209, 3, 3, // 201: decode to LDW_2rus using decoder 3 |
| 128 | // 201: } |
| 129 | // 201: } |
| 130 | 2, 92, // 205: case 0x2: { |
| 131 | OPC_Scope, 52, // 207: try { |
| 132 | OPC_SwitchField, 0, 11, // 209: switch Inst[10:0] { |
| 133 | 236, 15, 4, // 212: case 0x7ec: { |
| 134 | OPC_Decode, 248, 2, 0, // 215: decode to DENTSP_0R using decoder 0 |
| 135 | // 215: } |
| 136 | 237, 15, 4, // 219: case 0x7ed: { |
| 137 | OPC_Decode, 252, 2, 0, // 222: decode to DRESTSP_0R using decoder 0 |
| 138 | // 222: } |
| 139 | 238, 15, 4, // 226: case 0x7ee: { |
| 140 | OPC_Decode, 146, 3, 0, // 229: decode to GETID_0R using decoder 0 |
| 141 | // 229: } |
| 142 | 239, 15, 4, // 233: case 0x7ef: { |
| 143 | OPC_Decode, 147, 3, 0, // 236: decode to GETKEP_0R using decoder 0 |
| 144 | // 236: } |
| 145 | 252, 15, 4, // 240: case 0x7fc: { |
| 146 | OPC_Decode, 148, 3, 0, // 243: decode to GETKSP_0R using decoder 0 |
| 147 | // 243: } |
| 148 | 253, 15, 4, // 247: case 0x7fd: { |
| 149 | OPC_Decode, 198, 3, 0, // 250: decode to LDSED_0R using decoder 0 |
| 150 | // 250: } |
| 151 | 254, 15, 0, // 254: case 0x7fe: { |
| 152 | OPC_Decode, 196, 3, 0, // 257: decode to LDET_0R using decoder 0 |
| 153 | // 257: } |
| 154 | // 257: } // switch Inst[10:0] |
| 155 | OPC_Scope, 15, // 261: } else try { |
| 156 | OPC_SwitchField, 4, 7, // 263: switch Inst[10:4] { |
| 157 | 126, 4, // 266: case 0x7e: { |
| 158 | OPC_Decode, 141, 3, 1, // 268: decode to FREER_1r using decoder 1 |
| 159 | // 268: } |
| 160 | 127, 0, // 272: case 0x7f: { |
| 161 | OPC_Decode, 217, 3, 1, // 274: decode to MJOIN_1r using decoder 1 |
| 162 | // 274: } |
| 163 | // 274: } // switch Inst[10:4] |
| 164 | OPC_Scope, 15, // 278: } else try { |
| 165 | OPC_SwitchField, 4, 1, // 280: switch Inst[4] { |
| 166 | 0, 4, // 283: case 0x0: { |
| 167 | OPC_Decode, 161, 3, 2, // 285: decode to INITSP_2r using decoder 2 |
| 168 | // 285: } |
| 169 | 1, 0, // 289: case 0x1: { |
| 170 | OPC_Decode, 242, 3, 4, // 291: decode to SETD_2r using decoder 4 |
| 171 | // 291: } |
| 172 | // 291: } // switch Inst[4] |
| 173 | // 291: } else try { |
| 174 | OPC_Decode, 206, 2, 5, // 295: decode to ADD_3r using decoder 5 |
| 175 | // 295: } |
| 176 | // 295: } |
| 177 | 3, 38, // 299: case 0x3: { |
| 178 | OPC_Scope, 15, // 301: try { |
| 179 | OPC_SwitchField, 4, 7, // 303: switch Inst[10:4] { |
| 180 | 126, 4, // 306: case 0x7e: { |
| 181 | OPC_Decode, 156, 4, 1, // 308: decode to TSTART_1R using decoder 1 |
| 182 | // 308: } |
| 183 | 127, 0, // 312: case 0x7f: { |
| 184 | OPC_Decode, 220, 3, 1, // 314: decode to MSYNC_1r using decoder 1 |
| 185 | // 314: } |
| 186 | // 314: } // switch Inst[10:4] |
| 187 | OPC_Scope, 15, // 318: } else try { |
| 188 | OPC_SwitchField, 4, 1, // 320: switch Inst[4] { |
| 189 | 0, 4, // 323: case 0x0: { |
| 190 | OPC_Decode, 157, 3, 2, // 325: decode to INITCP_2r using decoder 2 |
| 191 | // 325: } |
| 192 | 1, 0, // 329: case 0x1: { |
| 193 | OPC_Decode, 154, 4, 6, // 331: decode to TSETMR_2r using decoder 6 |
| 194 | // 331: } |
| 195 | // 331: } // switch Inst[4] |
| 196 | // 331: } else try { |
| 197 | OPC_Decode, 149, 4, 5, // 335: decode to SUB_3r using decoder 5 |
| 198 | // 335: } |
| 199 | // 335: } |
| 200 | 4, 31, // 339: case 0x4: { |
| 201 | OPC_Scope, 15, // 341: try { |
| 202 | OPC_SwitchField, 4, 7, // 343: switch Inst[10:4] { |
| 203 | 126, 4, // 346: case 0x7e: { |
| 204 | OPC_Decode, 217, 2, 1, // 348: decode to BLA_1r using decoder 1 |
| 205 | // 348: } |
| 206 | 127, 0, // 352: case 0x7f: { |
| 207 | OPC_Decode, 211, 2, 1, // 354: decode to BAU_1r using decoder 1 |
| 208 | // 354: } |
| 209 | // 354: } // switch Inst[10:4] |
| 210 | OPC_Scope, 8, // 358: } else try { |
| 211 | OPC_CheckField, 4, 1, 1, // 360: check Inst[4] == 0x1 |
| 212 | OPC_Decode, 130, 3, 2, // 364: decode to EET_2r using decoder 2 |
| 213 | // 364: } else try { |
| 214 | OPC_Decode, 132, 4, 5, // 368: decode to SHL_3r using decoder 5 |
| 215 | // 368: } |
| 216 | // 368: } |
| 217 | 5, 38, // 372: case 0x5: { |
| 218 | OPC_Scope, 15, // 374: try { |
| 219 | OPC_SwitchField, 4, 7, // 376: switch Inst[10:4] { |
| 220 | 126, 4, // 379: case 0x7e: { |
| 221 | OPC_Decode, 234, 2, 1, // 381: decode to BRU_1r using decoder 1 |
| 222 | // 381: } |
| 223 | 127, 0, // 385: case 0x7f: { |
| 224 | OPC_Decode, 250, 3, 1, // 387: decode to SETSP_1r using decoder 1 |
| 225 | // 387: } |
| 226 | // 387: } // switch Inst[10:4] |
| 227 | OPC_Scope, 15, // 391: } else try { |
| 228 | OPC_SwitchField, 4, 1, // 393: switch Inst[4] { |
| 229 | 0, 4, // 396: case 0x0: { |
| 230 | OPC_Decode, 207, 2, 7, // 398: decode to ANDNOT_2r using decoder 7 |
| 231 | // 398: } |
| 232 | 1, 0, // 402: case 0x1: { |
| 233 | OPC_Decode, 129, 3, 2, // 404: decode to EEF_2r using decoder 2 |
| 234 | // 404: } |
| 235 | // 404: } // switch Inst[4] |
| 236 | // 404: } else try { |
| 237 | OPC_Decode, 134, 4, 5, // 408: decode to SHR_3r using decoder 5 |
| 238 | // 408: } |
| 239 | // 408: } |
| 240 | 6, 38, // 412: case 0x6: { |
| 241 | OPC_Scope, 15, // 414: try { |
| 242 | OPC_SwitchField, 4, 7, // 416: switch Inst[10:4] { |
| 243 | 126, 4, // 419: case 0x7e: { |
| 244 | OPC_Decode, 241, 3, 1, // 421: decode to SETDP_1r using decoder 1 |
| 245 | // 421: } |
| 246 | 127, 0, // 425: case 0x7f: { |
| 247 | OPC_Decode, 237, 3, 1, // 427: decode to SETCP_1r using decoder 1 |
| 248 | // 427: } |
| 249 | // 427: } // switch Inst[10:4] |
| 250 | OPC_Scope, 15, // 431: } else try { |
| 251 | OPC_SwitchField, 4, 1, // 433: switch Inst[4] { |
| 252 | 0, 4, // 436: case 0x0: { |
| 253 | OPC_Decode, 129, 4, 7, // 438: decode to SEXT_2r using decoder 7 |
| 254 | // 438: } |
| 255 | 1, 0, // 442: case 0x1: { |
| 256 | OPC_Decode, 130, 4, 8, // 444: decode to SEXT_rus using decoder 8 |
| 257 | // 444: } |
| 258 | // 444: } // switch Inst[4] |
| 259 | // 444: } else try { |
| 260 | OPC_Decode, 136, 3, 5, // 448: decode to EQ_3r using decoder 5 |
| 261 | // 448: } |
| 262 | // 448: } |
| 263 | 7, 38, // 452: case 0x7: { |
| 264 | OPC_Scope, 15, // 454: try { |
| 265 | OPC_SwitchField, 4, 7, // 456: switch Inst[10:4] { |
| 266 | 126, 4, // 459: case 0x7e: { |
| 267 | OPC_Decode, 249, 2, 1, // 461: decode to DGETREG_1r using decoder 1 |
| 268 | // 461: } |
| 269 | 127, 0, // 465: case 0x7f: { |
| 270 | OPC_Decode, 243, 3, 1, // 467: decode to SETEV_1r using decoder 1 |
| 271 | // 467: } |
| 272 | // 467: } // switch Inst[10:4] |
| 273 | OPC_Scope, 15, // 471: } else try { |
| 274 | OPC_SwitchField, 4, 1, // 473: switch Inst[4] { |
| 275 | 0, 4, // 476: case 0x0: { |
| 276 | OPC_Decode, 155, 3, 2, // 478: decode to GETTS_2r using decoder 2 |
| 277 | // 478: } |
| 278 | 1, 0, // 482: case 0x1: { |
| 279 | OPC_Decode, 248, 3, 4, // 484: decode to SETPT_2r using decoder 4 |
| 280 | // 484: } |
| 281 | // 484: } // switch Inst[4] |
| 282 | // 484: } else try { |
| 283 | OPC_Decode, 208, 2, 5, // 488: decode to AND_3r using decoder 5 |
| 284 | // 488: } |
| 285 | // 488: } |
| 286 | 8, 38, // 492: case 0x8: { |
| 287 | OPC_Scope, 15, // 494: try { |
| 288 | OPC_SwitchField, 4, 7, // 496: switch Inst[10:4] { |
| 289 | 126, 4, // 499: case 0x7e: { |
| 290 | OPC_Decode, 166, 3, 1, // 501: decode to KCALL_1r using decoder 1 |
| 291 | // 501: } |
| 292 | 127, 0, // 505: case 0x7f: { |
| 293 | OPC_Decode, 128, 4, 1, // 507: decode to SETV_1r using decoder 1 |
| 294 | // 507: } |
| 295 | // 507: } // switch Inst[10:4] |
| 296 | OPC_Scope, 15, // 511: } else try { |
| 297 | OPC_SwitchField, 4, 1, // 513: switch Inst[4] { |
| 298 | 0, 4, // 516: case 0x0: { |
| 299 | OPC_Decode, 161, 4, 7, // 518: decode to ZEXT_2r using decoder 7 |
| 300 | // 518: } |
| 301 | 1, 0, // 522: case 0x1: { |
| 302 | OPC_Decode, 162, 4, 8, // 524: decode to ZEXT_rus using decoder 8 |
| 303 | // 524: } |
| 304 | // 524: } // switch Inst[4] |
| 305 | // 524: } else try { |
| 306 | OPC_Decode, 224, 3, 5, // 528: decode to OR_3r using decoder 5 |
| 307 | // 528: } |
| 308 | // 528: } |
| 309 | 9, 38, // 532: case 0x9: { |
| 310 | OPC_Scope, 15, // 534: try { |
| 311 | OPC_SwitchField, 4, 7, // 536: switch Inst[10:4] { |
| 312 | 126, 4, // 539: case 0x7e: { |
| 313 | OPC_Decode, 254, 2, 1, // 541: decode to ECALLF_1r using decoder 1 |
| 314 | // 541: } |
| 315 | 127, 0, // 545: case 0x7f: { |
| 316 | OPC_Decode, 255, 2, 1, // 547: decode to ECALLT_1r using decoder 1 |
| 317 | // 547: } |
| 318 | // 547: } // switch Inst[10:4] |
| 319 | OPC_Scope, 15, // 551: } else try { |
| 320 | OPC_SwitchField, 4, 1, // 553: switch Inst[4] { |
| 321 | 0, 4, // 556: case 0x0: { |
| 322 | OPC_Decode, 225, 3, 2, // 558: decode to OUTCT_2r using decoder 2 |
| 323 | // 558: } |
| 324 | 1, 0, // 562: case 0x1: { |
| 325 | OPC_Decode, 226, 3, 9, // 564: decode to OUTCT_rus using decoder 9 |
| 326 | // 564: } |
| 327 | // 564: } // switch Inst[4] |
| 328 | // 564: } else try { |
| 329 | OPC_Decode, 210, 3, 5, // 568: decode to LDW_3r using decoder 5 |
| 330 | // 568: } |
| 331 | // 568: } |
| 332 | 10, 15, // 572: case 0xa: { |
| 333 | OPC_SwitchField, 10, 1, // 574: switch Inst[10] { |
| 334 | 0, 4, // 577: case 0x0: { |
| 335 | OPC_Decode, 143, 4, 10, // 579: decode to STWDP_ru6 using decoder 10 |
| 336 | // 579: } |
| 337 | 1, 0, // 583: case 0x1: { |
| 338 | OPC_Decode, 145, 4, 10, // 585: decode to STWSP_ru6 using decoder 10 |
| 339 | // 585: } |
| 340 | // 585: } // switch Inst[10] |
| 341 | // 585: } |
| 342 | 11, 15, // 589: case 0xb: { |
| 343 | OPC_SwitchField, 10, 1, // 591: switch Inst[10] { |
| 344 | 0, 4, // 594: case 0x0: { |
| 345 | OPC_Decode, 206, 3, 10, // 596: decode to LDWDP_ru6 using decoder 10 |
| 346 | // 596: } |
| 347 | 1, 0, // 600: case 0x1: { |
| 348 | OPC_Decode, 208, 3, 10, // 602: decode to LDWSP_ru6 using decoder 10 |
| 349 | // 602: } |
| 350 | // 602: } // switch Inst[10] |
| 351 | // 602: } |
| 352 | 12, 15, // 606: case 0xc: { |
| 353 | OPC_SwitchField, 10, 1, // 608: switch Inst[10] { |
| 354 | 0, 4, // 611: case 0x0: { |
| 355 | OPC_Decode, 189, 3, 10, // 613: decode to LDAWDP_ru6 using decoder 10 |
| 356 | // 613: } |
| 357 | 1, 0, // 617: case 0x1: { |
| 358 | OPC_Decode, 193, 3, 10, // 619: decode to LDAWSP_ru6 using decoder 10 |
| 359 | // 619: } |
| 360 | // 619: } // switch Inst[10] |
| 361 | // 619: } |
| 362 | 13, 15, // 623: case 0xd: { |
| 363 | OPC_SwitchField, 10, 1, // 625: switch Inst[10] { |
| 364 | 0, 4, // 628: case 0x0: { |
| 365 | OPC_Decode, 195, 3, 10, // 630: decode to LDC_ru6 using decoder 10 |
| 366 | // 630: } |
| 367 | 1, 0, // 634: case 0x1: { |
| 368 | OPC_Decode, 203, 3, 10, // 636: decode to LDWCP_ru6 using decoder 10 |
| 369 | // 636: } |
| 370 | // 636: } // switch Inst[10] |
| 371 | // 636: } |
| 372 | 14, 73, // 640: case 0xe: { |
| 373 | OPC_SwitchField, 10, 1, // 642: switch Inst[10] { |
| 374 | 0, 33, // 645: case 0x0: { |
| 375 | OPC_Scope, 27, // 647: try { |
| 376 | OPC_SwitchField, 6, 4, // 649: switch Inst[9:6] { |
| 377 | 12, 4, // 652: case 0xc: { |
| 378 | OPC_Decode, 233, 2, 11, // 654: decode to BRFU_u6 using decoder 11 |
| 379 | // 654: } |
| 380 | 13, 4, // 658: case 0xd: { |
| 381 | OPC_Decode, 216, 2, 11, // 660: decode to BLAT_u6 using decoder 11 |
| 382 | // 660: } |
| 383 | 14, 4, // 664: case 0xe: { |
| 384 | OPC_Decode, 138, 3, 11, // 666: decode to EXTDP_u6 using decoder 11 |
| 385 | // 666: } |
| 386 | 15, 0, // 670: case 0xf: { |
| 387 | OPC_Decode, 168, 3, 11, // 672: decode to KCALL_u6 using decoder 11 |
| 388 | // 672: } |
| 389 | // 672: } // switch Inst[9:6] |
| 390 | // 672: } else try { |
| 391 | OPC_Decode, 231, 2, 12, // 676: decode to BRFT_ru6 using decoder 12 |
| 392 | // 676: } |
| 393 | // 676: } |
| 394 | 1, 0, // 680: case 0x1: { |
| 395 | OPC_Scope, 27, // 682: try { |
| 396 | OPC_SwitchField, 6, 4, // 684: switch Inst[9:6] { |
| 397 | 12, 4, // 687: case 0xc: { |
| 398 | OPC_Decode, 227, 2, 13, // 689: decode to BRBU_u6 using decoder 13 |
| 399 | // 689: } |
| 400 | 13, 4, // 693: case 0xd: { |
| 401 | OPC_Decode, 134, 3, 11, // 695: decode to ENTSP_u6 using decoder 11 |
| 402 | // 695: } |
| 403 | 14, 4, // 699: case 0xe: { |
| 404 | OPC_Decode, 140, 3, 11, // 701: decode to EXTSP_u6 using decoder 11 |
| 405 | // 701: } |
| 406 | 15, 0, // 705: case 0xf: { |
| 407 | OPC_Decode, 235, 3, 11, // 707: decode to RETSP_u6 using decoder 11 |
| 408 | // 707: } |
| 409 | // 707: } // switch Inst[9:6] |
| 410 | // 707: } else try { |
| 411 | OPC_Decode, 225, 2, 14, // 711: decode to BRBT_ru6 using decoder 14 |
| 412 | // 711: } |
| 413 | // 711: } |
| 414 | // 711: } // switch Inst[10] |
| 415 | // 711: } |
| 416 | 15, 61, // 715: case 0xf: { |
| 417 | OPC_SwitchField, 10, 1, // 717: switch Inst[10] { |
| 418 | 0, 33, // 720: case 0x0: { |
| 419 | OPC_Scope, 27, // 722: try { |
| 420 | OPC_SwitchField, 6, 4, // 724: switch Inst[9:6] { |
| 421 | 12, 4, // 727: case 0xc: { |
| 422 | OPC_Decode, 243, 2, 11, // 729: decode to CLRSR_u6 using decoder 11 |
| 423 | // 729: } |
| 424 | 13, 4, // 733: case 0xd: { |
| 425 | OPC_Decode, 254, 3, 11, // 735: decode to SETSR_u6 using decoder 11 |
| 426 | // 735: } |
| 427 | 14, 4, // 739: case 0xe: { |
| 428 | OPC_Decode, 170, 3, 11, // 741: decode to KENTSP_u6 using decoder 11 |
| 429 | // 741: } |
| 430 | 15, 0, // 745: case 0xf: { |
| 431 | OPC_Decode, 172, 3, 11, // 747: decode to KRESTSP_u6 using decoder 11 |
| 432 | // 747: } |
| 433 | // 747: } // switch Inst[9:6] |
| 434 | // 747: } else try { |
| 435 | OPC_Decode, 229, 2, 12, // 751: decode to BRFF_ru6 using decoder 12 |
| 436 | // 751: } |
| 437 | // 751: } |
| 438 | 1, 0, // 755: case 0x1: { |
| 439 | OPC_Scope, 15, // 757: try { |
| 440 | OPC_SwitchField, 6, 4, // 759: switch Inst[9:6] { |
| 441 | 12, 4, // 762: case 0xc: { |
| 442 | OPC_Decode, 153, 3, 11, // 764: decode to GETSR_u6 using decoder 11 |
| 443 | // 764: } |
| 444 | 13, 0, // 768: case 0xd: { |
| 445 | OPC_Decode, 187, 3, 11, // 770: decode to LDAWCP_u6 using decoder 11 |
| 446 | // 770: } |
| 447 | // 770: } // switch Inst[9:6] |
| 448 | // 770: } else try { |
| 449 | OPC_Decode, 223, 2, 14, // 774: decode to BRBF_ru6 using decoder 14 |
| 450 | // 774: } |
| 451 | // 774: } |
| 452 | // 774: } // switch Inst[10] |
| 453 | // 774: } |
| 454 | 16, 38, // 778: case 0x10: { |
| 455 | OPC_Scope, 15, // 780: try { |
| 456 | OPC_SwitchField, 4, 7, // 782: switch Inst[10:4] { |
| 457 | 126, 4, // 785: case 0x7e: { |
| 458 | OPC_Decode, 239, 2, 1, // 787: decode to CLRPT_1R using decoder 1 |
| 459 | // 787: } |
| 460 | 127, 0, // 791: case 0x7f: { |
| 461 | OPC_Decode, 150, 4, 1, // 793: decode to SYNCR_1r using decoder 1 |
| 462 | // 793: } |
| 463 | // 793: } // switch Inst[10:4] |
| 464 | OPC_Scope, 15, // 797: } else try { |
| 465 | OPC_SwitchField, 4, 1, // 799: switch Inst[4] { |
| 466 | 0, 4, // 802: case 0x0: { |
| 467 | OPC_Decode, 151, 3, 9, // 804: decode to GETR_rus using decoder 9 |
| 468 | // 804: } |
| 469 | 1, 0, // 808: case 0x1: { |
| 470 | OPC_Decode, 156, 3, 2, // 810: decode to INCT_2r using decoder 2 |
| 471 | // 810: } |
| 472 | // 810: } // switch Inst[4] |
| 473 | // 810: } else try { |
| 474 | OPC_Decode, 175, 3, 5, // 814: decode to LD16S_3r using decoder 5 |
| 475 | // 814: } |
| 476 | // 814: } |
| 477 | 17, 21, // 818: case 0x11: { |
| 478 | OPC_Scope, 15, // 820: try { |
| 479 | OPC_SwitchField, 4, 1, // 822: switch Inst[4] { |
| 480 | 0, 4, // 825: case 0x0: { |
| 481 | OPC_Decode, 223, 3, 2, // 827: decode to NOT using decoder 2 |
| 482 | // 827: } |
| 483 | 1, 0, // 831: case 0x1: { |
| 484 | OPC_Decode, 164, 3, 2, // 833: decode to INT_2r using decoder 2 |
| 485 | // 833: } |
| 486 | // 833: } // switch Inst[4] |
| 487 | // 833: } else try { |
| 488 | OPC_Decode, 176, 3, 5, // 837: decode to LD8U_3r using decoder 5 |
| 489 | // 837: } |
| 490 | // 837: } |
| 491 | 18, 21, // 841: case 0x12: { |
| 492 | OPC_Scope, 15, // 843: try { |
| 493 | OPC_SwitchField, 4, 1, // 845: switch Inst[4] { |
| 494 | 0, 4, // 848: case 0x0: { |
| 495 | OPC_Decode, 222, 3, 2, // 850: decode to NEG using decoder 2 |
| 496 | // 850: } |
| 497 | 1, 0, // 854: case 0x1: { |
| 498 | OPC_Decode, 132, 3, 2, // 856: decode to ENDIN_2r using decoder 2 |
| 499 | // 856: } |
| 500 | // 856: } // switch Inst[4] |
| 501 | // 856: } else try { |
| 502 | OPC_Decode, 205, 2, 3, // 860: decode to ADD_2rus using decoder 3 |
| 503 | // 860: } |
| 504 | // 860: } |
| 505 | 19, 4, // 864: case 0x13: { |
| 506 | OPC_Decode, 148, 4, 3, // 866: decode to SUB_2rus using decoder 3 |
| 507 | // 866: } |
| 508 | 20, 21, // 870: case 0x14: { |
| 509 | OPC_Scope, 15, // 872: try { |
| 510 | OPC_SwitchField, 4, 1, // 874: switch Inst[4] { |
| 511 | 0, 4, // 877: case 0x0: { |
| 512 | OPC_Decode, 218, 3, 2, // 879: decode to MKMSK_2r using decoder 2 |
| 513 | // 879: } |
| 514 | 1, 0, // 883: case 0x1: { |
| 515 | OPC_Decode, 219, 3, 15, // 885: decode to MKMSK_rus using decoder 15 |
| 516 | // 885: } |
| 517 | // 885: } // switch Inst[4] |
| 518 | // 885: } else try { |
| 519 | OPC_Decode, 131, 4, 16, // 889: decode to SHL_2rus using decoder 16 |
| 520 | // 889: } |
| 521 | // 889: } |
| 522 | 21, 21, // 893: case 0x15: { |
| 523 | OPC_Scope, 15, // 895: try { |
| 524 | OPC_SwitchField, 4, 1, // 897: switch Inst[4] { |
| 525 | 0, 4, // 900: case 0x0: { |
| 526 | OPC_Decode, 230, 3, 4, // 902: decode to OUT_2r using decoder 4 |
| 527 | // 902: } |
| 528 | 1, 0, // 906: case 0x1: { |
| 529 | OPC_Decode, 228, 3, 7, // 908: decode to OUTSHR_2r using decoder 7 |
| 530 | // 908: } |
| 531 | // 908: } // switch Inst[4] |
| 532 | // 908: } else try { |
| 533 | OPC_Decode, 133, 4, 16, // 912: decode to SHR_2rus using decoder 16 |
| 534 | // 912: } |
| 535 | // 912: } |
| 536 | 22, 21, // 916: case 0x16: { |
| 537 | OPC_Scope, 15, // 918: try { |
| 538 | OPC_SwitchField, 4, 1, // 920: switch Inst[4] { |
| 539 | 0, 4, // 923: case 0x0: { |
| 540 | OPC_Decode, 165, 3, 2, // 925: decode to IN_2r using decoder 2 |
| 541 | // 925: } |
| 542 | 1, 0, // 929: case 0x1: { |
| 543 | OPC_Decode, 163, 3, 7, // 931: decode to INSHR_2r using decoder 7 |
| 544 | // 931: } |
| 545 | // 931: } // switch Inst[4] |
| 546 | // 931: } else try { |
| 547 | OPC_Decode, 135, 3, 3, // 935: decode to EQ_2rus using decoder 3 |
| 548 | // 935: } |
| 549 | // 935: } |
| 550 | 23, 21, // 939: case 0x17: { |
| 551 | OPC_Scope, 15, // 941: try { |
| 552 | OPC_SwitchField, 4, 1, // 943: switch Inst[4] { |
| 553 | 0, 4, // 946: case 0x0: { |
| 554 | OPC_Decode, 231, 3, 2, // 948: decode to PEEK_2r using decoder 2 |
| 555 | // 948: } |
| 556 | 1, 0, // 952: case 0x1: { |
| 557 | OPC_Decode, 151, 4, 2, // 954: decode to TESTCT_2r using decoder 2 |
| 558 | // 954: } |
| 559 | // 954: } // switch Inst[4] |
| 560 | // 954: } else try { |
| 561 | OPC_Decode, 155, 4, 17, // 958: decode to TSETR_3r using decoder 17 |
| 562 | // 958: } |
| 563 | // 958: } |
| 564 | 24, 21, // 962: case 0x18: { |
| 565 | OPC_Scope, 15, // 964: try { |
| 566 | OPC_SwitchField, 4, 1, // 966: switch Inst[4] { |
| 567 | 0, 4, // 969: case 0x0: { |
| 568 | OPC_Decode, 246, 3, 4, // 971: decode to SETPSC_2r using decoder 4 |
| 569 | // 971: } |
| 570 | 1, 0, // 975: case 0x1: { |
| 571 | OPC_Decode, 153, 4, 2, // 977: decode to TESTWCT_2r using decoder 2 |
| 572 | // 977: } |
| 573 | // 977: } // switch Inst[4] |
| 574 | // 977: } else try { |
| 575 | OPC_Decode, 212, 3, 5, // 981: decode to LSS_3r using decoder 5 |
| 576 | // 981: } |
| 577 | // 981: } |
| 578 | 25, 21, // 985: case 0x19: { |
| 579 | OPC_Scope, 15, // 987: try { |
| 580 | OPC_SwitchField, 4, 1, // 989: switch Inst[4] { |
| 581 | 0, 4, // 992: case 0x0: { |
| 582 | OPC_Decode, 236, 2, 2, // 994: decode to CHKCT_2r using decoder 2 |
| 583 | // 994: } |
| 584 | 1, 0, // 998: case 0x1: { |
| 585 | OPC_Decode, 237, 2, 15, // 1000: decode to CHKCT_rus using decoder 15 |
| 586 | // 1000: } |
| 587 | // 1000: } // switch Inst[4] |
| 588 | // 1000: } else try { |
| 589 | OPC_Decode, 214, 3, 5, // 1004: decode to LSU_3r using decoder 5 |
| 590 | // 1004: } |
| 591 | // 1004: } |
| 592 | 26, 15, // 1008: case 0x1a: { |
| 593 | OPC_SwitchField, 10, 1, // 1010: switch Inst[10] { |
| 594 | 0, 4, // 1013: case 0x0: { |
| 595 | OPC_Decode, 221, 2, 18, // 1015: decode to BLRF_u10 using decoder 18 |
| 596 | // 1015: } |
| 597 | 1, 0, // 1019: case 0x1: { |
| 598 | OPC_Decode, 219, 2, 19, // 1021: decode to BLRB_u10 using decoder 19 |
| 599 | // 1021: } |
| 600 | // 1021: } // switch Inst[10] |
| 601 | // 1021: } |
| 602 | 27, 15, // 1025: case 0x1b: { |
| 603 | OPC_SwitchField, 10, 1, // 1027: switch Inst[10] { |
| 604 | 0, 4, // 1030: case 0x0: { |
| 605 | OPC_Decode, 183, 3, 18, // 1032: decode to LDAPF_u10 using decoder 18 |
| 606 | // 1032: } |
| 607 | 1, 0, // 1036: case 0x1: { |
| 608 | OPC_Decode, 180, 3, 19, // 1038: decode to LDAPB_u10 using decoder 19 |
| 609 | // 1038: } |
| 610 | // 1038: } // switch Inst[10] |
| 611 | // 1038: } |
| 612 | 28, 15, // 1042: case 0x1c: { |
| 613 | OPC_SwitchField, 10, 1, // 1044: switch Inst[10] { |
| 614 | 0, 4, // 1047: case 0x0: { |
| 615 | OPC_Decode, 214, 2, 18, // 1049: decode to BLACP_u10 using decoder 18 |
| 616 | // 1049: } |
| 617 | 1, 0, // 1053: case 0x1: { |
| 618 | OPC_Decode, 204, 3, 18, // 1055: decode to LDWCP_u10 using decoder 18 |
| 619 | // 1055: } |
| 620 | // 1055: } // switch Inst[10] |
| 621 | // 1055: } |
| 622 | 29, 0, // 1059: case 0x1d: { |
| 623 | OPC_CheckField, 10, 1, 0, // 1061: check Inst[10] == 0x0 |
| 624 | OPC_Decode, 240, 3, 12, // 1065: decode to SETC_ru6 using decoder 12 |
| 625 | // 1065: } |
| 626 | // 1065: } // switch Inst[15:11] |
| 627 | }; |
| 628 | static const uint8_t DecoderTable32[793] = { |
| 629 | OPC_SwitchField, 27, 5, // 0: switch Inst[31:27] { |
| 630 | 0, 80, // 3: case 0x0: { |
| 631 | OPC_CheckField, 11, 5, 31, // 5: check Inst[15:11] == 0x1f |
| 632 | OPC_Scope, 25, // 9: try { |
| 633 | OPC_SwitchField, 4, 1, // 11: switch Inst[4] { |
| 634 | 0, 9, // 14: case 0x0: { |
| 635 | OPC_CheckField, 16, 11, 236, 15, // 16: check Inst[26:16] == 0x7ec |
| 636 | OPC_Decode, 212, 2, 20, // 21: decode to BITREV_l2r using decoder 20 |
| 637 | // 21: } |
| 638 | 1, 0, // 25: case 0x1: { |
| 639 | OPC_CheckField, 16, 11, 236, 15, // 27: check Inst[26:16] == 0x7ec |
| 640 | OPC_Decode, 235, 2, 20, // 32: decode to BYTEREV_l2r using decoder 20 |
| 641 | // 32: } |
| 642 | // 32: } // switch Inst[4] |
| 643 | OPC_Scope, 9, // 36: } else try { |
| 644 | OPC_CheckField, 16, 11, 236, 15, // 38: check Inst[26:16] == 0x7ec |
| 645 | OPC_Decode, 147, 4, 21, // 43: decode to STW_l3r using decoder 21 |
| 646 | OPC_Scope, 15, // 47: } else try { |
| 647 | OPC_SwitchField, 20, 7, // 49: switch Inst[26:20] { |
| 648 | 126, 4, // 52: case 0x7e: { |
| 649 | OPC_Decode, 245, 2, 22, // 54: decode to CRC8_l4r using decoder 22 |
| 650 | // 54: } |
| 651 | 127, 0, // 58: case 0x7f: { |
| 652 | OPC_Decode, 216, 3, 23, // 60: decode to MACCU_l4r using decoder 23 |
| 653 | // 60: } |
| 654 | // 60: } // switch Inst[26:20] |
| 655 | OPC_Scope, 15, // 64: } else try { |
| 656 | OPC_SwitchField, 20, 1, // 66: switch Inst[20] { |
| 657 | 0, 4, // 69: case 0x0: { |
| 658 | OPC_Decode, 197, 3, 24, // 71: decode to LDIVU_l5r using decoder 24 |
| 659 | // 71: } |
| 660 | 1, 0, // 75: case 0x1: { |
| 661 | OPC_Decode, 174, 3, 24, // 77: decode to LADD_l5r using decoder 24 |
| 662 | // 77: } |
| 663 | // 77: } // switch Inst[20] |
| 664 | // 77: } else try { |
| 665 | OPC_Decode, 211, 3, 25, // 81: decode to LMUL_l6r using decoder 25 |
| 666 | // 81: } |
| 667 | // 81: } |
| 668 | 1, 69, // 85: case 0x1: { |
| 669 | OPC_CheckField, 11, 5, 31, // 87: check Inst[15:11] == 0x1f |
| 670 | OPC_CheckField, 20, 1, 0, // 91: check Inst[20] == 0x0 |
| 671 | OPC_Scope, 31, // 95: try { |
| 672 | OPC_SwitchField, 4, 1, // 97: switch Inst[4] { |
| 673 | 0, 12, // 100: case 0x0: { |
| 674 | OPC_CheckField, 21, 6, 63, // 102: check Inst[26:21] == 0x3f |
| 675 | OPC_CheckField, 16, 4, 12, // 106: check Inst[19:16] == 0xc |
| 676 | OPC_Decode, 244, 2, 20, // 110: decode to CLZ_l2r using decoder 20 |
| 677 | // 110: } |
| 678 | 1, 0, // 114: case 0x1: { |
| 679 | OPC_CheckField, 21, 6, 63, // 116: check Inst[26:21] == 0x3f |
| 680 | OPC_CheckField, 16, 4, 12, // 120: check Inst[19:16] == 0xc |
| 681 | OPC_Decode, 236, 3, 26, // 124: decode to SETCLK_l2r using decoder 26 |
| 682 | // 124: } |
| 683 | // 124: } // switch Inst[4] |
| 684 | OPC_Scope, 12, // 128: } else try { |
| 685 | OPC_CheckField, 16, 4, 12, // 130: check Inst[19:16] == 0xc |
| 686 | OPC_CheckField, 21, 6, 63, // 134: check Inst[26:21] == 0x3f |
| 687 | OPC_Decode, 160, 4, 21, // 138: decode to XOR_l3r using decoder 21 |
| 688 | OPC_Scope, 8, // 142: } else try { |
| 689 | OPC_CheckField, 21, 6, 63, // 144: check Inst[26:21] == 0x3f |
| 690 | OPC_Decode, 215, 3, 23, // 148: decode to MACCS_l4r using decoder 23 |
| 691 | // 148: } else try { |
| 692 | OPC_Decode, 213, 3, 24, // 152: decode to LSUB_l5r using decoder 24 |
| 693 | // 152: } |
| 694 | // 152: } |
| 695 | 2, 27, // 156: case 0x2: { |
| 696 | OPC_CheckField, 11, 16, 159, 251, 3, // 158: check Inst[26:11] == 0xfd9f |
| 697 | OPC_Scope, 15, // 164: try { |
| 698 | OPC_SwitchField, 4, 1, // 166: switch Inst[4] { |
| 699 | 0, 4, // 169: case 0x0: { |
| 700 | OPC_Decode, 159, 3, 20, // 171: decode to INITLR_l2r using decoder 20 |
| 701 | // 171: } |
| 702 | 1, 0, // 175: case 0x1: { |
| 703 | OPC_Decode, 150, 3, 20, // 177: decode to GETPS_l2r using decoder 20 |
| 704 | // 177: } |
| 705 | // 177: } // switch Inst[4] |
| 706 | // 177: } else try { |
| 707 | OPC_Decode, 210, 2, 21, // 181: decode to ASHR_l3r using decoder 21 |
| 708 | // 181: } |
| 709 | // 181: } |
| 710 | 3, 27, // 185: case 0x3: { |
| 711 | OPC_CheckField, 11, 16, 159, 251, 3, // 187: check Inst[26:11] == 0xfd9f |
| 712 | OPC_Scope, 15, // 193: try { |
| 713 | OPC_SwitchField, 4, 1, // 195: switch Inst[4] { |
| 714 | 0, 4, // 198: case 0x0: { |
| 715 | OPC_Decode, 247, 3, 26, // 200: decode to SETPS_l2r using decoder 26 |
| 716 | // 200: } |
| 717 | 1, 0, // 204: case 0x1: { |
| 718 | OPC_Decode, 143, 3, 20, // 206: decode to GETD_l2r using decoder 20 |
| 719 | // 206: } |
| 720 | // 206: } // switch Inst[4] |
| 721 | // 206: } else try { |
| 722 | OPC_Decode, 191, 3, 21, // 210: decode to LDAWF_l3r using decoder 21 |
| 723 | // 210: } |
| 724 | // 210: } |
| 725 | 4, 27, // 214: case 0x4: { |
| 726 | OPC_CheckField, 11, 16, 159, 251, 3, // 216: check Inst[26:11] == 0xfd9f |
| 727 | OPC_Scope, 15, // 222: try { |
| 728 | OPC_SwitchField, 4, 1, // 224: switch Inst[4] { |
| 729 | 0, 4, // 227: case 0x0: { |
| 730 | OPC_Decode, 152, 4, 20, // 229: decode to TESTLCL_l2r using decoder 20 |
| 731 | // 229: } |
| 732 | 1, 0, // 233: case 0x1: { |
| 733 | OPC_Decode, 255, 3, 26, // 235: decode to SETTW_l2r using decoder 26 |
| 734 | // 235: } |
| 735 | // 235: } // switch Inst[4] |
| 736 | // 235: } else try { |
| 737 | OPC_Decode, 185, 3, 21, // 239: decode to LDAWB_l3r using decoder 21 |
| 738 | // 239: } |
| 739 | // 239: } |
| 740 | 5, 27, // 243: case 0x5: { |
| 741 | OPC_CheckField, 11, 16, 159, 251, 3, // 245: check Inst[26:11] == 0xfd9f |
| 742 | OPC_Scope, 15, // 251: try { |
| 743 | OPC_SwitchField, 4, 1, // 253: switch Inst[4] { |
| 744 | 0, 4, // 256: case 0x0: { |
| 745 | OPC_Decode, 249, 3, 26, // 258: decode to SETRDY_l2r using decoder 26 |
| 746 | // 258: } |
| 747 | 1, 0, // 262: case 0x1: { |
| 748 | OPC_Decode, 238, 3, 20, // 264: decode to SETC_l2r using decoder 20 |
| 749 | // 264: } |
| 750 | // 264: } // switch Inst[4] |
| 751 | // 264: } else try { |
| 752 | OPC_Decode, 178, 3, 21, // 268: decode to LDA16F_l3r using decoder 21 |
| 753 | // 268: } |
| 754 | // 268: } |
| 755 | 6, 27, // 272: case 0x6: { |
| 756 | OPC_CheckField, 11, 16, 159, 251, 3, // 274: check Inst[26:11] == 0xfd9f |
| 757 | OPC_Scope, 15, // 280: try { |
| 758 | OPC_SwitchField, 4, 1, // 282: switch Inst[4] { |
| 759 | 0, 4, // 285: case 0x0: { |
| 760 | OPC_Decode, 245, 3, 26, // 287: decode to SETN_l2r using decoder 26 |
| 761 | // 287: } |
| 762 | 1, 0, // 291: case 0x1: { |
| 763 | OPC_Decode, 149, 3, 20, // 293: decode to GETN_l2r using decoder 20 |
| 764 | // 293: } |
| 765 | // 293: } // switch Inst[4] |
| 766 | // 293: } else try { |
| 767 | OPC_Decode, 177, 3, 21, // 297: decode to LDA16B_l3r using decoder 21 |
| 768 | // 297: } |
| 769 | // 297: } |
| 770 | 7, 10, // 301: case 0x7: { |
| 771 | OPC_CheckField, 11, 16, 159, 251, 3, // 303: check Inst[26:11] == 0xfd9f |
| 772 | OPC_Decode, 221, 3, 21, // 309: decode to MUL_l3r using decoder 21 |
| 773 | // 309: } |
| 774 | 8, 10, // 313: case 0x8: { |
| 775 | OPC_CheckField, 11, 16, 159, 251, 3, // 315: check Inst[26:11] == 0xfd9f |
| 776 | OPC_Decode, 250, 2, 21, // 321: decode to DIVS_l3r using decoder 21 |
| 777 | // 321: } |
| 778 | 9, 10, // 325: case 0x9: { |
| 779 | OPC_CheckField, 11, 16, 159, 251, 3, // 327: check Inst[26:11] == 0xfd9f |
| 780 | OPC_Decode, 251, 2, 21, // 333: decode to DIVU_l3r using decoder 21 |
| 781 | // 333: } |
| 782 | 10, 23, // 337: case 0xa: { |
| 783 | OPC_SwitchField, 26, 1, // 339: switch Inst[26] { |
| 784 | 0, 8, // 342: case 0x0: { |
| 785 | OPC_CheckField, 10, 6, 60, // 344: check Inst[15:10] == 0x3c |
| 786 | OPC_Decode, 142, 4, 27, // 348: decode to STWDP_lru6 using decoder 27 |
| 787 | // 348: } |
| 788 | 1, 0, // 352: case 0x1: { |
| 789 | OPC_CheckField, 10, 6, 60, // 354: check Inst[15:10] == 0x3c |
| 790 | OPC_Decode, 144, 4, 27, // 358: decode to STWSP_lru6 using decoder 27 |
| 791 | // 358: } |
| 792 | // 358: } // switch Inst[26] |
| 793 | // 358: } |
| 794 | 11, 23, // 362: case 0xb: { |
| 795 | OPC_SwitchField, 26, 1, // 364: switch Inst[26] { |
| 796 | 0, 8, // 367: case 0x0: { |
| 797 | OPC_CheckField, 10, 6, 60, // 369: check Inst[15:10] == 0x3c |
| 798 | OPC_Decode, 205, 3, 27, // 373: decode to LDWDP_lru6 using decoder 27 |
| 799 | // 373: } |
| 800 | 1, 0, // 377: case 0x1: { |
| 801 | OPC_CheckField, 10, 6, 60, // 379: check Inst[15:10] == 0x3c |
| 802 | OPC_Decode, 207, 3, 27, // 383: decode to LDWSP_lru6 using decoder 27 |
| 803 | // 383: } |
| 804 | // 383: } // switch Inst[26] |
| 805 | // 383: } |
| 806 | 12, 23, // 387: case 0xc: { |
| 807 | OPC_SwitchField, 26, 1, // 389: switch Inst[26] { |
| 808 | 0, 8, // 392: case 0x0: { |
| 809 | OPC_CheckField, 10, 6, 60, // 394: check Inst[15:10] == 0x3c |
| 810 | OPC_Decode, 188, 3, 27, // 398: decode to LDAWDP_lru6 using decoder 27 |
| 811 | // 398: } |
| 812 | 1, 0, // 402: case 0x1: { |
| 813 | OPC_CheckField, 10, 6, 60, // 404: check Inst[15:10] == 0x3c |
| 814 | OPC_Decode, 192, 3, 27, // 408: decode to LDAWSP_lru6 using decoder 27 |
| 815 | // 408: } |
| 816 | // 408: } // switch Inst[26] |
| 817 | // 408: } |
| 818 | 13, 23, // 412: case 0xd: { |
| 819 | OPC_SwitchField, 26, 1, // 414: switch Inst[26] { |
| 820 | 0, 8, // 417: case 0x0: { |
| 821 | OPC_CheckField, 10, 6, 60, // 419: check Inst[15:10] == 0x3c |
| 822 | OPC_Decode, 194, 3, 27, // 423: decode to LDC_lru6 using decoder 27 |
| 823 | // 423: } |
| 824 | 1, 0, // 427: case 0x1: { |
| 825 | OPC_CheckField, 10, 6, 60, // 429: check Inst[15:10] == 0x3c |
| 826 | OPC_Decode, 201, 3, 27, // 433: decode to LDWCP_lru6 using decoder 27 |
| 827 | // 433: } |
| 828 | // 433: } // switch Inst[26] |
| 829 | // 433: } |
| 830 | 14, 81, // 437: case 0xe: { |
| 831 | OPC_SwitchField, 26, 1, // 439: switch Inst[26] { |
| 832 | 0, 37, // 442: case 0x0: { |
| 833 | OPC_CheckField, 10, 6, 60, // 444: check Inst[15:10] == 0x3c |
| 834 | OPC_Scope, 27, // 448: try { |
| 835 | OPC_SwitchField, 22, 4, // 450: switch Inst[25:22] { |
| 836 | 12, 4, // 453: case 0xc: { |
| 837 | OPC_Decode, 232, 2, 28, // 455: decode to BRFU_lu6 using decoder 28 |
| 838 | // 455: } |
| 839 | 13, 4, // 459: case 0xd: { |
| 840 | OPC_Decode, 215, 2, 28, // 461: decode to BLAT_lu6 using decoder 28 |
| 841 | // 461: } |
| 842 | 14, 4, // 465: case 0xe: { |
| 843 | OPC_Decode, 137, 3, 28, // 467: decode to EXTDP_lu6 using decoder 28 |
| 844 | // 467: } |
| 845 | 15, 0, // 471: case 0xf: { |
| 846 | OPC_Decode, 167, 3, 28, // 473: decode to KCALL_lu6 using decoder 28 |
| 847 | // 473: } |
| 848 | // 473: } // switch Inst[25:22] |
| 849 | // 473: } else try { |
| 850 | OPC_Decode, 230, 2, 29, // 477: decode to BRFT_lru6 using decoder 29 |
| 851 | // 477: } |
| 852 | // 477: } |
| 853 | 1, 0, // 481: case 0x1: { |
| 854 | OPC_CheckField, 10, 6, 60, // 483: check Inst[15:10] == 0x3c |
| 855 | OPC_Scope, 27, // 487: try { |
| 856 | OPC_SwitchField, 22, 4, // 489: switch Inst[25:22] { |
| 857 | 12, 4, // 492: case 0xc: { |
| 858 | OPC_Decode, 226, 2, 30, // 494: decode to BRBU_lu6 using decoder 30 |
| 859 | // 494: } |
| 860 | 13, 4, // 498: case 0xd: { |
| 861 | OPC_Decode, 133, 3, 28, // 500: decode to ENTSP_lu6 using decoder 28 |
| 862 | // 500: } |
| 863 | 14, 4, // 504: case 0xe: { |
| 864 | OPC_Decode, 139, 3, 28, // 506: decode to EXTSP_lu6 using decoder 28 |
| 865 | // 506: } |
| 866 | 15, 0, // 510: case 0xf: { |
| 867 | OPC_Decode, 234, 3, 28, // 512: decode to RETSP_lu6 using decoder 28 |
| 868 | // 512: } |
| 869 | // 512: } // switch Inst[25:22] |
| 870 | // 512: } else try { |
| 871 | OPC_Decode, 224, 2, 31, // 516: decode to BRBT_lru6 using decoder 31 |
| 872 | // 516: } |
| 873 | // 516: } |
| 874 | // 516: } // switch Inst[26] |
| 875 | // 516: } |
| 876 | 15, 69, // 520: case 0xf: { |
| 877 | OPC_SwitchField, 26, 1, // 522: switch Inst[26] { |
| 878 | 0, 37, // 525: case 0x0: { |
| 879 | OPC_CheckField, 10, 6, 60, // 527: check Inst[15:10] == 0x3c |
| 880 | OPC_Scope, 27, // 531: try { |
| 881 | OPC_SwitchField, 22, 4, // 533: switch Inst[25:22] { |
| 882 | 12, 4, // 536: case 0xc: { |
| 883 | OPC_Decode, 242, 2, 28, // 538: decode to CLRSR_lu6 using decoder 28 |
| 884 | // 538: } |
| 885 | 13, 4, // 542: case 0xd: { |
| 886 | OPC_Decode, 253, 3, 28, // 544: decode to SETSR_lu6 using decoder 28 |
| 887 | // 544: } |
| 888 | 14, 4, // 548: case 0xe: { |
| 889 | OPC_Decode, 169, 3, 28, // 550: decode to KENTSP_lu6 using decoder 28 |
| 890 | // 550: } |
| 891 | 15, 0, // 554: case 0xf: { |
| 892 | OPC_Decode, 171, 3, 28, // 556: decode to KRESTSP_lu6 using decoder 28 |
| 893 | // 556: } |
| 894 | // 556: } // switch Inst[25:22] |
| 895 | // 556: } else try { |
| 896 | OPC_Decode, 228, 2, 29, // 560: decode to BRFF_lru6 using decoder 29 |
| 897 | // 560: } |
| 898 | // 560: } |
| 899 | 1, 0, // 564: case 0x1: { |
| 900 | OPC_CheckField, 10, 6, 60, // 566: check Inst[15:10] == 0x3c |
| 901 | OPC_Scope, 15, // 570: try { |
| 902 | OPC_SwitchField, 22, 4, // 572: switch Inst[25:22] { |
| 903 | 12, 4, // 575: case 0xc: { |
| 904 | OPC_Decode, 152, 3, 28, // 577: decode to GETSR_lu6 using decoder 28 |
| 905 | // 577: } |
| 906 | 13, 0, // 581: case 0xd: { |
| 907 | OPC_Decode, 186, 3, 28, // 583: decode to LDAWCP_lu6 using decoder 28 |
| 908 | // 583: } |
| 909 | // 583: } // switch Inst[25:22] |
| 910 | // 583: } else try { |
| 911 | OPC_Decode, 222, 2, 31, // 587: decode to BRBF_lru6 using decoder 31 |
| 912 | // 587: } |
| 913 | // 587: } |
| 914 | // 587: } // switch Inst[26] |
| 915 | // 587: } |
| 916 | 16, 10, // 591: case 0x10: { |
| 917 | OPC_CheckField, 11, 16, 159, 251, 3, // 593: check Inst[26:11] == 0xfd9f |
| 918 | OPC_Decode, 136, 4, 21, // 599: decode to ST16_l3r using decoder 21 |
| 919 | // 599: } |
| 920 | 17, 10, // 603: case 0x11: { |
| 921 | OPC_CheckField, 11, 16, 159, 251, 3, // 605: check Inst[26:11] == 0xfd9f |
| 922 | OPC_Decode, 137, 4, 21, // 611: decode to ST8_l3r using decoder 21 |
| 923 | // 611: } |
| 924 | 18, 27, // 615: case 0x12: { |
| 925 | OPC_SwitchField, 11, 16, // 617: switch Inst[26:11] { |
| 926 | 159, 251, 3, 4, // 620: case 0xfd9f: { |
| 927 | OPC_Decode, 209, 2, 32, // 624: decode to ASHR_l2rus using decoder 32 |
| 928 | // 624: } |
| 929 | 191, 251, 3, 4, // 628: case 0xfdbf: { |
| 930 | OPC_Decode, 227, 3, 32, // 632: decode to OUTPW_l2rus using decoder 32 |
| 931 | // 632: } |
| 932 | 223, 251, 3, 0, // 636: case 0xfddf: { |
| 933 | OPC_Decode, 162, 3, 32, // 640: decode to INPW_l2rus using decoder 32 |
| 934 | // 640: } |
| 935 | // 640: } // switch Inst[26:11] |
| 936 | // 640: } |
| 937 | 19, 10, // 644: case 0x13: { |
| 938 | OPC_CheckField, 11, 16, 159, 251, 3, // 646: check Inst[26:11] == 0xfd9f |
| 939 | OPC_Decode, 190, 3, 33, // 652: decode to LDAWF_l2rus using decoder 33 |
| 940 | // 652: } |
| 941 | 20, 10, // 656: case 0x14: { |
| 942 | OPC_CheckField, 11, 16, 159, 251, 3, // 658: check Inst[26:11] == 0xfd9f |
| 943 | OPC_Decode, 184, 3, 33, // 664: decode to LDAWB_l2rus using decoder 33 |
| 944 | // 664: } |
| 945 | 21, 10, // 668: case 0x15: { |
| 946 | OPC_CheckField, 11, 16, 159, 251, 3, // 670: check Inst[26:11] == 0xfd9f |
| 947 | OPC_Decode, 246, 2, 34, // 676: decode to CRC_l3r using decoder 34 |
| 948 | // 676: } |
| 949 | 24, 10, // 680: case 0x18: { |
| 950 | OPC_CheckField, 11, 16, 159, 251, 3, // 682: check Inst[26:11] == 0xfd9f |
| 951 | OPC_Decode, 232, 3, 21, // 688: decode to REMS_l3r using decoder 21 |
| 952 | // 688: } |
| 953 | 25, 10, // 692: case 0x19: { |
| 954 | OPC_CheckField, 11, 16, 159, 251, 3, // 694: check Inst[26:11] == 0xfd9f |
| 955 | OPC_Decode, 233, 3, 21, // 700: decode to REMU_l3r using decoder 21 |
| 956 | // 700: } |
| 957 | 26, 23, // 704: case 0x1a: { |
| 958 | OPC_SwitchField, 26, 1, // 706: switch Inst[26] { |
| 959 | 0, 8, // 709: case 0x0: { |
| 960 | OPC_CheckField, 10, 6, 60, // 711: check Inst[15:10] == 0x3c |
| 961 | OPC_Decode, 220, 2, 35, // 715: decode to BLRF_lu10 using decoder 35 |
| 962 | // 715: } |
| 963 | 1, 0, // 719: case 0x1: { |
| 964 | OPC_CheckField, 10, 6, 60, // 721: check Inst[15:10] == 0x3c |
| 965 | OPC_Decode, 218, 2, 36, // 725: decode to BLRB_lu10 using decoder 36 |
| 966 | // 725: } |
| 967 | // 725: } // switch Inst[26] |
| 968 | // 725: } |
| 969 | 27, 23, // 729: case 0x1b: { |
| 970 | OPC_SwitchField, 26, 1, // 731: switch Inst[26] { |
| 971 | 0, 8, // 734: case 0x0: { |
| 972 | OPC_CheckField, 10, 6, 60, // 736: check Inst[15:10] == 0x3c |
| 973 | OPC_Decode, 181, 3, 35, // 740: decode to LDAPF_lu10 using decoder 35 |
| 974 | // 740: } |
| 975 | 1, 0, // 744: case 0x1: { |
| 976 | OPC_CheckField, 10, 6, 60, // 746: check Inst[15:10] == 0x3c |
| 977 | OPC_Decode, 179, 3, 36, // 750: decode to LDAPB_lu10 using decoder 36 |
| 978 | // 750: } |
| 979 | // 750: } // switch Inst[26] |
| 980 | // 750: } |
| 981 | 28, 23, // 754: case 0x1c: { |
| 982 | OPC_SwitchField, 26, 1, // 756: switch Inst[26] { |
| 983 | 0, 8, // 759: case 0x0: { |
| 984 | OPC_CheckField, 10, 6, 60, // 761: check Inst[15:10] == 0x3c |
| 985 | OPC_Decode, 213, 2, 35, // 765: decode to BLACP_lu10 using decoder 35 |
| 986 | // 765: } |
| 987 | 1, 0, // 769: case 0x1: { |
| 988 | OPC_CheckField, 10, 6, 60, // 771: check Inst[15:10] == 0x3c |
| 989 | OPC_Decode, 202, 3, 35, // 775: decode to LDWCP_lu10 using decoder 35 |
| 990 | // 775: } |
| 991 | // 775: } // switch Inst[26] |
| 992 | // 775: } |
| 993 | 29, 0, // 779: case 0x1d: { |
| 994 | OPC_CheckField, 26, 1, 0, // 781: check Inst[26] == 0x0 |
| 995 | OPC_CheckField, 10, 6, 60, // 785: check Inst[15:10] == 0x3c |
| 996 | OPC_Decode, 239, 3, 29, // 789: decode to SETC_lru6 using decoder 29 |
| 997 | // 789: } |
| 998 | // 789: } // switch Inst[31:27] |
| 999 | }; |
| 1000 | // Handling 37 cases. |
| 1001 | template <typename InsnType> |
| 1002 | static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) { |
| 1003 | DecodeComplete = true; |
| 1004 | using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>; |
| 1005 | TmpType tmp; |
| 1006 | switch (Idx) { |
| 1007 | default: llvm_unreachable("Invalid decoder index!" ); |
| 1008 | case 0: |
| 1009 | return S; |
| 1010 | case 1: |
| 1011 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1012 | if (!Check(S, DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1013 | return S; |
| 1014 | case 2: |
| 1015 | if (!Check(S, Decode2RInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1016 | return S; |
| 1017 | case 3: |
| 1018 | if (!Check(S, Decode2RUSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1019 | return S; |
| 1020 | case 4: |
| 1021 | if (!Check(S, DecodeR2RInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1022 | return S; |
| 1023 | case 5: |
| 1024 | if (!Check(S, Decode3RInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1025 | return S; |
| 1026 | case 6: |
| 1027 | if (!Check(S, Decode2RImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1028 | return S; |
| 1029 | case 7: |
| 1030 | if (!Check(S, Decode2RSrcDstInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1031 | return S; |
| 1032 | case 8: |
| 1033 | if (!Check(S, DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1034 | return S; |
| 1035 | case 9: |
| 1036 | if (!Check(S, DecodeRUSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1037 | return S; |
| 1038 | case 10: |
| 1039 | tmp = fieldFromInstruction(insn, 6, 4); |
| 1040 | if (!Check(S, DecodeRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1041 | tmp = fieldFromInstruction(insn, 0, 6); |
| 1042 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1043 | return S; |
| 1044 | case 11: |
| 1045 | tmp = fieldFromInstruction(insn, 0, 6); |
| 1046 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1047 | return S; |
| 1048 | case 12: |
| 1049 | tmp = fieldFromInstruction(insn, 6, 4); |
| 1050 | if (!Check(S, DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1051 | tmp = fieldFromInstruction(insn, 0, 6); |
| 1052 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1053 | return S; |
| 1054 | case 13: |
| 1055 | tmp = fieldFromInstruction(insn, 0, 6); |
| 1056 | if (!Check(S, DecodeNegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1057 | return S; |
| 1058 | case 14: |
| 1059 | tmp = fieldFromInstruction(insn, 6, 4); |
| 1060 | if (!Check(S, DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1061 | tmp = fieldFromInstruction(insn, 0, 6); |
| 1062 | if (!Check(S, DecodeNegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1063 | return S; |
| 1064 | case 15: |
| 1065 | if (!Check(S, DecodeRUSBitpInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1066 | return S; |
| 1067 | case 16: |
| 1068 | if (!Check(S, Decode2RUSBitpInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1069 | return S; |
| 1070 | case 17: |
| 1071 | if (!Check(S, Decode3RImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1072 | return S; |
| 1073 | case 18: |
| 1074 | tmp = fieldFromInstruction(insn, 0, 10); |
| 1075 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1076 | return S; |
| 1077 | case 19: |
| 1078 | tmp = fieldFromInstruction(insn, 0, 10); |
| 1079 | if (!Check(S, DecodeNegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1080 | return S; |
| 1081 | case 20: |
| 1082 | if (!Check(S, DecodeL2RInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1083 | return S; |
| 1084 | case 21: |
| 1085 | if (!Check(S, DecodeL3RInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1086 | return S; |
| 1087 | case 22: |
| 1088 | if (!Check(S, DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1089 | return S; |
| 1090 | case 23: |
| 1091 | if (!Check(S, DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1092 | return S; |
| 1093 | case 24: |
| 1094 | if (!Check(S, DecodeL5RInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1095 | return S; |
| 1096 | case 25: |
| 1097 | if (!Check(S, DecodeL6RInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1098 | return S; |
| 1099 | case 26: |
| 1100 | if (!Check(S, DecodeLR2RInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1101 | return S; |
| 1102 | case 27: |
| 1103 | tmp = fieldFromInstruction(insn, 22, 4); |
| 1104 | if (!Check(S, DecodeRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1105 | tmp = 0x0; |
| 1106 | tmp |= fieldFromInstruction(insn, 0, 10) << 6; |
| 1107 | tmp |= fieldFromInstruction(insn, 16, 6); |
| 1108 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1109 | return S; |
| 1110 | case 28: |
| 1111 | tmp = 0x0; |
| 1112 | tmp |= fieldFromInstruction(insn, 0, 10) << 6; |
| 1113 | tmp |= fieldFromInstruction(insn, 16, 6); |
| 1114 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1115 | return S; |
| 1116 | case 29: |
| 1117 | tmp = fieldFromInstruction(insn, 22, 4); |
| 1118 | if (!Check(S, DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1119 | tmp = 0x0; |
| 1120 | tmp |= fieldFromInstruction(insn, 0, 10) << 6; |
| 1121 | tmp |= fieldFromInstruction(insn, 16, 6); |
| 1122 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1123 | return S; |
| 1124 | case 30: |
| 1125 | tmp = 0x0; |
| 1126 | tmp |= fieldFromInstruction(insn, 0, 10) << 6; |
| 1127 | tmp |= fieldFromInstruction(insn, 16, 6); |
| 1128 | if (!Check(S, DecodeNegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1129 | return S; |
| 1130 | case 31: |
| 1131 | tmp = fieldFromInstruction(insn, 22, 4); |
| 1132 | if (!Check(S, DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1133 | tmp = 0x0; |
| 1134 | tmp |= fieldFromInstruction(insn, 0, 10) << 6; |
| 1135 | tmp |= fieldFromInstruction(insn, 16, 6); |
| 1136 | if (!Check(S, DecodeNegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1137 | return S; |
| 1138 | case 32: |
| 1139 | if (!Check(S, DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1140 | return S; |
| 1141 | case 33: |
| 1142 | if (!Check(S, DecodeL2RUSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1143 | return S; |
| 1144 | case 34: |
| 1145 | if (!Check(S, DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1146 | return S; |
| 1147 | case 35: |
| 1148 | tmp = 0x0; |
| 1149 | tmp |= fieldFromInstruction(insn, 0, 10) << 10; |
| 1150 | tmp |= fieldFromInstruction(insn, 16, 10); |
| 1151 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1152 | return S; |
| 1153 | case 36: |
| 1154 | tmp = 0x0; |
| 1155 | tmp |= fieldFromInstruction(insn, 0, 10) << 10; |
| 1156 | tmp |= fieldFromInstruction(insn, 16, 10); |
| 1157 | if (!Check(S, DecodeNegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1158 | return S; |
| 1159 | } |
| 1160 | } |
| 1161 | |
| 1162 | template <typename InsnType> |
| 1163 | static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, |
| 1164 | InsnType insn, uint64_t Address, |
| 1165 | const MCDisassembler *DisAsm, |
| 1166 | const MCSubtargetInfo &STI) { |
| 1167 | const uint8_t *Ptr = DecodeTable; |
| 1168 | |
| 1169 | SmallVector<const uint8_t *, 8> ScopeStack; |
| 1170 | DecodeStatus S = MCDisassembler::Success; |
| 1171 | while (true) { |
| 1172 | ptrdiff_t Loc = Ptr - DecodeTable; |
| 1173 | const uint8_t DecoderOp = *Ptr++; |
| 1174 | switch (DecoderOp) { |
| 1175 | default: |
| 1176 | errs() << Loc << ": Unexpected decode table opcode: " |
| 1177 | << (int)DecoderOp << '\n'; |
| 1178 | return MCDisassembler::Fail; |
| 1179 | case OPC_Scope: { |
| 1180 | unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1181 | const uint8_t *SkipTo = Ptr + NumToSkip; |
| 1182 | ScopeStack.push_back(Elt: SkipTo); |
| 1183 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable |
| 1184 | << ")\n" ); |
| 1185 | continue; |
| 1186 | } |
| 1187 | case OPC_SwitchField: { |
| 1188 | // Decode the start value. |
| 1189 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1190 | unsigned Len = *Ptr++; |
| 1191 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 1192 | uint64_t CaseValue; |
| 1193 | unsigned CaseSize; |
| 1194 | while (true) { |
| 1195 | CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1196 | CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1197 | if (FieldValue == CaseValue || !CaseSize) |
| 1198 | break; |
| 1199 | Ptr += CaseSize; |
| 1200 | } |
| 1201 | if (FieldValue == CaseValue) { |
| 1202 | LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len |
| 1203 | << "): " << FieldValue << '\n'); |
| 1204 | continue; |
| 1205 | } |
| 1206 | break; |
| 1207 | } |
| 1208 | case OPC_CheckField: { |
| 1209 | // Decode the start value. |
| 1210 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1211 | unsigned Len = *Ptr; |
| 1212 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 1213 | // Decode the field value. |
| 1214 | unsigned PtrLen = 0; |
| 1215 | uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen); |
| 1216 | Ptr += PtrLen; |
| 1217 | bool Failed = ExpectedValue != FieldValue; |
| 1218 | |
| 1219 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len |
| 1220 | << ", " << ExpectedValue << "): FieldValue = " |
| 1221 | << FieldValue << ", ExpectedValue = " << ExpectedValue |
| 1222 | << ": " << (Failed ? "FAIL, " : "PASS\n" );); |
| 1223 | if (!Failed) |
| 1224 | continue; |
| 1225 | break; |
| 1226 | } |
| 1227 | case OPC_Decode: { |
| 1228 | // Decode the Opcode value. |
| 1229 | unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1230 | unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1231 | |
| 1232 | MI.clear(); |
| 1233 | MI.setOpcode(Opc); |
| 1234 | bool DecodeComplete; |
| 1235 | S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm, |
| 1236 | DecodeComplete); |
| 1237 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc |
| 1238 | << ", using decoder " << DecodeIdx << ": " |
| 1239 | << (S ? "PASS, " : "FAIL, " )); |
| 1240 | |
| 1241 | if (DecodeComplete) { |
| 1242 | LLVM_DEBUG(dbgs() << "decoding complete\n" ); |
| 1243 | return S; |
| 1244 | } |
| 1245 | assert(S == MCDisassembler::Fail); |
| 1246 | // Reset decode status. This also drops a SoftFail status that could be |
| 1247 | // set before the decode attempt. |
| 1248 | S = MCDisassembler::Success; |
| 1249 | break; |
| 1250 | } |
| 1251 | } |
| 1252 | if (ScopeStack.empty()) { |
| 1253 | LLVM_DEBUG(dbgs() << "returning Fail\n" ); |
| 1254 | return MCDisassembler::Fail; |
| 1255 | } |
| 1256 | Ptr = ScopeStack.pop_back_val(); |
| 1257 | LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n'); |
| 1258 | } |
| 1259 | llvm_unreachable("bogosity detected in disassembler state machine!" ); |
| 1260 | } |
| 1261 | |
| 1262 | |
| 1263 | } // namespace |
| 1264 | |