1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::XCore {
13
14 enum {
15 PHI = 0, // Target.td:1200
16 INLINEASM = 1, // Target.td:1206
17 INLINEASM_BR = 2, // Target.td:1212
18 CFI_INSTRUCTION = 3, // Target.td:1221
19 EH_LABEL = 4, // Target.td:1230
20 GC_LABEL = 5, // Target.td:1239
21 ANNOTATION_LABEL = 6, // Target.td:1248
22 KILL = 7, // Target.td:1256
23 EXTRACT_SUBREG = 8, // Target.td:1263
24 INSERT_SUBREG = 9, // Target.td:1269
25 IMPLICIT_DEF = 10, // Target.td:1276
26 INIT_UNDEF = 11, // Target.td:1285
27 SUBREG_TO_REG = 12, // Target.td:1292
28 COPY_TO_REGCLASS = 13, // Target.td:1298
29 DBG_VALUE = 14, // Target.td:1305
30 DBG_VALUE_LIST = 15, // Target.td:1312
31 DBG_INSTR_REF = 16, // Target.td:1319
32 DBG_PHI = 17, // Target.td:1326
33 DBG_LABEL = 18, // Target.td:1333
34 REG_SEQUENCE = 19, // Target.td:1340
35 COPY = 20, // Target.td:1347
36 COPY_LANEMASK = 21, // Target.td:1355
37 BUNDLE = 22, // Target.td:1362
38 LIFETIME_START = 23, // Target.td:1368
39 LIFETIME_END = 24, // Target.td:1375
40 PSEUDO_PROBE = 25, // Target.td:1382
41 ARITH_FENCE = 26, // Target.td:1389
42 STACKMAP = 27, // Target.td:1398
43 FENTRY_CALL = 28, // Target.td:1533
44 PATCHPOINT = 29, // Target.td:1406
45 LOAD_STACK_GUARD = 30, // Target.td:1424
46 PREALLOCATED_SETUP = 31, // Target.td:1432
47 PREALLOCATED_ARG = 32, // Target.td:1438
48 STATEPOINT = 33, // Target.td:1415
49 LOCAL_ESCAPE = 34, // Target.td:1444
50 FAULTING_OP = 35, // Target.td:1453
51 PATCHABLE_OP = 36, // Target.td:1473
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481
53 PATCHABLE_RET = 38, // Target.td:1488
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1505
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1513
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1543
59 FAKE_USE = 44, // Target.td:1463
60 MEMBARRIER = 45, // Target.td:1549
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557
62 RELOC_NONE = 47, // Target.td:1565
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1576
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1580
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1584
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 ADJCALLSTACKDOWN = 323, // XCoreInstrInfo.td:356
339 ADJCALLSTACKUP = 324, // XCoreInstrInfo.td:359
340 BR_JT = 325, // XCoreInstrInfo.td:991
341 BR_JT32 = 326, // XCoreInstrInfo.td:996
342 EH_RETURN = 327, // XCoreInstrInfo.td:370
343 FRAME_TO_ARGS_OFFSET = 328, // XCoreInstrInfo.td:365
344 LDAWFI = 329, // XCoreInstrInfo.td:378
345 LDWFI = 330, // XCoreInstrInfo.td:374
346 SELECT_CC = 331, // XCoreInstrInfo.td:389
347 STWFI = 332, // XCoreInstrInfo.td:382
348 ADD_2rus = 333, // XCoreInstrInfo.td:247
349 ADD_3r = 334, // XCoreInstrInfo.td:244
350 ANDNOT_2r = 335, // XCoreInstrInfo.td:797
351 AND_3r = 336, // XCoreInstrInfo.td:408
352 ASHR_l2rus = 337, // XCoreInstrInfo.td:296
353 ASHR_l3r = 338, // XCoreInstrInfo.td:293
354 BAU_1r = 339, // XCoreInstrInfo.td:986
355 BITREV_l2r = 340, // XCoreInstrInfo.td:925
356 BLACP_lu10 = 341, // XCoreInstrInfo.td:746
357 BLACP_u10 = 342, // XCoreInstrInfo.td:744
358 BLAT_lu6 = 343, // XCoreInstrInfo.td:340
359 BLAT_u6 = 344, // XCoreInstrInfo.td:339
360 BLA_1r = 345, // XCoreInstrInfo.td:1025
361 BLRB_lu10 = 346, // XCoreInstrInfo.td:756
362 BLRB_u10 = 347, // XCoreInstrInfo.td:754
363 BLRF_lu10 = 348, // XCoreInstrInfo.td:751
364 BLRF_u10 = 349, // XCoreInstrInfo.td:748
365 BRBF_lru6 = 350, // XCoreInstrInfo.td:318
366 BRBF_ru6 = 351, // XCoreInstrInfo.td:316
367 BRBT_lru6 = 352, // XCoreInstrInfo.td:318
368 BRBT_ru6 = 353, // XCoreInstrInfo.td:316
369 BRBU_lu6 = 354, // XCoreInstrInfo.td:679
370 BRBU_u6 = 355, // XCoreInstrInfo.td:677
371 BRFF_lru6 = 356, // XCoreInstrInfo.td:311
372 BRFF_ru6 = 357, // XCoreInstrInfo.td:309
373 BRFT_lru6 = 358, // XCoreInstrInfo.td:311
374 BRFT_ru6 = 359, // XCoreInstrInfo.td:309
375 BRFU_lu6 = 360, // XCoreInstrInfo.td:683
376 BRFU_u6 = 361, // XCoreInstrInfo.td:681
377 BRU_1r = 362, // XCoreInstrInfo.td:1001
378 BYTEREV_l2r = 363, // XCoreInstrInfo.td:929
379 CHKCT_2r = 364, // XCoreInstrInfo.td:863
380 CHKCT_rus = 365, // XCoreInstrInfo.td:867
381 CLRE_0R = 366, // XCoreInstrInfo.td:1070
382 CLRPT_1R = 367, // XCoreInstrInfo.td:1065
383 CLRSR_branch_lu6 = 368, // XCoreInstrInfo.td:340
384 CLRSR_branch_u6 = 369, // XCoreInstrInfo.td:339
385 CLRSR_lu6 = 370, // XCoreInstrInfo.td:334
386 CLRSR_u6 = 371, // XCoreInstrInfo.td:332
387 CLZ_l2r = 372, // XCoreInstrInfo.td:933
388 CRC8_l4r = 373, // XCoreInstrInfo.td:533
389 CRC_l3r = 374, // XCoreInstrInfo.td:494
390 DCALL_0R = 375, // XCoreInstrInfo.td:1072
391 DENTSP_0R = 376, // XCoreInstrInfo.td:1075
392 DGETREG_1r = 377, // XCoreInstrInfo.td:1048
393 DIVS_l3r = 378, // XCoreInstrInfo.td:485
394 DIVU_l3r = 379, // XCoreInstrInfo.td:486
395 DRESTSP_0R = 380, // XCoreInstrInfo.td:1078
396 DRET_0R = 381, // XCoreInstrInfo.td:1080
397 ECALLF_1r = 382, // XCoreInstrInfo.td:1018
398 ECALLT_1r = 383, // XCoreInstrInfo.td:1013
399 EDU_1r = 384, // XCoreInstrInfo.td:1050
400 EEF_2r = 385, // XCoreInstrInfo.td:915
401 EET_2r = 386, // XCoreInstrInfo.td:918
402 EEU_1r = 387, // XCoreInstrInfo.td:1053
403 ENDIN_2r = 388, // XCoreInstrInfo.td:911
404 ENTSP_lu6 = 389, // XCoreInstrInfo.td:340
405 ENTSP_u6 = 390, // XCoreInstrInfo.td:339
406 EQ_2rus = 391, // XCoreInstrInfo.td:255
407 EQ_3r = 392, // XCoreInstrInfo.td:253
408 EXTDP_lu6 = 393, // XCoreInstrInfo.td:340
409 EXTDP_u6 = 394, // XCoreInstrInfo.td:339
410 EXTSP_lu6 = 395, // XCoreInstrInfo.td:340
411 EXTSP_u6 = 396, // XCoreInstrInfo.td:339
412 FREER_1r = 397, // XCoreInstrInfo.td:1034
413 FREET_0R = 398, // XCoreInstrInfo.td:1082
414 GETD_l2r = 399, // XCoreInstrInfo.td:937
415 GETED_0R = 400, // XCoreInstrInfo.td:1089
416 GETET_0R = 401, // XCoreInstrInfo.td:1093
417 GETID_0R = 402, // XCoreInstrInfo.td:1085
418 GETKEP_0R = 403, // XCoreInstrInfo.td:1097
419 GETKSP_0R = 404, // XCoreInstrInfo.td:1100
420 GETN_l2r = 405, // XCoreInstrInfo.td:940
421 GETPS_l2r = 406, // XCoreInstrInfo.td:951
422 GETR_rus = 407, // XCoreInstrInfo.td:811
423 GETSR_lu6 = 408, // XCoreInstrInfo.td:340
424 GETSR_u6 = 409, // XCoreInstrInfo.td:339
425 GETST_2r = 410, // XCoreInstrInfo.td:887
426 GETTS_2r = 411, // XCoreInstrInfo.td:815
427 INCT_2r = 412, // XCoreInstrInfo.td:845
428 INITCP_2r = 413, // XCoreInstrInfo.td:899
429 INITDP_2r = 414, // XCoreInstrInfo.td:903
430 INITLR_l2r = 415, // XCoreInstrInfo.td:959
431 INITPC_2r = 416, // XCoreInstrInfo.td:895
432 INITSP_2r = 417, // XCoreInstrInfo.td:891
433 INPW_l2rus = 418, // XCoreInstrInfo.td:511
434 INSHR_2r = 419, // XCoreInstrInfo.td:858
435 INT_2r = 420, // XCoreInstrInfo.td:849
436 IN_2r = 421, // XCoreInstrInfo.td:853
437 KCALL_1r = 422, // XCoreInstrInfo.td:1057
438 KCALL_lu6 = 423, // XCoreInstrInfo.td:340
439 KCALL_u6 = 424, // XCoreInstrInfo.td:339
440 KENTSP_lu6 = 425, // XCoreInstrInfo.td:340
441 KENTSP_u6 = 426, // XCoreInstrInfo.td:339
442 KRESTSP_lu6 = 427, // XCoreInstrInfo.td:340
443 KRESTSP_u6 = 428, // XCoreInstrInfo.td:339
444 KRET_0R = 429, // XCoreInstrInfo.td:1105
445 LADD_l5r = 430, // XCoreInstrInfo.td:541
446 LD16S_3r = 431, // XCoreInstrInfo.td:420
447 LD8U_3r = 432, // XCoreInstrInfo.td:424
448 LDA16B_l3r = 433, // XCoreInstrInfo.td:476
449 LDA16F_l3r = 434, // XCoreInstrInfo.td:470
450 LDAPB_lu10 = 435, // XCoreInstrInfo.td:732
451 LDAPB_u10 = 436, // XCoreInstrInfo.td:728
452 LDAPF_lu10 = 437, // XCoreInstrInfo.td:724
453 LDAPF_lu10_ba = 438, // XCoreInstrInfo.td:737
454 LDAPF_u10 = 439, // XCoreInstrInfo.td:722
455 LDAWB_l2rus = 440, // XCoreInstrInfo.td:466
456 LDAWB_l3r = 441, // XCoreInstrInfo.td:459
457 LDAWCP_lu6 = 442, // XCoreInstrInfo.td:692
458 LDAWCP_u6 = 443, // XCoreInstrInfo.td:688
459 LDAWDP_lru6 = 444, // XCoreInstrInfo.td:574
460 LDAWDP_ru6 = 445, // XCoreInstrInfo.td:570
461 LDAWF_l2rus = 446, // XCoreInstrInfo.td:455
462 LDAWF_l3r = 447, // XCoreInstrInfo.td:448
463 LDAWSP_lru6 = 448, // XCoreInstrInfo.td:628
464 LDAWSP_ru6 = 449, // XCoreInstrInfo.td:625
465 LDC_lru6 = 450, // XCoreInstrInfo.td:637
466 LDC_ru6 = 451, // XCoreInstrInfo.td:634
467 LDET_0R = 452, // XCoreInstrInfo.td:1108
468 LDIVU_l5r = 453, // XCoreInstrInfo.td:553
469 LDSED_0R = 454, // XCoreInstrInfo.td:1110
470 LDSPC_0R = 455, // XCoreInstrInfo.td:1112
471 LDSSR_0R = 456, // XCoreInstrInfo.td:1114
472 LDWCP_lru6 = 457, // XCoreInstrInfo.td:598
473 LDWCP_lu10 = 458, // XCoreInstrInfo.td:763
474 LDWCP_ru6 = 459, // XCoreInstrInfo.td:596
475 LDWCP_u10 = 460, // XCoreInstrInfo.td:761
476 LDWDP_lru6 = 461, // XCoreInstrInfo.td:582
477 LDWDP_ru6 = 462, // XCoreInstrInfo.td:579
478 LDWSP_lru6 = 463, // XCoreInstrInfo.td:619
479 LDWSP_ru6 = 464, // XCoreInstrInfo.td:615
480 LDW_2rus = 465, // XCoreInstrInfo.td:416
481 LDW_3r = 466, // XCoreInstrInfo.td:412
482 LMUL_l6r = 467, // XCoreInstrInfo.td:559
483 LSS_3r = 468, // XCoreInstrInfo.td:405
484 LSUB_l5r = 469, // XCoreInstrInfo.td:547
485 LSU_3r = 470, // XCoreInstrInfo.td:406
486 MACCS_l4r = 471, // XCoreInstrInfo.td:526
487 MACCU_l4r = 472, // XCoreInstrInfo.td:521
488 MJOIN_1r = 473, // XCoreInstrInfo.td:981
489 MKMSK_2r = 474, // XCoreInstrInfo.td:807
490 MKMSK_rus = 475, // XCoreInstrInfo.td:804
491 MSYNC_1r = 476, // XCoreInstrInfo.td:978
492 MUL_l3r = 477, // XCoreInstrInfo.td:482
493 NEG = 478, // XCoreInstrInfo.td:771
494 NOT = 479, // XCoreInstrInfo.td:768
495 OR_3r = 480, // XCoreInstrInfo.td:409
496 OUTCT_2r = 481, // XCoreInstrInfo.td:823
497 OUTCT_rus = 482, // XCoreInstrInfo.td:827
498 OUTPW_l2rus = 483, // XCoreInstrInfo.td:515
499 OUTSHR_2r = 484, // XCoreInstrInfo.td:840
500 OUTT_2r = 485, // XCoreInstrInfo.td:831
501 OUT_2r = 486, // XCoreInstrInfo.td:835
502 PEEK_2r = 487, // XCoreInstrInfo.td:907
503 REMS_l3r = 488, // XCoreInstrInfo.td:487
504 REMU_l3r = 489, // XCoreInstrInfo.td:488
505 RETSP_lu6 = 490, // XCoreInstrInfo.td:327
506 RETSP_u6 = 491, // XCoreInstrInfo.td:325
507 SETCLK_l2r = 492, // XCoreInstrInfo.td:963
508 SETCP_1r = 493, // XCoreInstrInfo.td:1010
509 SETC_l2r = 494, // XCoreInstrInfo.td:943
510 SETC_lru6 = 495, // XCoreInstrInfo.td:645
511 SETC_ru6 = 496, // XCoreInstrInfo.td:641
512 SETDP_1r = 497, // XCoreInstrInfo.td:1007
513 SETD_2r = 498, // XCoreInstrInfo.td:879
514 SETEV_1r = 499, // XCoreInstrInfo.td:1043
515 SETKEP_0R = 500, // XCoreInstrInfo.td:1118
516 SETN_l2r = 501, // XCoreInstrInfo.td:967
517 SETPSC_2r = 502, // XCoreInstrInfo.td:883
518 SETPS_l2r = 503, // XCoreInstrInfo.td:955
519 SETPT_2r = 504, // XCoreInstrInfo.td:819
520 SETRDY_l2r = 505, // XCoreInstrInfo.td:970
521 SETSP_1r = 506, // XCoreInstrInfo.td:1004
522 SETSR_branch_lu6 = 507, // XCoreInstrInfo.td:340
523 SETSR_branch_u6 = 508, // XCoreInstrInfo.td:339
524 SETSR_lu6 = 509, // XCoreInstrInfo.td:334
525 SETSR_u6 = 510, // XCoreInstrInfo.td:332
526 SETTW_l2r = 511, // XCoreInstrInfo.td:947
527 SETV_1r = 512, // XCoreInstrInfo.td:1039
528 SEXT_2r = 513, // XCoreInstrInfo.td:781
529 SEXT_rus = 514, // XCoreInstrInfo.td:775
530 SHL_2rus = 515, // XCoreInstrInfo.td:264
531 SHL_3r = 516, // XCoreInstrInfo.td:261
532 SHR_2rus = 517, // XCoreInstrInfo.td:264
533 SHR_3r = 518, // XCoreInstrInfo.td:261
534 SSYNC_0r = 519, // XCoreInstrInfo.td:1120
535 ST16_l3r = 520, // XCoreInstrInfo.td:502
536 ST8_l3r = 521, // XCoreInstrInfo.td:506
537 STET_0R = 522, // XCoreInstrInfo.td:1125
538 STSED_0R = 523, // XCoreInstrInfo.td:1127
539 STSPC_0R = 524, // XCoreInstrInfo.td:1129
540 STSSR_0R = 525, // XCoreInstrInfo.td:1131
541 STWDP_lru6 = 526, // XCoreInstrInfo.td:590
542 STWDP_ru6 = 527, // XCoreInstrInfo.td:587
543 STWSP_lru6 = 528, // XCoreInstrInfo.td:609
544 STWSP_ru6 = 529, // XCoreInstrInfo.td:605
545 STW_2rus = 530, // XCoreInstrInfo.td:434
546 STW_l3r = 531, // XCoreInstrInfo.td:430
547 SUB_2rus = 532, // XCoreInstrInfo.td:247
548 SUB_3r = 533, // XCoreInstrInfo.td:244
549 SYNCR_1r = 534, // XCoreInstrInfo.td:1030
550 TESTCT_2r = 535, // XCoreInstrInfo.td:871
551 TESTLCL_l2r = 536, // XCoreInstrInfo.td:974
552 TESTWCT_2r = 537, // XCoreInstrInfo.td:875
553 TSETMR_2r = 538, // XCoreInstrInfo.td:921
554 TSETR_3r = 539, // XCoreInstrInfo.td:444
555 TSTART_1R = 540, // XCoreInstrInfo.td:1063
556 WAITEF_1R = 541, // XCoreInstrInfo.td:1059
557 WAITET_1R = 542, // XCoreInstrInfo.td:1061
558 WAITEU_0R = 543, // XCoreInstrInfo.td:1136
559 XOR_l3r = 544, // XCoreInstrInfo.td:490
560 ZEXT_2r = 545, // XCoreInstrInfo.td:792
561 ZEXT_rus = 546, // XCoreInstrInfo.td:786
562 INSTRUCTION_LIST_END = 547
563 };
564
565} // namespace llvm::XCore
566
567#endif // GET_INSTRINFO_ENUM
568
569#ifdef GET_INSTRINFO_SCHED_ENUM
570#undef GET_INSTRINFO_SCHED_ENUM
571
572namespace llvm::XCore::Sched {
573
574 enum {
575 NoInstrModel = 0,
576 SCHED_LIST_END = 1
577 };
578
579} // namespace llvm::XCore::Sched
580
581#endif // GET_INSTRINFO_SCHED_ENUM
582
583#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
584
585namespace llvm {
586
587struct XCoreInstrTable {
588 MCInstrDesc Insts[547];
589 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
590 MCPhysReg ImplicitOps[11];
591 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
592 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
593 MCOperandInfo OperandInfo[213];
594};
595} // namespace llvm
596
597#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
598
599#ifdef GET_INSTRINFO_MC_DESC
600#undef GET_INSTRINFO_MC_DESC
601
602namespace llvm {
603
604static_assert((sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
605static constexpr unsigned XCoreOpInfoBase = (sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) / sizeof(MCOperandInfo);
606
607extern const XCoreInstrTable XCoreDescs = {
608 {
609 { 546, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 205, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_rus
610 { 545, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 172, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_2r
611 { 544, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_l3r
612 { 543, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEU_0R
613 { 542, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITET_1R
614 { 541, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEF_1R
615 { 540, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSTART_1R
616 { 539, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 210, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETR_3r
617 { 538, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 208, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETMR_2r
618 { 537, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTWCT_2r
619 { 536, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTLCL_l2r
620 { 535, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTCT_2r
621 { 534, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SYNCR_1r
622 { 533, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_3r
623 { 532, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_2rus
624 { 531, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_l3r
625 { 530, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_2rus
626 { 529, 2, 0, 2, 0, 1, 0, XCoreOpInfoBase + 191, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_ru6
627 { 528, 2, 0, 4, 0, 1, 0, XCoreOpInfoBase + 191, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_lru6
628 { 527, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_ru6
629 { 526, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_lru6
630 { 525, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSSR_0R
631 { 524, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSPC_0R
632 { 523, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSED_0R
633 { 522, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STET_0R
634 { 521, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST8_l3r
635 { 520, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST16_l3r
636 { 519, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SSYNC_0r
637 { 518, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_3r
638 { 517, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_2rus
639 { 516, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_3r
640 { 515, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_2rus
641 { 514, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 205, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_rus
642 { 513, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 172, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_2r
643 { 512, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 32, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETV_1r
644 { 511, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETTW_l2r
645 { 510, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_u6
646 { 509, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_lu6
647 { 508, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_u6
648 { 507, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_lu6
649 { 506, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 32, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSP_1r
650 { 505, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETRDY_l2r
651 { 504, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPT_2r
652 { 503, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPS_l2r
653 { 502, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPSC_2r
654 { 501, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETN_l2r
655 { 500, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETKEP_0R
656 { 499, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 32, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETEV_1r
657 { 498, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETD_2r
658 { 497, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETDP_1r
659 { 496, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 175, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_ru6
660 { 495, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 175, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_lru6
661 { 494, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_l2r
662 { 493, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCP_1r
663 { 492, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCLK_l2r
664 { 491, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_u6
665 { 490, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_lu6
666 { 489, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMU_l3r
667 { 488, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMS_l3r
668 { 487, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PEEK_2r
669 { 486, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUT_2r
670 { 485, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTT_2r
671 { 484, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 172, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTSHR_2r
672 { 483, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTPW_l2rus
673 { 482, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 175, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_rus
674 { 481, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_2r
675 { 480, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_3r
676 { 479, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
677 { 478, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG
678 { 477, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_l3r
679 { 476, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MSYNC_1r
680 { 475, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 175, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_rus
681 { 474, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_2r
682 { 473, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MJOIN_1r
683 { 472, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 199, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCU_l4r
684 { 471, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 199, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCS_l4r
685 { 470, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSU_3r
686 { 469, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 186, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSUB_l5r
687 { 468, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSS_3r
688 { 467, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LMUL_l6r
689 { 466, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_3r
690 { 465, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_2rus
691 { 464, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 191, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_ru6
692 { 463, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 191, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_lru6
693 { 462, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_ru6
694 { 461, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_lru6
695 { 460, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_u10
696 { 459, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_ru6
697 { 458, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lu10
698 { 457, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lru6
699 { 456, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSSR_0R
700 { 455, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSPC_0R
701 { 454, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSED_0R
702 { 453, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 186, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIVU_l5r
703 { 452, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDET_0R
704 { 451, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_ru6
705 { 450, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_lru6
706 { 449, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 191, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_ru6
707 { 448, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 191, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_lru6
708 { 447, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l3r
709 { 446, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l2rus
710 { 445, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_ru6
711 { 444, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 191, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_lru6
712 { 443, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_u6
713 { 442, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_lu6
714 { 441, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l3r
715 { 440, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l2rus
716 { 439, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_u10
717 { 438, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10_ba
718 { 437, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10
719 { 436, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_u10
720 { 435, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_lu10
721 { 434, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16F_l3r
722 { 433, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16B_l3r
723 { 432, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD8U_3r
724 { 431, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD16S_3r
725 { 430, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 186, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LADD_l5r
726 { 429, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRET_0R
727 { 428, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_u6
728 { 427, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_lu6
729 { 426, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_u6
730 { 425, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_lu6
731 { 424, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_u6
732 { 423, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_lu6
733 { 422, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_1r
734 { 421, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IN_2r
735 { 420, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INT_2r
736 { 419, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 172, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSHR_2r
737 { 418, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INPW_l2rus
738 { 417, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITSP_2r
739 { 416, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITPC_2r
740 { 415, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITLR_l2r
741 { 414, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITDP_2r
742 { 413, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITCP_2r
743 { 412, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INCT_2r
744 { 411, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETTS_2r
745 { 410, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETST_2r
746 { 409, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_u6
747 { 408, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_lu6
748 { 407, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 175, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETR_rus
749 { 406, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETPS_l2r
750 { 405, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETN_l2r
751 { 404, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKSP_0R
752 { 403, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKEP_0R
753 { 402, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETID_0R
754 { 401, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETET_0R
755 { 400, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETED_0R
756 { 399, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETD_l2r
757 { 398, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREET_0R
758 { 397, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREER_1r
759 { 396, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_u6
760 { 395, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_lu6
761 { 394, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_u6
762 { 393, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_lu6
763 { 392, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_3r
764 { 391, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_2rus
765 { 390, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_u6
766 { 389, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_lu6
767 { 388, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENDIN_2r
768 { 387, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEU_1r
769 { 386, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EET_2r
770 { 385, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEF_2r
771 { 384, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EDU_1r
772 { 383, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLT_1r
773 { 382, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLF_1r
774 { 381, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRET_0R
775 { 380, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRESTSP_0R
776 { 379, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVU_l3r
777 { 378, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVS_l3r
778 { 377, 1, 1, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DGETREG_1r
779 { 376, 0, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DENTSP_0R
780 { 375, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DCALL_0R
781 { 374, 4, 1, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC_l3r
782 { 373, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 177, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC8_l4r
783 { 372, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_l2r
784 { 371, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_u6
785 { 370, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_lu6
786 { 369, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_u6
787 { 368, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_lu6
788 { 367, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRPT_1R
789 { 366, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRE_0R
790 { 365, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 175, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_rus
791 { 364, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_2r
792 { 363, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BYTEREV_l2r
793 { 362, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRU_1r
794 { 361, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_u6
795 { 360, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_lu6
796 { 359, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_ru6
797 { 358, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_lru6
798 { 357, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_ru6
799 { 356, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_lru6
800 { 355, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_u6
801 { 354, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_lu6
802 { 353, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_ru6
803 { 352, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_lru6
804 { 351, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_ru6
805 { 350, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_lru6
806 { 349, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_u10
807 { 348, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_lu10
808 { 347, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_u10
809 { 346, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_lu10
810 { 345, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 32, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLA_1r
811 { 344, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_u6
812 { 343, 1, 0, 4, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_lu6
813 { 342, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_u10
814 { 341, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_lu10
815 { 340, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITREV_l2r
816 { 339, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BAU_1r
817 { 338, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l3r
818 { 337, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l2rus
819 { 336, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_3r
820 { 335, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 172, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_2r
821 { 334, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 169, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_3r
822 { 333, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 166, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_2rus
823 { 332, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWFI
824 { 331, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_CC
825 { 330, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWFI
826 { 329, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWFI
827 { 328, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FRAME_TO_ARGS_OFFSET
828 { 327, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_RETURN
829 { 326, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT32
830 { 325, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT
831 { 324, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
832 { 323, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
833 { 322, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
834 { 321, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
835 { 320, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
836 { 319, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
837 { 318, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
838 { 317, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
839 { 316, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
840 { 315, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
841 { 314, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
842 { 313, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
843 { 312, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
844 { 311, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
845 { 310, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
846 { 309, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
847 { 308, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
848 { 307, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
849 { 306, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
850 { 305, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
851 { 304, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
852 { 303, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
853 { 302, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
854 { 301, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
855 { 300, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
856 { 299, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
857 { 298, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
858 { 297, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
859 { 296, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
860 { 295, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
861 { 294, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
862 { 293, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
863 { 292, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
864 { 291, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
865 { 290, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
866 { 289, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
867 { 288, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
868 { 287, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
869 { 286, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
870 { 285, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
871 { 284, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
872 { 283, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
873 { 282, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
874 { 281, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
875 { 280, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
876 { 279, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
877 { 278, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
878 { 277, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
879 { 276, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
880 { 275, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
881 { 274, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
882 { 273, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
883 { 272, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
884 { 271, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
885 { 270, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
886 { 269, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
887 { 268, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
888 { 267, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
889 { 266, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
890 { 265, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
891 { 264, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
892 { 263, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
893 { 262, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
894 { 261, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
895 { 260, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
896 { 259, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
897 { 258, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
898 { 257, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
899 { 256, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
900 { 255, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
901 { 254, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
902 { 253, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
903 { 252, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
904 { 251, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
905 { 250, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
906 { 249, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
907 { 248, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
908 { 247, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
909 { 246, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
910 { 245, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
911 { 244, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
912 { 243, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
913 { 242, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
914 { 241, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
915 { 240, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
916 { 239, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
917 { 238, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
918 { 237, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
919 { 236, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
920 { 235, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
921 { 234, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
922 { 233, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
923 { 232, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
924 { 231, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
925 { 230, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
926 { 229, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
927 { 228, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
928 { 227, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
929 { 226, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
930 { 225, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
931 { 224, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
932 { 223, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
933 { 222, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
934 { 221, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
935 { 220, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
936 { 219, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
937 { 218, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
938 { 217, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
939 { 216, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
940 { 215, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
941 { 214, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
942 { 213, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
943 { 212, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
944 { 211, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
945 { 210, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
946 { 209, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
947 { 208, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
948 { 207, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
949 { 206, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
950 { 205, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
951 { 204, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
952 { 203, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
953 { 202, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
954 { 201, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
955 { 200, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
956 { 199, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
957 { 198, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
958 { 197, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
959 { 196, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
960 { 195, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
961 { 194, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
962 { 193, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
963 { 192, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
964 { 191, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
965 { 190, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
966 { 189, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
967 { 188, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
968 { 187, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
969 { 186, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
970 { 185, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
971 { 184, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
972 { 183, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
973 { 182, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
974 { 181, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
975 { 180, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
976 { 179, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
977 { 178, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
978 { 177, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
979 { 176, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
980 { 175, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
981 { 174, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
982 { 173, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
983 { 172, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
984 { 171, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
985 { 170, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
986 { 169, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
987 { 168, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
988 { 167, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
989 { 166, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
990 { 165, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
991 { 164, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
992 { 163, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
993 { 162, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
994 { 161, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
995 { 160, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
996 { 159, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
997 { 158, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
998 { 157, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
999 { 156, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1000 { 155, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1001 { 154, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1002 { 153, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1003 { 152, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1004 { 151, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1005 { 150, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1006 { 149, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1007 { 148, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1008 { 147, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1009 { 146, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1010 { 145, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1011 { 144, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1012 { 143, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1013 { 142, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1014 { 141, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1015 { 140, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1016 { 139, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1017 { 138, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1018 { 137, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1019 { 136, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1020 { 135, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1021 { 134, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1022 { 133, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1023 { 132, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1024 { 131, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1025 { 130, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1026 { 129, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1027 { 128, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1028 { 127, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1029 { 126, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1030 { 125, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1031 { 124, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1032 { 123, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1033 { 122, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1034 { 121, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1035 { 120, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1036 { 119, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1037 { 118, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1038 { 117, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1039 { 116, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1040 { 115, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1041 { 114, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1042 { 113, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1043 { 112, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1044 { 111, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1045 { 110, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1046 { 109, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1047 { 108, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1048 { 107, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1049 { 106, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1050 { 105, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1051 { 104, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1052 { 103, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1053 { 102, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1054 { 101, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1055 { 100, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1056 { 99, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1057 { 98, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1058 { 97, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1059 { 96, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1060 { 95, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1061 { 94, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1062 { 93, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1063 { 92, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1064 { 91, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1065 { 90, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1066 { 89, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1067 { 88, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1068 { 87, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1069 { 86, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1070 { 85, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1071 { 84, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1072 { 83, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1073 { 82, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1074 { 81, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1075 { 80, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1076 { 79, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1077 { 78, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1078 { 77, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1079 { 76, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1080 { 75, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1081 { 74, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1082 { 73, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1083 { 72, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1084 { 71, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1085 { 70, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1086 { 69, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1087 { 68, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1088 { 67, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1089 { 66, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1090 { 65, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1091 { 64, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1092 { 63, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1093 { 62, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1094 { 61, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1095 { 60, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1096 { 59, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1097 { 58, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1098 { 57, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1099 { 56, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1100 { 55, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1101 { 54, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1102 { 53, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1103 { 52, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1104 { 51, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1105 { 50, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1106 { 49, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1107 { 48, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1108 { 47, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1109 { 46, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1110 { 45, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1111 { 44, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1112 { 43, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1113 { 42, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14663
1114 { 41, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14662
1115 { 40, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1116 { 39, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1117 { 38, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1118 { 37, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1119 { 36, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1120 { 35, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1121 { 34, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1122 { 33, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1123 { 32, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14661
1124 { 31, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1125 { 30, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14301
1126 { 29, 6, 1, 0, 0, 0, 0, XCoreOpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1127 { 28, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1128 { 27, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1129 { 26, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1130 { 25, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1131 { 24, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1132 { 23, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1133 { 22, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1134 { 21, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1135 { 20, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1136 { 19, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1137 { 18, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1138 { 17, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1139 { 16, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1140 { 15, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1141 { 14, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1142 { 13, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1143 { 12, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1144 { 11, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1145 { 10, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1146 { 9, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1147 { 8, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1148 { 7, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1149 { 6, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1150 { 5, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1151 { 4, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1152 { 3, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1153 { 2, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1154 { 1, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1155 { 0, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1156 }, {
1157 /* 0 */
1158 /* 0 */ XCore::SP, XCore::SP,
1159 /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
1160 /* 9 */ XCore::R11,
1161 /* 10 */ XCore::SP,
1162 }, {
1163 0
1164 }, {
1165 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1166 /* 1 */
1167 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1168 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1169 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1170 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1171 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1172 /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1173 /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1174 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1175 /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1176 /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1177 /* 32 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1178 /* 33 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1179 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1180 /* 38 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1181 /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1182 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1183 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1184 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1185 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1186 /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1187 /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1188 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1189 /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1190 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1191 /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1192 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1193 /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1194 /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1195 /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1196 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1197 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1198 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1199 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1200 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1201 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1202 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1203 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1204 /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1205 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1206 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1207 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1208 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1209 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1210 /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1211 /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1212 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1213 /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1214 /* 155 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1215 /* 157 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1216 /* 159 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1217 /* 162 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1218 /* 166 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1219 /* 169 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1220 /* 172 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1221 /* 175 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1222 /* 177 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1223 /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1224 /* 186 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1225 /* 191 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1226 /* 193 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1227 /* 199 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1228 /* 205 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1229 /* 208 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1230 /* 210 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1231 }
1232};
1233
1234
1235#ifdef __GNUC__
1236#pragma GCC diagnostic push
1237#pragma GCC diagnostic ignored "-Woverlength-strings"
1238#endif
1239extern const char XCoreInstrNameData[] = {
1240 /* 0 */ "G_FLOG10\000"
1241 /* 9 */ "G_FEXP10\000"
1242 /* 18 */ "LDAPB_u10\000"
1243 /* 28 */ "BLRB_u10\000"
1244 /* 37 */ "LDAPF_u10\000"
1245 /* 47 */ "BLRF_u10\000"
1246 /* 56 */ "BLACP_u10\000"
1247 /* 66 */ "LDWCP_u10\000"
1248 /* 76 */ "LDAPB_lu10\000"
1249 /* 87 */ "BLRB_lu10\000"
1250 /* 97 */ "LDAPF_lu10\000"
1251 /* 108 */ "BLRF_lu10\000"
1252 /* 118 */ "BLACP_lu10\000"
1253 /* 129 */ "LDWCP_lu10\000"
1254 /* 140 */ "BR_JT32\000"
1255 /* 148 */ "G_FLOG2\000"
1256 /* 156 */ "G_FATAN2\000"
1257 /* 165 */ "G_FEXP2\000"
1258 /* 173 */ "KCALL_u6\000"
1259 /* 182 */ "LDAWCP_u6\000"
1260 /* 192 */ "EXTDP_u6\000"
1261 /* 201 */ "RETSP_u6\000"
1262 /* 210 */ "KENTSP_u6\000"
1263 /* 220 */ "KRESTSP_u6\000"
1264 /* 231 */ "EXTSP_u6\000"
1265 /* 240 */ "CLRSR_u6\000"
1266 /* 249 */ "GETSR_u6\000"
1267 /* 258 */ "SETSR_u6\000"
1268 /* 267 */ "BLAT_u6\000"
1269 /* 275 */ "BRBU_u6\000"
1270 /* 283 */ "BRFU_u6\000"
1271 /* 291 */ "CLRSR_branch_u6\000"
1272 /* 307 */ "SETSR_branch_u6\000"
1273 /* 323 */ "KCALL_lu6\000"
1274 /* 333 */ "LDAWCP_lu6\000"
1275 /* 344 */ "EXTDP_lu6\000"
1276 /* 354 */ "RETSP_lu6\000"
1277 /* 364 */ "KENTSP_lu6\000"
1278 /* 375 */ "KRESTSP_lu6\000"
1279 /* 387 */ "EXTSP_lu6\000"
1280 /* 397 */ "CLRSR_lu6\000"
1281 /* 407 */ "GETSR_lu6\000"
1282 /* 417 */ "SETSR_lu6\000"
1283 /* 427 */ "BLAT_lu6\000"
1284 /* 436 */ "BRBU_lu6\000"
1285 /* 445 */ "BRFU_lu6\000"
1286 /* 454 */ "CLRSR_branch_lu6\000"
1287 /* 471 */ "SETSR_branch_lu6\000"
1288 /* 488 */ "LDC_ru6\000"
1289 /* 496 */ "SETC_ru6\000"
1290 /* 505 */ "BRBF_ru6\000"
1291 /* 514 */ "BRFF_ru6\000"
1292 /* 523 */ "LDWCP_ru6\000"
1293 /* 533 */ "LDAWDP_ru6\000"
1294 /* 544 */ "LDWDP_ru6\000"
1295 /* 554 */ "STWDP_ru6\000"
1296 /* 564 */ "LDAWSP_ru6\000"
1297 /* 575 */ "LDWSP_ru6\000"
1298 /* 585 */ "STWSP_ru6\000"
1299 /* 595 */ "BRBT_ru6\000"
1300 /* 604 */ "BRFT_ru6\000"
1301 /* 613 */ "LDC_lru6\000"
1302 /* 622 */ "SETC_lru6\000"
1303 /* 632 */ "BRBF_lru6\000"
1304 /* 642 */ "BRFF_lru6\000"
1305 /* 652 */ "LDWCP_lru6\000"
1306 /* 663 */ "LDAWDP_lru6\000"
1307 /* 675 */ "LDWDP_lru6\000"
1308 /* 686 */ "STWDP_lru6\000"
1309 /* 697 */ "LDAWSP_lru6\000"
1310 /* 709 */ "LDWSP_lru6\000"
1311 /* 720 */ "STWSP_lru6\000"
1312 /* 731 */ "BRBT_lru6\000"
1313 /* 741 */ "BRFT_lru6\000"
1314 /* 751 */ "G_FMA\000"
1315 /* 757 */ "G_STRICT_FMA\000"
1316 /* 770 */ "G_FSUB\000"
1317 /* 777 */ "G_STRICT_FSUB\000"
1318 /* 791 */ "G_ATOMICRMW_FSUB\000"
1319 /* 808 */ "G_SUB\000"
1320 /* 814 */ "G_ATOMICRMW_SUB\000"
1321 /* 830 */ "SELECT_CC\000"
1322 /* 840 */ "G_INTRINSIC\000"
1323 /* 852 */ "G_FPTRUNC\000"
1324 /* 862 */ "G_INTRINSIC_TRUNC\000"
1325 /* 880 */ "G_TRUNC\000"
1326 /* 888 */ "G_BUILD_VECTOR_TRUNC\000"
1327 /* 909 */ "G_DYN_STACKALLOC\000"
1328 /* 926 */ "G_FMAD\000"
1329 /* 933 */ "G_INDEXED_SEXTLOAD\000"
1330 /* 952 */ "G_SEXTLOAD\000"
1331 /* 963 */ "G_INDEXED_ZEXTLOAD\000"
1332 /* 982 */ "G_ZEXTLOAD\000"
1333 /* 993 */ "G_INDEXED_LOAD\000"
1334 /* 1008 */ "G_LOAD\000"
1335 /* 1015 */ "G_VECREDUCE_FADD\000"
1336 /* 1032 */ "G_FADD\000"
1337 /* 1039 */ "G_VECREDUCE_SEQ_FADD\000"
1338 /* 1060 */ "G_STRICT_FADD\000"
1339 /* 1074 */ "G_ATOMICRMW_FADD\000"
1340 /* 1091 */ "G_VECREDUCE_ADD\000"
1341 /* 1107 */ "G_ADD\000"
1342 /* 1113 */ "G_PTR_ADD\000"
1343 /* 1123 */ "G_ATOMICRMW_ADD\000"
1344 /* 1139 */ "G_ATOMICRMW_NAND\000"
1345 /* 1156 */ "G_VECREDUCE_AND\000"
1346 /* 1172 */ "G_AND\000"
1347 /* 1178 */ "G_ATOMICRMW_AND\000"
1348 /* 1194 */ "LIFETIME_END\000"
1349 /* 1207 */ "G_BRCOND\000"
1350 /* 1216 */ "G_ATOMICRMW_USUB_COND\000"
1351 /* 1238 */ "G_LLROUND\000"
1352 /* 1248 */ "G_LROUND\000"
1353 /* 1257 */ "G_INTRINSIC_ROUND\000"
1354 /* 1275 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1355 /* 1301 */ "LOAD_STACK_GUARD\000"
1356 /* 1318 */ "PSEUDO_PROBE\000"
1357 /* 1331 */ "G_SSUBE\000"
1358 /* 1339 */ "G_USUBE\000"
1359 /* 1347 */ "G_FENCE\000"
1360 /* 1355 */ "ARITH_FENCE\000"
1361 /* 1367 */ "REG_SEQUENCE\000"
1362 /* 1380 */ "G_SADDE\000"
1363 /* 1388 */ "G_UADDE\000"
1364 /* 1396 */ "G_GET_FPMODE\000"
1365 /* 1409 */ "G_RESET_FPMODE\000"
1366 /* 1424 */ "G_SET_FPMODE\000"
1367 /* 1437 */ "G_FMINNUM_IEEE\000"
1368 /* 1452 */ "G_FMAXNUM_IEEE\000"
1369 /* 1467 */ "G_VSCALE\000"
1370 /* 1476 */ "G_JUMP_TABLE\000"
1371 /* 1489 */ "BUNDLE\000"
1372 /* 1496 */ "G_MEMCPY_INLINE\000"
1373 /* 1512 */ "RELOC_NONE\000"
1374 /* 1523 */ "LOCAL_ESCAPE\000"
1375 /* 1536 */ "G_STACKRESTORE\000"
1376 /* 1551 */ "G_INDEXED_STORE\000"
1377 /* 1567 */ "G_STORE\000"
1378 /* 1575 */ "G_BITREVERSE\000"
1379 /* 1588 */ "FAKE_USE\000"
1380 /* 1597 */ "DBG_VALUE\000"
1381 /* 1607 */ "G_GLOBAL_VALUE\000"
1382 /* 1622 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1383 /* 1645 */ "CONVERGENCECTRL_GLUE\000"
1384 /* 1666 */ "G_STACKSAVE\000"
1385 /* 1678 */ "G_MEMMOVE\000"
1386 /* 1688 */ "G_FREEZE\000"
1387 /* 1697 */ "G_FCANONICALIZE\000"
1388 /* 1713 */ "G_FMODF\000"
1389 /* 1721 */ "G_CTLZ_ZERO_UNDEF\000"
1390 /* 1739 */ "G_CTTZ_ZERO_UNDEF\000"
1391 /* 1757 */ "INIT_UNDEF\000"
1392 /* 1768 */ "G_IMPLICIT_DEF\000"
1393 /* 1783 */ "DBG_INSTR_REF\000"
1394 /* 1797 */ "G_FNEG\000"
1395 /* 1804 */ "EXTRACT_SUBREG\000"
1396 /* 1819 */ "INSERT_SUBREG\000"
1397 /* 1833 */ "G_SEXT_INREG\000"
1398 /* 1846 */ "SUBREG_TO_REG\000"
1399 /* 1860 */ "G_ATOMIC_CMPXCHG\000"
1400 /* 1877 */ "G_ATOMICRMW_XCHG\000"
1401 /* 1894 */ "G_GET_ROUNDING\000"
1402 /* 1909 */ "G_SET_ROUNDING\000"
1403 /* 1924 */ "G_FLOG\000"
1404 /* 1931 */ "G_VAARG\000"
1405 /* 1939 */ "PREALLOCATED_ARG\000"
1406 /* 1956 */ "G_PREFETCH\000"
1407 /* 1967 */ "G_SMULH\000"
1408 /* 1975 */ "G_UMULH\000"
1409 /* 1983 */ "G_FTANH\000"
1410 /* 1991 */ "G_FSINH\000"
1411 /* 1999 */ "G_FCOSH\000"
1412 /* 2007 */ "LDAWFI\000"
1413 /* 2014 */ "LDWFI\000"
1414 /* 2020 */ "STWFI\000"
1415 /* 2026 */ "DBG_PHI\000"
1416 /* 2034 */ "G_FPTOSI\000"
1417 /* 2043 */ "G_FPTOUI\000"
1418 /* 2052 */ "G_FPOWI\000"
1419 /* 2060 */ "COPY_LANEMASK\000"
1420 /* 2074 */ "G_PTRMASK\000"
1421 /* 2084 */ "GC_LABEL\000"
1422 /* 2093 */ "DBG_LABEL\000"
1423 /* 2103 */ "EH_LABEL\000"
1424 /* 2112 */ "ANNOTATION_LABEL\000"
1425 /* 2129 */ "ICALL_BRANCH_FUNNEL\000"
1426 /* 2149 */ "G_FSHL\000"
1427 /* 2156 */ "G_SHL\000"
1428 /* 2162 */ "G_FCEIL\000"
1429 /* 2170 */ "G_SAVGCEIL\000"
1430 /* 2181 */ "G_UAVGCEIL\000"
1431 /* 2192 */ "PATCHABLE_TAIL_CALL\000"
1432 /* 2212 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1433 /* 2239 */ "PATCHABLE_EVENT_CALL\000"
1434 /* 2260 */ "FENTRY_CALL\000"
1435 /* 2272 */ "KILL\000"
1436 /* 2277 */ "G_CONSTANT_POOL\000"
1437 /* 2293 */ "G_ROTL\000"
1438 /* 2300 */ "G_VECREDUCE_FMUL\000"
1439 /* 2317 */ "G_FMUL\000"
1440 /* 2324 */ "G_VECREDUCE_SEQ_FMUL\000"
1441 /* 2345 */ "G_STRICT_FMUL\000"
1442 /* 2359 */ "G_VECREDUCE_MUL\000"
1443 /* 2375 */ "G_MUL\000"
1444 /* 2381 */ "G_FREM\000"
1445 /* 2388 */ "G_STRICT_FREM\000"
1446 /* 2402 */ "G_SREM\000"
1447 /* 2409 */ "G_UREM\000"
1448 /* 2416 */ "G_SDIVREM\000"
1449 /* 2426 */ "G_UDIVREM\000"
1450 /* 2436 */ "INLINEASM\000"
1451 /* 2446 */ "G_VECREDUCE_FMINIMUM\000"
1452 /* 2467 */ "G_FMINIMUM\000"
1453 /* 2478 */ "G_ATOMICRMW_FMINIMUM\000"
1454 /* 2499 */ "G_VECREDUCE_FMAXIMUM\000"
1455 /* 2520 */ "G_FMAXIMUM\000"
1456 /* 2531 */ "G_ATOMICRMW_FMAXIMUM\000"
1457 /* 2552 */ "G_FMINIMUMNUM\000"
1458 /* 2566 */ "G_FMAXIMUMNUM\000"
1459 /* 2580 */ "G_FMINNUM\000"
1460 /* 2590 */ "G_FMAXNUM\000"
1461 /* 2600 */ "G_FATAN\000"
1462 /* 2608 */ "G_FTAN\000"
1463 /* 2615 */ "G_INTRINSIC_ROUNDEVEN\000"
1464 /* 2637 */ "G_ASSERT_ALIGN\000"
1465 /* 2652 */ "G_FCOPYSIGN\000"
1466 /* 2664 */ "G_VECREDUCE_FMIN\000"
1467 /* 2681 */ "G_ATOMICRMW_FMIN\000"
1468 /* 2698 */ "G_VECREDUCE_SMIN\000"
1469 /* 2715 */ "G_SMIN\000"
1470 /* 2722 */ "G_VECREDUCE_UMIN\000"
1471 /* 2739 */ "G_UMIN\000"
1472 /* 2746 */ "G_ATOMICRMW_UMIN\000"
1473 /* 2763 */ "G_ATOMICRMW_MIN\000"
1474 /* 2779 */ "G_FASIN\000"
1475 /* 2787 */ "G_FSIN\000"
1476 /* 2794 */ "CFI_INSTRUCTION\000"
1477 /* 2810 */ "EH_RETURN\000"
1478 /* 2820 */ "ADJCALLSTACKDOWN\000"
1479 /* 2837 */ "G_SSUBO\000"
1480 /* 2845 */ "G_USUBO\000"
1481 /* 2853 */ "G_SADDO\000"
1482 /* 2861 */ "G_UADDO\000"
1483 /* 2869 */ "JUMP_TABLE_DEBUG_INFO\000"
1484 /* 2891 */ "G_SMULO\000"
1485 /* 2899 */ "G_UMULO\000"
1486 /* 2907 */ "G_BZERO\000"
1487 /* 2915 */ "STACKMAP\000"
1488 /* 2924 */ "G_DEBUGTRAP\000"
1489 /* 2936 */ "G_UBSANTRAP\000"
1490 /* 2948 */ "G_TRAP\000"
1491 /* 2955 */ "G_ATOMICRMW_UDEC_WRAP\000"
1492 /* 2977 */ "G_ATOMICRMW_UINC_WRAP\000"
1493 /* 2999 */ "G_BSWAP\000"
1494 /* 3007 */ "G_SITOFP\000"
1495 /* 3016 */ "G_UITOFP\000"
1496 /* 3025 */ "G_FCMP\000"
1497 /* 3032 */ "G_ICMP\000"
1498 /* 3039 */ "G_SCMP\000"
1499 /* 3046 */ "G_UCMP\000"
1500 /* 3053 */ "CONVERGENCECTRL_LOOP\000"
1501 /* 3074 */ "G_CTPOP\000"
1502 /* 3082 */ "PATCHABLE_OP\000"
1503 /* 3095 */ "FAULTING_OP\000"
1504 /* 3107 */ "ADJCALLSTACKUP\000"
1505 /* 3122 */ "PREALLOCATED_SETUP\000"
1506 /* 3141 */ "G_FLDEXP\000"
1507 /* 3150 */ "G_STRICT_FLDEXP\000"
1508 /* 3166 */ "G_FEXP\000"
1509 /* 3173 */ "G_FFREXP\000"
1510 /* 3182 */ "LDSPC_0R\000"
1511 /* 3191 */ "STSPC_0R\000"
1512 /* 3200 */ "LDSED_0R\000"
1513 /* 3209 */ "STSED_0R\000"
1514 /* 3218 */ "GETED_0R\000"
1515 /* 3227 */ "GETID_0R\000"
1516 /* 3236 */ "CLRE_0R\000"
1517 /* 3244 */ "DCALL_0R\000"
1518 /* 3253 */ "GETKEP_0R\000"
1519 /* 3263 */ "SETKEP_0R\000"
1520 /* 3273 */ "GETKSP_0R\000"
1521 /* 3283 */ "DENTSP_0R\000"
1522 /* 3293 */ "DRESTSP_0R\000"
1523 /* 3304 */ "LDSSR_0R\000"
1524 /* 3313 */ "STSSR_0R\000"
1525 /* 3322 */ "LDET_0R\000"
1526 /* 3330 */ "FREET_0R\000"
1527 /* 3339 */ "DRET_0R\000"
1528 /* 3347 */ "KRET_0R\000"
1529 /* 3355 */ "GETET_0R\000"
1530 /* 3364 */ "STET_0R\000"
1531 /* 3372 */ "WAITEU_0R\000"
1532 /* 3382 */ "WAITEF_1R\000"
1533 /* 3392 */ "WAITET_1R\000"
1534 /* 3402 */ "CLRPT_1R\000"
1535 /* 3411 */ "TSTART_1R\000"
1536 /* 3421 */ "G_BR\000"
1537 /* 3426 */ "INLINEASM_BR\000"
1538 /* 3439 */ "G_BLOCK_ADDR\000"
1539 /* 3452 */ "MEMBARRIER\000"
1540 /* 3463 */ "G_CONSTANT_FOLD_BARRIER\000"
1541 /* 3487 */ "PATCHABLE_FUNCTION_ENTER\000"
1542 /* 3512 */ "G_READCYCLECOUNTER\000"
1543 /* 3531 */ "G_READSTEADYCOUNTER\000"
1544 /* 3551 */ "G_READ_REGISTER\000"
1545 /* 3567 */ "G_WRITE_REGISTER\000"
1546 /* 3584 */ "G_ASHR\000"
1547 /* 3591 */ "G_FSHR\000"
1548 /* 3598 */ "G_LSHR\000"
1549 /* 3605 */ "CONVERGENCECTRL_ANCHOR\000"
1550 /* 3628 */ "G_FFLOOR\000"
1551 /* 3637 */ "G_SAVGFLOOR\000"
1552 /* 3649 */ "G_UAVGFLOOR\000"
1553 /* 3661 */ "G_EXTRACT_SUBVECTOR\000"
1554 /* 3681 */ "G_INSERT_SUBVECTOR\000"
1555 /* 3700 */ "G_BUILD_VECTOR\000"
1556 /* 3715 */ "G_SHUFFLE_VECTOR\000"
1557 /* 3732 */ "G_STEP_VECTOR\000"
1558 /* 3746 */ "G_SPLAT_VECTOR\000"
1559 /* 3761 */ "G_VECREDUCE_XOR\000"
1560 /* 3777 */ "G_XOR\000"
1561 /* 3783 */ "G_ATOMICRMW_XOR\000"
1562 /* 3799 */ "G_VECREDUCE_OR\000"
1563 /* 3814 */ "G_OR\000"
1564 /* 3819 */ "G_ATOMICRMW_OR\000"
1565 /* 3834 */ "G_ROTR\000"
1566 /* 3841 */ "G_INTTOPTR\000"
1567 /* 3852 */ "G_FABS\000"
1568 /* 3859 */ "G_ABS\000"
1569 /* 3865 */ "G_ABDS\000"
1570 /* 3872 */ "G_UNMERGE_VALUES\000"
1571 /* 3889 */ "G_MERGE_VALUES\000"
1572 /* 3904 */ "G_CTLS\000"
1573 /* 3911 */ "G_FACOS\000"
1574 /* 3919 */ "G_FCOS\000"
1575 /* 3926 */ "G_FSINCOS\000"
1576 /* 3936 */ "G_CONCAT_VECTORS\000"
1577 /* 3953 */ "COPY_TO_REGCLASS\000"
1578 /* 3970 */ "G_IS_FPCLASS\000"
1579 /* 3983 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1580 /* 4013 */ "G_VECTOR_COMPRESS\000"
1581 /* 4031 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1582 /* 4058 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1583 /* 4096 */ "G_TRUNC_SSAT_S\000"
1584 /* 4111 */ "G_SSUBSAT\000"
1585 /* 4121 */ "G_USUBSAT\000"
1586 /* 4131 */ "G_SADDSAT\000"
1587 /* 4141 */ "G_UADDSAT\000"
1588 /* 4151 */ "G_SSHLSAT\000"
1589 /* 4161 */ "G_USHLSAT\000"
1590 /* 4171 */ "G_SMULFIXSAT\000"
1591 /* 4184 */ "G_UMULFIXSAT\000"
1592 /* 4197 */ "G_SDIVFIXSAT\000"
1593 /* 4210 */ "G_UDIVFIXSAT\000"
1594 /* 4223 */ "G_ATOMICRMW_USUB_SAT\000"
1595 /* 4244 */ "G_FPTOSI_SAT\000"
1596 /* 4257 */ "G_FPTOUI_SAT\000"
1597 /* 4270 */ "G_EXTRACT\000"
1598 /* 4280 */ "G_SELECT\000"
1599 /* 4289 */ "G_BRINDIRECT\000"
1600 /* 4302 */ "PATCHABLE_RET\000"
1601 /* 4316 */ "FRAME_TO_ARGS_OFFSET\000"
1602 /* 4337 */ "G_MEMSET\000"
1603 /* 4346 */ "PATCHABLE_FUNCTION_EXIT\000"
1604 /* 4370 */ "G_BRJT\000"
1605 /* 4377 */ "BR_JT\000"
1606 /* 4383 */ "G_EXTRACT_VECTOR_ELT\000"
1607 /* 4404 */ "G_INSERT_VECTOR_ELT\000"
1608 /* 4424 */ "G_FCONSTANT\000"
1609 /* 4436 */ "G_CONSTANT\000"
1610 /* 4447 */ "G_INTRINSIC_CONVERGENT\000"
1611 /* 4470 */ "STATEPOINT\000"
1612 /* 4481 */ "PATCHPOINT\000"
1613 /* 4492 */ "G_PTRTOINT\000"
1614 /* 4503 */ "G_FRINT\000"
1615 /* 4511 */ "G_INTRINSIC_LLRINT\000"
1616 /* 4530 */ "G_INTRINSIC_LRINT\000"
1617 /* 4548 */ "G_FNEARBYINT\000"
1618 /* 4561 */ "NOT\000"
1619 /* 4565 */ "G_VASTART\000"
1620 /* 4575 */ "LIFETIME_START\000"
1621 /* 4590 */ "G_INVOKE_REGION_START\000"
1622 /* 4612 */ "G_INSERT\000"
1623 /* 4621 */ "G_FSQRT\000"
1624 /* 4629 */ "G_STRICT_FSQRT\000"
1625 /* 4644 */ "G_BITCAST\000"
1626 /* 4654 */ "G_ADDRSPACE_CAST\000"
1627 /* 4671 */ "DBG_VALUE_LIST\000"
1628 /* 4686 */ "G_FPEXT\000"
1629 /* 4694 */ "G_SEXT\000"
1630 /* 4701 */ "G_ASSERT_SEXT\000"
1631 /* 4715 */ "G_ANYEXT\000"
1632 /* 4724 */ "G_ZEXT\000"
1633 /* 4731 */ "G_ASSERT_ZEXT\000"
1634 /* 4745 */ "G_ABDU\000"
1635 /* 4752 */ "G_TRUNC_SSAT_U\000"
1636 /* 4767 */ "G_TRUNC_USAT_U\000"
1637 /* 4782 */ "G_FDIV\000"
1638 /* 4789 */ "G_STRICT_FDIV\000"
1639 /* 4803 */ "G_SDIV\000"
1640 /* 4810 */ "G_UDIV\000"
1641 /* 4817 */ "G_GET_FPENV\000"
1642 /* 4829 */ "G_RESET_FPENV\000"
1643 /* 4843 */ "G_SET_FPENV\000"
1644 /* 4855 */ "G_FPOW\000"
1645 /* 4862 */ "G_VECREDUCE_FMAX\000"
1646 /* 4879 */ "G_ATOMICRMW_FMAX\000"
1647 /* 4896 */ "G_VECREDUCE_SMAX\000"
1648 /* 4913 */ "G_SMAX\000"
1649 /* 4920 */ "G_VECREDUCE_UMAX\000"
1650 /* 4937 */ "G_UMAX\000"
1651 /* 4944 */ "G_ATOMICRMW_UMAX\000"
1652 /* 4961 */ "G_ATOMICRMW_MAX\000"
1653 /* 4977 */ "G_FRAME_INDEX\000"
1654 /* 4991 */ "G_SBFX\000"
1655 /* 4998 */ "G_UBFX\000"
1656 /* 5005 */ "G_SMULFIX\000"
1657 /* 5015 */ "G_UMULFIX\000"
1658 /* 5025 */ "G_SDIVFIX\000"
1659 /* 5035 */ "G_UDIVFIX\000"
1660 /* 5045 */ "G_MEMCPY\000"
1661 /* 5054 */ "COPY\000"
1662 /* 5059 */ "CONVERGENCECTRL_ENTRY\000"
1663 /* 5081 */ "G_CTLZ\000"
1664 /* 5088 */ "G_CTTZ\000"
1665 /* 5095 */ "LDAPF_lu10_ba\000"
1666 /* 5109 */ "SSYNC_0r\000"
1667 /* 5118 */ "BLA_1r\000"
1668 /* 5125 */ "MSYNC_1r\000"
1669 /* 5134 */ "ECALLF_1r\000"
1670 /* 5144 */ "DGETREG_1r\000"
1671 /* 5155 */ "KCALL_1r\000"
1672 /* 5164 */ "MJOIN_1r\000"
1673 /* 5173 */ "SETCP_1r\000"
1674 /* 5182 */ "SETDP_1r\000"
1675 /* 5191 */ "SETSP_1r\000"
1676 /* 5200 */ "SYNCR_1r\000"
1677 /* 5209 */ "FREER_1r\000"
1678 /* 5218 */ "ECALLT_1r\000"
1679 /* 5228 */ "BAU_1r\000"
1680 /* 5235 */ "EDU_1r\000"
1681 /* 5242 */ "EEU_1r\000"
1682 /* 5249 */ "BRU_1r\000"
1683 /* 5256 */ "SETEV_1r\000"
1684 /* 5265 */ "SETV_1r\000"
1685 /* 5273 */ "INITPC_2r\000"
1686 /* 5283 */ "SETPSC_2r\000"
1687 /* 5293 */ "SETD_2r\000"
1688 /* 5301 */ "EEF_2r\000"
1689 /* 5308 */ "PEEK_2r\000"
1690 /* 5316 */ "MKMSK_2r\000"
1691 /* 5325 */ "ENDIN_2r\000"
1692 /* 5334 */ "INITCP_2r\000"
1693 /* 5344 */ "INITDP_2r\000"
1694 /* 5354 */ "INITSP_2r\000"
1695 /* 5364 */ "INSHR_2r\000"
1696 /* 5373 */ "OUTSHR_2r\000"
1697 /* 5383 */ "TSETMR_2r\000"
1698 /* 5393 */ "GETTS_2r\000"
1699 /* 5402 */ "CHKCT_2r\000"
1700 /* 5411 */ "INCT_2r\000"
1701 /* 5419 */ "TESTCT_2r\000"
1702 /* 5429 */ "OUTCT_2r\000"
1703 /* 5438 */ "TESTWCT_2r\000"
1704 /* 5449 */ "EET_2r\000"
1705 /* 5456 */ "INT_2r\000"
1706 /* 5463 */ "ANDNOT_2r\000"
1707 /* 5473 */ "SETPT_2r\000"
1708 /* 5482 */ "GETST_2r\000"
1709 /* 5491 */ "OUTT_2r\000"
1710 /* 5499 */ "OUT_2r\000"
1711 /* 5506 */ "SEXT_2r\000"
1712 /* 5514 */ "ZEXT_2r\000"
1713 /* 5522 */ "SETC_l2r\000"
1714 /* 5531 */ "GETD_l2r\000"
1715 /* 5540 */ "SETCLK_l2r\000"
1716 /* 5551 */ "TESTLCL_l2r\000"
1717 /* 5563 */ "GETN_l2r\000"
1718 /* 5572 */ "SETN_l2r\000"
1719 /* 5581 */ "INITLR_l2r\000"
1720 /* 5592 */ "GETPS_l2r\000"
1721 /* 5602 */ "SETPS_l2r\000"
1722 /* 5612 */ "BYTEREV_l2r\000"
1723 /* 5624 */ "BITREV_l2r\000"
1724 /* 5635 */ "SETTW_l2r\000"
1725 /* 5645 */ "SETRDY_l2r\000"
1726 /* 5656 */ "CLZ_l2r\000"
1727 /* 5664 */ "SUB_3r\000"
1728 /* 5671 */ "ADD_3r\000"
1729 /* 5678 */ "AND_3r\000"
1730 /* 5685 */ "SHL_3r\000"
1731 /* 5692 */ "EQ_3r\000"
1732 /* 5698 */ "SHR_3r\000"
1733 /* 5705 */ "OR_3r\000"
1734 /* 5711 */ "TSETR_3r\000"
1735 /* 5720 */ "LD16S_3r\000"
1736 /* 5729 */ "LSS_3r\000"
1737 /* 5736 */ "LD8U_3r\000"
1738 /* 5744 */ "LSU_3r\000"
1739 /* 5751 */ "LDW_3r\000"
1740 /* 5758 */ "ST16_l3r\000"
1741 /* 5767 */ "ST8_l3r\000"
1742 /* 5775 */ "LDA16B_l3r\000"
1743 /* 5786 */ "LDAWB_l3r\000"
1744 /* 5796 */ "CRC_l3r\000"
1745 /* 5804 */ "LDA16F_l3r\000"
1746 /* 5815 */ "LDAWF_l3r\000"
1747 /* 5825 */ "MUL_l3r\000"
1748 /* 5833 */ "ASHR_l3r\000"
1749 /* 5842 */ "XOR_l3r\000"
1750 /* 5850 */ "REMS_l3r\000"
1751 /* 5859 */ "DIVS_l3r\000"
1752 /* 5868 */ "REMU_l3r\000"
1753 /* 5877 */ "DIVU_l3r\000"
1754 /* 5886 */ "STW_l3r\000"
1755 /* 5894 */ "CRC8_l4r\000"
1756 /* 5903 */ "MACCS_l4r\000"
1757 /* 5913 */ "MACCU_l4r\000"
1758 /* 5923 */ "LSUB_l5r\000"
1759 /* 5932 */ "LADD_l5r\000"
1760 /* 5941 */ "LDIVU_l5r\000"
1761 /* 5951 */ "LMUL_l6r\000"
1762 /* 5960 */ "SUB_2rus\000"
1763 /* 5969 */ "ADD_2rus\000"
1764 /* 5978 */ "SHL_2rus\000"
1765 /* 5987 */ "EQ_2rus\000"
1766 /* 5995 */ "SHR_2rus\000"
1767 /* 6004 */ "LDW_2rus\000"
1768 /* 6013 */ "STW_2rus\000"
1769 /* 6022 */ "LDAWB_l2rus\000"
1770 /* 6034 */ "LDAWF_l2rus\000"
1771 /* 6046 */ "ASHR_l2rus\000"
1772 /* 6057 */ "INPW_l2rus\000"
1773 /* 6068 */ "OUTPW_l2rus\000"
1774 /* 6080 */ "MKMSK_rus\000"
1775 /* 6090 */ "GETR_rus\000"
1776 /* 6099 */ "CHKCT_rus\000"
1777 /* 6109 */ "OUTCT_rus\000"
1778 /* 6119 */ "SEXT_rus\000"
1779 /* 6128 */ "ZEXT_rus\000"
1780};
1781#ifdef __GNUC__
1782#pragma GCC diagnostic pop
1783#endif
1784
1785extern const unsigned XCoreInstrNameIndices[] = {
1786 2030U, 2436U, 3426U, 2794U, 2103U, 2084U, 2112U, 2272U,
1787 1804U, 1819U, 1770U, 1757U, 1846U, 3953U, 1597U, 4671U,
1788 1783U, 2026U, 2093U, 1367U, 5054U, 2060U, 1489U, 4575U,
1789 1194U, 1318U, 1355U, 2915U, 2260U, 4481U, 1301U, 3122U,
1790 1939U, 4470U, 1523U, 3095U, 3082U, 3487U, 4302U, 4346U,
1791 2192U, 2239U, 2212U, 2129U, 1588U, 3452U, 2869U, 1512U,
1792 5059U, 3605U, 3053U, 1645U, 4701U, 4731U, 2637U, 1107U,
1793 808U, 2375U, 4803U, 4810U, 2402U, 2409U, 2416U, 2426U,
1794 1172U, 3814U, 3777U, 3865U, 4745U, 3649U, 2181U, 3637U,
1795 2170U, 1768U, 2028U, 4977U, 1607U, 1622U, 2277U, 4270U,
1796 3872U, 4612U, 3889U, 3700U, 888U, 3936U, 4492U, 3841U,
1797 4644U, 1688U, 3463U, 1275U, 862U, 1257U, 4530U, 4511U,
1798 2615U, 3512U, 3531U, 1008U, 952U, 982U, 993U, 933U,
1799 963U, 1567U, 1551U, 3983U, 1860U, 1877U, 1123U, 814U,
1800 1178U, 1139U, 3819U, 3783U, 4961U, 2763U, 4944U, 2746U,
1801 1074U, 791U, 4879U, 2681U, 2531U, 2478U, 2977U, 2955U,
1802 1216U, 4223U, 1347U, 1956U, 1207U, 4289U, 4590U, 840U,
1803 4031U, 4447U, 4058U, 4715U, 880U, 4096U, 4752U, 4767U,
1804 4436U, 4424U, 4565U, 1931U, 4694U, 1833U, 4724U, 2156U,
1805 3598U, 3584U, 2149U, 3591U, 3834U, 2293U, 3032U, 3025U,
1806 3039U, 3046U, 4280U, 2861U, 1388U, 2845U, 1339U, 2853U,
1807 1380U, 2837U, 1331U, 2899U, 2891U, 1975U, 1967U, 4141U,
1808 4131U, 4121U, 4111U, 4161U, 4151U, 5005U, 5015U, 4171U,
1809 4184U, 5025U, 5035U, 4197U, 4210U, 1032U, 770U, 2317U,
1810 751U, 926U, 4782U, 2381U, 1713U, 4855U, 2052U, 3166U,
1811 165U, 9U, 1924U, 148U, 0U, 3141U, 3173U, 1797U,
1812 4686U, 852U, 2034U, 2043U, 3007U, 3016U, 4244U, 4257U,
1813 3852U, 2652U, 3970U, 1697U, 2580U, 2590U, 1437U, 1452U,
1814 2467U, 2520U, 2552U, 2566U, 4817U, 4843U, 4829U, 1396U,
1815 1424U, 1409U, 1894U, 1909U, 1113U, 2074U, 2715U, 4913U,
1816 2739U, 4937U, 3859U, 1248U, 1238U, 3421U, 4370U, 1467U,
1817 3681U, 3661U, 4404U, 4383U, 3715U, 3746U, 3732U, 4013U,
1818 5088U, 1739U, 5081U, 1721U, 3904U, 3074U, 2999U, 1575U,
1819 2162U, 3919U, 2787U, 3926U, 2608U, 3911U, 2779U, 2600U,
1820 156U, 1999U, 1991U, 1983U, 4621U, 3628U, 4503U, 4548U,
1821 4654U, 3439U, 1476U, 909U, 1666U, 1536U, 1060U, 777U,
1822 2345U, 4789U, 2388U, 757U, 4629U, 3150U, 3551U, 3567U,
1823 5045U, 1496U, 1678U, 4337U, 2907U, 2948U, 2924U, 2936U,
1824 1039U, 2324U, 1015U, 2300U, 4862U, 2664U, 2499U, 2446U,
1825 1091U, 2359U, 1156U, 3799U, 3761U, 4896U, 2698U, 4920U,
1826 2722U, 4991U, 4998U, 2820U, 3107U, 4377U, 140U, 2810U,
1827 4316U, 2007U, 2014U, 830U, 2020U, 5969U, 5671U, 5463U,
1828 5678U, 6046U, 5833U, 5228U, 5624U, 118U, 56U, 427U,
1829 267U, 5118U, 87U, 28U, 108U, 47U, 632U, 505U,
1830 731U, 595U, 436U, 275U, 642U, 514U, 741U, 604U,
1831 445U, 283U, 5249U, 5612U, 5402U, 6099U, 3236U, 3402U,
1832 454U, 291U, 397U, 240U, 5656U, 5894U, 5796U, 3244U,
1833 3283U, 5144U, 5859U, 5877U, 3293U, 3339U, 5134U, 5218U,
1834 5235U, 5301U, 5449U, 5242U, 5325U, 365U, 211U, 5987U,
1835 5692U, 344U, 192U, 387U, 231U, 5209U, 3330U, 5531U,
1836 3218U, 3355U, 3227U, 3253U, 3273U, 5563U, 5592U, 6090U,
1837 407U, 249U, 5482U, 5393U, 5411U, 5334U, 5344U, 5581U,
1838 5273U, 5354U, 6057U, 5364U, 5456U, 5328U, 5155U, 323U,
1839 173U, 364U, 210U, 375U, 220U, 3347U, 5932U, 5720U,
1840 5736U, 5775U, 5804U, 76U, 18U, 97U, 5095U, 37U,
1841 6022U, 5786U, 333U, 182U, 663U, 533U, 6034U, 5815U,
1842 697U, 564U, 613U, 488U, 3322U, 5941U, 3200U, 3182U,
1843 3304U, 652U, 129U, 523U, 66U, 675U, 544U, 709U,
1844 575U, 6004U, 5751U, 5951U, 5729U, 5923U, 5744U, 5903U,
1845 5913U, 5164U, 5316U, 6080U, 5125U, 5825U, 1800U, 4561U,
1846 5705U, 5429U, 6109U, 6068U, 5373U, 5491U, 5499U, 5308U,
1847 5850U, 5868U, 354U, 201U, 5540U, 5173U, 5522U, 622U,
1848 496U, 5182U, 5293U, 5256U, 3263U, 5572U, 5283U, 5602U,
1849 5473U, 5645U, 5191U, 471U, 307U, 417U, 258U, 5635U,
1850 5265U, 5506U, 6119U, 5978U, 5685U, 5995U, 5698U, 5109U,
1851 5758U, 5767U, 3364U, 3209U, 3191U, 3313U, 686U, 554U,
1852 720U, 585U, 6013U, 5886U, 5960U, 5664U, 5200U, 5419U,
1853 5551U, 5438U, 5383U, 5711U, 3411U, 3382U, 3392U, 3372U,
1854 5842U, 5514U, 6128U,
1855};
1856
1857static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1858 II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 547, nullptr, 0);
1859}
1860
1861
1862} // namespace llvm
1863
1864#endif // GET_INSTRINFO_MC_DESC
1865
1866#ifdef GET_INSTRINFO_HEADER
1867#undef GET_INSTRINFO_HEADER
1868
1869namespace llvm {
1870
1871struct XCoreGenInstrInfo : public TargetInstrInfo {
1872 explicit XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1873 ~XCoreGenInstrInfo() override = default;
1874};
1875
1876} // namespace llvm
1877
1878namespace llvm::XCore {
1879
1880
1881} // namespace llvm::XCore
1882
1883#endif // GET_INSTRINFO_HEADER
1884
1885#ifdef GET_INSTRINFO_HELPER_DECLS
1886#undef GET_INSTRINFO_HELPER_DECLS
1887
1888
1889#endif // GET_INSTRINFO_HELPER_DECLS
1890
1891#ifdef GET_INSTRINFO_HELPERS
1892#undef GET_INSTRINFO_HELPERS
1893
1894
1895#endif // GET_INSTRINFO_HELPERS
1896
1897#ifdef GET_INSTRINFO_CTOR_DTOR
1898#undef GET_INSTRINFO_CTOR_DTOR
1899
1900namespace llvm {
1901
1902extern const XCoreInstrTable XCoreDescs;
1903extern const unsigned XCoreInstrNameIndices[];
1904extern const char XCoreInstrNameData[];
1905XCoreGenInstrInfo::XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1906 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1907 InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 547);
1908}
1909
1910} // namespace llvm
1911
1912#endif // GET_INSTRINFO_CTOR_DTOR
1913
1914#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1915#undef GET_INSTRINFO_MC_HELPER_DECLS
1916
1917namespace llvm {
1918
1919class MCInst;
1920class FeatureBitset;
1921
1922namespace XCore_MC {
1923
1924void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1925
1926} // namespace XCore_MC
1927
1928} // namespace llvm
1929
1930#endif // GET_INSTRINFO_MC_HELPER_DECLS
1931
1932#ifdef GET_INSTRINFO_MC_HELPERS
1933#undef GET_INSTRINFO_MC_HELPERS
1934
1935namespace llvm::XCore_MC {
1936
1937
1938} // namespace llvm::XCore_MC
1939
1940#endif // GET_INSTRINFO_MC_HELPERS
1941
1942#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1943 defined(GET_AVAILABLE_OPCODE_CHECKER)
1944#define GET_COMPUTE_FEATURES
1945#endif
1946#ifdef GET_COMPUTE_FEATURES
1947#undef GET_COMPUTE_FEATURES
1948
1949namespace llvm::XCore_MC {
1950
1951// Bits for subtarget features that participate in instruction matching.
1952enum SubtargetFeatureBits : uint8_t {
1953};
1954
1955inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1956 FeatureBitset Features;
1957 return Features;
1958}
1959
1960inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1961 enum : uint8_t {
1962 CEFBS_None,
1963 };
1964
1965 static constexpr FeatureBitset FeatureBitsets[] = {
1966 {}, // CEFBS_None
1967 };
1968 static constexpr uint8_t RequiredFeaturesRefs[] = {
1969 CEFBS_None, // PHI
1970 CEFBS_None, // INLINEASM
1971 CEFBS_None, // INLINEASM_BR
1972 CEFBS_None, // CFI_INSTRUCTION
1973 CEFBS_None, // EH_LABEL
1974 CEFBS_None, // GC_LABEL
1975 CEFBS_None, // ANNOTATION_LABEL
1976 CEFBS_None, // KILL
1977 CEFBS_None, // EXTRACT_SUBREG
1978 CEFBS_None, // INSERT_SUBREG
1979 CEFBS_None, // IMPLICIT_DEF
1980 CEFBS_None, // INIT_UNDEF
1981 CEFBS_None, // SUBREG_TO_REG
1982 CEFBS_None, // COPY_TO_REGCLASS
1983 CEFBS_None, // DBG_VALUE
1984 CEFBS_None, // DBG_VALUE_LIST
1985 CEFBS_None, // DBG_INSTR_REF
1986 CEFBS_None, // DBG_PHI
1987 CEFBS_None, // DBG_LABEL
1988 CEFBS_None, // REG_SEQUENCE
1989 CEFBS_None, // COPY
1990 CEFBS_None, // COPY_LANEMASK
1991 CEFBS_None, // BUNDLE
1992 CEFBS_None, // LIFETIME_START
1993 CEFBS_None, // LIFETIME_END
1994 CEFBS_None, // PSEUDO_PROBE
1995 CEFBS_None, // ARITH_FENCE
1996 CEFBS_None, // STACKMAP
1997 CEFBS_None, // FENTRY_CALL
1998 CEFBS_None, // PATCHPOINT
1999 CEFBS_None, // LOAD_STACK_GUARD
2000 CEFBS_None, // PREALLOCATED_SETUP
2001 CEFBS_None, // PREALLOCATED_ARG
2002 CEFBS_None, // STATEPOINT
2003 CEFBS_None, // LOCAL_ESCAPE
2004 CEFBS_None, // FAULTING_OP
2005 CEFBS_None, // PATCHABLE_OP
2006 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2007 CEFBS_None, // PATCHABLE_RET
2008 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2009 CEFBS_None, // PATCHABLE_TAIL_CALL
2010 CEFBS_None, // PATCHABLE_EVENT_CALL
2011 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2012 CEFBS_None, // ICALL_BRANCH_FUNNEL
2013 CEFBS_None, // FAKE_USE
2014 CEFBS_None, // MEMBARRIER
2015 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2016 CEFBS_None, // RELOC_NONE
2017 CEFBS_None, // CONVERGENCECTRL_ENTRY
2018 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2019 CEFBS_None, // CONVERGENCECTRL_LOOP
2020 CEFBS_None, // CONVERGENCECTRL_GLUE
2021 CEFBS_None, // G_ASSERT_SEXT
2022 CEFBS_None, // G_ASSERT_ZEXT
2023 CEFBS_None, // G_ASSERT_ALIGN
2024 CEFBS_None, // G_ADD
2025 CEFBS_None, // G_SUB
2026 CEFBS_None, // G_MUL
2027 CEFBS_None, // G_SDIV
2028 CEFBS_None, // G_UDIV
2029 CEFBS_None, // G_SREM
2030 CEFBS_None, // G_UREM
2031 CEFBS_None, // G_SDIVREM
2032 CEFBS_None, // G_UDIVREM
2033 CEFBS_None, // G_AND
2034 CEFBS_None, // G_OR
2035 CEFBS_None, // G_XOR
2036 CEFBS_None, // G_ABDS
2037 CEFBS_None, // G_ABDU
2038 CEFBS_None, // G_UAVGFLOOR
2039 CEFBS_None, // G_UAVGCEIL
2040 CEFBS_None, // G_SAVGFLOOR
2041 CEFBS_None, // G_SAVGCEIL
2042 CEFBS_None, // G_IMPLICIT_DEF
2043 CEFBS_None, // G_PHI
2044 CEFBS_None, // G_FRAME_INDEX
2045 CEFBS_None, // G_GLOBAL_VALUE
2046 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2047 CEFBS_None, // G_CONSTANT_POOL
2048 CEFBS_None, // G_EXTRACT
2049 CEFBS_None, // G_UNMERGE_VALUES
2050 CEFBS_None, // G_INSERT
2051 CEFBS_None, // G_MERGE_VALUES
2052 CEFBS_None, // G_BUILD_VECTOR
2053 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2054 CEFBS_None, // G_CONCAT_VECTORS
2055 CEFBS_None, // G_PTRTOINT
2056 CEFBS_None, // G_INTTOPTR
2057 CEFBS_None, // G_BITCAST
2058 CEFBS_None, // G_FREEZE
2059 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2060 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2061 CEFBS_None, // G_INTRINSIC_TRUNC
2062 CEFBS_None, // G_INTRINSIC_ROUND
2063 CEFBS_None, // G_INTRINSIC_LRINT
2064 CEFBS_None, // G_INTRINSIC_LLRINT
2065 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2066 CEFBS_None, // G_READCYCLECOUNTER
2067 CEFBS_None, // G_READSTEADYCOUNTER
2068 CEFBS_None, // G_LOAD
2069 CEFBS_None, // G_SEXTLOAD
2070 CEFBS_None, // G_ZEXTLOAD
2071 CEFBS_None, // G_INDEXED_LOAD
2072 CEFBS_None, // G_INDEXED_SEXTLOAD
2073 CEFBS_None, // G_INDEXED_ZEXTLOAD
2074 CEFBS_None, // G_STORE
2075 CEFBS_None, // G_INDEXED_STORE
2076 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2077 CEFBS_None, // G_ATOMIC_CMPXCHG
2078 CEFBS_None, // G_ATOMICRMW_XCHG
2079 CEFBS_None, // G_ATOMICRMW_ADD
2080 CEFBS_None, // G_ATOMICRMW_SUB
2081 CEFBS_None, // G_ATOMICRMW_AND
2082 CEFBS_None, // G_ATOMICRMW_NAND
2083 CEFBS_None, // G_ATOMICRMW_OR
2084 CEFBS_None, // G_ATOMICRMW_XOR
2085 CEFBS_None, // G_ATOMICRMW_MAX
2086 CEFBS_None, // G_ATOMICRMW_MIN
2087 CEFBS_None, // G_ATOMICRMW_UMAX
2088 CEFBS_None, // G_ATOMICRMW_UMIN
2089 CEFBS_None, // G_ATOMICRMW_FADD
2090 CEFBS_None, // G_ATOMICRMW_FSUB
2091 CEFBS_None, // G_ATOMICRMW_FMAX
2092 CEFBS_None, // G_ATOMICRMW_FMIN
2093 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2094 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2095 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2096 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2097 CEFBS_None, // G_ATOMICRMW_USUB_COND
2098 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2099 CEFBS_None, // G_FENCE
2100 CEFBS_None, // G_PREFETCH
2101 CEFBS_None, // G_BRCOND
2102 CEFBS_None, // G_BRINDIRECT
2103 CEFBS_None, // G_INVOKE_REGION_START
2104 CEFBS_None, // G_INTRINSIC
2105 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2106 CEFBS_None, // G_INTRINSIC_CONVERGENT
2107 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2108 CEFBS_None, // G_ANYEXT
2109 CEFBS_None, // G_TRUNC
2110 CEFBS_None, // G_TRUNC_SSAT_S
2111 CEFBS_None, // G_TRUNC_SSAT_U
2112 CEFBS_None, // G_TRUNC_USAT_U
2113 CEFBS_None, // G_CONSTANT
2114 CEFBS_None, // G_FCONSTANT
2115 CEFBS_None, // G_VASTART
2116 CEFBS_None, // G_VAARG
2117 CEFBS_None, // G_SEXT
2118 CEFBS_None, // G_SEXT_INREG
2119 CEFBS_None, // G_ZEXT
2120 CEFBS_None, // G_SHL
2121 CEFBS_None, // G_LSHR
2122 CEFBS_None, // G_ASHR
2123 CEFBS_None, // G_FSHL
2124 CEFBS_None, // G_FSHR
2125 CEFBS_None, // G_ROTR
2126 CEFBS_None, // G_ROTL
2127 CEFBS_None, // G_ICMP
2128 CEFBS_None, // G_FCMP
2129 CEFBS_None, // G_SCMP
2130 CEFBS_None, // G_UCMP
2131 CEFBS_None, // G_SELECT
2132 CEFBS_None, // G_UADDO
2133 CEFBS_None, // G_UADDE
2134 CEFBS_None, // G_USUBO
2135 CEFBS_None, // G_USUBE
2136 CEFBS_None, // G_SADDO
2137 CEFBS_None, // G_SADDE
2138 CEFBS_None, // G_SSUBO
2139 CEFBS_None, // G_SSUBE
2140 CEFBS_None, // G_UMULO
2141 CEFBS_None, // G_SMULO
2142 CEFBS_None, // G_UMULH
2143 CEFBS_None, // G_SMULH
2144 CEFBS_None, // G_UADDSAT
2145 CEFBS_None, // G_SADDSAT
2146 CEFBS_None, // G_USUBSAT
2147 CEFBS_None, // G_SSUBSAT
2148 CEFBS_None, // G_USHLSAT
2149 CEFBS_None, // G_SSHLSAT
2150 CEFBS_None, // G_SMULFIX
2151 CEFBS_None, // G_UMULFIX
2152 CEFBS_None, // G_SMULFIXSAT
2153 CEFBS_None, // G_UMULFIXSAT
2154 CEFBS_None, // G_SDIVFIX
2155 CEFBS_None, // G_UDIVFIX
2156 CEFBS_None, // G_SDIVFIXSAT
2157 CEFBS_None, // G_UDIVFIXSAT
2158 CEFBS_None, // G_FADD
2159 CEFBS_None, // G_FSUB
2160 CEFBS_None, // G_FMUL
2161 CEFBS_None, // G_FMA
2162 CEFBS_None, // G_FMAD
2163 CEFBS_None, // G_FDIV
2164 CEFBS_None, // G_FREM
2165 CEFBS_None, // G_FMODF
2166 CEFBS_None, // G_FPOW
2167 CEFBS_None, // G_FPOWI
2168 CEFBS_None, // G_FEXP
2169 CEFBS_None, // G_FEXP2
2170 CEFBS_None, // G_FEXP10
2171 CEFBS_None, // G_FLOG
2172 CEFBS_None, // G_FLOG2
2173 CEFBS_None, // G_FLOG10
2174 CEFBS_None, // G_FLDEXP
2175 CEFBS_None, // G_FFREXP
2176 CEFBS_None, // G_FNEG
2177 CEFBS_None, // G_FPEXT
2178 CEFBS_None, // G_FPTRUNC
2179 CEFBS_None, // G_FPTOSI
2180 CEFBS_None, // G_FPTOUI
2181 CEFBS_None, // G_SITOFP
2182 CEFBS_None, // G_UITOFP
2183 CEFBS_None, // G_FPTOSI_SAT
2184 CEFBS_None, // G_FPTOUI_SAT
2185 CEFBS_None, // G_FABS
2186 CEFBS_None, // G_FCOPYSIGN
2187 CEFBS_None, // G_IS_FPCLASS
2188 CEFBS_None, // G_FCANONICALIZE
2189 CEFBS_None, // G_FMINNUM
2190 CEFBS_None, // G_FMAXNUM
2191 CEFBS_None, // G_FMINNUM_IEEE
2192 CEFBS_None, // G_FMAXNUM_IEEE
2193 CEFBS_None, // G_FMINIMUM
2194 CEFBS_None, // G_FMAXIMUM
2195 CEFBS_None, // G_FMINIMUMNUM
2196 CEFBS_None, // G_FMAXIMUMNUM
2197 CEFBS_None, // G_GET_FPENV
2198 CEFBS_None, // G_SET_FPENV
2199 CEFBS_None, // G_RESET_FPENV
2200 CEFBS_None, // G_GET_FPMODE
2201 CEFBS_None, // G_SET_FPMODE
2202 CEFBS_None, // G_RESET_FPMODE
2203 CEFBS_None, // G_GET_ROUNDING
2204 CEFBS_None, // G_SET_ROUNDING
2205 CEFBS_None, // G_PTR_ADD
2206 CEFBS_None, // G_PTRMASK
2207 CEFBS_None, // G_SMIN
2208 CEFBS_None, // G_SMAX
2209 CEFBS_None, // G_UMIN
2210 CEFBS_None, // G_UMAX
2211 CEFBS_None, // G_ABS
2212 CEFBS_None, // G_LROUND
2213 CEFBS_None, // G_LLROUND
2214 CEFBS_None, // G_BR
2215 CEFBS_None, // G_BRJT
2216 CEFBS_None, // G_VSCALE
2217 CEFBS_None, // G_INSERT_SUBVECTOR
2218 CEFBS_None, // G_EXTRACT_SUBVECTOR
2219 CEFBS_None, // G_INSERT_VECTOR_ELT
2220 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2221 CEFBS_None, // G_SHUFFLE_VECTOR
2222 CEFBS_None, // G_SPLAT_VECTOR
2223 CEFBS_None, // G_STEP_VECTOR
2224 CEFBS_None, // G_VECTOR_COMPRESS
2225 CEFBS_None, // G_CTTZ
2226 CEFBS_None, // G_CTTZ_ZERO_UNDEF
2227 CEFBS_None, // G_CTLZ
2228 CEFBS_None, // G_CTLZ_ZERO_UNDEF
2229 CEFBS_None, // G_CTLS
2230 CEFBS_None, // G_CTPOP
2231 CEFBS_None, // G_BSWAP
2232 CEFBS_None, // G_BITREVERSE
2233 CEFBS_None, // G_FCEIL
2234 CEFBS_None, // G_FCOS
2235 CEFBS_None, // G_FSIN
2236 CEFBS_None, // G_FSINCOS
2237 CEFBS_None, // G_FTAN
2238 CEFBS_None, // G_FACOS
2239 CEFBS_None, // G_FASIN
2240 CEFBS_None, // G_FATAN
2241 CEFBS_None, // G_FATAN2
2242 CEFBS_None, // G_FCOSH
2243 CEFBS_None, // G_FSINH
2244 CEFBS_None, // G_FTANH
2245 CEFBS_None, // G_FSQRT
2246 CEFBS_None, // G_FFLOOR
2247 CEFBS_None, // G_FRINT
2248 CEFBS_None, // G_FNEARBYINT
2249 CEFBS_None, // G_ADDRSPACE_CAST
2250 CEFBS_None, // G_BLOCK_ADDR
2251 CEFBS_None, // G_JUMP_TABLE
2252 CEFBS_None, // G_DYN_STACKALLOC
2253 CEFBS_None, // G_STACKSAVE
2254 CEFBS_None, // G_STACKRESTORE
2255 CEFBS_None, // G_STRICT_FADD
2256 CEFBS_None, // G_STRICT_FSUB
2257 CEFBS_None, // G_STRICT_FMUL
2258 CEFBS_None, // G_STRICT_FDIV
2259 CEFBS_None, // G_STRICT_FREM
2260 CEFBS_None, // G_STRICT_FMA
2261 CEFBS_None, // G_STRICT_FSQRT
2262 CEFBS_None, // G_STRICT_FLDEXP
2263 CEFBS_None, // G_READ_REGISTER
2264 CEFBS_None, // G_WRITE_REGISTER
2265 CEFBS_None, // G_MEMCPY
2266 CEFBS_None, // G_MEMCPY_INLINE
2267 CEFBS_None, // G_MEMMOVE
2268 CEFBS_None, // G_MEMSET
2269 CEFBS_None, // G_BZERO
2270 CEFBS_None, // G_TRAP
2271 CEFBS_None, // G_DEBUGTRAP
2272 CEFBS_None, // G_UBSANTRAP
2273 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2274 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2275 CEFBS_None, // G_VECREDUCE_FADD
2276 CEFBS_None, // G_VECREDUCE_FMUL
2277 CEFBS_None, // G_VECREDUCE_FMAX
2278 CEFBS_None, // G_VECREDUCE_FMIN
2279 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2280 CEFBS_None, // G_VECREDUCE_FMINIMUM
2281 CEFBS_None, // G_VECREDUCE_ADD
2282 CEFBS_None, // G_VECREDUCE_MUL
2283 CEFBS_None, // G_VECREDUCE_AND
2284 CEFBS_None, // G_VECREDUCE_OR
2285 CEFBS_None, // G_VECREDUCE_XOR
2286 CEFBS_None, // G_VECREDUCE_SMAX
2287 CEFBS_None, // G_VECREDUCE_SMIN
2288 CEFBS_None, // G_VECREDUCE_UMAX
2289 CEFBS_None, // G_VECREDUCE_UMIN
2290 CEFBS_None, // G_SBFX
2291 CEFBS_None, // G_UBFX
2292 CEFBS_None, // ADJCALLSTACKDOWN
2293 CEFBS_None, // ADJCALLSTACKUP
2294 CEFBS_None, // BR_JT
2295 CEFBS_None, // BR_JT32
2296 CEFBS_None, // EH_RETURN
2297 CEFBS_None, // FRAME_TO_ARGS_OFFSET
2298 CEFBS_None, // LDAWFI
2299 CEFBS_None, // LDWFI
2300 CEFBS_None, // SELECT_CC
2301 CEFBS_None, // STWFI
2302 CEFBS_None, // ADD_2rus
2303 CEFBS_None, // ADD_3r
2304 CEFBS_None, // ANDNOT_2r
2305 CEFBS_None, // AND_3r
2306 CEFBS_None, // ASHR_l2rus
2307 CEFBS_None, // ASHR_l3r
2308 CEFBS_None, // BAU_1r
2309 CEFBS_None, // BITREV_l2r
2310 CEFBS_None, // BLACP_lu10
2311 CEFBS_None, // BLACP_u10
2312 CEFBS_None, // BLAT_lu6
2313 CEFBS_None, // BLAT_u6
2314 CEFBS_None, // BLA_1r
2315 CEFBS_None, // BLRB_lu10
2316 CEFBS_None, // BLRB_u10
2317 CEFBS_None, // BLRF_lu10
2318 CEFBS_None, // BLRF_u10
2319 CEFBS_None, // BRBF_lru6
2320 CEFBS_None, // BRBF_ru6
2321 CEFBS_None, // BRBT_lru6
2322 CEFBS_None, // BRBT_ru6
2323 CEFBS_None, // BRBU_lu6
2324 CEFBS_None, // BRBU_u6
2325 CEFBS_None, // BRFF_lru6
2326 CEFBS_None, // BRFF_ru6
2327 CEFBS_None, // BRFT_lru6
2328 CEFBS_None, // BRFT_ru6
2329 CEFBS_None, // BRFU_lu6
2330 CEFBS_None, // BRFU_u6
2331 CEFBS_None, // BRU_1r
2332 CEFBS_None, // BYTEREV_l2r
2333 CEFBS_None, // CHKCT_2r
2334 CEFBS_None, // CHKCT_rus
2335 CEFBS_None, // CLRE_0R
2336 CEFBS_None, // CLRPT_1R
2337 CEFBS_None, // CLRSR_branch_lu6
2338 CEFBS_None, // CLRSR_branch_u6
2339 CEFBS_None, // CLRSR_lu6
2340 CEFBS_None, // CLRSR_u6
2341 CEFBS_None, // CLZ_l2r
2342 CEFBS_None, // CRC8_l4r
2343 CEFBS_None, // CRC_l3r
2344 CEFBS_None, // DCALL_0R
2345 CEFBS_None, // DENTSP_0R
2346 CEFBS_None, // DGETREG_1r
2347 CEFBS_None, // DIVS_l3r
2348 CEFBS_None, // DIVU_l3r
2349 CEFBS_None, // DRESTSP_0R
2350 CEFBS_None, // DRET_0R
2351 CEFBS_None, // ECALLF_1r
2352 CEFBS_None, // ECALLT_1r
2353 CEFBS_None, // EDU_1r
2354 CEFBS_None, // EEF_2r
2355 CEFBS_None, // EET_2r
2356 CEFBS_None, // EEU_1r
2357 CEFBS_None, // ENDIN_2r
2358 CEFBS_None, // ENTSP_lu6
2359 CEFBS_None, // ENTSP_u6
2360 CEFBS_None, // EQ_2rus
2361 CEFBS_None, // EQ_3r
2362 CEFBS_None, // EXTDP_lu6
2363 CEFBS_None, // EXTDP_u6
2364 CEFBS_None, // EXTSP_lu6
2365 CEFBS_None, // EXTSP_u6
2366 CEFBS_None, // FREER_1r
2367 CEFBS_None, // FREET_0R
2368 CEFBS_None, // GETD_l2r
2369 CEFBS_None, // GETED_0R
2370 CEFBS_None, // GETET_0R
2371 CEFBS_None, // GETID_0R
2372 CEFBS_None, // GETKEP_0R
2373 CEFBS_None, // GETKSP_0R
2374 CEFBS_None, // GETN_l2r
2375 CEFBS_None, // GETPS_l2r
2376 CEFBS_None, // GETR_rus
2377 CEFBS_None, // GETSR_lu6
2378 CEFBS_None, // GETSR_u6
2379 CEFBS_None, // GETST_2r
2380 CEFBS_None, // GETTS_2r
2381 CEFBS_None, // INCT_2r
2382 CEFBS_None, // INITCP_2r
2383 CEFBS_None, // INITDP_2r
2384 CEFBS_None, // INITLR_l2r
2385 CEFBS_None, // INITPC_2r
2386 CEFBS_None, // INITSP_2r
2387 CEFBS_None, // INPW_l2rus
2388 CEFBS_None, // INSHR_2r
2389 CEFBS_None, // INT_2r
2390 CEFBS_None, // IN_2r
2391 CEFBS_None, // KCALL_1r
2392 CEFBS_None, // KCALL_lu6
2393 CEFBS_None, // KCALL_u6
2394 CEFBS_None, // KENTSP_lu6
2395 CEFBS_None, // KENTSP_u6
2396 CEFBS_None, // KRESTSP_lu6
2397 CEFBS_None, // KRESTSP_u6
2398 CEFBS_None, // KRET_0R
2399 CEFBS_None, // LADD_l5r
2400 CEFBS_None, // LD16S_3r
2401 CEFBS_None, // LD8U_3r
2402 CEFBS_None, // LDA16B_l3r
2403 CEFBS_None, // LDA16F_l3r
2404 CEFBS_None, // LDAPB_lu10
2405 CEFBS_None, // LDAPB_u10
2406 CEFBS_None, // LDAPF_lu10
2407 CEFBS_None, // LDAPF_lu10_ba
2408 CEFBS_None, // LDAPF_u10
2409 CEFBS_None, // LDAWB_l2rus
2410 CEFBS_None, // LDAWB_l3r
2411 CEFBS_None, // LDAWCP_lu6
2412 CEFBS_None, // LDAWCP_u6
2413 CEFBS_None, // LDAWDP_lru6
2414 CEFBS_None, // LDAWDP_ru6
2415 CEFBS_None, // LDAWF_l2rus
2416 CEFBS_None, // LDAWF_l3r
2417 CEFBS_None, // LDAWSP_lru6
2418 CEFBS_None, // LDAWSP_ru6
2419 CEFBS_None, // LDC_lru6
2420 CEFBS_None, // LDC_ru6
2421 CEFBS_None, // LDET_0R
2422 CEFBS_None, // LDIVU_l5r
2423 CEFBS_None, // LDSED_0R
2424 CEFBS_None, // LDSPC_0R
2425 CEFBS_None, // LDSSR_0R
2426 CEFBS_None, // LDWCP_lru6
2427 CEFBS_None, // LDWCP_lu10
2428 CEFBS_None, // LDWCP_ru6
2429 CEFBS_None, // LDWCP_u10
2430 CEFBS_None, // LDWDP_lru6
2431 CEFBS_None, // LDWDP_ru6
2432 CEFBS_None, // LDWSP_lru6
2433 CEFBS_None, // LDWSP_ru6
2434 CEFBS_None, // LDW_2rus
2435 CEFBS_None, // LDW_3r
2436 CEFBS_None, // LMUL_l6r
2437 CEFBS_None, // LSS_3r
2438 CEFBS_None, // LSUB_l5r
2439 CEFBS_None, // LSU_3r
2440 CEFBS_None, // MACCS_l4r
2441 CEFBS_None, // MACCU_l4r
2442 CEFBS_None, // MJOIN_1r
2443 CEFBS_None, // MKMSK_2r
2444 CEFBS_None, // MKMSK_rus
2445 CEFBS_None, // MSYNC_1r
2446 CEFBS_None, // MUL_l3r
2447 CEFBS_None, // NEG
2448 CEFBS_None, // NOT
2449 CEFBS_None, // OR_3r
2450 CEFBS_None, // OUTCT_2r
2451 CEFBS_None, // OUTCT_rus
2452 CEFBS_None, // OUTPW_l2rus
2453 CEFBS_None, // OUTSHR_2r
2454 CEFBS_None, // OUTT_2r
2455 CEFBS_None, // OUT_2r
2456 CEFBS_None, // PEEK_2r
2457 CEFBS_None, // REMS_l3r
2458 CEFBS_None, // REMU_l3r
2459 CEFBS_None, // RETSP_lu6
2460 CEFBS_None, // RETSP_u6
2461 CEFBS_None, // SETCLK_l2r
2462 CEFBS_None, // SETCP_1r
2463 CEFBS_None, // SETC_l2r
2464 CEFBS_None, // SETC_lru6
2465 CEFBS_None, // SETC_ru6
2466 CEFBS_None, // SETDP_1r
2467 CEFBS_None, // SETD_2r
2468 CEFBS_None, // SETEV_1r
2469 CEFBS_None, // SETKEP_0R
2470 CEFBS_None, // SETN_l2r
2471 CEFBS_None, // SETPSC_2r
2472 CEFBS_None, // SETPS_l2r
2473 CEFBS_None, // SETPT_2r
2474 CEFBS_None, // SETRDY_l2r
2475 CEFBS_None, // SETSP_1r
2476 CEFBS_None, // SETSR_branch_lu6
2477 CEFBS_None, // SETSR_branch_u6
2478 CEFBS_None, // SETSR_lu6
2479 CEFBS_None, // SETSR_u6
2480 CEFBS_None, // SETTW_l2r
2481 CEFBS_None, // SETV_1r
2482 CEFBS_None, // SEXT_2r
2483 CEFBS_None, // SEXT_rus
2484 CEFBS_None, // SHL_2rus
2485 CEFBS_None, // SHL_3r
2486 CEFBS_None, // SHR_2rus
2487 CEFBS_None, // SHR_3r
2488 CEFBS_None, // SSYNC_0r
2489 CEFBS_None, // ST16_l3r
2490 CEFBS_None, // ST8_l3r
2491 CEFBS_None, // STET_0R
2492 CEFBS_None, // STSED_0R
2493 CEFBS_None, // STSPC_0R
2494 CEFBS_None, // STSSR_0R
2495 CEFBS_None, // STWDP_lru6
2496 CEFBS_None, // STWDP_ru6
2497 CEFBS_None, // STWSP_lru6
2498 CEFBS_None, // STWSP_ru6
2499 CEFBS_None, // STW_2rus
2500 CEFBS_None, // STW_l3r
2501 CEFBS_None, // SUB_2rus
2502 CEFBS_None, // SUB_3r
2503 CEFBS_None, // SYNCR_1r
2504 CEFBS_None, // TESTCT_2r
2505 CEFBS_None, // TESTLCL_l2r
2506 CEFBS_None, // TESTWCT_2r
2507 CEFBS_None, // TSETMR_2r
2508 CEFBS_None, // TSETR_3r
2509 CEFBS_None, // TSTART_1R
2510 CEFBS_None, // WAITEF_1R
2511 CEFBS_None, // WAITET_1R
2512 CEFBS_None, // WAITEU_0R
2513 CEFBS_None, // XOR_l3r
2514 CEFBS_None, // ZEXT_2r
2515 CEFBS_None, // ZEXT_rus
2516 };
2517
2518 assert(Opcode < 547);
2519 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2520}
2521
2522
2523} // namespace llvm::XCore_MC
2524
2525#endif // GET_COMPUTE_FEATURES
2526
2527#ifdef GET_AVAILABLE_OPCODE_CHECKER
2528#undef GET_AVAILABLE_OPCODE_CHECKER
2529
2530namespace llvm::XCore_MC {
2531
2532bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2533 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2534 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2535 FeatureBitset MissingFeatures =
2536 (AvailableFeatures & RequiredFeatures) ^
2537 RequiredFeatures;
2538 return !MissingFeatures.any();
2539}
2540
2541} // namespace llvm::XCore_MC
2542
2543#endif // GET_AVAILABLE_OPCODE_CHECKER
2544
2545#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2546#undef ENABLE_INSTR_PREDICATE_VERIFIER
2547
2548#include <sstream>
2549
2550namespace llvm::XCore_MC {
2551
2552#ifndef NDEBUG
2553static const char *SubtargetFeatureNames[] = {
2554 nullptr
2555};
2556
2557#endif // NDEBUG
2558
2559void verifyInstructionPredicates(
2560 unsigned Opcode, const FeatureBitset &Features) {
2561#ifndef NDEBUG
2562 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2563 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2564 FeatureBitset MissingFeatures =
2565 (AvailableFeatures & RequiredFeatures) ^
2566 RequiredFeatures;
2567 if (MissingFeatures.any()) {
2568 std::ostringstream Msg;
2569 Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
2570 << " instruction but the ";
2571 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2572 if (MissingFeatures.test(i))
2573 Msg << SubtargetFeatureNames[i] << " ";
2574 Msg << "predicate(s) are not met";
2575 report_fatal_error(Msg.str().c_str());
2576 }
2577#endif // NDEBUG
2578}
2579
2580} // namespace llvm::XCore_MC
2581
2582#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2583
2584