1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::XCore {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1678
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1674
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1682
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1686
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1867
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1859
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1874
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1474
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1486
96 G_INSERT = 81, // GenericOpcodes.td:1494
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1504
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1523
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1532
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1539
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1881
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_FMAXIMUMNUM = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_FMINIMUMNUM = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_UINC_WRAP = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_UDEC_WRAP = 129, // GenericOpcodes.td:1448
145 G_ATOMICRMW_USUB_COND = 130, // GenericOpcodes.td:1449
146 G_ATOMICRMW_USUB_SAT = 131, // GenericOpcodes.td:1450
147 G_FENCE = 132, // GenericOpcodes.td:1452
148 G_PREFETCH = 133, // GenericOpcodes.td:1459
149 G_BRCOND = 134, // GenericOpcodes.td:1594
150 G_BRINDIRECT = 135, // GenericOpcodes.td:1603
151 G_INVOKE_REGION_START = 136, // GenericOpcodes.td:1626
152 G_INTRINSIC = 137, // GenericOpcodes.td:1546
153 G_INTRINSIC_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1553
154 G_INTRINSIC_CONVERGENT = 139, // GenericOpcodes.td:1562
155 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1570
156 G_ANYEXT = 141, // GenericOpcodes.td:44
157 G_TRUNC = 142, // GenericOpcodes.td:83
158 G_TRUNC_SSAT_S = 143, // GenericOpcodes.td:90
159 G_TRUNC_SSAT_U = 144, // GenericOpcodes.td:97
160 G_TRUNC_USAT_U = 145, // GenericOpcodes.td:104
161 G_CONSTANT = 146, // GenericOpcodes.td:165
162 G_FCONSTANT = 147, // GenericOpcodes.td:172
163 G_VASTART = 148, // GenericOpcodes.td:178
164 G_VAARG = 149, // GenericOpcodes.td:185
165 G_SEXT = 150, // GenericOpcodes.td:52
166 G_SEXT_INREG = 151, // GenericOpcodes.td:66
167 G_ZEXT = 152, // GenericOpcodes.td:74
168 G_SHL = 153, // GenericOpcodes.td:396
169 G_LSHR = 154, // GenericOpcodes.td:403
170 G_ASHR = 155, // GenericOpcodes.td:410
171 G_FSHL = 156, // GenericOpcodes.td:462
172 G_FSHR = 157, // GenericOpcodes.td:470
173 G_ROTR = 158, // GenericOpcodes.td:477
174 G_ROTL = 159, // GenericOpcodes.td:484
175 G_ICMP = 160, // GenericOpcodes.td:491
176 G_FCMP = 161, // GenericOpcodes.td:498
177 G_SCMP = 162, // GenericOpcodes.td:505
178 G_UCMP = 163, // GenericOpcodes.td:512
179 G_SELECT = 164, // GenericOpcodes.td:519
180 G_UADDO = 165, // GenericOpcodes.td:584
181 G_UADDE = 166, // GenericOpcodes.td:592
182 G_USUBO = 167, // GenericOpcodes.td:614
183 G_USUBE = 168, // GenericOpcodes.td:620
184 G_SADDO = 169, // GenericOpcodes.td:599
185 G_SADDE = 170, // GenericOpcodes.td:607
186 G_SSUBO = 171, // GenericOpcodes.td:627
187 G_SSUBE = 172, // GenericOpcodes.td:634
188 G_UMULO = 173, // GenericOpcodes.td:641
189 G_SMULO = 174, // GenericOpcodes.td:649
190 G_UMULH = 175, // GenericOpcodes.td:658
191 G_SMULH = 176, // GenericOpcodes.td:667
192 G_UADDSAT = 177, // GenericOpcodes.td:679
193 G_SADDSAT = 178, // GenericOpcodes.td:687
194 G_USUBSAT = 179, // GenericOpcodes.td:695
195 G_SSUBSAT = 180, // GenericOpcodes.td:703
196 G_USHLSAT = 181, // GenericOpcodes.td:711
197 G_SSHLSAT = 182, // GenericOpcodes.td:719
198 G_SMULFIX = 183, // GenericOpcodes.td:731
199 G_UMULFIX = 184, // GenericOpcodes.td:738
200 G_SMULFIXSAT = 185, // GenericOpcodes.td:748
201 G_UMULFIXSAT = 186, // GenericOpcodes.td:755
202 G_SDIVFIX = 187, // GenericOpcodes.td:766
203 G_UDIVFIX = 188, // GenericOpcodes.td:773
204 G_SDIVFIXSAT = 189, // GenericOpcodes.td:783
205 G_UDIVFIXSAT = 190, // GenericOpcodes.td:790
206 G_FADD = 191, // GenericOpcodes.td:963
207 G_FSUB = 192, // GenericOpcodes.td:971
208 G_FMUL = 193, // GenericOpcodes.td:979
209 G_FMA = 194, // GenericOpcodes.td:988
210 G_FMAD = 195, // GenericOpcodes.td:997
211 G_FDIV = 196, // GenericOpcodes.td:1005
212 G_FREM = 197, // GenericOpcodes.td:1012
213 G_FMODF = 198, // GenericOpcodes.td:1019
214 G_FPOW = 199, // GenericOpcodes.td:1026
215 G_FPOWI = 200, // GenericOpcodes.td:1033
216 G_FEXP = 201, // GenericOpcodes.td:1040
217 G_FEXP2 = 202, // GenericOpcodes.td:1047
218 G_FEXP10 = 203, // GenericOpcodes.td:1054
219 G_FLOG = 204, // GenericOpcodes.td:1061
220 G_FLOG2 = 205, // GenericOpcodes.td:1068
221 G_FLOG10 = 206, // GenericOpcodes.td:1075
222 G_FLDEXP = 207, // GenericOpcodes.td:1082
223 G_FFREXP = 208, // GenericOpcodes.td:1089
224 G_FNEG = 209, // GenericOpcodes.td:801
225 G_FPEXT = 210, // GenericOpcodes.td:807
226 G_FPTRUNC = 211, // GenericOpcodes.td:813
227 G_FPTOSI = 212, // GenericOpcodes.td:819
228 G_FPTOUI = 213, // GenericOpcodes.td:825
229 G_SITOFP = 214, // GenericOpcodes.td:831
230 G_UITOFP = 215, // GenericOpcodes.td:837
231 G_FPTOSI_SAT = 216, // GenericOpcodes.td:843
232 G_FPTOUI_SAT = 217, // GenericOpcodes.td:849
233 G_FABS = 218, // GenericOpcodes.td:855
234 G_FCOPYSIGN = 219, // GenericOpcodes.td:861
235 G_IS_FPCLASS = 220, // GenericOpcodes.td:874
236 G_FCANONICALIZE = 221, // GenericOpcodes.td:867
237 G_FMINNUM = 222, // GenericOpcodes.td:887
238 G_FMAXNUM = 223, // GenericOpcodes.td:894
239 G_FMINNUM_IEEE = 224, // GenericOpcodes.td:912
240 G_FMAXNUM_IEEE = 225, // GenericOpcodes.td:919
241 G_FMINIMUM = 226, // GenericOpcodes.td:929
242 G_FMAXIMUM = 227, // GenericOpcodes.td:936
243 G_FMINIMUMNUM = 228, // GenericOpcodes.td:944
244 G_FMAXIMUMNUM = 229, // GenericOpcodes.td:951
245 G_GET_FPENV = 230, // GenericOpcodes.td:1219
246 G_SET_FPENV = 231, // GenericOpcodes.td:1226
247 G_RESET_FPENV = 232, // GenericOpcodes.td:1233
248 G_GET_FPMODE = 233, // GenericOpcodes.td:1240
249 G_SET_FPMODE = 234, // GenericOpcodes.td:1247
250 G_RESET_FPMODE = 235, // GenericOpcodes.td:1254
251 G_GET_ROUNDING = 236, // GenericOpcodes.td:1311
252 G_SET_ROUNDING = 237, // GenericOpcodes.td:1317
253 G_PTR_ADD = 238, // GenericOpcodes.td:526
254 G_PTRMASK = 239, // GenericOpcodes.td:534
255 G_SMIN = 240, // GenericOpcodes.td:541
256 G_SMAX = 241, // GenericOpcodes.td:549
257 G_UMIN = 242, // GenericOpcodes.td:557
258 G_UMAX = 243, // GenericOpcodes.td:565
259 G_ABS = 244, // GenericOpcodes.td:573
260 G_LROUND = 245, // GenericOpcodes.td:283
261 G_LLROUND = 246, // GenericOpcodes.td:289
262 G_BR = 247, // GenericOpcodes.td:1584
263 G_BRJT = 248, // GenericOpcodes.td:1614
264 G_VSCALE = 249, // GenericOpcodes.td:1514
265 G_INSERT_SUBVECTOR = 250, // GenericOpcodes.td:1658
266 G_EXTRACT_SUBVECTOR = 251, // GenericOpcodes.td:1665
267 G_INSERT_VECTOR_ELT = 252, // GenericOpcodes.td:1672
268 G_EXTRACT_VECTOR_ELT = 253, // GenericOpcodes.td:1679
269 G_SHUFFLE_VECTOR = 254, // GenericOpcodes.td:1689
270 G_SPLAT_VECTOR = 255, // GenericOpcodes.td:1696
271 G_STEP_VECTOR = 256, // GenericOpcodes.td:1703
272 G_VECTOR_COMPRESS = 257, // GenericOpcodes.td:1710
273 G_CTTZ = 258, // GenericOpcodes.td:205
274 G_CTTZ_ZERO_UNDEF = 259, // GenericOpcodes.td:211
275 G_CTLZ = 260, // GenericOpcodes.td:193
276 G_CTLZ_ZERO_UNDEF = 261, // GenericOpcodes.td:199
277 G_CTLS = 262, // GenericOpcodes.td:217
278 G_CTPOP = 263, // GenericOpcodes.td:223
279 G_BSWAP = 264, // GenericOpcodes.td:229
280 G_BITREVERSE = 265, // GenericOpcodes.td:235
281 G_FCEIL = 266, // GenericOpcodes.td:1096
282 G_FCOS = 267, // GenericOpcodes.td:1103
283 G_FSIN = 268, // GenericOpcodes.td:1110
284 G_FSINCOS = 269, // GenericOpcodes.td:1117
285 G_FTAN = 270, // GenericOpcodes.td:1124
286 G_FACOS = 271, // GenericOpcodes.td:1131
287 G_FASIN = 272, // GenericOpcodes.td:1138
288 G_FATAN = 273, // GenericOpcodes.td:1145
289 G_FATAN2 = 274, // GenericOpcodes.td:1152
290 G_FCOSH = 275, // GenericOpcodes.td:1159
291 G_FSINH = 276, // GenericOpcodes.td:1166
292 G_FTANH = 277, // GenericOpcodes.td:1173
293 G_FSQRT = 278, // GenericOpcodes.td:1183
294 G_FFLOOR = 279, // GenericOpcodes.td:1190
295 G_FRINT = 280, // GenericOpcodes.td:1197
296 G_FNEARBYINT = 281, // GenericOpcodes.td:1204
297 G_ADDRSPACE_CAST = 282, // GenericOpcodes.td:241
298 G_BLOCK_ADDR = 283, // GenericOpcodes.td:247
299 G_JUMP_TABLE = 284, // GenericOpcodes.td:253
300 G_DYN_STACKALLOC = 285, // GenericOpcodes.td:259
301 G_STACKSAVE = 286, // GenericOpcodes.td:265
302 G_STACKRESTORE = 287, // GenericOpcodes.td:271
303 G_STRICT_FADD = 288, // GenericOpcodes.td:1760
304 G_STRICT_FSUB = 289, // GenericOpcodes.td:1761
305 G_STRICT_FMUL = 290, // GenericOpcodes.td:1762
306 G_STRICT_FDIV = 291, // GenericOpcodes.td:1763
307 G_STRICT_FREM = 292, // GenericOpcodes.td:1764
308 G_STRICT_FMA = 293, // GenericOpcodes.td:1765
309 G_STRICT_FSQRT = 294, // GenericOpcodes.td:1766
310 G_STRICT_FLDEXP = 295, // GenericOpcodes.td:1767
311 G_READ_REGISTER = 296, // GenericOpcodes.td:1633
312 G_WRITE_REGISTER = 297, // GenericOpcodes.td:1643
313 G_MEMCPY = 298, // GenericOpcodes.td:1773
314 G_MEMCPY_INLINE = 299, // GenericOpcodes.td:1781
315 G_MEMMOVE = 300, // GenericOpcodes.td:1789
316 G_MEMSET = 301, // GenericOpcodes.td:1797
317 G_BZERO = 302, // GenericOpcodes.td:1804
318 G_TRAP = 303, // GenericOpcodes.td:1814
319 G_DEBUGTRAP = 304, // GenericOpcodes.td:1821
320 G_UBSANTRAP = 305, // GenericOpcodes.td:1827
321 G_VECREDUCE_SEQ_FADD = 306, // GenericOpcodes.td:1726
322 G_VECREDUCE_SEQ_FMUL = 307, // GenericOpcodes.td:1732
323 G_VECREDUCE_FADD = 308, // GenericOpcodes.td:1738
324 G_VECREDUCE_FMUL = 309, // GenericOpcodes.td:1739
325 G_VECREDUCE_FMAX = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMIN = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_FMAXIMUM = 312, // GenericOpcodes.td:1743
328 G_VECREDUCE_FMINIMUM = 313, // GenericOpcodes.td:1744
329 G_VECREDUCE_ADD = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_MUL = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_AND = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_OR = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_XOR = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_SMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_SMIN = 320, // GenericOpcodes.td:1752
336 G_VECREDUCE_UMAX = 321, // GenericOpcodes.td:1753
337 G_VECREDUCE_UMIN = 322, // GenericOpcodes.td:1754
338 G_SBFX = 323, // GenericOpcodes.td:1839
339 G_UBFX = 324, // GenericOpcodes.td:1847
340 ADJCALLSTACKDOWN = 325, // XCoreInstrInfo.td:356
341 ADJCALLSTACKUP = 326, // XCoreInstrInfo.td:359
342 BR_JT = 327, // XCoreInstrInfo.td:991
343 BR_JT32 = 328, // XCoreInstrInfo.td:996
344 EH_RETURN = 329, // XCoreInstrInfo.td:370
345 FRAME_TO_ARGS_OFFSET = 330, // XCoreInstrInfo.td:365
346 LDAWFI = 331, // XCoreInstrInfo.td:378
347 LDWFI = 332, // XCoreInstrInfo.td:374
348 SELECT_CC = 333, // XCoreInstrInfo.td:389
349 STWFI = 334, // XCoreInstrInfo.td:382
350 ADD_2rus = 335, // XCoreInstrInfo.td:247
351 ADD_3r = 336, // XCoreInstrInfo.td:244
352 ANDNOT_2r = 337, // XCoreInstrInfo.td:797
353 AND_3r = 338, // XCoreInstrInfo.td:408
354 ASHR_l2rus = 339, // XCoreInstrInfo.td:296
355 ASHR_l3r = 340, // XCoreInstrInfo.td:293
356 BAU_1r = 341, // XCoreInstrInfo.td:986
357 BITREV_l2r = 342, // XCoreInstrInfo.td:925
358 BLACP_lu10 = 343, // XCoreInstrInfo.td:746
359 BLACP_u10 = 344, // XCoreInstrInfo.td:744
360 BLAT_lu6 = 345, // XCoreInstrInfo.td:340
361 BLAT_u6 = 346, // XCoreInstrInfo.td:339
362 BLA_1r = 347, // XCoreInstrInfo.td:1025
363 BLRB_lu10 = 348, // XCoreInstrInfo.td:756
364 BLRB_u10 = 349, // XCoreInstrInfo.td:754
365 BLRF_lu10 = 350, // XCoreInstrInfo.td:751
366 BLRF_u10 = 351, // XCoreInstrInfo.td:748
367 BRBF_lru6 = 352, // XCoreInstrInfo.td:318
368 BRBF_ru6 = 353, // XCoreInstrInfo.td:316
369 BRBT_lru6 = 354, // XCoreInstrInfo.td:318
370 BRBT_ru6 = 355, // XCoreInstrInfo.td:316
371 BRBU_lu6 = 356, // XCoreInstrInfo.td:679
372 BRBU_u6 = 357, // XCoreInstrInfo.td:677
373 BRFF_lru6 = 358, // XCoreInstrInfo.td:311
374 BRFF_ru6 = 359, // XCoreInstrInfo.td:309
375 BRFT_lru6 = 360, // XCoreInstrInfo.td:311
376 BRFT_ru6 = 361, // XCoreInstrInfo.td:309
377 BRFU_lu6 = 362, // XCoreInstrInfo.td:683
378 BRFU_u6 = 363, // XCoreInstrInfo.td:681
379 BRU_1r = 364, // XCoreInstrInfo.td:1001
380 BYTEREV_l2r = 365, // XCoreInstrInfo.td:929
381 CHKCT_2r = 366, // XCoreInstrInfo.td:863
382 CHKCT_rus = 367, // XCoreInstrInfo.td:867
383 CLRE_0R = 368, // XCoreInstrInfo.td:1070
384 CLRPT_1R = 369, // XCoreInstrInfo.td:1065
385 CLRSR_branch_lu6 = 370, // XCoreInstrInfo.td:340
386 CLRSR_branch_u6 = 371, // XCoreInstrInfo.td:339
387 CLRSR_lu6 = 372, // XCoreInstrInfo.td:334
388 CLRSR_u6 = 373, // XCoreInstrInfo.td:332
389 CLZ_l2r = 374, // XCoreInstrInfo.td:933
390 CRC8_l4r = 375, // XCoreInstrInfo.td:533
391 CRC_l3r = 376, // XCoreInstrInfo.td:494
392 DCALL_0R = 377, // XCoreInstrInfo.td:1072
393 DENTSP_0R = 378, // XCoreInstrInfo.td:1075
394 DGETREG_1r = 379, // XCoreInstrInfo.td:1048
395 DIVS_l3r = 380, // XCoreInstrInfo.td:485
396 DIVU_l3r = 381, // XCoreInstrInfo.td:486
397 DRESTSP_0R = 382, // XCoreInstrInfo.td:1078
398 DRET_0R = 383, // XCoreInstrInfo.td:1080
399 ECALLF_1r = 384, // XCoreInstrInfo.td:1018
400 ECALLT_1r = 385, // XCoreInstrInfo.td:1013
401 EDU_1r = 386, // XCoreInstrInfo.td:1050
402 EEF_2r = 387, // XCoreInstrInfo.td:915
403 EET_2r = 388, // XCoreInstrInfo.td:918
404 EEU_1r = 389, // XCoreInstrInfo.td:1053
405 ENDIN_2r = 390, // XCoreInstrInfo.td:911
406 ENTSP_lu6 = 391, // XCoreInstrInfo.td:340
407 ENTSP_u6 = 392, // XCoreInstrInfo.td:339
408 EQ_2rus = 393, // XCoreInstrInfo.td:255
409 EQ_3r = 394, // XCoreInstrInfo.td:253
410 EXTDP_lu6 = 395, // XCoreInstrInfo.td:340
411 EXTDP_u6 = 396, // XCoreInstrInfo.td:339
412 EXTSP_lu6 = 397, // XCoreInstrInfo.td:340
413 EXTSP_u6 = 398, // XCoreInstrInfo.td:339
414 FREER_1r = 399, // XCoreInstrInfo.td:1034
415 FREET_0R = 400, // XCoreInstrInfo.td:1082
416 GETD_l2r = 401, // XCoreInstrInfo.td:937
417 GETED_0R = 402, // XCoreInstrInfo.td:1089
418 GETET_0R = 403, // XCoreInstrInfo.td:1093
419 GETID_0R = 404, // XCoreInstrInfo.td:1085
420 GETKEP_0R = 405, // XCoreInstrInfo.td:1097
421 GETKSP_0R = 406, // XCoreInstrInfo.td:1100
422 GETN_l2r = 407, // XCoreInstrInfo.td:940
423 GETPS_l2r = 408, // XCoreInstrInfo.td:951
424 GETR_rus = 409, // XCoreInstrInfo.td:811
425 GETSR_lu6 = 410, // XCoreInstrInfo.td:340
426 GETSR_u6 = 411, // XCoreInstrInfo.td:339
427 GETST_2r = 412, // XCoreInstrInfo.td:887
428 GETTS_2r = 413, // XCoreInstrInfo.td:815
429 INCT_2r = 414, // XCoreInstrInfo.td:845
430 INITCP_2r = 415, // XCoreInstrInfo.td:899
431 INITDP_2r = 416, // XCoreInstrInfo.td:903
432 INITLR_l2r = 417, // XCoreInstrInfo.td:959
433 INITPC_2r = 418, // XCoreInstrInfo.td:895
434 INITSP_2r = 419, // XCoreInstrInfo.td:891
435 INPW_l2rus = 420, // XCoreInstrInfo.td:511
436 INSHR_2r = 421, // XCoreInstrInfo.td:858
437 INT_2r = 422, // XCoreInstrInfo.td:849
438 IN_2r = 423, // XCoreInstrInfo.td:853
439 KCALL_1r = 424, // XCoreInstrInfo.td:1057
440 KCALL_lu6 = 425, // XCoreInstrInfo.td:340
441 KCALL_u6 = 426, // XCoreInstrInfo.td:339
442 KENTSP_lu6 = 427, // XCoreInstrInfo.td:340
443 KENTSP_u6 = 428, // XCoreInstrInfo.td:339
444 KRESTSP_lu6 = 429, // XCoreInstrInfo.td:340
445 KRESTSP_u6 = 430, // XCoreInstrInfo.td:339
446 KRET_0R = 431, // XCoreInstrInfo.td:1105
447 LADD_l5r = 432, // XCoreInstrInfo.td:541
448 LD16S_3r = 433, // XCoreInstrInfo.td:420
449 LD8U_3r = 434, // XCoreInstrInfo.td:424
450 LDA16B_l3r = 435, // XCoreInstrInfo.td:476
451 LDA16F_l3r = 436, // XCoreInstrInfo.td:470
452 LDAPB_lu10 = 437, // XCoreInstrInfo.td:732
453 LDAPB_u10 = 438, // XCoreInstrInfo.td:728
454 LDAPF_lu10 = 439, // XCoreInstrInfo.td:724
455 LDAPF_lu10_ba = 440, // XCoreInstrInfo.td:737
456 LDAPF_u10 = 441, // XCoreInstrInfo.td:722
457 LDAWB_l2rus = 442, // XCoreInstrInfo.td:466
458 LDAWB_l3r = 443, // XCoreInstrInfo.td:459
459 LDAWCP_lu6 = 444, // XCoreInstrInfo.td:692
460 LDAWCP_u6 = 445, // XCoreInstrInfo.td:688
461 LDAWDP_lru6 = 446, // XCoreInstrInfo.td:574
462 LDAWDP_ru6 = 447, // XCoreInstrInfo.td:570
463 LDAWF_l2rus = 448, // XCoreInstrInfo.td:455
464 LDAWF_l3r = 449, // XCoreInstrInfo.td:448
465 LDAWSP_lru6 = 450, // XCoreInstrInfo.td:628
466 LDAWSP_ru6 = 451, // XCoreInstrInfo.td:625
467 LDC_lru6 = 452, // XCoreInstrInfo.td:637
468 LDC_ru6 = 453, // XCoreInstrInfo.td:634
469 LDET_0R = 454, // XCoreInstrInfo.td:1108
470 LDIVU_l5r = 455, // XCoreInstrInfo.td:553
471 LDSED_0R = 456, // XCoreInstrInfo.td:1110
472 LDSPC_0R = 457, // XCoreInstrInfo.td:1112
473 LDSSR_0R = 458, // XCoreInstrInfo.td:1114
474 LDWCP_lru6 = 459, // XCoreInstrInfo.td:598
475 LDWCP_lu10 = 460, // XCoreInstrInfo.td:763
476 LDWCP_ru6 = 461, // XCoreInstrInfo.td:596
477 LDWCP_u10 = 462, // XCoreInstrInfo.td:761
478 LDWDP_lru6 = 463, // XCoreInstrInfo.td:582
479 LDWDP_ru6 = 464, // XCoreInstrInfo.td:579
480 LDWSP_lru6 = 465, // XCoreInstrInfo.td:619
481 LDWSP_ru6 = 466, // XCoreInstrInfo.td:615
482 LDW_2rus = 467, // XCoreInstrInfo.td:416
483 LDW_3r = 468, // XCoreInstrInfo.td:412
484 LMUL_l6r = 469, // XCoreInstrInfo.td:559
485 LSS_3r = 470, // XCoreInstrInfo.td:405
486 LSUB_l5r = 471, // XCoreInstrInfo.td:547
487 LSU_3r = 472, // XCoreInstrInfo.td:406
488 MACCS_l4r = 473, // XCoreInstrInfo.td:526
489 MACCU_l4r = 474, // XCoreInstrInfo.td:521
490 MJOIN_1r = 475, // XCoreInstrInfo.td:981
491 MKMSK_2r = 476, // XCoreInstrInfo.td:807
492 MKMSK_rus = 477, // XCoreInstrInfo.td:804
493 MSYNC_1r = 478, // XCoreInstrInfo.td:978
494 MUL_l3r = 479, // XCoreInstrInfo.td:482
495 NEG = 480, // XCoreInstrInfo.td:771
496 NOT = 481, // XCoreInstrInfo.td:768
497 OR_3r = 482, // XCoreInstrInfo.td:409
498 OUTCT_2r = 483, // XCoreInstrInfo.td:823
499 OUTCT_rus = 484, // XCoreInstrInfo.td:827
500 OUTPW_l2rus = 485, // XCoreInstrInfo.td:515
501 OUTSHR_2r = 486, // XCoreInstrInfo.td:840
502 OUTT_2r = 487, // XCoreInstrInfo.td:831
503 OUT_2r = 488, // XCoreInstrInfo.td:835
504 PEEK_2r = 489, // XCoreInstrInfo.td:907
505 REMS_l3r = 490, // XCoreInstrInfo.td:487
506 REMU_l3r = 491, // XCoreInstrInfo.td:488
507 RETSP_lu6 = 492, // XCoreInstrInfo.td:327
508 RETSP_u6 = 493, // XCoreInstrInfo.td:325
509 SETCLK_l2r = 494, // XCoreInstrInfo.td:963
510 SETCP_1r = 495, // XCoreInstrInfo.td:1010
511 SETC_l2r = 496, // XCoreInstrInfo.td:943
512 SETC_lru6 = 497, // XCoreInstrInfo.td:645
513 SETC_ru6 = 498, // XCoreInstrInfo.td:641
514 SETDP_1r = 499, // XCoreInstrInfo.td:1007
515 SETD_2r = 500, // XCoreInstrInfo.td:879
516 SETEV_1r = 501, // XCoreInstrInfo.td:1043
517 SETKEP_0R = 502, // XCoreInstrInfo.td:1118
518 SETN_l2r = 503, // XCoreInstrInfo.td:967
519 SETPSC_2r = 504, // XCoreInstrInfo.td:883
520 SETPS_l2r = 505, // XCoreInstrInfo.td:955
521 SETPT_2r = 506, // XCoreInstrInfo.td:819
522 SETRDY_l2r = 507, // XCoreInstrInfo.td:970
523 SETSP_1r = 508, // XCoreInstrInfo.td:1004
524 SETSR_branch_lu6 = 509, // XCoreInstrInfo.td:340
525 SETSR_branch_u6 = 510, // XCoreInstrInfo.td:339
526 SETSR_lu6 = 511, // XCoreInstrInfo.td:334
527 SETSR_u6 = 512, // XCoreInstrInfo.td:332
528 SETTW_l2r = 513, // XCoreInstrInfo.td:947
529 SETV_1r = 514, // XCoreInstrInfo.td:1039
530 SEXT_2r = 515, // XCoreInstrInfo.td:781
531 SEXT_rus = 516, // XCoreInstrInfo.td:775
532 SHL_2rus = 517, // XCoreInstrInfo.td:264
533 SHL_3r = 518, // XCoreInstrInfo.td:261
534 SHR_2rus = 519, // XCoreInstrInfo.td:264
535 SHR_3r = 520, // XCoreInstrInfo.td:261
536 SSYNC_0r = 521, // XCoreInstrInfo.td:1120
537 ST16_l3r = 522, // XCoreInstrInfo.td:502
538 ST8_l3r = 523, // XCoreInstrInfo.td:506
539 STET_0R = 524, // XCoreInstrInfo.td:1125
540 STSED_0R = 525, // XCoreInstrInfo.td:1127
541 STSPC_0R = 526, // XCoreInstrInfo.td:1129
542 STSSR_0R = 527, // XCoreInstrInfo.td:1131
543 STWDP_lru6 = 528, // XCoreInstrInfo.td:590
544 STWDP_ru6 = 529, // XCoreInstrInfo.td:587
545 STWSP_lru6 = 530, // XCoreInstrInfo.td:609
546 STWSP_ru6 = 531, // XCoreInstrInfo.td:605
547 STW_2rus = 532, // XCoreInstrInfo.td:434
548 STW_l3r = 533, // XCoreInstrInfo.td:430
549 SUB_2rus = 534, // XCoreInstrInfo.td:247
550 SUB_3r = 535, // XCoreInstrInfo.td:244
551 SYNCR_1r = 536, // XCoreInstrInfo.td:1030
552 TESTCT_2r = 537, // XCoreInstrInfo.td:871
553 TESTLCL_l2r = 538, // XCoreInstrInfo.td:974
554 TESTWCT_2r = 539, // XCoreInstrInfo.td:875
555 TSETMR_2r = 540, // XCoreInstrInfo.td:921
556 TSETR_3r = 541, // XCoreInstrInfo.td:444
557 TSTART_1R = 542, // XCoreInstrInfo.td:1063
558 WAITEF_1R = 543, // XCoreInstrInfo.td:1059
559 WAITET_1R = 544, // XCoreInstrInfo.td:1061
560 WAITEU_0R = 545, // XCoreInstrInfo.td:1136
561 XOR_l3r = 546, // XCoreInstrInfo.td:490
562 ZEXT_2r = 547, // XCoreInstrInfo.td:792
563 ZEXT_rus = 548, // XCoreInstrInfo.td:786
564 INSTRUCTION_LIST_END = 549
565 };
566
567} // namespace llvm::XCore
568
569#endif // GET_INSTRINFO_ENUM
570
571#ifdef GET_INSTRINFO_SCHED_ENUM
572#undef GET_INSTRINFO_SCHED_ENUM
573
574namespace llvm::XCore::Sched {
575
576 enum {
577 NoInstrModel = 0,
578 SCHED_LIST_END = 1
579 };
580
581} // namespace llvm::XCore::Sched
582
583#endif // GET_INSTRINFO_SCHED_ENUM
584
585#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
586
587namespace llvm {
588
589struct XCoreInstrTable {
590 MCInstrDesc Insts[549];
591 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
592 MCPhysReg ImplicitOps[11];
593 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
594 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
595 MCOperandInfo OperandInfo[209];
596};
597} // namespace llvm
598
599#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
600
601#ifdef GET_INSTRINFO_MC_DESC
602#undef GET_INSTRINFO_MC_DESC
603
604namespace llvm {
605
606static_assert((sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
607static constexpr unsigned XCoreOpInfoBase = (sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) / sizeof(MCOperandInfo);
608
609extern const XCoreInstrTable XCoreDescs = {
610 {
611 { 548, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_rus
612 { 547, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_2r
613 { 546, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_l3r
614 { 545, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEU_0R
615 { 544, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITET_1R
616 { 543, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEF_1R
617 { 542, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSTART_1R
618 { 541, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETR_3r
619 { 540, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETMR_2r
620 { 539, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTWCT_2r
621 { 538, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTLCL_l2r
622 { 537, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTCT_2r
623 { 536, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SYNCR_1r
624 { 535, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_3r
625 { 534, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_2rus
626 { 533, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_l3r
627 { 532, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_2rus
628 { 531, 2, 0, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_ru6
629 { 530, 2, 0, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_lru6
630 { 529, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_ru6
631 { 528, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_lru6
632 { 527, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSSR_0R
633 { 526, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSPC_0R
634 { 525, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSED_0R
635 { 524, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STET_0R
636 { 523, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST8_l3r
637 { 522, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST16_l3r
638 { 521, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SSYNC_0r
639 { 520, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_3r
640 { 519, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_2rus
641 { 518, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_3r
642 { 517, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_2rus
643 { 516, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_rus
644 { 515, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_2r
645 { 514, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETV_1r
646 { 513, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETTW_l2r
647 { 512, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_u6
648 { 511, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_lu6
649 { 510, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_u6
650 { 509, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_lu6
651 { 508, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 28, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSP_1r
652 { 507, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETRDY_l2r
653 { 506, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPT_2r
654 { 505, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPS_l2r
655 { 504, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPSC_2r
656 { 503, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETN_l2r
657 { 502, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETKEP_0R
658 { 501, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETEV_1r
659 { 500, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETD_2r
660 { 499, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETDP_1r
661 { 498, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_ru6
662 { 497, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_lru6
663 { 496, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_l2r
664 { 495, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCP_1r
665 { 494, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCLK_l2r
666 { 493, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_u6
667 { 492, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_lu6
668 { 491, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMU_l3r
669 { 490, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMS_l3r
670 { 489, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PEEK_2r
671 { 488, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUT_2r
672 { 487, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTT_2r
673 { 486, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTSHR_2r
674 { 485, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTPW_l2rus
675 { 484, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_rus
676 { 483, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_2r
677 { 482, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_3r
678 { 481, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
679 { 480, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG
680 { 479, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_l3r
681 { 478, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MSYNC_1r
682 { 477, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_rus
683 { 476, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_2r
684 { 475, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MJOIN_1r
685 { 474, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCU_l4r
686 { 473, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCS_l4r
687 { 472, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSU_3r
688 { 471, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSUB_l5r
689 { 470, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSS_3r
690 { 469, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 189, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LMUL_l6r
691 { 468, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_3r
692 { 467, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_2rus
693 { 466, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_ru6
694 { 465, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_lru6
695 { 464, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_ru6
696 { 463, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_lru6
697 { 462, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_u10
698 { 461, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_ru6
699 { 460, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lu10
700 { 459, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lru6
701 { 458, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSSR_0R
702 { 457, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSPC_0R
703 { 456, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSED_0R
704 { 455, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIVU_l5r
705 { 454, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDET_0R
706 { 453, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_ru6
707 { 452, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_lru6
708 { 451, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_ru6
709 { 450, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_lru6
710 { 449, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l3r
711 { 448, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l2rus
712 { 447, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_ru6
713 { 446, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_lru6
714 { 445, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_u6
715 { 444, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_lu6
716 { 443, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l3r
717 { 442, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l2rus
718 { 441, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_u10
719 { 440, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10_ba
720 { 439, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10
721 { 438, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_u10
722 { 437, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_lu10
723 { 436, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16F_l3r
724 { 435, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16B_l3r
725 { 434, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD8U_3r
726 { 433, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD16S_3r
727 { 432, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LADD_l5r
728 { 431, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRET_0R
729 { 430, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_u6
730 { 429, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_lu6
731 { 428, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_u6
732 { 427, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_lu6
733 { 426, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_u6
734 { 425, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_lu6
735 { 424, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_1r
736 { 423, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IN_2r
737 { 422, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INT_2r
738 { 421, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSHR_2r
739 { 420, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INPW_l2rus
740 { 419, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITSP_2r
741 { 418, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITPC_2r
742 { 417, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITLR_l2r
743 { 416, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITDP_2r
744 { 415, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITCP_2r
745 { 414, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INCT_2r
746 { 413, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETTS_2r
747 { 412, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETST_2r
748 { 411, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_u6
749 { 410, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_lu6
750 { 409, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETR_rus
751 { 408, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETPS_l2r
752 { 407, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETN_l2r
753 { 406, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKSP_0R
754 { 405, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKEP_0R
755 { 404, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETID_0R
756 { 403, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETET_0R
757 { 402, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETED_0R
758 { 401, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETD_l2r
759 { 400, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREET_0R
760 { 399, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREER_1r
761 { 398, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_u6
762 { 397, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_lu6
763 { 396, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_u6
764 { 395, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_lu6
765 { 394, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_3r
766 { 393, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_2rus
767 { 392, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_u6
768 { 391, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_lu6
769 { 390, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENDIN_2r
770 { 389, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEU_1r
771 { 388, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EET_2r
772 { 387, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEF_2r
773 { 386, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EDU_1r
774 { 385, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLT_1r
775 { 384, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLF_1r
776 { 383, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRET_0R
777 { 382, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRESTSP_0R
778 { 381, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVU_l3r
779 { 380, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVS_l3r
780 { 379, 1, 1, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DGETREG_1r
781 { 378, 0, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DENTSP_0R
782 { 377, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DCALL_0R
783 { 376, 4, 1, 4, 0, 0, 0, XCoreOpInfoBase + 178, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC_l3r
784 { 375, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 173, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC8_l4r
785 { 374, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_l2r
786 { 373, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_u6
787 { 372, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_lu6
788 { 371, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_u6
789 { 370, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_lu6
790 { 369, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRPT_1R
791 { 368, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRE_0R
792 { 367, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_rus
793 { 366, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_2r
794 { 365, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BYTEREV_l2r
795 { 364, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRU_1r
796 { 363, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_u6
797 { 362, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_lu6
798 { 361, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_ru6
799 { 360, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_lru6
800 { 359, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_ru6
801 { 358, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_lru6
802 { 357, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_u6
803 { 356, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_lu6
804 { 355, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_ru6
805 { 354, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_lru6
806 { 353, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_ru6
807 { 352, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_lru6
808 { 351, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_u10
809 { 350, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_lu10
810 { 349, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_u10
811 { 348, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_lu10
812 { 347, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 28, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLA_1r
813 { 346, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_u6
814 { 345, 1, 0, 4, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_lu6
815 { 344, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_u10
816 { 343, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_lu10
817 { 342, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITREV_l2r
818 { 341, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BAU_1r
819 { 340, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l3r
820 { 339, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l2rus
821 { 338, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_3r
822 { 337, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_2r
823 { 336, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_3r
824 { 335, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_2rus
825 { 334, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWFI
826 { 333, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_CC
827 { 332, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWFI
828 { 331, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWFI
829 { 330, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FRAME_TO_ARGS_OFFSET
830 { 329, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_RETURN
831 { 328, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT32
832 { 327, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT
833 { 326, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
834 { 325, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
835 { 324, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
836 { 323, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
837 { 322, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
838 { 321, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
839 { 320, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
840 { 319, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
841 { 318, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
842 { 317, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
843 { 316, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
844 { 315, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
845 { 314, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
846 { 313, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
847 { 312, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
848 { 311, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
849 { 310, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
850 { 309, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
851 { 308, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
852 { 307, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
853 { 306, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
854 { 305, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
855 { 304, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
856 { 303, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
857 { 302, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
858 { 301, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
859 { 300, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
860 { 299, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
861 { 298, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
862 { 297, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
863 { 296, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
864 { 295, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
865 { 294, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
866 { 293, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
867 { 292, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
868 { 291, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
869 { 290, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
870 { 289, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
871 { 288, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
872 { 287, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
873 { 286, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
874 { 285, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
875 { 284, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
876 { 283, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
877 { 282, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
878 { 281, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
879 { 280, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
880 { 279, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
881 { 278, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
882 { 277, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
883 { 276, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
884 { 275, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
885 { 274, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
886 { 273, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
887 { 272, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
888 { 271, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
889 { 270, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
890 { 269, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
891 { 268, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
892 { 267, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
893 { 266, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
894 { 265, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
895 { 264, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
896 { 263, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
897 { 262, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
898 { 261, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
899 { 260, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
900 { 259, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
901 { 258, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
902 { 257, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
903 { 256, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
904 { 255, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
905 { 254, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
906 { 253, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
907 { 252, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
908 { 251, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
909 { 250, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
910 { 249, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
911 { 248, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
912 { 247, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
913 { 246, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
914 { 245, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
915 { 244, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
916 { 243, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
917 { 242, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
918 { 241, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
919 { 240, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
920 { 239, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
921 { 238, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
922 { 237, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
923 { 236, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
924 { 235, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
925 { 234, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
926 { 233, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
927 { 232, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
928 { 231, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
929 { 230, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
930 { 229, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
931 { 228, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
932 { 227, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
933 { 226, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
934 { 225, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
935 { 224, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
936 { 223, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
937 { 222, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
938 { 221, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
939 { 220, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
940 { 219, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
941 { 218, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
942 { 217, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
943 { 216, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
944 { 215, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
945 { 214, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
946 { 213, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
947 { 212, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
948 { 211, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
949 { 210, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
950 { 209, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
951 { 208, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
952 { 207, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
953 { 206, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
954 { 205, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
955 { 204, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
956 { 203, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
957 { 202, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
958 { 201, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
959 { 200, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
960 { 199, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
961 { 198, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
962 { 197, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
963 { 196, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
964 { 195, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
965 { 194, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
966 { 193, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
967 { 192, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
968 { 191, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
969 { 190, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
970 { 189, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
971 { 188, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
972 { 187, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
973 { 186, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
974 { 185, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
975 { 184, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
976 { 183, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
977 { 182, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
978 { 181, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
979 { 180, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
980 { 179, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
981 { 178, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
982 { 177, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
983 { 176, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
984 { 175, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
985 { 174, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
986 { 173, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
987 { 172, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
988 { 171, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
989 { 170, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
990 { 169, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
991 { 168, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
992 { 167, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
993 { 166, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
994 { 165, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
995 { 164, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
996 { 163, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
997 { 162, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
998 { 161, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
999 { 160, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1000 { 159, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1001 { 158, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1002 { 157, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1003 { 156, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1004 { 155, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1005 { 154, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1006 { 153, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1007 { 152, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1008 { 151, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1009 { 150, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1010 { 149, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1011 { 148, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1012 { 147, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1013 { 146, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1014 { 145, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1015 { 144, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1016 { 143, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1017 { 142, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1018 { 141, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1019 { 140, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1020 { 139, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1021 { 138, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1022 { 137, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1023 { 136, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1024 { 135, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1025 { 134, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1026 { 133, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1027 { 132, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1028 { 131, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1029 { 130, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1030 { 129, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1031 { 128, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1032 { 127, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1033 { 126, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1034 { 125, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1035 { 124, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1036 { 123, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1037 { 122, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1038 { 121, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1039 { 120, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1040 { 119, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1041 { 118, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1042 { 117, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1043 { 116, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1044 { 115, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1045 { 114, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1046 { 113, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1047 { 112, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1048 { 111, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1049 { 110, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1050 { 109, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1051 { 108, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1052 { 107, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1053 { 106, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1054 { 105, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1055 { 104, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1056 { 103, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1057 { 102, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1058 { 101, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1059 { 100, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1060 { 99, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1061 { 98, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1062 { 97, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1063 { 96, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1064 { 95, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1065 { 94, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1066 { 93, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1067 { 92, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1068 { 91, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1069 { 90, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1070 { 89, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1071 { 88, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1072 { 87, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1073 { 86, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1074 { 85, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1075 { 84, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1076 { 83, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1077 { 82, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1078 { 81, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1079 { 80, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1080 { 79, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1081 { 78, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1082 { 77, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1083 { 76, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1084 { 75, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1085 { 74, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1086 { 73, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1087 { 72, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1088 { 71, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1089 { 70, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1090 { 69, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1091 { 68, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1092 { 67, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1093 { 66, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1094 { 65, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1095 { 64, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1096 { 63, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1097 { 62, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1098 { 61, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1099 { 60, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1100 { 59, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1101 { 58, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1102 { 57, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1103 { 56, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1104 { 55, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1105 { 54, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1106 { 53, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1107 { 52, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1108 { 51, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1109 { 50, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1110 { 49, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1111 { 48, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1112 { 47, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1113 { 46, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1114 { 45, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1115 { 44, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1116 { 43, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1117 { 42, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13904
1118 { 41, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13903
1119 { 40, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1120 { 39, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1121 { 38, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1122 { 37, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1123 { 36, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1124 { 35, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1125 { 34, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1126 { 33, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1127 { 32, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13902
1128 { 31, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1129 { 30, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13542
1130 { 29, 6, 1, 0, 0, 0, 0, XCoreOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1131 { 28, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1132 { 27, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1133 { 26, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1134 { 25, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1135 { 24, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1136 { 23, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1137 { 22, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1138 { 21, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1139 { 20, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1140 { 19, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1141 { 18, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1142 { 17, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1143 { 16, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1144 { 15, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1145 { 14, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1146 { 13, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1147 { 12, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1148 { 11, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1149 { 10, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1150 { 9, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1151 { 8, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1152 { 7, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1153 { 6, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1154 { 5, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1155 { 4, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1156 { 3, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1157 { 2, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1158 { 1, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1159 { 0, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1160 }, {
1161 /* 0 */
1162 /* 0 */ XCore::SP, XCore::SP,
1163 /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
1164 /* 9 */ XCore::R11,
1165 /* 10 */ XCore::SP,
1166 }, {
1167 0
1168 }, {
1169 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1170 /* 1 */
1171 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1172 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1173 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1174 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1175 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1176 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1177 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1178 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1179 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1180 /* 28 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1181 /* 29 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1182 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1183 /* 34 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1184 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1185 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1186 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1187 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1188 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1189 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1190 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1191 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1192 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1193 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1194 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1195 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1196 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1197 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1198 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1199 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1200 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1201 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1202 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1203 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1204 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1205 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1206 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1207 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1208 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1209 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1210 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1211 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1212 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1213 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1214 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1215 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1216 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1217 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1218 /* 153 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1219 /* 155 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1220 /* 158 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1221 /* 162 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1222 /* 165 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1223 /* 168 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1224 /* 171 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1225 /* 173 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1226 /* 178 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1227 /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1228 /* 187 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1229 /* 189 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1230 /* 195 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1231 /* 201 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1232 /* 204 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1233 /* 206 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1234 }
1235};
1236
1237
1238#ifdef __GNUC__
1239#pragma GCC diagnostic push
1240#pragma GCC diagnostic ignored "-Woverlength-strings"
1241#endif
1242extern const char XCoreInstrNameData[] = {
1243 /* 0 */ "G_FLOG10\000"
1244 /* 9 */ "G_FEXP10\000"
1245 /* 18 */ "LDAPB_u10\000"
1246 /* 28 */ "BLRB_u10\000"
1247 /* 37 */ "LDAPF_u10\000"
1248 /* 47 */ "BLRF_u10\000"
1249 /* 56 */ "BLACP_u10\000"
1250 /* 66 */ "LDWCP_u10\000"
1251 /* 76 */ "LDAPB_lu10\000"
1252 /* 87 */ "BLRB_lu10\000"
1253 /* 97 */ "LDAPF_lu10\000"
1254 /* 108 */ "BLRF_lu10\000"
1255 /* 118 */ "BLACP_lu10\000"
1256 /* 129 */ "LDWCP_lu10\000"
1257 /* 140 */ "BR_JT32\000"
1258 /* 148 */ "G_FLOG2\000"
1259 /* 156 */ "G_FATAN2\000"
1260 /* 165 */ "G_FEXP2\000"
1261 /* 173 */ "KCALL_u6\000"
1262 /* 182 */ "LDAWCP_u6\000"
1263 /* 192 */ "EXTDP_u6\000"
1264 /* 201 */ "RETSP_u6\000"
1265 /* 210 */ "KENTSP_u6\000"
1266 /* 220 */ "KRESTSP_u6\000"
1267 /* 231 */ "EXTSP_u6\000"
1268 /* 240 */ "CLRSR_u6\000"
1269 /* 249 */ "GETSR_u6\000"
1270 /* 258 */ "SETSR_u6\000"
1271 /* 267 */ "BLAT_u6\000"
1272 /* 275 */ "BRBU_u6\000"
1273 /* 283 */ "BRFU_u6\000"
1274 /* 291 */ "CLRSR_branch_u6\000"
1275 /* 307 */ "SETSR_branch_u6\000"
1276 /* 323 */ "KCALL_lu6\000"
1277 /* 333 */ "LDAWCP_lu6\000"
1278 /* 344 */ "EXTDP_lu6\000"
1279 /* 354 */ "RETSP_lu6\000"
1280 /* 364 */ "KENTSP_lu6\000"
1281 /* 375 */ "KRESTSP_lu6\000"
1282 /* 387 */ "EXTSP_lu6\000"
1283 /* 397 */ "CLRSR_lu6\000"
1284 /* 407 */ "GETSR_lu6\000"
1285 /* 417 */ "SETSR_lu6\000"
1286 /* 427 */ "BLAT_lu6\000"
1287 /* 436 */ "BRBU_lu6\000"
1288 /* 445 */ "BRFU_lu6\000"
1289 /* 454 */ "CLRSR_branch_lu6\000"
1290 /* 471 */ "SETSR_branch_lu6\000"
1291 /* 488 */ "LDC_ru6\000"
1292 /* 496 */ "SETC_ru6\000"
1293 /* 505 */ "BRBF_ru6\000"
1294 /* 514 */ "BRFF_ru6\000"
1295 /* 523 */ "LDWCP_ru6\000"
1296 /* 533 */ "LDAWDP_ru6\000"
1297 /* 544 */ "LDWDP_ru6\000"
1298 /* 554 */ "STWDP_ru6\000"
1299 /* 564 */ "LDAWSP_ru6\000"
1300 /* 575 */ "LDWSP_ru6\000"
1301 /* 585 */ "STWSP_ru6\000"
1302 /* 595 */ "BRBT_ru6\000"
1303 /* 604 */ "BRFT_ru6\000"
1304 /* 613 */ "LDC_lru6\000"
1305 /* 622 */ "SETC_lru6\000"
1306 /* 632 */ "BRBF_lru6\000"
1307 /* 642 */ "BRFF_lru6\000"
1308 /* 652 */ "LDWCP_lru6\000"
1309 /* 663 */ "LDAWDP_lru6\000"
1310 /* 675 */ "LDWDP_lru6\000"
1311 /* 686 */ "STWDP_lru6\000"
1312 /* 697 */ "LDAWSP_lru6\000"
1313 /* 709 */ "LDWSP_lru6\000"
1314 /* 720 */ "STWSP_lru6\000"
1315 /* 731 */ "BRBT_lru6\000"
1316 /* 741 */ "BRFT_lru6\000"
1317 /* 751 */ "G_FMA\000"
1318 /* 757 */ "G_STRICT_FMA\000"
1319 /* 770 */ "G_FSUB\000"
1320 /* 777 */ "G_STRICT_FSUB\000"
1321 /* 791 */ "G_ATOMICRMW_FSUB\000"
1322 /* 808 */ "G_SUB\000"
1323 /* 814 */ "G_ATOMICRMW_SUB\000"
1324 /* 830 */ "SELECT_CC\000"
1325 /* 840 */ "G_INTRINSIC\000"
1326 /* 852 */ "G_FPTRUNC\000"
1327 /* 862 */ "G_INTRINSIC_TRUNC\000"
1328 /* 880 */ "G_TRUNC\000"
1329 /* 888 */ "G_BUILD_VECTOR_TRUNC\000"
1330 /* 909 */ "G_DYN_STACKALLOC\000"
1331 /* 926 */ "G_FMAD\000"
1332 /* 933 */ "G_INDEXED_SEXTLOAD\000"
1333 /* 952 */ "G_SEXTLOAD\000"
1334 /* 963 */ "G_INDEXED_ZEXTLOAD\000"
1335 /* 982 */ "G_ZEXTLOAD\000"
1336 /* 993 */ "G_INDEXED_LOAD\000"
1337 /* 1008 */ "G_LOAD\000"
1338 /* 1015 */ "G_VECREDUCE_FADD\000"
1339 /* 1032 */ "G_FADD\000"
1340 /* 1039 */ "G_VECREDUCE_SEQ_FADD\000"
1341 /* 1060 */ "G_STRICT_FADD\000"
1342 /* 1074 */ "G_ATOMICRMW_FADD\000"
1343 /* 1091 */ "G_VECREDUCE_ADD\000"
1344 /* 1107 */ "G_ADD\000"
1345 /* 1113 */ "G_PTR_ADD\000"
1346 /* 1123 */ "G_ATOMICRMW_ADD\000"
1347 /* 1139 */ "G_ATOMICRMW_NAND\000"
1348 /* 1156 */ "G_VECREDUCE_AND\000"
1349 /* 1172 */ "G_AND\000"
1350 /* 1178 */ "G_ATOMICRMW_AND\000"
1351 /* 1194 */ "LIFETIME_END\000"
1352 /* 1207 */ "G_BRCOND\000"
1353 /* 1216 */ "G_ATOMICRMW_USUB_COND\000"
1354 /* 1238 */ "G_LLROUND\000"
1355 /* 1248 */ "G_LROUND\000"
1356 /* 1257 */ "G_INTRINSIC_ROUND\000"
1357 /* 1275 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1358 /* 1301 */ "LOAD_STACK_GUARD\000"
1359 /* 1318 */ "PSEUDO_PROBE\000"
1360 /* 1331 */ "G_SSUBE\000"
1361 /* 1339 */ "G_USUBE\000"
1362 /* 1347 */ "G_FENCE\000"
1363 /* 1355 */ "ARITH_FENCE\000"
1364 /* 1367 */ "REG_SEQUENCE\000"
1365 /* 1380 */ "G_SADDE\000"
1366 /* 1388 */ "G_UADDE\000"
1367 /* 1396 */ "G_GET_FPMODE\000"
1368 /* 1409 */ "G_RESET_FPMODE\000"
1369 /* 1424 */ "G_SET_FPMODE\000"
1370 /* 1437 */ "G_FMINNUM_IEEE\000"
1371 /* 1452 */ "G_FMAXNUM_IEEE\000"
1372 /* 1467 */ "G_VSCALE\000"
1373 /* 1476 */ "G_JUMP_TABLE\000"
1374 /* 1489 */ "BUNDLE\000"
1375 /* 1496 */ "G_MEMCPY_INLINE\000"
1376 /* 1512 */ "RELOC_NONE\000"
1377 /* 1523 */ "LOCAL_ESCAPE\000"
1378 /* 1536 */ "G_STACKRESTORE\000"
1379 /* 1551 */ "G_INDEXED_STORE\000"
1380 /* 1567 */ "G_STORE\000"
1381 /* 1575 */ "G_BITREVERSE\000"
1382 /* 1588 */ "FAKE_USE\000"
1383 /* 1597 */ "DBG_VALUE\000"
1384 /* 1607 */ "G_GLOBAL_VALUE\000"
1385 /* 1622 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1386 /* 1645 */ "CONVERGENCECTRL_GLUE\000"
1387 /* 1666 */ "G_STACKSAVE\000"
1388 /* 1678 */ "G_MEMMOVE\000"
1389 /* 1688 */ "G_FREEZE\000"
1390 /* 1697 */ "G_FCANONICALIZE\000"
1391 /* 1713 */ "G_FMODF\000"
1392 /* 1721 */ "G_CTLZ_ZERO_UNDEF\000"
1393 /* 1739 */ "G_CTTZ_ZERO_UNDEF\000"
1394 /* 1757 */ "INIT_UNDEF\000"
1395 /* 1768 */ "G_IMPLICIT_DEF\000"
1396 /* 1783 */ "DBG_INSTR_REF\000"
1397 /* 1797 */ "G_FNEG\000"
1398 /* 1804 */ "EXTRACT_SUBREG\000"
1399 /* 1819 */ "INSERT_SUBREG\000"
1400 /* 1833 */ "G_SEXT_INREG\000"
1401 /* 1846 */ "SUBREG_TO_REG\000"
1402 /* 1860 */ "G_ATOMIC_CMPXCHG\000"
1403 /* 1877 */ "G_ATOMICRMW_XCHG\000"
1404 /* 1894 */ "G_GET_ROUNDING\000"
1405 /* 1909 */ "G_SET_ROUNDING\000"
1406 /* 1924 */ "G_FLOG\000"
1407 /* 1931 */ "G_VAARG\000"
1408 /* 1939 */ "PREALLOCATED_ARG\000"
1409 /* 1956 */ "G_PREFETCH\000"
1410 /* 1967 */ "G_SMULH\000"
1411 /* 1975 */ "G_UMULH\000"
1412 /* 1983 */ "G_FTANH\000"
1413 /* 1991 */ "G_FSINH\000"
1414 /* 1999 */ "G_FCOSH\000"
1415 /* 2007 */ "LDAWFI\000"
1416 /* 2014 */ "LDWFI\000"
1417 /* 2020 */ "STWFI\000"
1418 /* 2026 */ "DBG_PHI\000"
1419 /* 2034 */ "G_FPTOSI\000"
1420 /* 2043 */ "G_FPTOUI\000"
1421 /* 2052 */ "G_FPOWI\000"
1422 /* 2060 */ "COPY_LANEMASK\000"
1423 /* 2074 */ "G_PTRMASK\000"
1424 /* 2084 */ "GC_LABEL\000"
1425 /* 2093 */ "DBG_LABEL\000"
1426 /* 2103 */ "EH_LABEL\000"
1427 /* 2112 */ "ANNOTATION_LABEL\000"
1428 /* 2129 */ "ICALL_BRANCH_FUNNEL\000"
1429 /* 2149 */ "G_FSHL\000"
1430 /* 2156 */ "G_SHL\000"
1431 /* 2162 */ "G_FCEIL\000"
1432 /* 2170 */ "G_SAVGCEIL\000"
1433 /* 2181 */ "G_UAVGCEIL\000"
1434 /* 2192 */ "PATCHABLE_TAIL_CALL\000"
1435 /* 2212 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1436 /* 2239 */ "PATCHABLE_EVENT_CALL\000"
1437 /* 2260 */ "FENTRY_CALL\000"
1438 /* 2272 */ "KILL\000"
1439 /* 2277 */ "G_CONSTANT_POOL\000"
1440 /* 2293 */ "G_ROTL\000"
1441 /* 2300 */ "G_VECREDUCE_FMUL\000"
1442 /* 2317 */ "G_FMUL\000"
1443 /* 2324 */ "G_VECREDUCE_SEQ_FMUL\000"
1444 /* 2345 */ "G_STRICT_FMUL\000"
1445 /* 2359 */ "G_VECREDUCE_MUL\000"
1446 /* 2375 */ "G_MUL\000"
1447 /* 2381 */ "G_FREM\000"
1448 /* 2388 */ "G_STRICT_FREM\000"
1449 /* 2402 */ "G_SREM\000"
1450 /* 2409 */ "G_UREM\000"
1451 /* 2416 */ "G_SDIVREM\000"
1452 /* 2426 */ "G_UDIVREM\000"
1453 /* 2436 */ "INLINEASM\000"
1454 /* 2446 */ "G_VECREDUCE_FMINIMUM\000"
1455 /* 2467 */ "G_FMINIMUM\000"
1456 /* 2478 */ "G_ATOMICRMW_FMINIMUM\000"
1457 /* 2499 */ "G_VECREDUCE_FMAXIMUM\000"
1458 /* 2520 */ "G_FMAXIMUM\000"
1459 /* 2531 */ "G_ATOMICRMW_FMAXIMUM\000"
1460 /* 2552 */ "G_FMINIMUMNUM\000"
1461 /* 2566 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1462 /* 2590 */ "G_FMAXIMUMNUM\000"
1463 /* 2604 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1464 /* 2628 */ "G_FMINNUM\000"
1465 /* 2638 */ "G_FMAXNUM\000"
1466 /* 2648 */ "G_FATAN\000"
1467 /* 2656 */ "G_FTAN\000"
1468 /* 2663 */ "G_INTRINSIC_ROUNDEVEN\000"
1469 /* 2685 */ "G_ASSERT_ALIGN\000"
1470 /* 2700 */ "G_FCOPYSIGN\000"
1471 /* 2712 */ "G_VECREDUCE_FMIN\000"
1472 /* 2729 */ "G_ATOMICRMW_FMIN\000"
1473 /* 2746 */ "G_VECREDUCE_SMIN\000"
1474 /* 2763 */ "G_SMIN\000"
1475 /* 2770 */ "G_VECREDUCE_UMIN\000"
1476 /* 2787 */ "G_UMIN\000"
1477 /* 2794 */ "G_ATOMICRMW_UMIN\000"
1478 /* 2811 */ "G_ATOMICRMW_MIN\000"
1479 /* 2827 */ "G_FASIN\000"
1480 /* 2835 */ "G_FSIN\000"
1481 /* 2842 */ "CFI_INSTRUCTION\000"
1482 /* 2858 */ "EH_RETURN\000"
1483 /* 2868 */ "ADJCALLSTACKDOWN\000"
1484 /* 2885 */ "G_SSUBO\000"
1485 /* 2893 */ "G_USUBO\000"
1486 /* 2901 */ "G_SADDO\000"
1487 /* 2909 */ "G_UADDO\000"
1488 /* 2917 */ "JUMP_TABLE_DEBUG_INFO\000"
1489 /* 2939 */ "G_SMULO\000"
1490 /* 2947 */ "G_UMULO\000"
1491 /* 2955 */ "G_BZERO\000"
1492 /* 2963 */ "STACKMAP\000"
1493 /* 2972 */ "G_DEBUGTRAP\000"
1494 /* 2984 */ "G_UBSANTRAP\000"
1495 /* 2996 */ "G_TRAP\000"
1496 /* 3003 */ "G_ATOMICRMW_UDEC_WRAP\000"
1497 /* 3025 */ "G_ATOMICRMW_UINC_WRAP\000"
1498 /* 3047 */ "G_BSWAP\000"
1499 /* 3055 */ "G_SITOFP\000"
1500 /* 3064 */ "G_UITOFP\000"
1501 /* 3073 */ "G_FCMP\000"
1502 /* 3080 */ "G_ICMP\000"
1503 /* 3087 */ "G_SCMP\000"
1504 /* 3094 */ "G_UCMP\000"
1505 /* 3101 */ "CONVERGENCECTRL_LOOP\000"
1506 /* 3122 */ "G_CTPOP\000"
1507 /* 3130 */ "PATCHABLE_OP\000"
1508 /* 3143 */ "FAULTING_OP\000"
1509 /* 3155 */ "ADJCALLSTACKUP\000"
1510 /* 3170 */ "PREALLOCATED_SETUP\000"
1511 /* 3189 */ "G_FLDEXP\000"
1512 /* 3198 */ "G_STRICT_FLDEXP\000"
1513 /* 3214 */ "G_FEXP\000"
1514 /* 3221 */ "G_FFREXP\000"
1515 /* 3230 */ "LDSPC_0R\000"
1516 /* 3239 */ "STSPC_0R\000"
1517 /* 3248 */ "LDSED_0R\000"
1518 /* 3257 */ "STSED_0R\000"
1519 /* 3266 */ "GETED_0R\000"
1520 /* 3275 */ "GETID_0R\000"
1521 /* 3284 */ "CLRE_0R\000"
1522 /* 3292 */ "DCALL_0R\000"
1523 /* 3301 */ "GETKEP_0R\000"
1524 /* 3311 */ "SETKEP_0R\000"
1525 /* 3321 */ "GETKSP_0R\000"
1526 /* 3331 */ "DENTSP_0R\000"
1527 /* 3341 */ "DRESTSP_0R\000"
1528 /* 3352 */ "LDSSR_0R\000"
1529 /* 3361 */ "STSSR_0R\000"
1530 /* 3370 */ "LDET_0R\000"
1531 /* 3378 */ "FREET_0R\000"
1532 /* 3387 */ "DRET_0R\000"
1533 /* 3395 */ "KRET_0R\000"
1534 /* 3403 */ "GETET_0R\000"
1535 /* 3412 */ "STET_0R\000"
1536 /* 3420 */ "WAITEU_0R\000"
1537 /* 3430 */ "WAITEF_1R\000"
1538 /* 3440 */ "WAITET_1R\000"
1539 /* 3450 */ "CLRPT_1R\000"
1540 /* 3459 */ "TSTART_1R\000"
1541 /* 3469 */ "G_BR\000"
1542 /* 3474 */ "INLINEASM_BR\000"
1543 /* 3487 */ "G_BLOCK_ADDR\000"
1544 /* 3500 */ "MEMBARRIER\000"
1545 /* 3511 */ "G_CONSTANT_FOLD_BARRIER\000"
1546 /* 3535 */ "PATCHABLE_FUNCTION_ENTER\000"
1547 /* 3560 */ "G_READCYCLECOUNTER\000"
1548 /* 3579 */ "G_READSTEADYCOUNTER\000"
1549 /* 3599 */ "G_READ_REGISTER\000"
1550 /* 3615 */ "G_WRITE_REGISTER\000"
1551 /* 3632 */ "G_ASHR\000"
1552 /* 3639 */ "G_FSHR\000"
1553 /* 3646 */ "G_LSHR\000"
1554 /* 3653 */ "CONVERGENCECTRL_ANCHOR\000"
1555 /* 3676 */ "G_FFLOOR\000"
1556 /* 3685 */ "G_SAVGFLOOR\000"
1557 /* 3697 */ "G_UAVGFLOOR\000"
1558 /* 3709 */ "G_EXTRACT_SUBVECTOR\000"
1559 /* 3729 */ "G_INSERT_SUBVECTOR\000"
1560 /* 3748 */ "G_BUILD_VECTOR\000"
1561 /* 3763 */ "G_SHUFFLE_VECTOR\000"
1562 /* 3780 */ "G_STEP_VECTOR\000"
1563 /* 3794 */ "G_SPLAT_VECTOR\000"
1564 /* 3809 */ "G_VECREDUCE_XOR\000"
1565 /* 3825 */ "G_XOR\000"
1566 /* 3831 */ "G_ATOMICRMW_XOR\000"
1567 /* 3847 */ "G_VECREDUCE_OR\000"
1568 /* 3862 */ "G_OR\000"
1569 /* 3867 */ "G_ATOMICRMW_OR\000"
1570 /* 3882 */ "G_ROTR\000"
1571 /* 3889 */ "G_INTTOPTR\000"
1572 /* 3900 */ "G_FABS\000"
1573 /* 3907 */ "G_ABS\000"
1574 /* 3913 */ "G_ABDS\000"
1575 /* 3920 */ "G_UNMERGE_VALUES\000"
1576 /* 3937 */ "G_MERGE_VALUES\000"
1577 /* 3952 */ "G_CTLS\000"
1578 /* 3959 */ "G_FACOS\000"
1579 /* 3967 */ "G_FCOS\000"
1580 /* 3974 */ "G_FSINCOS\000"
1581 /* 3984 */ "G_CONCAT_VECTORS\000"
1582 /* 4001 */ "COPY_TO_REGCLASS\000"
1583 /* 4018 */ "G_IS_FPCLASS\000"
1584 /* 4031 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1585 /* 4061 */ "G_VECTOR_COMPRESS\000"
1586 /* 4079 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1587 /* 4106 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1588 /* 4144 */ "G_TRUNC_SSAT_S\000"
1589 /* 4159 */ "G_SSUBSAT\000"
1590 /* 4169 */ "G_USUBSAT\000"
1591 /* 4179 */ "G_SADDSAT\000"
1592 /* 4189 */ "G_UADDSAT\000"
1593 /* 4199 */ "G_SSHLSAT\000"
1594 /* 4209 */ "G_USHLSAT\000"
1595 /* 4219 */ "G_SMULFIXSAT\000"
1596 /* 4232 */ "G_UMULFIXSAT\000"
1597 /* 4245 */ "G_SDIVFIXSAT\000"
1598 /* 4258 */ "G_UDIVFIXSAT\000"
1599 /* 4271 */ "G_ATOMICRMW_USUB_SAT\000"
1600 /* 4292 */ "G_FPTOSI_SAT\000"
1601 /* 4305 */ "G_FPTOUI_SAT\000"
1602 /* 4318 */ "G_EXTRACT\000"
1603 /* 4328 */ "G_SELECT\000"
1604 /* 4337 */ "G_BRINDIRECT\000"
1605 /* 4350 */ "PATCHABLE_RET\000"
1606 /* 4364 */ "FRAME_TO_ARGS_OFFSET\000"
1607 /* 4385 */ "G_MEMSET\000"
1608 /* 4394 */ "PATCHABLE_FUNCTION_EXIT\000"
1609 /* 4418 */ "G_BRJT\000"
1610 /* 4425 */ "BR_JT\000"
1611 /* 4431 */ "G_EXTRACT_VECTOR_ELT\000"
1612 /* 4452 */ "G_INSERT_VECTOR_ELT\000"
1613 /* 4472 */ "G_FCONSTANT\000"
1614 /* 4484 */ "G_CONSTANT\000"
1615 /* 4495 */ "G_INTRINSIC_CONVERGENT\000"
1616 /* 4518 */ "STATEPOINT\000"
1617 /* 4529 */ "PATCHPOINT\000"
1618 /* 4540 */ "G_PTRTOINT\000"
1619 /* 4551 */ "G_FRINT\000"
1620 /* 4559 */ "G_INTRINSIC_LLRINT\000"
1621 /* 4578 */ "G_INTRINSIC_LRINT\000"
1622 /* 4596 */ "G_FNEARBYINT\000"
1623 /* 4609 */ "NOT\000"
1624 /* 4613 */ "G_VASTART\000"
1625 /* 4623 */ "LIFETIME_START\000"
1626 /* 4638 */ "G_INVOKE_REGION_START\000"
1627 /* 4660 */ "G_INSERT\000"
1628 /* 4669 */ "G_FSQRT\000"
1629 /* 4677 */ "G_STRICT_FSQRT\000"
1630 /* 4692 */ "G_BITCAST\000"
1631 /* 4702 */ "G_ADDRSPACE_CAST\000"
1632 /* 4719 */ "DBG_VALUE_LIST\000"
1633 /* 4734 */ "G_FPEXT\000"
1634 /* 4742 */ "G_SEXT\000"
1635 /* 4749 */ "G_ASSERT_SEXT\000"
1636 /* 4763 */ "G_ANYEXT\000"
1637 /* 4772 */ "G_ZEXT\000"
1638 /* 4779 */ "G_ASSERT_ZEXT\000"
1639 /* 4793 */ "G_ABDU\000"
1640 /* 4800 */ "G_TRUNC_SSAT_U\000"
1641 /* 4815 */ "G_TRUNC_USAT_U\000"
1642 /* 4830 */ "G_FDIV\000"
1643 /* 4837 */ "G_STRICT_FDIV\000"
1644 /* 4851 */ "G_SDIV\000"
1645 /* 4858 */ "G_UDIV\000"
1646 /* 4865 */ "G_GET_FPENV\000"
1647 /* 4877 */ "G_RESET_FPENV\000"
1648 /* 4891 */ "G_SET_FPENV\000"
1649 /* 4903 */ "G_FPOW\000"
1650 /* 4910 */ "G_VECREDUCE_FMAX\000"
1651 /* 4927 */ "G_ATOMICRMW_FMAX\000"
1652 /* 4944 */ "G_VECREDUCE_SMAX\000"
1653 /* 4961 */ "G_SMAX\000"
1654 /* 4968 */ "G_VECREDUCE_UMAX\000"
1655 /* 4985 */ "G_UMAX\000"
1656 /* 4992 */ "G_ATOMICRMW_UMAX\000"
1657 /* 5009 */ "G_ATOMICRMW_MAX\000"
1658 /* 5025 */ "G_FRAME_INDEX\000"
1659 /* 5039 */ "G_SBFX\000"
1660 /* 5046 */ "G_UBFX\000"
1661 /* 5053 */ "G_SMULFIX\000"
1662 /* 5063 */ "G_UMULFIX\000"
1663 /* 5073 */ "G_SDIVFIX\000"
1664 /* 5083 */ "G_UDIVFIX\000"
1665 /* 5093 */ "G_MEMCPY\000"
1666 /* 5102 */ "COPY\000"
1667 /* 5107 */ "CONVERGENCECTRL_ENTRY\000"
1668 /* 5129 */ "G_CTLZ\000"
1669 /* 5136 */ "G_CTTZ\000"
1670 /* 5143 */ "LDAPF_lu10_ba\000"
1671 /* 5157 */ "SSYNC_0r\000"
1672 /* 5166 */ "BLA_1r\000"
1673 /* 5173 */ "MSYNC_1r\000"
1674 /* 5182 */ "ECALLF_1r\000"
1675 /* 5192 */ "DGETREG_1r\000"
1676 /* 5203 */ "KCALL_1r\000"
1677 /* 5212 */ "MJOIN_1r\000"
1678 /* 5221 */ "SETCP_1r\000"
1679 /* 5230 */ "SETDP_1r\000"
1680 /* 5239 */ "SETSP_1r\000"
1681 /* 5248 */ "SYNCR_1r\000"
1682 /* 5257 */ "FREER_1r\000"
1683 /* 5266 */ "ECALLT_1r\000"
1684 /* 5276 */ "BAU_1r\000"
1685 /* 5283 */ "EDU_1r\000"
1686 /* 5290 */ "EEU_1r\000"
1687 /* 5297 */ "BRU_1r\000"
1688 /* 5304 */ "SETEV_1r\000"
1689 /* 5313 */ "SETV_1r\000"
1690 /* 5321 */ "INITPC_2r\000"
1691 /* 5331 */ "SETPSC_2r\000"
1692 /* 5341 */ "SETD_2r\000"
1693 /* 5349 */ "EEF_2r\000"
1694 /* 5356 */ "PEEK_2r\000"
1695 /* 5364 */ "MKMSK_2r\000"
1696 /* 5373 */ "ENDIN_2r\000"
1697 /* 5382 */ "INITCP_2r\000"
1698 /* 5392 */ "INITDP_2r\000"
1699 /* 5402 */ "INITSP_2r\000"
1700 /* 5412 */ "INSHR_2r\000"
1701 /* 5421 */ "OUTSHR_2r\000"
1702 /* 5431 */ "TSETMR_2r\000"
1703 /* 5441 */ "GETTS_2r\000"
1704 /* 5450 */ "CHKCT_2r\000"
1705 /* 5459 */ "INCT_2r\000"
1706 /* 5467 */ "TESTCT_2r\000"
1707 /* 5477 */ "OUTCT_2r\000"
1708 /* 5486 */ "TESTWCT_2r\000"
1709 /* 5497 */ "EET_2r\000"
1710 /* 5504 */ "INT_2r\000"
1711 /* 5511 */ "ANDNOT_2r\000"
1712 /* 5521 */ "SETPT_2r\000"
1713 /* 5530 */ "GETST_2r\000"
1714 /* 5539 */ "OUTT_2r\000"
1715 /* 5547 */ "OUT_2r\000"
1716 /* 5554 */ "SEXT_2r\000"
1717 /* 5562 */ "ZEXT_2r\000"
1718 /* 5570 */ "SETC_l2r\000"
1719 /* 5579 */ "GETD_l2r\000"
1720 /* 5588 */ "SETCLK_l2r\000"
1721 /* 5599 */ "TESTLCL_l2r\000"
1722 /* 5611 */ "GETN_l2r\000"
1723 /* 5620 */ "SETN_l2r\000"
1724 /* 5629 */ "INITLR_l2r\000"
1725 /* 5640 */ "GETPS_l2r\000"
1726 /* 5650 */ "SETPS_l2r\000"
1727 /* 5660 */ "BYTEREV_l2r\000"
1728 /* 5672 */ "BITREV_l2r\000"
1729 /* 5683 */ "SETTW_l2r\000"
1730 /* 5693 */ "SETRDY_l2r\000"
1731 /* 5704 */ "CLZ_l2r\000"
1732 /* 5712 */ "SUB_3r\000"
1733 /* 5719 */ "ADD_3r\000"
1734 /* 5726 */ "AND_3r\000"
1735 /* 5733 */ "SHL_3r\000"
1736 /* 5740 */ "EQ_3r\000"
1737 /* 5746 */ "SHR_3r\000"
1738 /* 5753 */ "OR_3r\000"
1739 /* 5759 */ "TSETR_3r\000"
1740 /* 5768 */ "LD16S_3r\000"
1741 /* 5777 */ "LSS_3r\000"
1742 /* 5784 */ "LD8U_3r\000"
1743 /* 5792 */ "LSU_3r\000"
1744 /* 5799 */ "LDW_3r\000"
1745 /* 5806 */ "ST16_l3r\000"
1746 /* 5815 */ "ST8_l3r\000"
1747 /* 5823 */ "LDA16B_l3r\000"
1748 /* 5834 */ "LDAWB_l3r\000"
1749 /* 5844 */ "CRC_l3r\000"
1750 /* 5852 */ "LDA16F_l3r\000"
1751 /* 5863 */ "LDAWF_l3r\000"
1752 /* 5873 */ "MUL_l3r\000"
1753 /* 5881 */ "ASHR_l3r\000"
1754 /* 5890 */ "XOR_l3r\000"
1755 /* 5898 */ "REMS_l3r\000"
1756 /* 5907 */ "DIVS_l3r\000"
1757 /* 5916 */ "REMU_l3r\000"
1758 /* 5925 */ "DIVU_l3r\000"
1759 /* 5934 */ "STW_l3r\000"
1760 /* 5942 */ "CRC8_l4r\000"
1761 /* 5951 */ "MACCS_l4r\000"
1762 /* 5961 */ "MACCU_l4r\000"
1763 /* 5971 */ "LSUB_l5r\000"
1764 /* 5980 */ "LADD_l5r\000"
1765 /* 5989 */ "LDIVU_l5r\000"
1766 /* 5999 */ "LMUL_l6r\000"
1767 /* 6008 */ "SUB_2rus\000"
1768 /* 6017 */ "ADD_2rus\000"
1769 /* 6026 */ "SHL_2rus\000"
1770 /* 6035 */ "EQ_2rus\000"
1771 /* 6043 */ "SHR_2rus\000"
1772 /* 6052 */ "LDW_2rus\000"
1773 /* 6061 */ "STW_2rus\000"
1774 /* 6070 */ "LDAWB_l2rus\000"
1775 /* 6082 */ "LDAWF_l2rus\000"
1776 /* 6094 */ "ASHR_l2rus\000"
1777 /* 6105 */ "INPW_l2rus\000"
1778 /* 6116 */ "OUTPW_l2rus\000"
1779 /* 6128 */ "MKMSK_rus\000"
1780 /* 6138 */ "GETR_rus\000"
1781 /* 6147 */ "CHKCT_rus\000"
1782 /* 6157 */ "OUTCT_rus\000"
1783 /* 6167 */ "SEXT_rus\000"
1784 /* 6176 */ "ZEXT_rus\000"
1785};
1786#ifdef __GNUC__
1787#pragma GCC diagnostic pop
1788#endif
1789
1790extern const unsigned XCoreInstrNameIndices[] = {
1791 2030U, 2436U, 3474U, 2842U, 2103U, 2084U, 2112U, 2272U,
1792 1804U, 1819U, 1770U, 1757U, 1846U, 4001U, 1597U, 4719U,
1793 1783U, 2026U, 2093U, 1367U, 5102U, 2060U, 1489U, 4623U,
1794 1194U, 1318U, 1355U, 2963U, 2260U, 4529U, 1301U, 3170U,
1795 1939U, 4518U, 1523U, 3143U, 3130U, 3535U, 4350U, 4394U,
1796 2192U, 2239U, 2212U, 2129U, 1588U, 3500U, 2917U, 1512U,
1797 5107U, 3653U, 3101U, 1645U, 4749U, 4779U, 2685U, 1107U,
1798 808U, 2375U, 4851U, 4858U, 2402U, 2409U, 2416U, 2426U,
1799 1172U, 3862U, 3825U, 3913U, 4793U, 3697U, 2181U, 3685U,
1800 2170U, 1768U, 2028U, 5025U, 1607U, 1622U, 2277U, 4318U,
1801 3920U, 4660U, 3937U, 3748U, 888U, 3984U, 4540U, 3889U,
1802 4692U, 1688U, 3511U, 1275U, 862U, 1257U, 4578U, 4559U,
1803 2663U, 3560U, 3579U, 1008U, 952U, 982U, 993U, 933U,
1804 963U, 1567U, 1551U, 4031U, 1860U, 1877U, 1123U, 814U,
1805 1178U, 1139U, 3867U, 3831U, 5009U, 2811U, 4992U, 2794U,
1806 1074U, 791U, 4927U, 2729U, 2531U, 2478U, 2604U, 2566U,
1807 3025U, 3003U, 1216U, 4271U, 1347U, 1956U, 1207U, 4337U,
1808 4638U, 840U, 4079U, 4495U, 4106U, 4763U, 880U, 4144U,
1809 4800U, 4815U, 4484U, 4472U, 4613U, 1931U, 4742U, 1833U,
1810 4772U, 2156U, 3646U, 3632U, 2149U, 3639U, 3882U, 2293U,
1811 3080U, 3073U, 3087U, 3094U, 4328U, 2909U, 1388U, 2893U,
1812 1339U, 2901U, 1380U, 2885U, 1331U, 2947U, 2939U, 1975U,
1813 1967U, 4189U, 4179U, 4169U, 4159U, 4209U, 4199U, 5053U,
1814 5063U, 4219U, 4232U, 5073U, 5083U, 4245U, 4258U, 1032U,
1815 770U, 2317U, 751U, 926U, 4830U, 2381U, 1713U, 4903U,
1816 2052U, 3214U, 165U, 9U, 1924U, 148U, 0U, 3189U,
1817 3221U, 1797U, 4734U, 852U, 2034U, 2043U, 3055U, 3064U,
1818 4292U, 4305U, 3900U, 2700U, 4018U, 1697U, 2628U, 2638U,
1819 1437U, 1452U, 2467U, 2520U, 2552U, 2590U, 4865U, 4891U,
1820 4877U, 1396U, 1424U, 1409U, 1894U, 1909U, 1113U, 2074U,
1821 2763U, 4961U, 2787U, 4985U, 3907U, 1248U, 1238U, 3469U,
1822 4418U, 1467U, 3729U, 3709U, 4452U, 4431U, 3763U, 3794U,
1823 3780U, 4061U, 5136U, 1739U, 5129U, 1721U, 3952U, 3122U,
1824 3047U, 1575U, 2162U, 3967U, 2835U, 3974U, 2656U, 3959U,
1825 2827U, 2648U, 156U, 1999U, 1991U, 1983U, 4669U, 3676U,
1826 4551U, 4596U, 4702U, 3487U, 1476U, 909U, 1666U, 1536U,
1827 1060U, 777U, 2345U, 4837U, 2388U, 757U, 4677U, 3198U,
1828 3599U, 3615U, 5093U, 1496U, 1678U, 4385U, 2955U, 2996U,
1829 2972U, 2984U, 1039U, 2324U, 1015U, 2300U, 4910U, 2712U,
1830 2499U, 2446U, 1091U, 2359U, 1156U, 3847U, 3809U, 4944U,
1831 2746U, 4968U, 2770U, 5039U, 5046U, 2868U, 3155U, 4425U,
1832 140U, 2858U, 4364U, 2007U, 2014U, 830U, 2020U, 6017U,
1833 5719U, 5511U, 5726U, 6094U, 5881U, 5276U, 5672U, 118U,
1834 56U, 427U, 267U, 5166U, 87U, 28U, 108U, 47U,
1835 632U, 505U, 731U, 595U, 436U, 275U, 642U, 514U,
1836 741U, 604U, 445U, 283U, 5297U, 5660U, 5450U, 6147U,
1837 3284U, 3450U, 454U, 291U, 397U, 240U, 5704U, 5942U,
1838 5844U, 3292U, 3331U, 5192U, 5907U, 5925U, 3341U, 3387U,
1839 5182U, 5266U, 5283U, 5349U, 5497U, 5290U, 5373U, 365U,
1840 211U, 6035U, 5740U, 344U, 192U, 387U, 231U, 5257U,
1841 3378U, 5579U, 3266U, 3403U, 3275U, 3301U, 3321U, 5611U,
1842 5640U, 6138U, 407U, 249U, 5530U, 5441U, 5459U, 5382U,
1843 5392U, 5629U, 5321U, 5402U, 6105U, 5412U, 5504U, 5376U,
1844 5203U, 323U, 173U, 364U, 210U, 375U, 220U, 3395U,
1845 5980U, 5768U, 5784U, 5823U, 5852U, 76U, 18U, 97U,
1846 5143U, 37U, 6070U, 5834U, 333U, 182U, 663U, 533U,
1847 6082U, 5863U, 697U, 564U, 613U, 488U, 3370U, 5989U,
1848 3248U, 3230U, 3352U, 652U, 129U, 523U, 66U, 675U,
1849 544U, 709U, 575U, 6052U, 5799U, 5999U, 5777U, 5971U,
1850 5792U, 5951U, 5961U, 5212U, 5364U, 6128U, 5173U, 5873U,
1851 1800U, 4609U, 5753U, 5477U, 6157U, 6116U, 5421U, 5539U,
1852 5547U, 5356U, 5898U, 5916U, 354U, 201U, 5588U, 5221U,
1853 5570U, 622U, 496U, 5230U, 5341U, 5304U, 3311U, 5620U,
1854 5331U, 5650U, 5521U, 5693U, 5239U, 471U, 307U, 417U,
1855 258U, 5683U, 5313U, 5554U, 6167U, 6026U, 5733U, 6043U,
1856 5746U, 5157U, 5806U, 5815U, 3412U, 3257U, 3239U, 3361U,
1857 686U, 554U, 720U, 585U, 6061U, 5934U, 6008U, 5712U,
1858 5248U, 5467U, 5599U, 5486U, 5431U, 5759U, 3459U, 3430U,
1859 3440U, 3420U, 5890U, 5562U, 6176U,
1860};
1861
1862static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1863 II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 549, nullptr, 0);
1864}
1865
1866
1867} // namespace llvm
1868
1869#endif // GET_INSTRINFO_MC_DESC
1870
1871#ifdef GET_INSTRINFO_HEADER
1872#undef GET_INSTRINFO_HEADER
1873
1874namespace llvm {
1875
1876struct XCoreGenInstrInfo : public TargetInstrInfo {
1877 explicit XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1878 ~XCoreGenInstrInfo() override = default;
1879};
1880
1881} // namespace llvm
1882
1883namespace llvm::XCore {
1884
1885
1886} // namespace llvm::XCore
1887
1888#endif // GET_INSTRINFO_HEADER
1889
1890#ifdef GET_INSTRINFO_HELPER_DECLS
1891#undef GET_INSTRINFO_HELPER_DECLS
1892
1893
1894#endif // GET_INSTRINFO_HELPER_DECLS
1895
1896#ifdef GET_INSTRINFO_HELPERS
1897#undef GET_INSTRINFO_HELPERS
1898
1899
1900#endif // GET_INSTRINFO_HELPERS
1901
1902#ifdef GET_INSTRINFO_CTOR_DTOR
1903#undef GET_INSTRINFO_CTOR_DTOR
1904
1905namespace llvm {
1906
1907extern const XCoreInstrTable XCoreDescs;
1908extern const unsigned XCoreInstrNameIndices[];
1909extern const char XCoreInstrNameData[];
1910XCoreGenInstrInfo::XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1911 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1912 InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 549);
1913}
1914
1915} // namespace llvm
1916
1917#endif // GET_INSTRINFO_CTOR_DTOR
1918
1919#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1920#undef GET_INSTRINFO_MC_HELPER_DECLS
1921
1922namespace llvm {
1923
1924class MCInst;
1925class FeatureBitset;
1926
1927namespace XCore_MC {
1928
1929void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1930
1931} // namespace XCore_MC
1932
1933} // namespace llvm
1934
1935#endif // GET_INSTRINFO_MC_HELPER_DECLS
1936
1937#ifdef GET_INSTRINFO_MC_HELPERS
1938#undef GET_INSTRINFO_MC_HELPERS
1939
1940namespace llvm::XCore_MC {
1941
1942
1943} // namespace llvm::XCore_MC
1944
1945#endif // GET_INSTRINFO_MC_HELPERS
1946
1947#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1948 defined(GET_AVAILABLE_OPCODE_CHECKER)
1949#define GET_COMPUTE_FEATURES
1950#endif
1951#ifdef GET_COMPUTE_FEATURES
1952#undef GET_COMPUTE_FEATURES
1953
1954namespace llvm::XCore_MC {
1955
1956// Bits for subtarget features that participate in instruction matching.
1957enum SubtargetFeatureBits : uint8_t {
1958};
1959
1960inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1961 FeatureBitset Features;
1962 return Features;
1963}
1964
1965inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1966 enum : uint8_t {
1967 CEFBS_None,
1968 };
1969
1970 static constexpr FeatureBitset FeatureBitsets[] = {
1971 {}, // CEFBS_None
1972 };
1973 static constexpr uint8_t RequiredFeaturesRefs[] = {
1974 CEFBS_None, // PHI
1975 CEFBS_None, // INLINEASM
1976 CEFBS_None, // INLINEASM_BR
1977 CEFBS_None, // CFI_INSTRUCTION
1978 CEFBS_None, // EH_LABEL
1979 CEFBS_None, // GC_LABEL
1980 CEFBS_None, // ANNOTATION_LABEL
1981 CEFBS_None, // KILL
1982 CEFBS_None, // EXTRACT_SUBREG
1983 CEFBS_None, // INSERT_SUBREG
1984 CEFBS_None, // IMPLICIT_DEF
1985 CEFBS_None, // INIT_UNDEF
1986 CEFBS_None, // SUBREG_TO_REG
1987 CEFBS_None, // COPY_TO_REGCLASS
1988 CEFBS_None, // DBG_VALUE
1989 CEFBS_None, // DBG_VALUE_LIST
1990 CEFBS_None, // DBG_INSTR_REF
1991 CEFBS_None, // DBG_PHI
1992 CEFBS_None, // DBG_LABEL
1993 CEFBS_None, // REG_SEQUENCE
1994 CEFBS_None, // COPY
1995 CEFBS_None, // COPY_LANEMASK
1996 CEFBS_None, // BUNDLE
1997 CEFBS_None, // LIFETIME_START
1998 CEFBS_None, // LIFETIME_END
1999 CEFBS_None, // PSEUDO_PROBE
2000 CEFBS_None, // ARITH_FENCE
2001 CEFBS_None, // STACKMAP
2002 CEFBS_None, // FENTRY_CALL
2003 CEFBS_None, // PATCHPOINT
2004 CEFBS_None, // LOAD_STACK_GUARD
2005 CEFBS_None, // PREALLOCATED_SETUP
2006 CEFBS_None, // PREALLOCATED_ARG
2007 CEFBS_None, // STATEPOINT
2008 CEFBS_None, // LOCAL_ESCAPE
2009 CEFBS_None, // FAULTING_OP
2010 CEFBS_None, // PATCHABLE_OP
2011 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2012 CEFBS_None, // PATCHABLE_RET
2013 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2014 CEFBS_None, // PATCHABLE_TAIL_CALL
2015 CEFBS_None, // PATCHABLE_EVENT_CALL
2016 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2017 CEFBS_None, // ICALL_BRANCH_FUNNEL
2018 CEFBS_None, // FAKE_USE
2019 CEFBS_None, // MEMBARRIER
2020 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2021 CEFBS_None, // RELOC_NONE
2022 CEFBS_None, // CONVERGENCECTRL_ENTRY
2023 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2024 CEFBS_None, // CONVERGENCECTRL_LOOP
2025 CEFBS_None, // CONVERGENCECTRL_GLUE
2026 CEFBS_None, // G_ASSERT_SEXT
2027 CEFBS_None, // G_ASSERT_ZEXT
2028 CEFBS_None, // G_ASSERT_ALIGN
2029 CEFBS_None, // G_ADD
2030 CEFBS_None, // G_SUB
2031 CEFBS_None, // G_MUL
2032 CEFBS_None, // G_SDIV
2033 CEFBS_None, // G_UDIV
2034 CEFBS_None, // G_SREM
2035 CEFBS_None, // G_UREM
2036 CEFBS_None, // G_SDIVREM
2037 CEFBS_None, // G_UDIVREM
2038 CEFBS_None, // G_AND
2039 CEFBS_None, // G_OR
2040 CEFBS_None, // G_XOR
2041 CEFBS_None, // G_ABDS
2042 CEFBS_None, // G_ABDU
2043 CEFBS_None, // G_UAVGFLOOR
2044 CEFBS_None, // G_UAVGCEIL
2045 CEFBS_None, // G_SAVGFLOOR
2046 CEFBS_None, // G_SAVGCEIL
2047 CEFBS_None, // G_IMPLICIT_DEF
2048 CEFBS_None, // G_PHI
2049 CEFBS_None, // G_FRAME_INDEX
2050 CEFBS_None, // G_GLOBAL_VALUE
2051 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2052 CEFBS_None, // G_CONSTANT_POOL
2053 CEFBS_None, // G_EXTRACT
2054 CEFBS_None, // G_UNMERGE_VALUES
2055 CEFBS_None, // G_INSERT
2056 CEFBS_None, // G_MERGE_VALUES
2057 CEFBS_None, // G_BUILD_VECTOR
2058 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2059 CEFBS_None, // G_CONCAT_VECTORS
2060 CEFBS_None, // G_PTRTOINT
2061 CEFBS_None, // G_INTTOPTR
2062 CEFBS_None, // G_BITCAST
2063 CEFBS_None, // G_FREEZE
2064 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2065 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2066 CEFBS_None, // G_INTRINSIC_TRUNC
2067 CEFBS_None, // G_INTRINSIC_ROUND
2068 CEFBS_None, // G_INTRINSIC_LRINT
2069 CEFBS_None, // G_INTRINSIC_LLRINT
2070 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2071 CEFBS_None, // G_READCYCLECOUNTER
2072 CEFBS_None, // G_READSTEADYCOUNTER
2073 CEFBS_None, // G_LOAD
2074 CEFBS_None, // G_SEXTLOAD
2075 CEFBS_None, // G_ZEXTLOAD
2076 CEFBS_None, // G_INDEXED_LOAD
2077 CEFBS_None, // G_INDEXED_SEXTLOAD
2078 CEFBS_None, // G_INDEXED_ZEXTLOAD
2079 CEFBS_None, // G_STORE
2080 CEFBS_None, // G_INDEXED_STORE
2081 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2082 CEFBS_None, // G_ATOMIC_CMPXCHG
2083 CEFBS_None, // G_ATOMICRMW_XCHG
2084 CEFBS_None, // G_ATOMICRMW_ADD
2085 CEFBS_None, // G_ATOMICRMW_SUB
2086 CEFBS_None, // G_ATOMICRMW_AND
2087 CEFBS_None, // G_ATOMICRMW_NAND
2088 CEFBS_None, // G_ATOMICRMW_OR
2089 CEFBS_None, // G_ATOMICRMW_XOR
2090 CEFBS_None, // G_ATOMICRMW_MAX
2091 CEFBS_None, // G_ATOMICRMW_MIN
2092 CEFBS_None, // G_ATOMICRMW_UMAX
2093 CEFBS_None, // G_ATOMICRMW_UMIN
2094 CEFBS_None, // G_ATOMICRMW_FADD
2095 CEFBS_None, // G_ATOMICRMW_FSUB
2096 CEFBS_None, // G_ATOMICRMW_FMAX
2097 CEFBS_None, // G_ATOMICRMW_FMIN
2098 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2099 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2100 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2101 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2102 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2103 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2104 CEFBS_None, // G_ATOMICRMW_USUB_COND
2105 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2106 CEFBS_None, // G_FENCE
2107 CEFBS_None, // G_PREFETCH
2108 CEFBS_None, // G_BRCOND
2109 CEFBS_None, // G_BRINDIRECT
2110 CEFBS_None, // G_INVOKE_REGION_START
2111 CEFBS_None, // G_INTRINSIC
2112 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2113 CEFBS_None, // G_INTRINSIC_CONVERGENT
2114 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2115 CEFBS_None, // G_ANYEXT
2116 CEFBS_None, // G_TRUNC
2117 CEFBS_None, // G_TRUNC_SSAT_S
2118 CEFBS_None, // G_TRUNC_SSAT_U
2119 CEFBS_None, // G_TRUNC_USAT_U
2120 CEFBS_None, // G_CONSTANT
2121 CEFBS_None, // G_FCONSTANT
2122 CEFBS_None, // G_VASTART
2123 CEFBS_None, // G_VAARG
2124 CEFBS_None, // G_SEXT
2125 CEFBS_None, // G_SEXT_INREG
2126 CEFBS_None, // G_ZEXT
2127 CEFBS_None, // G_SHL
2128 CEFBS_None, // G_LSHR
2129 CEFBS_None, // G_ASHR
2130 CEFBS_None, // G_FSHL
2131 CEFBS_None, // G_FSHR
2132 CEFBS_None, // G_ROTR
2133 CEFBS_None, // G_ROTL
2134 CEFBS_None, // G_ICMP
2135 CEFBS_None, // G_FCMP
2136 CEFBS_None, // G_SCMP
2137 CEFBS_None, // G_UCMP
2138 CEFBS_None, // G_SELECT
2139 CEFBS_None, // G_UADDO
2140 CEFBS_None, // G_UADDE
2141 CEFBS_None, // G_USUBO
2142 CEFBS_None, // G_USUBE
2143 CEFBS_None, // G_SADDO
2144 CEFBS_None, // G_SADDE
2145 CEFBS_None, // G_SSUBO
2146 CEFBS_None, // G_SSUBE
2147 CEFBS_None, // G_UMULO
2148 CEFBS_None, // G_SMULO
2149 CEFBS_None, // G_UMULH
2150 CEFBS_None, // G_SMULH
2151 CEFBS_None, // G_UADDSAT
2152 CEFBS_None, // G_SADDSAT
2153 CEFBS_None, // G_USUBSAT
2154 CEFBS_None, // G_SSUBSAT
2155 CEFBS_None, // G_USHLSAT
2156 CEFBS_None, // G_SSHLSAT
2157 CEFBS_None, // G_SMULFIX
2158 CEFBS_None, // G_UMULFIX
2159 CEFBS_None, // G_SMULFIXSAT
2160 CEFBS_None, // G_UMULFIXSAT
2161 CEFBS_None, // G_SDIVFIX
2162 CEFBS_None, // G_UDIVFIX
2163 CEFBS_None, // G_SDIVFIXSAT
2164 CEFBS_None, // G_UDIVFIXSAT
2165 CEFBS_None, // G_FADD
2166 CEFBS_None, // G_FSUB
2167 CEFBS_None, // G_FMUL
2168 CEFBS_None, // G_FMA
2169 CEFBS_None, // G_FMAD
2170 CEFBS_None, // G_FDIV
2171 CEFBS_None, // G_FREM
2172 CEFBS_None, // G_FMODF
2173 CEFBS_None, // G_FPOW
2174 CEFBS_None, // G_FPOWI
2175 CEFBS_None, // G_FEXP
2176 CEFBS_None, // G_FEXP2
2177 CEFBS_None, // G_FEXP10
2178 CEFBS_None, // G_FLOG
2179 CEFBS_None, // G_FLOG2
2180 CEFBS_None, // G_FLOG10
2181 CEFBS_None, // G_FLDEXP
2182 CEFBS_None, // G_FFREXP
2183 CEFBS_None, // G_FNEG
2184 CEFBS_None, // G_FPEXT
2185 CEFBS_None, // G_FPTRUNC
2186 CEFBS_None, // G_FPTOSI
2187 CEFBS_None, // G_FPTOUI
2188 CEFBS_None, // G_SITOFP
2189 CEFBS_None, // G_UITOFP
2190 CEFBS_None, // G_FPTOSI_SAT
2191 CEFBS_None, // G_FPTOUI_SAT
2192 CEFBS_None, // G_FABS
2193 CEFBS_None, // G_FCOPYSIGN
2194 CEFBS_None, // G_IS_FPCLASS
2195 CEFBS_None, // G_FCANONICALIZE
2196 CEFBS_None, // G_FMINNUM
2197 CEFBS_None, // G_FMAXNUM
2198 CEFBS_None, // G_FMINNUM_IEEE
2199 CEFBS_None, // G_FMAXNUM_IEEE
2200 CEFBS_None, // G_FMINIMUM
2201 CEFBS_None, // G_FMAXIMUM
2202 CEFBS_None, // G_FMINIMUMNUM
2203 CEFBS_None, // G_FMAXIMUMNUM
2204 CEFBS_None, // G_GET_FPENV
2205 CEFBS_None, // G_SET_FPENV
2206 CEFBS_None, // G_RESET_FPENV
2207 CEFBS_None, // G_GET_FPMODE
2208 CEFBS_None, // G_SET_FPMODE
2209 CEFBS_None, // G_RESET_FPMODE
2210 CEFBS_None, // G_GET_ROUNDING
2211 CEFBS_None, // G_SET_ROUNDING
2212 CEFBS_None, // G_PTR_ADD
2213 CEFBS_None, // G_PTRMASK
2214 CEFBS_None, // G_SMIN
2215 CEFBS_None, // G_SMAX
2216 CEFBS_None, // G_UMIN
2217 CEFBS_None, // G_UMAX
2218 CEFBS_None, // G_ABS
2219 CEFBS_None, // G_LROUND
2220 CEFBS_None, // G_LLROUND
2221 CEFBS_None, // G_BR
2222 CEFBS_None, // G_BRJT
2223 CEFBS_None, // G_VSCALE
2224 CEFBS_None, // G_INSERT_SUBVECTOR
2225 CEFBS_None, // G_EXTRACT_SUBVECTOR
2226 CEFBS_None, // G_INSERT_VECTOR_ELT
2227 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2228 CEFBS_None, // G_SHUFFLE_VECTOR
2229 CEFBS_None, // G_SPLAT_VECTOR
2230 CEFBS_None, // G_STEP_VECTOR
2231 CEFBS_None, // G_VECTOR_COMPRESS
2232 CEFBS_None, // G_CTTZ
2233 CEFBS_None, // G_CTTZ_ZERO_UNDEF
2234 CEFBS_None, // G_CTLZ
2235 CEFBS_None, // G_CTLZ_ZERO_UNDEF
2236 CEFBS_None, // G_CTLS
2237 CEFBS_None, // G_CTPOP
2238 CEFBS_None, // G_BSWAP
2239 CEFBS_None, // G_BITREVERSE
2240 CEFBS_None, // G_FCEIL
2241 CEFBS_None, // G_FCOS
2242 CEFBS_None, // G_FSIN
2243 CEFBS_None, // G_FSINCOS
2244 CEFBS_None, // G_FTAN
2245 CEFBS_None, // G_FACOS
2246 CEFBS_None, // G_FASIN
2247 CEFBS_None, // G_FATAN
2248 CEFBS_None, // G_FATAN2
2249 CEFBS_None, // G_FCOSH
2250 CEFBS_None, // G_FSINH
2251 CEFBS_None, // G_FTANH
2252 CEFBS_None, // G_FSQRT
2253 CEFBS_None, // G_FFLOOR
2254 CEFBS_None, // G_FRINT
2255 CEFBS_None, // G_FNEARBYINT
2256 CEFBS_None, // G_ADDRSPACE_CAST
2257 CEFBS_None, // G_BLOCK_ADDR
2258 CEFBS_None, // G_JUMP_TABLE
2259 CEFBS_None, // G_DYN_STACKALLOC
2260 CEFBS_None, // G_STACKSAVE
2261 CEFBS_None, // G_STACKRESTORE
2262 CEFBS_None, // G_STRICT_FADD
2263 CEFBS_None, // G_STRICT_FSUB
2264 CEFBS_None, // G_STRICT_FMUL
2265 CEFBS_None, // G_STRICT_FDIV
2266 CEFBS_None, // G_STRICT_FREM
2267 CEFBS_None, // G_STRICT_FMA
2268 CEFBS_None, // G_STRICT_FSQRT
2269 CEFBS_None, // G_STRICT_FLDEXP
2270 CEFBS_None, // G_READ_REGISTER
2271 CEFBS_None, // G_WRITE_REGISTER
2272 CEFBS_None, // G_MEMCPY
2273 CEFBS_None, // G_MEMCPY_INLINE
2274 CEFBS_None, // G_MEMMOVE
2275 CEFBS_None, // G_MEMSET
2276 CEFBS_None, // G_BZERO
2277 CEFBS_None, // G_TRAP
2278 CEFBS_None, // G_DEBUGTRAP
2279 CEFBS_None, // G_UBSANTRAP
2280 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2281 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2282 CEFBS_None, // G_VECREDUCE_FADD
2283 CEFBS_None, // G_VECREDUCE_FMUL
2284 CEFBS_None, // G_VECREDUCE_FMAX
2285 CEFBS_None, // G_VECREDUCE_FMIN
2286 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2287 CEFBS_None, // G_VECREDUCE_FMINIMUM
2288 CEFBS_None, // G_VECREDUCE_ADD
2289 CEFBS_None, // G_VECREDUCE_MUL
2290 CEFBS_None, // G_VECREDUCE_AND
2291 CEFBS_None, // G_VECREDUCE_OR
2292 CEFBS_None, // G_VECREDUCE_XOR
2293 CEFBS_None, // G_VECREDUCE_SMAX
2294 CEFBS_None, // G_VECREDUCE_SMIN
2295 CEFBS_None, // G_VECREDUCE_UMAX
2296 CEFBS_None, // G_VECREDUCE_UMIN
2297 CEFBS_None, // G_SBFX
2298 CEFBS_None, // G_UBFX
2299 CEFBS_None, // ADJCALLSTACKDOWN
2300 CEFBS_None, // ADJCALLSTACKUP
2301 CEFBS_None, // BR_JT
2302 CEFBS_None, // BR_JT32
2303 CEFBS_None, // EH_RETURN
2304 CEFBS_None, // FRAME_TO_ARGS_OFFSET
2305 CEFBS_None, // LDAWFI
2306 CEFBS_None, // LDWFI
2307 CEFBS_None, // SELECT_CC
2308 CEFBS_None, // STWFI
2309 CEFBS_None, // ADD_2rus
2310 CEFBS_None, // ADD_3r
2311 CEFBS_None, // ANDNOT_2r
2312 CEFBS_None, // AND_3r
2313 CEFBS_None, // ASHR_l2rus
2314 CEFBS_None, // ASHR_l3r
2315 CEFBS_None, // BAU_1r
2316 CEFBS_None, // BITREV_l2r
2317 CEFBS_None, // BLACP_lu10
2318 CEFBS_None, // BLACP_u10
2319 CEFBS_None, // BLAT_lu6
2320 CEFBS_None, // BLAT_u6
2321 CEFBS_None, // BLA_1r
2322 CEFBS_None, // BLRB_lu10
2323 CEFBS_None, // BLRB_u10
2324 CEFBS_None, // BLRF_lu10
2325 CEFBS_None, // BLRF_u10
2326 CEFBS_None, // BRBF_lru6
2327 CEFBS_None, // BRBF_ru6
2328 CEFBS_None, // BRBT_lru6
2329 CEFBS_None, // BRBT_ru6
2330 CEFBS_None, // BRBU_lu6
2331 CEFBS_None, // BRBU_u6
2332 CEFBS_None, // BRFF_lru6
2333 CEFBS_None, // BRFF_ru6
2334 CEFBS_None, // BRFT_lru6
2335 CEFBS_None, // BRFT_ru6
2336 CEFBS_None, // BRFU_lu6
2337 CEFBS_None, // BRFU_u6
2338 CEFBS_None, // BRU_1r
2339 CEFBS_None, // BYTEREV_l2r
2340 CEFBS_None, // CHKCT_2r
2341 CEFBS_None, // CHKCT_rus
2342 CEFBS_None, // CLRE_0R
2343 CEFBS_None, // CLRPT_1R
2344 CEFBS_None, // CLRSR_branch_lu6
2345 CEFBS_None, // CLRSR_branch_u6
2346 CEFBS_None, // CLRSR_lu6
2347 CEFBS_None, // CLRSR_u6
2348 CEFBS_None, // CLZ_l2r
2349 CEFBS_None, // CRC8_l4r
2350 CEFBS_None, // CRC_l3r
2351 CEFBS_None, // DCALL_0R
2352 CEFBS_None, // DENTSP_0R
2353 CEFBS_None, // DGETREG_1r
2354 CEFBS_None, // DIVS_l3r
2355 CEFBS_None, // DIVU_l3r
2356 CEFBS_None, // DRESTSP_0R
2357 CEFBS_None, // DRET_0R
2358 CEFBS_None, // ECALLF_1r
2359 CEFBS_None, // ECALLT_1r
2360 CEFBS_None, // EDU_1r
2361 CEFBS_None, // EEF_2r
2362 CEFBS_None, // EET_2r
2363 CEFBS_None, // EEU_1r
2364 CEFBS_None, // ENDIN_2r
2365 CEFBS_None, // ENTSP_lu6
2366 CEFBS_None, // ENTSP_u6
2367 CEFBS_None, // EQ_2rus
2368 CEFBS_None, // EQ_3r
2369 CEFBS_None, // EXTDP_lu6
2370 CEFBS_None, // EXTDP_u6
2371 CEFBS_None, // EXTSP_lu6
2372 CEFBS_None, // EXTSP_u6
2373 CEFBS_None, // FREER_1r
2374 CEFBS_None, // FREET_0R
2375 CEFBS_None, // GETD_l2r
2376 CEFBS_None, // GETED_0R
2377 CEFBS_None, // GETET_0R
2378 CEFBS_None, // GETID_0R
2379 CEFBS_None, // GETKEP_0R
2380 CEFBS_None, // GETKSP_0R
2381 CEFBS_None, // GETN_l2r
2382 CEFBS_None, // GETPS_l2r
2383 CEFBS_None, // GETR_rus
2384 CEFBS_None, // GETSR_lu6
2385 CEFBS_None, // GETSR_u6
2386 CEFBS_None, // GETST_2r
2387 CEFBS_None, // GETTS_2r
2388 CEFBS_None, // INCT_2r
2389 CEFBS_None, // INITCP_2r
2390 CEFBS_None, // INITDP_2r
2391 CEFBS_None, // INITLR_l2r
2392 CEFBS_None, // INITPC_2r
2393 CEFBS_None, // INITSP_2r
2394 CEFBS_None, // INPW_l2rus
2395 CEFBS_None, // INSHR_2r
2396 CEFBS_None, // INT_2r
2397 CEFBS_None, // IN_2r
2398 CEFBS_None, // KCALL_1r
2399 CEFBS_None, // KCALL_lu6
2400 CEFBS_None, // KCALL_u6
2401 CEFBS_None, // KENTSP_lu6
2402 CEFBS_None, // KENTSP_u6
2403 CEFBS_None, // KRESTSP_lu6
2404 CEFBS_None, // KRESTSP_u6
2405 CEFBS_None, // KRET_0R
2406 CEFBS_None, // LADD_l5r
2407 CEFBS_None, // LD16S_3r
2408 CEFBS_None, // LD8U_3r
2409 CEFBS_None, // LDA16B_l3r
2410 CEFBS_None, // LDA16F_l3r
2411 CEFBS_None, // LDAPB_lu10
2412 CEFBS_None, // LDAPB_u10
2413 CEFBS_None, // LDAPF_lu10
2414 CEFBS_None, // LDAPF_lu10_ba
2415 CEFBS_None, // LDAPF_u10
2416 CEFBS_None, // LDAWB_l2rus
2417 CEFBS_None, // LDAWB_l3r
2418 CEFBS_None, // LDAWCP_lu6
2419 CEFBS_None, // LDAWCP_u6
2420 CEFBS_None, // LDAWDP_lru6
2421 CEFBS_None, // LDAWDP_ru6
2422 CEFBS_None, // LDAWF_l2rus
2423 CEFBS_None, // LDAWF_l3r
2424 CEFBS_None, // LDAWSP_lru6
2425 CEFBS_None, // LDAWSP_ru6
2426 CEFBS_None, // LDC_lru6
2427 CEFBS_None, // LDC_ru6
2428 CEFBS_None, // LDET_0R
2429 CEFBS_None, // LDIVU_l5r
2430 CEFBS_None, // LDSED_0R
2431 CEFBS_None, // LDSPC_0R
2432 CEFBS_None, // LDSSR_0R
2433 CEFBS_None, // LDWCP_lru6
2434 CEFBS_None, // LDWCP_lu10
2435 CEFBS_None, // LDWCP_ru6
2436 CEFBS_None, // LDWCP_u10
2437 CEFBS_None, // LDWDP_lru6
2438 CEFBS_None, // LDWDP_ru6
2439 CEFBS_None, // LDWSP_lru6
2440 CEFBS_None, // LDWSP_ru6
2441 CEFBS_None, // LDW_2rus
2442 CEFBS_None, // LDW_3r
2443 CEFBS_None, // LMUL_l6r
2444 CEFBS_None, // LSS_3r
2445 CEFBS_None, // LSUB_l5r
2446 CEFBS_None, // LSU_3r
2447 CEFBS_None, // MACCS_l4r
2448 CEFBS_None, // MACCU_l4r
2449 CEFBS_None, // MJOIN_1r
2450 CEFBS_None, // MKMSK_2r
2451 CEFBS_None, // MKMSK_rus
2452 CEFBS_None, // MSYNC_1r
2453 CEFBS_None, // MUL_l3r
2454 CEFBS_None, // NEG
2455 CEFBS_None, // NOT
2456 CEFBS_None, // OR_3r
2457 CEFBS_None, // OUTCT_2r
2458 CEFBS_None, // OUTCT_rus
2459 CEFBS_None, // OUTPW_l2rus
2460 CEFBS_None, // OUTSHR_2r
2461 CEFBS_None, // OUTT_2r
2462 CEFBS_None, // OUT_2r
2463 CEFBS_None, // PEEK_2r
2464 CEFBS_None, // REMS_l3r
2465 CEFBS_None, // REMU_l3r
2466 CEFBS_None, // RETSP_lu6
2467 CEFBS_None, // RETSP_u6
2468 CEFBS_None, // SETCLK_l2r
2469 CEFBS_None, // SETCP_1r
2470 CEFBS_None, // SETC_l2r
2471 CEFBS_None, // SETC_lru6
2472 CEFBS_None, // SETC_ru6
2473 CEFBS_None, // SETDP_1r
2474 CEFBS_None, // SETD_2r
2475 CEFBS_None, // SETEV_1r
2476 CEFBS_None, // SETKEP_0R
2477 CEFBS_None, // SETN_l2r
2478 CEFBS_None, // SETPSC_2r
2479 CEFBS_None, // SETPS_l2r
2480 CEFBS_None, // SETPT_2r
2481 CEFBS_None, // SETRDY_l2r
2482 CEFBS_None, // SETSP_1r
2483 CEFBS_None, // SETSR_branch_lu6
2484 CEFBS_None, // SETSR_branch_u6
2485 CEFBS_None, // SETSR_lu6
2486 CEFBS_None, // SETSR_u6
2487 CEFBS_None, // SETTW_l2r
2488 CEFBS_None, // SETV_1r
2489 CEFBS_None, // SEXT_2r
2490 CEFBS_None, // SEXT_rus
2491 CEFBS_None, // SHL_2rus
2492 CEFBS_None, // SHL_3r
2493 CEFBS_None, // SHR_2rus
2494 CEFBS_None, // SHR_3r
2495 CEFBS_None, // SSYNC_0r
2496 CEFBS_None, // ST16_l3r
2497 CEFBS_None, // ST8_l3r
2498 CEFBS_None, // STET_0R
2499 CEFBS_None, // STSED_0R
2500 CEFBS_None, // STSPC_0R
2501 CEFBS_None, // STSSR_0R
2502 CEFBS_None, // STWDP_lru6
2503 CEFBS_None, // STWDP_ru6
2504 CEFBS_None, // STWSP_lru6
2505 CEFBS_None, // STWSP_ru6
2506 CEFBS_None, // STW_2rus
2507 CEFBS_None, // STW_l3r
2508 CEFBS_None, // SUB_2rus
2509 CEFBS_None, // SUB_3r
2510 CEFBS_None, // SYNCR_1r
2511 CEFBS_None, // TESTCT_2r
2512 CEFBS_None, // TESTLCL_l2r
2513 CEFBS_None, // TESTWCT_2r
2514 CEFBS_None, // TSETMR_2r
2515 CEFBS_None, // TSETR_3r
2516 CEFBS_None, // TSTART_1R
2517 CEFBS_None, // WAITEF_1R
2518 CEFBS_None, // WAITET_1R
2519 CEFBS_None, // WAITEU_0R
2520 CEFBS_None, // XOR_l3r
2521 CEFBS_None, // ZEXT_2r
2522 CEFBS_None, // ZEXT_rus
2523 };
2524
2525 assert(Opcode < 549);
2526 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2527}
2528
2529
2530} // namespace llvm::XCore_MC
2531
2532#endif // GET_COMPUTE_FEATURES
2533
2534#ifdef GET_AVAILABLE_OPCODE_CHECKER
2535#undef GET_AVAILABLE_OPCODE_CHECKER
2536
2537namespace llvm::XCore_MC {
2538
2539bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2540 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2541 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2542 FeatureBitset MissingFeatures =
2543 (AvailableFeatures & RequiredFeatures) ^
2544 RequiredFeatures;
2545 return !MissingFeatures.any();
2546}
2547
2548} // namespace llvm::XCore_MC
2549
2550#endif // GET_AVAILABLE_OPCODE_CHECKER
2551
2552#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2553#undef ENABLE_INSTR_PREDICATE_VERIFIER
2554
2555#include <sstream>
2556
2557namespace llvm::XCore_MC {
2558
2559#ifndef NDEBUG
2560static const char *SubtargetFeatureNames[] = {
2561 nullptr
2562};
2563
2564#endif // NDEBUG
2565
2566void verifyInstructionPredicates(
2567 unsigned Opcode, const FeatureBitset &Features) {
2568#ifndef NDEBUG
2569 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2570 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2571 FeatureBitset MissingFeatures =
2572 (AvailableFeatures & RequiredFeatures) ^
2573 RequiredFeatures;
2574 if (MissingFeatures.any()) {
2575 std::ostringstream Msg;
2576 Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
2577 << " instruction but the ";
2578 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2579 if (MissingFeatures.test(i))
2580 Msg << SubtargetFeatureNames[i] << " ";
2581 Msg << "predicate(s) are not met";
2582 report_fatal_error(Msg.str().c_str());
2583 }
2584#endif // NDEBUG
2585}
2586
2587} // namespace llvm::XCore_MC
2588
2589#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2590
2591