1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::XCore {
13
14 enum {
15 PHI = 0, // Target.td:1324
16 INLINEASM = 1, // Target.td:1330
17 INLINEASM_BR = 2, // Target.td:1336
18 CFI_INSTRUCTION = 3, // Target.td:1345
19 EH_LABEL = 4, // Target.td:1354
20 GC_LABEL = 5, // Target.td:1363
21 ANNOTATION_LABEL = 6, // Target.td:1372
22 KILL = 7, // Target.td:1380
23 EXTRACT_SUBREG = 8, // Target.td:1387
24 INSERT_SUBREG = 9, // Target.td:1393
25 IMPLICIT_DEF = 10, // Target.td:1400
26 INIT_UNDEF = 11, // Target.td:1409
27 SUBREG_TO_REG = 12, // Target.td:1416
28 COPY_TO_REGCLASS = 13, // Target.td:1422
29 DBG_VALUE = 14, // Target.td:1429
30 DBG_VALUE_LIST = 15, // Target.td:1436
31 DBG_INSTR_REF = 16, // Target.td:1443
32 DBG_PHI = 17, // Target.td:1450
33 DBG_LABEL = 18, // Target.td:1457
34 REG_SEQUENCE = 19, // Target.td:1464
35 COPY = 20, // Target.td:1471
36 COPY_LANEMASK = 21, // Target.td:1479
37 BUNDLE = 22, // Target.td:1486
38 LIFETIME_START = 23, // Target.td:1492
39 LIFETIME_END = 24, // Target.td:1499
40 PSEUDO_PROBE = 25, // Target.td:1506
41 ARITH_FENCE = 26, // Target.td:1513
42 STACKMAP = 27, // Target.td:1522
43 FENTRY_CALL = 28, // Target.td:1657
44 PATCHPOINT = 29, // Target.td:1530
45 LOAD_STACK_GUARD = 30, // Target.td:1548
46 PREALLOCATED_SETUP = 31, // Target.td:1556
47 PREALLOCATED_ARG = 32, // Target.td:1562
48 STATEPOINT = 33, // Target.td:1539
49 LOCAL_ESCAPE = 34, // Target.td:1568
50 FAULTING_OP = 35, // Target.td:1577
51 PATCHABLE_OP = 36, // Target.td:1597
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1605
53 PATCHABLE_RET = 38, // Target.td:1612
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1621
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1629
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1637
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1647
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1667
59 FAKE_USE = 44, // Target.td:1587
60 MEMBARRIER = 45, // Target.td:1673
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1681
62 RELOC_NONE = 47, // Target.td:1689
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1701
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1697
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1705
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1709
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1929
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1921
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1936
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1516
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1529
96 G_INSERT = 81, // GenericOpcodes.td:1538
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1548
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1568
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1578
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1585
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1943
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1481
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1482
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1483
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1484
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1485
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1486
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1487
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1488
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1494
150 G_PREFETCH = 135, // GenericOpcodes.td:1501
151 G_BRCOND = 136, // GenericOpcodes.td:1641
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1650
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1673
154 G_INTRINSIC = 139, // GenericOpcodes.td:1593
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1600
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1609
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1617
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1631
265 G_BRJT = 250, // GenericOpcodes.td:1661
266 G_VSCALE = 251, // GenericOpcodes.td:1559
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1705
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1713
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1721
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1729
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1740
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1748
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1756
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1763
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1813
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1814
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1815
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1816
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1817
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1818
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1819
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1820
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1821
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1822
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1680
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1690
318 G_MEMCPY = 303, // GenericOpcodes.td:1828
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1836
320 G_MEMMOVE = 305, // GenericOpcodes.td:1844
321 G_MEMSET = 306, // GenericOpcodes.td:1852
322 G_BZERO = 307, // GenericOpcodes.td:1859
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1866
324 G_TRAP = 309, // GenericOpcodes.td:1876
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1883
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1889
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1779
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1785
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1791
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1792
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1794
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1795
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1796
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1797
335 G_VECREDUCE_ADD = 320, // GenericOpcodes.td:1799
336 G_VECREDUCE_MUL = 321, // GenericOpcodes.td:1800
337 G_VECREDUCE_AND = 322, // GenericOpcodes.td:1801
338 G_VECREDUCE_OR = 323, // GenericOpcodes.td:1802
339 G_VECREDUCE_XOR = 324, // GenericOpcodes.td:1803
340 G_VECREDUCE_SMAX = 325, // GenericOpcodes.td:1804
341 G_VECREDUCE_SMIN = 326, // GenericOpcodes.td:1805
342 G_VECREDUCE_UMAX = 327, // GenericOpcodes.td:1806
343 G_VECREDUCE_UMIN = 328, // GenericOpcodes.td:1807
344 G_SBFX = 329, // GenericOpcodes.td:1901
345 G_UBFX = 330, // GenericOpcodes.td:1909
346 ADJCALLSTACKDOWN = 331, // XCoreInstrInfo.td:356
347 ADJCALLSTACKUP = 332, // XCoreInstrInfo.td:359
348 BR_JT = 333, // XCoreInstrInfo.td:991
349 BR_JT32 = 334, // XCoreInstrInfo.td:996
350 EH_RETURN = 335, // XCoreInstrInfo.td:370
351 FRAME_TO_ARGS_OFFSET = 336, // XCoreInstrInfo.td:365
352 LDAWFI = 337, // XCoreInstrInfo.td:378
353 LDWFI = 338, // XCoreInstrInfo.td:374
354 SELECT_CC = 339, // XCoreInstrInfo.td:389
355 STWFI = 340, // XCoreInstrInfo.td:382
356 ADD_2rus = 341, // XCoreInstrInfo.td:247
357 ADD_3r = 342, // XCoreInstrInfo.td:244
358 ANDNOT_2r = 343, // XCoreInstrInfo.td:797
359 AND_3r = 344, // XCoreInstrInfo.td:408
360 ASHR_l2rus = 345, // XCoreInstrInfo.td:296
361 ASHR_l3r = 346, // XCoreInstrInfo.td:293
362 BAU_1r = 347, // XCoreInstrInfo.td:986
363 BITREV_l2r = 348, // XCoreInstrInfo.td:925
364 BLACP_lu10 = 349, // XCoreInstrInfo.td:746
365 BLACP_u10 = 350, // XCoreInstrInfo.td:744
366 BLAT_lu6 = 351, // XCoreInstrInfo.td:340
367 BLAT_u6 = 352, // XCoreInstrInfo.td:339
368 BLA_1r = 353, // XCoreInstrInfo.td:1025
369 BLRB_lu10 = 354, // XCoreInstrInfo.td:756
370 BLRB_u10 = 355, // XCoreInstrInfo.td:754
371 BLRF_lu10 = 356, // XCoreInstrInfo.td:751
372 BLRF_u10 = 357, // XCoreInstrInfo.td:748
373 BRBF_lru6 = 358, // XCoreInstrInfo.td:318
374 BRBF_ru6 = 359, // XCoreInstrInfo.td:316
375 BRBT_lru6 = 360, // XCoreInstrInfo.td:318
376 BRBT_ru6 = 361, // XCoreInstrInfo.td:316
377 BRBU_lu6 = 362, // XCoreInstrInfo.td:679
378 BRBU_u6 = 363, // XCoreInstrInfo.td:677
379 BRFF_lru6 = 364, // XCoreInstrInfo.td:311
380 BRFF_ru6 = 365, // XCoreInstrInfo.td:309
381 BRFT_lru6 = 366, // XCoreInstrInfo.td:311
382 BRFT_ru6 = 367, // XCoreInstrInfo.td:309
383 BRFU_lu6 = 368, // XCoreInstrInfo.td:683
384 BRFU_u6 = 369, // XCoreInstrInfo.td:681
385 BRU_1r = 370, // XCoreInstrInfo.td:1001
386 BYTEREV_l2r = 371, // XCoreInstrInfo.td:929
387 CHKCT_2r = 372, // XCoreInstrInfo.td:863
388 CHKCT_rus = 373, // XCoreInstrInfo.td:867
389 CLRE_0R = 374, // XCoreInstrInfo.td:1070
390 CLRPT_1R = 375, // XCoreInstrInfo.td:1065
391 CLRSR_branch_lu6 = 376, // XCoreInstrInfo.td:340
392 CLRSR_branch_u6 = 377, // XCoreInstrInfo.td:339
393 CLRSR_lu6 = 378, // XCoreInstrInfo.td:334
394 CLRSR_u6 = 379, // XCoreInstrInfo.td:332
395 CLZ_l2r = 380, // XCoreInstrInfo.td:933
396 CRC8_l4r = 381, // XCoreInstrInfo.td:533
397 CRC_l3r = 382, // XCoreInstrInfo.td:494
398 DCALL_0R = 383, // XCoreInstrInfo.td:1072
399 DENTSP_0R = 384, // XCoreInstrInfo.td:1075
400 DGETREG_1r = 385, // XCoreInstrInfo.td:1048
401 DIVS_l3r = 386, // XCoreInstrInfo.td:485
402 DIVU_l3r = 387, // XCoreInstrInfo.td:486
403 DRESTSP_0R = 388, // XCoreInstrInfo.td:1078
404 DRET_0R = 389, // XCoreInstrInfo.td:1080
405 ECALLF_1r = 390, // XCoreInstrInfo.td:1018
406 ECALLT_1r = 391, // XCoreInstrInfo.td:1013
407 EDU_1r = 392, // XCoreInstrInfo.td:1050
408 EEF_2r = 393, // XCoreInstrInfo.td:915
409 EET_2r = 394, // XCoreInstrInfo.td:918
410 EEU_1r = 395, // XCoreInstrInfo.td:1053
411 ENDIN_2r = 396, // XCoreInstrInfo.td:911
412 ENTSP_lu6 = 397, // XCoreInstrInfo.td:340
413 ENTSP_u6 = 398, // XCoreInstrInfo.td:339
414 EQ_2rus = 399, // XCoreInstrInfo.td:255
415 EQ_3r = 400, // XCoreInstrInfo.td:253
416 EXTDP_lu6 = 401, // XCoreInstrInfo.td:340
417 EXTDP_u6 = 402, // XCoreInstrInfo.td:339
418 EXTSP_lu6 = 403, // XCoreInstrInfo.td:340
419 EXTSP_u6 = 404, // XCoreInstrInfo.td:339
420 FREER_1r = 405, // XCoreInstrInfo.td:1034
421 FREET_0R = 406, // XCoreInstrInfo.td:1082
422 GETD_l2r = 407, // XCoreInstrInfo.td:937
423 GETED_0R = 408, // XCoreInstrInfo.td:1089
424 GETET_0R = 409, // XCoreInstrInfo.td:1093
425 GETID_0R = 410, // XCoreInstrInfo.td:1085
426 GETKEP_0R = 411, // XCoreInstrInfo.td:1097
427 GETKSP_0R = 412, // XCoreInstrInfo.td:1100
428 GETN_l2r = 413, // XCoreInstrInfo.td:940
429 GETPS_l2r = 414, // XCoreInstrInfo.td:951
430 GETR_rus = 415, // XCoreInstrInfo.td:811
431 GETSR_lu6 = 416, // XCoreInstrInfo.td:340
432 GETSR_u6 = 417, // XCoreInstrInfo.td:339
433 GETST_2r = 418, // XCoreInstrInfo.td:887
434 GETTS_2r = 419, // XCoreInstrInfo.td:815
435 INCT_2r = 420, // XCoreInstrInfo.td:845
436 INITCP_2r = 421, // XCoreInstrInfo.td:899
437 INITDP_2r = 422, // XCoreInstrInfo.td:903
438 INITLR_l2r = 423, // XCoreInstrInfo.td:959
439 INITPC_2r = 424, // XCoreInstrInfo.td:895
440 INITSP_2r = 425, // XCoreInstrInfo.td:891
441 INPW_l2rus = 426, // XCoreInstrInfo.td:511
442 INSHR_2r = 427, // XCoreInstrInfo.td:858
443 INT_2r = 428, // XCoreInstrInfo.td:849
444 IN_2r = 429, // XCoreInstrInfo.td:853
445 KCALL_1r = 430, // XCoreInstrInfo.td:1057
446 KCALL_lu6 = 431, // XCoreInstrInfo.td:340
447 KCALL_u6 = 432, // XCoreInstrInfo.td:339
448 KENTSP_lu6 = 433, // XCoreInstrInfo.td:340
449 KENTSP_u6 = 434, // XCoreInstrInfo.td:339
450 KRESTSP_lu6 = 435, // XCoreInstrInfo.td:340
451 KRESTSP_u6 = 436, // XCoreInstrInfo.td:339
452 KRET_0R = 437, // XCoreInstrInfo.td:1105
453 LADD_l5r = 438, // XCoreInstrInfo.td:541
454 LD16S_3r = 439, // XCoreInstrInfo.td:420
455 LD8U_3r = 440, // XCoreInstrInfo.td:424
456 LDA16B_l3r = 441, // XCoreInstrInfo.td:476
457 LDA16F_l3r = 442, // XCoreInstrInfo.td:470
458 LDAPB_lu10 = 443, // XCoreInstrInfo.td:732
459 LDAPB_u10 = 444, // XCoreInstrInfo.td:728
460 LDAPF_lu10 = 445, // XCoreInstrInfo.td:724
461 LDAPF_lu10_ba = 446, // XCoreInstrInfo.td:737
462 LDAPF_u10 = 447, // XCoreInstrInfo.td:722
463 LDAWB_l2rus = 448, // XCoreInstrInfo.td:466
464 LDAWB_l3r = 449, // XCoreInstrInfo.td:459
465 LDAWCP_lu6 = 450, // XCoreInstrInfo.td:692
466 LDAWCP_u6 = 451, // XCoreInstrInfo.td:688
467 LDAWDP_lru6 = 452, // XCoreInstrInfo.td:574
468 LDAWDP_ru6 = 453, // XCoreInstrInfo.td:570
469 LDAWF_l2rus = 454, // XCoreInstrInfo.td:455
470 LDAWF_l3r = 455, // XCoreInstrInfo.td:448
471 LDAWSP_lru6 = 456, // XCoreInstrInfo.td:628
472 LDAWSP_ru6 = 457, // XCoreInstrInfo.td:625
473 LDC_lru6 = 458, // XCoreInstrInfo.td:637
474 LDC_ru6 = 459, // XCoreInstrInfo.td:634
475 LDET_0R = 460, // XCoreInstrInfo.td:1108
476 LDIVU_l5r = 461, // XCoreInstrInfo.td:553
477 LDSED_0R = 462, // XCoreInstrInfo.td:1110
478 LDSPC_0R = 463, // XCoreInstrInfo.td:1112
479 LDSSR_0R = 464, // XCoreInstrInfo.td:1114
480 LDWCP_lru6 = 465, // XCoreInstrInfo.td:598
481 LDWCP_lu10 = 466, // XCoreInstrInfo.td:763
482 LDWCP_ru6 = 467, // XCoreInstrInfo.td:596
483 LDWCP_u10 = 468, // XCoreInstrInfo.td:761
484 LDWDP_lru6 = 469, // XCoreInstrInfo.td:582
485 LDWDP_ru6 = 470, // XCoreInstrInfo.td:579
486 LDWSP_lru6 = 471, // XCoreInstrInfo.td:619
487 LDWSP_ru6 = 472, // XCoreInstrInfo.td:615
488 LDW_2rus = 473, // XCoreInstrInfo.td:416
489 LDW_3r = 474, // XCoreInstrInfo.td:412
490 LMUL_l6r = 475, // XCoreInstrInfo.td:559
491 LSS_3r = 476, // XCoreInstrInfo.td:405
492 LSUB_l5r = 477, // XCoreInstrInfo.td:547
493 LSU_3r = 478, // XCoreInstrInfo.td:406
494 MACCS_l4r = 479, // XCoreInstrInfo.td:526
495 MACCU_l4r = 480, // XCoreInstrInfo.td:521
496 MJOIN_1r = 481, // XCoreInstrInfo.td:981
497 MKMSK_2r = 482, // XCoreInstrInfo.td:807
498 MKMSK_rus = 483, // XCoreInstrInfo.td:804
499 MSYNC_1r = 484, // XCoreInstrInfo.td:978
500 MUL_l3r = 485, // XCoreInstrInfo.td:482
501 NEG = 486, // XCoreInstrInfo.td:771
502 NOT = 487, // XCoreInstrInfo.td:768
503 OR_3r = 488, // XCoreInstrInfo.td:409
504 OUTCT_2r = 489, // XCoreInstrInfo.td:823
505 OUTCT_rus = 490, // XCoreInstrInfo.td:827
506 OUTPW_l2rus = 491, // XCoreInstrInfo.td:515
507 OUTSHR_2r = 492, // XCoreInstrInfo.td:840
508 OUTT_2r = 493, // XCoreInstrInfo.td:831
509 OUT_2r = 494, // XCoreInstrInfo.td:835
510 PEEK_2r = 495, // XCoreInstrInfo.td:907
511 REMS_l3r = 496, // XCoreInstrInfo.td:487
512 REMU_l3r = 497, // XCoreInstrInfo.td:488
513 RETSP_lu6 = 498, // XCoreInstrInfo.td:327
514 RETSP_u6 = 499, // XCoreInstrInfo.td:325
515 SETCLK_l2r = 500, // XCoreInstrInfo.td:963
516 SETCP_1r = 501, // XCoreInstrInfo.td:1010
517 SETC_l2r = 502, // XCoreInstrInfo.td:943
518 SETC_lru6 = 503, // XCoreInstrInfo.td:645
519 SETC_ru6 = 504, // XCoreInstrInfo.td:641
520 SETDP_1r = 505, // XCoreInstrInfo.td:1007
521 SETD_2r = 506, // XCoreInstrInfo.td:879
522 SETEV_1r = 507, // XCoreInstrInfo.td:1043
523 SETKEP_0R = 508, // XCoreInstrInfo.td:1118
524 SETN_l2r = 509, // XCoreInstrInfo.td:967
525 SETPSC_2r = 510, // XCoreInstrInfo.td:883
526 SETPS_l2r = 511, // XCoreInstrInfo.td:955
527 SETPT_2r = 512, // XCoreInstrInfo.td:819
528 SETRDY_l2r = 513, // XCoreInstrInfo.td:970
529 SETSP_1r = 514, // XCoreInstrInfo.td:1004
530 SETSR_branch_lu6 = 515, // XCoreInstrInfo.td:340
531 SETSR_branch_u6 = 516, // XCoreInstrInfo.td:339
532 SETSR_lu6 = 517, // XCoreInstrInfo.td:334
533 SETSR_u6 = 518, // XCoreInstrInfo.td:332
534 SETTW_l2r = 519, // XCoreInstrInfo.td:947
535 SETV_1r = 520, // XCoreInstrInfo.td:1039
536 SEXT_2r = 521, // XCoreInstrInfo.td:781
537 SEXT_rus = 522, // XCoreInstrInfo.td:775
538 SHL_2rus = 523, // XCoreInstrInfo.td:264
539 SHL_3r = 524, // XCoreInstrInfo.td:261
540 SHR_2rus = 525, // XCoreInstrInfo.td:264
541 SHR_3r = 526, // XCoreInstrInfo.td:261
542 SSYNC_0r = 527, // XCoreInstrInfo.td:1120
543 ST16_l3r = 528, // XCoreInstrInfo.td:502
544 ST8_l3r = 529, // XCoreInstrInfo.td:506
545 STET_0R = 530, // XCoreInstrInfo.td:1125
546 STSED_0R = 531, // XCoreInstrInfo.td:1127
547 STSPC_0R = 532, // XCoreInstrInfo.td:1129
548 STSSR_0R = 533, // XCoreInstrInfo.td:1131
549 STWDP_lru6 = 534, // XCoreInstrInfo.td:590
550 STWDP_ru6 = 535, // XCoreInstrInfo.td:587
551 STWSP_lru6 = 536, // XCoreInstrInfo.td:609
552 STWSP_ru6 = 537, // XCoreInstrInfo.td:605
553 STW_2rus = 538, // XCoreInstrInfo.td:434
554 STW_l3r = 539, // XCoreInstrInfo.td:430
555 SUB_2rus = 540, // XCoreInstrInfo.td:247
556 SUB_3r = 541, // XCoreInstrInfo.td:244
557 SYNCR_1r = 542, // XCoreInstrInfo.td:1030
558 TESTCT_2r = 543, // XCoreInstrInfo.td:871
559 TESTLCL_l2r = 544, // XCoreInstrInfo.td:974
560 TESTWCT_2r = 545, // XCoreInstrInfo.td:875
561 TSETMR_2r = 546, // XCoreInstrInfo.td:921
562 TSETR_3r = 547, // XCoreInstrInfo.td:444
563 TSTART_1R = 548, // XCoreInstrInfo.td:1063
564 WAITEF_1R = 549, // XCoreInstrInfo.td:1059
565 WAITET_1R = 550, // XCoreInstrInfo.td:1061
566 WAITEU_0R = 551, // XCoreInstrInfo.td:1136
567 XOR_l3r = 552, // XCoreInstrInfo.td:490
568 ZEXT_2r = 553, // XCoreInstrInfo.td:792
569 ZEXT_rus = 554, // XCoreInstrInfo.td:786
570 INSTRUCTION_LIST_END = 555
571 };
572
573} // namespace llvm::XCore
574
575#endif // GET_INSTRINFO_ENUM
576
577#ifdef GET_INSTRINFO_SCHED_ENUM
578#undef GET_INSTRINFO_SCHED_ENUM
579
580namespace llvm::XCore::Sched {
581
582 enum {
583 NoInstrModel = 0,
584 SCHED_LIST_END = 1
585 };
586
587} // namespace llvm::XCore::Sched
588
589#endif // GET_INSTRINFO_SCHED_ENUM
590
591#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
592
593namespace llvm {
594
595struct XCoreInstrTable {
596 MCInstrDesc Insts[555];
597 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
598 MCPhysReg ImplicitOps[11];
599 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
600 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
601 MCOperandInfo OperandInfo[209];
602};
603} // namespace llvm
604
605#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
606
607#ifdef GET_INSTRINFO_MC_DESC
608#undef GET_INSTRINFO_MC_DESC
609
610namespace llvm {
611
612static_assert((sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
613static constexpr unsigned XCoreOpInfoBase = (sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) / sizeof(MCOperandInfo);
614
615extern const XCoreInstrTable XCoreDescs = {
616 {
617 { 554, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_rus
618 { 553, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_2r
619 { 552, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_l3r
620 { 551, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEU_0R
621 { 550, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITET_1R
622 { 549, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEF_1R
623 { 548, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSTART_1R
624 { 547, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETR_3r
625 { 546, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETMR_2r
626 { 545, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTWCT_2r
627 { 544, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTLCL_l2r
628 { 543, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTCT_2r
629 { 542, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SYNCR_1r
630 { 541, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_3r
631 { 540, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_2rus
632 { 539, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_l3r
633 { 538, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_2rus
634 { 537, 2, 0, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_ru6
635 { 536, 2, 0, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_lru6
636 { 535, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_ru6
637 { 534, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_lru6
638 { 533, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSSR_0R
639 { 532, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSPC_0R
640 { 531, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSED_0R
641 { 530, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STET_0R
642 { 529, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST8_l3r
643 { 528, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST16_l3r
644 { 527, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SSYNC_0r
645 { 526, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_3r
646 { 525, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_2rus
647 { 524, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_3r
648 { 523, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_2rus
649 { 522, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_rus
650 { 521, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_2r
651 { 520, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETV_1r
652 { 519, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETTW_l2r
653 { 518, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_u6
654 { 517, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_lu6
655 { 516, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_u6
656 { 515, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_lu6
657 { 514, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 28, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSP_1r
658 { 513, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETRDY_l2r
659 { 512, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPT_2r
660 { 511, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPS_l2r
661 { 510, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPSC_2r
662 { 509, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETN_l2r
663 { 508, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETKEP_0R
664 { 507, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETEV_1r
665 { 506, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETD_2r
666 { 505, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETDP_1r
667 { 504, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_ru6
668 { 503, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_lru6
669 { 502, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_l2r
670 { 501, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCP_1r
671 { 500, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCLK_l2r
672 { 499, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_u6
673 { 498, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_lu6
674 { 497, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMU_l3r
675 { 496, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMS_l3r
676 { 495, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PEEK_2r
677 { 494, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUT_2r
678 { 493, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTT_2r
679 { 492, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTSHR_2r
680 { 491, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTPW_l2rus
681 { 490, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_rus
682 { 489, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_2r
683 { 488, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_3r
684 { 487, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
685 { 486, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG
686 { 485, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_l3r
687 { 484, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MSYNC_1r
688 { 483, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_rus
689 { 482, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_2r
690 { 481, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MJOIN_1r
691 { 480, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCU_l4r
692 { 479, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCS_l4r
693 { 478, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSU_3r
694 { 477, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSUB_l5r
695 { 476, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSS_3r
696 { 475, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 189, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LMUL_l6r
697 { 474, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_3r
698 { 473, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_2rus
699 { 472, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_ru6
700 { 471, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_lru6
701 { 470, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_ru6
702 { 469, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_lru6
703 { 468, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_u10
704 { 467, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_ru6
705 { 466, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lu10
706 { 465, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lru6
707 { 464, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSSR_0R
708 { 463, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSPC_0R
709 { 462, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSED_0R
710 { 461, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIVU_l5r
711 { 460, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDET_0R
712 { 459, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_ru6
713 { 458, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_lru6
714 { 457, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_ru6
715 { 456, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_lru6
716 { 455, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l3r
717 { 454, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l2rus
718 { 453, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_ru6
719 { 452, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_lru6
720 { 451, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_u6
721 { 450, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_lu6
722 { 449, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l3r
723 { 448, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l2rus
724 { 447, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_u10
725 { 446, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10_ba
726 { 445, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10
727 { 444, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_u10
728 { 443, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_lu10
729 { 442, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16F_l3r
730 { 441, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16B_l3r
731 { 440, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD8U_3r
732 { 439, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD16S_3r
733 { 438, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LADD_l5r
734 { 437, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRET_0R
735 { 436, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_u6
736 { 435, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_lu6
737 { 434, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_u6
738 { 433, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_lu6
739 { 432, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_u6
740 { 431, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_lu6
741 { 430, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_1r
742 { 429, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IN_2r
743 { 428, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INT_2r
744 { 427, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSHR_2r
745 { 426, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INPW_l2rus
746 { 425, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITSP_2r
747 { 424, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITPC_2r
748 { 423, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITLR_l2r
749 { 422, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITDP_2r
750 { 421, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITCP_2r
751 { 420, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INCT_2r
752 { 419, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETTS_2r
753 { 418, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETST_2r
754 { 417, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_u6
755 { 416, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_lu6
756 { 415, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETR_rus
757 { 414, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETPS_l2r
758 { 413, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETN_l2r
759 { 412, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKSP_0R
760 { 411, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKEP_0R
761 { 410, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETID_0R
762 { 409, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETET_0R
763 { 408, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETED_0R
764 { 407, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETD_l2r
765 { 406, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREET_0R
766 { 405, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREER_1r
767 { 404, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_u6
768 { 403, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_lu6
769 { 402, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_u6
770 { 401, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_lu6
771 { 400, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_3r
772 { 399, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_2rus
773 { 398, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_u6
774 { 397, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_lu6
775 { 396, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENDIN_2r
776 { 395, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEU_1r
777 { 394, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EET_2r
778 { 393, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEF_2r
779 { 392, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EDU_1r
780 { 391, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLT_1r
781 { 390, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLF_1r
782 { 389, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRET_0R
783 { 388, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRESTSP_0R
784 { 387, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVU_l3r
785 { 386, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVS_l3r
786 { 385, 1, 1, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DGETREG_1r
787 { 384, 0, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DENTSP_0R
788 { 383, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DCALL_0R
789 { 382, 4, 1, 4, 0, 0, 0, XCoreOpInfoBase + 178, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC_l3r
790 { 381, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 173, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC8_l4r
791 { 380, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_l2r
792 { 379, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_u6
793 { 378, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_lu6
794 { 377, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_u6
795 { 376, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_lu6
796 { 375, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRPT_1R
797 { 374, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRE_0R
798 { 373, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_rus
799 { 372, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_2r
800 { 371, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BYTEREV_l2r
801 { 370, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRU_1r
802 { 369, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_u6
803 { 368, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_lu6
804 { 367, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_ru6
805 { 366, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_lru6
806 { 365, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_ru6
807 { 364, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_lru6
808 { 363, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_u6
809 { 362, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_lu6
810 { 361, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_ru6
811 { 360, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_lru6
812 { 359, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_ru6
813 { 358, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_lru6
814 { 357, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_u10
815 { 356, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_lu10
816 { 355, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_u10
817 { 354, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_lu10
818 { 353, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 28, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLA_1r
819 { 352, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_u6
820 { 351, 1, 0, 4, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_lu6
821 { 350, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_u10
822 { 349, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_lu10
823 { 348, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITREV_l2r
824 { 347, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BAU_1r
825 { 346, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l3r
826 { 345, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l2rus
827 { 344, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_3r
828 { 343, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_2r
829 { 342, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_3r
830 { 341, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_2rus
831 { 340, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWFI
832 { 339, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_CC
833 { 338, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWFI
834 { 337, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWFI
835 { 336, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FRAME_TO_ARGS_OFFSET
836 { 335, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_RETURN
837 { 334, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT32
838 { 333, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT
839 { 332, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
840 { 331, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
841 { 330, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
842 { 329, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
843 { 328, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
844 { 327, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
845 { 326, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
846 { 325, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
847 { 324, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
848 { 323, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
849 { 322, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
850 { 321, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
851 { 320, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
852 { 319, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
853 { 318, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
854 { 317, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
855 { 316, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
856 { 315, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
857 { 314, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
858 { 313, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
859 { 312, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
860 { 311, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
861 { 310, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
862 { 309, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
863 { 308, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
864 { 307, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
865 { 306, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
866 { 305, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
867 { 304, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
868 { 303, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
869 { 302, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
870 { 301, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
871 { 300, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
872 { 299, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
873 { 298, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
874 { 297, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
875 { 296, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
876 { 295, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
877 { 294, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
878 { 293, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
879 { 292, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
880 { 291, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
881 { 290, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
882 { 289, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
883 { 288, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
884 { 287, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
885 { 286, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
886 { 285, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
887 { 284, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
888 { 283, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
889 { 282, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
890 { 281, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
891 { 280, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
892 { 279, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
893 { 278, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
894 { 277, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
895 { 276, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
896 { 275, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
897 { 274, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
898 { 273, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
899 { 272, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
900 { 271, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
901 { 270, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
902 { 269, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
903 { 268, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
904 { 267, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
905 { 266, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
906 { 265, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
907 { 264, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
908 { 263, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
909 { 262, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
910 { 261, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
911 { 260, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
912 { 259, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
913 { 258, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
914 { 257, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
915 { 256, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
916 { 255, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
917 { 254, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
918 { 253, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
919 { 252, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
920 { 251, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
921 { 250, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
922 { 249, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
923 { 248, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
924 { 247, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
925 { 246, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
926 { 245, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
927 { 244, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
928 { 243, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
929 { 242, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
930 { 241, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
931 { 240, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
932 { 239, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
933 { 238, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
934 { 237, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
935 { 236, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
936 { 235, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
937 { 234, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
938 { 233, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
939 { 232, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
940 { 231, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
941 { 230, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
942 { 229, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
943 { 228, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
944 { 227, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
945 { 226, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
946 { 225, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
947 { 224, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
948 { 223, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
949 { 222, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
950 { 221, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
951 { 220, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
952 { 219, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
953 { 218, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
954 { 217, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
955 { 216, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
956 { 215, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
957 { 214, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
958 { 213, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
959 { 212, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
960 { 211, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
961 { 210, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
962 { 209, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
963 { 208, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
964 { 207, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
965 { 206, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
966 { 205, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
967 { 204, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
968 { 203, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
969 { 202, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
970 { 201, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
971 { 200, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
972 { 199, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
973 { 198, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
974 { 197, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
975 { 196, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
976 { 195, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
977 { 194, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
978 { 193, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
979 { 192, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
980 { 191, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
981 { 190, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
982 { 189, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
983 { 188, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
984 { 187, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
985 { 186, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
986 { 185, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
987 { 184, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
988 { 183, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
989 { 182, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
990 { 181, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
991 { 180, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
992 { 179, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
993 { 178, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
994 { 177, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
995 { 176, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
996 { 175, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
997 { 174, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
998 { 173, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
999 { 172, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1000 { 171, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1001 { 170, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1002 { 169, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1003 { 168, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1004 { 167, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1005 { 166, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1006 { 165, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1007 { 164, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1008 { 163, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1009 { 162, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1010 { 161, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1011 { 160, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1012 { 159, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1013 { 158, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1014 { 157, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1015 { 156, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1016 { 155, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1017 { 154, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1018 { 153, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1019 { 152, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1020 { 151, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1021 { 150, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1022 { 149, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1023 { 148, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1024 { 147, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1025 { 146, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1026 { 145, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1027 { 144, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1028 { 143, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1029 { 142, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1030 { 141, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1031 { 140, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1032 { 139, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1033 { 138, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1034 { 137, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1035 { 136, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1036 { 135, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1037 { 134, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1038 { 133, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1039 { 132, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1040 { 131, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1041 { 130, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1042 { 129, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1043 { 128, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1044 { 127, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1045 { 126, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1046 { 125, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1047 { 124, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1048 { 123, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1049 { 122, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1050 { 121, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1051 { 120, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1052 { 119, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1053 { 118, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1054 { 117, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1055 { 116, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1056 { 115, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1057 { 114, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1058 { 113, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1059 { 112, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1060 { 111, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1061 { 110, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1062 { 109, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1063 { 108, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1064 { 107, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1065 { 106, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1066 { 105, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1067 { 104, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1068 { 103, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1069 { 102, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1070 { 101, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1071 { 100, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1072 { 99, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1073 { 98, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1074 { 97, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1075 { 96, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1076 { 95, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1077 { 94, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1078 { 93, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1079 { 92, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1080 { 91, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1081 { 90, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1082 { 89, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1083 { 88, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1084 { 87, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1085 { 86, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1086 { 85, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1087 { 84, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1088 { 83, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1089 { 82, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1090 { 81, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1091 { 80, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1092 { 79, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1093 { 78, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1094 { 77, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1095 { 76, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1096 { 75, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1097 { 74, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1098 { 73, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1099 { 72, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1100 { 71, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1101 { 70, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1102 { 69, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1103 { 68, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1104 { 67, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1105 { 66, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1106 { 65, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1107 { 64, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1108 { 63, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1109 { 62, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1110 { 61, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1111 { 60, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1112 { 59, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1113 { 58, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1114 { 57, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1115 { 56, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1116 { 55, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1117 { 54, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1118 { 53, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1119 { 52, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1120 { 51, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1121 { 50, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1122 { 49, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1123 { 48, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1124 { 47, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1125 { 46, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1126 { 45, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1127 { 44, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1128 { 43, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1129 { 42, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13918
1130 { 41, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13917
1131 { 40, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1132 { 39, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1133 { 38, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1134 { 37, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1135 { 36, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1136 { 35, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1137 { 34, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1138 { 33, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1139 { 32, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13916
1140 { 31, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1141 { 30, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13555
1142 { 29, 6, 1, 0, 0, 0, 0, XCoreOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1143 { 28, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1144 { 27, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1145 { 26, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1146 { 25, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1147 { 24, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1148 { 23, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1149 { 22, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1150 { 21, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1151 { 20, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1152 { 19, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1153 { 18, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1154 { 17, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1155 { 16, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1156 { 15, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1157 { 14, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1158 { 13, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1159 { 12, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1160 { 11, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1161 { 10, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1162 { 9, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1163 { 8, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1164 { 7, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1165 { 6, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1166 { 5, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1167 { 4, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1168 { 3, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1169 { 2, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1170 { 1, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1171 { 0, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1172 }, {
1173 /* 0 */
1174 /* 0 */ XCore::SP, XCore::SP,
1175 /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
1176 /* 9 */ XCore::R11,
1177 /* 10 */ XCore::SP,
1178 }, {
1179 0
1180 }, {
1181 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1182 /* 1 */
1183 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1184 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1185 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1186 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1187 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1188 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1189 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1190 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1191 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1192 /* 28 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1193 /* 29 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1194 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1195 /* 34 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1196 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1197 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1198 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1199 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1200 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1201 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1202 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1203 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1204 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1205 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1206 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1207 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1208 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1209 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1210 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1211 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1212 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1213 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1214 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1215 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1216 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1217 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1218 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1219 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1220 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1221 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1222 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1223 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1224 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1225 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1226 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1227 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1228 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1229 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1230 /* 153 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1231 /* 155 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1232 /* 158 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1233 /* 162 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1234 /* 165 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1235 /* 168 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1236 /* 171 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1237 /* 173 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1238 /* 178 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1239 /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1240 /* 187 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1241 /* 189 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1242 /* 195 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1243 /* 201 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1244 /* 204 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1245 /* 206 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1246 }
1247};
1248
1249
1250#ifdef __GNUC__
1251#pragma GCC diagnostic push
1252#pragma GCC diagnostic ignored "-Woverlength-strings"
1253#endif
1254extern const char XCoreInstrNameData[] = {
1255 /* 0 */ "G_FLOG10\000"
1256 /* 9 */ "G_FEXP10\000"
1257 /* 18 */ "LDAPB_u10\000"
1258 /* 28 */ "BLRB_u10\000"
1259 /* 37 */ "LDAPF_u10\000"
1260 /* 47 */ "BLRF_u10\000"
1261 /* 56 */ "BLACP_u10\000"
1262 /* 66 */ "LDWCP_u10\000"
1263 /* 76 */ "LDAPB_lu10\000"
1264 /* 87 */ "BLRB_lu10\000"
1265 /* 97 */ "LDAPF_lu10\000"
1266 /* 108 */ "BLRF_lu10\000"
1267 /* 118 */ "BLACP_lu10\000"
1268 /* 129 */ "LDWCP_lu10\000"
1269 /* 140 */ "BR_JT32\000"
1270 /* 148 */ "G_FLOG2\000"
1271 /* 156 */ "G_FATAN2\000"
1272 /* 165 */ "G_FEXP2\000"
1273 /* 173 */ "KCALL_u6\000"
1274 /* 182 */ "LDAWCP_u6\000"
1275 /* 192 */ "EXTDP_u6\000"
1276 /* 201 */ "RETSP_u6\000"
1277 /* 210 */ "KENTSP_u6\000"
1278 /* 220 */ "KRESTSP_u6\000"
1279 /* 231 */ "EXTSP_u6\000"
1280 /* 240 */ "CLRSR_u6\000"
1281 /* 249 */ "GETSR_u6\000"
1282 /* 258 */ "SETSR_u6\000"
1283 /* 267 */ "BLAT_u6\000"
1284 /* 275 */ "BRBU_u6\000"
1285 /* 283 */ "BRFU_u6\000"
1286 /* 291 */ "CLRSR_branch_u6\000"
1287 /* 307 */ "SETSR_branch_u6\000"
1288 /* 323 */ "KCALL_lu6\000"
1289 /* 333 */ "LDAWCP_lu6\000"
1290 /* 344 */ "EXTDP_lu6\000"
1291 /* 354 */ "RETSP_lu6\000"
1292 /* 364 */ "KENTSP_lu6\000"
1293 /* 375 */ "KRESTSP_lu6\000"
1294 /* 387 */ "EXTSP_lu6\000"
1295 /* 397 */ "CLRSR_lu6\000"
1296 /* 407 */ "GETSR_lu6\000"
1297 /* 417 */ "SETSR_lu6\000"
1298 /* 427 */ "BLAT_lu6\000"
1299 /* 436 */ "BRBU_lu6\000"
1300 /* 445 */ "BRFU_lu6\000"
1301 /* 454 */ "CLRSR_branch_lu6\000"
1302 /* 471 */ "SETSR_branch_lu6\000"
1303 /* 488 */ "LDC_ru6\000"
1304 /* 496 */ "SETC_ru6\000"
1305 /* 505 */ "BRBF_ru6\000"
1306 /* 514 */ "BRFF_ru6\000"
1307 /* 523 */ "LDWCP_ru6\000"
1308 /* 533 */ "LDAWDP_ru6\000"
1309 /* 544 */ "LDWDP_ru6\000"
1310 /* 554 */ "STWDP_ru6\000"
1311 /* 564 */ "LDAWSP_ru6\000"
1312 /* 575 */ "LDWSP_ru6\000"
1313 /* 585 */ "STWSP_ru6\000"
1314 /* 595 */ "BRBT_ru6\000"
1315 /* 604 */ "BRFT_ru6\000"
1316 /* 613 */ "LDC_lru6\000"
1317 /* 622 */ "SETC_lru6\000"
1318 /* 632 */ "BRBF_lru6\000"
1319 /* 642 */ "BRFF_lru6\000"
1320 /* 652 */ "LDWCP_lru6\000"
1321 /* 663 */ "LDAWDP_lru6\000"
1322 /* 675 */ "LDWDP_lru6\000"
1323 /* 686 */ "STWDP_lru6\000"
1324 /* 697 */ "LDAWSP_lru6\000"
1325 /* 709 */ "LDWSP_lru6\000"
1326 /* 720 */ "STWSP_lru6\000"
1327 /* 731 */ "BRBT_lru6\000"
1328 /* 741 */ "BRFT_lru6\000"
1329 /* 751 */ "G_FMA\000"
1330 /* 757 */ "G_STRICT_FMA\000"
1331 /* 770 */ "G_FSUB\000"
1332 /* 777 */ "G_STRICT_FSUB\000"
1333 /* 791 */ "G_ATOMICRMW_FSUB\000"
1334 /* 808 */ "G_SUB\000"
1335 /* 814 */ "G_ATOMICRMW_SUB\000"
1336 /* 830 */ "SELECT_CC\000"
1337 /* 840 */ "G_INTRINSIC\000"
1338 /* 852 */ "G_FPTRUNC\000"
1339 /* 862 */ "G_INTRINSIC_TRUNC\000"
1340 /* 880 */ "G_TRUNC\000"
1341 /* 888 */ "G_BUILD_VECTOR_TRUNC\000"
1342 /* 909 */ "G_DYN_STACKALLOC\000"
1343 /* 926 */ "G_FMAD\000"
1344 /* 933 */ "G_FPEXTLOAD\000"
1345 /* 945 */ "G_INDEXED_SEXTLOAD\000"
1346 /* 964 */ "G_SEXTLOAD\000"
1347 /* 975 */ "G_INDEXED_ZEXTLOAD\000"
1348 /* 994 */ "G_ZEXTLOAD\000"
1349 /* 1005 */ "G_INDEXED_LOAD\000"
1350 /* 1020 */ "G_LOAD\000"
1351 /* 1027 */ "G_VECREDUCE_FADD\000"
1352 /* 1044 */ "G_FADD\000"
1353 /* 1051 */ "G_VECREDUCE_SEQ_FADD\000"
1354 /* 1072 */ "G_STRICT_FADD\000"
1355 /* 1086 */ "G_ATOMICRMW_FADD\000"
1356 /* 1103 */ "G_VECREDUCE_ADD\000"
1357 /* 1119 */ "G_ADD\000"
1358 /* 1125 */ "G_PTR_ADD\000"
1359 /* 1135 */ "G_ATOMICRMW_ADD\000"
1360 /* 1151 */ "G_ATOMICRMW_NAND\000"
1361 /* 1168 */ "G_VECREDUCE_AND\000"
1362 /* 1184 */ "G_AND\000"
1363 /* 1190 */ "G_ATOMICRMW_AND\000"
1364 /* 1206 */ "LIFETIME_END\000"
1365 /* 1219 */ "G_BRCOND\000"
1366 /* 1228 */ "G_ATOMICRMW_USUB_COND\000"
1367 /* 1250 */ "G_LLROUND\000"
1368 /* 1260 */ "G_LROUND\000"
1369 /* 1269 */ "G_INTRINSIC_ROUND\000"
1370 /* 1287 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1371 /* 1313 */ "LOAD_STACK_GUARD\000"
1372 /* 1330 */ "PSEUDO_PROBE\000"
1373 /* 1343 */ "G_SSUBE\000"
1374 /* 1351 */ "G_USUBE\000"
1375 /* 1359 */ "G_FENCE\000"
1376 /* 1367 */ "ARITH_FENCE\000"
1377 /* 1379 */ "REG_SEQUENCE\000"
1378 /* 1392 */ "G_SADDE\000"
1379 /* 1400 */ "G_UADDE\000"
1380 /* 1408 */ "G_GET_FPMODE\000"
1381 /* 1421 */ "G_RESET_FPMODE\000"
1382 /* 1436 */ "G_SET_FPMODE\000"
1383 /* 1449 */ "G_FMINNUM_IEEE\000"
1384 /* 1464 */ "G_FMAXNUM_IEEE\000"
1385 /* 1479 */ "G_VSCALE\000"
1386 /* 1488 */ "G_JUMP_TABLE\000"
1387 /* 1501 */ "BUNDLE\000"
1388 /* 1508 */ "G_MEMSET_INLINE\000"
1389 /* 1524 */ "G_MEMCPY_INLINE\000"
1390 /* 1540 */ "RELOC_NONE\000"
1391 /* 1551 */ "LOCAL_ESCAPE\000"
1392 /* 1564 */ "G_FPTRUNCSTORE\000"
1393 /* 1579 */ "G_STACKRESTORE\000"
1394 /* 1594 */ "G_INDEXED_STORE\000"
1395 /* 1610 */ "G_STORE\000"
1396 /* 1618 */ "G_BITREVERSE\000"
1397 /* 1631 */ "FAKE_USE\000"
1398 /* 1640 */ "DBG_VALUE\000"
1399 /* 1650 */ "G_GLOBAL_VALUE\000"
1400 /* 1665 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1401 /* 1688 */ "CONVERGENCECTRL_GLUE\000"
1402 /* 1709 */ "G_STACKSAVE\000"
1403 /* 1721 */ "G_MEMMOVE\000"
1404 /* 1731 */ "G_FREEZE\000"
1405 /* 1740 */ "G_FCANONICALIZE\000"
1406 /* 1756 */ "G_FMODF\000"
1407 /* 1764 */ "INIT_UNDEF\000"
1408 /* 1775 */ "G_IMPLICIT_DEF\000"
1409 /* 1790 */ "DBG_INSTR_REF\000"
1410 /* 1804 */ "G_FNEG\000"
1411 /* 1811 */ "EXTRACT_SUBREG\000"
1412 /* 1826 */ "INSERT_SUBREG\000"
1413 /* 1840 */ "G_SEXT_INREG\000"
1414 /* 1853 */ "SUBREG_TO_REG\000"
1415 /* 1867 */ "G_ATOMIC_CMPXCHG\000"
1416 /* 1884 */ "G_ATOMICRMW_XCHG\000"
1417 /* 1901 */ "G_GET_ROUNDING\000"
1418 /* 1916 */ "G_SET_ROUNDING\000"
1419 /* 1931 */ "G_FLOG\000"
1420 /* 1938 */ "G_VAARG\000"
1421 /* 1946 */ "PREALLOCATED_ARG\000"
1422 /* 1963 */ "G_PREFETCH\000"
1423 /* 1974 */ "G_SMULH\000"
1424 /* 1982 */ "G_UMULH\000"
1425 /* 1990 */ "G_FTANH\000"
1426 /* 1998 */ "G_FSINH\000"
1427 /* 2006 */ "G_FCOSH\000"
1428 /* 2014 */ "LDAWFI\000"
1429 /* 2021 */ "LDWFI\000"
1430 /* 2027 */ "STWFI\000"
1431 /* 2033 */ "DBG_PHI\000"
1432 /* 2041 */ "G_FPTOSI\000"
1433 /* 2050 */ "G_FPTOUI\000"
1434 /* 2059 */ "G_FPOWI\000"
1435 /* 2067 */ "COPY_LANEMASK\000"
1436 /* 2081 */ "G_PTRMASK\000"
1437 /* 2091 */ "GC_LABEL\000"
1438 /* 2100 */ "DBG_LABEL\000"
1439 /* 2110 */ "EH_LABEL\000"
1440 /* 2119 */ "ANNOTATION_LABEL\000"
1441 /* 2136 */ "ICALL_BRANCH_FUNNEL\000"
1442 /* 2156 */ "G_FSHL\000"
1443 /* 2163 */ "G_SHL\000"
1444 /* 2169 */ "G_FCEIL\000"
1445 /* 2177 */ "G_SAVGCEIL\000"
1446 /* 2188 */ "G_UAVGCEIL\000"
1447 /* 2199 */ "PATCHABLE_TAIL_CALL\000"
1448 /* 2219 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1449 /* 2246 */ "PATCHABLE_EVENT_CALL\000"
1450 /* 2267 */ "FENTRY_CALL\000"
1451 /* 2279 */ "KILL\000"
1452 /* 2284 */ "G_CONSTANT_POOL\000"
1453 /* 2300 */ "G_ROTL\000"
1454 /* 2307 */ "G_VECREDUCE_FMUL\000"
1455 /* 2324 */ "G_FMUL\000"
1456 /* 2331 */ "G_VECREDUCE_SEQ_FMUL\000"
1457 /* 2352 */ "G_STRICT_FMUL\000"
1458 /* 2366 */ "G_CLMUL\000"
1459 /* 2374 */ "G_VECREDUCE_MUL\000"
1460 /* 2390 */ "G_MUL\000"
1461 /* 2396 */ "G_FREM\000"
1462 /* 2403 */ "G_STRICT_FREM\000"
1463 /* 2417 */ "G_SREM\000"
1464 /* 2424 */ "G_UREM\000"
1465 /* 2431 */ "G_SDIVREM\000"
1466 /* 2441 */ "G_UDIVREM\000"
1467 /* 2451 */ "INLINEASM\000"
1468 /* 2461 */ "G_VECREDUCE_FMINIMUM\000"
1469 /* 2482 */ "G_FMINIMUM\000"
1470 /* 2493 */ "G_ATOMICRMW_FMINIMUM\000"
1471 /* 2514 */ "G_VECREDUCE_FMAXIMUM\000"
1472 /* 2535 */ "G_FMAXIMUM\000"
1473 /* 2546 */ "G_ATOMICRMW_FMAXIMUM\000"
1474 /* 2567 */ "G_FMINIMUMNUM\000"
1475 /* 2581 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1476 /* 2605 */ "G_FMAXIMUMNUM\000"
1477 /* 2619 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1478 /* 2643 */ "G_FMINNUM\000"
1479 /* 2653 */ "G_FMAXNUM\000"
1480 /* 2663 */ "G_FATAN\000"
1481 /* 2671 */ "G_FTAN\000"
1482 /* 2678 */ "G_INTRINSIC_ROUNDEVEN\000"
1483 /* 2700 */ "G_ASSERT_ALIGN\000"
1484 /* 2715 */ "G_FCOPYSIGN\000"
1485 /* 2727 */ "G_VECREDUCE_FMIN\000"
1486 /* 2744 */ "G_ATOMICRMW_FMIN\000"
1487 /* 2761 */ "G_VECREDUCE_SMIN\000"
1488 /* 2778 */ "G_SMIN\000"
1489 /* 2785 */ "G_VECREDUCE_UMIN\000"
1490 /* 2802 */ "G_UMIN\000"
1491 /* 2809 */ "G_ATOMICRMW_UMIN\000"
1492 /* 2826 */ "G_ATOMICRMW_MIN\000"
1493 /* 2842 */ "G_FASIN\000"
1494 /* 2850 */ "G_FSIN\000"
1495 /* 2857 */ "CFI_INSTRUCTION\000"
1496 /* 2873 */ "G_CTLZ_ZERO_POISON\000"
1497 /* 2892 */ "G_CTTZ_ZERO_POISON\000"
1498 /* 2911 */ "EH_RETURN\000"
1499 /* 2921 */ "ADJCALLSTACKDOWN\000"
1500 /* 2938 */ "G_SSUBO\000"
1501 /* 2946 */ "G_USUBO\000"
1502 /* 2954 */ "G_SADDO\000"
1503 /* 2962 */ "G_UADDO\000"
1504 /* 2970 */ "JUMP_TABLE_DEBUG_INFO\000"
1505 /* 2992 */ "G_SMULO\000"
1506 /* 3000 */ "G_UMULO\000"
1507 /* 3008 */ "G_BZERO\000"
1508 /* 3016 */ "STACKMAP\000"
1509 /* 3025 */ "G_DEBUGTRAP\000"
1510 /* 3037 */ "G_UBSANTRAP\000"
1511 /* 3049 */ "G_TRAP\000"
1512 /* 3056 */ "G_ATOMICRMW_UDEC_WRAP\000"
1513 /* 3078 */ "G_ATOMICRMW_UINC_WRAP\000"
1514 /* 3100 */ "G_BSWAP\000"
1515 /* 3108 */ "G_SITOFP\000"
1516 /* 3117 */ "G_UITOFP\000"
1517 /* 3126 */ "G_FCMP\000"
1518 /* 3133 */ "G_STRICT_FCMP\000"
1519 /* 3147 */ "G_ICMP\000"
1520 /* 3154 */ "G_SCMP\000"
1521 /* 3161 */ "G_UCMP\000"
1522 /* 3168 */ "CONVERGENCECTRL_LOOP\000"
1523 /* 3189 */ "G_CTPOP\000"
1524 /* 3197 */ "PATCHABLE_OP\000"
1525 /* 3210 */ "FAULTING_OP\000"
1526 /* 3222 */ "ADJCALLSTACKUP\000"
1527 /* 3237 */ "PREALLOCATED_SETUP\000"
1528 /* 3256 */ "G_FLDEXP\000"
1529 /* 3265 */ "G_STRICT_FLDEXP\000"
1530 /* 3281 */ "G_FEXP\000"
1531 /* 3288 */ "G_FFREXP\000"
1532 /* 3297 */ "LDSPC_0R\000"
1533 /* 3306 */ "STSPC_0R\000"
1534 /* 3315 */ "LDSED_0R\000"
1535 /* 3324 */ "STSED_0R\000"
1536 /* 3333 */ "GETED_0R\000"
1537 /* 3342 */ "GETID_0R\000"
1538 /* 3351 */ "CLRE_0R\000"
1539 /* 3359 */ "DCALL_0R\000"
1540 /* 3368 */ "GETKEP_0R\000"
1541 /* 3378 */ "SETKEP_0R\000"
1542 /* 3388 */ "GETKSP_0R\000"
1543 /* 3398 */ "DENTSP_0R\000"
1544 /* 3408 */ "DRESTSP_0R\000"
1545 /* 3419 */ "LDSSR_0R\000"
1546 /* 3428 */ "STSSR_0R\000"
1547 /* 3437 */ "LDET_0R\000"
1548 /* 3445 */ "FREET_0R\000"
1549 /* 3454 */ "DRET_0R\000"
1550 /* 3462 */ "KRET_0R\000"
1551 /* 3470 */ "GETET_0R\000"
1552 /* 3479 */ "STET_0R\000"
1553 /* 3487 */ "WAITEU_0R\000"
1554 /* 3497 */ "WAITEF_1R\000"
1555 /* 3507 */ "WAITET_1R\000"
1556 /* 3517 */ "CLRPT_1R\000"
1557 /* 3526 */ "TSTART_1R\000"
1558 /* 3536 */ "G_BR\000"
1559 /* 3541 */ "INLINEASM_BR\000"
1560 /* 3554 */ "G_BLOCK_ADDR\000"
1561 /* 3567 */ "MEMBARRIER\000"
1562 /* 3578 */ "G_CONSTANT_FOLD_BARRIER\000"
1563 /* 3602 */ "PATCHABLE_FUNCTION_ENTER\000"
1564 /* 3627 */ "G_READCYCLECOUNTER\000"
1565 /* 3646 */ "G_READSTEADYCOUNTER\000"
1566 /* 3666 */ "G_READ_REGISTER\000"
1567 /* 3682 */ "G_WRITE_REGISTER\000"
1568 /* 3699 */ "G_ASHR\000"
1569 /* 3706 */ "G_FSHR\000"
1570 /* 3713 */ "G_LSHR\000"
1571 /* 3720 */ "CONVERGENCECTRL_ANCHOR\000"
1572 /* 3743 */ "G_FFLOOR\000"
1573 /* 3752 */ "G_SAVGFLOOR\000"
1574 /* 3764 */ "G_UAVGFLOOR\000"
1575 /* 3776 */ "G_EXTRACT_SUBVECTOR\000"
1576 /* 3796 */ "G_INSERT_SUBVECTOR\000"
1577 /* 3815 */ "G_BUILD_VECTOR\000"
1578 /* 3830 */ "G_SHUFFLE_VECTOR\000"
1579 /* 3847 */ "G_STEP_VECTOR\000"
1580 /* 3861 */ "G_SPLAT_VECTOR\000"
1581 /* 3876 */ "G_VECREDUCE_XOR\000"
1582 /* 3892 */ "G_XOR\000"
1583 /* 3898 */ "G_ATOMICRMW_XOR\000"
1584 /* 3914 */ "G_VECREDUCE_OR\000"
1585 /* 3929 */ "G_OR\000"
1586 /* 3934 */ "G_ATOMICRMW_OR\000"
1587 /* 3949 */ "G_ROTR\000"
1588 /* 3956 */ "G_INTTOPTR\000"
1589 /* 3967 */ "G_FABS\000"
1590 /* 3974 */ "G_ABS\000"
1591 /* 3980 */ "G_ABDS\000"
1592 /* 3987 */ "G_UNMERGE_VALUES\000"
1593 /* 4004 */ "G_MERGE_VALUES\000"
1594 /* 4019 */ "G_CTLS\000"
1595 /* 4026 */ "G_FACOS\000"
1596 /* 4034 */ "G_FCOS\000"
1597 /* 4041 */ "G_FSINCOS\000"
1598 /* 4051 */ "G_STRICT_FCMPS\000"
1599 /* 4066 */ "G_CONCAT_VECTORS\000"
1600 /* 4083 */ "COPY_TO_REGCLASS\000"
1601 /* 4100 */ "G_IS_FPCLASS\000"
1602 /* 4113 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1603 /* 4143 */ "G_VECTOR_COMPRESS\000"
1604 /* 4161 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1605 /* 4188 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1606 /* 4226 */ "G_TRUNC_SSAT_S\000"
1607 /* 4241 */ "G_SSUBSAT\000"
1608 /* 4251 */ "G_USUBSAT\000"
1609 /* 4261 */ "G_SADDSAT\000"
1610 /* 4271 */ "G_UADDSAT\000"
1611 /* 4281 */ "G_SSHLSAT\000"
1612 /* 4291 */ "G_USHLSAT\000"
1613 /* 4301 */ "G_SMULFIXSAT\000"
1614 /* 4314 */ "G_UMULFIXSAT\000"
1615 /* 4327 */ "G_SDIVFIXSAT\000"
1616 /* 4340 */ "G_UDIVFIXSAT\000"
1617 /* 4353 */ "G_ATOMICRMW_USUB_SAT\000"
1618 /* 4374 */ "G_FPTOSI_SAT\000"
1619 /* 4387 */ "G_FPTOUI_SAT\000"
1620 /* 4400 */ "G_EXTRACT\000"
1621 /* 4410 */ "G_SELECT\000"
1622 /* 4419 */ "G_BRINDIRECT\000"
1623 /* 4432 */ "PATCHABLE_RET\000"
1624 /* 4446 */ "FRAME_TO_ARGS_OFFSET\000"
1625 /* 4467 */ "G_MEMSET\000"
1626 /* 4476 */ "PATCHABLE_FUNCTION_EXIT\000"
1627 /* 4500 */ "G_BRJT\000"
1628 /* 4507 */ "BR_JT\000"
1629 /* 4513 */ "G_EXTRACT_VECTOR_ELT\000"
1630 /* 4534 */ "G_INSERT_VECTOR_ELT\000"
1631 /* 4554 */ "G_FCONSTANT\000"
1632 /* 4566 */ "G_CONSTANT\000"
1633 /* 4577 */ "G_INTRINSIC_CONVERGENT\000"
1634 /* 4600 */ "STATEPOINT\000"
1635 /* 4611 */ "PATCHPOINT\000"
1636 /* 4622 */ "G_PTRTOINT\000"
1637 /* 4633 */ "G_FRINT\000"
1638 /* 4641 */ "G_INTRINSIC_LLRINT\000"
1639 /* 4660 */ "G_INTRINSIC_LRINT\000"
1640 /* 4678 */ "G_FNEARBYINT\000"
1641 /* 4691 */ "NOT\000"
1642 /* 4695 */ "G_VASTART\000"
1643 /* 4705 */ "LIFETIME_START\000"
1644 /* 4720 */ "G_INVOKE_REGION_START\000"
1645 /* 4742 */ "G_INSERT\000"
1646 /* 4751 */ "G_FSQRT\000"
1647 /* 4759 */ "G_STRICT_FSQRT\000"
1648 /* 4774 */ "G_BITCAST\000"
1649 /* 4784 */ "G_ADDRSPACE_CAST\000"
1650 /* 4801 */ "DBG_VALUE_LIST\000"
1651 /* 4816 */ "G_FPEXT\000"
1652 /* 4824 */ "G_SEXT\000"
1653 /* 4831 */ "G_ASSERT_SEXT\000"
1654 /* 4845 */ "G_ANYEXT\000"
1655 /* 4854 */ "G_ZEXT\000"
1656 /* 4861 */ "G_ASSERT_ZEXT\000"
1657 /* 4875 */ "G_ABDU\000"
1658 /* 4882 */ "G_TRUNC_SSAT_U\000"
1659 /* 4897 */ "G_TRUNC_USAT_U\000"
1660 /* 4912 */ "G_FDIV\000"
1661 /* 4919 */ "G_STRICT_FDIV\000"
1662 /* 4933 */ "G_SDIV\000"
1663 /* 4940 */ "G_UDIV\000"
1664 /* 4947 */ "G_GET_FPENV\000"
1665 /* 4959 */ "G_RESET_FPENV\000"
1666 /* 4973 */ "G_SET_FPENV\000"
1667 /* 4985 */ "G_FPOW\000"
1668 /* 4992 */ "G_VECREDUCE_FMAX\000"
1669 /* 5009 */ "G_ATOMICRMW_FMAX\000"
1670 /* 5026 */ "G_VECREDUCE_SMAX\000"
1671 /* 5043 */ "G_SMAX\000"
1672 /* 5050 */ "G_VECREDUCE_UMAX\000"
1673 /* 5067 */ "G_UMAX\000"
1674 /* 5074 */ "G_ATOMICRMW_UMAX\000"
1675 /* 5091 */ "G_ATOMICRMW_MAX\000"
1676 /* 5107 */ "G_FRAME_INDEX\000"
1677 /* 5121 */ "G_SBFX\000"
1678 /* 5128 */ "G_UBFX\000"
1679 /* 5135 */ "G_SMULFIX\000"
1680 /* 5145 */ "G_UMULFIX\000"
1681 /* 5155 */ "G_SDIVFIX\000"
1682 /* 5165 */ "G_UDIVFIX\000"
1683 /* 5175 */ "G_MEMCPY\000"
1684 /* 5184 */ "COPY\000"
1685 /* 5189 */ "CONVERGENCECTRL_ENTRY\000"
1686 /* 5211 */ "G_CTLZ\000"
1687 /* 5218 */ "G_CTTZ\000"
1688 /* 5225 */ "LDAPF_lu10_ba\000"
1689 /* 5239 */ "SSYNC_0r\000"
1690 /* 5248 */ "BLA_1r\000"
1691 /* 5255 */ "MSYNC_1r\000"
1692 /* 5264 */ "ECALLF_1r\000"
1693 /* 5274 */ "DGETREG_1r\000"
1694 /* 5285 */ "KCALL_1r\000"
1695 /* 5294 */ "MJOIN_1r\000"
1696 /* 5303 */ "SETCP_1r\000"
1697 /* 5312 */ "SETDP_1r\000"
1698 /* 5321 */ "SETSP_1r\000"
1699 /* 5330 */ "SYNCR_1r\000"
1700 /* 5339 */ "FREER_1r\000"
1701 /* 5348 */ "ECALLT_1r\000"
1702 /* 5358 */ "BAU_1r\000"
1703 /* 5365 */ "EDU_1r\000"
1704 /* 5372 */ "EEU_1r\000"
1705 /* 5379 */ "BRU_1r\000"
1706 /* 5386 */ "SETEV_1r\000"
1707 /* 5395 */ "SETV_1r\000"
1708 /* 5403 */ "INITPC_2r\000"
1709 /* 5413 */ "SETPSC_2r\000"
1710 /* 5423 */ "SETD_2r\000"
1711 /* 5431 */ "EEF_2r\000"
1712 /* 5438 */ "PEEK_2r\000"
1713 /* 5446 */ "MKMSK_2r\000"
1714 /* 5455 */ "ENDIN_2r\000"
1715 /* 5464 */ "INITCP_2r\000"
1716 /* 5474 */ "INITDP_2r\000"
1717 /* 5484 */ "INITSP_2r\000"
1718 /* 5494 */ "INSHR_2r\000"
1719 /* 5503 */ "OUTSHR_2r\000"
1720 /* 5513 */ "TSETMR_2r\000"
1721 /* 5523 */ "GETTS_2r\000"
1722 /* 5532 */ "CHKCT_2r\000"
1723 /* 5541 */ "INCT_2r\000"
1724 /* 5549 */ "TESTCT_2r\000"
1725 /* 5559 */ "OUTCT_2r\000"
1726 /* 5568 */ "TESTWCT_2r\000"
1727 /* 5579 */ "EET_2r\000"
1728 /* 5586 */ "INT_2r\000"
1729 /* 5593 */ "ANDNOT_2r\000"
1730 /* 5603 */ "SETPT_2r\000"
1731 /* 5612 */ "GETST_2r\000"
1732 /* 5621 */ "OUTT_2r\000"
1733 /* 5629 */ "OUT_2r\000"
1734 /* 5636 */ "SEXT_2r\000"
1735 /* 5644 */ "ZEXT_2r\000"
1736 /* 5652 */ "SETC_l2r\000"
1737 /* 5661 */ "GETD_l2r\000"
1738 /* 5670 */ "SETCLK_l2r\000"
1739 /* 5681 */ "TESTLCL_l2r\000"
1740 /* 5693 */ "GETN_l2r\000"
1741 /* 5702 */ "SETN_l2r\000"
1742 /* 5711 */ "INITLR_l2r\000"
1743 /* 5722 */ "GETPS_l2r\000"
1744 /* 5732 */ "SETPS_l2r\000"
1745 /* 5742 */ "BYTEREV_l2r\000"
1746 /* 5754 */ "BITREV_l2r\000"
1747 /* 5765 */ "SETTW_l2r\000"
1748 /* 5775 */ "SETRDY_l2r\000"
1749 /* 5786 */ "CLZ_l2r\000"
1750 /* 5794 */ "SUB_3r\000"
1751 /* 5801 */ "ADD_3r\000"
1752 /* 5808 */ "AND_3r\000"
1753 /* 5815 */ "SHL_3r\000"
1754 /* 5822 */ "EQ_3r\000"
1755 /* 5828 */ "SHR_3r\000"
1756 /* 5835 */ "OR_3r\000"
1757 /* 5841 */ "TSETR_3r\000"
1758 /* 5850 */ "LD16S_3r\000"
1759 /* 5859 */ "LSS_3r\000"
1760 /* 5866 */ "LD8U_3r\000"
1761 /* 5874 */ "LSU_3r\000"
1762 /* 5881 */ "LDW_3r\000"
1763 /* 5888 */ "ST16_l3r\000"
1764 /* 5897 */ "ST8_l3r\000"
1765 /* 5905 */ "LDA16B_l3r\000"
1766 /* 5916 */ "LDAWB_l3r\000"
1767 /* 5926 */ "CRC_l3r\000"
1768 /* 5934 */ "LDA16F_l3r\000"
1769 /* 5945 */ "LDAWF_l3r\000"
1770 /* 5955 */ "MUL_l3r\000"
1771 /* 5963 */ "ASHR_l3r\000"
1772 /* 5972 */ "XOR_l3r\000"
1773 /* 5980 */ "REMS_l3r\000"
1774 /* 5989 */ "DIVS_l3r\000"
1775 /* 5998 */ "REMU_l3r\000"
1776 /* 6007 */ "DIVU_l3r\000"
1777 /* 6016 */ "STW_l3r\000"
1778 /* 6024 */ "CRC8_l4r\000"
1779 /* 6033 */ "MACCS_l4r\000"
1780 /* 6043 */ "MACCU_l4r\000"
1781 /* 6053 */ "LSUB_l5r\000"
1782 /* 6062 */ "LADD_l5r\000"
1783 /* 6071 */ "LDIVU_l5r\000"
1784 /* 6081 */ "LMUL_l6r\000"
1785 /* 6090 */ "SUB_2rus\000"
1786 /* 6099 */ "ADD_2rus\000"
1787 /* 6108 */ "SHL_2rus\000"
1788 /* 6117 */ "EQ_2rus\000"
1789 /* 6125 */ "SHR_2rus\000"
1790 /* 6134 */ "LDW_2rus\000"
1791 /* 6143 */ "STW_2rus\000"
1792 /* 6152 */ "LDAWB_l2rus\000"
1793 /* 6164 */ "LDAWF_l2rus\000"
1794 /* 6176 */ "ASHR_l2rus\000"
1795 /* 6187 */ "INPW_l2rus\000"
1796 /* 6198 */ "OUTPW_l2rus\000"
1797 /* 6210 */ "MKMSK_rus\000"
1798 /* 6220 */ "GETR_rus\000"
1799 /* 6229 */ "CHKCT_rus\000"
1800 /* 6239 */ "OUTCT_rus\000"
1801 /* 6249 */ "SEXT_rus\000"
1802 /* 6258 */ "ZEXT_rus\000"
1803};
1804#ifdef __GNUC__
1805#pragma GCC diagnostic pop
1806#endif
1807
1808extern const unsigned XCoreInstrNameIndices[] = {
1809 2037U, 2451U, 3541U, 2857U, 2110U, 2091U, 2119U, 2279U,
1810 1811U, 1826U, 1777U, 1764U, 1853U, 4083U, 1640U, 4801U,
1811 1790U, 2033U, 2100U, 1379U, 5184U, 2067U, 1501U, 4705U,
1812 1206U, 1330U, 1367U, 3016U, 2267U, 4611U, 1313U, 3237U,
1813 1946U, 4600U, 1551U, 3210U, 3197U, 3602U, 4432U, 4476U,
1814 2199U, 2246U, 2219U, 2136U, 1631U, 3567U, 2970U, 1540U,
1815 5189U, 3720U, 3168U, 1688U, 4831U, 4861U, 2700U, 1119U,
1816 808U, 2390U, 4933U, 4940U, 2417U, 2424U, 2431U, 2441U,
1817 1184U, 3929U, 3892U, 3980U, 4875U, 3764U, 2188U, 3752U,
1818 2177U, 1775U, 2035U, 5107U, 1650U, 1665U, 2284U, 4400U,
1819 3987U, 4742U, 4004U, 3815U, 888U, 4066U, 4622U, 3956U,
1820 4774U, 1731U, 3578U, 1287U, 862U, 1269U, 4660U, 4641U,
1821 2678U, 3627U, 3646U, 1020U, 964U, 994U, 933U, 1005U,
1822 945U, 975U, 1610U, 1564U, 1594U, 4113U, 1867U, 1884U,
1823 1135U, 814U, 1190U, 1151U, 3934U, 3898U, 5091U, 2826U,
1824 5074U, 2809U, 1086U, 791U, 5009U, 2744U, 2546U, 2493U,
1825 2619U, 2581U, 3078U, 3056U, 1228U, 4353U, 1359U, 1963U,
1826 1219U, 4419U, 4720U, 840U, 4161U, 4577U, 4188U, 4845U,
1827 880U, 4226U, 4882U, 4897U, 4566U, 4554U, 4695U, 1938U,
1828 4824U, 1840U, 4854U, 2163U, 3713U, 3699U, 2156U, 3706U,
1829 3949U, 2300U, 3147U, 3126U, 3154U, 3161U, 4410U, 2962U,
1830 1400U, 2946U, 1351U, 2954U, 1392U, 2938U, 1343U, 3000U,
1831 2992U, 1982U, 1974U, 4271U, 4261U, 4251U, 4241U, 4291U,
1832 4281U, 5135U, 5145U, 4301U, 4314U, 5155U, 5165U, 4327U,
1833 4340U, 1044U, 770U, 2324U, 751U, 926U, 4912U, 2396U,
1834 1756U, 4985U, 2059U, 3281U, 165U, 9U, 1931U, 148U,
1835 0U, 3256U, 3288U, 1804U, 4816U, 852U, 2041U, 2050U,
1836 3108U, 3117U, 4374U, 4387U, 3967U, 2715U, 4100U, 1740U,
1837 2643U, 2653U, 1449U, 1464U, 2482U, 2535U, 2567U, 2605U,
1838 4947U, 4973U, 4959U, 1408U, 1436U, 1421U, 1901U, 1916U,
1839 1125U, 2081U, 2778U, 5043U, 2802U, 5067U, 3974U, 1260U,
1840 1250U, 3536U, 4500U, 1479U, 3796U, 3776U, 4534U, 4513U,
1841 3830U, 3861U, 3847U, 4143U, 5218U, 2892U, 5211U, 2873U,
1842 4019U, 3189U, 3100U, 1618U, 2366U, 2169U, 4034U, 2850U,
1843 4041U, 2671U, 4026U, 2842U, 2663U, 156U, 2006U, 1998U,
1844 1990U, 4751U, 3743U, 4633U, 4678U, 4784U, 3554U, 1488U,
1845 909U, 1709U, 1579U, 1072U, 777U, 2352U, 4919U, 2403U,
1846 757U, 4759U, 3265U, 3133U, 4051U, 3666U, 3682U, 5175U,
1847 1524U, 1721U, 4467U, 3008U, 1508U, 3049U, 3025U, 3037U,
1848 1051U, 2331U, 1027U, 2307U, 4992U, 2727U, 2514U, 2461U,
1849 1103U, 2374U, 1168U, 3914U, 3876U, 5026U, 2761U, 5050U,
1850 2785U, 5121U, 5128U, 2921U, 3222U, 4507U, 140U, 2911U,
1851 4446U, 2014U, 2021U, 830U, 2027U, 6099U, 5801U, 5593U,
1852 5808U, 6176U, 5963U, 5358U, 5754U, 118U, 56U, 427U,
1853 267U, 5248U, 87U, 28U, 108U, 47U, 632U, 505U,
1854 731U, 595U, 436U, 275U, 642U, 514U, 741U, 604U,
1855 445U, 283U, 5379U, 5742U, 5532U, 6229U, 3351U, 3517U,
1856 454U, 291U, 397U, 240U, 5786U, 6024U, 5926U, 3359U,
1857 3398U, 5274U, 5989U, 6007U, 3408U, 3454U, 5264U, 5348U,
1858 5365U, 5431U, 5579U, 5372U, 5455U, 365U, 211U, 6117U,
1859 5822U, 344U, 192U, 387U, 231U, 5339U, 3445U, 5661U,
1860 3333U, 3470U, 3342U, 3368U, 3388U, 5693U, 5722U, 6220U,
1861 407U, 249U, 5612U, 5523U, 5541U, 5464U, 5474U, 5711U,
1862 5403U, 5484U, 6187U, 5494U, 5586U, 5458U, 5285U, 323U,
1863 173U, 364U, 210U, 375U, 220U, 3462U, 6062U, 5850U,
1864 5866U, 5905U, 5934U, 76U, 18U, 97U, 5225U, 37U,
1865 6152U, 5916U, 333U, 182U, 663U, 533U, 6164U, 5945U,
1866 697U, 564U, 613U, 488U, 3437U, 6071U, 3315U, 3297U,
1867 3419U, 652U, 129U, 523U, 66U, 675U, 544U, 709U,
1868 575U, 6134U, 5881U, 6081U, 5859U, 6053U, 5874U, 6033U,
1869 6043U, 5294U, 5446U, 6210U, 5255U, 5955U, 1807U, 4691U,
1870 5835U, 5559U, 6239U, 6198U, 5503U, 5621U, 5629U, 5438U,
1871 5980U, 5998U, 354U, 201U, 5670U, 5303U, 5652U, 622U,
1872 496U, 5312U, 5423U, 5386U, 3378U, 5702U, 5413U, 5732U,
1873 5603U, 5775U, 5321U, 471U, 307U, 417U, 258U, 5765U,
1874 5395U, 5636U, 6249U, 6108U, 5815U, 6125U, 5828U, 5239U,
1875 5888U, 5897U, 3479U, 3324U, 3306U, 3428U, 686U, 554U,
1876 720U, 585U, 6143U, 6016U, 6090U, 5794U, 5330U, 5549U,
1877 5681U, 5568U, 5513U, 5841U, 3526U, 3497U, 3507U, 3487U,
1878 5972U, 5644U, 6258U,
1879};
1880
1881static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1882 II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 555, nullptr, 0);
1883}
1884
1885
1886} // namespace llvm
1887
1888#endif // GET_INSTRINFO_MC_DESC
1889
1890#ifdef GET_INSTRINFO_HEADER
1891#undef GET_INSTRINFO_HEADER
1892
1893namespace llvm {
1894
1895struct XCoreGenInstrInfo : public TargetInstrInfo {
1896 explicit XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1897 ~XCoreGenInstrInfo() override = default;
1898};
1899
1900} // namespace llvm
1901
1902namespace llvm::XCore {
1903
1904
1905} // namespace llvm::XCore
1906
1907#endif // GET_INSTRINFO_HEADER
1908
1909#ifdef GET_INSTRINFO_HELPER_DECLS
1910#undef GET_INSTRINFO_HELPER_DECLS
1911
1912
1913#endif // GET_INSTRINFO_HELPER_DECLS
1914
1915#ifdef GET_INSTRINFO_HELPERS
1916#undef GET_INSTRINFO_HELPERS
1917
1918
1919#endif // GET_INSTRINFO_HELPERS
1920
1921#ifdef GET_INSTRINFO_CTOR_DTOR
1922#undef GET_INSTRINFO_CTOR_DTOR
1923
1924namespace llvm {
1925
1926extern const XCoreInstrTable XCoreDescs;
1927extern const unsigned XCoreInstrNameIndices[];
1928extern const char XCoreInstrNameData[];
1929XCoreGenInstrInfo::XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1930 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1931 InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 555);
1932}
1933
1934} // namespace llvm
1935
1936#endif // GET_INSTRINFO_CTOR_DTOR
1937
1938#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1939#undef GET_INSTRINFO_MC_HELPER_DECLS
1940
1941namespace llvm {
1942
1943class MCInst;
1944class FeatureBitset;
1945
1946namespace XCore_MC {
1947
1948void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1949
1950} // namespace XCore_MC
1951
1952} // namespace llvm
1953
1954#endif // GET_INSTRINFO_MC_HELPER_DECLS
1955
1956#ifdef GET_INSTRINFO_MC_HELPERS
1957#undef GET_INSTRINFO_MC_HELPERS
1958
1959namespace llvm::XCore_MC {
1960
1961
1962} // namespace llvm::XCore_MC
1963
1964#endif // GET_INSTRINFO_MC_HELPERS
1965
1966#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1967 defined(GET_AVAILABLE_OPCODE_CHECKER)
1968#define GET_COMPUTE_FEATURES
1969#endif
1970#ifdef GET_COMPUTE_FEATURES
1971#undef GET_COMPUTE_FEATURES
1972
1973namespace llvm::XCore_MC {
1974
1975// Bits for subtarget features that participate in instruction matching.
1976enum SubtargetFeatureBits : uint8_t {
1977};
1978
1979inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1980 FeatureBitset Features;
1981 return Features;
1982}
1983
1984inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1985 enum : uint8_t {
1986 CEFBS_None,
1987 };
1988
1989 static constexpr FeatureBitset FeatureBitsets[] = {
1990 {}, // CEFBS_None
1991 };
1992 static constexpr uint8_t RequiredFeaturesRefs[] = {
1993 CEFBS_None, // PHI
1994 CEFBS_None, // INLINEASM
1995 CEFBS_None, // INLINEASM_BR
1996 CEFBS_None, // CFI_INSTRUCTION
1997 CEFBS_None, // EH_LABEL
1998 CEFBS_None, // GC_LABEL
1999 CEFBS_None, // ANNOTATION_LABEL
2000 CEFBS_None, // KILL
2001 CEFBS_None, // EXTRACT_SUBREG
2002 CEFBS_None, // INSERT_SUBREG
2003 CEFBS_None, // IMPLICIT_DEF
2004 CEFBS_None, // INIT_UNDEF
2005 CEFBS_None, // SUBREG_TO_REG
2006 CEFBS_None, // COPY_TO_REGCLASS
2007 CEFBS_None, // DBG_VALUE
2008 CEFBS_None, // DBG_VALUE_LIST
2009 CEFBS_None, // DBG_INSTR_REF
2010 CEFBS_None, // DBG_PHI
2011 CEFBS_None, // DBG_LABEL
2012 CEFBS_None, // REG_SEQUENCE
2013 CEFBS_None, // COPY
2014 CEFBS_None, // COPY_LANEMASK
2015 CEFBS_None, // BUNDLE
2016 CEFBS_None, // LIFETIME_START
2017 CEFBS_None, // LIFETIME_END
2018 CEFBS_None, // PSEUDO_PROBE
2019 CEFBS_None, // ARITH_FENCE
2020 CEFBS_None, // STACKMAP
2021 CEFBS_None, // FENTRY_CALL
2022 CEFBS_None, // PATCHPOINT
2023 CEFBS_None, // LOAD_STACK_GUARD
2024 CEFBS_None, // PREALLOCATED_SETUP
2025 CEFBS_None, // PREALLOCATED_ARG
2026 CEFBS_None, // STATEPOINT
2027 CEFBS_None, // LOCAL_ESCAPE
2028 CEFBS_None, // FAULTING_OP
2029 CEFBS_None, // PATCHABLE_OP
2030 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2031 CEFBS_None, // PATCHABLE_RET
2032 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2033 CEFBS_None, // PATCHABLE_TAIL_CALL
2034 CEFBS_None, // PATCHABLE_EVENT_CALL
2035 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2036 CEFBS_None, // ICALL_BRANCH_FUNNEL
2037 CEFBS_None, // FAKE_USE
2038 CEFBS_None, // MEMBARRIER
2039 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2040 CEFBS_None, // RELOC_NONE
2041 CEFBS_None, // CONVERGENCECTRL_ENTRY
2042 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2043 CEFBS_None, // CONVERGENCECTRL_LOOP
2044 CEFBS_None, // CONVERGENCECTRL_GLUE
2045 CEFBS_None, // G_ASSERT_SEXT
2046 CEFBS_None, // G_ASSERT_ZEXT
2047 CEFBS_None, // G_ASSERT_ALIGN
2048 CEFBS_None, // G_ADD
2049 CEFBS_None, // G_SUB
2050 CEFBS_None, // G_MUL
2051 CEFBS_None, // G_SDIV
2052 CEFBS_None, // G_UDIV
2053 CEFBS_None, // G_SREM
2054 CEFBS_None, // G_UREM
2055 CEFBS_None, // G_SDIVREM
2056 CEFBS_None, // G_UDIVREM
2057 CEFBS_None, // G_AND
2058 CEFBS_None, // G_OR
2059 CEFBS_None, // G_XOR
2060 CEFBS_None, // G_ABDS
2061 CEFBS_None, // G_ABDU
2062 CEFBS_None, // G_UAVGFLOOR
2063 CEFBS_None, // G_UAVGCEIL
2064 CEFBS_None, // G_SAVGFLOOR
2065 CEFBS_None, // G_SAVGCEIL
2066 CEFBS_None, // G_IMPLICIT_DEF
2067 CEFBS_None, // G_PHI
2068 CEFBS_None, // G_FRAME_INDEX
2069 CEFBS_None, // G_GLOBAL_VALUE
2070 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2071 CEFBS_None, // G_CONSTANT_POOL
2072 CEFBS_None, // G_EXTRACT
2073 CEFBS_None, // G_UNMERGE_VALUES
2074 CEFBS_None, // G_INSERT
2075 CEFBS_None, // G_MERGE_VALUES
2076 CEFBS_None, // G_BUILD_VECTOR
2077 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2078 CEFBS_None, // G_CONCAT_VECTORS
2079 CEFBS_None, // G_PTRTOINT
2080 CEFBS_None, // G_INTTOPTR
2081 CEFBS_None, // G_BITCAST
2082 CEFBS_None, // G_FREEZE
2083 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2084 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2085 CEFBS_None, // G_INTRINSIC_TRUNC
2086 CEFBS_None, // G_INTRINSIC_ROUND
2087 CEFBS_None, // G_INTRINSIC_LRINT
2088 CEFBS_None, // G_INTRINSIC_LLRINT
2089 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2090 CEFBS_None, // G_READCYCLECOUNTER
2091 CEFBS_None, // G_READSTEADYCOUNTER
2092 CEFBS_None, // G_LOAD
2093 CEFBS_None, // G_SEXTLOAD
2094 CEFBS_None, // G_ZEXTLOAD
2095 CEFBS_None, // G_FPEXTLOAD
2096 CEFBS_None, // G_INDEXED_LOAD
2097 CEFBS_None, // G_INDEXED_SEXTLOAD
2098 CEFBS_None, // G_INDEXED_ZEXTLOAD
2099 CEFBS_None, // G_STORE
2100 CEFBS_None, // G_FPTRUNCSTORE
2101 CEFBS_None, // G_INDEXED_STORE
2102 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2103 CEFBS_None, // G_ATOMIC_CMPXCHG
2104 CEFBS_None, // G_ATOMICRMW_XCHG
2105 CEFBS_None, // G_ATOMICRMW_ADD
2106 CEFBS_None, // G_ATOMICRMW_SUB
2107 CEFBS_None, // G_ATOMICRMW_AND
2108 CEFBS_None, // G_ATOMICRMW_NAND
2109 CEFBS_None, // G_ATOMICRMW_OR
2110 CEFBS_None, // G_ATOMICRMW_XOR
2111 CEFBS_None, // G_ATOMICRMW_MAX
2112 CEFBS_None, // G_ATOMICRMW_MIN
2113 CEFBS_None, // G_ATOMICRMW_UMAX
2114 CEFBS_None, // G_ATOMICRMW_UMIN
2115 CEFBS_None, // G_ATOMICRMW_FADD
2116 CEFBS_None, // G_ATOMICRMW_FSUB
2117 CEFBS_None, // G_ATOMICRMW_FMAX
2118 CEFBS_None, // G_ATOMICRMW_FMIN
2119 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2120 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2121 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2122 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2123 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2124 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2125 CEFBS_None, // G_ATOMICRMW_USUB_COND
2126 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2127 CEFBS_None, // G_FENCE
2128 CEFBS_None, // G_PREFETCH
2129 CEFBS_None, // G_BRCOND
2130 CEFBS_None, // G_BRINDIRECT
2131 CEFBS_None, // G_INVOKE_REGION_START
2132 CEFBS_None, // G_INTRINSIC
2133 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2134 CEFBS_None, // G_INTRINSIC_CONVERGENT
2135 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2136 CEFBS_None, // G_ANYEXT
2137 CEFBS_None, // G_TRUNC
2138 CEFBS_None, // G_TRUNC_SSAT_S
2139 CEFBS_None, // G_TRUNC_SSAT_U
2140 CEFBS_None, // G_TRUNC_USAT_U
2141 CEFBS_None, // G_CONSTANT
2142 CEFBS_None, // G_FCONSTANT
2143 CEFBS_None, // G_VASTART
2144 CEFBS_None, // G_VAARG
2145 CEFBS_None, // G_SEXT
2146 CEFBS_None, // G_SEXT_INREG
2147 CEFBS_None, // G_ZEXT
2148 CEFBS_None, // G_SHL
2149 CEFBS_None, // G_LSHR
2150 CEFBS_None, // G_ASHR
2151 CEFBS_None, // G_FSHL
2152 CEFBS_None, // G_FSHR
2153 CEFBS_None, // G_ROTR
2154 CEFBS_None, // G_ROTL
2155 CEFBS_None, // G_ICMP
2156 CEFBS_None, // G_FCMP
2157 CEFBS_None, // G_SCMP
2158 CEFBS_None, // G_UCMP
2159 CEFBS_None, // G_SELECT
2160 CEFBS_None, // G_UADDO
2161 CEFBS_None, // G_UADDE
2162 CEFBS_None, // G_USUBO
2163 CEFBS_None, // G_USUBE
2164 CEFBS_None, // G_SADDO
2165 CEFBS_None, // G_SADDE
2166 CEFBS_None, // G_SSUBO
2167 CEFBS_None, // G_SSUBE
2168 CEFBS_None, // G_UMULO
2169 CEFBS_None, // G_SMULO
2170 CEFBS_None, // G_UMULH
2171 CEFBS_None, // G_SMULH
2172 CEFBS_None, // G_UADDSAT
2173 CEFBS_None, // G_SADDSAT
2174 CEFBS_None, // G_USUBSAT
2175 CEFBS_None, // G_SSUBSAT
2176 CEFBS_None, // G_USHLSAT
2177 CEFBS_None, // G_SSHLSAT
2178 CEFBS_None, // G_SMULFIX
2179 CEFBS_None, // G_UMULFIX
2180 CEFBS_None, // G_SMULFIXSAT
2181 CEFBS_None, // G_UMULFIXSAT
2182 CEFBS_None, // G_SDIVFIX
2183 CEFBS_None, // G_UDIVFIX
2184 CEFBS_None, // G_SDIVFIXSAT
2185 CEFBS_None, // G_UDIVFIXSAT
2186 CEFBS_None, // G_FADD
2187 CEFBS_None, // G_FSUB
2188 CEFBS_None, // G_FMUL
2189 CEFBS_None, // G_FMA
2190 CEFBS_None, // G_FMAD
2191 CEFBS_None, // G_FDIV
2192 CEFBS_None, // G_FREM
2193 CEFBS_None, // G_FMODF
2194 CEFBS_None, // G_FPOW
2195 CEFBS_None, // G_FPOWI
2196 CEFBS_None, // G_FEXP
2197 CEFBS_None, // G_FEXP2
2198 CEFBS_None, // G_FEXP10
2199 CEFBS_None, // G_FLOG
2200 CEFBS_None, // G_FLOG2
2201 CEFBS_None, // G_FLOG10
2202 CEFBS_None, // G_FLDEXP
2203 CEFBS_None, // G_FFREXP
2204 CEFBS_None, // G_FNEG
2205 CEFBS_None, // G_FPEXT
2206 CEFBS_None, // G_FPTRUNC
2207 CEFBS_None, // G_FPTOSI
2208 CEFBS_None, // G_FPTOUI
2209 CEFBS_None, // G_SITOFP
2210 CEFBS_None, // G_UITOFP
2211 CEFBS_None, // G_FPTOSI_SAT
2212 CEFBS_None, // G_FPTOUI_SAT
2213 CEFBS_None, // G_FABS
2214 CEFBS_None, // G_FCOPYSIGN
2215 CEFBS_None, // G_IS_FPCLASS
2216 CEFBS_None, // G_FCANONICALIZE
2217 CEFBS_None, // G_FMINNUM
2218 CEFBS_None, // G_FMAXNUM
2219 CEFBS_None, // G_FMINNUM_IEEE
2220 CEFBS_None, // G_FMAXNUM_IEEE
2221 CEFBS_None, // G_FMINIMUM
2222 CEFBS_None, // G_FMAXIMUM
2223 CEFBS_None, // G_FMINIMUMNUM
2224 CEFBS_None, // G_FMAXIMUMNUM
2225 CEFBS_None, // G_GET_FPENV
2226 CEFBS_None, // G_SET_FPENV
2227 CEFBS_None, // G_RESET_FPENV
2228 CEFBS_None, // G_GET_FPMODE
2229 CEFBS_None, // G_SET_FPMODE
2230 CEFBS_None, // G_RESET_FPMODE
2231 CEFBS_None, // G_GET_ROUNDING
2232 CEFBS_None, // G_SET_ROUNDING
2233 CEFBS_None, // G_PTR_ADD
2234 CEFBS_None, // G_PTRMASK
2235 CEFBS_None, // G_SMIN
2236 CEFBS_None, // G_SMAX
2237 CEFBS_None, // G_UMIN
2238 CEFBS_None, // G_UMAX
2239 CEFBS_None, // G_ABS
2240 CEFBS_None, // G_LROUND
2241 CEFBS_None, // G_LLROUND
2242 CEFBS_None, // G_BR
2243 CEFBS_None, // G_BRJT
2244 CEFBS_None, // G_VSCALE
2245 CEFBS_None, // G_INSERT_SUBVECTOR
2246 CEFBS_None, // G_EXTRACT_SUBVECTOR
2247 CEFBS_None, // G_INSERT_VECTOR_ELT
2248 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2249 CEFBS_None, // G_SHUFFLE_VECTOR
2250 CEFBS_None, // G_SPLAT_VECTOR
2251 CEFBS_None, // G_STEP_VECTOR
2252 CEFBS_None, // G_VECTOR_COMPRESS
2253 CEFBS_None, // G_CTTZ
2254 CEFBS_None, // G_CTTZ_ZERO_POISON
2255 CEFBS_None, // G_CTLZ
2256 CEFBS_None, // G_CTLZ_ZERO_POISON
2257 CEFBS_None, // G_CTLS
2258 CEFBS_None, // G_CTPOP
2259 CEFBS_None, // G_BSWAP
2260 CEFBS_None, // G_BITREVERSE
2261 CEFBS_None, // G_CLMUL
2262 CEFBS_None, // G_FCEIL
2263 CEFBS_None, // G_FCOS
2264 CEFBS_None, // G_FSIN
2265 CEFBS_None, // G_FSINCOS
2266 CEFBS_None, // G_FTAN
2267 CEFBS_None, // G_FACOS
2268 CEFBS_None, // G_FASIN
2269 CEFBS_None, // G_FATAN
2270 CEFBS_None, // G_FATAN2
2271 CEFBS_None, // G_FCOSH
2272 CEFBS_None, // G_FSINH
2273 CEFBS_None, // G_FTANH
2274 CEFBS_None, // G_FSQRT
2275 CEFBS_None, // G_FFLOOR
2276 CEFBS_None, // G_FRINT
2277 CEFBS_None, // G_FNEARBYINT
2278 CEFBS_None, // G_ADDRSPACE_CAST
2279 CEFBS_None, // G_BLOCK_ADDR
2280 CEFBS_None, // G_JUMP_TABLE
2281 CEFBS_None, // G_DYN_STACKALLOC
2282 CEFBS_None, // G_STACKSAVE
2283 CEFBS_None, // G_STACKRESTORE
2284 CEFBS_None, // G_STRICT_FADD
2285 CEFBS_None, // G_STRICT_FSUB
2286 CEFBS_None, // G_STRICT_FMUL
2287 CEFBS_None, // G_STRICT_FDIV
2288 CEFBS_None, // G_STRICT_FREM
2289 CEFBS_None, // G_STRICT_FMA
2290 CEFBS_None, // G_STRICT_FSQRT
2291 CEFBS_None, // G_STRICT_FLDEXP
2292 CEFBS_None, // G_STRICT_FCMP
2293 CEFBS_None, // G_STRICT_FCMPS
2294 CEFBS_None, // G_READ_REGISTER
2295 CEFBS_None, // G_WRITE_REGISTER
2296 CEFBS_None, // G_MEMCPY
2297 CEFBS_None, // G_MEMCPY_INLINE
2298 CEFBS_None, // G_MEMMOVE
2299 CEFBS_None, // G_MEMSET
2300 CEFBS_None, // G_BZERO
2301 CEFBS_None, // G_MEMSET_INLINE
2302 CEFBS_None, // G_TRAP
2303 CEFBS_None, // G_DEBUGTRAP
2304 CEFBS_None, // G_UBSANTRAP
2305 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2306 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2307 CEFBS_None, // G_VECREDUCE_FADD
2308 CEFBS_None, // G_VECREDUCE_FMUL
2309 CEFBS_None, // G_VECREDUCE_FMAX
2310 CEFBS_None, // G_VECREDUCE_FMIN
2311 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2312 CEFBS_None, // G_VECREDUCE_FMINIMUM
2313 CEFBS_None, // G_VECREDUCE_ADD
2314 CEFBS_None, // G_VECREDUCE_MUL
2315 CEFBS_None, // G_VECREDUCE_AND
2316 CEFBS_None, // G_VECREDUCE_OR
2317 CEFBS_None, // G_VECREDUCE_XOR
2318 CEFBS_None, // G_VECREDUCE_SMAX
2319 CEFBS_None, // G_VECREDUCE_SMIN
2320 CEFBS_None, // G_VECREDUCE_UMAX
2321 CEFBS_None, // G_VECREDUCE_UMIN
2322 CEFBS_None, // G_SBFX
2323 CEFBS_None, // G_UBFX
2324 CEFBS_None, // ADJCALLSTACKDOWN
2325 CEFBS_None, // ADJCALLSTACKUP
2326 CEFBS_None, // BR_JT
2327 CEFBS_None, // BR_JT32
2328 CEFBS_None, // EH_RETURN
2329 CEFBS_None, // FRAME_TO_ARGS_OFFSET
2330 CEFBS_None, // LDAWFI
2331 CEFBS_None, // LDWFI
2332 CEFBS_None, // SELECT_CC
2333 CEFBS_None, // STWFI
2334 CEFBS_None, // ADD_2rus
2335 CEFBS_None, // ADD_3r
2336 CEFBS_None, // ANDNOT_2r
2337 CEFBS_None, // AND_3r
2338 CEFBS_None, // ASHR_l2rus
2339 CEFBS_None, // ASHR_l3r
2340 CEFBS_None, // BAU_1r
2341 CEFBS_None, // BITREV_l2r
2342 CEFBS_None, // BLACP_lu10
2343 CEFBS_None, // BLACP_u10
2344 CEFBS_None, // BLAT_lu6
2345 CEFBS_None, // BLAT_u6
2346 CEFBS_None, // BLA_1r
2347 CEFBS_None, // BLRB_lu10
2348 CEFBS_None, // BLRB_u10
2349 CEFBS_None, // BLRF_lu10
2350 CEFBS_None, // BLRF_u10
2351 CEFBS_None, // BRBF_lru6
2352 CEFBS_None, // BRBF_ru6
2353 CEFBS_None, // BRBT_lru6
2354 CEFBS_None, // BRBT_ru6
2355 CEFBS_None, // BRBU_lu6
2356 CEFBS_None, // BRBU_u6
2357 CEFBS_None, // BRFF_lru6
2358 CEFBS_None, // BRFF_ru6
2359 CEFBS_None, // BRFT_lru6
2360 CEFBS_None, // BRFT_ru6
2361 CEFBS_None, // BRFU_lu6
2362 CEFBS_None, // BRFU_u6
2363 CEFBS_None, // BRU_1r
2364 CEFBS_None, // BYTEREV_l2r
2365 CEFBS_None, // CHKCT_2r
2366 CEFBS_None, // CHKCT_rus
2367 CEFBS_None, // CLRE_0R
2368 CEFBS_None, // CLRPT_1R
2369 CEFBS_None, // CLRSR_branch_lu6
2370 CEFBS_None, // CLRSR_branch_u6
2371 CEFBS_None, // CLRSR_lu6
2372 CEFBS_None, // CLRSR_u6
2373 CEFBS_None, // CLZ_l2r
2374 CEFBS_None, // CRC8_l4r
2375 CEFBS_None, // CRC_l3r
2376 CEFBS_None, // DCALL_0R
2377 CEFBS_None, // DENTSP_0R
2378 CEFBS_None, // DGETREG_1r
2379 CEFBS_None, // DIVS_l3r
2380 CEFBS_None, // DIVU_l3r
2381 CEFBS_None, // DRESTSP_0R
2382 CEFBS_None, // DRET_0R
2383 CEFBS_None, // ECALLF_1r
2384 CEFBS_None, // ECALLT_1r
2385 CEFBS_None, // EDU_1r
2386 CEFBS_None, // EEF_2r
2387 CEFBS_None, // EET_2r
2388 CEFBS_None, // EEU_1r
2389 CEFBS_None, // ENDIN_2r
2390 CEFBS_None, // ENTSP_lu6
2391 CEFBS_None, // ENTSP_u6
2392 CEFBS_None, // EQ_2rus
2393 CEFBS_None, // EQ_3r
2394 CEFBS_None, // EXTDP_lu6
2395 CEFBS_None, // EXTDP_u6
2396 CEFBS_None, // EXTSP_lu6
2397 CEFBS_None, // EXTSP_u6
2398 CEFBS_None, // FREER_1r
2399 CEFBS_None, // FREET_0R
2400 CEFBS_None, // GETD_l2r
2401 CEFBS_None, // GETED_0R
2402 CEFBS_None, // GETET_0R
2403 CEFBS_None, // GETID_0R
2404 CEFBS_None, // GETKEP_0R
2405 CEFBS_None, // GETKSP_0R
2406 CEFBS_None, // GETN_l2r
2407 CEFBS_None, // GETPS_l2r
2408 CEFBS_None, // GETR_rus
2409 CEFBS_None, // GETSR_lu6
2410 CEFBS_None, // GETSR_u6
2411 CEFBS_None, // GETST_2r
2412 CEFBS_None, // GETTS_2r
2413 CEFBS_None, // INCT_2r
2414 CEFBS_None, // INITCP_2r
2415 CEFBS_None, // INITDP_2r
2416 CEFBS_None, // INITLR_l2r
2417 CEFBS_None, // INITPC_2r
2418 CEFBS_None, // INITSP_2r
2419 CEFBS_None, // INPW_l2rus
2420 CEFBS_None, // INSHR_2r
2421 CEFBS_None, // INT_2r
2422 CEFBS_None, // IN_2r
2423 CEFBS_None, // KCALL_1r
2424 CEFBS_None, // KCALL_lu6
2425 CEFBS_None, // KCALL_u6
2426 CEFBS_None, // KENTSP_lu6
2427 CEFBS_None, // KENTSP_u6
2428 CEFBS_None, // KRESTSP_lu6
2429 CEFBS_None, // KRESTSP_u6
2430 CEFBS_None, // KRET_0R
2431 CEFBS_None, // LADD_l5r
2432 CEFBS_None, // LD16S_3r
2433 CEFBS_None, // LD8U_3r
2434 CEFBS_None, // LDA16B_l3r
2435 CEFBS_None, // LDA16F_l3r
2436 CEFBS_None, // LDAPB_lu10
2437 CEFBS_None, // LDAPB_u10
2438 CEFBS_None, // LDAPF_lu10
2439 CEFBS_None, // LDAPF_lu10_ba
2440 CEFBS_None, // LDAPF_u10
2441 CEFBS_None, // LDAWB_l2rus
2442 CEFBS_None, // LDAWB_l3r
2443 CEFBS_None, // LDAWCP_lu6
2444 CEFBS_None, // LDAWCP_u6
2445 CEFBS_None, // LDAWDP_lru6
2446 CEFBS_None, // LDAWDP_ru6
2447 CEFBS_None, // LDAWF_l2rus
2448 CEFBS_None, // LDAWF_l3r
2449 CEFBS_None, // LDAWSP_lru6
2450 CEFBS_None, // LDAWSP_ru6
2451 CEFBS_None, // LDC_lru6
2452 CEFBS_None, // LDC_ru6
2453 CEFBS_None, // LDET_0R
2454 CEFBS_None, // LDIVU_l5r
2455 CEFBS_None, // LDSED_0R
2456 CEFBS_None, // LDSPC_0R
2457 CEFBS_None, // LDSSR_0R
2458 CEFBS_None, // LDWCP_lru6
2459 CEFBS_None, // LDWCP_lu10
2460 CEFBS_None, // LDWCP_ru6
2461 CEFBS_None, // LDWCP_u10
2462 CEFBS_None, // LDWDP_lru6
2463 CEFBS_None, // LDWDP_ru6
2464 CEFBS_None, // LDWSP_lru6
2465 CEFBS_None, // LDWSP_ru6
2466 CEFBS_None, // LDW_2rus
2467 CEFBS_None, // LDW_3r
2468 CEFBS_None, // LMUL_l6r
2469 CEFBS_None, // LSS_3r
2470 CEFBS_None, // LSUB_l5r
2471 CEFBS_None, // LSU_3r
2472 CEFBS_None, // MACCS_l4r
2473 CEFBS_None, // MACCU_l4r
2474 CEFBS_None, // MJOIN_1r
2475 CEFBS_None, // MKMSK_2r
2476 CEFBS_None, // MKMSK_rus
2477 CEFBS_None, // MSYNC_1r
2478 CEFBS_None, // MUL_l3r
2479 CEFBS_None, // NEG
2480 CEFBS_None, // NOT
2481 CEFBS_None, // OR_3r
2482 CEFBS_None, // OUTCT_2r
2483 CEFBS_None, // OUTCT_rus
2484 CEFBS_None, // OUTPW_l2rus
2485 CEFBS_None, // OUTSHR_2r
2486 CEFBS_None, // OUTT_2r
2487 CEFBS_None, // OUT_2r
2488 CEFBS_None, // PEEK_2r
2489 CEFBS_None, // REMS_l3r
2490 CEFBS_None, // REMU_l3r
2491 CEFBS_None, // RETSP_lu6
2492 CEFBS_None, // RETSP_u6
2493 CEFBS_None, // SETCLK_l2r
2494 CEFBS_None, // SETCP_1r
2495 CEFBS_None, // SETC_l2r
2496 CEFBS_None, // SETC_lru6
2497 CEFBS_None, // SETC_ru6
2498 CEFBS_None, // SETDP_1r
2499 CEFBS_None, // SETD_2r
2500 CEFBS_None, // SETEV_1r
2501 CEFBS_None, // SETKEP_0R
2502 CEFBS_None, // SETN_l2r
2503 CEFBS_None, // SETPSC_2r
2504 CEFBS_None, // SETPS_l2r
2505 CEFBS_None, // SETPT_2r
2506 CEFBS_None, // SETRDY_l2r
2507 CEFBS_None, // SETSP_1r
2508 CEFBS_None, // SETSR_branch_lu6
2509 CEFBS_None, // SETSR_branch_u6
2510 CEFBS_None, // SETSR_lu6
2511 CEFBS_None, // SETSR_u6
2512 CEFBS_None, // SETTW_l2r
2513 CEFBS_None, // SETV_1r
2514 CEFBS_None, // SEXT_2r
2515 CEFBS_None, // SEXT_rus
2516 CEFBS_None, // SHL_2rus
2517 CEFBS_None, // SHL_3r
2518 CEFBS_None, // SHR_2rus
2519 CEFBS_None, // SHR_3r
2520 CEFBS_None, // SSYNC_0r
2521 CEFBS_None, // ST16_l3r
2522 CEFBS_None, // ST8_l3r
2523 CEFBS_None, // STET_0R
2524 CEFBS_None, // STSED_0R
2525 CEFBS_None, // STSPC_0R
2526 CEFBS_None, // STSSR_0R
2527 CEFBS_None, // STWDP_lru6
2528 CEFBS_None, // STWDP_ru6
2529 CEFBS_None, // STWSP_lru6
2530 CEFBS_None, // STWSP_ru6
2531 CEFBS_None, // STW_2rus
2532 CEFBS_None, // STW_l3r
2533 CEFBS_None, // SUB_2rus
2534 CEFBS_None, // SUB_3r
2535 CEFBS_None, // SYNCR_1r
2536 CEFBS_None, // TESTCT_2r
2537 CEFBS_None, // TESTLCL_l2r
2538 CEFBS_None, // TESTWCT_2r
2539 CEFBS_None, // TSETMR_2r
2540 CEFBS_None, // TSETR_3r
2541 CEFBS_None, // TSTART_1R
2542 CEFBS_None, // WAITEF_1R
2543 CEFBS_None, // WAITET_1R
2544 CEFBS_None, // WAITEU_0R
2545 CEFBS_None, // XOR_l3r
2546 CEFBS_None, // ZEXT_2r
2547 CEFBS_None, // ZEXT_rus
2548 };
2549
2550 assert(Opcode < 555);
2551 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2552}
2553
2554
2555} // namespace llvm::XCore_MC
2556
2557#endif // GET_COMPUTE_FEATURES
2558
2559#ifdef GET_AVAILABLE_OPCODE_CHECKER
2560#undef GET_AVAILABLE_OPCODE_CHECKER
2561
2562namespace llvm::XCore_MC {
2563
2564bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2565 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2566 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2567 FeatureBitset MissingFeatures =
2568 (AvailableFeatures & RequiredFeatures) ^
2569 RequiredFeatures;
2570 return !MissingFeatures.any();
2571}
2572
2573} // namespace llvm::XCore_MC
2574
2575#endif // GET_AVAILABLE_OPCODE_CHECKER
2576
2577#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2578#undef ENABLE_INSTR_PREDICATE_VERIFIER
2579
2580#include <sstream>
2581
2582namespace llvm::XCore_MC {
2583
2584#ifndef NDEBUG
2585static const char *SubtargetFeatureNames[] = {
2586 nullptr
2587};
2588
2589#endif // NDEBUG
2590
2591void verifyInstructionPredicates(
2592 unsigned Opcode, const FeatureBitset &Features) {
2593#ifndef NDEBUG
2594 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2595 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2596 FeatureBitset MissingFeatures =
2597 (AvailableFeatures & RequiredFeatures) ^
2598 RequiredFeatures;
2599 if (MissingFeatures.any()) {
2600 std::ostringstream Msg;
2601 Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
2602 << " instruction but the ";
2603 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2604 if (MissingFeatures.test(i))
2605 Msg << SubtargetFeatureNames[i] << " ";
2606 Msg << "predicate(s) are not met";
2607 report_fatal_error(Msg.str().c_str());
2608 }
2609#endif // NDEBUG
2610}
2611
2612} // namespace llvm::XCore_MC
2613
2614#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2615
2616