1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::XCore {
13
14 enum {
15 PHI = 0, // Target.td:1329
16 INLINEASM = 1, // Target.td:1335
17 INLINEASM_BR = 2, // Target.td:1341
18 CFI_INSTRUCTION = 3, // Target.td:1350
19 EH_LABEL = 4, // Target.td:1359
20 GC_LABEL = 5, // Target.td:1368
21 ANNOTATION_LABEL = 6, // Target.td:1377
22 KILL = 7, // Target.td:1385
23 EXTRACT_SUBREG = 8, // Target.td:1392
24 INSERT_SUBREG = 9, // Target.td:1398
25 IMPLICIT_DEF = 10, // Target.td:1405
26 INIT_UNDEF = 11, // Target.td:1414
27 SUBREG_TO_REG = 12, // Target.td:1421
28 COPY_TO_REGCLASS = 13, // Target.td:1427
29 DBG_VALUE = 14, // Target.td:1434
30 DBG_VALUE_LIST = 15, // Target.td:1441
31 DBG_INSTR_REF = 16, // Target.td:1448
32 DBG_PHI = 17, // Target.td:1455
33 DBG_LABEL = 18, // Target.td:1462
34 REG_SEQUENCE = 19, // Target.td:1469
35 COPY = 20, // Target.td:1476
36 COPY_LANEMASK = 21, // Target.td:1484
37 BUNDLE = 22, // Target.td:1491
38 LIFETIME_START = 23, // Target.td:1497
39 LIFETIME_END = 24, // Target.td:1504
40 PSEUDO_PROBE = 25, // Target.td:1511
41 ARITH_FENCE = 26, // Target.td:1518
42 STACKMAP = 27, // Target.td:1527
43 FENTRY_CALL = 28, // Target.td:1662
44 PATCHPOINT = 29, // Target.td:1535
45 LOAD_STACK_GUARD = 30, // Target.td:1553
46 PREALLOCATED_SETUP = 31, // Target.td:1561
47 PREALLOCATED_ARG = 32, // Target.td:1567
48 STATEPOINT = 33, // Target.td:1544
49 LOCAL_ESCAPE = 34, // Target.td:1573
50 FAULTING_OP = 35, // Target.td:1582
51 PATCHABLE_OP = 36, // Target.td:1602
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1610
53 PATCHABLE_RET = 38, // Target.td:1617
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1626
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1634
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1642
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1652
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1672
59 FAKE_USE = 44, // Target.td:1592
60 MEMBARRIER = 45, // Target.td:1678
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1686
62 RELOC_NONE = 47, // Target.td:1694
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1706
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1702
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1710
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1714
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1937
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1929
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1944
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1522
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1535
96 G_INSERT = 81, // GenericOpcodes.td:1544
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1554
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1574
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1584
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1591
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1951
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1491
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1492
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1493
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1494
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1495
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1496
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1497
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1498
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1481
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1482
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1483
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1484
149 G_FENCE = 134, // GenericOpcodes.td:1500
150 G_PREFETCH = 135, // GenericOpcodes.td:1507
151 G_BRCOND = 136, // GenericOpcodes.td:1647
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1656
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1679
154 G_INTRINSIC = 139, // GenericOpcodes.td:1599
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1606
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1615
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1623
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1637
265 G_BRJT = 250, // GenericOpcodes.td:1667
266 G_VSCALE = 251, // GenericOpcodes.td:1565
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1711
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1719
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1727
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1735
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1746
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1754
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1762
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1769
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1821
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1822
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1823
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1824
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1825
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1826
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1827
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1828
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1829
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1830
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1686
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1696
318 G_MEMCPY = 303, // GenericOpcodes.td:1836
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1844
320 G_MEMMOVE = 305, // GenericOpcodes.td:1852
321 G_MEMSET = 306, // GenericOpcodes.td:1860
322 G_BZERO = 307, // GenericOpcodes.td:1867
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1874
324 G_TRAP = 309, // GenericOpcodes.td:1884
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1891
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1897
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1785
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1791
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1797
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1798
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1800
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1801
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1802
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1803
335 G_VECREDUCE_FMAXIMUMNUM = 320, // GenericOpcodes.td:1804
336 G_VECREDUCE_FMINIMUMNUM = 321, // GenericOpcodes.td:1805
337 G_VECREDUCE_ADD = 322, // GenericOpcodes.td:1807
338 G_VECREDUCE_MUL = 323, // GenericOpcodes.td:1808
339 G_VECREDUCE_AND = 324, // GenericOpcodes.td:1809
340 G_VECREDUCE_OR = 325, // GenericOpcodes.td:1810
341 G_VECREDUCE_XOR = 326, // GenericOpcodes.td:1811
342 G_VECREDUCE_SMAX = 327, // GenericOpcodes.td:1812
343 G_VECREDUCE_SMIN = 328, // GenericOpcodes.td:1813
344 G_VECREDUCE_UMAX = 329, // GenericOpcodes.td:1814
345 G_VECREDUCE_UMIN = 330, // GenericOpcodes.td:1815
346 G_SBFX = 331, // GenericOpcodes.td:1909
347 G_UBFX = 332, // GenericOpcodes.td:1917
348 ADJCALLSTACKDOWN = 333, // XCoreInstrInfo.td:356
349 ADJCALLSTACKUP = 334, // XCoreInstrInfo.td:359
350 BR_JT = 335, // XCoreInstrInfo.td:991
351 BR_JT32 = 336, // XCoreInstrInfo.td:996
352 EH_RETURN = 337, // XCoreInstrInfo.td:370
353 FRAME_TO_ARGS_OFFSET = 338, // XCoreInstrInfo.td:365
354 LDAWFI = 339, // XCoreInstrInfo.td:378
355 LDWFI = 340, // XCoreInstrInfo.td:374
356 SELECT_CC = 341, // XCoreInstrInfo.td:389
357 STWFI = 342, // XCoreInstrInfo.td:382
358 ADD_2rus = 343, // XCoreInstrInfo.td:247
359 ADD_3r = 344, // XCoreInstrInfo.td:244
360 ANDNOT_2r = 345, // XCoreInstrInfo.td:797
361 AND_3r = 346, // XCoreInstrInfo.td:408
362 ASHR_l2rus = 347, // XCoreInstrInfo.td:296
363 ASHR_l3r = 348, // XCoreInstrInfo.td:293
364 BAU_1r = 349, // XCoreInstrInfo.td:986
365 BITREV_l2r = 350, // XCoreInstrInfo.td:925
366 BLACP_lu10 = 351, // XCoreInstrInfo.td:746
367 BLACP_u10 = 352, // XCoreInstrInfo.td:744
368 BLAT_lu6 = 353, // XCoreInstrInfo.td:340
369 BLAT_u6 = 354, // XCoreInstrInfo.td:339
370 BLA_1r = 355, // XCoreInstrInfo.td:1025
371 BLRB_lu10 = 356, // XCoreInstrInfo.td:756
372 BLRB_u10 = 357, // XCoreInstrInfo.td:754
373 BLRF_lu10 = 358, // XCoreInstrInfo.td:751
374 BLRF_u10 = 359, // XCoreInstrInfo.td:748
375 BRBF_lru6 = 360, // XCoreInstrInfo.td:318
376 BRBF_ru6 = 361, // XCoreInstrInfo.td:316
377 BRBT_lru6 = 362, // XCoreInstrInfo.td:318
378 BRBT_ru6 = 363, // XCoreInstrInfo.td:316
379 BRBU_lu6 = 364, // XCoreInstrInfo.td:679
380 BRBU_u6 = 365, // XCoreInstrInfo.td:677
381 BRFF_lru6 = 366, // XCoreInstrInfo.td:311
382 BRFF_ru6 = 367, // XCoreInstrInfo.td:309
383 BRFT_lru6 = 368, // XCoreInstrInfo.td:311
384 BRFT_ru6 = 369, // XCoreInstrInfo.td:309
385 BRFU_lu6 = 370, // XCoreInstrInfo.td:683
386 BRFU_u6 = 371, // XCoreInstrInfo.td:681
387 BRU_1r = 372, // XCoreInstrInfo.td:1001
388 BYTEREV_l2r = 373, // XCoreInstrInfo.td:929
389 CHKCT_2r = 374, // XCoreInstrInfo.td:863
390 CHKCT_rus = 375, // XCoreInstrInfo.td:867
391 CLRE_0R = 376, // XCoreInstrInfo.td:1070
392 CLRPT_1R = 377, // XCoreInstrInfo.td:1065
393 CLRSR_branch_lu6 = 378, // XCoreInstrInfo.td:340
394 CLRSR_branch_u6 = 379, // XCoreInstrInfo.td:339
395 CLRSR_lu6 = 380, // XCoreInstrInfo.td:334
396 CLRSR_u6 = 381, // XCoreInstrInfo.td:332
397 CLZ_l2r = 382, // XCoreInstrInfo.td:933
398 CRC8_l4r = 383, // XCoreInstrInfo.td:533
399 CRC_l3r = 384, // XCoreInstrInfo.td:494
400 DCALL_0R = 385, // XCoreInstrInfo.td:1072
401 DENTSP_0R = 386, // XCoreInstrInfo.td:1075
402 DGETREG_1r = 387, // XCoreInstrInfo.td:1048
403 DIVS_l3r = 388, // XCoreInstrInfo.td:485
404 DIVU_l3r = 389, // XCoreInstrInfo.td:486
405 DRESTSP_0R = 390, // XCoreInstrInfo.td:1078
406 DRET_0R = 391, // XCoreInstrInfo.td:1080
407 ECALLF_1r = 392, // XCoreInstrInfo.td:1018
408 ECALLT_1r = 393, // XCoreInstrInfo.td:1013
409 EDU_1r = 394, // XCoreInstrInfo.td:1050
410 EEF_2r = 395, // XCoreInstrInfo.td:915
411 EET_2r = 396, // XCoreInstrInfo.td:918
412 EEU_1r = 397, // XCoreInstrInfo.td:1053
413 ENDIN_2r = 398, // XCoreInstrInfo.td:911
414 ENTSP_lu6 = 399, // XCoreInstrInfo.td:340
415 ENTSP_u6 = 400, // XCoreInstrInfo.td:339
416 EQ_2rus = 401, // XCoreInstrInfo.td:255
417 EQ_3r = 402, // XCoreInstrInfo.td:253
418 EXTDP_lu6 = 403, // XCoreInstrInfo.td:340
419 EXTDP_u6 = 404, // XCoreInstrInfo.td:339
420 EXTSP_lu6 = 405, // XCoreInstrInfo.td:340
421 EXTSP_u6 = 406, // XCoreInstrInfo.td:339
422 FREER_1r = 407, // XCoreInstrInfo.td:1034
423 FREET_0R = 408, // XCoreInstrInfo.td:1082
424 GETD_l2r = 409, // XCoreInstrInfo.td:937
425 GETED_0R = 410, // XCoreInstrInfo.td:1089
426 GETET_0R = 411, // XCoreInstrInfo.td:1093
427 GETID_0R = 412, // XCoreInstrInfo.td:1085
428 GETKEP_0R = 413, // XCoreInstrInfo.td:1097
429 GETKSP_0R = 414, // XCoreInstrInfo.td:1100
430 GETN_l2r = 415, // XCoreInstrInfo.td:940
431 GETPS_l2r = 416, // XCoreInstrInfo.td:951
432 GETR_rus = 417, // XCoreInstrInfo.td:811
433 GETSR_lu6 = 418, // XCoreInstrInfo.td:340
434 GETSR_u6 = 419, // XCoreInstrInfo.td:339
435 GETST_2r = 420, // XCoreInstrInfo.td:887
436 GETTS_2r = 421, // XCoreInstrInfo.td:815
437 INCT_2r = 422, // XCoreInstrInfo.td:845
438 INITCP_2r = 423, // XCoreInstrInfo.td:899
439 INITDP_2r = 424, // XCoreInstrInfo.td:903
440 INITLR_l2r = 425, // XCoreInstrInfo.td:959
441 INITPC_2r = 426, // XCoreInstrInfo.td:895
442 INITSP_2r = 427, // XCoreInstrInfo.td:891
443 INPW_l2rus = 428, // XCoreInstrInfo.td:511
444 INSHR_2r = 429, // XCoreInstrInfo.td:858
445 INT_2r = 430, // XCoreInstrInfo.td:849
446 IN_2r = 431, // XCoreInstrInfo.td:853
447 KCALL_1r = 432, // XCoreInstrInfo.td:1057
448 KCALL_lu6 = 433, // XCoreInstrInfo.td:340
449 KCALL_u6 = 434, // XCoreInstrInfo.td:339
450 KENTSP_lu6 = 435, // XCoreInstrInfo.td:340
451 KENTSP_u6 = 436, // XCoreInstrInfo.td:339
452 KRESTSP_lu6 = 437, // XCoreInstrInfo.td:340
453 KRESTSP_u6 = 438, // XCoreInstrInfo.td:339
454 KRET_0R = 439, // XCoreInstrInfo.td:1105
455 LADD_l5r = 440, // XCoreInstrInfo.td:541
456 LD16S_3r = 441, // XCoreInstrInfo.td:420
457 LD8U_3r = 442, // XCoreInstrInfo.td:424
458 LDA16B_l3r = 443, // XCoreInstrInfo.td:476
459 LDA16F_l3r = 444, // XCoreInstrInfo.td:470
460 LDAPB_lu10 = 445, // XCoreInstrInfo.td:732
461 LDAPB_u10 = 446, // XCoreInstrInfo.td:728
462 LDAPF_lu10 = 447, // XCoreInstrInfo.td:724
463 LDAPF_lu10_ba = 448, // XCoreInstrInfo.td:737
464 LDAPF_u10 = 449, // XCoreInstrInfo.td:722
465 LDAWB_l2rus = 450, // XCoreInstrInfo.td:466
466 LDAWB_l3r = 451, // XCoreInstrInfo.td:459
467 LDAWCP_lu6 = 452, // XCoreInstrInfo.td:692
468 LDAWCP_u6 = 453, // XCoreInstrInfo.td:688
469 LDAWDP_lru6 = 454, // XCoreInstrInfo.td:574
470 LDAWDP_ru6 = 455, // XCoreInstrInfo.td:570
471 LDAWF_l2rus = 456, // XCoreInstrInfo.td:455
472 LDAWF_l3r = 457, // XCoreInstrInfo.td:448
473 LDAWSP_lru6 = 458, // XCoreInstrInfo.td:628
474 LDAWSP_ru6 = 459, // XCoreInstrInfo.td:625
475 LDC_lru6 = 460, // XCoreInstrInfo.td:637
476 LDC_ru6 = 461, // XCoreInstrInfo.td:634
477 LDET_0R = 462, // XCoreInstrInfo.td:1108
478 LDIVU_l5r = 463, // XCoreInstrInfo.td:553
479 LDSED_0R = 464, // XCoreInstrInfo.td:1110
480 LDSPC_0R = 465, // XCoreInstrInfo.td:1112
481 LDSSR_0R = 466, // XCoreInstrInfo.td:1114
482 LDWCP_lru6 = 467, // XCoreInstrInfo.td:598
483 LDWCP_lu10 = 468, // XCoreInstrInfo.td:763
484 LDWCP_ru6 = 469, // XCoreInstrInfo.td:596
485 LDWCP_u10 = 470, // XCoreInstrInfo.td:761
486 LDWDP_lru6 = 471, // XCoreInstrInfo.td:582
487 LDWDP_ru6 = 472, // XCoreInstrInfo.td:579
488 LDWSP_lru6 = 473, // XCoreInstrInfo.td:619
489 LDWSP_ru6 = 474, // XCoreInstrInfo.td:615
490 LDW_2rus = 475, // XCoreInstrInfo.td:416
491 LDW_3r = 476, // XCoreInstrInfo.td:412
492 LMUL_l6r = 477, // XCoreInstrInfo.td:559
493 LSS_3r = 478, // XCoreInstrInfo.td:405
494 LSUB_l5r = 479, // XCoreInstrInfo.td:547
495 LSU_3r = 480, // XCoreInstrInfo.td:406
496 MACCS_l4r = 481, // XCoreInstrInfo.td:526
497 MACCU_l4r = 482, // XCoreInstrInfo.td:521
498 MJOIN_1r = 483, // XCoreInstrInfo.td:981
499 MKMSK_2r = 484, // XCoreInstrInfo.td:807
500 MKMSK_rus = 485, // XCoreInstrInfo.td:804
501 MSYNC_1r = 486, // XCoreInstrInfo.td:978
502 MUL_l3r = 487, // XCoreInstrInfo.td:482
503 NEG = 488, // XCoreInstrInfo.td:771
504 NOT = 489, // XCoreInstrInfo.td:768
505 OR_3r = 490, // XCoreInstrInfo.td:409
506 OUTCT_2r = 491, // XCoreInstrInfo.td:823
507 OUTCT_rus = 492, // XCoreInstrInfo.td:827
508 OUTPW_l2rus = 493, // XCoreInstrInfo.td:515
509 OUTSHR_2r = 494, // XCoreInstrInfo.td:840
510 OUTT_2r = 495, // XCoreInstrInfo.td:831
511 OUT_2r = 496, // XCoreInstrInfo.td:835
512 PEEK_2r = 497, // XCoreInstrInfo.td:907
513 REMS_l3r = 498, // XCoreInstrInfo.td:487
514 REMU_l3r = 499, // XCoreInstrInfo.td:488
515 RETSP_lu6 = 500, // XCoreInstrInfo.td:327
516 RETSP_u6 = 501, // XCoreInstrInfo.td:325
517 SETCLK_l2r = 502, // XCoreInstrInfo.td:963
518 SETCP_1r = 503, // XCoreInstrInfo.td:1010
519 SETC_l2r = 504, // XCoreInstrInfo.td:943
520 SETC_lru6 = 505, // XCoreInstrInfo.td:645
521 SETC_ru6 = 506, // XCoreInstrInfo.td:641
522 SETDP_1r = 507, // XCoreInstrInfo.td:1007
523 SETD_2r = 508, // XCoreInstrInfo.td:879
524 SETEV_1r = 509, // XCoreInstrInfo.td:1043
525 SETKEP_0R = 510, // XCoreInstrInfo.td:1118
526 SETN_l2r = 511, // XCoreInstrInfo.td:967
527 SETPSC_2r = 512, // XCoreInstrInfo.td:883
528 SETPS_l2r = 513, // XCoreInstrInfo.td:955
529 SETPT_2r = 514, // XCoreInstrInfo.td:819
530 SETRDY_l2r = 515, // XCoreInstrInfo.td:970
531 SETSP_1r = 516, // XCoreInstrInfo.td:1004
532 SETSR_branch_lu6 = 517, // XCoreInstrInfo.td:340
533 SETSR_branch_u6 = 518, // XCoreInstrInfo.td:339
534 SETSR_lu6 = 519, // XCoreInstrInfo.td:334
535 SETSR_u6 = 520, // XCoreInstrInfo.td:332
536 SETTW_l2r = 521, // XCoreInstrInfo.td:947
537 SETV_1r = 522, // XCoreInstrInfo.td:1039
538 SEXT_2r = 523, // XCoreInstrInfo.td:781
539 SEXT_rus = 524, // XCoreInstrInfo.td:775
540 SHL_2rus = 525, // XCoreInstrInfo.td:264
541 SHL_3r = 526, // XCoreInstrInfo.td:261
542 SHR_2rus = 527, // XCoreInstrInfo.td:264
543 SHR_3r = 528, // XCoreInstrInfo.td:261
544 SSYNC_0r = 529, // XCoreInstrInfo.td:1120
545 ST16_l3r = 530, // XCoreInstrInfo.td:502
546 ST8_l3r = 531, // XCoreInstrInfo.td:506
547 STET_0R = 532, // XCoreInstrInfo.td:1125
548 STSED_0R = 533, // XCoreInstrInfo.td:1127
549 STSPC_0R = 534, // XCoreInstrInfo.td:1129
550 STSSR_0R = 535, // XCoreInstrInfo.td:1131
551 STWDP_lru6 = 536, // XCoreInstrInfo.td:590
552 STWDP_ru6 = 537, // XCoreInstrInfo.td:587
553 STWSP_lru6 = 538, // XCoreInstrInfo.td:609
554 STWSP_ru6 = 539, // XCoreInstrInfo.td:605
555 STW_2rus = 540, // XCoreInstrInfo.td:434
556 STW_l3r = 541, // XCoreInstrInfo.td:430
557 SUB_2rus = 542, // XCoreInstrInfo.td:247
558 SUB_3r = 543, // XCoreInstrInfo.td:244
559 SYNCR_1r = 544, // XCoreInstrInfo.td:1030
560 TESTCT_2r = 545, // XCoreInstrInfo.td:871
561 TESTLCL_l2r = 546, // XCoreInstrInfo.td:974
562 TESTWCT_2r = 547, // XCoreInstrInfo.td:875
563 TSETMR_2r = 548, // XCoreInstrInfo.td:921
564 TSETR_3r = 549, // XCoreInstrInfo.td:444
565 TSTART_1R = 550, // XCoreInstrInfo.td:1063
566 WAITEF_1R = 551, // XCoreInstrInfo.td:1059
567 WAITET_1R = 552, // XCoreInstrInfo.td:1061
568 WAITEU_0R = 553, // XCoreInstrInfo.td:1136
569 XOR_l3r = 554, // XCoreInstrInfo.td:490
570 ZEXT_2r = 555, // XCoreInstrInfo.td:792
571 ZEXT_rus = 556, // XCoreInstrInfo.td:786
572 INSTRUCTION_LIST_END = 557
573 };
574
575} // namespace llvm::XCore
576
577#endif // GET_INSTRINFO_ENUM
578
579#ifdef GET_INSTRINFO_SCHED_ENUM
580#undef GET_INSTRINFO_SCHED_ENUM
581
582namespace llvm::XCore::Sched {
583
584 enum {
585 NoInstrModel = 0,
586 SCHED_LIST_END = 1
587 };
588
589} // namespace llvm::XCore::Sched
590
591#endif // GET_INSTRINFO_SCHED_ENUM
592
593#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
594
595namespace llvm {
596
597struct XCoreInstrTable {
598 MCInstrDesc Insts[557];
599 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
600 MCPhysReg ImplicitOps[11];
601 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
602 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
603 MCOperandInfo OperandInfo[209];
604};
605} // namespace llvm
606
607#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
608
609#ifdef GET_INSTRINFO_MC_DESC
610#undef GET_INSTRINFO_MC_DESC
611
612namespace llvm {
613
614static_assert((sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
615static constexpr unsigned XCoreOpInfoBase = (sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) / sizeof(MCOperandInfo);
616
617extern const XCoreInstrTable XCoreDescs = {
618 {
619 { 556, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_rus
620 { 555, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_2r
621 { 554, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_l3r
622 { 553, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEU_0R
623 { 552, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITET_1R
624 { 551, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEF_1R
625 { 550, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSTART_1R
626 { 549, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETR_3r
627 { 548, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETMR_2r
628 { 547, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTWCT_2r
629 { 546, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTLCL_l2r
630 { 545, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTCT_2r
631 { 544, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SYNCR_1r
632 { 543, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_3r
633 { 542, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_2rus
634 { 541, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_l3r
635 { 540, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_2rus
636 { 539, 2, 0, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_ru6
637 { 538, 2, 0, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_lru6
638 { 537, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_ru6
639 { 536, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_lru6
640 { 535, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSSR_0R
641 { 534, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSPC_0R
642 { 533, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSED_0R
643 { 532, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STET_0R
644 { 531, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST8_l3r
645 { 530, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST16_l3r
646 { 529, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SSYNC_0r
647 { 528, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_3r
648 { 527, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_2rus
649 { 526, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_3r
650 { 525, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_2rus
651 { 524, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_rus
652 { 523, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_2r
653 { 522, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETV_1r
654 { 521, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETTW_l2r
655 { 520, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_u6
656 { 519, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_lu6
657 { 518, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_u6
658 { 517, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_lu6
659 { 516, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 28, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSP_1r
660 { 515, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETRDY_l2r
661 { 514, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPT_2r
662 { 513, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPS_l2r
663 { 512, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPSC_2r
664 { 511, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETN_l2r
665 { 510, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETKEP_0R
666 { 509, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETEV_1r
667 { 508, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETD_2r
668 { 507, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETDP_1r
669 { 506, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_ru6
670 { 505, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_lru6
671 { 504, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_l2r
672 { 503, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCP_1r
673 { 502, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCLK_l2r
674 { 501, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_u6
675 { 500, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_lu6
676 { 499, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMU_l3r
677 { 498, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMS_l3r
678 { 497, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PEEK_2r
679 { 496, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUT_2r
680 { 495, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTT_2r
681 { 494, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTSHR_2r
682 { 493, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTPW_l2rus
683 { 492, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_rus
684 { 491, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_2r
685 { 490, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_3r
686 { 489, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
687 { 488, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG
688 { 487, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_l3r
689 { 486, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MSYNC_1r
690 { 485, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_rus
691 { 484, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_2r
692 { 483, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MJOIN_1r
693 { 482, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCU_l4r
694 { 481, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCS_l4r
695 { 480, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSU_3r
696 { 479, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSUB_l5r
697 { 478, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSS_3r
698 { 477, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 189, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LMUL_l6r
699 { 476, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_3r
700 { 475, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_2rus
701 { 474, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_ru6
702 { 473, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_lru6
703 { 472, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_ru6
704 { 471, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_lru6
705 { 470, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_u10
706 { 469, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_ru6
707 { 468, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lu10
708 { 467, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lru6
709 { 466, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSSR_0R
710 { 465, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSPC_0R
711 { 464, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSED_0R
712 { 463, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIVU_l5r
713 { 462, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDET_0R
714 { 461, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_ru6
715 { 460, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_lru6
716 { 459, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_ru6
717 { 458, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_lru6
718 { 457, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l3r
719 { 456, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l2rus
720 { 455, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_ru6
721 { 454, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_lru6
722 { 453, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_u6
723 { 452, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_lu6
724 { 451, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l3r
725 { 450, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l2rus
726 { 449, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_u10
727 { 448, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10_ba
728 { 447, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10
729 { 446, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_u10
730 { 445, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_lu10
731 { 444, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16F_l3r
732 { 443, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16B_l3r
733 { 442, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD8U_3r
734 { 441, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD16S_3r
735 { 440, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LADD_l5r
736 { 439, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRET_0R
737 { 438, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_u6
738 { 437, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_lu6
739 { 436, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_u6
740 { 435, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_lu6
741 { 434, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_u6
742 { 433, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_lu6
743 { 432, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_1r
744 { 431, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IN_2r
745 { 430, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INT_2r
746 { 429, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSHR_2r
747 { 428, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INPW_l2rus
748 { 427, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITSP_2r
749 { 426, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITPC_2r
750 { 425, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITLR_l2r
751 { 424, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITDP_2r
752 { 423, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITCP_2r
753 { 422, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INCT_2r
754 { 421, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETTS_2r
755 { 420, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETST_2r
756 { 419, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_u6
757 { 418, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_lu6
758 { 417, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETR_rus
759 { 416, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETPS_l2r
760 { 415, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETN_l2r
761 { 414, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKSP_0R
762 { 413, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKEP_0R
763 { 412, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETID_0R
764 { 411, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETET_0R
765 { 410, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETED_0R
766 { 409, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETD_l2r
767 { 408, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREET_0R
768 { 407, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREER_1r
769 { 406, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_u6
770 { 405, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_lu6
771 { 404, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_u6
772 { 403, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_lu6
773 { 402, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_3r
774 { 401, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_2rus
775 { 400, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_u6
776 { 399, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_lu6
777 { 398, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENDIN_2r
778 { 397, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEU_1r
779 { 396, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EET_2r
780 { 395, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEF_2r
781 { 394, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EDU_1r
782 { 393, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLT_1r
783 { 392, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLF_1r
784 { 391, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRET_0R
785 { 390, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRESTSP_0R
786 { 389, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVU_l3r
787 { 388, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVS_l3r
788 { 387, 1, 1, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DGETREG_1r
789 { 386, 0, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DENTSP_0R
790 { 385, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DCALL_0R
791 { 384, 4, 1, 4, 0, 0, 0, XCoreOpInfoBase + 178, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC_l3r
792 { 383, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 173, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC8_l4r
793 { 382, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_l2r
794 { 381, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_u6
795 { 380, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_lu6
796 { 379, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_u6
797 { 378, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_lu6
798 { 377, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRPT_1R
799 { 376, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRE_0R
800 { 375, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_rus
801 { 374, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_2r
802 { 373, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BYTEREV_l2r
803 { 372, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRU_1r
804 { 371, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_u6
805 { 370, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_lu6
806 { 369, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_ru6
807 { 368, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_lru6
808 { 367, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_ru6
809 { 366, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_lru6
810 { 365, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_u6
811 { 364, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_lu6
812 { 363, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_ru6
813 { 362, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_lru6
814 { 361, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_ru6
815 { 360, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_lru6
816 { 359, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_u10
817 { 358, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_lu10
818 { 357, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_u10
819 { 356, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_lu10
820 { 355, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 28, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLA_1r
821 { 354, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_u6
822 { 353, 1, 0, 4, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_lu6
823 { 352, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_u10
824 { 351, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_lu10
825 { 350, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITREV_l2r
826 { 349, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BAU_1r
827 { 348, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l3r
828 { 347, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l2rus
829 { 346, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_3r
830 { 345, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_2r
831 { 344, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_3r
832 { 343, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_2rus
833 { 342, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWFI
834 { 341, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_CC
835 { 340, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWFI
836 { 339, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWFI
837 { 338, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FRAME_TO_ARGS_OFFSET
838 { 337, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_RETURN
839 { 336, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT32
840 { 335, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT
841 { 334, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
842 { 333, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
843 { 332, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
844 { 331, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
845 { 330, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
846 { 329, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
847 { 328, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
848 { 327, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
849 { 326, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
850 { 325, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
851 { 324, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
852 { 323, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
853 { 322, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
854 { 321, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
855 { 320, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
856 { 319, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
857 { 318, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
858 { 317, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
859 { 316, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
860 { 315, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
861 { 314, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
862 { 313, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
863 { 312, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
864 { 311, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
865 { 310, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
866 { 309, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
867 { 308, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
868 { 307, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
869 { 306, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
870 { 305, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
871 { 304, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
872 { 303, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
873 { 302, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
874 { 301, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
875 { 300, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
876 { 299, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
877 { 298, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
878 { 297, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
879 { 296, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
880 { 295, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
881 { 294, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
882 { 293, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
883 { 292, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
884 { 291, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
885 { 290, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
886 { 289, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
887 { 288, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
888 { 287, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
889 { 286, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
890 { 285, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
891 { 284, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
892 { 283, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
893 { 282, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
894 { 281, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
895 { 280, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
896 { 279, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
897 { 278, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
898 { 277, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
899 { 276, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
900 { 275, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
901 { 274, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
902 { 273, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
903 { 272, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
904 { 271, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
905 { 270, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
906 { 269, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
907 { 268, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
908 { 267, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
909 { 266, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
910 { 265, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
911 { 264, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
912 { 263, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
913 { 262, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
914 { 261, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
915 { 260, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
916 { 259, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
917 { 258, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
918 { 257, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
919 { 256, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
920 { 255, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
921 { 254, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
922 { 253, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
923 { 252, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
924 { 251, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
925 { 250, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
926 { 249, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
927 { 248, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
928 { 247, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
929 { 246, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
930 { 245, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
931 { 244, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
932 { 243, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
933 { 242, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
934 { 241, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
935 { 240, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
936 { 239, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
937 { 238, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
938 { 237, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
939 { 236, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
940 { 235, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
941 { 234, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
942 { 233, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
943 { 232, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
944 { 231, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
945 { 230, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
946 { 229, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
947 { 228, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
948 { 227, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
949 { 226, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
950 { 225, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
951 { 224, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
952 { 223, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
953 { 222, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
954 { 221, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
955 { 220, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
956 { 219, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
957 { 218, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
958 { 217, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
959 { 216, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
960 { 215, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
961 { 214, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
962 { 213, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
963 { 212, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
964 { 211, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
965 { 210, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
966 { 209, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
967 { 208, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
968 { 207, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
969 { 206, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
970 { 205, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
971 { 204, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
972 { 203, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
973 { 202, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
974 { 201, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
975 { 200, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
976 { 199, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
977 { 198, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
978 { 197, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
979 { 196, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
980 { 195, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
981 { 194, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
982 { 193, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
983 { 192, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
984 { 191, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
985 { 190, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
986 { 189, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
987 { 188, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
988 { 187, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
989 { 186, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
990 { 185, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
991 { 184, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
992 { 183, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
993 { 182, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
994 { 181, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
995 { 180, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
996 { 179, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
997 { 178, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
998 { 177, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
999 { 176, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1000 { 175, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1001 { 174, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1002 { 173, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1003 { 172, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1004 { 171, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1005 { 170, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1006 { 169, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1007 { 168, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1008 { 167, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1009 { 166, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1010 { 165, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1011 { 164, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1012 { 163, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1013 { 162, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1014 { 161, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1015 { 160, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1016 { 159, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1017 { 158, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1018 { 157, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1019 { 156, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1020 { 155, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1021 { 154, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1022 { 153, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1023 { 152, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1024 { 151, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1025 { 150, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1026 { 149, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1027 { 148, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1028 { 147, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1029 { 146, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1030 { 145, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1031 { 144, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1032 { 143, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1033 { 142, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1034 { 141, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1035 { 140, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1036 { 139, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1037 { 138, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1038 { 137, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1039 { 136, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1040 { 135, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1041 { 134, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1042 { 133, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1043 { 132, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1044 { 131, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1045 { 130, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1046 { 129, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1047 { 128, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1048 { 127, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1049 { 126, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1050 { 125, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1051 { 124, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1052 { 123, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1053 { 122, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1054 { 121, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1055 { 120, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1056 { 119, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1057 { 118, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1058 { 117, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1059 { 116, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1060 { 115, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1061 { 114, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1062 { 113, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1063 { 112, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1064 { 111, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1065 { 110, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1066 { 109, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1067 { 108, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1068 { 107, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1069 { 106, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1070 { 105, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1071 { 104, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1072 { 103, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1073 { 102, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1074 { 101, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1075 { 100, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1076 { 99, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1077 { 98, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1078 { 97, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1079 { 96, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1080 { 95, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1081 { 94, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1082 { 93, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1083 { 92, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1084 { 91, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1085 { 90, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1086 { 89, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1087 { 88, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1088 { 87, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1089 { 86, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1090 { 85, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1091 { 84, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1092 { 83, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1093 { 82, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1094 { 81, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1095 { 80, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1096 { 79, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1097 { 78, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1098 { 77, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1099 { 76, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1100 { 75, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1101 { 74, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1102 { 73, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1103 { 72, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1104 { 71, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1105 { 70, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1106 { 69, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1107 { 68, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1108 { 67, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1109 { 66, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1110 { 65, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1111 { 64, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1112 { 63, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1113 { 62, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1114 { 61, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1115 { 60, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1116 { 59, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1117 { 58, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1118 { 57, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1119 { 56, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1120 { 55, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1121 { 54, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1122 { 53, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1123 { 52, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1124 { 51, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1125 { 50, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1126 { 49, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1127 { 48, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1128 { 47, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1129 { 46, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1130 { 45, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1131 { 44, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1132 { 43, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1133 { 42, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14345
1134 { 41, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14344
1135 { 40, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1136 { 39, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1137 { 38, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1138 { 37, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1139 { 36, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1140 { 35, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1141 { 34, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1142 { 33, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1143 { 32, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14343
1144 { 31, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1145 { 30, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13978
1146 { 29, 6, 1, 0, 0, 0, 0, XCoreOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1147 { 28, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1148 { 27, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1149 { 26, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1150 { 25, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1151 { 24, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1152 { 23, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1153 { 22, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1154 { 21, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1155 { 20, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1156 { 19, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1157 { 18, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1158 { 17, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1159 { 16, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1160 { 15, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1161 { 14, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1162 { 13, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1163 { 12, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1164 { 11, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1165 { 10, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1166 { 9, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1167 { 8, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1168 { 7, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1169 { 6, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1170 { 5, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1171 { 4, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1172 { 3, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1173 { 2, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1174 { 1, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1175 { 0, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1176 }, {
1177 /* 0 */
1178 /* 0 */ XCore::SP, XCore::SP,
1179 /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
1180 /* 9 */ XCore::R11,
1181 /* 10 */ XCore::SP,
1182 }, {
1183 0
1184 }, {
1185 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1186 /* 1 */
1187 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1188 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1189 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1190 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1191 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1192 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1193 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1194 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1195 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1196 /* 28 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1197 /* 29 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1198 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1199 /* 34 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1200 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1201 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1202 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1203 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1204 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1205 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1206 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1207 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1208 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1209 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1210 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1211 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1212 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1213 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1214 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1215 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1216 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1217 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1218 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1219 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1220 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1221 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1222 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1223 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1224 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1225 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1226 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1227 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1228 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1229 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1230 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1231 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1232 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1233 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1234 /* 153 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1235 /* 155 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1236 /* 158 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1237 /* 162 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1238 /* 165 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1239 /* 168 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1240 /* 171 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1241 /* 173 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1242 /* 178 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1243 /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1244 /* 187 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1245 /* 189 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1246 /* 195 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1247 /* 201 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1248 /* 204 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1249 /* 206 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1250 }
1251};
1252
1253
1254#ifdef __GNUC__
1255#pragma GCC diagnostic push
1256#pragma GCC diagnostic ignored "-Woverlength-strings"
1257#endif
1258extern const char XCoreInstrNameData[] = {
1259 /* 0 */ "G_FLOG10\000"
1260 /* 9 */ "G_FEXP10\000"
1261 /* 18 */ "LDAPB_u10\000"
1262 /* 28 */ "BLRB_u10\000"
1263 /* 37 */ "LDAPF_u10\000"
1264 /* 47 */ "BLRF_u10\000"
1265 /* 56 */ "BLACP_u10\000"
1266 /* 66 */ "LDWCP_u10\000"
1267 /* 76 */ "LDAPB_lu10\000"
1268 /* 87 */ "BLRB_lu10\000"
1269 /* 97 */ "LDAPF_lu10\000"
1270 /* 108 */ "BLRF_lu10\000"
1271 /* 118 */ "BLACP_lu10\000"
1272 /* 129 */ "LDWCP_lu10\000"
1273 /* 140 */ "BR_JT32\000"
1274 /* 148 */ "G_FLOG2\000"
1275 /* 156 */ "G_FATAN2\000"
1276 /* 165 */ "G_FEXP2\000"
1277 /* 173 */ "KCALL_u6\000"
1278 /* 182 */ "LDAWCP_u6\000"
1279 /* 192 */ "EXTDP_u6\000"
1280 /* 201 */ "RETSP_u6\000"
1281 /* 210 */ "KENTSP_u6\000"
1282 /* 220 */ "KRESTSP_u6\000"
1283 /* 231 */ "EXTSP_u6\000"
1284 /* 240 */ "CLRSR_u6\000"
1285 /* 249 */ "GETSR_u6\000"
1286 /* 258 */ "SETSR_u6\000"
1287 /* 267 */ "BLAT_u6\000"
1288 /* 275 */ "BRBU_u6\000"
1289 /* 283 */ "BRFU_u6\000"
1290 /* 291 */ "CLRSR_branch_u6\000"
1291 /* 307 */ "SETSR_branch_u6\000"
1292 /* 323 */ "KCALL_lu6\000"
1293 /* 333 */ "LDAWCP_lu6\000"
1294 /* 344 */ "EXTDP_lu6\000"
1295 /* 354 */ "RETSP_lu6\000"
1296 /* 364 */ "KENTSP_lu6\000"
1297 /* 375 */ "KRESTSP_lu6\000"
1298 /* 387 */ "EXTSP_lu6\000"
1299 /* 397 */ "CLRSR_lu6\000"
1300 /* 407 */ "GETSR_lu6\000"
1301 /* 417 */ "SETSR_lu6\000"
1302 /* 427 */ "BLAT_lu6\000"
1303 /* 436 */ "BRBU_lu6\000"
1304 /* 445 */ "BRFU_lu6\000"
1305 /* 454 */ "CLRSR_branch_lu6\000"
1306 /* 471 */ "SETSR_branch_lu6\000"
1307 /* 488 */ "LDC_ru6\000"
1308 /* 496 */ "SETC_ru6\000"
1309 /* 505 */ "BRBF_ru6\000"
1310 /* 514 */ "BRFF_ru6\000"
1311 /* 523 */ "LDWCP_ru6\000"
1312 /* 533 */ "LDAWDP_ru6\000"
1313 /* 544 */ "LDWDP_ru6\000"
1314 /* 554 */ "STWDP_ru6\000"
1315 /* 564 */ "LDAWSP_ru6\000"
1316 /* 575 */ "LDWSP_ru6\000"
1317 /* 585 */ "STWSP_ru6\000"
1318 /* 595 */ "BRBT_ru6\000"
1319 /* 604 */ "BRFT_ru6\000"
1320 /* 613 */ "LDC_lru6\000"
1321 /* 622 */ "SETC_lru6\000"
1322 /* 632 */ "BRBF_lru6\000"
1323 /* 642 */ "BRFF_lru6\000"
1324 /* 652 */ "LDWCP_lru6\000"
1325 /* 663 */ "LDAWDP_lru6\000"
1326 /* 675 */ "LDWDP_lru6\000"
1327 /* 686 */ "STWDP_lru6\000"
1328 /* 697 */ "LDAWSP_lru6\000"
1329 /* 709 */ "LDWSP_lru6\000"
1330 /* 720 */ "STWSP_lru6\000"
1331 /* 731 */ "BRBT_lru6\000"
1332 /* 741 */ "BRFT_lru6\000"
1333 /* 751 */ "G_FMA\000"
1334 /* 757 */ "G_STRICT_FMA\000"
1335 /* 770 */ "G_FSUB\000"
1336 /* 777 */ "G_STRICT_FSUB\000"
1337 /* 791 */ "G_ATOMICRMW_FSUB\000"
1338 /* 808 */ "G_SUB\000"
1339 /* 814 */ "G_ATOMICRMW_SUB\000"
1340 /* 830 */ "SELECT_CC\000"
1341 /* 840 */ "G_INTRINSIC\000"
1342 /* 852 */ "G_FPTRUNC\000"
1343 /* 862 */ "G_INTRINSIC_TRUNC\000"
1344 /* 880 */ "G_TRUNC\000"
1345 /* 888 */ "G_BUILD_VECTOR_TRUNC\000"
1346 /* 909 */ "G_DYN_STACKALLOC\000"
1347 /* 926 */ "G_FMAD\000"
1348 /* 933 */ "G_FPEXTLOAD\000"
1349 /* 945 */ "G_INDEXED_SEXTLOAD\000"
1350 /* 964 */ "G_SEXTLOAD\000"
1351 /* 975 */ "G_INDEXED_ZEXTLOAD\000"
1352 /* 994 */ "G_ZEXTLOAD\000"
1353 /* 1005 */ "G_INDEXED_LOAD\000"
1354 /* 1020 */ "G_LOAD\000"
1355 /* 1027 */ "G_VECREDUCE_FADD\000"
1356 /* 1044 */ "G_FADD\000"
1357 /* 1051 */ "G_VECREDUCE_SEQ_FADD\000"
1358 /* 1072 */ "G_STRICT_FADD\000"
1359 /* 1086 */ "G_ATOMICRMW_FADD\000"
1360 /* 1103 */ "G_VECREDUCE_ADD\000"
1361 /* 1119 */ "G_ADD\000"
1362 /* 1125 */ "G_PTR_ADD\000"
1363 /* 1135 */ "G_ATOMICRMW_ADD\000"
1364 /* 1151 */ "G_ATOMICRMW_NAND\000"
1365 /* 1168 */ "G_VECREDUCE_AND\000"
1366 /* 1184 */ "G_AND\000"
1367 /* 1190 */ "G_ATOMICRMW_AND\000"
1368 /* 1206 */ "LIFETIME_END\000"
1369 /* 1219 */ "G_BRCOND\000"
1370 /* 1228 */ "G_ATOMICRMW_USUB_COND\000"
1371 /* 1250 */ "G_LLROUND\000"
1372 /* 1260 */ "G_LROUND\000"
1373 /* 1269 */ "G_INTRINSIC_ROUND\000"
1374 /* 1287 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1375 /* 1313 */ "LOAD_STACK_GUARD\000"
1376 /* 1330 */ "PSEUDO_PROBE\000"
1377 /* 1343 */ "G_SSUBE\000"
1378 /* 1351 */ "G_USUBE\000"
1379 /* 1359 */ "G_FENCE\000"
1380 /* 1367 */ "ARITH_FENCE\000"
1381 /* 1379 */ "REG_SEQUENCE\000"
1382 /* 1392 */ "G_SADDE\000"
1383 /* 1400 */ "G_UADDE\000"
1384 /* 1408 */ "G_GET_FPMODE\000"
1385 /* 1421 */ "G_RESET_FPMODE\000"
1386 /* 1436 */ "G_SET_FPMODE\000"
1387 /* 1449 */ "G_FMINNUM_IEEE\000"
1388 /* 1464 */ "G_FMAXNUM_IEEE\000"
1389 /* 1479 */ "G_VSCALE\000"
1390 /* 1488 */ "G_JUMP_TABLE\000"
1391 /* 1501 */ "BUNDLE\000"
1392 /* 1508 */ "G_MEMSET_INLINE\000"
1393 /* 1524 */ "G_MEMCPY_INLINE\000"
1394 /* 1540 */ "RELOC_NONE\000"
1395 /* 1551 */ "LOCAL_ESCAPE\000"
1396 /* 1564 */ "G_FPTRUNCSTORE\000"
1397 /* 1579 */ "G_STACKRESTORE\000"
1398 /* 1594 */ "G_INDEXED_STORE\000"
1399 /* 1610 */ "G_STORE\000"
1400 /* 1618 */ "G_BITREVERSE\000"
1401 /* 1631 */ "FAKE_USE\000"
1402 /* 1640 */ "DBG_VALUE\000"
1403 /* 1650 */ "G_GLOBAL_VALUE\000"
1404 /* 1665 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1405 /* 1688 */ "CONVERGENCECTRL_GLUE\000"
1406 /* 1709 */ "G_STACKSAVE\000"
1407 /* 1721 */ "G_MEMMOVE\000"
1408 /* 1731 */ "G_FREEZE\000"
1409 /* 1740 */ "G_FCANONICALIZE\000"
1410 /* 1756 */ "G_FMODF\000"
1411 /* 1764 */ "INIT_UNDEF\000"
1412 /* 1775 */ "G_IMPLICIT_DEF\000"
1413 /* 1790 */ "DBG_INSTR_REF\000"
1414 /* 1804 */ "G_FNEG\000"
1415 /* 1811 */ "EXTRACT_SUBREG\000"
1416 /* 1826 */ "INSERT_SUBREG\000"
1417 /* 1840 */ "G_SEXT_INREG\000"
1418 /* 1853 */ "SUBREG_TO_REG\000"
1419 /* 1867 */ "G_ATOMIC_CMPXCHG\000"
1420 /* 1884 */ "G_ATOMICRMW_XCHG\000"
1421 /* 1901 */ "G_GET_ROUNDING\000"
1422 /* 1916 */ "G_SET_ROUNDING\000"
1423 /* 1931 */ "G_FLOG\000"
1424 /* 1938 */ "G_VAARG\000"
1425 /* 1946 */ "PREALLOCATED_ARG\000"
1426 /* 1963 */ "G_PREFETCH\000"
1427 /* 1974 */ "G_SMULH\000"
1428 /* 1982 */ "G_UMULH\000"
1429 /* 1990 */ "G_FTANH\000"
1430 /* 1998 */ "G_FSINH\000"
1431 /* 2006 */ "G_FCOSH\000"
1432 /* 2014 */ "LDAWFI\000"
1433 /* 2021 */ "LDWFI\000"
1434 /* 2027 */ "STWFI\000"
1435 /* 2033 */ "DBG_PHI\000"
1436 /* 2041 */ "G_FPTOSI\000"
1437 /* 2050 */ "G_FPTOUI\000"
1438 /* 2059 */ "G_FPOWI\000"
1439 /* 2067 */ "COPY_LANEMASK\000"
1440 /* 2081 */ "G_PTRMASK\000"
1441 /* 2091 */ "GC_LABEL\000"
1442 /* 2100 */ "DBG_LABEL\000"
1443 /* 2110 */ "EH_LABEL\000"
1444 /* 2119 */ "ANNOTATION_LABEL\000"
1445 /* 2136 */ "ICALL_BRANCH_FUNNEL\000"
1446 /* 2156 */ "G_FSHL\000"
1447 /* 2163 */ "G_SHL\000"
1448 /* 2169 */ "G_FCEIL\000"
1449 /* 2177 */ "G_SAVGCEIL\000"
1450 /* 2188 */ "G_UAVGCEIL\000"
1451 /* 2199 */ "PATCHABLE_TAIL_CALL\000"
1452 /* 2219 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1453 /* 2246 */ "PATCHABLE_EVENT_CALL\000"
1454 /* 2267 */ "FENTRY_CALL\000"
1455 /* 2279 */ "KILL\000"
1456 /* 2284 */ "G_CONSTANT_POOL\000"
1457 /* 2300 */ "G_ROTL\000"
1458 /* 2307 */ "G_VECREDUCE_FMUL\000"
1459 /* 2324 */ "G_FMUL\000"
1460 /* 2331 */ "G_VECREDUCE_SEQ_FMUL\000"
1461 /* 2352 */ "G_STRICT_FMUL\000"
1462 /* 2366 */ "G_CLMUL\000"
1463 /* 2374 */ "G_VECREDUCE_MUL\000"
1464 /* 2390 */ "G_MUL\000"
1465 /* 2396 */ "G_FREM\000"
1466 /* 2403 */ "G_STRICT_FREM\000"
1467 /* 2417 */ "G_SREM\000"
1468 /* 2424 */ "G_UREM\000"
1469 /* 2431 */ "G_SDIVREM\000"
1470 /* 2441 */ "G_UDIVREM\000"
1471 /* 2451 */ "INLINEASM\000"
1472 /* 2461 */ "G_VECREDUCE_FMINIMUM\000"
1473 /* 2482 */ "G_FMINIMUM\000"
1474 /* 2493 */ "G_ATOMICRMW_FMINIMUM\000"
1475 /* 2514 */ "G_VECREDUCE_FMAXIMUM\000"
1476 /* 2535 */ "G_FMAXIMUM\000"
1477 /* 2546 */ "G_ATOMICRMW_FMAXIMUM\000"
1478 /* 2567 */ "G_VECREDUCE_FMINIMUMNUM\000"
1479 /* 2591 */ "G_FMINIMUMNUM\000"
1480 /* 2605 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1481 /* 2629 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1482 /* 2653 */ "G_FMAXIMUMNUM\000"
1483 /* 2667 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1484 /* 2691 */ "G_FMINNUM\000"
1485 /* 2701 */ "G_FMAXNUM\000"
1486 /* 2711 */ "G_FATAN\000"
1487 /* 2719 */ "G_FTAN\000"
1488 /* 2726 */ "G_INTRINSIC_ROUNDEVEN\000"
1489 /* 2748 */ "G_ASSERT_ALIGN\000"
1490 /* 2763 */ "G_FCOPYSIGN\000"
1491 /* 2775 */ "G_VECREDUCE_FMIN\000"
1492 /* 2792 */ "G_ATOMICRMW_FMIN\000"
1493 /* 2809 */ "G_VECREDUCE_SMIN\000"
1494 /* 2826 */ "G_SMIN\000"
1495 /* 2833 */ "G_VECREDUCE_UMIN\000"
1496 /* 2850 */ "G_UMIN\000"
1497 /* 2857 */ "G_ATOMICRMW_UMIN\000"
1498 /* 2874 */ "G_ATOMICRMW_MIN\000"
1499 /* 2890 */ "G_FASIN\000"
1500 /* 2898 */ "G_FSIN\000"
1501 /* 2905 */ "CFI_INSTRUCTION\000"
1502 /* 2921 */ "G_CTLZ_ZERO_POISON\000"
1503 /* 2940 */ "G_CTTZ_ZERO_POISON\000"
1504 /* 2959 */ "EH_RETURN\000"
1505 /* 2969 */ "ADJCALLSTACKDOWN\000"
1506 /* 2986 */ "G_SSUBO\000"
1507 /* 2994 */ "G_USUBO\000"
1508 /* 3002 */ "G_SADDO\000"
1509 /* 3010 */ "G_UADDO\000"
1510 /* 3018 */ "JUMP_TABLE_DEBUG_INFO\000"
1511 /* 3040 */ "G_SMULO\000"
1512 /* 3048 */ "G_UMULO\000"
1513 /* 3056 */ "G_BZERO\000"
1514 /* 3064 */ "STACKMAP\000"
1515 /* 3073 */ "G_DEBUGTRAP\000"
1516 /* 3085 */ "G_UBSANTRAP\000"
1517 /* 3097 */ "G_TRAP\000"
1518 /* 3104 */ "G_ATOMICRMW_UDEC_WRAP\000"
1519 /* 3126 */ "G_ATOMICRMW_UINC_WRAP\000"
1520 /* 3148 */ "G_BSWAP\000"
1521 /* 3156 */ "G_SITOFP\000"
1522 /* 3165 */ "G_UITOFP\000"
1523 /* 3174 */ "G_FCMP\000"
1524 /* 3181 */ "G_STRICT_FCMP\000"
1525 /* 3195 */ "G_ICMP\000"
1526 /* 3202 */ "G_SCMP\000"
1527 /* 3209 */ "G_UCMP\000"
1528 /* 3216 */ "CONVERGENCECTRL_LOOP\000"
1529 /* 3237 */ "G_CTPOP\000"
1530 /* 3245 */ "PATCHABLE_OP\000"
1531 /* 3258 */ "FAULTING_OP\000"
1532 /* 3270 */ "ADJCALLSTACKUP\000"
1533 /* 3285 */ "PREALLOCATED_SETUP\000"
1534 /* 3304 */ "G_FLDEXP\000"
1535 /* 3313 */ "G_STRICT_FLDEXP\000"
1536 /* 3329 */ "G_FEXP\000"
1537 /* 3336 */ "G_FFREXP\000"
1538 /* 3345 */ "LDSPC_0R\000"
1539 /* 3354 */ "STSPC_0R\000"
1540 /* 3363 */ "LDSED_0R\000"
1541 /* 3372 */ "STSED_0R\000"
1542 /* 3381 */ "GETED_0R\000"
1543 /* 3390 */ "GETID_0R\000"
1544 /* 3399 */ "CLRE_0R\000"
1545 /* 3407 */ "DCALL_0R\000"
1546 /* 3416 */ "GETKEP_0R\000"
1547 /* 3426 */ "SETKEP_0R\000"
1548 /* 3436 */ "GETKSP_0R\000"
1549 /* 3446 */ "DENTSP_0R\000"
1550 /* 3456 */ "DRESTSP_0R\000"
1551 /* 3467 */ "LDSSR_0R\000"
1552 /* 3476 */ "STSSR_0R\000"
1553 /* 3485 */ "LDET_0R\000"
1554 /* 3493 */ "FREET_0R\000"
1555 /* 3502 */ "DRET_0R\000"
1556 /* 3510 */ "KRET_0R\000"
1557 /* 3518 */ "GETET_0R\000"
1558 /* 3527 */ "STET_0R\000"
1559 /* 3535 */ "WAITEU_0R\000"
1560 /* 3545 */ "WAITEF_1R\000"
1561 /* 3555 */ "WAITET_1R\000"
1562 /* 3565 */ "CLRPT_1R\000"
1563 /* 3574 */ "TSTART_1R\000"
1564 /* 3584 */ "G_BR\000"
1565 /* 3589 */ "INLINEASM_BR\000"
1566 /* 3602 */ "G_BLOCK_ADDR\000"
1567 /* 3615 */ "MEMBARRIER\000"
1568 /* 3626 */ "G_CONSTANT_FOLD_BARRIER\000"
1569 /* 3650 */ "PATCHABLE_FUNCTION_ENTER\000"
1570 /* 3675 */ "G_READCYCLECOUNTER\000"
1571 /* 3694 */ "G_READSTEADYCOUNTER\000"
1572 /* 3714 */ "G_READ_REGISTER\000"
1573 /* 3730 */ "G_WRITE_REGISTER\000"
1574 /* 3747 */ "G_ASHR\000"
1575 /* 3754 */ "G_FSHR\000"
1576 /* 3761 */ "G_LSHR\000"
1577 /* 3768 */ "CONVERGENCECTRL_ANCHOR\000"
1578 /* 3791 */ "G_FFLOOR\000"
1579 /* 3800 */ "G_SAVGFLOOR\000"
1580 /* 3812 */ "G_UAVGFLOOR\000"
1581 /* 3824 */ "G_EXTRACT_SUBVECTOR\000"
1582 /* 3844 */ "G_INSERT_SUBVECTOR\000"
1583 /* 3863 */ "G_BUILD_VECTOR\000"
1584 /* 3878 */ "G_SHUFFLE_VECTOR\000"
1585 /* 3895 */ "G_STEP_VECTOR\000"
1586 /* 3909 */ "G_SPLAT_VECTOR\000"
1587 /* 3924 */ "G_VECREDUCE_XOR\000"
1588 /* 3940 */ "G_XOR\000"
1589 /* 3946 */ "G_ATOMICRMW_XOR\000"
1590 /* 3962 */ "G_VECREDUCE_OR\000"
1591 /* 3977 */ "G_OR\000"
1592 /* 3982 */ "G_ATOMICRMW_OR\000"
1593 /* 3997 */ "G_ROTR\000"
1594 /* 4004 */ "G_INTTOPTR\000"
1595 /* 4015 */ "G_FABS\000"
1596 /* 4022 */ "G_ABS\000"
1597 /* 4028 */ "G_ABDS\000"
1598 /* 4035 */ "G_UNMERGE_VALUES\000"
1599 /* 4052 */ "G_MERGE_VALUES\000"
1600 /* 4067 */ "G_CTLS\000"
1601 /* 4074 */ "G_FACOS\000"
1602 /* 4082 */ "G_FCOS\000"
1603 /* 4089 */ "G_FSINCOS\000"
1604 /* 4099 */ "G_STRICT_FCMPS\000"
1605 /* 4114 */ "G_CONCAT_VECTORS\000"
1606 /* 4131 */ "COPY_TO_REGCLASS\000"
1607 /* 4148 */ "G_IS_FPCLASS\000"
1608 /* 4161 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1609 /* 4191 */ "G_VECTOR_COMPRESS\000"
1610 /* 4209 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1611 /* 4236 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1612 /* 4274 */ "G_TRUNC_SSAT_S\000"
1613 /* 4289 */ "G_SSUBSAT\000"
1614 /* 4299 */ "G_USUBSAT\000"
1615 /* 4309 */ "G_SADDSAT\000"
1616 /* 4319 */ "G_UADDSAT\000"
1617 /* 4329 */ "G_SSHLSAT\000"
1618 /* 4339 */ "G_USHLSAT\000"
1619 /* 4349 */ "G_SMULFIXSAT\000"
1620 /* 4362 */ "G_UMULFIXSAT\000"
1621 /* 4375 */ "G_SDIVFIXSAT\000"
1622 /* 4388 */ "G_UDIVFIXSAT\000"
1623 /* 4401 */ "G_ATOMICRMW_USUB_SAT\000"
1624 /* 4422 */ "G_FPTOSI_SAT\000"
1625 /* 4435 */ "G_FPTOUI_SAT\000"
1626 /* 4448 */ "G_EXTRACT\000"
1627 /* 4458 */ "G_SELECT\000"
1628 /* 4467 */ "G_BRINDIRECT\000"
1629 /* 4480 */ "PATCHABLE_RET\000"
1630 /* 4494 */ "FRAME_TO_ARGS_OFFSET\000"
1631 /* 4515 */ "G_MEMSET\000"
1632 /* 4524 */ "PATCHABLE_FUNCTION_EXIT\000"
1633 /* 4548 */ "G_BRJT\000"
1634 /* 4555 */ "BR_JT\000"
1635 /* 4561 */ "G_EXTRACT_VECTOR_ELT\000"
1636 /* 4582 */ "G_INSERT_VECTOR_ELT\000"
1637 /* 4602 */ "G_FCONSTANT\000"
1638 /* 4614 */ "G_CONSTANT\000"
1639 /* 4625 */ "G_INTRINSIC_CONVERGENT\000"
1640 /* 4648 */ "STATEPOINT\000"
1641 /* 4659 */ "PATCHPOINT\000"
1642 /* 4670 */ "G_PTRTOINT\000"
1643 /* 4681 */ "G_FRINT\000"
1644 /* 4689 */ "G_INTRINSIC_LLRINT\000"
1645 /* 4708 */ "G_INTRINSIC_LRINT\000"
1646 /* 4726 */ "G_FNEARBYINT\000"
1647 /* 4739 */ "NOT\000"
1648 /* 4743 */ "G_VASTART\000"
1649 /* 4753 */ "LIFETIME_START\000"
1650 /* 4768 */ "G_INVOKE_REGION_START\000"
1651 /* 4790 */ "G_INSERT\000"
1652 /* 4799 */ "G_FSQRT\000"
1653 /* 4807 */ "G_STRICT_FSQRT\000"
1654 /* 4822 */ "G_BITCAST\000"
1655 /* 4832 */ "G_ADDRSPACE_CAST\000"
1656 /* 4849 */ "DBG_VALUE_LIST\000"
1657 /* 4864 */ "G_FPEXT\000"
1658 /* 4872 */ "G_SEXT\000"
1659 /* 4879 */ "G_ASSERT_SEXT\000"
1660 /* 4893 */ "G_ANYEXT\000"
1661 /* 4902 */ "G_ZEXT\000"
1662 /* 4909 */ "G_ASSERT_ZEXT\000"
1663 /* 4923 */ "G_ABDU\000"
1664 /* 4930 */ "G_TRUNC_SSAT_U\000"
1665 /* 4945 */ "G_TRUNC_USAT_U\000"
1666 /* 4960 */ "G_FDIV\000"
1667 /* 4967 */ "G_STRICT_FDIV\000"
1668 /* 4981 */ "G_SDIV\000"
1669 /* 4988 */ "G_UDIV\000"
1670 /* 4995 */ "G_GET_FPENV\000"
1671 /* 5007 */ "G_RESET_FPENV\000"
1672 /* 5021 */ "G_SET_FPENV\000"
1673 /* 5033 */ "G_FPOW\000"
1674 /* 5040 */ "G_VECREDUCE_FMAX\000"
1675 /* 5057 */ "G_ATOMICRMW_FMAX\000"
1676 /* 5074 */ "G_VECREDUCE_SMAX\000"
1677 /* 5091 */ "G_SMAX\000"
1678 /* 5098 */ "G_VECREDUCE_UMAX\000"
1679 /* 5115 */ "G_UMAX\000"
1680 /* 5122 */ "G_ATOMICRMW_UMAX\000"
1681 /* 5139 */ "G_ATOMICRMW_MAX\000"
1682 /* 5155 */ "G_FRAME_INDEX\000"
1683 /* 5169 */ "G_SBFX\000"
1684 /* 5176 */ "G_UBFX\000"
1685 /* 5183 */ "G_SMULFIX\000"
1686 /* 5193 */ "G_UMULFIX\000"
1687 /* 5203 */ "G_SDIVFIX\000"
1688 /* 5213 */ "G_UDIVFIX\000"
1689 /* 5223 */ "G_MEMCPY\000"
1690 /* 5232 */ "COPY\000"
1691 /* 5237 */ "CONVERGENCECTRL_ENTRY\000"
1692 /* 5259 */ "G_CTLZ\000"
1693 /* 5266 */ "G_CTTZ\000"
1694 /* 5273 */ "LDAPF_lu10_ba\000"
1695 /* 5287 */ "SSYNC_0r\000"
1696 /* 5296 */ "BLA_1r\000"
1697 /* 5303 */ "MSYNC_1r\000"
1698 /* 5312 */ "ECALLF_1r\000"
1699 /* 5322 */ "DGETREG_1r\000"
1700 /* 5333 */ "KCALL_1r\000"
1701 /* 5342 */ "MJOIN_1r\000"
1702 /* 5351 */ "SETCP_1r\000"
1703 /* 5360 */ "SETDP_1r\000"
1704 /* 5369 */ "SETSP_1r\000"
1705 /* 5378 */ "SYNCR_1r\000"
1706 /* 5387 */ "FREER_1r\000"
1707 /* 5396 */ "ECALLT_1r\000"
1708 /* 5406 */ "BAU_1r\000"
1709 /* 5413 */ "EDU_1r\000"
1710 /* 5420 */ "EEU_1r\000"
1711 /* 5427 */ "BRU_1r\000"
1712 /* 5434 */ "SETEV_1r\000"
1713 /* 5443 */ "SETV_1r\000"
1714 /* 5451 */ "INITPC_2r\000"
1715 /* 5461 */ "SETPSC_2r\000"
1716 /* 5471 */ "SETD_2r\000"
1717 /* 5479 */ "EEF_2r\000"
1718 /* 5486 */ "PEEK_2r\000"
1719 /* 5494 */ "MKMSK_2r\000"
1720 /* 5503 */ "ENDIN_2r\000"
1721 /* 5512 */ "INITCP_2r\000"
1722 /* 5522 */ "INITDP_2r\000"
1723 /* 5532 */ "INITSP_2r\000"
1724 /* 5542 */ "INSHR_2r\000"
1725 /* 5551 */ "OUTSHR_2r\000"
1726 /* 5561 */ "TSETMR_2r\000"
1727 /* 5571 */ "GETTS_2r\000"
1728 /* 5580 */ "CHKCT_2r\000"
1729 /* 5589 */ "INCT_2r\000"
1730 /* 5597 */ "TESTCT_2r\000"
1731 /* 5607 */ "OUTCT_2r\000"
1732 /* 5616 */ "TESTWCT_2r\000"
1733 /* 5627 */ "EET_2r\000"
1734 /* 5634 */ "INT_2r\000"
1735 /* 5641 */ "ANDNOT_2r\000"
1736 /* 5651 */ "SETPT_2r\000"
1737 /* 5660 */ "GETST_2r\000"
1738 /* 5669 */ "OUTT_2r\000"
1739 /* 5677 */ "OUT_2r\000"
1740 /* 5684 */ "SEXT_2r\000"
1741 /* 5692 */ "ZEXT_2r\000"
1742 /* 5700 */ "SETC_l2r\000"
1743 /* 5709 */ "GETD_l2r\000"
1744 /* 5718 */ "SETCLK_l2r\000"
1745 /* 5729 */ "TESTLCL_l2r\000"
1746 /* 5741 */ "GETN_l2r\000"
1747 /* 5750 */ "SETN_l2r\000"
1748 /* 5759 */ "INITLR_l2r\000"
1749 /* 5770 */ "GETPS_l2r\000"
1750 /* 5780 */ "SETPS_l2r\000"
1751 /* 5790 */ "BYTEREV_l2r\000"
1752 /* 5802 */ "BITREV_l2r\000"
1753 /* 5813 */ "SETTW_l2r\000"
1754 /* 5823 */ "SETRDY_l2r\000"
1755 /* 5834 */ "CLZ_l2r\000"
1756 /* 5842 */ "SUB_3r\000"
1757 /* 5849 */ "ADD_3r\000"
1758 /* 5856 */ "AND_3r\000"
1759 /* 5863 */ "SHL_3r\000"
1760 /* 5870 */ "EQ_3r\000"
1761 /* 5876 */ "SHR_3r\000"
1762 /* 5883 */ "OR_3r\000"
1763 /* 5889 */ "TSETR_3r\000"
1764 /* 5898 */ "LD16S_3r\000"
1765 /* 5907 */ "LSS_3r\000"
1766 /* 5914 */ "LD8U_3r\000"
1767 /* 5922 */ "LSU_3r\000"
1768 /* 5929 */ "LDW_3r\000"
1769 /* 5936 */ "ST16_l3r\000"
1770 /* 5945 */ "ST8_l3r\000"
1771 /* 5953 */ "LDA16B_l3r\000"
1772 /* 5964 */ "LDAWB_l3r\000"
1773 /* 5974 */ "CRC_l3r\000"
1774 /* 5982 */ "LDA16F_l3r\000"
1775 /* 5993 */ "LDAWF_l3r\000"
1776 /* 6003 */ "MUL_l3r\000"
1777 /* 6011 */ "ASHR_l3r\000"
1778 /* 6020 */ "XOR_l3r\000"
1779 /* 6028 */ "REMS_l3r\000"
1780 /* 6037 */ "DIVS_l3r\000"
1781 /* 6046 */ "REMU_l3r\000"
1782 /* 6055 */ "DIVU_l3r\000"
1783 /* 6064 */ "STW_l3r\000"
1784 /* 6072 */ "CRC8_l4r\000"
1785 /* 6081 */ "MACCS_l4r\000"
1786 /* 6091 */ "MACCU_l4r\000"
1787 /* 6101 */ "LSUB_l5r\000"
1788 /* 6110 */ "LADD_l5r\000"
1789 /* 6119 */ "LDIVU_l5r\000"
1790 /* 6129 */ "LMUL_l6r\000"
1791 /* 6138 */ "SUB_2rus\000"
1792 /* 6147 */ "ADD_2rus\000"
1793 /* 6156 */ "SHL_2rus\000"
1794 /* 6165 */ "EQ_2rus\000"
1795 /* 6173 */ "SHR_2rus\000"
1796 /* 6182 */ "LDW_2rus\000"
1797 /* 6191 */ "STW_2rus\000"
1798 /* 6200 */ "LDAWB_l2rus\000"
1799 /* 6212 */ "LDAWF_l2rus\000"
1800 /* 6224 */ "ASHR_l2rus\000"
1801 /* 6235 */ "INPW_l2rus\000"
1802 /* 6246 */ "OUTPW_l2rus\000"
1803 /* 6258 */ "MKMSK_rus\000"
1804 /* 6268 */ "GETR_rus\000"
1805 /* 6277 */ "CHKCT_rus\000"
1806 /* 6287 */ "OUTCT_rus\000"
1807 /* 6297 */ "SEXT_rus\000"
1808 /* 6306 */ "ZEXT_rus\000"
1809};
1810#ifdef __GNUC__
1811#pragma GCC diagnostic pop
1812#endif
1813
1814extern const unsigned XCoreInstrNameIndices[] = {
1815 2037U, 2451U, 3589U, 2905U, 2110U, 2091U, 2119U, 2279U,
1816 1811U, 1826U, 1777U, 1764U, 1853U, 4131U, 1640U, 4849U,
1817 1790U, 2033U, 2100U, 1379U, 5232U, 2067U, 1501U, 4753U,
1818 1206U, 1330U, 1367U, 3064U, 2267U, 4659U, 1313U, 3285U,
1819 1946U, 4648U, 1551U, 3258U, 3245U, 3650U, 4480U, 4524U,
1820 2199U, 2246U, 2219U, 2136U, 1631U, 3615U, 3018U, 1540U,
1821 5237U, 3768U, 3216U, 1688U, 4879U, 4909U, 2748U, 1119U,
1822 808U, 2390U, 4981U, 4988U, 2417U, 2424U, 2431U, 2441U,
1823 1184U, 3977U, 3940U, 4028U, 4923U, 3812U, 2188U, 3800U,
1824 2177U, 1775U, 2035U, 5155U, 1650U, 1665U, 2284U, 4448U,
1825 4035U, 4790U, 4052U, 3863U, 888U, 4114U, 4670U, 4004U,
1826 4822U, 1731U, 3626U, 1287U, 862U, 1269U, 4708U, 4689U,
1827 2726U, 3675U, 3694U, 1020U, 964U, 994U, 933U, 1005U,
1828 945U, 975U, 1610U, 1564U, 1594U, 4161U, 1867U, 1884U,
1829 1135U, 814U, 1190U, 1151U, 3982U, 3946U, 5139U, 2874U,
1830 5122U, 2857U, 1086U, 791U, 5057U, 2792U, 2546U, 2493U,
1831 2667U, 2605U, 3126U, 3104U, 1228U, 4401U, 1359U, 1963U,
1832 1219U, 4467U, 4768U, 840U, 4209U, 4625U, 4236U, 4893U,
1833 880U, 4274U, 4930U, 4945U, 4614U, 4602U, 4743U, 1938U,
1834 4872U, 1840U, 4902U, 2163U, 3761U, 3747U, 2156U, 3754U,
1835 3997U, 2300U, 3195U, 3174U, 3202U, 3209U, 4458U, 3010U,
1836 1400U, 2994U, 1351U, 3002U, 1392U, 2986U, 1343U, 3048U,
1837 3040U, 1982U, 1974U, 4319U, 4309U, 4299U, 4289U, 4339U,
1838 4329U, 5183U, 5193U, 4349U, 4362U, 5203U, 5213U, 4375U,
1839 4388U, 1044U, 770U, 2324U, 751U, 926U, 4960U, 2396U,
1840 1756U, 5033U, 2059U, 3329U, 165U, 9U, 1931U, 148U,
1841 0U, 3304U, 3336U, 1804U, 4864U, 852U, 2041U, 2050U,
1842 3156U, 3165U, 4422U, 4435U, 4015U, 2763U, 4148U, 1740U,
1843 2691U, 2701U, 1449U, 1464U, 2482U, 2535U, 2591U, 2653U,
1844 4995U, 5021U, 5007U, 1408U, 1436U, 1421U, 1901U, 1916U,
1845 1125U, 2081U, 2826U, 5091U, 2850U, 5115U, 4022U, 1260U,
1846 1250U, 3584U, 4548U, 1479U, 3844U, 3824U, 4582U, 4561U,
1847 3878U, 3909U, 3895U, 4191U, 5266U, 2940U, 5259U, 2921U,
1848 4067U, 3237U, 3148U, 1618U, 2366U, 2169U, 4082U, 2898U,
1849 4089U, 2719U, 4074U, 2890U, 2711U, 156U, 2006U, 1998U,
1850 1990U, 4799U, 3791U, 4681U, 4726U, 4832U, 3602U, 1488U,
1851 909U, 1709U, 1579U, 1072U, 777U, 2352U, 4967U, 2403U,
1852 757U, 4807U, 3313U, 3181U, 4099U, 3714U, 3730U, 5223U,
1853 1524U, 1721U, 4515U, 3056U, 1508U, 3097U, 3073U, 3085U,
1854 1051U, 2331U, 1027U, 2307U, 5040U, 2775U, 2514U, 2461U,
1855 2629U, 2567U, 1103U, 2374U, 1168U, 3962U, 3924U, 5074U,
1856 2809U, 5098U, 2833U, 5169U, 5176U, 2969U, 3270U, 4555U,
1857 140U, 2959U, 4494U, 2014U, 2021U, 830U, 2027U, 6147U,
1858 5849U, 5641U, 5856U, 6224U, 6011U, 5406U, 5802U, 118U,
1859 56U, 427U, 267U, 5296U, 87U, 28U, 108U, 47U,
1860 632U, 505U, 731U, 595U, 436U, 275U, 642U, 514U,
1861 741U, 604U, 445U, 283U, 5427U, 5790U, 5580U, 6277U,
1862 3399U, 3565U, 454U, 291U, 397U, 240U, 5834U, 6072U,
1863 5974U, 3407U, 3446U, 5322U, 6037U, 6055U, 3456U, 3502U,
1864 5312U, 5396U, 5413U, 5479U, 5627U, 5420U, 5503U, 365U,
1865 211U, 6165U, 5870U, 344U, 192U, 387U, 231U, 5387U,
1866 3493U, 5709U, 3381U, 3518U, 3390U, 3416U, 3436U, 5741U,
1867 5770U, 6268U, 407U, 249U, 5660U, 5571U, 5589U, 5512U,
1868 5522U, 5759U, 5451U, 5532U, 6235U, 5542U, 5634U, 5506U,
1869 5333U, 323U, 173U, 364U, 210U, 375U, 220U, 3510U,
1870 6110U, 5898U, 5914U, 5953U, 5982U, 76U, 18U, 97U,
1871 5273U, 37U, 6200U, 5964U, 333U, 182U, 663U, 533U,
1872 6212U, 5993U, 697U, 564U, 613U, 488U, 3485U, 6119U,
1873 3363U, 3345U, 3467U, 652U, 129U, 523U, 66U, 675U,
1874 544U, 709U, 575U, 6182U, 5929U, 6129U, 5907U, 6101U,
1875 5922U, 6081U, 6091U, 5342U, 5494U, 6258U, 5303U, 6003U,
1876 1807U, 4739U, 5883U, 5607U, 6287U, 6246U, 5551U, 5669U,
1877 5677U, 5486U, 6028U, 6046U, 354U, 201U, 5718U, 5351U,
1878 5700U, 622U, 496U, 5360U, 5471U, 5434U, 3426U, 5750U,
1879 5461U, 5780U, 5651U, 5823U, 5369U, 471U, 307U, 417U,
1880 258U, 5813U, 5443U, 5684U, 6297U, 6156U, 5863U, 6173U,
1881 5876U, 5287U, 5936U, 5945U, 3527U, 3372U, 3354U, 3476U,
1882 686U, 554U, 720U, 585U, 6191U, 6064U, 6138U, 5842U,
1883 5378U, 5597U, 5729U, 5616U, 5561U, 5889U, 3574U, 3545U,
1884 3555U, 3535U, 6020U, 5692U, 6306U,
1885};
1886
1887static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1888 II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 557, nullptr, 0);
1889}
1890
1891
1892} // namespace llvm
1893
1894#endif // GET_INSTRINFO_MC_DESC
1895
1896#ifdef GET_INSTRINFO_HEADER
1897#undef GET_INSTRINFO_HEADER
1898
1899namespace llvm {
1900
1901struct XCoreGenInstrInfo : public TargetInstrInfo {
1902 explicit XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1903 ~XCoreGenInstrInfo() override = default;
1904};
1905
1906} // namespace llvm
1907
1908namespace llvm::XCore {
1909
1910
1911} // namespace llvm::XCore
1912
1913#endif // GET_INSTRINFO_HEADER
1914
1915#ifdef GET_INSTRINFO_HELPER_DECLS
1916#undef GET_INSTRINFO_HELPER_DECLS
1917
1918
1919#endif // GET_INSTRINFO_HELPER_DECLS
1920
1921#ifdef GET_INSTRINFO_HELPERS
1922#undef GET_INSTRINFO_HELPERS
1923
1924
1925#endif // GET_INSTRINFO_HELPERS
1926
1927#ifdef GET_INSTRINFO_CTOR_DTOR
1928#undef GET_INSTRINFO_CTOR_DTOR
1929
1930namespace llvm {
1931
1932extern const XCoreInstrTable XCoreDescs;
1933extern const unsigned XCoreInstrNameIndices[];
1934extern const char XCoreInstrNameData[];
1935XCoreGenInstrInfo::XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1936 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1937 InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 557);
1938}
1939
1940} // namespace llvm
1941
1942#endif // GET_INSTRINFO_CTOR_DTOR
1943
1944#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1945#undef GET_INSTRINFO_MC_HELPER_DECLS
1946
1947namespace llvm {
1948
1949class MCInst;
1950class FeatureBitset;
1951
1952namespace XCore_MC {
1953
1954void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1955
1956} // namespace XCore_MC
1957
1958} // namespace llvm
1959
1960#endif // GET_INSTRINFO_MC_HELPER_DECLS
1961
1962#ifdef GET_INSTRINFO_MC_HELPERS
1963#undef GET_INSTRINFO_MC_HELPERS
1964
1965namespace llvm::XCore_MC {
1966
1967
1968} // namespace llvm::XCore_MC
1969
1970#endif // GET_INSTRINFO_MC_HELPERS
1971
1972#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1973 defined(GET_AVAILABLE_OPCODE_CHECKER)
1974#define GET_COMPUTE_FEATURES
1975#endif
1976#ifdef GET_COMPUTE_FEATURES
1977#undef GET_COMPUTE_FEATURES
1978
1979namespace llvm::XCore_MC {
1980
1981// Bits for subtarget features that participate in instruction matching.
1982enum SubtargetFeatureBits : uint8_t {
1983};
1984
1985inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1986 FeatureBitset Features;
1987 return Features;
1988}
1989
1990inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1991 enum : uint8_t {
1992 CEFBS_None,
1993 };
1994
1995 static constexpr FeatureBitset FeatureBitsets[] = {
1996 {}, // CEFBS_None
1997 };
1998 static constexpr uint8_t RequiredFeaturesRefs[] = {
1999 CEFBS_None, // PHI
2000 CEFBS_None, // INLINEASM
2001 CEFBS_None, // INLINEASM_BR
2002 CEFBS_None, // CFI_INSTRUCTION
2003 CEFBS_None, // EH_LABEL
2004 CEFBS_None, // GC_LABEL
2005 CEFBS_None, // ANNOTATION_LABEL
2006 CEFBS_None, // KILL
2007 CEFBS_None, // EXTRACT_SUBREG
2008 CEFBS_None, // INSERT_SUBREG
2009 CEFBS_None, // IMPLICIT_DEF
2010 CEFBS_None, // INIT_UNDEF
2011 CEFBS_None, // SUBREG_TO_REG
2012 CEFBS_None, // COPY_TO_REGCLASS
2013 CEFBS_None, // DBG_VALUE
2014 CEFBS_None, // DBG_VALUE_LIST
2015 CEFBS_None, // DBG_INSTR_REF
2016 CEFBS_None, // DBG_PHI
2017 CEFBS_None, // DBG_LABEL
2018 CEFBS_None, // REG_SEQUENCE
2019 CEFBS_None, // COPY
2020 CEFBS_None, // COPY_LANEMASK
2021 CEFBS_None, // BUNDLE
2022 CEFBS_None, // LIFETIME_START
2023 CEFBS_None, // LIFETIME_END
2024 CEFBS_None, // PSEUDO_PROBE
2025 CEFBS_None, // ARITH_FENCE
2026 CEFBS_None, // STACKMAP
2027 CEFBS_None, // FENTRY_CALL
2028 CEFBS_None, // PATCHPOINT
2029 CEFBS_None, // LOAD_STACK_GUARD
2030 CEFBS_None, // PREALLOCATED_SETUP
2031 CEFBS_None, // PREALLOCATED_ARG
2032 CEFBS_None, // STATEPOINT
2033 CEFBS_None, // LOCAL_ESCAPE
2034 CEFBS_None, // FAULTING_OP
2035 CEFBS_None, // PATCHABLE_OP
2036 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2037 CEFBS_None, // PATCHABLE_RET
2038 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2039 CEFBS_None, // PATCHABLE_TAIL_CALL
2040 CEFBS_None, // PATCHABLE_EVENT_CALL
2041 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2042 CEFBS_None, // ICALL_BRANCH_FUNNEL
2043 CEFBS_None, // FAKE_USE
2044 CEFBS_None, // MEMBARRIER
2045 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2046 CEFBS_None, // RELOC_NONE
2047 CEFBS_None, // CONVERGENCECTRL_ENTRY
2048 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2049 CEFBS_None, // CONVERGENCECTRL_LOOP
2050 CEFBS_None, // CONVERGENCECTRL_GLUE
2051 CEFBS_None, // G_ASSERT_SEXT
2052 CEFBS_None, // G_ASSERT_ZEXT
2053 CEFBS_None, // G_ASSERT_ALIGN
2054 CEFBS_None, // G_ADD
2055 CEFBS_None, // G_SUB
2056 CEFBS_None, // G_MUL
2057 CEFBS_None, // G_SDIV
2058 CEFBS_None, // G_UDIV
2059 CEFBS_None, // G_SREM
2060 CEFBS_None, // G_UREM
2061 CEFBS_None, // G_SDIVREM
2062 CEFBS_None, // G_UDIVREM
2063 CEFBS_None, // G_AND
2064 CEFBS_None, // G_OR
2065 CEFBS_None, // G_XOR
2066 CEFBS_None, // G_ABDS
2067 CEFBS_None, // G_ABDU
2068 CEFBS_None, // G_UAVGFLOOR
2069 CEFBS_None, // G_UAVGCEIL
2070 CEFBS_None, // G_SAVGFLOOR
2071 CEFBS_None, // G_SAVGCEIL
2072 CEFBS_None, // G_IMPLICIT_DEF
2073 CEFBS_None, // G_PHI
2074 CEFBS_None, // G_FRAME_INDEX
2075 CEFBS_None, // G_GLOBAL_VALUE
2076 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2077 CEFBS_None, // G_CONSTANT_POOL
2078 CEFBS_None, // G_EXTRACT
2079 CEFBS_None, // G_UNMERGE_VALUES
2080 CEFBS_None, // G_INSERT
2081 CEFBS_None, // G_MERGE_VALUES
2082 CEFBS_None, // G_BUILD_VECTOR
2083 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2084 CEFBS_None, // G_CONCAT_VECTORS
2085 CEFBS_None, // G_PTRTOINT
2086 CEFBS_None, // G_INTTOPTR
2087 CEFBS_None, // G_BITCAST
2088 CEFBS_None, // G_FREEZE
2089 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2090 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2091 CEFBS_None, // G_INTRINSIC_TRUNC
2092 CEFBS_None, // G_INTRINSIC_ROUND
2093 CEFBS_None, // G_INTRINSIC_LRINT
2094 CEFBS_None, // G_INTRINSIC_LLRINT
2095 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2096 CEFBS_None, // G_READCYCLECOUNTER
2097 CEFBS_None, // G_READSTEADYCOUNTER
2098 CEFBS_None, // G_LOAD
2099 CEFBS_None, // G_SEXTLOAD
2100 CEFBS_None, // G_ZEXTLOAD
2101 CEFBS_None, // G_FPEXTLOAD
2102 CEFBS_None, // G_INDEXED_LOAD
2103 CEFBS_None, // G_INDEXED_SEXTLOAD
2104 CEFBS_None, // G_INDEXED_ZEXTLOAD
2105 CEFBS_None, // G_STORE
2106 CEFBS_None, // G_FPTRUNCSTORE
2107 CEFBS_None, // G_INDEXED_STORE
2108 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2109 CEFBS_None, // G_ATOMIC_CMPXCHG
2110 CEFBS_None, // G_ATOMICRMW_XCHG
2111 CEFBS_None, // G_ATOMICRMW_ADD
2112 CEFBS_None, // G_ATOMICRMW_SUB
2113 CEFBS_None, // G_ATOMICRMW_AND
2114 CEFBS_None, // G_ATOMICRMW_NAND
2115 CEFBS_None, // G_ATOMICRMW_OR
2116 CEFBS_None, // G_ATOMICRMW_XOR
2117 CEFBS_None, // G_ATOMICRMW_MAX
2118 CEFBS_None, // G_ATOMICRMW_MIN
2119 CEFBS_None, // G_ATOMICRMW_UMAX
2120 CEFBS_None, // G_ATOMICRMW_UMIN
2121 CEFBS_None, // G_ATOMICRMW_FADD
2122 CEFBS_None, // G_ATOMICRMW_FSUB
2123 CEFBS_None, // G_ATOMICRMW_FMAX
2124 CEFBS_None, // G_ATOMICRMW_FMIN
2125 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2126 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2127 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2128 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2129 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2130 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2131 CEFBS_None, // G_ATOMICRMW_USUB_COND
2132 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2133 CEFBS_None, // G_FENCE
2134 CEFBS_None, // G_PREFETCH
2135 CEFBS_None, // G_BRCOND
2136 CEFBS_None, // G_BRINDIRECT
2137 CEFBS_None, // G_INVOKE_REGION_START
2138 CEFBS_None, // G_INTRINSIC
2139 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2140 CEFBS_None, // G_INTRINSIC_CONVERGENT
2141 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2142 CEFBS_None, // G_ANYEXT
2143 CEFBS_None, // G_TRUNC
2144 CEFBS_None, // G_TRUNC_SSAT_S
2145 CEFBS_None, // G_TRUNC_SSAT_U
2146 CEFBS_None, // G_TRUNC_USAT_U
2147 CEFBS_None, // G_CONSTANT
2148 CEFBS_None, // G_FCONSTANT
2149 CEFBS_None, // G_VASTART
2150 CEFBS_None, // G_VAARG
2151 CEFBS_None, // G_SEXT
2152 CEFBS_None, // G_SEXT_INREG
2153 CEFBS_None, // G_ZEXT
2154 CEFBS_None, // G_SHL
2155 CEFBS_None, // G_LSHR
2156 CEFBS_None, // G_ASHR
2157 CEFBS_None, // G_FSHL
2158 CEFBS_None, // G_FSHR
2159 CEFBS_None, // G_ROTR
2160 CEFBS_None, // G_ROTL
2161 CEFBS_None, // G_ICMP
2162 CEFBS_None, // G_FCMP
2163 CEFBS_None, // G_SCMP
2164 CEFBS_None, // G_UCMP
2165 CEFBS_None, // G_SELECT
2166 CEFBS_None, // G_UADDO
2167 CEFBS_None, // G_UADDE
2168 CEFBS_None, // G_USUBO
2169 CEFBS_None, // G_USUBE
2170 CEFBS_None, // G_SADDO
2171 CEFBS_None, // G_SADDE
2172 CEFBS_None, // G_SSUBO
2173 CEFBS_None, // G_SSUBE
2174 CEFBS_None, // G_UMULO
2175 CEFBS_None, // G_SMULO
2176 CEFBS_None, // G_UMULH
2177 CEFBS_None, // G_SMULH
2178 CEFBS_None, // G_UADDSAT
2179 CEFBS_None, // G_SADDSAT
2180 CEFBS_None, // G_USUBSAT
2181 CEFBS_None, // G_SSUBSAT
2182 CEFBS_None, // G_USHLSAT
2183 CEFBS_None, // G_SSHLSAT
2184 CEFBS_None, // G_SMULFIX
2185 CEFBS_None, // G_UMULFIX
2186 CEFBS_None, // G_SMULFIXSAT
2187 CEFBS_None, // G_UMULFIXSAT
2188 CEFBS_None, // G_SDIVFIX
2189 CEFBS_None, // G_UDIVFIX
2190 CEFBS_None, // G_SDIVFIXSAT
2191 CEFBS_None, // G_UDIVFIXSAT
2192 CEFBS_None, // G_FADD
2193 CEFBS_None, // G_FSUB
2194 CEFBS_None, // G_FMUL
2195 CEFBS_None, // G_FMA
2196 CEFBS_None, // G_FMAD
2197 CEFBS_None, // G_FDIV
2198 CEFBS_None, // G_FREM
2199 CEFBS_None, // G_FMODF
2200 CEFBS_None, // G_FPOW
2201 CEFBS_None, // G_FPOWI
2202 CEFBS_None, // G_FEXP
2203 CEFBS_None, // G_FEXP2
2204 CEFBS_None, // G_FEXP10
2205 CEFBS_None, // G_FLOG
2206 CEFBS_None, // G_FLOG2
2207 CEFBS_None, // G_FLOG10
2208 CEFBS_None, // G_FLDEXP
2209 CEFBS_None, // G_FFREXP
2210 CEFBS_None, // G_FNEG
2211 CEFBS_None, // G_FPEXT
2212 CEFBS_None, // G_FPTRUNC
2213 CEFBS_None, // G_FPTOSI
2214 CEFBS_None, // G_FPTOUI
2215 CEFBS_None, // G_SITOFP
2216 CEFBS_None, // G_UITOFP
2217 CEFBS_None, // G_FPTOSI_SAT
2218 CEFBS_None, // G_FPTOUI_SAT
2219 CEFBS_None, // G_FABS
2220 CEFBS_None, // G_FCOPYSIGN
2221 CEFBS_None, // G_IS_FPCLASS
2222 CEFBS_None, // G_FCANONICALIZE
2223 CEFBS_None, // G_FMINNUM
2224 CEFBS_None, // G_FMAXNUM
2225 CEFBS_None, // G_FMINNUM_IEEE
2226 CEFBS_None, // G_FMAXNUM_IEEE
2227 CEFBS_None, // G_FMINIMUM
2228 CEFBS_None, // G_FMAXIMUM
2229 CEFBS_None, // G_FMINIMUMNUM
2230 CEFBS_None, // G_FMAXIMUMNUM
2231 CEFBS_None, // G_GET_FPENV
2232 CEFBS_None, // G_SET_FPENV
2233 CEFBS_None, // G_RESET_FPENV
2234 CEFBS_None, // G_GET_FPMODE
2235 CEFBS_None, // G_SET_FPMODE
2236 CEFBS_None, // G_RESET_FPMODE
2237 CEFBS_None, // G_GET_ROUNDING
2238 CEFBS_None, // G_SET_ROUNDING
2239 CEFBS_None, // G_PTR_ADD
2240 CEFBS_None, // G_PTRMASK
2241 CEFBS_None, // G_SMIN
2242 CEFBS_None, // G_SMAX
2243 CEFBS_None, // G_UMIN
2244 CEFBS_None, // G_UMAX
2245 CEFBS_None, // G_ABS
2246 CEFBS_None, // G_LROUND
2247 CEFBS_None, // G_LLROUND
2248 CEFBS_None, // G_BR
2249 CEFBS_None, // G_BRJT
2250 CEFBS_None, // G_VSCALE
2251 CEFBS_None, // G_INSERT_SUBVECTOR
2252 CEFBS_None, // G_EXTRACT_SUBVECTOR
2253 CEFBS_None, // G_INSERT_VECTOR_ELT
2254 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2255 CEFBS_None, // G_SHUFFLE_VECTOR
2256 CEFBS_None, // G_SPLAT_VECTOR
2257 CEFBS_None, // G_STEP_VECTOR
2258 CEFBS_None, // G_VECTOR_COMPRESS
2259 CEFBS_None, // G_CTTZ
2260 CEFBS_None, // G_CTTZ_ZERO_POISON
2261 CEFBS_None, // G_CTLZ
2262 CEFBS_None, // G_CTLZ_ZERO_POISON
2263 CEFBS_None, // G_CTLS
2264 CEFBS_None, // G_CTPOP
2265 CEFBS_None, // G_BSWAP
2266 CEFBS_None, // G_BITREVERSE
2267 CEFBS_None, // G_CLMUL
2268 CEFBS_None, // G_FCEIL
2269 CEFBS_None, // G_FCOS
2270 CEFBS_None, // G_FSIN
2271 CEFBS_None, // G_FSINCOS
2272 CEFBS_None, // G_FTAN
2273 CEFBS_None, // G_FACOS
2274 CEFBS_None, // G_FASIN
2275 CEFBS_None, // G_FATAN
2276 CEFBS_None, // G_FATAN2
2277 CEFBS_None, // G_FCOSH
2278 CEFBS_None, // G_FSINH
2279 CEFBS_None, // G_FTANH
2280 CEFBS_None, // G_FSQRT
2281 CEFBS_None, // G_FFLOOR
2282 CEFBS_None, // G_FRINT
2283 CEFBS_None, // G_FNEARBYINT
2284 CEFBS_None, // G_ADDRSPACE_CAST
2285 CEFBS_None, // G_BLOCK_ADDR
2286 CEFBS_None, // G_JUMP_TABLE
2287 CEFBS_None, // G_DYN_STACKALLOC
2288 CEFBS_None, // G_STACKSAVE
2289 CEFBS_None, // G_STACKRESTORE
2290 CEFBS_None, // G_STRICT_FADD
2291 CEFBS_None, // G_STRICT_FSUB
2292 CEFBS_None, // G_STRICT_FMUL
2293 CEFBS_None, // G_STRICT_FDIV
2294 CEFBS_None, // G_STRICT_FREM
2295 CEFBS_None, // G_STRICT_FMA
2296 CEFBS_None, // G_STRICT_FSQRT
2297 CEFBS_None, // G_STRICT_FLDEXP
2298 CEFBS_None, // G_STRICT_FCMP
2299 CEFBS_None, // G_STRICT_FCMPS
2300 CEFBS_None, // G_READ_REGISTER
2301 CEFBS_None, // G_WRITE_REGISTER
2302 CEFBS_None, // G_MEMCPY
2303 CEFBS_None, // G_MEMCPY_INLINE
2304 CEFBS_None, // G_MEMMOVE
2305 CEFBS_None, // G_MEMSET
2306 CEFBS_None, // G_BZERO
2307 CEFBS_None, // G_MEMSET_INLINE
2308 CEFBS_None, // G_TRAP
2309 CEFBS_None, // G_DEBUGTRAP
2310 CEFBS_None, // G_UBSANTRAP
2311 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2312 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2313 CEFBS_None, // G_VECREDUCE_FADD
2314 CEFBS_None, // G_VECREDUCE_FMUL
2315 CEFBS_None, // G_VECREDUCE_FMAX
2316 CEFBS_None, // G_VECREDUCE_FMIN
2317 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2318 CEFBS_None, // G_VECREDUCE_FMINIMUM
2319 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2320 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2321 CEFBS_None, // G_VECREDUCE_ADD
2322 CEFBS_None, // G_VECREDUCE_MUL
2323 CEFBS_None, // G_VECREDUCE_AND
2324 CEFBS_None, // G_VECREDUCE_OR
2325 CEFBS_None, // G_VECREDUCE_XOR
2326 CEFBS_None, // G_VECREDUCE_SMAX
2327 CEFBS_None, // G_VECREDUCE_SMIN
2328 CEFBS_None, // G_VECREDUCE_UMAX
2329 CEFBS_None, // G_VECREDUCE_UMIN
2330 CEFBS_None, // G_SBFX
2331 CEFBS_None, // G_UBFX
2332 CEFBS_None, // ADJCALLSTACKDOWN
2333 CEFBS_None, // ADJCALLSTACKUP
2334 CEFBS_None, // BR_JT
2335 CEFBS_None, // BR_JT32
2336 CEFBS_None, // EH_RETURN
2337 CEFBS_None, // FRAME_TO_ARGS_OFFSET
2338 CEFBS_None, // LDAWFI
2339 CEFBS_None, // LDWFI
2340 CEFBS_None, // SELECT_CC
2341 CEFBS_None, // STWFI
2342 CEFBS_None, // ADD_2rus
2343 CEFBS_None, // ADD_3r
2344 CEFBS_None, // ANDNOT_2r
2345 CEFBS_None, // AND_3r
2346 CEFBS_None, // ASHR_l2rus
2347 CEFBS_None, // ASHR_l3r
2348 CEFBS_None, // BAU_1r
2349 CEFBS_None, // BITREV_l2r
2350 CEFBS_None, // BLACP_lu10
2351 CEFBS_None, // BLACP_u10
2352 CEFBS_None, // BLAT_lu6
2353 CEFBS_None, // BLAT_u6
2354 CEFBS_None, // BLA_1r
2355 CEFBS_None, // BLRB_lu10
2356 CEFBS_None, // BLRB_u10
2357 CEFBS_None, // BLRF_lu10
2358 CEFBS_None, // BLRF_u10
2359 CEFBS_None, // BRBF_lru6
2360 CEFBS_None, // BRBF_ru6
2361 CEFBS_None, // BRBT_lru6
2362 CEFBS_None, // BRBT_ru6
2363 CEFBS_None, // BRBU_lu6
2364 CEFBS_None, // BRBU_u6
2365 CEFBS_None, // BRFF_lru6
2366 CEFBS_None, // BRFF_ru6
2367 CEFBS_None, // BRFT_lru6
2368 CEFBS_None, // BRFT_ru6
2369 CEFBS_None, // BRFU_lu6
2370 CEFBS_None, // BRFU_u6
2371 CEFBS_None, // BRU_1r
2372 CEFBS_None, // BYTEREV_l2r
2373 CEFBS_None, // CHKCT_2r
2374 CEFBS_None, // CHKCT_rus
2375 CEFBS_None, // CLRE_0R
2376 CEFBS_None, // CLRPT_1R
2377 CEFBS_None, // CLRSR_branch_lu6
2378 CEFBS_None, // CLRSR_branch_u6
2379 CEFBS_None, // CLRSR_lu6
2380 CEFBS_None, // CLRSR_u6
2381 CEFBS_None, // CLZ_l2r
2382 CEFBS_None, // CRC8_l4r
2383 CEFBS_None, // CRC_l3r
2384 CEFBS_None, // DCALL_0R
2385 CEFBS_None, // DENTSP_0R
2386 CEFBS_None, // DGETREG_1r
2387 CEFBS_None, // DIVS_l3r
2388 CEFBS_None, // DIVU_l3r
2389 CEFBS_None, // DRESTSP_0R
2390 CEFBS_None, // DRET_0R
2391 CEFBS_None, // ECALLF_1r
2392 CEFBS_None, // ECALLT_1r
2393 CEFBS_None, // EDU_1r
2394 CEFBS_None, // EEF_2r
2395 CEFBS_None, // EET_2r
2396 CEFBS_None, // EEU_1r
2397 CEFBS_None, // ENDIN_2r
2398 CEFBS_None, // ENTSP_lu6
2399 CEFBS_None, // ENTSP_u6
2400 CEFBS_None, // EQ_2rus
2401 CEFBS_None, // EQ_3r
2402 CEFBS_None, // EXTDP_lu6
2403 CEFBS_None, // EXTDP_u6
2404 CEFBS_None, // EXTSP_lu6
2405 CEFBS_None, // EXTSP_u6
2406 CEFBS_None, // FREER_1r
2407 CEFBS_None, // FREET_0R
2408 CEFBS_None, // GETD_l2r
2409 CEFBS_None, // GETED_0R
2410 CEFBS_None, // GETET_0R
2411 CEFBS_None, // GETID_0R
2412 CEFBS_None, // GETKEP_0R
2413 CEFBS_None, // GETKSP_0R
2414 CEFBS_None, // GETN_l2r
2415 CEFBS_None, // GETPS_l2r
2416 CEFBS_None, // GETR_rus
2417 CEFBS_None, // GETSR_lu6
2418 CEFBS_None, // GETSR_u6
2419 CEFBS_None, // GETST_2r
2420 CEFBS_None, // GETTS_2r
2421 CEFBS_None, // INCT_2r
2422 CEFBS_None, // INITCP_2r
2423 CEFBS_None, // INITDP_2r
2424 CEFBS_None, // INITLR_l2r
2425 CEFBS_None, // INITPC_2r
2426 CEFBS_None, // INITSP_2r
2427 CEFBS_None, // INPW_l2rus
2428 CEFBS_None, // INSHR_2r
2429 CEFBS_None, // INT_2r
2430 CEFBS_None, // IN_2r
2431 CEFBS_None, // KCALL_1r
2432 CEFBS_None, // KCALL_lu6
2433 CEFBS_None, // KCALL_u6
2434 CEFBS_None, // KENTSP_lu6
2435 CEFBS_None, // KENTSP_u6
2436 CEFBS_None, // KRESTSP_lu6
2437 CEFBS_None, // KRESTSP_u6
2438 CEFBS_None, // KRET_0R
2439 CEFBS_None, // LADD_l5r
2440 CEFBS_None, // LD16S_3r
2441 CEFBS_None, // LD8U_3r
2442 CEFBS_None, // LDA16B_l3r
2443 CEFBS_None, // LDA16F_l3r
2444 CEFBS_None, // LDAPB_lu10
2445 CEFBS_None, // LDAPB_u10
2446 CEFBS_None, // LDAPF_lu10
2447 CEFBS_None, // LDAPF_lu10_ba
2448 CEFBS_None, // LDAPF_u10
2449 CEFBS_None, // LDAWB_l2rus
2450 CEFBS_None, // LDAWB_l3r
2451 CEFBS_None, // LDAWCP_lu6
2452 CEFBS_None, // LDAWCP_u6
2453 CEFBS_None, // LDAWDP_lru6
2454 CEFBS_None, // LDAWDP_ru6
2455 CEFBS_None, // LDAWF_l2rus
2456 CEFBS_None, // LDAWF_l3r
2457 CEFBS_None, // LDAWSP_lru6
2458 CEFBS_None, // LDAWSP_ru6
2459 CEFBS_None, // LDC_lru6
2460 CEFBS_None, // LDC_ru6
2461 CEFBS_None, // LDET_0R
2462 CEFBS_None, // LDIVU_l5r
2463 CEFBS_None, // LDSED_0R
2464 CEFBS_None, // LDSPC_0R
2465 CEFBS_None, // LDSSR_0R
2466 CEFBS_None, // LDWCP_lru6
2467 CEFBS_None, // LDWCP_lu10
2468 CEFBS_None, // LDWCP_ru6
2469 CEFBS_None, // LDWCP_u10
2470 CEFBS_None, // LDWDP_lru6
2471 CEFBS_None, // LDWDP_ru6
2472 CEFBS_None, // LDWSP_lru6
2473 CEFBS_None, // LDWSP_ru6
2474 CEFBS_None, // LDW_2rus
2475 CEFBS_None, // LDW_3r
2476 CEFBS_None, // LMUL_l6r
2477 CEFBS_None, // LSS_3r
2478 CEFBS_None, // LSUB_l5r
2479 CEFBS_None, // LSU_3r
2480 CEFBS_None, // MACCS_l4r
2481 CEFBS_None, // MACCU_l4r
2482 CEFBS_None, // MJOIN_1r
2483 CEFBS_None, // MKMSK_2r
2484 CEFBS_None, // MKMSK_rus
2485 CEFBS_None, // MSYNC_1r
2486 CEFBS_None, // MUL_l3r
2487 CEFBS_None, // NEG
2488 CEFBS_None, // NOT
2489 CEFBS_None, // OR_3r
2490 CEFBS_None, // OUTCT_2r
2491 CEFBS_None, // OUTCT_rus
2492 CEFBS_None, // OUTPW_l2rus
2493 CEFBS_None, // OUTSHR_2r
2494 CEFBS_None, // OUTT_2r
2495 CEFBS_None, // OUT_2r
2496 CEFBS_None, // PEEK_2r
2497 CEFBS_None, // REMS_l3r
2498 CEFBS_None, // REMU_l3r
2499 CEFBS_None, // RETSP_lu6
2500 CEFBS_None, // RETSP_u6
2501 CEFBS_None, // SETCLK_l2r
2502 CEFBS_None, // SETCP_1r
2503 CEFBS_None, // SETC_l2r
2504 CEFBS_None, // SETC_lru6
2505 CEFBS_None, // SETC_ru6
2506 CEFBS_None, // SETDP_1r
2507 CEFBS_None, // SETD_2r
2508 CEFBS_None, // SETEV_1r
2509 CEFBS_None, // SETKEP_0R
2510 CEFBS_None, // SETN_l2r
2511 CEFBS_None, // SETPSC_2r
2512 CEFBS_None, // SETPS_l2r
2513 CEFBS_None, // SETPT_2r
2514 CEFBS_None, // SETRDY_l2r
2515 CEFBS_None, // SETSP_1r
2516 CEFBS_None, // SETSR_branch_lu6
2517 CEFBS_None, // SETSR_branch_u6
2518 CEFBS_None, // SETSR_lu6
2519 CEFBS_None, // SETSR_u6
2520 CEFBS_None, // SETTW_l2r
2521 CEFBS_None, // SETV_1r
2522 CEFBS_None, // SEXT_2r
2523 CEFBS_None, // SEXT_rus
2524 CEFBS_None, // SHL_2rus
2525 CEFBS_None, // SHL_3r
2526 CEFBS_None, // SHR_2rus
2527 CEFBS_None, // SHR_3r
2528 CEFBS_None, // SSYNC_0r
2529 CEFBS_None, // ST16_l3r
2530 CEFBS_None, // ST8_l3r
2531 CEFBS_None, // STET_0R
2532 CEFBS_None, // STSED_0R
2533 CEFBS_None, // STSPC_0R
2534 CEFBS_None, // STSSR_0R
2535 CEFBS_None, // STWDP_lru6
2536 CEFBS_None, // STWDP_ru6
2537 CEFBS_None, // STWSP_lru6
2538 CEFBS_None, // STWSP_ru6
2539 CEFBS_None, // STW_2rus
2540 CEFBS_None, // STW_l3r
2541 CEFBS_None, // SUB_2rus
2542 CEFBS_None, // SUB_3r
2543 CEFBS_None, // SYNCR_1r
2544 CEFBS_None, // TESTCT_2r
2545 CEFBS_None, // TESTLCL_l2r
2546 CEFBS_None, // TESTWCT_2r
2547 CEFBS_None, // TSETMR_2r
2548 CEFBS_None, // TSETR_3r
2549 CEFBS_None, // TSTART_1R
2550 CEFBS_None, // WAITEF_1R
2551 CEFBS_None, // WAITET_1R
2552 CEFBS_None, // WAITEU_0R
2553 CEFBS_None, // XOR_l3r
2554 CEFBS_None, // ZEXT_2r
2555 CEFBS_None, // ZEXT_rus
2556 };
2557
2558 assert(Opcode < 557);
2559 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2560}
2561
2562
2563} // namespace llvm::XCore_MC
2564
2565#endif // GET_COMPUTE_FEATURES
2566
2567#ifdef GET_AVAILABLE_OPCODE_CHECKER
2568#undef GET_AVAILABLE_OPCODE_CHECKER
2569
2570namespace llvm::XCore_MC {
2571
2572bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2573 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2574 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2575 FeatureBitset MissingFeatures =
2576 (AvailableFeatures & RequiredFeatures) ^
2577 RequiredFeatures;
2578 return !MissingFeatures.any();
2579}
2580
2581} // namespace llvm::XCore_MC
2582
2583#endif // GET_AVAILABLE_OPCODE_CHECKER
2584
2585#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2586#undef ENABLE_INSTR_PREDICATE_VERIFIER
2587
2588#include <sstream>
2589
2590namespace llvm::XCore_MC {
2591
2592#ifndef NDEBUG
2593static const char *SubtargetFeatureNames[] = {
2594 nullptr
2595};
2596
2597#endif // NDEBUG
2598
2599void verifyInstructionPredicates(
2600 unsigned Opcode, const FeatureBitset &Features) {
2601#ifndef NDEBUG
2602 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2603 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2604 FeatureBitset MissingFeatures =
2605 (AvailableFeatures & RequiredFeatures) ^
2606 RequiredFeatures;
2607 if (MissingFeatures.any()) {
2608 std::ostringstream Msg;
2609 Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
2610 << " instruction but the ";
2611 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2612 if (MissingFeatures.test(i))
2613 Msg << SubtargetFeatureNames[i] << " ";
2614 Msg << "predicate(s) are not met";
2615 report_fatal_error(Msg.str().c_str());
2616 }
2617#endif // NDEBUG
2618}
2619
2620} // namespace llvm::XCore_MC
2621
2622#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2623
2624