1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::XCore {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1540
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553
96 G_INSERT = 81, // GenericOpcodes.td:1562
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1572
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340
114 G_LOAD = 99, // GenericOpcodes.td:1367
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1376
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1384
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1393
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420
121 G_STORE = 106, // GenericOpcodes.td:1428
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1446
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502
149 G_FENCE = 134, // GenericOpcodes.td:1518
150 G_PREFETCH = 135, // GenericOpcodes.td:1525
151 G_BRCOND = 136, // GenericOpcodes.td:1665
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1674
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697
154 G_INTRINSIC = 139, // GenericOpcodes.td:1617
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:619
183 G_UADDE = 168, // GenericOpcodes.td:627
184 G_USUBO = 169, // GenericOpcodes.td:649
185 G_USUBE = 170, // GenericOpcodes.td:655
186 G_SADDO = 171, // GenericOpcodes.td:634
187 G_SADDE = 172, // GenericOpcodes.td:642
188 G_SSUBO = 173, // GenericOpcodes.td:662
189 G_SSUBE = 174, // GenericOpcodes.td:669
190 G_UMULO = 175, // GenericOpcodes.td:676
191 G_SMULO = 176, // GenericOpcodes.td:684
192 G_UMULH = 177, // GenericOpcodes.td:693
193 G_SMULH = 178, // GenericOpcodes.td:702
194 G_UADDSAT = 179, // GenericOpcodes.td:714
195 G_SADDSAT = 180, // GenericOpcodes.td:722
196 G_USUBSAT = 181, // GenericOpcodes.td:730
197 G_SSUBSAT = 182, // GenericOpcodes.td:738
198 G_USHLSAT = 183, // GenericOpcodes.td:746
199 G_SSHLSAT = 184, // GenericOpcodes.td:754
200 G_SMULFIX = 185, // GenericOpcodes.td:766
201 G_UMULFIX = 186, // GenericOpcodes.td:773
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:783
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:790
204 G_SDIVFIX = 189, // GenericOpcodes.td:801
205 G_UDIVFIX = 190, // GenericOpcodes.td:808
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:818
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:825
208 G_FADD = 193, // GenericOpcodes.td:998
209 G_FSUB = 194, // GenericOpcodes.td:1006
210 G_FMUL = 195, // GenericOpcodes.td:1014
211 G_FMA = 196, // GenericOpcodes.td:1023
212 G_FMAD = 197, // GenericOpcodes.td:1032
213 G_FDIV = 198, // GenericOpcodes.td:1040
214 G_FREM = 199, // GenericOpcodes.td:1047
215 G_FMODF = 200, // GenericOpcodes.td:1054
216 G_FPOW = 201, // GenericOpcodes.td:1061
217 G_FPOWI = 202, // GenericOpcodes.td:1068
218 G_FEXP = 203, // GenericOpcodes.td:1075
219 G_FEXP2 = 204, // GenericOpcodes.td:1082
220 G_FEXP10 = 205, // GenericOpcodes.td:1089
221 G_FLOG = 206, // GenericOpcodes.td:1096
222 G_FLOG2 = 207, // GenericOpcodes.td:1103
223 G_FLOG10 = 208, // GenericOpcodes.td:1110
224 G_FLDEXP = 209, // GenericOpcodes.td:1117
225 G_FFREXP = 210, // GenericOpcodes.td:1124
226 G_FNEG = 211, // GenericOpcodes.td:836
227 G_FPEXT = 212, // GenericOpcodes.td:842
228 G_FPTRUNC = 213, // GenericOpcodes.td:848
229 G_FPTOSI = 214, // GenericOpcodes.td:854
230 G_FPTOUI = 215, // GenericOpcodes.td:860
231 G_SITOFP = 216, // GenericOpcodes.td:866
232 G_UITOFP = 217, // GenericOpcodes.td:872
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:878
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:884
235 G_FABS = 220, // GenericOpcodes.td:890
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:896
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:909
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:902
239 G_FMINNUM = 224, // GenericOpcodes.td:922
240 G_FMAXNUM = 225, // GenericOpcodes.td:929
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954
243 G_FMINIMUM = 228, // GenericOpcodes.td:964
244 G_FMAXIMUM = 229, // GenericOpcodes.td:971
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:979
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986
247 G_GET_FPENV = 232, // GenericOpcodes.td:1254
248 G_SET_FPENV = 233, // GenericOpcodes.td:1261
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1268
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1275
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1282
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1289
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1346
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1352
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1655
265 G_BRJT = 250, // GenericOpcodes.td:1685
266 G_VSCALE = 251, // GenericOpcodes.td:1583
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1780
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_CLMULR = 270, // GenericOpcodes.td:606
286 G_FCEIL = 271, // GenericOpcodes.td:1131
287 G_FCOS = 272, // GenericOpcodes.td:1138
288 G_FSIN = 273, // GenericOpcodes.td:1145
289 G_FSINCOS = 274, // GenericOpcodes.td:1152
290 G_FTAN = 275, // GenericOpcodes.td:1159
291 G_FACOS = 276, // GenericOpcodes.td:1166
292 G_FASIN = 277, // GenericOpcodes.td:1173
293 G_FATAN = 278, // GenericOpcodes.td:1180
294 G_FATAN2 = 279, // GenericOpcodes.td:1187
295 G_FCOSH = 280, // GenericOpcodes.td:1194
296 G_FSINH = 281, // GenericOpcodes.td:1201
297 G_FTANH = 282, // GenericOpcodes.td:1208
298 G_FSQRT = 283, // GenericOpcodes.td:1218
299 G_FFLOOR = 284, // GenericOpcodes.td:1225
300 G_FRINT = 285, // GenericOpcodes.td:1232
301 G_FNEARBYINT = 286, // GenericOpcodes.td:1239
302 G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248
303 G_BLOCK_ADDR = 288, // GenericOpcodes.td:254
304 G_JUMP_TABLE = 289, // GenericOpcodes.td:260
305 G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266
306 G_STACKSAVE = 291, // GenericOpcodes.td:272
307 G_STACKRESTORE = 292, // GenericOpcodes.td:278
308 G_STRICT_FADD = 293, // GenericOpcodes.td:1839
309 G_STRICT_FSUB = 294, // GenericOpcodes.td:1840
310 G_STRICT_FMUL = 295, // GenericOpcodes.td:1841
311 G_STRICT_FDIV = 296, // GenericOpcodes.td:1842
312 G_STRICT_FREM = 297, // GenericOpcodes.td:1843
313 G_STRICT_FMA = 298, // GenericOpcodes.td:1844
314 G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845
315 G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846
316 G_STRICT_FCMP = 301, // GenericOpcodes.td:1847
317 G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848
318 G_READ_REGISTER = 303, // GenericOpcodes.td:1704
319 G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714
320 G_MEMCPY = 305, // GenericOpcodes.td:1854
321 G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862
322 G_MEMMOVE = 307, // GenericOpcodes.td:1870
323 G_MEMSET = 308, // GenericOpcodes.td:1878
324 G_BZERO = 309, // GenericOpcodes.td:1885
325 G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892
326 G_TRAP = 311, // GenericOpcodes.td:1902
327 G_DEBUGTRAP = 312, // GenericOpcodes.td:1909
328 G_UBSANTRAP = 313, // GenericOpcodes.td:1915
329 G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803
330 G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809
331 G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815
332 G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816
333 G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818
334 G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819
335 G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820
336 G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821
337 G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822
338 G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823
339 G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825
340 G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826
341 G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827
342 G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828
343 G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829
344 G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830
345 G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831
346 G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832
347 G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833
348 G_SBFX = 333, // GenericOpcodes.td:1927
349 G_UBFX = 334, // GenericOpcodes.td:1935
350 ADJCALLSTACKDOWN = 335, // XCoreInstrInfo.td:356
351 ADJCALLSTACKUP = 336, // XCoreInstrInfo.td:359
352 BR_JT = 337, // XCoreInstrInfo.td:991
353 BR_JT32 = 338, // XCoreInstrInfo.td:996
354 EH_RETURN = 339, // XCoreInstrInfo.td:370
355 FRAME_TO_ARGS_OFFSET = 340, // XCoreInstrInfo.td:365
356 LDAWFI = 341, // XCoreInstrInfo.td:378
357 LDWFI = 342, // XCoreInstrInfo.td:374
358 SELECT_CC = 343, // XCoreInstrInfo.td:389
359 STWFI = 344, // XCoreInstrInfo.td:382
360 ADD_2rus = 345, // XCoreInstrInfo.td:247
361 ADD_3r = 346, // XCoreInstrInfo.td:244
362 ANDNOT_2r = 347, // XCoreInstrInfo.td:797
363 AND_3r = 348, // XCoreInstrInfo.td:408
364 ASHR_l2rus = 349, // XCoreInstrInfo.td:296
365 ASHR_l3r = 350, // XCoreInstrInfo.td:293
366 BAU_1r = 351, // XCoreInstrInfo.td:986
367 BITREV_l2r = 352, // XCoreInstrInfo.td:925
368 BLACP_lu10 = 353, // XCoreInstrInfo.td:746
369 BLACP_u10 = 354, // XCoreInstrInfo.td:744
370 BLAT_lu6 = 355, // XCoreInstrInfo.td:340
371 BLAT_u6 = 356, // XCoreInstrInfo.td:339
372 BLA_1r = 357, // XCoreInstrInfo.td:1025
373 BLRB_lu10 = 358, // XCoreInstrInfo.td:756
374 BLRB_u10 = 359, // XCoreInstrInfo.td:754
375 BLRF_lu10 = 360, // XCoreInstrInfo.td:751
376 BLRF_u10 = 361, // XCoreInstrInfo.td:748
377 BRBF_lru6 = 362, // XCoreInstrInfo.td:318
378 BRBF_ru6 = 363, // XCoreInstrInfo.td:316
379 BRBT_lru6 = 364, // XCoreInstrInfo.td:318
380 BRBT_ru6 = 365, // XCoreInstrInfo.td:316
381 BRBU_lu6 = 366, // XCoreInstrInfo.td:679
382 BRBU_u6 = 367, // XCoreInstrInfo.td:677
383 BRFF_lru6 = 368, // XCoreInstrInfo.td:311
384 BRFF_ru6 = 369, // XCoreInstrInfo.td:309
385 BRFT_lru6 = 370, // XCoreInstrInfo.td:311
386 BRFT_ru6 = 371, // XCoreInstrInfo.td:309
387 BRFU_lu6 = 372, // XCoreInstrInfo.td:683
388 BRFU_u6 = 373, // XCoreInstrInfo.td:681
389 BRU_1r = 374, // XCoreInstrInfo.td:1001
390 BYTEREV_l2r = 375, // XCoreInstrInfo.td:929
391 CHKCT_2r = 376, // XCoreInstrInfo.td:863
392 CHKCT_rus = 377, // XCoreInstrInfo.td:867
393 CLRE_0R = 378, // XCoreInstrInfo.td:1070
394 CLRPT_1R = 379, // XCoreInstrInfo.td:1065
395 CLRSR_branch_lu6 = 380, // XCoreInstrInfo.td:340
396 CLRSR_branch_u6 = 381, // XCoreInstrInfo.td:339
397 CLRSR_lu6 = 382, // XCoreInstrInfo.td:334
398 CLRSR_u6 = 383, // XCoreInstrInfo.td:332
399 CLZ_l2r = 384, // XCoreInstrInfo.td:933
400 CRC8_l4r = 385, // XCoreInstrInfo.td:533
401 CRC_l3r = 386, // XCoreInstrInfo.td:494
402 DCALL_0R = 387, // XCoreInstrInfo.td:1072
403 DENTSP_0R = 388, // XCoreInstrInfo.td:1075
404 DGETREG_1r = 389, // XCoreInstrInfo.td:1048
405 DIVS_l3r = 390, // XCoreInstrInfo.td:485
406 DIVU_l3r = 391, // XCoreInstrInfo.td:486
407 DRESTSP_0R = 392, // XCoreInstrInfo.td:1078
408 DRET_0R = 393, // XCoreInstrInfo.td:1080
409 ECALLF_1r = 394, // XCoreInstrInfo.td:1018
410 ECALLT_1r = 395, // XCoreInstrInfo.td:1013
411 EDU_1r = 396, // XCoreInstrInfo.td:1050
412 EEF_2r = 397, // XCoreInstrInfo.td:915
413 EET_2r = 398, // XCoreInstrInfo.td:918
414 EEU_1r = 399, // XCoreInstrInfo.td:1053
415 ENDIN_2r = 400, // XCoreInstrInfo.td:911
416 ENTSP_lu6 = 401, // XCoreInstrInfo.td:340
417 ENTSP_u6 = 402, // XCoreInstrInfo.td:339
418 EQ_2rus = 403, // XCoreInstrInfo.td:255
419 EQ_3r = 404, // XCoreInstrInfo.td:253
420 EXTDP_lu6 = 405, // XCoreInstrInfo.td:340
421 EXTDP_u6 = 406, // XCoreInstrInfo.td:339
422 EXTSP_lu6 = 407, // XCoreInstrInfo.td:340
423 EXTSP_u6 = 408, // XCoreInstrInfo.td:339
424 FREER_1r = 409, // XCoreInstrInfo.td:1034
425 FREET_0R = 410, // XCoreInstrInfo.td:1082
426 GETD_l2r = 411, // XCoreInstrInfo.td:937
427 GETED_0R = 412, // XCoreInstrInfo.td:1089
428 GETET_0R = 413, // XCoreInstrInfo.td:1093
429 GETID_0R = 414, // XCoreInstrInfo.td:1085
430 GETKEP_0R = 415, // XCoreInstrInfo.td:1097
431 GETKSP_0R = 416, // XCoreInstrInfo.td:1100
432 GETN_l2r = 417, // XCoreInstrInfo.td:940
433 GETPS_l2r = 418, // XCoreInstrInfo.td:951
434 GETR_rus = 419, // XCoreInstrInfo.td:811
435 GETSR_lu6 = 420, // XCoreInstrInfo.td:340
436 GETSR_u6 = 421, // XCoreInstrInfo.td:339
437 GETST_2r = 422, // XCoreInstrInfo.td:887
438 GETTS_2r = 423, // XCoreInstrInfo.td:815
439 INCT_2r = 424, // XCoreInstrInfo.td:845
440 INITCP_2r = 425, // XCoreInstrInfo.td:899
441 INITDP_2r = 426, // XCoreInstrInfo.td:903
442 INITLR_l2r = 427, // XCoreInstrInfo.td:959
443 INITPC_2r = 428, // XCoreInstrInfo.td:895
444 INITSP_2r = 429, // XCoreInstrInfo.td:891
445 INPW_l2rus = 430, // XCoreInstrInfo.td:511
446 INSHR_2r = 431, // XCoreInstrInfo.td:858
447 INT_2r = 432, // XCoreInstrInfo.td:849
448 IN_2r = 433, // XCoreInstrInfo.td:853
449 KCALL_1r = 434, // XCoreInstrInfo.td:1057
450 KCALL_lu6 = 435, // XCoreInstrInfo.td:340
451 KCALL_u6 = 436, // XCoreInstrInfo.td:339
452 KENTSP_lu6 = 437, // XCoreInstrInfo.td:340
453 KENTSP_u6 = 438, // XCoreInstrInfo.td:339
454 KRESTSP_lu6 = 439, // XCoreInstrInfo.td:340
455 KRESTSP_u6 = 440, // XCoreInstrInfo.td:339
456 KRET_0R = 441, // XCoreInstrInfo.td:1105
457 LADD_l5r = 442, // XCoreInstrInfo.td:541
458 LD16S_3r = 443, // XCoreInstrInfo.td:420
459 LD8U_3r = 444, // XCoreInstrInfo.td:424
460 LDA16B_l3r = 445, // XCoreInstrInfo.td:476
461 LDA16F_l3r = 446, // XCoreInstrInfo.td:470
462 LDAPB_lu10 = 447, // XCoreInstrInfo.td:732
463 LDAPB_u10 = 448, // XCoreInstrInfo.td:728
464 LDAPF_lu10 = 449, // XCoreInstrInfo.td:724
465 LDAPF_lu10_ba = 450, // XCoreInstrInfo.td:737
466 LDAPF_u10 = 451, // XCoreInstrInfo.td:722
467 LDAWB_l2rus = 452, // XCoreInstrInfo.td:466
468 LDAWB_l3r = 453, // XCoreInstrInfo.td:459
469 LDAWCP_lu6 = 454, // XCoreInstrInfo.td:692
470 LDAWCP_u6 = 455, // XCoreInstrInfo.td:688
471 LDAWDP_lru6 = 456, // XCoreInstrInfo.td:574
472 LDAWDP_ru6 = 457, // XCoreInstrInfo.td:570
473 LDAWF_l2rus = 458, // XCoreInstrInfo.td:455
474 LDAWF_l3r = 459, // XCoreInstrInfo.td:448
475 LDAWSP_lru6 = 460, // XCoreInstrInfo.td:628
476 LDAWSP_ru6 = 461, // XCoreInstrInfo.td:625
477 LDC_lru6 = 462, // XCoreInstrInfo.td:637
478 LDC_ru6 = 463, // XCoreInstrInfo.td:634
479 LDET_0R = 464, // XCoreInstrInfo.td:1108
480 LDIVU_l5r = 465, // XCoreInstrInfo.td:553
481 LDSED_0R = 466, // XCoreInstrInfo.td:1110
482 LDSPC_0R = 467, // XCoreInstrInfo.td:1112
483 LDSSR_0R = 468, // XCoreInstrInfo.td:1114
484 LDWCP_lru6 = 469, // XCoreInstrInfo.td:598
485 LDWCP_lu10 = 470, // XCoreInstrInfo.td:763
486 LDWCP_ru6 = 471, // XCoreInstrInfo.td:596
487 LDWCP_u10 = 472, // XCoreInstrInfo.td:761
488 LDWDP_lru6 = 473, // XCoreInstrInfo.td:582
489 LDWDP_ru6 = 474, // XCoreInstrInfo.td:579
490 LDWSP_lru6 = 475, // XCoreInstrInfo.td:619
491 LDWSP_ru6 = 476, // XCoreInstrInfo.td:615
492 LDW_2rus = 477, // XCoreInstrInfo.td:416
493 LDW_3r = 478, // XCoreInstrInfo.td:412
494 LMUL_l6r = 479, // XCoreInstrInfo.td:559
495 LSS_3r = 480, // XCoreInstrInfo.td:405
496 LSUB_l5r = 481, // XCoreInstrInfo.td:547
497 LSU_3r = 482, // XCoreInstrInfo.td:406
498 MACCS_l4r = 483, // XCoreInstrInfo.td:526
499 MACCU_l4r = 484, // XCoreInstrInfo.td:521
500 MJOIN_1r = 485, // XCoreInstrInfo.td:981
501 MKMSK_2r = 486, // XCoreInstrInfo.td:807
502 MKMSK_rus = 487, // XCoreInstrInfo.td:804
503 MSYNC_1r = 488, // XCoreInstrInfo.td:978
504 MUL_l3r = 489, // XCoreInstrInfo.td:482
505 NEG = 490, // XCoreInstrInfo.td:771
506 NOT = 491, // XCoreInstrInfo.td:768
507 OR_3r = 492, // XCoreInstrInfo.td:409
508 OUTCT_2r = 493, // XCoreInstrInfo.td:823
509 OUTCT_rus = 494, // XCoreInstrInfo.td:827
510 OUTPW_l2rus = 495, // XCoreInstrInfo.td:515
511 OUTSHR_2r = 496, // XCoreInstrInfo.td:840
512 OUTT_2r = 497, // XCoreInstrInfo.td:831
513 OUT_2r = 498, // XCoreInstrInfo.td:835
514 PEEK_2r = 499, // XCoreInstrInfo.td:907
515 REMS_l3r = 500, // XCoreInstrInfo.td:487
516 REMU_l3r = 501, // XCoreInstrInfo.td:488
517 RETSP_lu6 = 502, // XCoreInstrInfo.td:327
518 RETSP_u6 = 503, // XCoreInstrInfo.td:325
519 SETCLK_l2r = 504, // XCoreInstrInfo.td:963
520 SETCP_1r = 505, // XCoreInstrInfo.td:1010
521 SETC_l2r = 506, // XCoreInstrInfo.td:943
522 SETC_lru6 = 507, // XCoreInstrInfo.td:645
523 SETC_ru6 = 508, // XCoreInstrInfo.td:641
524 SETDP_1r = 509, // XCoreInstrInfo.td:1007
525 SETD_2r = 510, // XCoreInstrInfo.td:879
526 SETEV_1r = 511, // XCoreInstrInfo.td:1043
527 SETKEP_0R = 512, // XCoreInstrInfo.td:1118
528 SETN_l2r = 513, // XCoreInstrInfo.td:967
529 SETPSC_2r = 514, // XCoreInstrInfo.td:883
530 SETPS_l2r = 515, // XCoreInstrInfo.td:955
531 SETPT_2r = 516, // XCoreInstrInfo.td:819
532 SETRDY_l2r = 517, // XCoreInstrInfo.td:970
533 SETSP_1r = 518, // XCoreInstrInfo.td:1004
534 SETSR_branch_lu6 = 519, // XCoreInstrInfo.td:340
535 SETSR_branch_u6 = 520, // XCoreInstrInfo.td:339
536 SETSR_lu6 = 521, // XCoreInstrInfo.td:334
537 SETSR_u6 = 522, // XCoreInstrInfo.td:332
538 SETTW_l2r = 523, // XCoreInstrInfo.td:947
539 SETV_1r = 524, // XCoreInstrInfo.td:1039
540 SEXT_2r = 525, // XCoreInstrInfo.td:781
541 SEXT_rus = 526, // XCoreInstrInfo.td:775
542 SHL_2rus = 527, // XCoreInstrInfo.td:264
543 SHL_3r = 528, // XCoreInstrInfo.td:261
544 SHR_2rus = 529, // XCoreInstrInfo.td:264
545 SHR_3r = 530, // XCoreInstrInfo.td:261
546 SSYNC_0r = 531, // XCoreInstrInfo.td:1120
547 ST16_l3r = 532, // XCoreInstrInfo.td:502
548 ST8_l3r = 533, // XCoreInstrInfo.td:506
549 STET_0R = 534, // XCoreInstrInfo.td:1125
550 STSED_0R = 535, // XCoreInstrInfo.td:1127
551 STSPC_0R = 536, // XCoreInstrInfo.td:1129
552 STSSR_0R = 537, // XCoreInstrInfo.td:1131
553 STWDP_lru6 = 538, // XCoreInstrInfo.td:590
554 STWDP_ru6 = 539, // XCoreInstrInfo.td:587
555 STWSP_lru6 = 540, // XCoreInstrInfo.td:609
556 STWSP_ru6 = 541, // XCoreInstrInfo.td:605
557 STW_2rus = 542, // XCoreInstrInfo.td:434
558 STW_l3r = 543, // XCoreInstrInfo.td:430
559 SUB_2rus = 544, // XCoreInstrInfo.td:247
560 SUB_3r = 545, // XCoreInstrInfo.td:244
561 SYNCR_1r = 546, // XCoreInstrInfo.td:1030
562 TESTCT_2r = 547, // XCoreInstrInfo.td:871
563 TESTLCL_l2r = 548, // XCoreInstrInfo.td:974
564 TESTWCT_2r = 549, // XCoreInstrInfo.td:875
565 TSETMR_2r = 550, // XCoreInstrInfo.td:921
566 TSETR_3r = 551, // XCoreInstrInfo.td:444
567 TSTART_1R = 552, // XCoreInstrInfo.td:1063
568 WAITEF_1R = 553, // XCoreInstrInfo.td:1059
569 WAITET_1R = 554, // XCoreInstrInfo.td:1061
570 WAITEU_0R = 555, // XCoreInstrInfo.td:1136
571 XOR_l3r = 556, // XCoreInstrInfo.td:490
572 ZEXT_2r = 557, // XCoreInstrInfo.td:792
573 ZEXT_rus = 558, // XCoreInstrInfo.td:786
574 INSTRUCTION_LIST_END = 559
575 };
576
577} // namespace llvm::XCore
578
579#endif // GET_INSTRINFO_ENUM
580
581#ifdef GET_INSTRINFO_SCHED_ENUM
582#undef GET_INSTRINFO_SCHED_ENUM
583
584namespace llvm::XCore::Sched {
585
586 enum {
587 NoInstrModel = 0,
588 SCHED_LIST_END = 1
589 };
590
591} // namespace llvm::XCore::Sched
592
593#endif // GET_INSTRINFO_SCHED_ENUM
594
595#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
596
597namespace llvm {
598
599struct XCoreInstrTable {
600 MCInstrDesc Insts[559];
601 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
602 MCPhysReg ImplicitOps[11];
603 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
604 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
605 MCOperandInfo OperandInfo[209];
606};
607} // namespace llvm
608
609#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
610
611#ifdef GET_INSTRINFO_MC_DESC
612#undef GET_INSTRINFO_MC_DESC
613
614namespace llvm {
615
616static_assert((sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
617static constexpr unsigned XCoreOpInfoBase = (sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) / sizeof(MCOperandInfo);
618
619extern const XCoreInstrTable XCoreDescs = {
620 {
621 { 558, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_rus
622 { 557, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_2r
623 { 556, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_l3r
624 { 555, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEU_0R
625 { 554, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITET_1R
626 { 553, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEF_1R
627 { 552, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSTART_1R
628 { 551, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETR_3r
629 { 550, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETMR_2r
630 { 549, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTWCT_2r
631 { 548, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTLCL_l2r
632 { 547, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTCT_2r
633 { 546, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SYNCR_1r
634 { 545, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_3r
635 { 544, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_2rus
636 { 543, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_l3r
637 { 542, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_2rus
638 { 541, 2, 0, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_ru6
639 { 540, 2, 0, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_lru6
640 { 539, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_ru6
641 { 538, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_lru6
642 { 537, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSSR_0R
643 { 536, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSPC_0R
644 { 535, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSED_0R
645 { 534, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STET_0R
646 { 533, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST8_l3r
647 { 532, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST16_l3r
648 { 531, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SSYNC_0r
649 { 530, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_3r
650 { 529, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_2rus
651 { 528, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_3r
652 { 527, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_2rus
653 { 526, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_rus
654 { 525, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_2r
655 { 524, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETV_1r
656 { 523, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETTW_l2r
657 { 522, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_u6
658 { 521, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_lu6
659 { 520, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_u6
660 { 519, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_lu6
661 { 518, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 28, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSP_1r
662 { 517, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETRDY_l2r
663 { 516, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPT_2r
664 { 515, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPS_l2r
665 { 514, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPSC_2r
666 { 513, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETN_l2r
667 { 512, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETKEP_0R
668 { 511, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETEV_1r
669 { 510, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETD_2r
670 { 509, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETDP_1r
671 { 508, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_ru6
672 { 507, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_lru6
673 { 506, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_l2r
674 { 505, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCP_1r
675 { 504, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCLK_l2r
676 { 503, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_u6
677 { 502, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_lu6
678 { 501, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMU_l3r
679 { 500, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMS_l3r
680 { 499, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PEEK_2r
681 { 498, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUT_2r
682 { 497, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTT_2r
683 { 496, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTSHR_2r
684 { 495, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTPW_l2rus
685 { 494, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_rus
686 { 493, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_2r
687 { 492, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_3r
688 { 491, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
689 { 490, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG
690 { 489, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_l3r
691 { 488, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MSYNC_1r
692 { 487, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_rus
693 { 486, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_2r
694 { 485, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MJOIN_1r
695 { 484, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCU_l4r
696 { 483, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCS_l4r
697 { 482, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSU_3r
698 { 481, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSUB_l5r
699 { 480, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSS_3r
700 { 479, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 189, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LMUL_l6r
701 { 478, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_3r
702 { 477, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_2rus
703 { 476, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_ru6
704 { 475, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_lru6
705 { 474, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_ru6
706 { 473, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_lru6
707 { 472, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_u10
708 { 471, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_ru6
709 { 470, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lu10
710 { 469, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lru6
711 { 468, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSSR_0R
712 { 467, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSPC_0R
713 { 466, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSED_0R
714 { 465, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIVU_l5r
715 { 464, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDET_0R
716 { 463, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_ru6
717 { 462, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_lru6
718 { 461, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_ru6
719 { 460, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_lru6
720 { 459, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l3r
721 { 458, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l2rus
722 { 457, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_ru6
723 { 456, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_lru6
724 { 455, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_u6
725 { 454, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_lu6
726 { 453, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l3r
727 { 452, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l2rus
728 { 451, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_u10
729 { 450, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10_ba
730 { 449, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10
731 { 448, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_u10
732 { 447, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_lu10
733 { 446, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16F_l3r
734 { 445, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16B_l3r
735 { 444, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD8U_3r
736 { 443, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD16S_3r
737 { 442, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LADD_l5r
738 { 441, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRET_0R
739 { 440, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_u6
740 { 439, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_lu6
741 { 438, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_u6
742 { 437, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_lu6
743 { 436, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_u6
744 { 435, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_lu6
745 { 434, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_1r
746 { 433, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IN_2r
747 { 432, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INT_2r
748 { 431, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSHR_2r
749 { 430, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INPW_l2rus
750 { 429, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITSP_2r
751 { 428, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITPC_2r
752 { 427, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITLR_l2r
753 { 426, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITDP_2r
754 { 425, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITCP_2r
755 { 424, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INCT_2r
756 { 423, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETTS_2r
757 { 422, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETST_2r
758 { 421, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_u6
759 { 420, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_lu6
760 { 419, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETR_rus
761 { 418, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETPS_l2r
762 { 417, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETN_l2r
763 { 416, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKSP_0R
764 { 415, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKEP_0R
765 { 414, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETID_0R
766 { 413, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETET_0R
767 { 412, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETED_0R
768 { 411, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETD_l2r
769 { 410, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREET_0R
770 { 409, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREER_1r
771 { 408, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_u6
772 { 407, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_lu6
773 { 406, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_u6
774 { 405, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_lu6
775 { 404, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_3r
776 { 403, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_2rus
777 { 402, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_u6
778 { 401, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_lu6
779 { 400, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENDIN_2r
780 { 399, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEU_1r
781 { 398, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EET_2r
782 { 397, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEF_2r
783 { 396, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EDU_1r
784 { 395, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLT_1r
785 { 394, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLF_1r
786 { 393, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRET_0R
787 { 392, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRESTSP_0R
788 { 391, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVU_l3r
789 { 390, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVS_l3r
790 { 389, 1, 1, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DGETREG_1r
791 { 388, 0, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DENTSP_0R
792 { 387, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DCALL_0R
793 { 386, 4, 1, 4, 0, 0, 0, XCoreOpInfoBase + 178, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC_l3r
794 { 385, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 173, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC8_l4r
795 { 384, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_l2r
796 { 383, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_u6
797 { 382, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_lu6
798 { 381, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_u6
799 { 380, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_lu6
800 { 379, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRPT_1R
801 { 378, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRE_0R
802 { 377, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_rus
803 { 376, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_2r
804 { 375, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BYTEREV_l2r
805 { 374, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRU_1r
806 { 373, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_u6
807 { 372, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_lu6
808 { 371, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_ru6
809 { 370, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_lru6
810 { 369, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_ru6
811 { 368, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_lru6
812 { 367, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_u6
813 { 366, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_lu6
814 { 365, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_ru6
815 { 364, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_lru6
816 { 363, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_ru6
817 { 362, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_lru6
818 { 361, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_u10
819 { 360, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_lu10
820 { 359, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_u10
821 { 358, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_lu10
822 { 357, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 28, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLA_1r
823 { 356, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_u6
824 { 355, 1, 0, 4, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_lu6
825 { 354, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_u10
826 { 353, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_lu10
827 { 352, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITREV_l2r
828 { 351, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BAU_1r
829 { 350, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l3r
830 { 349, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l2rus
831 { 348, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_3r
832 { 347, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_2r
833 { 346, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_3r
834 { 345, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_2rus
835 { 344, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWFI
836 { 343, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_CC
837 { 342, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWFI
838 { 341, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWFI
839 { 340, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FRAME_TO_ARGS_OFFSET
840 { 339, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_RETURN
841 { 338, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT32
842 { 337, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT
843 { 336, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
844 { 335, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
845 { 334, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
846 { 333, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
847 { 332, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
848 { 331, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
849 { 330, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
850 { 329, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
851 { 328, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
852 { 327, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
853 { 326, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
854 { 325, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
855 { 324, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
856 { 323, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
857 { 322, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
858 { 321, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
859 { 320, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
860 { 319, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
861 { 318, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
862 { 317, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
863 { 316, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
864 { 315, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
865 { 314, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
866 { 313, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
867 { 312, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
868 { 311, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
869 { 310, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
870 { 309, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
871 { 308, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
872 { 307, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
873 { 306, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
874 { 305, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
875 { 304, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
876 { 303, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
877 { 302, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
878 { 301, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
879 { 300, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
880 { 299, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
881 { 298, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
882 { 297, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
883 { 296, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
884 { 295, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
885 { 294, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
886 { 293, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
887 { 292, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
888 { 291, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
889 { 290, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
890 { 289, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
891 { 288, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
892 { 287, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
893 { 286, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
894 { 285, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
895 { 284, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
896 { 283, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
897 { 282, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
898 { 281, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
899 { 280, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
900 { 279, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
901 { 278, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
902 { 277, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
903 { 276, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
904 { 275, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
905 { 274, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
906 { 273, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
907 { 272, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
908 { 271, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
909 { 270, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULR
910 { 269, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
911 { 268, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
912 { 267, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
913 { 266, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
914 { 265, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
915 { 264, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
916 { 263, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
917 { 262, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
918 { 261, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
919 { 260, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
920 { 259, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
921 { 258, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
922 { 257, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
923 { 256, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
924 { 255, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
925 { 254, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
926 { 253, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
927 { 252, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
928 { 251, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
929 { 250, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
930 { 249, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
931 { 248, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
932 { 247, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
933 { 246, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
934 { 245, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
935 { 244, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
936 { 243, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
937 { 242, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
938 { 241, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
939 { 240, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
940 { 239, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
941 { 238, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
942 { 237, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
943 { 236, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
944 { 235, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
945 { 234, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
946 { 233, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
947 { 232, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
948 { 231, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
949 { 230, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
950 { 229, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
951 { 228, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
952 { 227, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
953 { 226, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
954 { 225, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
955 { 224, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
956 { 223, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
957 { 222, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
958 { 221, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
959 { 220, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
960 { 219, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
961 { 218, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
962 { 217, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
963 { 216, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
964 { 215, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
965 { 214, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
966 { 213, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
967 { 212, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
968 { 211, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
969 { 210, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
970 { 209, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
971 { 208, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
972 { 207, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
973 { 206, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
974 { 205, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
975 { 204, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
976 { 203, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
977 { 202, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
978 { 201, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
979 { 200, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
980 { 199, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
981 { 198, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
982 { 197, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
983 { 196, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
984 { 195, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
985 { 194, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
986 { 193, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
987 { 192, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
988 { 191, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
989 { 190, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
990 { 189, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
991 { 188, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
992 { 187, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
993 { 186, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
994 { 185, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
995 { 184, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
996 { 183, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
997 { 182, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
998 { 181, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
999 { 180, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1000 { 179, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1001 { 178, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1002 { 177, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1003 { 176, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1004 { 175, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1005 { 174, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1006 { 173, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1007 { 172, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1008 { 171, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1009 { 170, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1010 { 169, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1011 { 168, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1012 { 167, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1013 { 166, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1014 { 165, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1015 { 164, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1016 { 163, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1017 { 162, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1018 { 161, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1019 { 160, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1020 { 159, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1021 { 158, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1022 { 157, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1023 { 156, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1024 { 155, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1025 { 154, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1026 { 153, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1027 { 152, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1028 { 151, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1029 { 150, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1030 { 149, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1031 { 148, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1032 { 147, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1033 { 146, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1034 { 145, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1035 { 144, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1036 { 143, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1037 { 142, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1038 { 141, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1039 { 140, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1040 { 139, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1041 { 138, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1042 { 137, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1043 { 136, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1044 { 135, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1045 { 134, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1046 { 133, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1047 { 132, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1048 { 131, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1049 { 130, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1050 { 129, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1051 { 128, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1052 { 127, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1053 { 126, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1054 { 125, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1055 { 124, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1056 { 123, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1057 { 122, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1058 { 121, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1059 { 120, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1060 { 119, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1061 { 118, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1062 { 117, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1063 { 116, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1064 { 115, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1065 { 114, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1066 { 113, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1067 { 112, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1068 { 111, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1069 { 110, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1070 { 109, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1071 { 108, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1072 { 107, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1073 { 106, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1074 { 105, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1075 { 104, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1076 { 103, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1077 { 102, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1078 { 101, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1079 { 100, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1080 { 99, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1081 { 98, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1082 { 97, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1083 { 96, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1084 { 95, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1085 { 94, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1086 { 93, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1087 { 92, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1088 { 91, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1089 { 90, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1090 { 89, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1091 { 88, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1092 { 87, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1093 { 86, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1094 { 85, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1095 { 84, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1096 { 83, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1097 { 82, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1098 { 81, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1099 { 80, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1100 { 79, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1101 { 78, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1102 { 77, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1103 { 76, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1104 { 75, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1105 { 74, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1106 { 73, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1107 { 72, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1108 { 71, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1109 { 70, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1110 { 69, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1111 { 68, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1112 { 67, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1113 { 66, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1114 { 65, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1115 { 64, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1116 { 63, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1117 { 62, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1118 { 61, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1119 { 60, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1120 { 59, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1121 { 58, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1122 { 57, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1123 { 56, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1124 { 55, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1125 { 54, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1126 { 53, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1127 { 52, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1128 { 51, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1129 { 50, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1130 { 49, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1131 { 48, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1132 { 47, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1133 { 46, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1134 { 45, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1135 { 44, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1136 { 43, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1137 { 42, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14788
1138 { 41, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14787
1139 { 40, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1140 { 39, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1141 { 38, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1142 { 37, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1143 { 36, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1144 { 35, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1145 { 34, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1146 { 33, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1147 { 32, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14786
1148 { 31, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1149 { 30, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14418
1150 { 29, 6, 1, 0, 0, 0, 0, XCoreOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1151 { 28, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1152 { 27, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1153 { 26, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1154 { 25, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1155 { 24, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1156 { 23, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1157 { 22, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1158 { 21, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1159 { 20, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1160 { 19, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1161 { 18, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1162 { 17, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1163 { 16, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1164 { 15, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1165 { 14, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1166 { 13, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1167 { 12, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1168 { 11, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1169 { 10, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1170 { 9, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1171 { 8, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1172 { 7, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1173 { 6, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1174 { 5, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1175 { 4, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1176 { 3, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1177 { 2, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1178 { 1, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1179 { 0, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1180 }, {
1181 /* 0 */
1182 /* 0 */ XCore::SP, XCore::SP,
1183 /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
1184 /* 9 */ XCore::R11,
1185 /* 10 */ XCore::SP,
1186 }, {
1187 0
1188 }, {
1189 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1190 /* 1 */
1191 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1192 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1193 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1194 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1195 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1196 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1197 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1198 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1199 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1200 /* 28 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1201 /* 29 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1202 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1203 /* 34 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1204 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1205 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1206 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1207 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1208 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1209 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1210 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1211 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1212 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1213 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1214 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1215 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1216 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1217 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1218 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1219 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1220 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1221 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1222 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1223 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1224 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1225 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1226 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1227 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1228 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1229 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1230 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1231 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1232 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1233 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1234 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1235 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1236 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1237 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1238 /* 153 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1239 /* 155 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1240 /* 158 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1241 /* 162 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1242 /* 165 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1243 /* 168 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1244 /* 171 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1245 /* 173 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1246 /* 178 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1247 /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1248 /* 187 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1249 /* 189 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1250 /* 195 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1251 /* 201 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1252 /* 204 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1253 /* 206 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1254 }
1255};
1256
1257
1258#ifdef __GNUC__
1259#pragma GCC diagnostic push
1260#pragma GCC diagnostic ignored "-Woverlength-strings"
1261#endif
1262extern const char XCoreInstrNameData[] = {
1263 /* 0 */ "G_FLOG10\000"
1264 /* 9 */ "G_FEXP10\000"
1265 /* 18 */ "LDAPB_u10\000"
1266 /* 28 */ "BLRB_u10\000"
1267 /* 37 */ "LDAPF_u10\000"
1268 /* 47 */ "BLRF_u10\000"
1269 /* 56 */ "BLACP_u10\000"
1270 /* 66 */ "LDWCP_u10\000"
1271 /* 76 */ "LDAPB_lu10\000"
1272 /* 87 */ "BLRB_lu10\000"
1273 /* 97 */ "LDAPF_lu10\000"
1274 /* 108 */ "BLRF_lu10\000"
1275 /* 118 */ "BLACP_lu10\000"
1276 /* 129 */ "LDWCP_lu10\000"
1277 /* 140 */ "BR_JT32\000"
1278 /* 148 */ "G_FLOG2\000"
1279 /* 156 */ "G_FATAN2\000"
1280 /* 165 */ "G_FEXP2\000"
1281 /* 173 */ "KCALL_u6\000"
1282 /* 182 */ "LDAWCP_u6\000"
1283 /* 192 */ "EXTDP_u6\000"
1284 /* 201 */ "RETSP_u6\000"
1285 /* 210 */ "KENTSP_u6\000"
1286 /* 220 */ "KRESTSP_u6\000"
1287 /* 231 */ "EXTSP_u6\000"
1288 /* 240 */ "CLRSR_u6\000"
1289 /* 249 */ "GETSR_u6\000"
1290 /* 258 */ "SETSR_u6\000"
1291 /* 267 */ "BLAT_u6\000"
1292 /* 275 */ "BRBU_u6\000"
1293 /* 283 */ "BRFU_u6\000"
1294 /* 291 */ "CLRSR_branch_u6\000"
1295 /* 307 */ "SETSR_branch_u6\000"
1296 /* 323 */ "KCALL_lu6\000"
1297 /* 333 */ "LDAWCP_lu6\000"
1298 /* 344 */ "EXTDP_lu6\000"
1299 /* 354 */ "RETSP_lu6\000"
1300 /* 364 */ "KENTSP_lu6\000"
1301 /* 375 */ "KRESTSP_lu6\000"
1302 /* 387 */ "EXTSP_lu6\000"
1303 /* 397 */ "CLRSR_lu6\000"
1304 /* 407 */ "GETSR_lu6\000"
1305 /* 417 */ "SETSR_lu6\000"
1306 /* 427 */ "BLAT_lu6\000"
1307 /* 436 */ "BRBU_lu6\000"
1308 /* 445 */ "BRFU_lu6\000"
1309 /* 454 */ "CLRSR_branch_lu6\000"
1310 /* 471 */ "SETSR_branch_lu6\000"
1311 /* 488 */ "LDC_ru6\000"
1312 /* 496 */ "SETC_ru6\000"
1313 /* 505 */ "BRBF_ru6\000"
1314 /* 514 */ "BRFF_ru6\000"
1315 /* 523 */ "LDWCP_ru6\000"
1316 /* 533 */ "LDAWDP_ru6\000"
1317 /* 544 */ "LDWDP_ru6\000"
1318 /* 554 */ "STWDP_ru6\000"
1319 /* 564 */ "LDAWSP_ru6\000"
1320 /* 575 */ "LDWSP_ru6\000"
1321 /* 585 */ "STWSP_ru6\000"
1322 /* 595 */ "BRBT_ru6\000"
1323 /* 604 */ "BRFT_ru6\000"
1324 /* 613 */ "LDC_lru6\000"
1325 /* 622 */ "SETC_lru6\000"
1326 /* 632 */ "BRBF_lru6\000"
1327 /* 642 */ "BRFF_lru6\000"
1328 /* 652 */ "LDWCP_lru6\000"
1329 /* 663 */ "LDAWDP_lru6\000"
1330 /* 675 */ "LDWDP_lru6\000"
1331 /* 686 */ "STWDP_lru6\000"
1332 /* 697 */ "LDAWSP_lru6\000"
1333 /* 709 */ "LDWSP_lru6\000"
1334 /* 720 */ "STWSP_lru6\000"
1335 /* 731 */ "BRBT_lru6\000"
1336 /* 741 */ "BRFT_lru6\000"
1337 /* 751 */ "G_FMA\000"
1338 /* 757 */ "G_STRICT_FMA\000"
1339 /* 770 */ "G_FSUB\000"
1340 /* 777 */ "G_STRICT_FSUB\000"
1341 /* 791 */ "G_ATOMICRMW_FSUB\000"
1342 /* 808 */ "G_SUB\000"
1343 /* 814 */ "G_ATOMICRMW_SUB\000"
1344 /* 830 */ "SELECT_CC\000"
1345 /* 840 */ "G_INTRINSIC\000"
1346 /* 852 */ "G_FPTRUNC\000"
1347 /* 862 */ "G_INTRINSIC_TRUNC\000"
1348 /* 880 */ "G_TRUNC\000"
1349 /* 888 */ "G_BUILD_VECTOR_TRUNC\000"
1350 /* 909 */ "G_DYN_STACKALLOC\000"
1351 /* 926 */ "G_FMAD\000"
1352 /* 933 */ "G_FPEXTLOAD\000"
1353 /* 945 */ "G_INDEXED_SEXTLOAD\000"
1354 /* 964 */ "G_SEXTLOAD\000"
1355 /* 975 */ "G_INDEXED_ZEXTLOAD\000"
1356 /* 994 */ "G_ZEXTLOAD\000"
1357 /* 1005 */ "G_INDEXED_LOAD\000"
1358 /* 1020 */ "G_LOAD\000"
1359 /* 1027 */ "G_VECREDUCE_FADD\000"
1360 /* 1044 */ "G_FADD\000"
1361 /* 1051 */ "G_VECREDUCE_SEQ_FADD\000"
1362 /* 1072 */ "G_STRICT_FADD\000"
1363 /* 1086 */ "G_ATOMICRMW_FADD\000"
1364 /* 1103 */ "G_VECREDUCE_ADD\000"
1365 /* 1119 */ "G_ADD\000"
1366 /* 1125 */ "G_PTR_ADD\000"
1367 /* 1135 */ "G_ATOMICRMW_ADD\000"
1368 /* 1151 */ "G_ATOMICRMW_NAND\000"
1369 /* 1168 */ "G_VECREDUCE_AND\000"
1370 /* 1184 */ "G_AND\000"
1371 /* 1190 */ "G_ATOMICRMW_AND\000"
1372 /* 1206 */ "LIFETIME_END\000"
1373 /* 1219 */ "G_BRCOND\000"
1374 /* 1228 */ "G_ATOMICRMW_USUB_COND\000"
1375 /* 1250 */ "G_LLROUND\000"
1376 /* 1260 */ "G_LROUND\000"
1377 /* 1269 */ "G_INTRINSIC_ROUND\000"
1378 /* 1287 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1379 /* 1313 */ "LOAD_STACK_GUARD\000"
1380 /* 1330 */ "PSEUDO_PROBE\000"
1381 /* 1343 */ "G_SSUBE\000"
1382 /* 1351 */ "G_USUBE\000"
1383 /* 1359 */ "G_FENCE\000"
1384 /* 1367 */ "ARITH_FENCE\000"
1385 /* 1379 */ "REG_SEQUENCE\000"
1386 /* 1392 */ "G_SADDE\000"
1387 /* 1400 */ "G_UADDE\000"
1388 /* 1408 */ "G_GET_FPMODE\000"
1389 /* 1421 */ "G_RESET_FPMODE\000"
1390 /* 1436 */ "G_SET_FPMODE\000"
1391 /* 1449 */ "G_FMINNUM_IEEE\000"
1392 /* 1464 */ "G_FMAXNUM_IEEE\000"
1393 /* 1479 */ "G_VSCALE\000"
1394 /* 1488 */ "G_JUMP_TABLE\000"
1395 /* 1501 */ "BUNDLE\000"
1396 /* 1508 */ "G_MEMSET_INLINE\000"
1397 /* 1524 */ "G_MEMCPY_INLINE\000"
1398 /* 1540 */ "RELOC_NONE\000"
1399 /* 1551 */ "LOCAL_ESCAPE\000"
1400 /* 1564 */ "G_FPTRUNCSTORE\000"
1401 /* 1579 */ "G_STACKRESTORE\000"
1402 /* 1594 */ "G_INDEXED_STORE\000"
1403 /* 1610 */ "G_STORE\000"
1404 /* 1618 */ "G_BITREVERSE\000"
1405 /* 1631 */ "FAKE_USE\000"
1406 /* 1640 */ "DBG_VALUE\000"
1407 /* 1650 */ "G_GLOBAL_VALUE\000"
1408 /* 1665 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1409 /* 1688 */ "CONVERGENCECTRL_GLUE\000"
1410 /* 1709 */ "G_STACKSAVE\000"
1411 /* 1721 */ "G_MEMMOVE\000"
1412 /* 1731 */ "G_FREEZE\000"
1413 /* 1740 */ "G_FCANONICALIZE\000"
1414 /* 1756 */ "G_FMODF\000"
1415 /* 1764 */ "INIT_UNDEF\000"
1416 /* 1775 */ "G_IMPLICIT_DEF\000"
1417 /* 1790 */ "DBG_INSTR_REF\000"
1418 /* 1804 */ "G_FNEG\000"
1419 /* 1811 */ "EXTRACT_SUBREG\000"
1420 /* 1826 */ "INSERT_SUBREG\000"
1421 /* 1840 */ "G_SEXT_INREG\000"
1422 /* 1853 */ "SUBREG_TO_REG\000"
1423 /* 1867 */ "G_ATOMIC_CMPXCHG\000"
1424 /* 1884 */ "G_ATOMICRMW_XCHG\000"
1425 /* 1901 */ "G_GET_ROUNDING\000"
1426 /* 1916 */ "G_SET_ROUNDING\000"
1427 /* 1931 */ "G_FLOG\000"
1428 /* 1938 */ "G_VAARG\000"
1429 /* 1946 */ "PREALLOCATED_ARG\000"
1430 /* 1963 */ "G_PREFETCH\000"
1431 /* 1974 */ "G_CLMULH\000"
1432 /* 1983 */ "G_SMULH\000"
1433 /* 1991 */ "G_UMULH\000"
1434 /* 1999 */ "G_FTANH\000"
1435 /* 2007 */ "G_FSINH\000"
1436 /* 2015 */ "G_FCOSH\000"
1437 /* 2023 */ "LDAWFI\000"
1438 /* 2030 */ "LDWFI\000"
1439 /* 2036 */ "STWFI\000"
1440 /* 2042 */ "DBG_PHI\000"
1441 /* 2050 */ "G_FPTOSI\000"
1442 /* 2059 */ "G_FPTOUI\000"
1443 /* 2068 */ "G_FPOWI\000"
1444 /* 2076 */ "COPY_LANEMASK\000"
1445 /* 2090 */ "G_PTRMASK\000"
1446 /* 2100 */ "GC_LABEL\000"
1447 /* 2109 */ "DBG_LABEL\000"
1448 /* 2119 */ "EH_LABEL\000"
1449 /* 2128 */ "ANNOTATION_LABEL\000"
1450 /* 2145 */ "ICALL_BRANCH_FUNNEL\000"
1451 /* 2165 */ "G_FSHL\000"
1452 /* 2172 */ "G_SHL\000"
1453 /* 2178 */ "G_FCEIL\000"
1454 /* 2186 */ "G_SAVGCEIL\000"
1455 /* 2197 */ "G_UAVGCEIL\000"
1456 /* 2208 */ "PATCHABLE_TAIL_CALL\000"
1457 /* 2228 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1458 /* 2255 */ "PATCHABLE_EVENT_CALL\000"
1459 /* 2276 */ "FENTRY_CALL\000"
1460 /* 2288 */ "KILL\000"
1461 /* 2293 */ "G_CONSTANT_POOL\000"
1462 /* 2309 */ "G_ROTL\000"
1463 /* 2316 */ "G_VECREDUCE_FMUL\000"
1464 /* 2333 */ "G_FMUL\000"
1465 /* 2340 */ "G_VECREDUCE_SEQ_FMUL\000"
1466 /* 2361 */ "G_STRICT_FMUL\000"
1467 /* 2375 */ "G_CLMUL\000"
1468 /* 2383 */ "G_VECREDUCE_MUL\000"
1469 /* 2399 */ "G_MUL\000"
1470 /* 2405 */ "G_FREM\000"
1471 /* 2412 */ "G_STRICT_FREM\000"
1472 /* 2426 */ "G_SREM\000"
1473 /* 2433 */ "G_UREM\000"
1474 /* 2440 */ "G_SDIVREM\000"
1475 /* 2450 */ "G_UDIVREM\000"
1476 /* 2460 */ "INLINEASM\000"
1477 /* 2470 */ "G_VECREDUCE_FMINIMUM\000"
1478 /* 2491 */ "G_FMINIMUM\000"
1479 /* 2502 */ "G_ATOMICRMW_FMINIMUM\000"
1480 /* 2523 */ "G_VECREDUCE_FMAXIMUM\000"
1481 /* 2544 */ "G_FMAXIMUM\000"
1482 /* 2555 */ "G_ATOMICRMW_FMAXIMUM\000"
1483 /* 2576 */ "G_VECREDUCE_FMINIMUMNUM\000"
1484 /* 2600 */ "G_FMINIMUMNUM\000"
1485 /* 2614 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1486 /* 2638 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1487 /* 2662 */ "G_FMAXIMUMNUM\000"
1488 /* 2676 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1489 /* 2700 */ "G_FMINNUM\000"
1490 /* 2710 */ "G_FMAXNUM\000"
1491 /* 2720 */ "G_FATAN\000"
1492 /* 2728 */ "G_FTAN\000"
1493 /* 2735 */ "G_INTRINSIC_ROUNDEVEN\000"
1494 /* 2757 */ "G_ASSERT_ALIGN\000"
1495 /* 2772 */ "G_FCOPYSIGN\000"
1496 /* 2784 */ "G_VECREDUCE_FMIN\000"
1497 /* 2801 */ "G_ATOMICRMW_FMIN\000"
1498 /* 2818 */ "G_VECREDUCE_SMIN\000"
1499 /* 2835 */ "G_SMIN\000"
1500 /* 2842 */ "G_VECREDUCE_UMIN\000"
1501 /* 2859 */ "G_UMIN\000"
1502 /* 2866 */ "G_ATOMICRMW_UMIN\000"
1503 /* 2883 */ "G_ATOMICRMW_MIN\000"
1504 /* 2899 */ "G_FASIN\000"
1505 /* 2907 */ "G_FSIN\000"
1506 /* 2914 */ "CFI_INSTRUCTION\000"
1507 /* 2930 */ "G_CTLZ_ZERO_POISON\000"
1508 /* 2949 */ "G_CTTZ_ZERO_POISON\000"
1509 /* 2968 */ "EH_RETURN\000"
1510 /* 2978 */ "ADJCALLSTACKDOWN\000"
1511 /* 2995 */ "G_SSUBO\000"
1512 /* 3003 */ "G_USUBO\000"
1513 /* 3011 */ "G_SADDO\000"
1514 /* 3019 */ "G_UADDO\000"
1515 /* 3027 */ "JUMP_TABLE_DEBUG_INFO\000"
1516 /* 3049 */ "G_SMULO\000"
1517 /* 3057 */ "G_UMULO\000"
1518 /* 3065 */ "G_BZERO\000"
1519 /* 3073 */ "STACKMAP\000"
1520 /* 3082 */ "G_DEBUGTRAP\000"
1521 /* 3094 */ "G_UBSANTRAP\000"
1522 /* 3106 */ "G_TRAP\000"
1523 /* 3113 */ "G_ATOMICRMW_UDEC_WRAP\000"
1524 /* 3135 */ "G_ATOMICRMW_UINC_WRAP\000"
1525 /* 3157 */ "G_BSWAP\000"
1526 /* 3165 */ "G_SITOFP\000"
1527 /* 3174 */ "G_UITOFP\000"
1528 /* 3183 */ "G_FCMP\000"
1529 /* 3190 */ "G_STRICT_FCMP\000"
1530 /* 3204 */ "G_ICMP\000"
1531 /* 3211 */ "G_SCMP\000"
1532 /* 3218 */ "G_UCMP\000"
1533 /* 3225 */ "CONVERGENCECTRL_LOOP\000"
1534 /* 3246 */ "G_CTPOP\000"
1535 /* 3254 */ "PATCHABLE_OP\000"
1536 /* 3267 */ "FAULTING_OP\000"
1537 /* 3279 */ "ADJCALLSTACKUP\000"
1538 /* 3294 */ "PREALLOCATED_SETUP\000"
1539 /* 3313 */ "G_FLDEXP\000"
1540 /* 3322 */ "G_STRICT_FLDEXP\000"
1541 /* 3338 */ "G_FEXP\000"
1542 /* 3345 */ "G_FFREXP\000"
1543 /* 3354 */ "LDSPC_0R\000"
1544 /* 3363 */ "STSPC_0R\000"
1545 /* 3372 */ "LDSED_0R\000"
1546 /* 3381 */ "STSED_0R\000"
1547 /* 3390 */ "GETED_0R\000"
1548 /* 3399 */ "GETID_0R\000"
1549 /* 3408 */ "CLRE_0R\000"
1550 /* 3416 */ "DCALL_0R\000"
1551 /* 3425 */ "GETKEP_0R\000"
1552 /* 3435 */ "SETKEP_0R\000"
1553 /* 3445 */ "GETKSP_0R\000"
1554 /* 3455 */ "DENTSP_0R\000"
1555 /* 3465 */ "DRESTSP_0R\000"
1556 /* 3476 */ "LDSSR_0R\000"
1557 /* 3485 */ "STSSR_0R\000"
1558 /* 3494 */ "LDET_0R\000"
1559 /* 3502 */ "FREET_0R\000"
1560 /* 3511 */ "DRET_0R\000"
1561 /* 3519 */ "KRET_0R\000"
1562 /* 3527 */ "GETET_0R\000"
1563 /* 3536 */ "STET_0R\000"
1564 /* 3544 */ "WAITEU_0R\000"
1565 /* 3554 */ "WAITEF_1R\000"
1566 /* 3564 */ "WAITET_1R\000"
1567 /* 3574 */ "CLRPT_1R\000"
1568 /* 3583 */ "TSTART_1R\000"
1569 /* 3593 */ "G_BR\000"
1570 /* 3598 */ "INLINEASM_BR\000"
1571 /* 3611 */ "G_BLOCK_ADDR\000"
1572 /* 3624 */ "MEMBARRIER\000"
1573 /* 3635 */ "G_CONSTANT_FOLD_BARRIER\000"
1574 /* 3659 */ "PATCHABLE_FUNCTION_ENTER\000"
1575 /* 3684 */ "G_READCYCLECOUNTER\000"
1576 /* 3703 */ "G_READSTEADYCOUNTER\000"
1577 /* 3723 */ "G_READ_REGISTER\000"
1578 /* 3739 */ "G_WRITE_REGISTER\000"
1579 /* 3756 */ "G_ASHR\000"
1580 /* 3763 */ "G_FSHR\000"
1581 /* 3770 */ "G_LSHR\000"
1582 /* 3777 */ "G_CLMULR\000"
1583 /* 3786 */ "CONVERGENCECTRL_ANCHOR\000"
1584 /* 3809 */ "G_FFLOOR\000"
1585 /* 3818 */ "G_SAVGFLOOR\000"
1586 /* 3830 */ "G_UAVGFLOOR\000"
1587 /* 3842 */ "G_EXTRACT_SUBVECTOR\000"
1588 /* 3862 */ "G_INSERT_SUBVECTOR\000"
1589 /* 3881 */ "G_BUILD_VECTOR\000"
1590 /* 3896 */ "G_SHUFFLE_VECTOR\000"
1591 /* 3913 */ "G_STEP_VECTOR\000"
1592 /* 3927 */ "G_SPLAT_VECTOR\000"
1593 /* 3942 */ "G_VECREDUCE_XOR\000"
1594 /* 3958 */ "G_XOR\000"
1595 /* 3964 */ "G_ATOMICRMW_XOR\000"
1596 /* 3980 */ "G_VECREDUCE_OR\000"
1597 /* 3995 */ "G_OR\000"
1598 /* 4000 */ "G_ATOMICRMW_OR\000"
1599 /* 4015 */ "G_ROTR\000"
1600 /* 4022 */ "G_INTTOPTR\000"
1601 /* 4033 */ "G_FABS\000"
1602 /* 4040 */ "G_ABS\000"
1603 /* 4046 */ "G_ABDS\000"
1604 /* 4053 */ "G_UNMERGE_VALUES\000"
1605 /* 4070 */ "G_MERGE_VALUES\000"
1606 /* 4085 */ "G_CTLS\000"
1607 /* 4092 */ "G_FACOS\000"
1608 /* 4100 */ "G_FCOS\000"
1609 /* 4107 */ "G_FSINCOS\000"
1610 /* 4117 */ "G_STRICT_FCMPS\000"
1611 /* 4132 */ "G_CONCAT_VECTORS\000"
1612 /* 4149 */ "COPY_TO_REGCLASS\000"
1613 /* 4166 */ "G_IS_FPCLASS\000"
1614 /* 4179 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1615 /* 4209 */ "G_VECTOR_COMPRESS\000"
1616 /* 4227 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1617 /* 4254 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1618 /* 4292 */ "G_TRUNC_SSAT_S\000"
1619 /* 4307 */ "G_SSUBSAT\000"
1620 /* 4317 */ "G_USUBSAT\000"
1621 /* 4327 */ "G_SADDSAT\000"
1622 /* 4337 */ "G_UADDSAT\000"
1623 /* 4347 */ "G_SSHLSAT\000"
1624 /* 4357 */ "G_USHLSAT\000"
1625 /* 4367 */ "G_SMULFIXSAT\000"
1626 /* 4380 */ "G_UMULFIXSAT\000"
1627 /* 4393 */ "G_SDIVFIXSAT\000"
1628 /* 4406 */ "G_UDIVFIXSAT\000"
1629 /* 4419 */ "G_ATOMICRMW_USUB_SAT\000"
1630 /* 4440 */ "G_FPTOSI_SAT\000"
1631 /* 4453 */ "G_FPTOUI_SAT\000"
1632 /* 4466 */ "G_EXTRACT\000"
1633 /* 4476 */ "G_SELECT\000"
1634 /* 4485 */ "G_BRINDIRECT\000"
1635 /* 4498 */ "PATCHABLE_RET\000"
1636 /* 4512 */ "FRAME_TO_ARGS_OFFSET\000"
1637 /* 4533 */ "G_MEMSET\000"
1638 /* 4542 */ "PATCHABLE_FUNCTION_EXIT\000"
1639 /* 4566 */ "G_BRJT\000"
1640 /* 4573 */ "BR_JT\000"
1641 /* 4579 */ "G_EXTRACT_VECTOR_ELT\000"
1642 /* 4600 */ "G_INSERT_VECTOR_ELT\000"
1643 /* 4620 */ "G_FCONSTANT\000"
1644 /* 4632 */ "G_CONSTANT\000"
1645 /* 4643 */ "G_INTRINSIC_CONVERGENT\000"
1646 /* 4666 */ "STATEPOINT\000"
1647 /* 4677 */ "PATCHPOINT\000"
1648 /* 4688 */ "G_PTRTOINT\000"
1649 /* 4699 */ "G_FRINT\000"
1650 /* 4707 */ "G_INTRINSIC_LLRINT\000"
1651 /* 4726 */ "G_INTRINSIC_LRINT\000"
1652 /* 4744 */ "G_FNEARBYINT\000"
1653 /* 4757 */ "NOT\000"
1654 /* 4761 */ "G_VASTART\000"
1655 /* 4771 */ "LIFETIME_START\000"
1656 /* 4786 */ "G_INVOKE_REGION_START\000"
1657 /* 4808 */ "G_INSERT\000"
1658 /* 4817 */ "G_FSQRT\000"
1659 /* 4825 */ "G_STRICT_FSQRT\000"
1660 /* 4840 */ "G_BITCAST\000"
1661 /* 4850 */ "G_ADDRSPACE_CAST\000"
1662 /* 4867 */ "DBG_VALUE_LIST\000"
1663 /* 4882 */ "G_FPEXT\000"
1664 /* 4890 */ "G_SEXT\000"
1665 /* 4897 */ "G_ASSERT_SEXT\000"
1666 /* 4911 */ "G_ANYEXT\000"
1667 /* 4920 */ "G_ZEXT\000"
1668 /* 4927 */ "G_ASSERT_ZEXT\000"
1669 /* 4941 */ "G_ABDU\000"
1670 /* 4948 */ "G_TRUNC_SSAT_U\000"
1671 /* 4963 */ "G_TRUNC_USAT_U\000"
1672 /* 4978 */ "G_FDIV\000"
1673 /* 4985 */ "G_STRICT_FDIV\000"
1674 /* 4999 */ "G_SDIV\000"
1675 /* 5006 */ "G_UDIV\000"
1676 /* 5013 */ "G_GET_FPENV\000"
1677 /* 5025 */ "G_RESET_FPENV\000"
1678 /* 5039 */ "G_SET_FPENV\000"
1679 /* 5051 */ "G_FPOW\000"
1680 /* 5058 */ "G_VECREDUCE_FMAX\000"
1681 /* 5075 */ "G_ATOMICRMW_FMAX\000"
1682 /* 5092 */ "G_VECREDUCE_SMAX\000"
1683 /* 5109 */ "G_SMAX\000"
1684 /* 5116 */ "G_VECREDUCE_UMAX\000"
1685 /* 5133 */ "G_UMAX\000"
1686 /* 5140 */ "G_ATOMICRMW_UMAX\000"
1687 /* 5157 */ "G_ATOMICRMW_MAX\000"
1688 /* 5173 */ "G_FRAME_INDEX\000"
1689 /* 5187 */ "G_SBFX\000"
1690 /* 5194 */ "G_UBFX\000"
1691 /* 5201 */ "G_SMULFIX\000"
1692 /* 5211 */ "G_UMULFIX\000"
1693 /* 5221 */ "G_SDIVFIX\000"
1694 /* 5231 */ "G_UDIVFIX\000"
1695 /* 5241 */ "G_MEMCPY\000"
1696 /* 5250 */ "COPY\000"
1697 /* 5255 */ "CONVERGENCECTRL_ENTRY\000"
1698 /* 5277 */ "G_CTLZ\000"
1699 /* 5284 */ "G_CTTZ\000"
1700 /* 5291 */ "LDAPF_lu10_ba\000"
1701 /* 5305 */ "SSYNC_0r\000"
1702 /* 5314 */ "BLA_1r\000"
1703 /* 5321 */ "MSYNC_1r\000"
1704 /* 5330 */ "ECALLF_1r\000"
1705 /* 5340 */ "DGETREG_1r\000"
1706 /* 5351 */ "KCALL_1r\000"
1707 /* 5360 */ "MJOIN_1r\000"
1708 /* 5369 */ "SETCP_1r\000"
1709 /* 5378 */ "SETDP_1r\000"
1710 /* 5387 */ "SETSP_1r\000"
1711 /* 5396 */ "SYNCR_1r\000"
1712 /* 5405 */ "FREER_1r\000"
1713 /* 5414 */ "ECALLT_1r\000"
1714 /* 5424 */ "BAU_1r\000"
1715 /* 5431 */ "EDU_1r\000"
1716 /* 5438 */ "EEU_1r\000"
1717 /* 5445 */ "BRU_1r\000"
1718 /* 5452 */ "SETEV_1r\000"
1719 /* 5461 */ "SETV_1r\000"
1720 /* 5469 */ "INITPC_2r\000"
1721 /* 5479 */ "SETPSC_2r\000"
1722 /* 5489 */ "SETD_2r\000"
1723 /* 5497 */ "EEF_2r\000"
1724 /* 5504 */ "PEEK_2r\000"
1725 /* 5512 */ "MKMSK_2r\000"
1726 /* 5521 */ "ENDIN_2r\000"
1727 /* 5530 */ "INITCP_2r\000"
1728 /* 5540 */ "INITDP_2r\000"
1729 /* 5550 */ "INITSP_2r\000"
1730 /* 5560 */ "INSHR_2r\000"
1731 /* 5569 */ "OUTSHR_2r\000"
1732 /* 5579 */ "TSETMR_2r\000"
1733 /* 5589 */ "GETTS_2r\000"
1734 /* 5598 */ "CHKCT_2r\000"
1735 /* 5607 */ "INCT_2r\000"
1736 /* 5615 */ "TESTCT_2r\000"
1737 /* 5625 */ "OUTCT_2r\000"
1738 /* 5634 */ "TESTWCT_2r\000"
1739 /* 5645 */ "EET_2r\000"
1740 /* 5652 */ "INT_2r\000"
1741 /* 5659 */ "ANDNOT_2r\000"
1742 /* 5669 */ "SETPT_2r\000"
1743 /* 5678 */ "GETST_2r\000"
1744 /* 5687 */ "OUTT_2r\000"
1745 /* 5695 */ "OUT_2r\000"
1746 /* 5702 */ "SEXT_2r\000"
1747 /* 5710 */ "ZEXT_2r\000"
1748 /* 5718 */ "SETC_l2r\000"
1749 /* 5727 */ "GETD_l2r\000"
1750 /* 5736 */ "SETCLK_l2r\000"
1751 /* 5747 */ "TESTLCL_l2r\000"
1752 /* 5759 */ "GETN_l2r\000"
1753 /* 5768 */ "SETN_l2r\000"
1754 /* 5777 */ "INITLR_l2r\000"
1755 /* 5788 */ "GETPS_l2r\000"
1756 /* 5798 */ "SETPS_l2r\000"
1757 /* 5808 */ "BYTEREV_l2r\000"
1758 /* 5820 */ "BITREV_l2r\000"
1759 /* 5831 */ "SETTW_l2r\000"
1760 /* 5841 */ "SETRDY_l2r\000"
1761 /* 5852 */ "CLZ_l2r\000"
1762 /* 5860 */ "SUB_3r\000"
1763 /* 5867 */ "ADD_3r\000"
1764 /* 5874 */ "AND_3r\000"
1765 /* 5881 */ "SHL_3r\000"
1766 /* 5888 */ "EQ_3r\000"
1767 /* 5894 */ "SHR_3r\000"
1768 /* 5901 */ "OR_3r\000"
1769 /* 5907 */ "TSETR_3r\000"
1770 /* 5916 */ "LD16S_3r\000"
1771 /* 5925 */ "LSS_3r\000"
1772 /* 5932 */ "LD8U_3r\000"
1773 /* 5940 */ "LSU_3r\000"
1774 /* 5947 */ "LDW_3r\000"
1775 /* 5954 */ "ST16_l3r\000"
1776 /* 5963 */ "ST8_l3r\000"
1777 /* 5971 */ "LDA16B_l3r\000"
1778 /* 5982 */ "LDAWB_l3r\000"
1779 /* 5992 */ "CRC_l3r\000"
1780 /* 6000 */ "LDA16F_l3r\000"
1781 /* 6011 */ "LDAWF_l3r\000"
1782 /* 6021 */ "MUL_l3r\000"
1783 /* 6029 */ "ASHR_l3r\000"
1784 /* 6038 */ "XOR_l3r\000"
1785 /* 6046 */ "REMS_l3r\000"
1786 /* 6055 */ "DIVS_l3r\000"
1787 /* 6064 */ "REMU_l3r\000"
1788 /* 6073 */ "DIVU_l3r\000"
1789 /* 6082 */ "STW_l3r\000"
1790 /* 6090 */ "CRC8_l4r\000"
1791 /* 6099 */ "MACCS_l4r\000"
1792 /* 6109 */ "MACCU_l4r\000"
1793 /* 6119 */ "LSUB_l5r\000"
1794 /* 6128 */ "LADD_l5r\000"
1795 /* 6137 */ "LDIVU_l5r\000"
1796 /* 6147 */ "LMUL_l6r\000"
1797 /* 6156 */ "SUB_2rus\000"
1798 /* 6165 */ "ADD_2rus\000"
1799 /* 6174 */ "SHL_2rus\000"
1800 /* 6183 */ "EQ_2rus\000"
1801 /* 6191 */ "SHR_2rus\000"
1802 /* 6200 */ "LDW_2rus\000"
1803 /* 6209 */ "STW_2rus\000"
1804 /* 6218 */ "LDAWB_l2rus\000"
1805 /* 6230 */ "LDAWF_l2rus\000"
1806 /* 6242 */ "ASHR_l2rus\000"
1807 /* 6253 */ "INPW_l2rus\000"
1808 /* 6264 */ "OUTPW_l2rus\000"
1809 /* 6276 */ "MKMSK_rus\000"
1810 /* 6286 */ "GETR_rus\000"
1811 /* 6295 */ "CHKCT_rus\000"
1812 /* 6305 */ "OUTCT_rus\000"
1813 /* 6315 */ "SEXT_rus\000"
1814 /* 6324 */ "ZEXT_rus\000"
1815};
1816#ifdef __GNUC__
1817#pragma GCC diagnostic pop
1818#endif
1819
1820extern const unsigned XCoreInstrNameIndices[] = {
1821 2046U, 2460U, 3598U, 2914U, 2119U, 2100U, 2128U, 2288U,
1822 1811U, 1826U, 1777U, 1764U, 1853U, 4149U, 1640U, 4867U,
1823 1790U, 2042U, 2109U, 1379U, 5250U, 2076U, 1501U, 4771U,
1824 1206U, 1330U, 1367U, 3073U, 2276U, 4677U, 1313U, 3294U,
1825 1946U, 4666U, 1551U, 3267U, 3254U, 3659U, 4498U, 4542U,
1826 2208U, 2255U, 2228U, 2145U, 1631U, 3624U, 3027U, 1540U,
1827 5255U, 3786U, 3225U, 1688U, 4897U, 4927U, 2757U, 1119U,
1828 808U, 2399U, 4999U, 5006U, 2426U, 2433U, 2440U, 2450U,
1829 1184U, 3995U, 3958U, 4046U, 4941U, 3830U, 2197U, 3818U,
1830 2186U, 1775U, 2044U, 5173U, 1650U, 1665U, 2293U, 4466U,
1831 4053U, 4808U, 4070U, 3881U, 888U, 4132U, 4688U, 4022U,
1832 4840U, 1731U, 3635U, 1287U, 862U, 1269U, 4726U, 4707U,
1833 2735U, 3684U, 3703U, 1020U, 964U, 994U, 933U, 1005U,
1834 945U, 975U, 1610U, 1564U, 1594U, 4179U, 1867U, 1884U,
1835 1135U, 814U, 1190U, 1151U, 4000U, 3964U, 5157U, 2883U,
1836 5140U, 2866U, 1086U, 791U, 5075U, 2801U, 2555U, 2502U,
1837 2676U, 2614U, 3135U, 3113U, 1228U, 4419U, 1359U, 1963U,
1838 1219U, 4485U, 4786U, 840U, 4227U, 4643U, 4254U, 4911U,
1839 880U, 4292U, 4948U, 4963U, 4632U, 4620U, 4761U, 1938U,
1840 4890U, 1840U, 4920U, 2172U, 3770U, 3756U, 2165U, 3763U,
1841 4015U, 2309U, 3204U, 3183U, 3211U, 3218U, 4476U, 3019U,
1842 1400U, 3003U, 1351U, 3011U, 1392U, 2995U, 1343U, 3057U,
1843 3049U, 1991U, 1983U, 4337U, 4327U, 4317U, 4307U, 4357U,
1844 4347U, 5201U, 5211U, 4367U, 4380U, 5221U, 5231U, 4393U,
1845 4406U, 1044U, 770U, 2333U, 751U, 926U, 4978U, 2405U,
1846 1756U, 5051U, 2068U, 3338U, 165U, 9U, 1931U, 148U,
1847 0U, 3313U, 3345U, 1804U, 4882U, 852U, 2050U, 2059U,
1848 3165U, 3174U, 4440U, 4453U, 4033U, 2772U, 4166U, 1740U,
1849 2700U, 2710U, 1449U, 1464U, 2491U, 2544U, 2600U, 2662U,
1850 5013U, 5039U, 5025U, 1408U, 1436U, 1421U, 1901U, 1916U,
1851 1125U, 2090U, 2835U, 5109U, 2859U, 5133U, 4040U, 1260U,
1852 1250U, 3593U, 4566U, 1479U, 3862U, 3842U, 4600U, 4579U,
1853 3896U, 3927U, 3913U, 4209U, 5284U, 2949U, 5277U, 2930U,
1854 4085U, 3246U, 3157U, 1618U, 2375U, 1974U, 3777U, 2178U,
1855 4100U, 2907U, 4107U, 2728U, 4092U, 2899U, 2720U, 156U,
1856 2015U, 2007U, 1999U, 4817U, 3809U, 4699U, 4744U, 4850U,
1857 3611U, 1488U, 909U, 1709U, 1579U, 1072U, 777U, 2361U,
1858 4985U, 2412U, 757U, 4825U, 3322U, 3190U, 4117U, 3723U,
1859 3739U, 5241U, 1524U, 1721U, 4533U, 3065U, 1508U, 3106U,
1860 3082U, 3094U, 1051U, 2340U, 1027U, 2316U, 5058U, 2784U,
1861 2523U, 2470U, 2638U, 2576U, 1103U, 2383U, 1168U, 3980U,
1862 3942U, 5092U, 2818U, 5116U, 2842U, 5187U, 5194U, 2978U,
1863 3279U, 4573U, 140U, 2968U, 4512U, 2023U, 2030U, 830U,
1864 2036U, 6165U, 5867U, 5659U, 5874U, 6242U, 6029U, 5424U,
1865 5820U, 118U, 56U, 427U, 267U, 5314U, 87U, 28U,
1866 108U, 47U, 632U, 505U, 731U, 595U, 436U, 275U,
1867 642U, 514U, 741U, 604U, 445U, 283U, 5445U, 5808U,
1868 5598U, 6295U, 3408U, 3574U, 454U, 291U, 397U, 240U,
1869 5852U, 6090U, 5992U, 3416U, 3455U, 5340U, 6055U, 6073U,
1870 3465U, 3511U, 5330U, 5414U, 5431U, 5497U, 5645U, 5438U,
1871 5521U, 365U, 211U, 6183U, 5888U, 344U, 192U, 387U,
1872 231U, 5405U, 3502U, 5727U, 3390U, 3527U, 3399U, 3425U,
1873 3445U, 5759U, 5788U, 6286U, 407U, 249U, 5678U, 5589U,
1874 5607U, 5530U, 5540U, 5777U, 5469U, 5550U, 6253U, 5560U,
1875 5652U, 5524U, 5351U, 323U, 173U, 364U, 210U, 375U,
1876 220U, 3519U, 6128U, 5916U, 5932U, 5971U, 6000U, 76U,
1877 18U, 97U, 5291U, 37U, 6218U, 5982U, 333U, 182U,
1878 663U, 533U, 6230U, 6011U, 697U, 564U, 613U, 488U,
1879 3494U, 6137U, 3372U, 3354U, 3476U, 652U, 129U, 523U,
1880 66U, 675U, 544U, 709U, 575U, 6200U, 5947U, 6147U,
1881 5925U, 6119U, 5940U, 6099U, 6109U, 5360U, 5512U, 6276U,
1882 5321U, 6021U, 1807U, 4757U, 5901U, 5625U, 6305U, 6264U,
1883 5569U, 5687U, 5695U, 5504U, 6046U, 6064U, 354U, 201U,
1884 5736U, 5369U, 5718U, 622U, 496U, 5378U, 5489U, 5452U,
1885 3435U, 5768U, 5479U, 5798U, 5669U, 5841U, 5387U, 471U,
1886 307U, 417U, 258U, 5831U, 5461U, 5702U, 6315U, 6174U,
1887 5881U, 6191U, 5894U, 5305U, 5954U, 5963U, 3536U, 3381U,
1888 3363U, 3485U, 686U, 554U, 720U, 585U, 6209U, 6082U,
1889 6156U, 5860U, 5396U, 5615U, 5747U, 5634U, 5579U, 5907U,
1890 3583U, 3554U, 3564U, 3544U, 6038U, 5710U, 6324U,
1891};
1892
1893static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1894 II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 559, nullptr, 0);
1895}
1896
1897
1898} // namespace llvm
1899
1900#endif // GET_INSTRINFO_MC_DESC
1901
1902#ifdef GET_INSTRINFO_HEADER
1903#undef GET_INSTRINFO_HEADER
1904
1905namespace llvm {
1906
1907struct XCoreGenInstrInfo : public TargetInstrInfo {
1908 explicit XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1909 ~XCoreGenInstrInfo() override = default;
1910};
1911
1912} // namespace llvm
1913
1914namespace llvm::XCore {
1915
1916
1917} // namespace llvm::XCore
1918
1919#endif // GET_INSTRINFO_HEADER
1920
1921#ifdef GET_INSTRINFO_HELPER_DECLS
1922#undef GET_INSTRINFO_HELPER_DECLS
1923
1924
1925#endif // GET_INSTRINFO_HELPER_DECLS
1926
1927#ifdef GET_INSTRINFO_HELPERS
1928#undef GET_INSTRINFO_HELPERS
1929
1930
1931#endif // GET_INSTRINFO_HELPERS
1932
1933#ifdef GET_INSTRINFO_CTOR_DTOR
1934#undef GET_INSTRINFO_CTOR_DTOR
1935
1936namespace llvm {
1937
1938extern const XCoreInstrTable XCoreDescs;
1939extern const unsigned XCoreInstrNameIndices[];
1940extern const char XCoreInstrNameData[];
1941XCoreGenInstrInfo::XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1942 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1943 InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 559);
1944}
1945
1946} // namespace llvm
1947
1948#endif // GET_INSTRINFO_CTOR_DTOR
1949
1950#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1951#undef GET_INSTRINFO_MC_HELPER_DECLS
1952
1953namespace llvm {
1954
1955class MCInst;
1956class FeatureBitset;
1957
1958namespace XCore_MC {
1959
1960void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1961
1962} // namespace XCore_MC
1963
1964} // namespace llvm
1965
1966#endif // GET_INSTRINFO_MC_HELPER_DECLS
1967
1968#ifdef GET_INSTRINFO_MC_HELPERS
1969#undef GET_INSTRINFO_MC_HELPERS
1970
1971namespace llvm::XCore_MC {
1972
1973
1974} // namespace llvm::XCore_MC
1975
1976#endif // GET_INSTRINFO_MC_HELPERS
1977
1978#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1979 defined(GET_AVAILABLE_OPCODE_CHECKER)
1980#define GET_COMPUTE_FEATURES
1981#endif
1982#ifdef GET_COMPUTE_FEATURES
1983#undef GET_COMPUTE_FEATURES
1984
1985namespace llvm::XCore_MC {
1986
1987// Bits for subtarget features that participate in instruction matching.
1988enum SubtargetFeatureBits : uint8_t {
1989};
1990
1991inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1992 FeatureBitset Features;
1993 return Features;
1994}
1995
1996inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1997 enum : uint8_t {
1998 CEFBS_None,
1999 };
2000
2001 static constexpr FeatureBitset FeatureBitsets[] = {
2002 {}, // CEFBS_None
2003 };
2004 static constexpr uint8_t RequiredFeaturesRefs[] = {
2005 CEFBS_None, // PHI
2006 CEFBS_None, // INLINEASM
2007 CEFBS_None, // INLINEASM_BR
2008 CEFBS_None, // CFI_INSTRUCTION
2009 CEFBS_None, // EH_LABEL
2010 CEFBS_None, // GC_LABEL
2011 CEFBS_None, // ANNOTATION_LABEL
2012 CEFBS_None, // KILL
2013 CEFBS_None, // EXTRACT_SUBREG
2014 CEFBS_None, // INSERT_SUBREG
2015 CEFBS_None, // IMPLICIT_DEF
2016 CEFBS_None, // INIT_UNDEF
2017 CEFBS_None, // SUBREG_TO_REG
2018 CEFBS_None, // COPY_TO_REGCLASS
2019 CEFBS_None, // DBG_VALUE
2020 CEFBS_None, // DBG_VALUE_LIST
2021 CEFBS_None, // DBG_INSTR_REF
2022 CEFBS_None, // DBG_PHI
2023 CEFBS_None, // DBG_LABEL
2024 CEFBS_None, // REG_SEQUENCE
2025 CEFBS_None, // COPY
2026 CEFBS_None, // COPY_LANEMASK
2027 CEFBS_None, // BUNDLE
2028 CEFBS_None, // LIFETIME_START
2029 CEFBS_None, // LIFETIME_END
2030 CEFBS_None, // PSEUDO_PROBE
2031 CEFBS_None, // ARITH_FENCE
2032 CEFBS_None, // STACKMAP
2033 CEFBS_None, // FENTRY_CALL
2034 CEFBS_None, // PATCHPOINT
2035 CEFBS_None, // LOAD_STACK_GUARD
2036 CEFBS_None, // PREALLOCATED_SETUP
2037 CEFBS_None, // PREALLOCATED_ARG
2038 CEFBS_None, // STATEPOINT
2039 CEFBS_None, // LOCAL_ESCAPE
2040 CEFBS_None, // FAULTING_OP
2041 CEFBS_None, // PATCHABLE_OP
2042 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2043 CEFBS_None, // PATCHABLE_RET
2044 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2045 CEFBS_None, // PATCHABLE_TAIL_CALL
2046 CEFBS_None, // PATCHABLE_EVENT_CALL
2047 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2048 CEFBS_None, // ICALL_BRANCH_FUNNEL
2049 CEFBS_None, // FAKE_USE
2050 CEFBS_None, // MEMBARRIER
2051 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2052 CEFBS_None, // RELOC_NONE
2053 CEFBS_None, // CONVERGENCECTRL_ENTRY
2054 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2055 CEFBS_None, // CONVERGENCECTRL_LOOP
2056 CEFBS_None, // CONVERGENCECTRL_GLUE
2057 CEFBS_None, // G_ASSERT_SEXT
2058 CEFBS_None, // G_ASSERT_ZEXT
2059 CEFBS_None, // G_ASSERT_ALIGN
2060 CEFBS_None, // G_ADD
2061 CEFBS_None, // G_SUB
2062 CEFBS_None, // G_MUL
2063 CEFBS_None, // G_SDIV
2064 CEFBS_None, // G_UDIV
2065 CEFBS_None, // G_SREM
2066 CEFBS_None, // G_UREM
2067 CEFBS_None, // G_SDIVREM
2068 CEFBS_None, // G_UDIVREM
2069 CEFBS_None, // G_AND
2070 CEFBS_None, // G_OR
2071 CEFBS_None, // G_XOR
2072 CEFBS_None, // G_ABDS
2073 CEFBS_None, // G_ABDU
2074 CEFBS_None, // G_UAVGFLOOR
2075 CEFBS_None, // G_UAVGCEIL
2076 CEFBS_None, // G_SAVGFLOOR
2077 CEFBS_None, // G_SAVGCEIL
2078 CEFBS_None, // G_IMPLICIT_DEF
2079 CEFBS_None, // G_PHI
2080 CEFBS_None, // G_FRAME_INDEX
2081 CEFBS_None, // G_GLOBAL_VALUE
2082 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2083 CEFBS_None, // G_CONSTANT_POOL
2084 CEFBS_None, // G_EXTRACT
2085 CEFBS_None, // G_UNMERGE_VALUES
2086 CEFBS_None, // G_INSERT
2087 CEFBS_None, // G_MERGE_VALUES
2088 CEFBS_None, // G_BUILD_VECTOR
2089 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2090 CEFBS_None, // G_CONCAT_VECTORS
2091 CEFBS_None, // G_PTRTOINT
2092 CEFBS_None, // G_INTTOPTR
2093 CEFBS_None, // G_BITCAST
2094 CEFBS_None, // G_FREEZE
2095 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2096 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2097 CEFBS_None, // G_INTRINSIC_TRUNC
2098 CEFBS_None, // G_INTRINSIC_ROUND
2099 CEFBS_None, // G_INTRINSIC_LRINT
2100 CEFBS_None, // G_INTRINSIC_LLRINT
2101 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2102 CEFBS_None, // G_READCYCLECOUNTER
2103 CEFBS_None, // G_READSTEADYCOUNTER
2104 CEFBS_None, // G_LOAD
2105 CEFBS_None, // G_SEXTLOAD
2106 CEFBS_None, // G_ZEXTLOAD
2107 CEFBS_None, // G_FPEXTLOAD
2108 CEFBS_None, // G_INDEXED_LOAD
2109 CEFBS_None, // G_INDEXED_SEXTLOAD
2110 CEFBS_None, // G_INDEXED_ZEXTLOAD
2111 CEFBS_None, // G_STORE
2112 CEFBS_None, // G_FPTRUNCSTORE
2113 CEFBS_None, // G_INDEXED_STORE
2114 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2115 CEFBS_None, // G_ATOMIC_CMPXCHG
2116 CEFBS_None, // G_ATOMICRMW_XCHG
2117 CEFBS_None, // G_ATOMICRMW_ADD
2118 CEFBS_None, // G_ATOMICRMW_SUB
2119 CEFBS_None, // G_ATOMICRMW_AND
2120 CEFBS_None, // G_ATOMICRMW_NAND
2121 CEFBS_None, // G_ATOMICRMW_OR
2122 CEFBS_None, // G_ATOMICRMW_XOR
2123 CEFBS_None, // G_ATOMICRMW_MAX
2124 CEFBS_None, // G_ATOMICRMW_MIN
2125 CEFBS_None, // G_ATOMICRMW_UMAX
2126 CEFBS_None, // G_ATOMICRMW_UMIN
2127 CEFBS_None, // G_ATOMICRMW_FADD
2128 CEFBS_None, // G_ATOMICRMW_FSUB
2129 CEFBS_None, // G_ATOMICRMW_FMAX
2130 CEFBS_None, // G_ATOMICRMW_FMIN
2131 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2132 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2133 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2134 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2135 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2136 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2137 CEFBS_None, // G_ATOMICRMW_USUB_COND
2138 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2139 CEFBS_None, // G_FENCE
2140 CEFBS_None, // G_PREFETCH
2141 CEFBS_None, // G_BRCOND
2142 CEFBS_None, // G_BRINDIRECT
2143 CEFBS_None, // G_INVOKE_REGION_START
2144 CEFBS_None, // G_INTRINSIC
2145 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2146 CEFBS_None, // G_INTRINSIC_CONVERGENT
2147 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2148 CEFBS_None, // G_ANYEXT
2149 CEFBS_None, // G_TRUNC
2150 CEFBS_None, // G_TRUNC_SSAT_S
2151 CEFBS_None, // G_TRUNC_SSAT_U
2152 CEFBS_None, // G_TRUNC_USAT_U
2153 CEFBS_None, // G_CONSTANT
2154 CEFBS_None, // G_FCONSTANT
2155 CEFBS_None, // G_VASTART
2156 CEFBS_None, // G_VAARG
2157 CEFBS_None, // G_SEXT
2158 CEFBS_None, // G_SEXT_INREG
2159 CEFBS_None, // G_ZEXT
2160 CEFBS_None, // G_SHL
2161 CEFBS_None, // G_LSHR
2162 CEFBS_None, // G_ASHR
2163 CEFBS_None, // G_FSHL
2164 CEFBS_None, // G_FSHR
2165 CEFBS_None, // G_ROTR
2166 CEFBS_None, // G_ROTL
2167 CEFBS_None, // G_ICMP
2168 CEFBS_None, // G_FCMP
2169 CEFBS_None, // G_SCMP
2170 CEFBS_None, // G_UCMP
2171 CEFBS_None, // G_SELECT
2172 CEFBS_None, // G_UADDO
2173 CEFBS_None, // G_UADDE
2174 CEFBS_None, // G_USUBO
2175 CEFBS_None, // G_USUBE
2176 CEFBS_None, // G_SADDO
2177 CEFBS_None, // G_SADDE
2178 CEFBS_None, // G_SSUBO
2179 CEFBS_None, // G_SSUBE
2180 CEFBS_None, // G_UMULO
2181 CEFBS_None, // G_SMULO
2182 CEFBS_None, // G_UMULH
2183 CEFBS_None, // G_SMULH
2184 CEFBS_None, // G_UADDSAT
2185 CEFBS_None, // G_SADDSAT
2186 CEFBS_None, // G_USUBSAT
2187 CEFBS_None, // G_SSUBSAT
2188 CEFBS_None, // G_USHLSAT
2189 CEFBS_None, // G_SSHLSAT
2190 CEFBS_None, // G_SMULFIX
2191 CEFBS_None, // G_UMULFIX
2192 CEFBS_None, // G_SMULFIXSAT
2193 CEFBS_None, // G_UMULFIXSAT
2194 CEFBS_None, // G_SDIVFIX
2195 CEFBS_None, // G_UDIVFIX
2196 CEFBS_None, // G_SDIVFIXSAT
2197 CEFBS_None, // G_UDIVFIXSAT
2198 CEFBS_None, // G_FADD
2199 CEFBS_None, // G_FSUB
2200 CEFBS_None, // G_FMUL
2201 CEFBS_None, // G_FMA
2202 CEFBS_None, // G_FMAD
2203 CEFBS_None, // G_FDIV
2204 CEFBS_None, // G_FREM
2205 CEFBS_None, // G_FMODF
2206 CEFBS_None, // G_FPOW
2207 CEFBS_None, // G_FPOWI
2208 CEFBS_None, // G_FEXP
2209 CEFBS_None, // G_FEXP2
2210 CEFBS_None, // G_FEXP10
2211 CEFBS_None, // G_FLOG
2212 CEFBS_None, // G_FLOG2
2213 CEFBS_None, // G_FLOG10
2214 CEFBS_None, // G_FLDEXP
2215 CEFBS_None, // G_FFREXP
2216 CEFBS_None, // G_FNEG
2217 CEFBS_None, // G_FPEXT
2218 CEFBS_None, // G_FPTRUNC
2219 CEFBS_None, // G_FPTOSI
2220 CEFBS_None, // G_FPTOUI
2221 CEFBS_None, // G_SITOFP
2222 CEFBS_None, // G_UITOFP
2223 CEFBS_None, // G_FPTOSI_SAT
2224 CEFBS_None, // G_FPTOUI_SAT
2225 CEFBS_None, // G_FABS
2226 CEFBS_None, // G_FCOPYSIGN
2227 CEFBS_None, // G_IS_FPCLASS
2228 CEFBS_None, // G_FCANONICALIZE
2229 CEFBS_None, // G_FMINNUM
2230 CEFBS_None, // G_FMAXNUM
2231 CEFBS_None, // G_FMINNUM_IEEE
2232 CEFBS_None, // G_FMAXNUM_IEEE
2233 CEFBS_None, // G_FMINIMUM
2234 CEFBS_None, // G_FMAXIMUM
2235 CEFBS_None, // G_FMINIMUMNUM
2236 CEFBS_None, // G_FMAXIMUMNUM
2237 CEFBS_None, // G_GET_FPENV
2238 CEFBS_None, // G_SET_FPENV
2239 CEFBS_None, // G_RESET_FPENV
2240 CEFBS_None, // G_GET_FPMODE
2241 CEFBS_None, // G_SET_FPMODE
2242 CEFBS_None, // G_RESET_FPMODE
2243 CEFBS_None, // G_GET_ROUNDING
2244 CEFBS_None, // G_SET_ROUNDING
2245 CEFBS_None, // G_PTR_ADD
2246 CEFBS_None, // G_PTRMASK
2247 CEFBS_None, // G_SMIN
2248 CEFBS_None, // G_SMAX
2249 CEFBS_None, // G_UMIN
2250 CEFBS_None, // G_UMAX
2251 CEFBS_None, // G_ABS
2252 CEFBS_None, // G_LROUND
2253 CEFBS_None, // G_LLROUND
2254 CEFBS_None, // G_BR
2255 CEFBS_None, // G_BRJT
2256 CEFBS_None, // G_VSCALE
2257 CEFBS_None, // G_INSERT_SUBVECTOR
2258 CEFBS_None, // G_EXTRACT_SUBVECTOR
2259 CEFBS_None, // G_INSERT_VECTOR_ELT
2260 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2261 CEFBS_None, // G_SHUFFLE_VECTOR
2262 CEFBS_None, // G_SPLAT_VECTOR
2263 CEFBS_None, // G_STEP_VECTOR
2264 CEFBS_None, // G_VECTOR_COMPRESS
2265 CEFBS_None, // G_CTTZ
2266 CEFBS_None, // G_CTTZ_ZERO_POISON
2267 CEFBS_None, // G_CTLZ
2268 CEFBS_None, // G_CTLZ_ZERO_POISON
2269 CEFBS_None, // G_CTLS
2270 CEFBS_None, // G_CTPOP
2271 CEFBS_None, // G_BSWAP
2272 CEFBS_None, // G_BITREVERSE
2273 CEFBS_None, // G_CLMUL
2274 CEFBS_None, // G_CLMULH
2275 CEFBS_None, // G_CLMULR
2276 CEFBS_None, // G_FCEIL
2277 CEFBS_None, // G_FCOS
2278 CEFBS_None, // G_FSIN
2279 CEFBS_None, // G_FSINCOS
2280 CEFBS_None, // G_FTAN
2281 CEFBS_None, // G_FACOS
2282 CEFBS_None, // G_FASIN
2283 CEFBS_None, // G_FATAN
2284 CEFBS_None, // G_FATAN2
2285 CEFBS_None, // G_FCOSH
2286 CEFBS_None, // G_FSINH
2287 CEFBS_None, // G_FTANH
2288 CEFBS_None, // G_FSQRT
2289 CEFBS_None, // G_FFLOOR
2290 CEFBS_None, // G_FRINT
2291 CEFBS_None, // G_FNEARBYINT
2292 CEFBS_None, // G_ADDRSPACE_CAST
2293 CEFBS_None, // G_BLOCK_ADDR
2294 CEFBS_None, // G_JUMP_TABLE
2295 CEFBS_None, // G_DYN_STACKALLOC
2296 CEFBS_None, // G_STACKSAVE
2297 CEFBS_None, // G_STACKRESTORE
2298 CEFBS_None, // G_STRICT_FADD
2299 CEFBS_None, // G_STRICT_FSUB
2300 CEFBS_None, // G_STRICT_FMUL
2301 CEFBS_None, // G_STRICT_FDIV
2302 CEFBS_None, // G_STRICT_FREM
2303 CEFBS_None, // G_STRICT_FMA
2304 CEFBS_None, // G_STRICT_FSQRT
2305 CEFBS_None, // G_STRICT_FLDEXP
2306 CEFBS_None, // G_STRICT_FCMP
2307 CEFBS_None, // G_STRICT_FCMPS
2308 CEFBS_None, // G_READ_REGISTER
2309 CEFBS_None, // G_WRITE_REGISTER
2310 CEFBS_None, // G_MEMCPY
2311 CEFBS_None, // G_MEMCPY_INLINE
2312 CEFBS_None, // G_MEMMOVE
2313 CEFBS_None, // G_MEMSET
2314 CEFBS_None, // G_BZERO
2315 CEFBS_None, // G_MEMSET_INLINE
2316 CEFBS_None, // G_TRAP
2317 CEFBS_None, // G_DEBUGTRAP
2318 CEFBS_None, // G_UBSANTRAP
2319 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2320 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2321 CEFBS_None, // G_VECREDUCE_FADD
2322 CEFBS_None, // G_VECREDUCE_FMUL
2323 CEFBS_None, // G_VECREDUCE_FMAX
2324 CEFBS_None, // G_VECREDUCE_FMIN
2325 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2326 CEFBS_None, // G_VECREDUCE_FMINIMUM
2327 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2328 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2329 CEFBS_None, // G_VECREDUCE_ADD
2330 CEFBS_None, // G_VECREDUCE_MUL
2331 CEFBS_None, // G_VECREDUCE_AND
2332 CEFBS_None, // G_VECREDUCE_OR
2333 CEFBS_None, // G_VECREDUCE_XOR
2334 CEFBS_None, // G_VECREDUCE_SMAX
2335 CEFBS_None, // G_VECREDUCE_SMIN
2336 CEFBS_None, // G_VECREDUCE_UMAX
2337 CEFBS_None, // G_VECREDUCE_UMIN
2338 CEFBS_None, // G_SBFX
2339 CEFBS_None, // G_UBFX
2340 CEFBS_None, // ADJCALLSTACKDOWN
2341 CEFBS_None, // ADJCALLSTACKUP
2342 CEFBS_None, // BR_JT
2343 CEFBS_None, // BR_JT32
2344 CEFBS_None, // EH_RETURN
2345 CEFBS_None, // FRAME_TO_ARGS_OFFSET
2346 CEFBS_None, // LDAWFI
2347 CEFBS_None, // LDWFI
2348 CEFBS_None, // SELECT_CC
2349 CEFBS_None, // STWFI
2350 CEFBS_None, // ADD_2rus
2351 CEFBS_None, // ADD_3r
2352 CEFBS_None, // ANDNOT_2r
2353 CEFBS_None, // AND_3r
2354 CEFBS_None, // ASHR_l2rus
2355 CEFBS_None, // ASHR_l3r
2356 CEFBS_None, // BAU_1r
2357 CEFBS_None, // BITREV_l2r
2358 CEFBS_None, // BLACP_lu10
2359 CEFBS_None, // BLACP_u10
2360 CEFBS_None, // BLAT_lu6
2361 CEFBS_None, // BLAT_u6
2362 CEFBS_None, // BLA_1r
2363 CEFBS_None, // BLRB_lu10
2364 CEFBS_None, // BLRB_u10
2365 CEFBS_None, // BLRF_lu10
2366 CEFBS_None, // BLRF_u10
2367 CEFBS_None, // BRBF_lru6
2368 CEFBS_None, // BRBF_ru6
2369 CEFBS_None, // BRBT_lru6
2370 CEFBS_None, // BRBT_ru6
2371 CEFBS_None, // BRBU_lu6
2372 CEFBS_None, // BRBU_u6
2373 CEFBS_None, // BRFF_lru6
2374 CEFBS_None, // BRFF_ru6
2375 CEFBS_None, // BRFT_lru6
2376 CEFBS_None, // BRFT_ru6
2377 CEFBS_None, // BRFU_lu6
2378 CEFBS_None, // BRFU_u6
2379 CEFBS_None, // BRU_1r
2380 CEFBS_None, // BYTEREV_l2r
2381 CEFBS_None, // CHKCT_2r
2382 CEFBS_None, // CHKCT_rus
2383 CEFBS_None, // CLRE_0R
2384 CEFBS_None, // CLRPT_1R
2385 CEFBS_None, // CLRSR_branch_lu6
2386 CEFBS_None, // CLRSR_branch_u6
2387 CEFBS_None, // CLRSR_lu6
2388 CEFBS_None, // CLRSR_u6
2389 CEFBS_None, // CLZ_l2r
2390 CEFBS_None, // CRC8_l4r
2391 CEFBS_None, // CRC_l3r
2392 CEFBS_None, // DCALL_0R
2393 CEFBS_None, // DENTSP_0R
2394 CEFBS_None, // DGETREG_1r
2395 CEFBS_None, // DIVS_l3r
2396 CEFBS_None, // DIVU_l3r
2397 CEFBS_None, // DRESTSP_0R
2398 CEFBS_None, // DRET_0R
2399 CEFBS_None, // ECALLF_1r
2400 CEFBS_None, // ECALLT_1r
2401 CEFBS_None, // EDU_1r
2402 CEFBS_None, // EEF_2r
2403 CEFBS_None, // EET_2r
2404 CEFBS_None, // EEU_1r
2405 CEFBS_None, // ENDIN_2r
2406 CEFBS_None, // ENTSP_lu6
2407 CEFBS_None, // ENTSP_u6
2408 CEFBS_None, // EQ_2rus
2409 CEFBS_None, // EQ_3r
2410 CEFBS_None, // EXTDP_lu6
2411 CEFBS_None, // EXTDP_u6
2412 CEFBS_None, // EXTSP_lu6
2413 CEFBS_None, // EXTSP_u6
2414 CEFBS_None, // FREER_1r
2415 CEFBS_None, // FREET_0R
2416 CEFBS_None, // GETD_l2r
2417 CEFBS_None, // GETED_0R
2418 CEFBS_None, // GETET_0R
2419 CEFBS_None, // GETID_0R
2420 CEFBS_None, // GETKEP_0R
2421 CEFBS_None, // GETKSP_0R
2422 CEFBS_None, // GETN_l2r
2423 CEFBS_None, // GETPS_l2r
2424 CEFBS_None, // GETR_rus
2425 CEFBS_None, // GETSR_lu6
2426 CEFBS_None, // GETSR_u6
2427 CEFBS_None, // GETST_2r
2428 CEFBS_None, // GETTS_2r
2429 CEFBS_None, // INCT_2r
2430 CEFBS_None, // INITCP_2r
2431 CEFBS_None, // INITDP_2r
2432 CEFBS_None, // INITLR_l2r
2433 CEFBS_None, // INITPC_2r
2434 CEFBS_None, // INITSP_2r
2435 CEFBS_None, // INPW_l2rus
2436 CEFBS_None, // INSHR_2r
2437 CEFBS_None, // INT_2r
2438 CEFBS_None, // IN_2r
2439 CEFBS_None, // KCALL_1r
2440 CEFBS_None, // KCALL_lu6
2441 CEFBS_None, // KCALL_u6
2442 CEFBS_None, // KENTSP_lu6
2443 CEFBS_None, // KENTSP_u6
2444 CEFBS_None, // KRESTSP_lu6
2445 CEFBS_None, // KRESTSP_u6
2446 CEFBS_None, // KRET_0R
2447 CEFBS_None, // LADD_l5r
2448 CEFBS_None, // LD16S_3r
2449 CEFBS_None, // LD8U_3r
2450 CEFBS_None, // LDA16B_l3r
2451 CEFBS_None, // LDA16F_l3r
2452 CEFBS_None, // LDAPB_lu10
2453 CEFBS_None, // LDAPB_u10
2454 CEFBS_None, // LDAPF_lu10
2455 CEFBS_None, // LDAPF_lu10_ba
2456 CEFBS_None, // LDAPF_u10
2457 CEFBS_None, // LDAWB_l2rus
2458 CEFBS_None, // LDAWB_l3r
2459 CEFBS_None, // LDAWCP_lu6
2460 CEFBS_None, // LDAWCP_u6
2461 CEFBS_None, // LDAWDP_lru6
2462 CEFBS_None, // LDAWDP_ru6
2463 CEFBS_None, // LDAWF_l2rus
2464 CEFBS_None, // LDAWF_l3r
2465 CEFBS_None, // LDAWSP_lru6
2466 CEFBS_None, // LDAWSP_ru6
2467 CEFBS_None, // LDC_lru6
2468 CEFBS_None, // LDC_ru6
2469 CEFBS_None, // LDET_0R
2470 CEFBS_None, // LDIVU_l5r
2471 CEFBS_None, // LDSED_0R
2472 CEFBS_None, // LDSPC_0R
2473 CEFBS_None, // LDSSR_0R
2474 CEFBS_None, // LDWCP_lru6
2475 CEFBS_None, // LDWCP_lu10
2476 CEFBS_None, // LDWCP_ru6
2477 CEFBS_None, // LDWCP_u10
2478 CEFBS_None, // LDWDP_lru6
2479 CEFBS_None, // LDWDP_ru6
2480 CEFBS_None, // LDWSP_lru6
2481 CEFBS_None, // LDWSP_ru6
2482 CEFBS_None, // LDW_2rus
2483 CEFBS_None, // LDW_3r
2484 CEFBS_None, // LMUL_l6r
2485 CEFBS_None, // LSS_3r
2486 CEFBS_None, // LSUB_l5r
2487 CEFBS_None, // LSU_3r
2488 CEFBS_None, // MACCS_l4r
2489 CEFBS_None, // MACCU_l4r
2490 CEFBS_None, // MJOIN_1r
2491 CEFBS_None, // MKMSK_2r
2492 CEFBS_None, // MKMSK_rus
2493 CEFBS_None, // MSYNC_1r
2494 CEFBS_None, // MUL_l3r
2495 CEFBS_None, // NEG
2496 CEFBS_None, // NOT
2497 CEFBS_None, // OR_3r
2498 CEFBS_None, // OUTCT_2r
2499 CEFBS_None, // OUTCT_rus
2500 CEFBS_None, // OUTPW_l2rus
2501 CEFBS_None, // OUTSHR_2r
2502 CEFBS_None, // OUTT_2r
2503 CEFBS_None, // OUT_2r
2504 CEFBS_None, // PEEK_2r
2505 CEFBS_None, // REMS_l3r
2506 CEFBS_None, // REMU_l3r
2507 CEFBS_None, // RETSP_lu6
2508 CEFBS_None, // RETSP_u6
2509 CEFBS_None, // SETCLK_l2r
2510 CEFBS_None, // SETCP_1r
2511 CEFBS_None, // SETC_l2r
2512 CEFBS_None, // SETC_lru6
2513 CEFBS_None, // SETC_ru6
2514 CEFBS_None, // SETDP_1r
2515 CEFBS_None, // SETD_2r
2516 CEFBS_None, // SETEV_1r
2517 CEFBS_None, // SETKEP_0R
2518 CEFBS_None, // SETN_l2r
2519 CEFBS_None, // SETPSC_2r
2520 CEFBS_None, // SETPS_l2r
2521 CEFBS_None, // SETPT_2r
2522 CEFBS_None, // SETRDY_l2r
2523 CEFBS_None, // SETSP_1r
2524 CEFBS_None, // SETSR_branch_lu6
2525 CEFBS_None, // SETSR_branch_u6
2526 CEFBS_None, // SETSR_lu6
2527 CEFBS_None, // SETSR_u6
2528 CEFBS_None, // SETTW_l2r
2529 CEFBS_None, // SETV_1r
2530 CEFBS_None, // SEXT_2r
2531 CEFBS_None, // SEXT_rus
2532 CEFBS_None, // SHL_2rus
2533 CEFBS_None, // SHL_3r
2534 CEFBS_None, // SHR_2rus
2535 CEFBS_None, // SHR_3r
2536 CEFBS_None, // SSYNC_0r
2537 CEFBS_None, // ST16_l3r
2538 CEFBS_None, // ST8_l3r
2539 CEFBS_None, // STET_0R
2540 CEFBS_None, // STSED_0R
2541 CEFBS_None, // STSPC_0R
2542 CEFBS_None, // STSSR_0R
2543 CEFBS_None, // STWDP_lru6
2544 CEFBS_None, // STWDP_ru6
2545 CEFBS_None, // STWSP_lru6
2546 CEFBS_None, // STWSP_ru6
2547 CEFBS_None, // STW_2rus
2548 CEFBS_None, // STW_l3r
2549 CEFBS_None, // SUB_2rus
2550 CEFBS_None, // SUB_3r
2551 CEFBS_None, // SYNCR_1r
2552 CEFBS_None, // TESTCT_2r
2553 CEFBS_None, // TESTLCL_l2r
2554 CEFBS_None, // TESTWCT_2r
2555 CEFBS_None, // TSETMR_2r
2556 CEFBS_None, // TSETR_3r
2557 CEFBS_None, // TSTART_1R
2558 CEFBS_None, // WAITEF_1R
2559 CEFBS_None, // WAITET_1R
2560 CEFBS_None, // WAITEU_0R
2561 CEFBS_None, // XOR_l3r
2562 CEFBS_None, // ZEXT_2r
2563 CEFBS_None, // ZEXT_rus
2564 };
2565
2566 assert(Opcode < 559);
2567 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2568}
2569
2570
2571} // namespace llvm::XCore_MC
2572
2573#endif // GET_COMPUTE_FEATURES
2574
2575#ifdef GET_AVAILABLE_OPCODE_CHECKER
2576#undef GET_AVAILABLE_OPCODE_CHECKER
2577
2578namespace llvm::XCore_MC {
2579
2580bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2581 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2582 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2583 FeatureBitset MissingFeatures =
2584 (AvailableFeatures & RequiredFeatures) ^
2585 RequiredFeatures;
2586 return !MissingFeatures.any();
2587}
2588
2589} // namespace llvm::XCore_MC
2590
2591#endif // GET_AVAILABLE_OPCODE_CHECKER
2592
2593#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2594#undef ENABLE_INSTR_PREDICATE_VERIFIER
2595
2596#include <sstream>
2597
2598namespace llvm::XCore_MC {
2599
2600#ifndef NDEBUG
2601static const char *SubtargetFeatureNames[] = {
2602 nullptr
2603};
2604
2605#endif // NDEBUG
2606
2607void verifyInstructionPredicates(
2608 unsigned Opcode, const FeatureBitset &Features) {
2609#ifndef NDEBUG
2610 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2611 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2612 FeatureBitset MissingFeatures =
2613 (AvailableFeatures & RequiredFeatures) ^
2614 RequiredFeatures;
2615 if (MissingFeatures.any()) {
2616 std::ostringstream Msg;
2617 Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
2618 << " instruction but the ";
2619 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2620 if (MissingFeatures.test(i))
2621 Msg << SubtargetFeatureNames[i] << " ";
2622 Msg << "predicate(s) are not met";
2623 report_fatal_error(Msg.str().c_str());
2624 }
2625#endif // NDEBUG
2626}
2627
2628} // namespace llvm::XCore_MC
2629
2630#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2631
2632