1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::XCore {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 ADJCALLSTACKDOWN = 334, // XCoreInstrInfo.td:356
350 ADJCALLSTACKUP = 335, // XCoreInstrInfo.td:359
351 BR_JT = 336, // XCoreInstrInfo.td:991
352 BR_JT32 = 337, // XCoreInstrInfo.td:996
353 EH_RETURN = 338, // XCoreInstrInfo.td:370
354 FRAME_TO_ARGS_OFFSET = 339, // XCoreInstrInfo.td:365
355 LDAWFI = 340, // XCoreInstrInfo.td:378
356 LDWFI = 341, // XCoreInstrInfo.td:374
357 SELECT_CC = 342, // XCoreInstrInfo.td:389
358 STWFI = 343, // XCoreInstrInfo.td:382
359 ADD_2rus = 344, // XCoreInstrInfo.td:247
360 ADD_3r = 345, // XCoreInstrInfo.td:244
361 ANDNOT_2r = 346, // XCoreInstrInfo.td:797
362 AND_3r = 347, // XCoreInstrInfo.td:408
363 ASHR_l2rus = 348, // XCoreInstrInfo.td:296
364 ASHR_l3r = 349, // XCoreInstrInfo.td:293
365 BAU_1r = 350, // XCoreInstrInfo.td:986
366 BITREV_l2r = 351, // XCoreInstrInfo.td:925
367 BLACP_lu10 = 352, // XCoreInstrInfo.td:746
368 BLACP_u10 = 353, // XCoreInstrInfo.td:744
369 BLAT_lu6 = 354, // XCoreInstrInfo.td:340
370 BLAT_u6 = 355, // XCoreInstrInfo.td:339
371 BLA_1r = 356, // XCoreInstrInfo.td:1025
372 BLRB_lu10 = 357, // XCoreInstrInfo.td:756
373 BLRB_u10 = 358, // XCoreInstrInfo.td:754
374 BLRF_lu10 = 359, // XCoreInstrInfo.td:751
375 BLRF_u10 = 360, // XCoreInstrInfo.td:748
376 BRBF_lru6 = 361, // XCoreInstrInfo.td:318
377 BRBF_ru6 = 362, // XCoreInstrInfo.td:316
378 BRBT_lru6 = 363, // XCoreInstrInfo.td:318
379 BRBT_ru6 = 364, // XCoreInstrInfo.td:316
380 BRBU_lu6 = 365, // XCoreInstrInfo.td:679
381 BRBU_u6 = 366, // XCoreInstrInfo.td:677
382 BRFF_lru6 = 367, // XCoreInstrInfo.td:311
383 BRFF_ru6 = 368, // XCoreInstrInfo.td:309
384 BRFT_lru6 = 369, // XCoreInstrInfo.td:311
385 BRFT_ru6 = 370, // XCoreInstrInfo.td:309
386 BRFU_lu6 = 371, // XCoreInstrInfo.td:683
387 BRFU_u6 = 372, // XCoreInstrInfo.td:681
388 BRU_1r = 373, // XCoreInstrInfo.td:1001
389 BYTEREV_l2r = 374, // XCoreInstrInfo.td:929
390 CHKCT_2r = 375, // XCoreInstrInfo.td:863
391 CHKCT_rus = 376, // XCoreInstrInfo.td:867
392 CLRE_0R = 377, // XCoreInstrInfo.td:1070
393 CLRPT_1R = 378, // XCoreInstrInfo.td:1065
394 CLRSR_branch_lu6 = 379, // XCoreInstrInfo.td:340
395 CLRSR_branch_u6 = 380, // XCoreInstrInfo.td:339
396 CLRSR_lu6 = 381, // XCoreInstrInfo.td:334
397 CLRSR_u6 = 382, // XCoreInstrInfo.td:332
398 CLZ_l2r = 383, // XCoreInstrInfo.td:933
399 CRC8_l4r = 384, // XCoreInstrInfo.td:533
400 CRC_l3r = 385, // XCoreInstrInfo.td:494
401 DCALL_0R = 386, // XCoreInstrInfo.td:1072
402 DENTSP_0R = 387, // XCoreInstrInfo.td:1075
403 DGETREG_1r = 388, // XCoreInstrInfo.td:1048
404 DIVS_l3r = 389, // XCoreInstrInfo.td:485
405 DIVU_l3r = 390, // XCoreInstrInfo.td:486
406 DRESTSP_0R = 391, // XCoreInstrInfo.td:1078
407 DRET_0R = 392, // XCoreInstrInfo.td:1080
408 ECALLF_1r = 393, // XCoreInstrInfo.td:1018
409 ECALLT_1r = 394, // XCoreInstrInfo.td:1013
410 EDU_1r = 395, // XCoreInstrInfo.td:1050
411 EEF_2r = 396, // XCoreInstrInfo.td:915
412 EET_2r = 397, // XCoreInstrInfo.td:918
413 EEU_1r = 398, // XCoreInstrInfo.td:1053
414 ENDIN_2r = 399, // XCoreInstrInfo.td:911
415 ENTSP_lu6 = 400, // XCoreInstrInfo.td:340
416 ENTSP_u6 = 401, // XCoreInstrInfo.td:339
417 EQ_2rus = 402, // XCoreInstrInfo.td:255
418 EQ_3r = 403, // XCoreInstrInfo.td:253
419 EXTDP_lu6 = 404, // XCoreInstrInfo.td:340
420 EXTDP_u6 = 405, // XCoreInstrInfo.td:339
421 EXTSP_lu6 = 406, // XCoreInstrInfo.td:340
422 EXTSP_u6 = 407, // XCoreInstrInfo.td:339
423 FREER_1r = 408, // XCoreInstrInfo.td:1034
424 FREET_0R = 409, // XCoreInstrInfo.td:1082
425 GETD_l2r = 410, // XCoreInstrInfo.td:937
426 GETED_0R = 411, // XCoreInstrInfo.td:1089
427 GETET_0R = 412, // XCoreInstrInfo.td:1093
428 GETID_0R = 413, // XCoreInstrInfo.td:1085
429 GETKEP_0R = 414, // XCoreInstrInfo.td:1097
430 GETKSP_0R = 415, // XCoreInstrInfo.td:1100
431 GETN_l2r = 416, // XCoreInstrInfo.td:940
432 GETPS_l2r = 417, // XCoreInstrInfo.td:951
433 GETR_rus = 418, // XCoreInstrInfo.td:811
434 GETSR_lu6 = 419, // XCoreInstrInfo.td:340
435 GETSR_u6 = 420, // XCoreInstrInfo.td:339
436 GETST_2r = 421, // XCoreInstrInfo.td:887
437 GETTS_2r = 422, // XCoreInstrInfo.td:815
438 INCT_2r = 423, // XCoreInstrInfo.td:845
439 INITCP_2r = 424, // XCoreInstrInfo.td:899
440 INITDP_2r = 425, // XCoreInstrInfo.td:903
441 INITLR_l2r = 426, // XCoreInstrInfo.td:959
442 INITPC_2r = 427, // XCoreInstrInfo.td:895
443 INITSP_2r = 428, // XCoreInstrInfo.td:891
444 INPW_l2rus = 429, // XCoreInstrInfo.td:511
445 INSHR_2r = 430, // XCoreInstrInfo.td:858
446 INT_2r = 431, // XCoreInstrInfo.td:849
447 IN_2r = 432, // XCoreInstrInfo.td:853
448 KCALL_1r = 433, // XCoreInstrInfo.td:1057
449 KCALL_lu6 = 434, // XCoreInstrInfo.td:340
450 KCALL_u6 = 435, // XCoreInstrInfo.td:339
451 KENTSP_lu6 = 436, // XCoreInstrInfo.td:340
452 KENTSP_u6 = 437, // XCoreInstrInfo.td:339
453 KRESTSP_lu6 = 438, // XCoreInstrInfo.td:340
454 KRESTSP_u6 = 439, // XCoreInstrInfo.td:339
455 KRET_0R = 440, // XCoreInstrInfo.td:1105
456 LADD_l5r = 441, // XCoreInstrInfo.td:541
457 LD16S_3r = 442, // XCoreInstrInfo.td:420
458 LD8U_3r = 443, // XCoreInstrInfo.td:424
459 LDA16B_l3r = 444, // XCoreInstrInfo.td:476
460 LDA16F_l3r = 445, // XCoreInstrInfo.td:470
461 LDAPB_lu10 = 446, // XCoreInstrInfo.td:732
462 LDAPB_u10 = 447, // XCoreInstrInfo.td:728
463 LDAPF_lu10 = 448, // XCoreInstrInfo.td:724
464 LDAPF_lu10_ba = 449, // XCoreInstrInfo.td:737
465 LDAPF_u10 = 450, // XCoreInstrInfo.td:722
466 LDAWB_l2rus = 451, // XCoreInstrInfo.td:466
467 LDAWB_l3r = 452, // XCoreInstrInfo.td:459
468 LDAWCP_lu6 = 453, // XCoreInstrInfo.td:692
469 LDAWCP_u6 = 454, // XCoreInstrInfo.td:688
470 LDAWDP_lru6 = 455, // XCoreInstrInfo.td:574
471 LDAWDP_ru6 = 456, // XCoreInstrInfo.td:570
472 LDAWF_l2rus = 457, // XCoreInstrInfo.td:455
473 LDAWF_l3r = 458, // XCoreInstrInfo.td:448
474 LDAWSP_lru6 = 459, // XCoreInstrInfo.td:628
475 LDAWSP_ru6 = 460, // XCoreInstrInfo.td:625
476 LDC_lru6 = 461, // XCoreInstrInfo.td:637
477 LDC_ru6 = 462, // XCoreInstrInfo.td:634
478 LDET_0R = 463, // XCoreInstrInfo.td:1108
479 LDIVU_l5r = 464, // XCoreInstrInfo.td:553
480 LDSED_0R = 465, // XCoreInstrInfo.td:1110
481 LDSPC_0R = 466, // XCoreInstrInfo.td:1112
482 LDSSR_0R = 467, // XCoreInstrInfo.td:1114
483 LDWCP_lru6 = 468, // XCoreInstrInfo.td:598
484 LDWCP_lu10 = 469, // XCoreInstrInfo.td:763
485 LDWCP_ru6 = 470, // XCoreInstrInfo.td:596
486 LDWCP_u10 = 471, // XCoreInstrInfo.td:761
487 LDWDP_lru6 = 472, // XCoreInstrInfo.td:582
488 LDWDP_ru6 = 473, // XCoreInstrInfo.td:579
489 LDWSP_lru6 = 474, // XCoreInstrInfo.td:619
490 LDWSP_ru6 = 475, // XCoreInstrInfo.td:615
491 LDW_2rus = 476, // XCoreInstrInfo.td:416
492 LDW_3r = 477, // XCoreInstrInfo.td:412
493 LMUL_l6r = 478, // XCoreInstrInfo.td:559
494 LSS_3r = 479, // XCoreInstrInfo.td:405
495 LSUB_l5r = 480, // XCoreInstrInfo.td:547
496 LSU_3r = 481, // XCoreInstrInfo.td:406
497 MACCS_l4r = 482, // XCoreInstrInfo.td:526
498 MACCU_l4r = 483, // XCoreInstrInfo.td:521
499 MJOIN_1r = 484, // XCoreInstrInfo.td:981
500 MKMSK_2r = 485, // XCoreInstrInfo.td:807
501 MKMSK_rus = 486, // XCoreInstrInfo.td:804
502 MSYNC_1r = 487, // XCoreInstrInfo.td:978
503 MUL_l3r = 488, // XCoreInstrInfo.td:482
504 NEG = 489, // XCoreInstrInfo.td:771
505 NOT = 490, // XCoreInstrInfo.td:768
506 OR_3r = 491, // XCoreInstrInfo.td:409
507 OUTCT_2r = 492, // XCoreInstrInfo.td:823
508 OUTCT_rus = 493, // XCoreInstrInfo.td:827
509 OUTPW_l2rus = 494, // XCoreInstrInfo.td:515
510 OUTSHR_2r = 495, // XCoreInstrInfo.td:840
511 OUTT_2r = 496, // XCoreInstrInfo.td:831
512 OUT_2r = 497, // XCoreInstrInfo.td:835
513 PEEK_2r = 498, // XCoreInstrInfo.td:907
514 REMS_l3r = 499, // XCoreInstrInfo.td:487
515 REMU_l3r = 500, // XCoreInstrInfo.td:488
516 RETSP_lu6 = 501, // XCoreInstrInfo.td:327
517 RETSP_u6 = 502, // XCoreInstrInfo.td:325
518 SETCLK_l2r = 503, // XCoreInstrInfo.td:963
519 SETCP_1r = 504, // XCoreInstrInfo.td:1010
520 SETC_l2r = 505, // XCoreInstrInfo.td:943
521 SETC_lru6 = 506, // XCoreInstrInfo.td:645
522 SETC_ru6 = 507, // XCoreInstrInfo.td:641
523 SETDP_1r = 508, // XCoreInstrInfo.td:1007
524 SETD_2r = 509, // XCoreInstrInfo.td:879
525 SETEV_1r = 510, // XCoreInstrInfo.td:1043
526 SETKEP_0R = 511, // XCoreInstrInfo.td:1118
527 SETN_l2r = 512, // XCoreInstrInfo.td:967
528 SETPSC_2r = 513, // XCoreInstrInfo.td:883
529 SETPS_l2r = 514, // XCoreInstrInfo.td:955
530 SETPT_2r = 515, // XCoreInstrInfo.td:819
531 SETRDY_l2r = 516, // XCoreInstrInfo.td:970
532 SETSP_1r = 517, // XCoreInstrInfo.td:1004
533 SETSR_branch_lu6 = 518, // XCoreInstrInfo.td:340
534 SETSR_branch_u6 = 519, // XCoreInstrInfo.td:339
535 SETSR_lu6 = 520, // XCoreInstrInfo.td:334
536 SETSR_u6 = 521, // XCoreInstrInfo.td:332
537 SETTW_l2r = 522, // XCoreInstrInfo.td:947
538 SETV_1r = 523, // XCoreInstrInfo.td:1039
539 SEXT_2r = 524, // XCoreInstrInfo.td:781
540 SEXT_rus = 525, // XCoreInstrInfo.td:775
541 SHL_2rus = 526, // XCoreInstrInfo.td:264
542 SHL_3r = 527, // XCoreInstrInfo.td:261
543 SHR_2rus = 528, // XCoreInstrInfo.td:264
544 SHR_3r = 529, // XCoreInstrInfo.td:261
545 SSYNC_0r = 530, // XCoreInstrInfo.td:1120
546 ST16_l3r = 531, // XCoreInstrInfo.td:502
547 ST8_l3r = 532, // XCoreInstrInfo.td:506
548 STET_0R = 533, // XCoreInstrInfo.td:1125
549 STSED_0R = 534, // XCoreInstrInfo.td:1127
550 STSPC_0R = 535, // XCoreInstrInfo.td:1129
551 STSSR_0R = 536, // XCoreInstrInfo.td:1131
552 STWDP_lru6 = 537, // XCoreInstrInfo.td:590
553 STWDP_ru6 = 538, // XCoreInstrInfo.td:587
554 STWSP_lru6 = 539, // XCoreInstrInfo.td:609
555 STWSP_ru6 = 540, // XCoreInstrInfo.td:605
556 STW_2rus = 541, // XCoreInstrInfo.td:434
557 STW_l3r = 542, // XCoreInstrInfo.td:430
558 SUB_2rus = 543, // XCoreInstrInfo.td:247
559 SUB_3r = 544, // XCoreInstrInfo.td:244
560 SYNCR_1r = 545, // XCoreInstrInfo.td:1030
561 TESTCT_2r = 546, // XCoreInstrInfo.td:871
562 TESTLCL_l2r = 547, // XCoreInstrInfo.td:974
563 TESTWCT_2r = 548, // XCoreInstrInfo.td:875
564 TSETMR_2r = 549, // XCoreInstrInfo.td:921
565 TSETR_3r = 550, // XCoreInstrInfo.td:444
566 TSTART_1R = 551, // XCoreInstrInfo.td:1063
567 WAITEF_1R = 552, // XCoreInstrInfo.td:1059
568 WAITET_1R = 553, // XCoreInstrInfo.td:1061
569 WAITEU_0R = 554, // XCoreInstrInfo.td:1136
570 XOR_l3r = 555, // XCoreInstrInfo.td:490
571 ZEXT_2r = 556, // XCoreInstrInfo.td:792
572 ZEXT_rus = 557, // XCoreInstrInfo.td:786
573 INSTRUCTION_LIST_END = 558
574 };
575
576} // namespace llvm::XCore
577
578#endif // GET_INSTRINFO_ENUM
579
580#ifdef GET_INSTRINFO_SCHED_ENUM
581#undef GET_INSTRINFO_SCHED_ENUM
582
583namespace llvm::XCore::Sched {
584
585 enum {
586 NoInstrModel = 0,
587 SCHED_LIST_END = 1
588 };
589
590} // namespace llvm::XCore::Sched
591
592#endif // GET_INSTRINFO_SCHED_ENUM
593
594#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
595
596namespace llvm {
597
598struct XCoreInstrTable {
599 MCInstrDesc Insts[558];
600 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
601 MCPhysReg ImplicitOps[11];
602 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
603 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
604 MCOperandInfo OperandInfo[209];
605};
606} // namespace llvm
607
608#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
609
610#ifdef GET_INSTRINFO_MC_DESC
611#undef GET_INSTRINFO_MC_DESC
612
613namespace llvm {
614
615static_assert((sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
616static constexpr unsigned XCoreOpInfoBase = (sizeof XCoreInstrTable::ImplicitOps + sizeof XCoreInstrTable::Padding) / sizeof(MCOperandInfo);
617
618extern const XCoreInstrTable XCoreDescs = {
619 {
620 { 557, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_rus
621 { 556, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT_2r
622 { 555, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_l3r
623 { 554, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEU_0R
624 { 553, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITET_1R
625 { 552, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WAITEF_1R
626 { 551, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSTART_1R
627 { 550, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETR_3r
628 { 549, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TSETMR_2r
629 { 548, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTWCT_2r
630 { 547, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTLCL_l2r
631 { 546, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TESTCT_2r
632 { 545, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SYNCR_1r
633 { 544, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_3r
634 { 543, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_2rus
635 { 542, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_l3r
636 { 541, 3, 0, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_2rus
637 { 540, 2, 0, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_ru6
638 { 539, 2, 0, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWSP_lru6
639 { 538, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_ru6
640 { 537, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWDP_lru6
641 { 536, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSSR_0R
642 { 535, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSPC_0R
643 { 534, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSED_0R
644 { 533, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STET_0R
645 { 532, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST8_l3r
646 { 531, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ST16_l3r
647 { 530, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SSYNC_0r
648 { 529, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_3r
649 { 528, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_2rus
650 { 527, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_3r
651 { 526, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_2rus
652 { 525, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 201, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_rus
653 { 524, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT_2r
654 { 523, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETV_1r
655 { 522, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETTW_l2r
656 { 521, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_u6
657 { 520, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_lu6
658 { 519, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_u6
659 { 518, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSR_branch_lu6
660 { 517, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 28, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETSP_1r
661 { 516, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETRDY_l2r
662 { 515, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPT_2r
663 { 514, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPS_l2r
664 { 513, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETPSC_2r
665 { 512, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETN_l2r
666 { 511, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETKEP_0R
667 { 510, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 28, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETEV_1r
668 { 509, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETD_2r
669 { 508, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETDP_1r
670 { 507, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_ru6
671 { 506, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_lru6
672 { 505, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETC_l2r
673 { 504, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCP_1r
674 { 503, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SETCLK_l2r
675 { 502, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_u6
676 { 501, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETSP_lu6
677 { 500, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMU_l3r
678 { 499, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REMS_l3r
679 { 498, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PEEK_2r
680 { 497, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUT_2r
681 { 496, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTT_2r
682 { 495, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTSHR_2r
683 { 494, 3, 0, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTPW_l2rus
684 { 493, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_rus
685 { 492, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTCT_2r
686 { 491, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_3r
687 { 490, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
688 { 489, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG
689 { 488, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_l3r
690 { 487, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MSYNC_1r
691 { 486, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_rus
692 { 485, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MKMSK_2r
693 { 484, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MJOIN_1r
694 { 483, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCU_l4r
695 { 482, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 195, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MACCS_l4r
696 { 481, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSU_3r
697 { 480, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSUB_l5r
698 { 479, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSS_3r
699 { 478, 6, 2, 4, 0, 0, 0, XCoreOpInfoBase + 189, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LMUL_l6r
700 { 477, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_3r
701 { 476, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_2rus
702 { 475, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_ru6
703 { 474, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSP_lru6
704 { 473, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_ru6
705 { 472, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWDP_lru6
706 { 471, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_u10
707 { 470, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_ru6
708 { 469, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lu10
709 { 468, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWCP_lru6
710 { 467, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSSR_0R
711 { 466, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSPC_0R
712 { 465, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSED_0R
713 { 464, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIVU_l5r
714 { 463, 0, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDET_0R
715 { 462, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_ru6
716 { 461, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDC_lru6
717 { 460, 2, 1, 2, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_ru6
718 { 459, 2, 1, 4, 0, 1, 0, XCoreOpInfoBase + 187, 10, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWSP_lru6
719 { 458, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l3r
720 { 457, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWF_l2rus
721 { 456, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_ru6
722 { 455, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 187, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWDP_lru6
723 { 454, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_u6
724 { 453, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWCP_lu6
725 { 452, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l3r
726 { 451, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWB_l2rus
727 { 450, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_u10
728 { 449, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10_ba
729 { 448, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPF_lu10
730 { 447, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_u10
731 { 446, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 0, 9, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAPB_lu10
732 { 445, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16F_l3r
733 { 444, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDA16B_l3r
734 { 443, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD8U_3r
735 { 442, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD16S_3r
736 { 441, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 182, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LADD_l5r
737 { 440, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRET_0R
738 { 439, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_u6
739 { 438, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KRESTSP_lu6
740 { 437, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_u6
741 { 436, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KENTSP_lu6
742 { 435, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_u6
743 { 434, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_lu6
744 { 433, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KCALL_1r
745 { 432, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IN_2r
746 { 431, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INT_2r
747 { 430, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSHR_2r
748 { 429, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INPW_l2rus
749 { 428, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITSP_2r
750 { 427, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITPC_2r
751 { 426, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITLR_l2r
752 { 425, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITDP_2r
753 { 424, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INITCP_2r
754 { 423, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INCT_2r
755 { 422, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETTS_2r
756 { 421, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETST_2r
757 { 420, 1, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_u6
758 { 419, 1, 0, 4, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETSR_lu6
759 { 418, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETR_rus
760 { 417, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETPS_l2r
761 { 416, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETN_l2r
762 { 415, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKSP_0R
763 { 414, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETKEP_0R
764 { 413, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETID_0R
765 { 412, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETET_0R
766 { 411, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETED_0R
767 { 410, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GETD_l2r
768 { 409, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREET_0R
769 { 408, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FREER_1r
770 { 407, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_u6
771 { 406, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTSP_lu6
772 { 405, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_u6
773 { 404, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTDP_lu6
774 { 403, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_3r
775 { 402, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_2rus
776 { 401, 1, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_u6
777 { 400, 1, 0, 4, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENTSP_lu6
778 { 399, 2, 1, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ENDIN_2r
779 { 398, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEU_1r
780 { 397, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EET_2r
781 { 396, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EEF_2r
782 { 395, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EDU_1r
783 { 394, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLT_1r
784 { 393, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ECALLF_1r
785 { 392, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRET_0R
786 { 391, 0, 0, 2, 0, 0, 1, XCoreOpInfoBase + 1, 10, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DRESTSP_0R
787 { 390, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVU_l3r
788 { 389, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIVS_l3r
789 { 388, 1, 1, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DGETREG_1r
790 { 387, 0, 0, 2, 0, 1, 1, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DENTSP_0R
791 { 386, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DCALL_0R
792 { 385, 4, 1, 4, 0, 0, 0, XCoreOpInfoBase + 178, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC_l3r
793 { 384, 5, 2, 4, 0, 0, 0, XCoreOpInfoBase + 173, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CRC8_l4r
794 { 383, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_l2r
795 { 382, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_u6
796 { 381, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_lu6
797 { 380, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_u6
798 { 379, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRSR_branch_lu6
799 { 378, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRPT_1R
800 { 377, 0, 0, 2, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLRE_0R
801 { 376, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 171, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_rus
802 { 375, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CHKCT_2r
803 { 374, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BYTEREV_l2r
804 { 373, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRU_1r
805 { 372, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_u6
806 { 371, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFU_lu6
807 { 370, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_ru6
808 { 369, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFT_lru6
809 { 368, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_ru6
810 { 367, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRFF_lru6
811 { 366, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_u6
812 { 365, 1, 0, 4, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBU_lu6
813 { 364, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_ru6
814 { 363, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBT_lru6
815 { 362, 2, 0, 2, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_ru6
816 { 361, 2, 0, 4, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBF_lru6
817 { 360, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_u10
818 { 359, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRF_lu10
819 { 358, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_u10
820 { 357, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 0, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLRB_lu10
821 { 356, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 28, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLA_1r
822 { 355, 1, 0, 2, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_u6
823 { 354, 1, 0, 4, 0, 1, 0, XCoreOpInfoBase + 1, 9, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLAT_lu6
824 { 353, 1, 0, 2, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_u10
825 { 352, 1, 0, 4, 0, 1, 6, XCoreOpInfoBase + 1, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLACP_lu10
826 { 351, 2, 1, 4, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITREV_l2r
827 { 350, 1, 0, 2, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BAU_1r
828 { 349, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l3r
829 { 348, 3, 1, 4, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASHR_l2rus
830 { 347, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_3r
831 { 346, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 168, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_2r
832 { 345, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 165, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_3r
833 { 344, 3, 1, 2, 0, 0, 0, XCoreOpInfoBase + 162, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_2rus
834 { 343, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWFI
835 { 342, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_CC
836 { 341, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWFI
837 { 340, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDAWFI
838 { 339, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FRAME_TO_ARGS_OFFSET
839 { 338, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_RETURN
840 { 337, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT32
841 { 336, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_JT
842 { 335, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
843 { 334, 2, 0, 0, 0, 1, 1, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
844 { 333, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
845 { 332, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
846 { 331, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
847 { 330, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
848 { 329, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
849 { 328, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
850 { 327, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
851 { 326, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
852 { 325, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
853 { 324, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
854 { 323, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
855 { 322, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
856 { 321, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
857 { 320, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
858 { 319, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
859 { 318, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
860 { 317, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
861 { 316, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
862 { 315, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
863 { 314, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
864 { 313, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
865 { 312, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
866 { 311, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
867 { 310, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
868 { 309, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
869 { 308, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
870 { 307, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
871 { 306, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
872 { 305, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
873 { 304, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
874 { 303, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
875 { 302, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
876 { 301, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
877 { 300, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
878 { 299, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
879 { 298, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
880 { 297, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
881 { 296, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
882 { 295, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
883 { 294, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
884 { 293, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
885 { 292, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
886 { 291, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
887 { 290, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
888 { 289, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
889 { 288, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
890 { 287, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
891 { 286, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
892 { 285, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
893 { 284, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
894 { 283, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
895 { 282, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
896 { 281, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
897 { 280, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
898 { 279, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
899 { 278, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
900 { 277, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
901 { 276, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
902 { 275, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
903 { 274, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
904 { 273, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
905 { 272, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
906 { 271, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
907 { 270, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
908 { 269, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
909 { 268, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
910 { 267, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
911 { 266, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
912 { 265, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
913 { 264, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
914 { 263, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
915 { 262, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
916 { 261, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
917 { 260, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
918 { 259, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
919 { 258, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
920 { 257, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
921 { 256, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
922 { 255, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
923 { 254, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
924 { 253, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
925 { 252, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
926 { 251, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
927 { 250, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
928 { 249, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
929 { 248, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
930 { 247, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
931 { 246, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
932 { 245, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
933 { 244, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
934 { 243, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
935 { 242, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
936 { 241, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
937 { 240, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
938 { 239, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
939 { 238, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
940 { 237, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
941 { 236, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
942 { 235, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
943 { 234, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
944 { 233, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
945 { 232, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
946 { 231, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
947 { 230, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
948 { 229, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
949 { 228, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
950 { 227, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
951 { 226, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
952 { 225, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
953 { 224, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
954 { 223, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
955 { 222, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
956 { 221, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
957 { 220, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
958 { 219, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
959 { 218, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
960 { 217, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
961 { 216, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
962 { 215, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
963 { 214, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
964 { 213, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
965 { 212, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
966 { 211, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
967 { 210, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
968 { 209, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
969 { 208, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
970 { 207, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
971 { 206, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
972 { 205, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
973 { 204, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
974 { 203, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
975 { 202, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
976 { 201, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
977 { 200, 3, 2, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
978 { 199, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
979 { 198, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
980 { 197, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
981 { 196, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
982 { 195, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
983 { 194, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
984 { 193, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
985 { 192, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
986 { 191, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
987 { 190, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
988 { 189, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
989 { 188, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
990 { 187, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
991 { 186, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
992 { 185, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
993 { 184, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
994 { 183, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
995 { 182, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
996 { 181, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
997 { 180, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
998 { 179, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
999 { 178, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1000 { 177, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1001 { 176, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1002 { 175, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1003 { 174, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1004 { 173, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1005 { 172, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1006 { 171, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1007 { 170, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1008 { 169, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1009 { 168, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1010 { 167, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1011 { 166, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1012 { 165, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1013 { 164, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1014 { 163, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1015 { 162, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1016 { 161, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1017 { 160, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1018 { 159, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1019 { 158, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1020 { 157, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1021 { 156, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1022 { 155, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1023 { 154, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1024 { 153, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1025 { 152, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1026 { 151, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1027 { 150, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1028 { 149, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1029 { 148, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1030 { 147, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1031 { 146, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1032 { 145, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1033 { 144, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1034 { 143, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1035 { 142, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1036 { 141, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1037 { 140, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1038 { 139, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1039 { 138, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1040 { 137, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1041 { 136, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1042 { 135, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1043 { 134, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1044 { 133, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1045 { 132, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1046 { 131, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1047 { 130, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1048 { 129, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1049 { 128, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1050 { 127, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1051 { 126, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1052 { 125, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1053 { 124, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1054 { 123, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1055 { 122, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1056 { 121, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1057 { 120, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1058 { 119, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1059 { 118, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1060 { 117, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1061 { 116, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1062 { 115, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1063 { 114, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1064 { 113, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1065 { 112, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1066 { 111, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1067 { 110, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1068 { 109, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1069 { 108, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1070 { 107, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1071 { 106, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1072 { 105, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1073 { 104, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1074 { 103, 5, 2, 0, 0, 0, 0, XCoreOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1075 { 102, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1076 { 101, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1077 { 100, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1078 { 99, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1079 { 98, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1080 { 97, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1081 { 96, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1082 { 95, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1083 { 94, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1084 { 93, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1085 { 92, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1086 { 91, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1087 { 90, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1088 { 89, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1089 { 88, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1090 { 87, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1091 { 86, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1092 { 85, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1093 { 84, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1094 { 83, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1095 { 82, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1096 { 81, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1097 { 80, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1098 { 79, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1099 { 78, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1100 { 77, 5, 1, 0, 0, 0, 0, XCoreOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1101 { 76, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1102 { 75, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1103 { 74, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1104 { 73, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1105 { 72, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1106 { 71, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1107 { 70, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1108 { 69, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1109 { 68, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1110 { 67, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1111 { 66, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1112 { 65, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1113 { 64, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1114 { 63, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1115 { 62, 4, 2, 0, 0, 0, 0, XCoreOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1116 { 61, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1117 { 60, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1118 { 59, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1119 { 58, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1120 { 57, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1121 { 56, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1122 { 55, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1123 { 54, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1124 { 53, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1125 { 52, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1126 { 51, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1127 { 50, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1128 { 49, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1129 { 48, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1130 { 47, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1131 { 46, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1132 { 45, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1133 { 44, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1134 { 43, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1135 { 42, 3, 0, 0, 0, 0, 0, XCoreOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14716
1136 { 41, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14715
1137 { 40, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1138 { 39, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1139 { 38, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1140 { 37, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1141 { 36, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1142 { 35, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1143 { 34, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1144 { 33, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1145 { 32, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14714
1146 { 31, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1147 { 30, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14348
1148 { 29, 6, 1, 0, 0, 0, 0, XCoreOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1149 { 28, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1150 { 27, 2, 0, 0, 0, 0, 0, XCoreOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1151 { 26, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1152 { 25, 4, 0, 0, 0, 0, 0, XCoreOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1153 { 24, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1154 { 23, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1155 { 22, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1156 { 21, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1157 { 20, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1158 { 19, 2, 1, 0, 0, 0, 0, XCoreOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1159 { 18, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1160 { 17, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1161 { 16, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1162 { 15, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1163 { 14, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1164 { 13, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1165 { 12, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1166 { 11, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1167 { 10, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1168 { 9, 4, 1, 0, 0, 0, 0, XCoreOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1169 { 8, 3, 1, 0, 0, 0, 0, XCoreOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1170 { 7, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1171 { 6, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1172 { 5, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1173 { 4, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1174 { 3, 1, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1175 { 2, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1176 { 1, 0, 0, 0, 0, 0, 0, XCoreOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1177 { 0, 1, 1, 0, 0, 0, 0, XCoreOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1178 }, {
1179 /* 0 */
1180 /* 0 */ XCore::SP, XCore::SP,
1181 /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
1182 /* 9 */ XCore::R11,
1183 /* 10 */ XCore::SP,
1184 }, {
1185 0
1186 }, {
1187 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1188 /* 1 */
1189 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1190 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1191 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1192 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1193 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1194 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1195 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1196 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1197 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1198 /* 28 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1199 /* 29 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1200 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1201 /* 34 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1202 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1203 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1204 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1205 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1206 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1207 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1208 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1209 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1210 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1211 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1212 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1213 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1214 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1215 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1216 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1217 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1218 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1219 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1220 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1221 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1222 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1223 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1224 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1225 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1226 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1227 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1228 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1229 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1230 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1231 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1232 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1233 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1234 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1235 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1236 /* 153 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1237 /* 155 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1238 /* 158 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1239 /* 162 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1240 /* 165 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1241 /* 168 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1242 /* 171 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1243 /* 173 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1244 /* 178 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1245 /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1246 /* 187 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1247 /* 189 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1248 /* 195 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1249 /* 201 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1250 /* 204 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1251 /* 206 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1252 }
1253};
1254
1255
1256#ifdef __GNUC__
1257#pragma GCC diagnostic push
1258#pragma GCC diagnostic ignored "-Woverlength-strings"
1259#endif
1260extern const char XCoreInstrNameData[] = {
1261 /* 0 */ "G_FLOG10\000"
1262 /* 9 */ "G_FEXP10\000"
1263 /* 18 */ "LDAPB_u10\000"
1264 /* 28 */ "BLRB_u10\000"
1265 /* 37 */ "LDAPF_u10\000"
1266 /* 47 */ "BLRF_u10\000"
1267 /* 56 */ "BLACP_u10\000"
1268 /* 66 */ "LDWCP_u10\000"
1269 /* 76 */ "LDAPB_lu10\000"
1270 /* 87 */ "BLRB_lu10\000"
1271 /* 97 */ "LDAPF_lu10\000"
1272 /* 108 */ "BLRF_lu10\000"
1273 /* 118 */ "BLACP_lu10\000"
1274 /* 129 */ "LDWCP_lu10\000"
1275 /* 140 */ "BR_JT32\000"
1276 /* 148 */ "G_FLOG2\000"
1277 /* 156 */ "G_FATAN2\000"
1278 /* 165 */ "G_FEXP2\000"
1279 /* 173 */ "KCALL_u6\000"
1280 /* 182 */ "LDAWCP_u6\000"
1281 /* 192 */ "EXTDP_u6\000"
1282 /* 201 */ "RETSP_u6\000"
1283 /* 210 */ "KENTSP_u6\000"
1284 /* 220 */ "KRESTSP_u6\000"
1285 /* 231 */ "EXTSP_u6\000"
1286 /* 240 */ "CLRSR_u6\000"
1287 /* 249 */ "GETSR_u6\000"
1288 /* 258 */ "SETSR_u6\000"
1289 /* 267 */ "BLAT_u6\000"
1290 /* 275 */ "BRBU_u6\000"
1291 /* 283 */ "BRFU_u6\000"
1292 /* 291 */ "CLRSR_branch_u6\000"
1293 /* 307 */ "SETSR_branch_u6\000"
1294 /* 323 */ "KCALL_lu6\000"
1295 /* 333 */ "LDAWCP_lu6\000"
1296 /* 344 */ "EXTDP_lu6\000"
1297 /* 354 */ "RETSP_lu6\000"
1298 /* 364 */ "KENTSP_lu6\000"
1299 /* 375 */ "KRESTSP_lu6\000"
1300 /* 387 */ "EXTSP_lu6\000"
1301 /* 397 */ "CLRSR_lu6\000"
1302 /* 407 */ "GETSR_lu6\000"
1303 /* 417 */ "SETSR_lu6\000"
1304 /* 427 */ "BLAT_lu6\000"
1305 /* 436 */ "BRBU_lu6\000"
1306 /* 445 */ "BRFU_lu6\000"
1307 /* 454 */ "CLRSR_branch_lu6\000"
1308 /* 471 */ "SETSR_branch_lu6\000"
1309 /* 488 */ "LDC_ru6\000"
1310 /* 496 */ "SETC_ru6\000"
1311 /* 505 */ "BRBF_ru6\000"
1312 /* 514 */ "BRFF_ru6\000"
1313 /* 523 */ "LDWCP_ru6\000"
1314 /* 533 */ "LDAWDP_ru6\000"
1315 /* 544 */ "LDWDP_ru6\000"
1316 /* 554 */ "STWDP_ru6\000"
1317 /* 564 */ "LDAWSP_ru6\000"
1318 /* 575 */ "LDWSP_ru6\000"
1319 /* 585 */ "STWSP_ru6\000"
1320 /* 595 */ "BRBT_ru6\000"
1321 /* 604 */ "BRFT_ru6\000"
1322 /* 613 */ "LDC_lru6\000"
1323 /* 622 */ "SETC_lru6\000"
1324 /* 632 */ "BRBF_lru6\000"
1325 /* 642 */ "BRFF_lru6\000"
1326 /* 652 */ "LDWCP_lru6\000"
1327 /* 663 */ "LDAWDP_lru6\000"
1328 /* 675 */ "LDWDP_lru6\000"
1329 /* 686 */ "STWDP_lru6\000"
1330 /* 697 */ "LDAWSP_lru6\000"
1331 /* 709 */ "LDWSP_lru6\000"
1332 /* 720 */ "STWSP_lru6\000"
1333 /* 731 */ "BRBT_lru6\000"
1334 /* 741 */ "BRFT_lru6\000"
1335 /* 751 */ "G_FMA\000"
1336 /* 757 */ "G_STRICT_FMA\000"
1337 /* 770 */ "G_FSUB\000"
1338 /* 777 */ "G_STRICT_FSUB\000"
1339 /* 791 */ "G_ATOMICRMW_FSUB\000"
1340 /* 808 */ "G_SUB\000"
1341 /* 814 */ "G_ATOMICRMW_SUB\000"
1342 /* 830 */ "SELECT_CC\000"
1343 /* 840 */ "G_INTRINSIC\000"
1344 /* 852 */ "G_FPTRUNC\000"
1345 /* 862 */ "G_INTRINSIC_TRUNC\000"
1346 /* 880 */ "G_TRUNC\000"
1347 /* 888 */ "G_BUILD_VECTOR_TRUNC\000"
1348 /* 909 */ "G_DYN_STACKALLOC\000"
1349 /* 926 */ "G_FMAD\000"
1350 /* 933 */ "G_FPEXTLOAD\000"
1351 /* 945 */ "G_INDEXED_SEXTLOAD\000"
1352 /* 964 */ "G_SEXTLOAD\000"
1353 /* 975 */ "G_INDEXED_ZEXTLOAD\000"
1354 /* 994 */ "G_ZEXTLOAD\000"
1355 /* 1005 */ "G_INDEXED_LOAD\000"
1356 /* 1020 */ "G_LOAD\000"
1357 /* 1027 */ "G_VECREDUCE_FADD\000"
1358 /* 1044 */ "G_FADD\000"
1359 /* 1051 */ "G_VECREDUCE_SEQ_FADD\000"
1360 /* 1072 */ "G_STRICT_FADD\000"
1361 /* 1086 */ "G_ATOMICRMW_FADD\000"
1362 /* 1103 */ "G_VECREDUCE_ADD\000"
1363 /* 1119 */ "G_ADD\000"
1364 /* 1125 */ "G_PTR_ADD\000"
1365 /* 1135 */ "G_ATOMICRMW_ADD\000"
1366 /* 1151 */ "G_ATOMICRMW_NAND\000"
1367 /* 1168 */ "G_VECREDUCE_AND\000"
1368 /* 1184 */ "G_AND\000"
1369 /* 1190 */ "G_ATOMICRMW_AND\000"
1370 /* 1206 */ "LIFETIME_END\000"
1371 /* 1219 */ "G_BRCOND\000"
1372 /* 1228 */ "G_ATOMICRMW_USUB_COND\000"
1373 /* 1250 */ "G_LLROUND\000"
1374 /* 1260 */ "G_LROUND\000"
1375 /* 1269 */ "G_INTRINSIC_ROUND\000"
1376 /* 1287 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1377 /* 1313 */ "LOAD_STACK_GUARD\000"
1378 /* 1330 */ "PSEUDO_PROBE\000"
1379 /* 1343 */ "G_SSUBE\000"
1380 /* 1351 */ "G_USUBE\000"
1381 /* 1359 */ "G_FENCE\000"
1382 /* 1367 */ "ARITH_FENCE\000"
1383 /* 1379 */ "REG_SEQUENCE\000"
1384 /* 1392 */ "G_SADDE\000"
1385 /* 1400 */ "G_UADDE\000"
1386 /* 1408 */ "G_GET_FPMODE\000"
1387 /* 1421 */ "G_RESET_FPMODE\000"
1388 /* 1436 */ "G_SET_FPMODE\000"
1389 /* 1449 */ "G_FMINNUM_IEEE\000"
1390 /* 1464 */ "G_FMAXNUM_IEEE\000"
1391 /* 1479 */ "G_VSCALE\000"
1392 /* 1488 */ "G_JUMP_TABLE\000"
1393 /* 1501 */ "BUNDLE\000"
1394 /* 1508 */ "G_MEMSET_INLINE\000"
1395 /* 1524 */ "G_MEMCPY_INLINE\000"
1396 /* 1540 */ "RELOC_NONE\000"
1397 /* 1551 */ "LOCAL_ESCAPE\000"
1398 /* 1564 */ "G_FPTRUNCSTORE\000"
1399 /* 1579 */ "G_STACKRESTORE\000"
1400 /* 1594 */ "G_INDEXED_STORE\000"
1401 /* 1610 */ "G_STORE\000"
1402 /* 1618 */ "G_BITREVERSE\000"
1403 /* 1631 */ "FAKE_USE\000"
1404 /* 1640 */ "DBG_VALUE\000"
1405 /* 1650 */ "G_GLOBAL_VALUE\000"
1406 /* 1665 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1407 /* 1688 */ "CONVERGENCECTRL_GLUE\000"
1408 /* 1709 */ "G_STACKSAVE\000"
1409 /* 1721 */ "G_MEMMOVE\000"
1410 /* 1731 */ "G_FREEZE\000"
1411 /* 1740 */ "G_FCANONICALIZE\000"
1412 /* 1756 */ "G_FMODF\000"
1413 /* 1764 */ "INIT_UNDEF\000"
1414 /* 1775 */ "G_IMPLICIT_DEF\000"
1415 /* 1790 */ "DBG_INSTR_REF\000"
1416 /* 1804 */ "G_FNEG\000"
1417 /* 1811 */ "EXTRACT_SUBREG\000"
1418 /* 1826 */ "INSERT_SUBREG\000"
1419 /* 1840 */ "G_SEXT_INREG\000"
1420 /* 1853 */ "SUBREG_TO_REG\000"
1421 /* 1867 */ "G_ATOMIC_CMPXCHG\000"
1422 /* 1884 */ "G_ATOMICRMW_XCHG\000"
1423 /* 1901 */ "G_GET_ROUNDING\000"
1424 /* 1916 */ "G_SET_ROUNDING\000"
1425 /* 1931 */ "G_FLOG\000"
1426 /* 1938 */ "G_VAARG\000"
1427 /* 1946 */ "PREALLOCATED_ARG\000"
1428 /* 1963 */ "G_PREFETCH\000"
1429 /* 1974 */ "G_CLMULH\000"
1430 /* 1983 */ "G_SMULH\000"
1431 /* 1991 */ "G_UMULH\000"
1432 /* 1999 */ "G_FTANH\000"
1433 /* 2007 */ "G_FSINH\000"
1434 /* 2015 */ "G_FCOSH\000"
1435 /* 2023 */ "LDAWFI\000"
1436 /* 2030 */ "LDWFI\000"
1437 /* 2036 */ "STWFI\000"
1438 /* 2042 */ "DBG_PHI\000"
1439 /* 2050 */ "G_FPTOSI\000"
1440 /* 2059 */ "G_FPTOUI\000"
1441 /* 2068 */ "G_FPOWI\000"
1442 /* 2076 */ "COPY_LANEMASK\000"
1443 /* 2090 */ "G_PTRMASK\000"
1444 /* 2100 */ "GC_LABEL\000"
1445 /* 2109 */ "DBG_LABEL\000"
1446 /* 2119 */ "EH_LABEL\000"
1447 /* 2128 */ "ANNOTATION_LABEL\000"
1448 /* 2145 */ "ICALL_BRANCH_FUNNEL\000"
1449 /* 2165 */ "G_FSHL\000"
1450 /* 2172 */ "G_SHL\000"
1451 /* 2178 */ "G_FCEIL\000"
1452 /* 2186 */ "G_SAVGCEIL\000"
1453 /* 2197 */ "G_UAVGCEIL\000"
1454 /* 2208 */ "PATCHABLE_TAIL_CALL\000"
1455 /* 2228 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1456 /* 2255 */ "PATCHABLE_EVENT_CALL\000"
1457 /* 2276 */ "FENTRY_CALL\000"
1458 /* 2288 */ "KILL\000"
1459 /* 2293 */ "G_CONSTANT_POOL\000"
1460 /* 2309 */ "G_ROTL\000"
1461 /* 2316 */ "G_VECREDUCE_FMUL\000"
1462 /* 2333 */ "G_FMUL\000"
1463 /* 2340 */ "G_VECREDUCE_SEQ_FMUL\000"
1464 /* 2361 */ "G_STRICT_FMUL\000"
1465 /* 2375 */ "G_CLMUL\000"
1466 /* 2383 */ "G_VECREDUCE_MUL\000"
1467 /* 2399 */ "G_MUL\000"
1468 /* 2405 */ "G_FREM\000"
1469 /* 2412 */ "G_STRICT_FREM\000"
1470 /* 2426 */ "G_SREM\000"
1471 /* 2433 */ "G_UREM\000"
1472 /* 2440 */ "G_SDIVREM\000"
1473 /* 2450 */ "G_UDIVREM\000"
1474 /* 2460 */ "INLINEASM\000"
1475 /* 2470 */ "G_VECREDUCE_FMINIMUM\000"
1476 /* 2491 */ "G_FMINIMUM\000"
1477 /* 2502 */ "G_ATOMICRMW_FMINIMUM\000"
1478 /* 2523 */ "G_VECREDUCE_FMAXIMUM\000"
1479 /* 2544 */ "G_FMAXIMUM\000"
1480 /* 2555 */ "G_ATOMICRMW_FMAXIMUM\000"
1481 /* 2576 */ "G_VECREDUCE_FMINIMUMNUM\000"
1482 /* 2600 */ "G_FMINIMUMNUM\000"
1483 /* 2614 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1484 /* 2638 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1485 /* 2662 */ "G_FMAXIMUMNUM\000"
1486 /* 2676 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1487 /* 2700 */ "G_FMINNUM\000"
1488 /* 2710 */ "G_FMAXNUM\000"
1489 /* 2720 */ "G_FATAN\000"
1490 /* 2728 */ "G_FTAN\000"
1491 /* 2735 */ "G_INTRINSIC_ROUNDEVEN\000"
1492 /* 2757 */ "G_ASSERT_ALIGN\000"
1493 /* 2772 */ "G_FCOPYSIGN\000"
1494 /* 2784 */ "G_VECREDUCE_FMIN\000"
1495 /* 2801 */ "G_ATOMICRMW_FMIN\000"
1496 /* 2818 */ "G_VECREDUCE_SMIN\000"
1497 /* 2835 */ "G_SMIN\000"
1498 /* 2842 */ "G_VECREDUCE_UMIN\000"
1499 /* 2859 */ "G_UMIN\000"
1500 /* 2866 */ "G_ATOMICRMW_UMIN\000"
1501 /* 2883 */ "G_ATOMICRMW_MIN\000"
1502 /* 2899 */ "G_FASIN\000"
1503 /* 2907 */ "G_FSIN\000"
1504 /* 2914 */ "CFI_INSTRUCTION\000"
1505 /* 2930 */ "G_CTLZ_ZERO_POISON\000"
1506 /* 2949 */ "G_CTTZ_ZERO_POISON\000"
1507 /* 2968 */ "EH_RETURN\000"
1508 /* 2978 */ "ADJCALLSTACKDOWN\000"
1509 /* 2995 */ "G_SSUBO\000"
1510 /* 3003 */ "G_USUBO\000"
1511 /* 3011 */ "G_SADDO\000"
1512 /* 3019 */ "G_UADDO\000"
1513 /* 3027 */ "JUMP_TABLE_DEBUG_INFO\000"
1514 /* 3049 */ "G_SMULO\000"
1515 /* 3057 */ "G_UMULO\000"
1516 /* 3065 */ "G_BZERO\000"
1517 /* 3073 */ "STACKMAP\000"
1518 /* 3082 */ "G_DEBUGTRAP\000"
1519 /* 3094 */ "G_UBSANTRAP\000"
1520 /* 3106 */ "G_TRAP\000"
1521 /* 3113 */ "G_ATOMICRMW_UDEC_WRAP\000"
1522 /* 3135 */ "G_ATOMICRMW_UINC_WRAP\000"
1523 /* 3157 */ "G_BSWAP\000"
1524 /* 3165 */ "G_SITOFP\000"
1525 /* 3174 */ "G_UITOFP\000"
1526 /* 3183 */ "G_FCMP\000"
1527 /* 3190 */ "G_STRICT_FCMP\000"
1528 /* 3204 */ "G_ICMP\000"
1529 /* 3211 */ "G_SCMP\000"
1530 /* 3218 */ "G_UCMP\000"
1531 /* 3225 */ "CONVERGENCECTRL_LOOP\000"
1532 /* 3246 */ "G_CTPOP\000"
1533 /* 3254 */ "PATCHABLE_OP\000"
1534 /* 3267 */ "FAULTING_OP\000"
1535 /* 3279 */ "ADJCALLSTACKUP\000"
1536 /* 3294 */ "PREALLOCATED_SETUP\000"
1537 /* 3313 */ "G_FLDEXP\000"
1538 /* 3322 */ "G_STRICT_FLDEXP\000"
1539 /* 3338 */ "G_FEXP\000"
1540 /* 3345 */ "G_FFREXP\000"
1541 /* 3354 */ "LDSPC_0R\000"
1542 /* 3363 */ "STSPC_0R\000"
1543 /* 3372 */ "LDSED_0R\000"
1544 /* 3381 */ "STSED_0R\000"
1545 /* 3390 */ "GETED_0R\000"
1546 /* 3399 */ "GETID_0R\000"
1547 /* 3408 */ "CLRE_0R\000"
1548 /* 3416 */ "DCALL_0R\000"
1549 /* 3425 */ "GETKEP_0R\000"
1550 /* 3435 */ "SETKEP_0R\000"
1551 /* 3445 */ "GETKSP_0R\000"
1552 /* 3455 */ "DENTSP_0R\000"
1553 /* 3465 */ "DRESTSP_0R\000"
1554 /* 3476 */ "LDSSR_0R\000"
1555 /* 3485 */ "STSSR_0R\000"
1556 /* 3494 */ "LDET_0R\000"
1557 /* 3502 */ "FREET_0R\000"
1558 /* 3511 */ "DRET_0R\000"
1559 /* 3519 */ "KRET_0R\000"
1560 /* 3527 */ "GETET_0R\000"
1561 /* 3536 */ "STET_0R\000"
1562 /* 3544 */ "WAITEU_0R\000"
1563 /* 3554 */ "WAITEF_1R\000"
1564 /* 3564 */ "WAITET_1R\000"
1565 /* 3574 */ "CLRPT_1R\000"
1566 /* 3583 */ "TSTART_1R\000"
1567 /* 3593 */ "G_BR\000"
1568 /* 3598 */ "INLINEASM_BR\000"
1569 /* 3611 */ "G_BLOCK_ADDR\000"
1570 /* 3624 */ "MEMBARRIER\000"
1571 /* 3635 */ "G_CONSTANT_FOLD_BARRIER\000"
1572 /* 3659 */ "PATCHABLE_FUNCTION_ENTER\000"
1573 /* 3684 */ "G_READCYCLECOUNTER\000"
1574 /* 3703 */ "G_READSTEADYCOUNTER\000"
1575 /* 3723 */ "G_READ_REGISTER\000"
1576 /* 3739 */ "G_WRITE_REGISTER\000"
1577 /* 3756 */ "G_ASHR\000"
1578 /* 3763 */ "G_FSHR\000"
1579 /* 3770 */ "G_LSHR\000"
1580 /* 3777 */ "CONVERGENCECTRL_ANCHOR\000"
1581 /* 3800 */ "G_FFLOOR\000"
1582 /* 3809 */ "G_SAVGFLOOR\000"
1583 /* 3821 */ "G_UAVGFLOOR\000"
1584 /* 3833 */ "G_EXTRACT_SUBVECTOR\000"
1585 /* 3853 */ "G_INSERT_SUBVECTOR\000"
1586 /* 3872 */ "G_BUILD_VECTOR\000"
1587 /* 3887 */ "G_SHUFFLE_VECTOR\000"
1588 /* 3904 */ "G_STEP_VECTOR\000"
1589 /* 3918 */ "G_SPLAT_VECTOR\000"
1590 /* 3933 */ "G_VECREDUCE_XOR\000"
1591 /* 3949 */ "G_XOR\000"
1592 /* 3955 */ "G_ATOMICRMW_XOR\000"
1593 /* 3971 */ "G_VECREDUCE_OR\000"
1594 /* 3986 */ "G_OR\000"
1595 /* 3991 */ "G_ATOMICRMW_OR\000"
1596 /* 4006 */ "G_ROTR\000"
1597 /* 4013 */ "G_INTTOPTR\000"
1598 /* 4024 */ "G_FABS\000"
1599 /* 4031 */ "G_ABS\000"
1600 /* 4037 */ "G_ABDS\000"
1601 /* 4044 */ "G_UNMERGE_VALUES\000"
1602 /* 4061 */ "G_MERGE_VALUES\000"
1603 /* 4076 */ "G_CTLS\000"
1604 /* 4083 */ "G_FACOS\000"
1605 /* 4091 */ "G_FCOS\000"
1606 /* 4098 */ "G_FSINCOS\000"
1607 /* 4108 */ "G_STRICT_FCMPS\000"
1608 /* 4123 */ "G_CONCAT_VECTORS\000"
1609 /* 4140 */ "COPY_TO_REGCLASS\000"
1610 /* 4157 */ "G_IS_FPCLASS\000"
1611 /* 4170 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1612 /* 4200 */ "G_VECTOR_COMPRESS\000"
1613 /* 4218 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1614 /* 4245 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1615 /* 4283 */ "G_TRUNC_SSAT_S\000"
1616 /* 4298 */ "G_SSUBSAT\000"
1617 /* 4308 */ "G_USUBSAT\000"
1618 /* 4318 */ "G_SADDSAT\000"
1619 /* 4328 */ "G_UADDSAT\000"
1620 /* 4338 */ "G_SSHLSAT\000"
1621 /* 4348 */ "G_USHLSAT\000"
1622 /* 4358 */ "G_SMULFIXSAT\000"
1623 /* 4371 */ "G_UMULFIXSAT\000"
1624 /* 4384 */ "G_SDIVFIXSAT\000"
1625 /* 4397 */ "G_UDIVFIXSAT\000"
1626 /* 4410 */ "G_ATOMICRMW_USUB_SAT\000"
1627 /* 4431 */ "G_FPTOSI_SAT\000"
1628 /* 4444 */ "G_FPTOUI_SAT\000"
1629 /* 4457 */ "G_EXTRACT\000"
1630 /* 4467 */ "G_SELECT\000"
1631 /* 4476 */ "G_BRINDIRECT\000"
1632 /* 4489 */ "PATCHABLE_RET\000"
1633 /* 4503 */ "FRAME_TO_ARGS_OFFSET\000"
1634 /* 4524 */ "G_MEMSET\000"
1635 /* 4533 */ "PATCHABLE_FUNCTION_EXIT\000"
1636 /* 4557 */ "G_BRJT\000"
1637 /* 4564 */ "BR_JT\000"
1638 /* 4570 */ "G_EXTRACT_VECTOR_ELT\000"
1639 /* 4591 */ "G_INSERT_VECTOR_ELT\000"
1640 /* 4611 */ "G_FCONSTANT\000"
1641 /* 4623 */ "G_CONSTANT\000"
1642 /* 4634 */ "G_INTRINSIC_CONVERGENT\000"
1643 /* 4657 */ "STATEPOINT\000"
1644 /* 4668 */ "PATCHPOINT\000"
1645 /* 4679 */ "G_PTRTOINT\000"
1646 /* 4690 */ "G_FRINT\000"
1647 /* 4698 */ "G_INTRINSIC_LLRINT\000"
1648 /* 4717 */ "G_INTRINSIC_LRINT\000"
1649 /* 4735 */ "G_FNEARBYINT\000"
1650 /* 4748 */ "NOT\000"
1651 /* 4752 */ "G_VASTART\000"
1652 /* 4762 */ "LIFETIME_START\000"
1653 /* 4777 */ "G_INVOKE_REGION_START\000"
1654 /* 4799 */ "G_INSERT\000"
1655 /* 4808 */ "G_FSQRT\000"
1656 /* 4816 */ "G_STRICT_FSQRT\000"
1657 /* 4831 */ "G_BITCAST\000"
1658 /* 4841 */ "G_ADDRSPACE_CAST\000"
1659 /* 4858 */ "DBG_VALUE_LIST\000"
1660 /* 4873 */ "G_FPEXT\000"
1661 /* 4881 */ "G_SEXT\000"
1662 /* 4888 */ "G_ASSERT_SEXT\000"
1663 /* 4902 */ "G_ANYEXT\000"
1664 /* 4911 */ "G_ZEXT\000"
1665 /* 4918 */ "G_ASSERT_ZEXT\000"
1666 /* 4932 */ "G_ABDU\000"
1667 /* 4939 */ "G_TRUNC_SSAT_U\000"
1668 /* 4954 */ "G_TRUNC_USAT_U\000"
1669 /* 4969 */ "G_FDIV\000"
1670 /* 4976 */ "G_STRICT_FDIV\000"
1671 /* 4990 */ "G_SDIV\000"
1672 /* 4997 */ "G_UDIV\000"
1673 /* 5004 */ "G_GET_FPENV\000"
1674 /* 5016 */ "G_RESET_FPENV\000"
1675 /* 5030 */ "G_SET_FPENV\000"
1676 /* 5042 */ "G_FPOW\000"
1677 /* 5049 */ "G_VECREDUCE_FMAX\000"
1678 /* 5066 */ "G_ATOMICRMW_FMAX\000"
1679 /* 5083 */ "G_VECREDUCE_SMAX\000"
1680 /* 5100 */ "G_SMAX\000"
1681 /* 5107 */ "G_VECREDUCE_UMAX\000"
1682 /* 5124 */ "G_UMAX\000"
1683 /* 5131 */ "G_ATOMICRMW_UMAX\000"
1684 /* 5148 */ "G_ATOMICRMW_MAX\000"
1685 /* 5164 */ "G_FRAME_INDEX\000"
1686 /* 5178 */ "G_SBFX\000"
1687 /* 5185 */ "G_UBFX\000"
1688 /* 5192 */ "G_SMULFIX\000"
1689 /* 5202 */ "G_UMULFIX\000"
1690 /* 5212 */ "G_SDIVFIX\000"
1691 /* 5222 */ "G_UDIVFIX\000"
1692 /* 5232 */ "G_MEMCPY\000"
1693 /* 5241 */ "COPY\000"
1694 /* 5246 */ "CONVERGENCECTRL_ENTRY\000"
1695 /* 5268 */ "G_CTLZ\000"
1696 /* 5275 */ "G_CTTZ\000"
1697 /* 5282 */ "LDAPF_lu10_ba\000"
1698 /* 5296 */ "SSYNC_0r\000"
1699 /* 5305 */ "BLA_1r\000"
1700 /* 5312 */ "MSYNC_1r\000"
1701 /* 5321 */ "ECALLF_1r\000"
1702 /* 5331 */ "DGETREG_1r\000"
1703 /* 5342 */ "KCALL_1r\000"
1704 /* 5351 */ "MJOIN_1r\000"
1705 /* 5360 */ "SETCP_1r\000"
1706 /* 5369 */ "SETDP_1r\000"
1707 /* 5378 */ "SETSP_1r\000"
1708 /* 5387 */ "SYNCR_1r\000"
1709 /* 5396 */ "FREER_1r\000"
1710 /* 5405 */ "ECALLT_1r\000"
1711 /* 5415 */ "BAU_1r\000"
1712 /* 5422 */ "EDU_1r\000"
1713 /* 5429 */ "EEU_1r\000"
1714 /* 5436 */ "BRU_1r\000"
1715 /* 5443 */ "SETEV_1r\000"
1716 /* 5452 */ "SETV_1r\000"
1717 /* 5460 */ "INITPC_2r\000"
1718 /* 5470 */ "SETPSC_2r\000"
1719 /* 5480 */ "SETD_2r\000"
1720 /* 5488 */ "EEF_2r\000"
1721 /* 5495 */ "PEEK_2r\000"
1722 /* 5503 */ "MKMSK_2r\000"
1723 /* 5512 */ "ENDIN_2r\000"
1724 /* 5521 */ "INITCP_2r\000"
1725 /* 5531 */ "INITDP_2r\000"
1726 /* 5541 */ "INITSP_2r\000"
1727 /* 5551 */ "INSHR_2r\000"
1728 /* 5560 */ "OUTSHR_2r\000"
1729 /* 5570 */ "TSETMR_2r\000"
1730 /* 5580 */ "GETTS_2r\000"
1731 /* 5589 */ "CHKCT_2r\000"
1732 /* 5598 */ "INCT_2r\000"
1733 /* 5606 */ "TESTCT_2r\000"
1734 /* 5616 */ "OUTCT_2r\000"
1735 /* 5625 */ "TESTWCT_2r\000"
1736 /* 5636 */ "EET_2r\000"
1737 /* 5643 */ "INT_2r\000"
1738 /* 5650 */ "ANDNOT_2r\000"
1739 /* 5660 */ "SETPT_2r\000"
1740 /* 5669 */ "GETST_2r\000"
1741 /* 5678 */ "OUTT_2r\000"
1742 /* 5686 */ "OUT_2r\000"
1743 /* 5693 */ "SEXT_2r\000"
1744 /* 5701 */ "ZEXT_2r\000"
1745 /* 5709 */ "SETC_l2r\000"
1746 /* 5718 */ "GETD_l2r\000"
1747 /* 5727 */ "SETCLK_l2r\000"
1748 /* 5738 */ "TESTLCL_l2r\000"
1749 /* 5750 */ "GETN_l2r\000"
1750 /* 5759 */ "SETN_l2r\000"
1751 /* 5768 */ "INITLR_l2r\000"
1752 /* 5779 */ "GETPS_l2r\000"
1753 /* 5789 */ "SETPS_l2r\000"
1754 /* 5799 */ "BYTEREV_l2r\000"
1755 /* 5811 */ "BITREV_l2r\000"
1756 /* 5822 */ "SETTW_l2r\000"
1757 /* 5832 */ "SETRDY_l2r\000"
1758 /* 5843 */ "CLZ_l2r\000"
1759 /* 5851 */ "SUB_3r\000"
1760 /* 5858 */ "ADD_3r\000"
1761 /* 5865 */ "AND_3r\000"
1762 /* 5872 */ "SHL_3r\000"
1763 /* 5879 */ "EQ_3r\000"
1764 /* 5885 */ "SHR_3r\000"
1765 /* 5892 */ "OR_3r\000"
1766 /* 5898 */ "TSETR_3r\000"
1767 /* 5907 */ "LD16S_3r\000"
1768 /* 5916 */ "LSS_3r\000"
1769 /* 5923 */ "LD8U_3r\000"
1770 /* 5931 */ "LSU_3r\000"
1771 /* 5938 */ "LDW_3r\000"
1772 /* 5945 */ "ST16_l3r\000"
1773 /* 5954 */ "ST8_l3r\000"
1774 /* 5962 */ "LDA16B_l3r\000"
1775 /* 5973 */ "LDAWB_l3r\000"
1776 /* 5983 */ "CRC_l3r\000"
1777 /* 5991 */ "LDA16F_l3r\000"
1778 /* 6002 */ "LDAWF_l3r\000"
1779 /* 6012 */ "MUL_l3r\000"
1780 /* 6020 */ "ASHR_l3r\000"
1781 /* 6029 */ "XOR_l3r\000"
1782 /* 6037 */ "REMS_l3r\000"
1783 /* 6046 */ "DIVS_l3r\000"
1784 /* 6055 */ "REMU_l3r\000"
1785 /* 6064 */ "DIVU_l3r\000"
1786 /* 6073 */ "STW_l3r\000"
1787 /* 6081 */ "CRC8_l4r\000"
1788 /* 6090 */ "MACCS_l4r\000"
1789 /* 6100 */ "MACCU_l4r\000"
1790 /* 6110 */ "LSUB_l5r\000"
1791 /* 6119 */ "LADD_l5r\000"
1792 /* 6128 */ "LDIVU_l5r\000"
1793 /* 6138 */ "LMUL_l6r\000"
1794 /* 6147 */ "SUB_2rus\000"
1795 /* 6156 */ "ADD_2rus\000"
1796 /* 6165 */ "SHL_2rus\000"
1797 /* 6174 */ "EQ_2rus\000"
1798 /* 6182 */ "SHR_2rus\000"
1799 /* 6191 */ "LDW_2rus\000"
1800 /* 6200 */ "STW_2rus\000"
1801 /* 6209 */ "LDAWB_l2rus\000"
1802 /* 6221 */ "LDAWF_l2rus\000"
1803 /* 6233 */ "ASHR_l2rus\000"
1804 /* 6244 */ "INPW_l2rus\000"
1805 /* 6255 */ "OUTPW_l2rus\000"
1806 /* 6267 */ "MKMSK_rus\000"
1807 /* 6277 */ "GETR_rus\000"
1808 /* 6286 */ "CHKCT_rus\000"
1809 /* 6296 */ "OUTCT_rus\000"
1810 /* 6306 */ "SEXT_rus\000"
1811 /* 6315 */ "ZEXT_rus\000"
1812};
1813#ifdef __GNUC__
1814#pragma GCC diagnostic pop
1815#endif
1816
1817extern const unsigned XCoreInstrNameIndices[] = {
1818 2046U, 2460U, 3598U, 2914U, 2119U, 2100U, 2128U, 2288U,
1819 1811U, 1826U, 1777U, 1764U, 1853U, 4140U, 1640U, 4858U,
1820 1790U, 2042U, 2109U, 1379U, 5241U, 2076U, 1501U, 4762U,
1821 1206U, 1330U, 1367U, 3073U, 2276U, 4668U, 1313U, 3294U,
1822 1946U, 4657U, 1551U, 3267U, 3254U, 3659U, 4489U, 4533U,
1823 2208U, 2255U, 2228U, 2145U, 1631U, 3624U, 3027U, 1540U,
1824 5246U, 3777U, 3225U, 1688U, 4888U, 4918U, 2757U, 1119U,
1825 808U, 2399U, 4990U, 4997U, 2426U, 2433U, 2440U, 2450U,
1826 1184U, 3986U, 3949U, 4037U, 4932U, 3821U, 2197U, 3809U,
1827 2186U, 1775U, 2044U, 5164U, 1650U, 1665U, 2293U, 4457U,
1828 4044U, 4799U, 4061U, 3872U, 888U, 4123U, 4679U, 4013U,
1829 4831U, 1731U, 3635U, 1287U, 862U, 1269U, 4717U, 4698U,
1830 2735U, 3684U, 3703U, 1020U, 964U, 994U, 933U, 1005U,
1831 945U, 975U, 1610U, 1564U, 1594U, 4170U, 1867U, 1884U,
1832 1135U, 814U, 1190U, 1151U, 3991U, 3955U, 5148U, 2883U,
1833 5131U, 2866U, 1086U, 791U, 5066U, 2801U, 2555U, 2502U,
1834 2676U, 2614U, 3135U, 3113U, 1228U, 4410U, 1359U, 1963U,
1835 1219U, 4476U, 4777U, 840U, 4218U, 4634U, 4245U, 4902U,
1836 880U, 4283U, 4939U, 4954U, 4623U, 4611U, 4752U, 1938U,
1837 4881U, 1840U, 4911U, 2172U, 3770U, 3756U, 2165U, 3763U,
1838 4006U, 2309U, 3204U, 3183U, 3211U, 3218U, 4467U, 3019U,
1839 1400U, 3003U, 1351U, 3011U, 1392U, 2995U, 1343U, 3057U,
1840 3049U, 1991U, 1983U, 4328U, 4318U, 4308U, 4298U, 4348U,
1841 4338U, 5192U, 5202U, 4358U, 4371U, 5212U, 5222U, 4384U,
1842 4397U, 1044U, 770U, 2333U, 751U, 926U, 4969U, 2405U,
1843 1756U, 5042U, 2068U, 3338U, 165U, 9U, 1931U, 148U,
1844 0U, 3313U, 3345U, 1804U, 4873U, 852U, 2050U, 2059U,
1845 3165U, 3174U, 4431U, 4444U, 4024U, 2772U, 4157U, 1740U,
1846 2700U, 2710U, 1449U, 1464U, 2491U, 2544U, 2600U, 2662U,
1847 5004U, 5030U, 5016U, 1408U, 1436U, 1421U, 1901U, 1916U,
1848 1125U, 2090U, 2835U, 5100U, 2859U, 5124U, 4031U, 1260U,
1849 1250U, 3593U, 4557U, 1479U, 3853U, 3833U, 4591U, 4570U,
1850 3887U, 3918U, 3904U, 4200U, 5275U, 2949U, 5268U, 2930U,
1851 4076U, 3246U, 3157U, 1618U, 2375U, 1974U, 2178U, 4091U,
1852 2907U, 4098U, 2728U, 4083U, 2899U, 2720U, 156U, 2015U,
1853 2007U, 1999U, 4808U, 3800U, 4690U, 4735U, 4841U, 3611U,
1854 1488U, 909U, 1709U, 1579U, 1072U, 777U, 2361U, 4976U,
1855 2412U, 757U, 4816U, 3322U, 3190U, 4108U, 3723U, 3739U,
1856 5232U, 1524U, 1721U, 4524U, 3065U, 1508U, 3106U, 3082U,
1857 3094U, 1051U, 2340U, 1027U, 2316U, 5049U, 2784U, 2523U,
1858 2470U, 2638U, 2576U, 1103U, 2383U, 1168U, 3971U, 3933U,
1859 5083U, 2818U, 5107U, 2842U, 5178U, 5185U, 2978U, 3279U,
1860 4564U, 140U, 2968U, 4503U, 2023U, 2030U, 830U, 2036U,
1861 6156U, 5858U, 5650U, 5865U, 6233U, 6020U, 5415U, 5811U,
1862 118U, 56U, 427U, 267U, 5305U, 87U, 28U, 108U,
1863 47U, 632U, 505U, 731U, 595U, 436U, 275U, 642U,
1864 514U, 741U, 604U, 445U, 283U, 5436U, 5799U, 5589U,
1865 6286U, 3408U, 3574U, 454U, 291U, 397U, 240U, 5843U,
1866 6081U, 5983U, 3416U, 3455U, 5331U, 6046U, 6064U, 3465U,
1867 3511U, 5321U, 5405U, 5422U, 5488U, 5636U, 5429U, 5512U,
1868 365U, 211U, 6174U, 5879U, 344U, 192U, 387U, 231U,
1869 5396U, 3502U, 5718U, 3390U, 3527U, 3399U, 3425U, 3445U,
1870 5750U, 5779U, 6277U, 407U, 249U, 5669U, 5580U, 5598U,
1871 5521U, 5531U, 5768U, 5460U, 5541U, 6244U, 5551U, 5643U,
1872 5515U, 5342U, 323U, 173U, 364U, 210U, 375U, 220U,
1873 3519U, 6119U, 5907U, 5923U, 5962U, 5991U, 76U, 18U,
1874 97U, 5282U, 37U, 6209U, 5973U, 333U, 182U, 663U,
1875 533U, 6221U, 6002U, 697U, 564U, 613U, 488U, 3494U,
1876 6128U, 3372U, 3354U, 3476U, 652U, 129U, 523U, 66U,
1877 675U, 544U, 709U, 575U, 6191U, 5938U, 6138U, 5916U,
1878 6110U, 5931U, 6090U, 6100U, 5351U, 5503U, 6267U, 5312U,
1879 6012U, 1807U, 4748U, 5892U, 5616U, 6296U, 6255U, 5560U,
1880 5678U, 5686U, 5495U, 6037U, 6055U, 354U, 201U, 5727U,
1881 5360U, 5709U, 622U, 496U, 5369U, 5480U, 5443U, 3435U,
1882 5759U, 5470U, 5789U, 5660U, 5832U, 5378U, 471U, 307U,
1883 417U, 258U, 5822U, 5452U, 5693U, 6306U, 6165U, 5872U,
1884 6182U, 5885U, 5296U, 5945U, 5954U, 3536U, 3381U, 3363U,
1885 3485U, 686U, 554U, 720U, 585U, 6200U, 6073U, 6147U,
1886 5851U, 5387U, 5606U, 5738U, 5625U, 5570U, 5898U, 3583U,
1887 3554U, 3564U, 3544U, 6029U, 5701U, 6315U,
1888};
1889
1890static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1891 II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 558, nullptr, 0);
1892}
1893
1894
1895} // namespace llvm
1896
1897#endif // GET_INSTRINFO_MC_DESC
1898
1899#ifdef GET_INSTRINFO_HEADER
1900#undef GET_INSTRINFO_HEADER
1901
1902namespace llvm {
1903
1904struct XCoreGenInstrInfo : public TargetInstrInfo {
1905 explicit XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1906 ~XCoreGenInstrInfo() override = default;
1907};
1908
1909} // namespace llvm
1910
1911namespace llvm::XCore {
1912
1913
1914} // namespace llvm::XCore
1915
1916#endif // GET_INSTRINFO_HEADER
1917
1918#ifdef GET_INSTRINFO_HELPER_DECLS
1919#undef GET_INSTRINFO_HELPER_DECLS
1920
1921
1922#endif // GET_INSTRINFO_HELPER_DECLS
1923
1924#ifdef GET_INSTRINFO_HELPERS
1925#undef GET_INSTRINFO_HELPERS
1926
1927
1928#endif // GET_INSTRINFO_HELPERS
1929
1930#ifdef GET_INSTRINFO_CTOR_DTOR
1931#undef GET_INSTRINFO_CTOR_DTOR
1932
1933namespace llvm {
1934
1935extern const XCoreInstrTable XCoreDescs;
1936extern const unsigned XCoreInstrNameIndices[];
1937extern const char XCoreInstrNameData[];
1938XCoreGenInstrInfo::XCoreGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1939 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1940 InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 558);
1941}
1942
1943} // namespace llvm
1944
1945#endif // GET_INSTRINFO_CTOR_DTOR
1946
1947#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1948#undef GET_INSTRINFO_MC_HELPER_DECLS
1949
1950namespace llvm {
1951
1952class MCInst;
1953class FeatureBitset;
1954
1955namespace XCore_MC {
1956
1957void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1958
1959} // namespace XCore_MC
1960
1961} // namespace llvm
1962
1963#endif // GET_INSTRINFO_MC_HELPER_DECLS
1964
1965#ifdef GET_INSTRINFO_MC_HELPERS
1966#undef GET_INSTRINFO_MC_HELPERS
1967
1968namespace llvm::XCore_MC {
1969
1970
1971} // namespace llvm::XCore_MC
1972
1973#endif // GET_INSTRINFO_MC_HELPERS
1974
1975#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1976 defined(GET_AVAILABLE_OPCODE_CHECKER)
1977#define GET_COMPUTE_FEATURES
1978#endif
1979#ifdef GET_COMPUTE_FEATURES
1980#undef GET_COMPUTE_FEATURES
1981
1982namespace llvm::XCore_MC {
1983
1984// Bits for subtarget features that participate in instruction matching.
1985enum SubtargetFeatureBits : uint8_t {
1986};
1987
1988inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1989 FeatureBitset Features;
1990 return Features;
1991}
1992
1993inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1994 enum : uint8_t {
1995 CEFBS_None,
1996 };
1997
1998 static constexpr FeatureBitset FeatureBitsets[] = {
1999 {}, // CEFBS_None
2000 };
2001 static constexpr uint8_t RequiredFeaturesRefs[] = {
2002 CEFBS_None, // PHI
2003 CEFBS_None, // INLINEASM
2004 CEFBS_None, // INLINEASM_BR
2005 CEFBS_None, // CFI_INSTRUCTION
2006 CEFBS_None, // EH_LABEL
2007 CEFBS_None, // GC_LABEL
2008 CEFBS_None, // ANNOTATION_LABEL
2009 CEFBS_None, // KILL
2010 CEFBS_None, // EXTRACT_SUBREG
2011 CEFBS_None, // INSERT_SUBREG
2012 CEFBS_None, // IMPLICIT_DEF
2013 CEFBS_None, // INIT_UNDEF
2014 CEFBS_None, // SUBREG_TO_REG
2015 CEFBS_None, // COPY_TO_REGCLASS
2016 CEFBS_None, // DBG_VALUE
2017 CEFBS_None, // DBG_VALUE_LIST
2018 CEFBS_None, // DBG_INSTR_REF
2019 CEFBS_None, // DBG_PHI
2020 CEFBS_None, // DBG_LABEL
2021 CEFBS_None, // REG_SEQUENCE
2022 CEFBS_None, // COPY
2023 CEFBS_None, // COPY_LANEMASK
2024 CEFBS_None, // BUNDLE
2025 CEFBS_None, // LIFETIME_START
2026 CEFBS_None, // LIFETIME_END
2027 CEFBS_None, // PSEUDO_PROBE
2028 CEFBS_None, // ARITH_FENCE
2029 CEFBS_None, // STACKMAP
2030 CEFBS_None, // FENTRY_CALL
2031 CEFBS_None, // PATCHPOINT
2032 CEFBS_None, // LOAD_STACK_GUARD
2033 CEFBS_None, // PREALLOCATED_SETUP
2034 CEFBS_None, // PREALLOCATED_ARG
2035 CEFBS_None, // STATEPOINT
2036 CEFBS_None, // LOCAL_ESCAPE
2037 CEFBS_None, // FAULTING_OP
2038 CEFBS_None, // PATCHABLE_OP
2039 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2040 CEFBS_None, // PATCHABLE_RET
2041 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2042 CEFBS_None, // PATCHABLE_TAIL_CALL
2043 CEFBS_None, // PATCHABLE_EVENT_CALL
2044 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2045 CEFBS_None, // ICALL_BRANCH_FUNNEL
2046 CEFBS_None, // FAKE_USE
2047 CEFBS_None, // MEMBARRIER
2048 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2049 CEFBS_None, // RELOC_NONE
2050 CEFBS_None, // CONVERGENCECTRL_ENTRY
2051 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2052 CEFBS_None, // CONVERGENCECTRL_LOOP
2053 CEFBS_None, // CONVERGENCECTRL_GLUE
2054 CEFBS_None, // G_ASSERT_SEXT
2055 CEFBS_None, // G_ASSERT_ZEXT
2056 CEFBS_None, // G_ASSERT_ALIGN
2057 CEFBS_None, // G_ADD
2058 CEFBS_None, // G_SUB
2059 CEFBS_None, // G_MUL
2060 CEFBS_None, // G_SDIV
2061 CEFBS_None, // G_UDIV
2062 CEFBS_None, // G_SREM
2063 CEFBS_None, // G_UREM
2064 CEFBS_None, // G_SDIVREM
2065 CEFBS_None, // G_UDIVREM
2066 CEFBS_None, // G_AND
2067 CEFBS_None, // G_OR
2068 CEFBS_None, // G_XOR
2069 CEFBS_None, // G_ABDS
2070 CEFBS_None, // G_ABDU
2071 CEFBS_None, // G_UAVGFLOOR
2072 CEFBS_None, // G_UAVGCEIL
2073 CEFBS_None, // G_SAVGFLOOR
2074 CEFBS_None, // G_SAVGCEIL
2075 CEFBS_None, // G_IMPLICIT_DEF
2076 CEFBS_None, // G_PHI
2077 CEFBS_None, // G_FRAME_INDEX
2078 CEFBS_None, // G_GLOBAL_VALUE
2079 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2080 CEFBS_None, // G_CONSTANT_POOL
2081 CEFBS_None, // G_EXTRACT
2082 CEFBS_None, // G_UNMERGE_VALUES
2083 CEFBS_None, // G_INSERT
2084 CEFBS_None, // G_MERGE_VALUES
2085 CEFBS_None, // G_BUILD_VECTOR
2086 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2087 CEFBS_None, // G_CONCAT_VECTORS
2088 CEFBS_None, // G_PTRTOINT
2089 CEFBS_None, // G_INTTOPTR
2090 CEFBS_None, // G_BITCAST
2091 CEFBS_None, // G_FREEZE
2092 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2093 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2094 CEFBS_None, // G_INTRINSIC_TRUNC
2095 CEFBS_None, // G_INTRINSIC_ROUND
2096 CEFBS_None, // G_INTRINSIC_LRINT
2097 CEFBS_None, // G_INTRINSIC_LLRINT
2098 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2099 CEFBS_None, // G_READCYCLECOUNTER
2100 CEFBS_None, // G_READSTEADYCOUNTER
2101 CEFBS_None, // G_LOAD
2102 CEFBS_None, // G_SEXTLOAD
2103 CEFBS_None, // G_ZEXTLOAD
2104 CEFBS_None, // G_FPEXTLOAD
2105 CEFBS_None, // G_INDEXED_LOAD
2106 CEFBS_None, // G_INDEXED_SEXTLOAD
2107 CEFBS_None, // G_INDEXED_ZEXTLOAD
2108 CEFBS_None, // G_STORE
2109 CEFBS_None, // G_FPTRUNCSTORE
2110 CEFBS_None, // G_INDEXED_STORE
2111 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2112 CEFBS_None, // G_ATOMIC_CMPXCHG
2113 CEFBS_None, // G_ATOMICRMW_XCHG
2114 CEFBS_None, // G_ATOMICRMW_ADD
2115 CEFBS_None, // G_ATOMICRMW_SUB
2116 CEFBS_None, // G_ATOMICRMW_AND
2117 CEFBS_None, // G_ATOMICRMW_NAND
2118 CEFBS_None, // G_ATOMICRMW_OR
2119 CEFBS_None, // G_ATOMICRMW_XOR
2120 CEFBS_None, // G_ATOMICRMW_MAX
2121 CEFBS_None, // G_ATOMICRMW_MIN
2122 CEFBS_None, // G_ATOMICRMW_UMAX
2123 CEFBS_None, // G_ATOMICRMW_UMIN
2124 CEFBS_None, // G_ATOMICRMW_FADD
2125 CEFBS_None, // G_ATOMICRMW_FSUB
2126 CEFBS_None, // G_ATOMICRMW_FMAX
2127 CEFBS_None, // G_ATOMICRMW_FMIN
2128 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2129 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2130 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2131 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2132 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2133 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2134 CEFBS_None, // G_ATOMICRMW_USUB_COND
2135 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2136 CEFBS_None, // G_FENCE
2137 CEFBS_None, // G_PREFETCH
2138 CEFBS_None, // G_BRCOND
2139 CEFBS_None, // G_BRINDIRECT
2140 CEFBS_None, // G_INVOKE_REGION_START
2141 CEFBS_None, // G_INTRINSIC
2142 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2143 CEFBS_None, // G_INTRINSIC_CONVERGENT
2144 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2145 CEFBS_None, // G_ANYEXT
2146 CEFBS_None, // G_TRUNC
2147 CEFBS_None, // G_TRUNC_SSAT_S
2148 CEFBS_None, // G_TRUNC_SSAT_U
2149 CEFBS_None, // G_TRUNC_USAT_U
2150 CEFBS_None, // G_CONSTANT
2151 CEFBS_None, // G_FCONSTANT
2152 CEFBS_None, // G_VASTART
2153 CEFBS_None, // G_VAARG
2154 CEFBS_None, // G_SEXT
2155 CEFBS_None, // G_SEXT_INREG
2156 CEFBS_None, // G_ZEXT
2157 CEFBS_None, // G_SHL
2158 CEFBS_None, // G_LSHR
2159 CEFBS_None, // G_ASHR
2160 CEFBS_None, // G_FSHL
2161 CEFBS_None, // G_FSHR
2162 CEFBS_None, // G_ROTR
2163 CEFBS_None, // G_ROTL
2164 CEFBS_None, // G_ICMP
2165 CEFBS_None, // G_FCMP
2166 CEFBS_None, // G_SCMP
2167 CEFBS_None, // G_UCMP
2168 CEFBS_None, // G_SELECT
2169 CEFBS_None, // G_UADDO
2170 CEFBS_None, // G_UADDE
2171 CEFBS_None, // G_USUBO
2172 CEFBS_None, // G_USUBE
2173 CEFBS_None, // G_SADDO
2174 CEFBS_None, // G_SADDE
2175 CEFBS_None, // G_SSUBO
2176 CEFBS_None, // G_SSUBE
2177 CEFBS_None, // G_UMULO
2178 CEFBS_None, // G_SMULO
2179 CEFBS_None, // G_UMULH
2180 CEFBS_None, // G_SMULH
2181 CEFBS_None, // G_UADDSAT
2182 CEFBS_None, // G_SADDSAT
2183 CEFBS_None, // G_USUBSAT
2184 CEFBS_None, // G_SSUBSAT
2185 CEFBS_None, // G_USHLSAT
2186 CEFBS_None, // G_SSHLSAT
2187 CEFBS_None, // G_SMULFIX
2188 CEFBS_None, // G_UMULFIX
2189 CEFBS_None, // G_SMULFIXSAT
2190 CEFBS_None, // G_UMULFIXSAT
2191 CEFBS_None, // G_SDIVFIX
2192 CEFBS_None, // G_UDIVFIX
2193 CEFBS_None, // G_SDIVFIXSAT
2194 CEFBS_None, // G_UDIVFIXSAT
2195 CEFBS_None, // G_FADD
2196 CEFBS_None, // G_FSUB
2197 CEFBS_None, // G_FMUL
2198 CEFBS_None, // G_FMA
2199 CEFBS_None, // G_FMAD
2200 CEFBS_None, // G_FDIV
2201 CEFBS_None, // G_FREM
2202 CEFBS_None, // G_FMODF
2203 CEFBS_None, // G_FPOW
2204 CEFBS_None, // G_FPOWI
2205 CEFBS_None, // G_FEXP
2206 CEFBS_None, // G_FEXP2
2207 CEFBS_None, // G_FEXP10
2208 CEFBS_None, // G_FLOG
2209 CEFBS_None, // G_FLOG2
2210 CEFBS_None, // G_FLOG10
2211 CEFBS_None, // G_FLDEXP
2212 CEFBS_None, // G_FFREXP
2213 CEFBS_None, // G_FNEG
2214 CEFBS_None, // G_FPEXT
2215 CEFBS_None, // G_FPTRUNC
2216 CEFBS_None, // G_FPTOSI
2217 CEFBS_None, // G_FPTOUI
2218 CEFBS_None, // G_SITOFP
2219 CEFBS_None, // G_UITOFP
2220 CEFBS_None, // G_FPTOSI_SAT
2221 CEFBS_None, // G_FPTOUI_SAT
2222 CEFBS_None, // G_FABS
2223 CEFBS_None, // G_FCOPYSIGN
2224 CEFBS_None, // G_IS_FPCLASS
2225 CEFBS_None, // G_FCANONICALIZE
2226 CEFBS_None, // G_FMINNUM
2227 CEFBS_None, // G_FMAXNUM
2228 CEFBS_None, // G_FMINNUM_IEEE
2229 CEFBS_None, // G_FMAXNUM_IEEE
2230 CEFBS_None, // G_FMINIMUM
2231 CEFBS_None, // G_FMAXIMUM
2232 CEFBS_None, // G_FMINIMUMNUM
2233 CEFBS_None, // G_FMAXIMUMNUM
2234 CEFBS_None, // G_GET_FPENV
2235 CEFBS_None, // G_SET_FPENV
2236 CEFBS_None, // G_RESET_FPENV
2237 CEFBS_None, // G_GET_FPMODE
2238 CEFBS_None, // G_SET_FPMODE
2239 CEFBS_None, // G_RESET_FPMODE
2240 CEFBS_None, // G_GET_ROUNDING
2241 CEFBS_None, // G_SET_ROUNDING
2242 CEFBS_None, // G_PTR_ADD
2243 CEFBS_None, // G_PTRMASK
2244 CEFBS_None, // G_SMIN
2245 CEFBS_None, // G_SMAX
2246 CEFBS_None, // G_UMIN
2247 CEFBS_None, // G_UMAX
2248 CEFBS_None, // G_ABS
2249 CEFBS_None, // G_LROUND
2250 CEFBS_None, // G_LLROUND
2251 CEFBS_None, // G_BR
2252 CEFBS_None, // G_BRJT
2253 CEFBS_None, // G_VSCALE
2254 CEFBS_None, // G_INSERT_SUBVECTOR
2255 CEFBS_None, // G_EXTRACT_SUBVECTOR
2256 CEFBS_None, // G_INSERT_VECTOR_ELT
2257 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2258 CEFBS_None, // G_SHUFFLE_VECTOR
2259 CEFBS_None, // G_SPLAT_VECTOR
2260 CEFBS_None, // G_STEP_VECTOR
2261 CEFBS_None, // G_VECTOR_COMPRESS
2262 CEFBS_None, // G_CTTZ
2263 CEFBS_None, // G_CTTZ_ZERO_POISON
2264 CEFBS_None, // G_CTLZ
2265 CEFBS_None, // G_CTLZ_ZERO_POISON
2266 CEFBS_None, // G_CTLS
2267 CEFBS_None, // G_CTPOP
2268 CEFBS_None, // G_BSWAP
2269 CEFBS_None, // G_BITREVERSE
2270 CEFBS_None, // G_CLMUL
2271 CEFBS_None, // G_CLMULH
2272 CEFBS_None, // G_FCEIL
2273 CEFBS_None, // G_FCOS
2274 CEFBS_None, // G_FSIN
2275 CEFBS_None, // G_FSINCOS
2276 CEFBS_None, // G_FTAN
2277 CEFBS_None, // G_FACOS
2278 CEFBS_None, // G_FASIN
2279 CEFBS_None, // G_FATAN
2280 CEFBS_None, // G_FATAN2
2281 CEFBS_None, // G_FCOSH
2282 CEFBS_None, // G_FSINH
2283 CEFBS_None, // G_FTANH
2284 CEFBS_None, // G_FSQRT
2285 CEFBS_None, // G_FFLOOR
2286 CEFBS_None, // G_FRINT
2287 CEFBS_None, // G_FNEARBYINT
2288 CEFBS_None, // G_ADDRSPACE_CAST
2289 CEFBS_None, // G_BLOCK_ADDR
2290 CEFBS_None, // G_JUMP_TABLE
2291 CEFBS_None, // G_DYN_STACKALLOC
2292 CEFBS_None, // G_STACKSAVE
2293 CEFBS_None, // G_STACKRESTORE
2294 CEFBS_None, // G_STRICT_FADD
2295 CEFBS_None, // G_STRICT_FSUB
2296 CEFBS_None, // G_STRICT_FMUL
2297 CEFBS_None, // G_STRICT_FDIV
2298 CEFBS_None, // G_STRICT_FREM
2299 CEFBS_None, // G_STRICT_FMA
2300 CEFBS_None, // G_STRICT_FSQRT
2301 CEFBS_None, // G_STRICT_FLDEXP
2302 CEFBS_None, // G_STRICT_FCMP
2303 CEFBS_None, // G_STRICT_FCMPS
2304 CEFBS_None, // G_READ_REGISTER
2305 CEFBS_None, // G_WRITE_REGISTER
2306 CEFBS_None, // G_MEMCPY
2307 CEFBS_None, // G_MEMCPY_INLINE
2308 CEFBS_None, // G_MEMMOVE
2309 CEFBS_None, // G_MEMSET
2310 CEFBS_None, // G_BZERO
2311 CEFBS_None, // G_MEMSET_INLINE
2312 CEFBS_None, // G_TRAP
2313 CEFBS_None, // G_DEBUGTRAP
2314 CEFBS_None, // G_UBSANTRAP
2315 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2316 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2317 CEFBS_None, // G_VECREDUCE_FADD
2318 CEFBS_None, // G_VECREDUCE_FMUL
2319 CEFBS_None, // G_VECREDUCE_FMAX
2320 CEFBS_None, // G_VECREDUCE_FMIN
2321 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2322 CEFBS_None, // G_VECREDUCE_FMINIMUM
2323 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2324 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2325 CEFBS_None, // G_VECREDUCE_ADD
2326 CEFBS_None, // G_VECREDUCE_MUL
2327 CEFBS_None, // G_VECREDUCE_AND
2328 CEFBS_None, // G_VECREDUCE_OR
2329 CEFBS_None, // G_VECREDUCE_XOR
2330 CEFBS_None, // G_VECREDUCE_SMAX
2331 CEFBS_None, // G_VECREDUCE_SMIN
2332 CEFBS_None, // G_VECREDUCE_UMAX
2333 CEFBS_None, // G_VECREDUCE_UMIN
2334 CEFBS_None, // G_SBFX
2335 CEFBS_None, // G_UBFX
2336 CEFBS_None, // ADJCALLSTACKDOWN
2337 CEFBS_None, // ADJCALLSTACKUP
2338 CEFBS_None, // BR_JT
2339 CEFBS_None, // BR_JT32
2340 CEFBS_None, // EH_RETURN
2341 CEFBS_None, // FRAME_TO_ARGS_OFFSET
2342 CEFBS_None, // LDAWFI
2343 CEFBS_None, // LDWFI
2344 CEFBS_None, // SELECT_CC
2345 CEFBS_None, // STWFI
2346 CEFBS_None, // ADD_2rus
2347 CEFBS_None, // ADD_3r
2348 CEFBS_None, // ANDNOT_2r
2349 CEFBS_None, // AND_3r
2350 CEFBS_None, // ASHR_l2rus
2351 CEFBS_None, // ASHR_l3r
2352 CEFBS_None, // BAU_1r
2353 CEFBS_None, // BITREV_l2r
2354 CEFBS_None, // BLACP_lu10
2355 CEFBS_None, // BLACP_u10
2356 CEFBS_None, // BLAT_lu6
2357 CEFBS_None, // BLAT_u6
2358 CEFBS_None, // BLA_1r
2359 CEFBS_None, // BLRB_lu10
2360 CEFBS_None, // BLRB_u10
2361 CEFBS_None, // BLRF_lu10
2362 CEFBS_None, // BLRF_u10
2363 CEFBS_None, // BRBF_lru6
2364 CEFBS_None, // BRBF_ru6
2365 CEFBS_None, // BRBT_lru6
2366 CEFBS_None, // BRBT_ru6
2367 CEFBS_None, // BRBU_lu6
2368 CEFBS_None, // BRBU_u6
2369 CEFBS_None, // BRFF_lru6
2370 CEFBS_None, // BRFF_ru6
2371 CEFBS_None, // BRFT_lru6
2372 CEFBS_None, // BRFT_ru6
2373 CEFBS_None, // BRFU_lu6
2374 CEFBS_None, // BRFU_u6
2375 CEFBS_None, // BRU_1r
2376 CEFBS_None, // BYTEREV_l2r
2377 CEFBS_None, // CHKCT_2r
2378 CEFBS_None, // CHKCT_rus
2379 CEFBS_None, // CLRE_0R
2380 CEFBS_None, // CLRPT_1R
2381 CEFBS_None, // CLRSR_branch_lu6
2382 CEFBS_None, // CLRSR_branch_u6
2383 CEFBS_None, // CLRSR_lu6
2384 CEFBS_None, // CLRSR_u6
2385 CEFBS_None, // CLZ_l2r
2386 CEFBS_None, // CRC8_l4r
2387 CEFBS_None, // CRC_l3r
2388 CEFBS_None, // DCALL_0R
2389 CEFBS_None, // DENTSP_0R
2390 CEFBS_None, // DGETREG_1r
2391 CEFBS_None, // DIVS_l3r
2392 CEFBS_None, // DIVU_l3r
2393 CEFBS_None, // DRESTSP_0R
2394 CEFBS_None, // DRET_0R
2395 CEFBS_None, // ECALLF_1r
2396 CEFBS_None, // ECALLT_1r
2397 CEFBS_None, // EDU_1r
2398 CEFBS_None, // EEF_2r
2399 CEFBS_None, // EET_2r
2400 CEFBS_None, // EEU_1r
2401 CEFBS_None, // ENDIN_2r
2402 CEFBS_None, // ENTSP_lu6
2403 CEFBS_None, // ENTSP_u6
2404 CEFBS_None, // EQ_2rus
2405 CEFBS_None, // EQ_3r
2406 CEFBS_None, // EXTDP_lu6
2407 CEFBS_None, // EXTDP_u6
2408 CEFBS_None, // EXTSP_lu6
2409 CEFBS_None, // EXTSP_u6
2410 CEFBS_None, // FREER_1r
2411 CEFBS_None, // FREET_0R
2412 CEFBS_None, // GETD_l2r
2413 CEFBS_None, // GETED_0R
2414 CEFBS_None, // GETET_0R
2415 CEFBS_None, // GETID_0R
2416 CEFBS_None, // GETKEP_0R
2417 CEFBS_None, // GETKSP_0R
2418 CEFBS_None, // GETN_l2r
2419 CEFBS_None, // GETPS_l2r
2420 CEFBS_None, // GETR_rus
2421 CEFBS_None, // GETSR_lu6
2422 CEFBS_None, // GETSR_u6
2423 CEFBS_None, // GETST_2r
2424 CEFBS_None, // GETTS_2r
2425 CEFBS_None, // INCT_2r
2426 CEFBS_None, // INITCP_2r
2427 CEFBS_None, // INITDP_2r
2428 CEFBS_None, // INITLR_l2r
2429 CEFBS_None, // INITPC_2r
2430 CEFBS_None, // INITSP_2r
2431 CEFBS_None, // INPW_l2rus
2432 CEFBS_None, // INSHR_2r
2433 CEFBS_None, // INT_2r
2434 CEFBS_None, // IN_2r
2435 CEFBS_None, // KCALL_1r
2436 CEFBS_None, // KCALL_lu6
2437 CEFBS_None, // KCALL_u6
2438 CEFBS_None, // KENTSP_lu6
2439 CEFBS_None, // KENTSP_u6
2440 CEFBS_None, // KRESTSP_lu6
2441 CEFBS_None, // KRESTSP_u6
2442 CEFBS_None, // KRET_0R
2443 CEFBS_None, // LADD_l5r
2444 CEFBS_None, // LD16S_3r
2445 CEFBS_None, // LD8U_3r
2446 CEFBS_None, // LDA16B_l3r
2447 CEFBS_None, // LDA16F_l3r
2448 CEFBS_None, // LDAPB_lu10
2449 CEFBS_None, // LDAPB_u10
2450 CEFBS_None, // LDAPF_lu10
2451 CEFBS_None, // LDAPF_lu10_ba
2452 CEFBS_None, // LDAPF_u10
2453 CEFBS_None, // LDAWB_l2rus
2454 CEFBS_None, // LDAWB_l3r
2455 CEFBS_None, // LDAWCP_lu6
2456 CEFBS_None, // LDAWCP_u6
2457 CEFBS_None, // LDAWDP_lru6
2458 CEFBS_None, // LDAWDP_ru6
2459 CEFBS_None, // LDAWF_l2rus
2460 CEFBS_None, // LDAWF_l3r
2461 CEFBS_None, // LDAWSP_lru6
2462 CEFBS_None, // LDAWSP_ru6
2463 CEFBS_None, // LDC_lru6
2464 CEFBS_None, // LDC_ru6
2465 CEFBS_None, // LDET_0R
2466 CEFBS_None, // LDIVU_l5r
2467 CEFBS_None, // LDSED_0R
2468 CEFBS_None, // LDSPC_0R
2469 CEFBS_None, // LDSSR_0R
2470 CEFBS_None, // LDWCP_lru6
2471 CEFBS_None, // LDWCP_lu10
2472 CEFBS_None, // LDWCP_ru6
2473 CEFBS_None, // LDWCP_u10
2474 CEFBS_None, // LDWDP_lru6
2475 CEFBS_None, // LDWDP_ru6
2476 CEFBS_None, // LDWSP_lru6
2477 CEFBS_None, // LDWSP_ru6
2478 CEFBS_None, // LDW_2rus
2479 CEFBS_None, // LDW_3r
2480 CEFBS_None, // LMUL_l6r
2481 CEFBS_None, // LSS_3r
2482 CEFBS_None, // LSUB_l5r
2483 CEFBS_None, // LSU_3r
2484 CEFBS_None, // MACCS_l4r
2485 CEFBS_None, // MACCU_l4r
2486 CEFBS_None, // MJOIN_1r
2487 CEFBS_None, // MKMSK_2r
2488 CEFBS_None, // MKMSK_rus
2489 CEFBS_None, // MSYNC_1r
2490 CEFBS_None, // MUL_l3r
2491 CEFBS_None, // NEG
2492 CEFBS_None, // NOT
2493 CEFBS_None, // OR_3r
2494 CEFBS_None, // OUTCT_2r
2495 CEFBS_None, // OUTCT_rus
2496 CEFBS_None, // OUTPW_l2rus
2497 CEFBS_None, // OUTSHR_2r
2498 CEFBS_None, // OUTT_2r
2499 CEFBS_None, // OUT_2r
2500 CEFBS_None, // PEEK_2r
2501 CEFBS_None, // REMS_l3r
2502 CEFBS_None, // REMU_l3r
2503 CEFBS_None, // RETSP_lu6
2504 CEFBS_None, // RETSP_u6
2505 CEFBS_None, // SETCLK_l2r
2506 CEFBS_None, // SETCP_1r
2507 CEFBS_None, // SETC_l2r
2508 CEFBS_None, // SETC_lru6
2509 CEFBS_None, // SETC_ru6
2510 CEFBS_None, // SETDP_1r
2511 CEFBS_None, // SETD_2r
2512 CEFBS_None, // SETEV_1r
2513 CEFBS_None, // SETKEP_0R
2514 CEFBS_None, // SETN_l2r
2515 CEFBS_None, // SETPSC_2r
2516 CEFBS_None, // SETPS_l2r
2517 CEFBS_None, // SETPT_2r
2518 CEFBS_None, // SETRDY_l2r
2519 CEFBS_None, // SETSP_1r
2520 CEFBS_None, // SETSR_branch_lu6
2521 CEFBS_None, // SETSR_branch_u6
2522 CEFBS_None, // SETSR_lu6
2523 CEFBS_None, // SETSR_u6
2524 CEFBS_None, // SETTW_l2r
2525 CEFBS_None, // SETV_1r
2526 CEFBS_None, // SEXT_2r
2527 CEFBS_None, // SEXT_rus
2528 CEFBS_None, // SHL_2rus
2529 CEFBS_None, // SHL_3r
2530 CEFBS_None, // SHR_2rus
2531 CEFBS_None, // SHR_3r
2532 CEFBS_None, // SSYNC_0r
2533 CEFBS_None, // ST16_l3r
2534 CEFBS_None, // ST8_l3r
2535 CEFBS_None, // STET_0R
2536 CEFBS_None, // STSED_0R
2537 CEFBS_None, // STSPC_0R
2538 CEFBS_None, // STSSR_0R
2539 CEFBS_None, // STWDP_lru6
2540 CEFBS_None, // STWDP_ru6
2541 CEFBS_None, // STWSP_lru6
2542 CEFBS_None, // STWSP_ru6
2543 CEFBS_None, // STW_2rus
2544 CEFBS_None, // STW_l3r
2545 CEFBS_None, // SUB_2rus
2546 CEFBS_None, // SUB_3r
2547 CEFBS_None, // SYNCR_1r
2548 CEFBS_None, // TESTCT_2r
2549 CEFBS_None, // TESTLCL_l2r
2550 CEFBS_None, // TESTWCT_2r
2551 CEFBS_None, // TSETMR_2r
2552 CEFBS_None, // TSETR_3r
2553 CEFBS_None, // TSTART_1R
2554 CEFBS_None, // WAITEF_1R
2555 CEFBS_None, // WAITET_1R
2556 CEFBS_None, // WAITEU_0R
2557 CEFBS_None, // XOR_l3r
2558 CEFBS_None, // ZEXT_2r
2559 CEFBS_None, // ZEXT_rus
2560 };
2561
2562 assert(Opcode < 558);
2563 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2564}
2565
2566
2567} // namespace llvm::XCore_MC
2568
2569#endif // GET_COMPUTE_FEATURES
2570
2571#ifdef GET_AVAILABLE_OPCODE_CHECKER
2572#undef GET_AVAILABLE_OPCODE_CHECKER
2573
2574namespace llvm::XCore_MC {
2575
2576bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2577 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2578 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2579 FeatureBitset MissingFeatures =
2580 (AvailableFeatures & RequiredFeatures) ^
2581 RequiredFeatures;
2582 return !MissingFeatures.any();
2583}
2584
2585} // namespace llvm::XCore_MC
2586
2587#endif // GET_AVAILABLE_OPCODE_CHECKER
2588
2589#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2590#undef ENABLE_INSTR_PREDICATE_VERIFIER
2591
2592#include <sstream>
2593
2594namespace llvm::XCore_MC {
2595
2596#ifndef NDEBUG
2597static const char *SubtargetFeatureNames[] = {
2598 nullptr
2599};
2600
2601#endif // NDEBUG
2602
2603void verifyInstructionPredicates(
2604 unsigned Opcode, const FeatureBitset &Features) {
2605#ifndef NDEBUG
2606 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2607 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2608 FeatureBitset MissingFeatures =
2609 (AvailableFeatures & RequiredFeatures) ^
2610 RequiredFeatures;
2611 if (MissingFeatures.any()) {
2612 std::ostringstream Msg;
2613 Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
2614 << " instruction but the ";
2615 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2616 if (MissingFeatures.test(i))
2617 Msg << SubtargetFeatureNames[i] << " ";
2618 Msg << "predicate(s) are not met";
2619 report_fatal_error(Msg.str().c_str());
2620 }
2621#endif // NDEBUG
2622}
2623
2624} // namespace llvm::XCore_MC
2625
2626#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2627
2628