1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12const MCRegisterClass &getXCoreMCRegisterClass(unsigned RC);
13namespace XCore {
14
15enum : unsigned {
16 NoRegister,
17 CP = 1,
18 DP = 2,
19 LR = 3,
20 SP = 4,
21 R0 = 5,
22 R1 = 6,
23 R2 = 7,
24 R3 = 8,
25 R4 = 9,
26 R5 = 10,
27 R6 = 11,
28 R7 = 12,
29 R8 = 13,
30 R9 = 14,
31 R10 = 15,
32 R11 = 16,
33 NUM_TARGET_REGS // 17
34};
35
36} // namespace XCore
37
38// Register classes
39
40namespace XCore {
41
42enum {
43 RRegsRegClassID = 0,
44 GRRegsRegClassID = 1,
45
46};
47
48} // namespace XCore
49// Register pressure sets enum.
50namespace XCore {
51
52enum RegisterPressureSets {
53 GRRegs = 0,
54};
55
56} // namespace XCore
57
58} // namespace llvm
59