1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass XCoreMCRegisterClasses[];
13
14namespace XCore {
15
16enum : unsigned {
17 NoRegister,
18 CP = 1,
19 DP = 2,
20 LR = 3,
21 SP = 4,
22 R0 = 5,
23 R1 = 6,
24 R2 = 7,
25 R3 = 8,
26 R4 = 9,
27 R5 = 10,
28 R6 = 11,
29 R7 = 12,
30 R8 = 13,
31 R9 = 14,
32 R10 = 15,
33 R11 = 16,
34 NUM_TARGET_REGS // 17
35};
36
37} // namespace XCore
38
39// Register classes
40
41namespace XCore {
42
43enum {
44 RRegsRegClassID = 0,
45 GRRegsRegClassID = 1,
46
47};
48
49} // namespace XCore
50// Register pressure sets enum.
51namespace XCore {
52
53enum RegisterPressureSets {
54 GRRegs = 0,
55};
56
57} // namespace XCore
58
59} // namespace llvm
60