1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14
15} // namespace llvm
16
17#endif // GET_SUBTARGETINFO_ENUM
18
19#ifdef GET_SUBTARGETINFO_MACRO
20
21
22#undef GET_SUBTARGETINFO_MACRO
23#endif // GET_SUBTARGETINFO_MACRO
24
25#ifdef GET_SUBTARGETINFO_MC_DESC
26#undef GET_SUBTARGETINFO_MC_DESC
27
28namespace llvm {
29
30
31#ifdef DBGFIELD
32#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
33#endif
34#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35#define DBGFIELD(x) x,
36#define DBGVAL_OR_NULLPTR(x) x
37#else
38#define DBGFIELD(x)
39#define DBGVAL_OR_NULLPTR(x) nullptr
40#endif
41
42// ===============================================================
43// Data tables for the new per-operand machine model.
44
45// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
46extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[] = {
47 { 0, 0, 0 }, // Invalid
48}; // XCoreWriteProcResTable
49
50// {Cycles, WriteResourceID}
51extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[] = {
52 { 0, 0}, // Invalid
53}; // XCoreWriteLatencyTable
54
55// {UseIdx, WriteResourceID, Cycles}
56extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[] = {
57 {0, 0, 0}, // Invalid
58}; // XCoreReadAdvanceTable
59
60#ifdef __GNUC__
61#pragma GCC diagnostic push
62#pragma GCC diagnostic ignored "-Woverlength-strings"
63#endif
64static constexpr char XCoreSchedClassNamesStorage[] =
65 "\0"
66 "InvalidSchedClass\0"
67 ;
68#ifdef __GNUC__
69#pragma GCC diagnostic pop
70#endif
71
72static constexpr llvm::StringTable
73XCoreSchedClassNames = XCoreSchedClassNamesStorage;
74
75static const llvm::MCSchedModel NoSchedModel = {
76 MCSchedModel::DefaultIssueWidth,
77 MCSchedModel::DefaultMicroOpBufferSize,
78 MCSchedModel::DefaultLoopMicroOpBufferSize,
79 MCSchedModel::DefaultLoadLatency,
80 MCSchedModel::DefaultHighLatency,
81 MCSchedModel::DefaultMispredictPenalty,
82 false, // PostRAScheduler
83 false, // CompleteModel
84 false, // EnableIntervals
85 0, // Processor ID
86 nullptr, nullptr, 0, 0, // No instruction-level machine model.
87 DBGVAL_OR_NULLPTR(&XCoreSchedClassNames), // SchedClassNames
88 nullptr, // No Itinerary
89 nullptr // No extra processor descriptor
90};
91
92#undef DBGFIELD
93
94#undef DBGVAL_OR_NULLPTR
95
96// Sorted (by key) array of values for CPU subtype.
97extern const llvm::SubtargetSubTypeKV XCoreSubTypeKV[] = {
98 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
99 { "xs1b-generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
100};
101
102// Sorted array of names of CPU subtypes, including aliases.
103extern const llvm::StringRef XCoreNames[] = {
104"generic",
105"xs1b-generic"};
106
107namespace XCore_MC {
108
109unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
110 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
111 // Don't know how to resolve this scheduling class.
112 return 0;
113}
114
115} // namespace XCore_MC
116struct XCoreGenMCSubtargetInfo : public MCSubtargetInfo {
117 XCoreGenMCSubtargetInfo(const Triple &TT,
118 StringRef CPU, StringRef TuneCPU, StringRef FS,
119 ArrayRef<StringRef> PN,
120 ArrayRef<SubtargetFeatureKV> PF,
121 ArrayRef<SubtargetSubTypeKV> PD,
122 const MCWriteProcResEntry *WPR,
123 const MCWriteLatencyEntry *WL,
124 const MCReadAdvanceEntry *RA, const InstrStage *IS,
125 const unsigned *OC, const unsigned *FP) :
126 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
127 WPR, WL, RA, IS, OC, FP) { }
128
129 unsigned resolveVariantSchedClass(unsigned SchedClass,
130 const MCInst *MI, const MCInstrInfo *MCII,
131 unsigned CPUID) const final {
132 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
133 }
134};
135
136static inline MCSubtargetInfo *createXCoreMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
137 return new XCoreGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, XCoreNames, {}, XCoreSubTypeKV,
138 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
139 nullptr, nullptr, nullptr);
140}
141
142
143} // namespace llvm
144
145#endif // GET_SUBTARGETINFO_MC_DESC
146
147#ifdef GET_SUBTARGETINFO_TARGET_DESC
148#undef GET_SUBTARGETINFO_TARGET_DESC
149
150#include "llvm/ADT/BitmaskEnum.h"
151#include "llvm/Support/Debug.h"
152#include "llvm/Support/raw_ostream.h"
153
154// ParseSubtargetFeatures - Parses features string setting specified
155// subtarget options.
156void llvm::XCoreSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
157 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
158 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
159 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
160}
161
162#endif // GET_SUBTARGETINFO_TARGET_DESC
163
164#ifdef GET_SUBTARGETINFO_HEADER
165#undef GET_SUBTARGETINFO_HEADER
166
167namespace llvm {
168
169class DFAPacketizer;
170namespace XCore_MC {
171
172unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
173
174} // namespace XCore_MC
175struct XCoreGenSubtargetInfo : public TargetSubtargetInfo {
176 explicit XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
177public:
178 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
179 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
180 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
181};
182
183} // namespace llvm
184
185#endif // GET_SUBTARGETINFO_HEADER
186
187#ifdef GET_SUBTARGETINFO_CTOR
188#undef GET_SUBTARGETINFO_CTOR
189
190#include "llvm/CodeGen/TargetSchedule.h"
191
192namespace llvm {
193
194extern const llvm::StringRef XCoreNames[];
195extern const llvm::SubtargetFeatureKV XCoreFeatureKV[];
196extern const llvm::SubtargetSubTypeKV XCoreSubTypeKV[];
197extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[];
198extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[];
199extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[];
200XCoreGenSubtargetInfo::XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
201 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(XCoreNames, 2), {}, ArrayRef(XCoreSubTypeKV, 2),
202 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
203 nullptr, nullptr, nullptr) {}
204
205unsigned XCoreGenSubtargetInfo
206::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
207 report_fatal_error("Expected a variant SchedClass");
208} // XCoreGenSubtargetInfo::resolveSchedClass
209
210unsigned XCoreGenSubtargetInfo
211::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
212 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
213} // XCoreGenSubtargetInfo::resolveVariantSchedClass
214
215
216} // namespace llvm
217
218#endif // GET_SUBTARGETINFO_CTOR
219
220#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
221#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
222
223
224#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
225
226#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
227#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
228
229
230#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
231
232