1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14
15} // namespace llvm
16
17#endif // GET_SUBTARGETINFO_ENUM
18
19#ifdef GET_SUBTARGETINFO_MACRO
20
21
22#undef GET_SUBTARGETINFO_MACRO
23#endif // GET_SUBTARGETINFO_MACRO
24
25#ifdef GET_SUBTARGETINFO_MC_DESC
26#undef GET_SUBTARGETINFO_MC_DESC
27
28namespace llvm {
29
30
31#ifdef DBGFIELD
32#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
33#endif
34#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35#define DBGFIELD(x) x,
36#define DBGVAL_OR_NULLPTR(x) x
37#else
38#define DBGFIELD(x)
39#define DBGVAL_OR_NULLPTR(x) nullptr
40#endif
41
42// ===============================================================
43// Data tables for the new per-operand machine model.
44
45static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
46static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
47
48// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
49extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[] = {
50 { 0, 0, 0 }, // Invalid
51}; // XCoreWriteProcResTable
52
53// {Cycles, WriteResourceID}
54extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[] = {
55 { 0, 0}, // Invalid
56}; // XCoreWriteLatencyTable
57
58// {UseIdx, WriteResourceID, Cycles}
59extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[] = {
60 {0, 0, 0}, // Invalid
61}; // XCoreReadAdvanceTable
62
63#ifdef __GNUC__
64#pragma GCC diagnostic push
65#pragma GCC diagnostic ignored "-Woverlength-strings"
66#endif
67static constexpr char XCoreSchedClassNamesStorage[] =
68 "\0"
69 "InvalidSchedClass\0"
70 ;
71#ifdef __GNUC__
72#pragma GCC diagnostic pop
73#endif
74
75static constexpr llvm::StringTable
76XCoreSchedClassNames = XCoreSchedClassNamesStorage;
77
78extern const llvm::MCSchedModel XCoreSchedModels[] = {
79{ // NoSchedModel
80 MCSchedModel::DefaultIssueWidth,
81 MCSchedModel::DefaultMicroOpBufferSize,
82 MCSchedModel::DefaultLoopMicroOpBufferSize,
83 MCSchedModel::DefaultLoadLatency,
84 MCSchedModel::DefaultHighLatency,
85 MCSchedModel::DefaultMispredictPenalty,
86 false, // PostRAScheduler
87 false, // CompleteModel
88 false, // EnableIntervals
89 0, // Processor ID
90 nullptr, nullptr, 0, 0, // No instruction-level machine model.
91 DBGVAL_OR_NULLPTR(&XCoreSchedClassNames), // SchedClassNames
92 nullptr, // No Itinerary
93 nullptr // No extra processor descriptor
94 },
95};
96
97#undef DBGFIELD
98
99#undef DBGVAL_OR_NULLPTR
100
101// Sorted (by key) array of values for CPU subtype.
102extern const llvm::SubtargetSubTypeKVStorage< 2, 23> XCoreSubTypeKVStorage = {
103 {
104 { sizeof(SubtargetSubTypeKV) * 2 + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
105 { sizeof(SubtargetSubTypeKV) * 1 + 9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
106 },
107 "\000generic\000xs1b-generic\000"};
108
109namespace XCore_MC {
110
111unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
112 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
113 // Don't know how to resolve this scheduling class.
114 return 0;
115}
116
117} // namespace XCore_MC
118struct XCoreGenMCSubtargetInfo : public MCSubtargetInfo {
119 XCoreGenMCSubtargetInfo(const Triple &TT,
120 StringRef CPU, StringRef TuneCPU, StringRef FS,
121 StringTable PN,
122 ArrayRef<SubtargetFeatureKV> PF,
123 ArrayRef<SubtargetSubTypeKV> PD,
124 const MCSchedModel *PSM,
125 const MCWriteProcResEntry *WPR,
126 const MCWriteLatencyEntry *WL,
127 const MCReadAdvanceEntry *RA, const InstrStage *IS,
128 const unsigned *OC, const unsigned *FP) :
129 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
130 WPR, WL, RA, IS, OC, FP) { }
131
132 unsigned resolveVariantSchedClass(unsigned SchedClass,
133 const MCInst *MI, const MCInstrInfo *MCII,
134 unsigned CPUID) const final {
135 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
136 }
137};
138
139static inline MCSubtargetInfo *createXCoreMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
140 return new XCoreGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(XCoreSubTypeKVStorage.Strings), {}, XCoreSubTypeKVStorage.SubTypes, XCoreSchedModels,
141 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
142 nullptr, nullptr, nullptr);
143}
144
145
146} // namespace llvm
147
148#endif // GET_SUBTARGETINFO_MC_DESC
149
150#ifdef GET_SUBTARGETINFO_TARGET_DESC
151#undef GET_SUBTARGETINFO_TARGET_DESC
152
153#include "llvm/ADT/BitmaskEnum.h"
154#include "llvm/Support/Debug.h"
155#include "llvm/Support/raw_ostream.h"
156
157// ParseSubtargetFeatures - Parses features string setting specified
158// subtarget options.
159void llvm::XCoreSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
160 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
161 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
162 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
163}
164
165#endif // GET_SUBTARGETINFO_TARGET_DESC
166
167#ifdef GET_SUBTARGETINFO_HEADER
168#undef GET_SUBTARGETINFO_HEADER
169
170namespace llvm {
171
172class DFAPacketizer;
173namespace XCore_MC {
174
175unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
176
177} // namespace XCore_MC
178struct XCoreGenSubtargetInfo : public TargetSubtargetInfo {
179 explicit XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
180public:
181 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
182 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
183 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
184 const FeatureBitset &getInlineIgnoreFeatures() const override;
185 const FeatureBitset &getInlineInverseFeatures() const override;
186 const FeatureBitset &getInlineMustMatchFeatures() const override;
187};
188
189} // namespace llvm
190
191#endif // GET_SUBTARGETINFO_HEADER
192
193#ifdef GET_SUBTARGETINFO_CTOR
194#undef GET_SUBTARGETINFO_CTOR
195
196#include "llvm/CodeGen/TargetSchedule.h"
197
198namespace llvm {
199
200extern const llvm::StringRef XCoreNames[];
201extern const llvm::SubtargetSubTypeKVStorage<2, 23> XCoreSubTypeKVStorage;
202extern const llvm::MCSchedModel XCoreSchedModels[];
203extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[];
204extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[];
205extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[];
206XCoreGenSubtargetInfo::XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
207 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(XCoreSubTypeKVStorage.Strings), {}, ArrayRef(XCoreSubTypeKVStorage.SubTypes), XCoreSchedModels,
208 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
209 nullptr, nullptr, nullptr) {}
210
211unsigned XCoreGenSubtargetInfo
212::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
213 report_fatal_error("Expected a variant SchedClass");
214} // XCoreGenSubtargetInfo::resolveSchedClass
215
216unsigned XCoreGenSubtargetInfo
217::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
218 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
219} // XCoreGenSubtargetInfo::resolveVariantSchedClass
220
221const FeatureBitset &XCoreGenSubtargetInfo::getInlineIgnoreFeatures() const {
222 static constexpr FeatureBitset Features = {
223 };
224 return Features;
225}
226
227const FeatureBitset &XCoreGenSubtargetInfo::getInlineInverseFeatures() const {
228 static constexpr FeatureBitset Features = {
229 };
230 return Features;
231}
232
233const FeatureBitset &XCoreGenSubtargetInfo::getInlineMustMatchFeatures() const {
234 static constexpr FeatureBitset Features = {
235 };
236 return Features;
237}
238
239
240} // namespace llvm
241
242#endif // GET_SUBTARGETINFO_CTOR
243
244#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
245#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
246
247
248#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
249
250#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
251#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
252
253
254#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
255
256