1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14
15} // namespace llvm
16
17#endif // GET_SUBTARGETINFO_ENUM
18
19#ifdef GET_SUBTARGETINFO_MACRO
20
21
22#undef GET_SUBTARGETINFO_MACRO
23#endif // GET_SUBTARGETINFO_MACRO
24
25#ifdef GET_SUBTARGETINFO_MC_DESC
26#undef GET_SUBTARGETINFO_MC_DESC
27
28namespace llvm {
29
30
31#ifdef DBGFIELD
32#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
33#endif
34#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35#define DBGFIELD(x) x,
36#define DBGVAL_OR_NULLPTR(x) x
37#else
38#define DBGFIELD(x)
39#define DBGVAL_OR_NULLPTR(x) nullptr
40#endif
41
42// ===============================================================
43// Data tables for the new per-operand machine model.
44
45static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
46static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
47
48// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
49extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[] = {
50 { 0, 0, 0 }, // Invalid
51}; // XCoreWriteProcResTable
52
53// {Cycles, WriteResourceID}
54extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[] = {
55 { 0, 0}, // Invalid
56}; // XCoreWriteLatencyTable
57
58// {UseIdx, WriteResourceID, Cycles}
59extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[] = {
60 {0, 0, 0}, // Invalid
61}; // XCoreReadAdvanceTable
62
63#ifdef __GNUC__
64#pragma GCC diagnostic push
65#pragma GCC diagnostic ignored "-Woverlength-strings"
66#endif
67static constexpr char XCoreSchedClassNamesStorage[] =
68 "\0"
69 "InvalidSchedClass\0"
70 ;
71#ifdef __GNUC__
72#pragma GCC diagnostic pop
73#endif
74
75static constexpr llvm::StringTable
76XCoreSchedClassNames = XCoreSchedClassNamesStorage;
77
78extern const llvm::MCSchedModel XCoreSchedModels[] = {
79{ // NoSchedModel
80 MCSchedModel::DefaultIssueWidth,
81 MCSchedModel::DefaultMicroOpBufferSize,
82 MCSchedModel::DefaultLoopMicroOpBufferSize,
83 MCSchedModel::DefaultLoadLatency,
84 MCSchedModel::DefaultHighLatency,
85 MCSchedModel::DefaultMispredictPenalty,
86 false, // PostRAScheduler
87 false, // CompleteModel
88 false, // EnableIntervals
89 0, // Processor ID
90 nullptr, nullptr, 0, 0, // No instruction-level machine model.
91 DBGVAL_OR_NULLPTR(&XCoreSchedClassNames), // SchedClassNames
92 nullptr, // No Itinerary
93 nullptr // No extra processor descriptor
94 },
95};
96
97#undef DBGFIELD
98
99#undef DBGVAL_OR_NULLPTR
100
101static constexpr size_t XCoreCPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 0>);
102// Sorted (by key) array of values for CPU subtype.
103extern const llvm::SubtargetSubTypeKVStorage< 2, 0, 23> XCoreSubTypeKVStorage = {
104 {
105 { sizeof(SubtargetSubTypeKV) * 2 + XCoreCPUAliasArraySize + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
106 { sizeof(SubtargetSubTypeKV) * 1 + XCoreCPUAliasArraySize + 9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
107 },
108 { {
109 } },
110 "\000generic\000xs1b-generic\000"};
111
112namespace XCore_MC {
113
114unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
115 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
116 // Don't know how to resolve this scheduling class.
117 return 0;
118}
119
120} // namespace XCore_MC
121struct XCoreGenMCSubtargetInfo : public MCSubtargetInfo {
122 XCoreGenMCSubtargetInfo(const Triple &TT,
123 StringRef CPU, StringRef TuneCPU, StringRef FS,
124 StringTable PN,
125 ArrayRef<SubtargetFeatureKV> PF,
126 ArrayRef<SubtargetSubTypeKV> PD,
127 ArrayRef<SubtargetSubTypeAliasKV> PA,
128 const MCSchedModel *PSM,
129 const MCWriteProcResEntry *WPR,
130 const MCWriteLatencyEntry *WL,
131 const MCReadAdvanceEntry *RA, const InstrStage *IS,
132 const unsigned *OC, const unsigned *FP) :
133 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
134 WPR, WL, RA, IS, OC, FP) { }
135
136 unsigned resolveVariantSchedClass(unsigned SchedClass,
137 const MCInst *MI, const MCInstrInfo *MCII,
138 unsigned CPUID) const final {
139 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
140 }
141};
142
143static inline MCSubtargetInfo *createXCoreMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
144 return new XCoreGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(XCoreSubTypeKVStorage.Strings), {}, XCoreSubTypeKVStorage.SubTypes, ArrayRef(XCoreSubTypeKVStorage.Aliases).take_front(0), XCoreSchedModels,
145 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
146 nullptr, nullptr, nullptr);
147}
148
149
150} // namespace llvm
151
152#endif // GET_SUBTARGETINFO_MC_DESC
153
154#ifdef GET_SUBTARGETINFO_TARGET_DESC
155#undef GET_SUBTARGETINFO_TARGET_DESC
156
157#include "llvm/ADT/BitmaskEnum.h"
158#include "llvm/Support/Debug.h"
159#include "llvm/Support/raw_ostream.h"
160
161// ParseSubtargetFeatures - Parses features string setting specified
162// subtarget options.
163void llvm::XCoreSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
164 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
165 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
166 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
167}
168
169#endif // GET_SUBTARGETINFO_TARGET_DESC
170
171#ifdef GET_SUBTARGETINFO_HEADER
172#undef GET_SUBTARGETINFO_HEADER
173
174namespace llvm {
175
176class DFAPacketizer;
177namespace XCore_MC {
178
179unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
180
181} // namespace XCore_MC
182struct XCoreGenSubtargetInfo : public TargetSubtargetInfo {
183 explicit XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
184public:
185 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
186 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
187 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
188 const FeatureBitset &getInlineIgnoreFeatures() const override;
189 const FeatureBitset &getInlineInverseFeatures() const override;
190 const FeatureBitset &getInlineMustMatchFeatures() const override;
191};
192
193} // namespace llvm
194
195#endif // GET_SUBTARGETINFO_HEADER
196
197#ifdef GET_SUBTARGETINFO_CTOR
198#undef GET_SUBTARGETINFO_CTOR
199
200#include "llvm/CodeGen/TargetSchedule.h"
201
202namespace llvm {
203
204extern const llvm::StringRef XCoreNames[];
205extern const llvm::SubtargetSubTypeKVStorage<2, 0, 23> XCoreSubTypeKVStorage;
206extern const llvm::MCSchedModel XCoreSchedModels[];
207extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[];
208extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[];
209extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[];
210XCoreGenSubtargetInfo::XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
211 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(XCoreSubTypeKVStorage.Strings), {}, ArrayRef(XCoreSubTypeKVStorage.SubTypes), ArrayRef(XCoreSubTypeKVStorage.Aliases).take_front(0), XCoreSchedModels,
212 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
213 nullptr, nullptr, nullptr) {}
214
215unsigned XCoreGenSubtargetInfo
216::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
217 report_fatal_error("Expected a variant SchedClass");
218} // XCoreGenSubtargetInfo::resolveSchedClass
219
220unsigned XCoreGenSubtargetInfo
221::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
222 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
223} // XCoreGenSubtargetInfo::resolveVariantSchedClass
224
225const FeatureBitset &XCoreGenSubtargetInfo::getInlineIgnoreFeatures() const {
226 static constexpr FeatureBitset Features = {
227 };
228 return Features;
229}
230
231const FeatureBitset &XCoreGenSubtargetInfo::getInlineInverseFeatures() const {
232 static constexpr FeatureBitset Features = {
233 };
234 return Features;
235}
236
237const FeatureBitset &XCoreGenSubtargetInfo::getInlineMustMatchFeatures() const {
238 static constexpr FeatureBitset Features = {
239 };
240 return Features;
241}
242
243
244} // namespace llvm
245
246#endif // GET_SUBTARGETINFO_CTOR
247
248#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
249#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
250
251
252#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
253
254#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
255#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
256
257
258#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
259
260