1//===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares AMDGPU TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
15
16#include "clang/Basic/TargetID.h"
17#include "clang/Basic/TargetInfo.h"
18#include "clang/Basic/TargetOptions.h"
19#include "llvm/ADT/StringSet.h"
20#include "llvm/Support/AMDGPUAddrSpace.h"
21#include "llvm/Support/Compiler.h"
22#include "llvm/TargetParser/AMDGPUTargetParser.h"
23#include "llvm/TargetParser/Triple.h"
24#include <optional>
25
26namespace clang {
27namespace targets {
28
29class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
30
31 static const char *const GCCRegNames[];
32
33 static const LangASMap AMDGPUAddrSpaceMap;
34
35 llvm::AMDGPU::GPUKind GPUKind;
36 unsigned WavefrontSize;
37
38 /// Whether to use cumode or WGP mode. True for cumode. False for WGP mode.
39 bool CUMode;
40
41 /// Whether having image instructions.
42 bool HasImage = false;
43
44 /// Target ID is device name followed by optional feature name postfixed
45 /// by plus or minus sign delimitted by colon, e.g. gfx908:xnack+:sramecc-.
46 /// If the target ID contains feature+, map it to true.
47 /// If the target ID contains feature-, map it to false.
48 /// If the target ID does not contain a feature (default), do not map it.
49 llvm::StringMap<bool> OffloadArchFeatures;
50 std::string TargetID;
51
52 bool hasFP64() const { return getTriple().isAMDGCN(); }
53
54 /// Has fast fma f32
55 bool hasFastFMAF() const {
56 return getTriple().isAMDGCN() &&
57 llvm::AMDGPU::getFeatureBitset(AK: GPUKind).test(
58 I: llvm::AMDGPU::FEAT_FAST_FMAF);
59 }
60
61 /// Has fast fma f64
62 bool hasFastFMA() const { return getTriple().isAMDGCN(); }
63
64 bool hasFMAF() const {
65 return getTriple().isAMDGCN() ||
66 llvm::AMDGPU::getFeatureBitsetR600(AK: GPUKind).test(
67 I: llvm::AMDGPU::R600_FEAT_FMAF);
68 }
69
70 bool hasFullRateDenormalsF32() const {
71 return getTriple().isAMDGCN() &&
72 llvm::AMDGPU::getFeatureBitset(AK: GPUKind).test(
73 I: llvm::AMDGPU::FEAT_FAST_DENORMAL_F32);
74 }
75
76 bool hasLDEXPF() const { return getTriple().isAMDGCN(); }
77
78 static bool isR600(const llvm::Triple &TT) {
79 return TT.getArch() == llvm::Triple::r600;
80 }
81
82 bool hasFlatSupport() const {
83 if (GPUKind >= llvm::AMDGPU::GK_GFX700)
84 return true;
85
86 // Dummy target is assumed to be gfx700+ for amdhsa.
87 if (GPUKind == llvm::AMDGPU::GK_NONE &&
88 getTriple().getOS() == llvm::Triple::AMDHSA)
89 return true;
90
91 return false;
92 }
93
94public:
95 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
96
97 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts,
98 const TargetInfo *Aux) override;
99
100 uint64_t getPointerWidthV(LangAS AS) const override {
101 if (isR600(TT: getTriple()))
102 return 32;
103 unsigned TargetAS = getTargetAddressSpace(AS);
104
105 if (TargetAS == llvm::AMDGPUAS::PRIVATE_ADDRESS ||
106 TargetAS == llvm::AMDGPUAS::LOCAL_ADDRESS)
107 return 32;
108
109 return 64;
110 }
111
112 uint64_t getPointerAlignV(LangAS AddrSpace) const override {
113 return getPointerWidthV(AS: AddrSpace);
114 }
115
116 virtual bool isAddressSpaceSupersetOf(LangAS A, LangAS B) const override {
117 // The flat address space AS(0) is a superset of all the other address
118 // spaces used by the backend target.
119 return A == B ||
120 ((A == LangAS::Default ||
121 (isTargetAddressSpace(AS: A) &&
122 toTargetAddressSpace(AS: A) == llvm::AMDGPUAS::FLAT_ADDRESS)) &&
123 isTargetAddressSpace(AS: B) &&
124 toTargetAddressSpace(AS: B) >= llvm::AMDGPUAS::FLAT_ADDRESS &&
125 toTargetAddressSpace(AS: B) <= llvm::AMDGPUAS::PRIVATE_ADDRESS &&
126 toTargetAddressSpace(AS: B) != llvm::AMDGPUAS::REGION_ADDRESS);
127 }
128
129 uint64_t getMaxPointerWidth() const override {
130 return getTriple().isAMDGCN() ? 64 : 32;
131 }
132
133 bool hasBFloat16Type() const override { return getTriple().isAMDGCN(); }
134
135 std::string_view getClobbers() const override { return ""; }
136
137 ArrayRef<const char *> getGCCRegNames() const override;
138
139 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
140 return {};
141 }
142
143 /// Accepted register names: (n, m is unsigned integer, n < m)
144 /// v
145 /// s
146 /// a
147 /// {vn}, {v[n]}
148 /// {sn}, {s[n]}
149 /// {an}, {a[n]}
150 /// {S} , where S is a special register name
151 ////{v[n:m]}
152 /// {s[n:m]}
153 /// {a[n:m]}
154 bool validateAsmConstraint(const char *&Name,
155 TargetInfo::ConstraintInfo &Info) const override {
156 static const ::llvm::StringSet<> SpecialRegs({
157 "exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma",
158 "flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo",
159 "exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi",
160 });
161
162 switch (*Name) {
163 case 'I':
164 Info.setRequiresImmediate(Min: -16, Max: 64);
165 return true;
166 case 'J':
167 Info.setRequiresImmediate(Min: -32768, Max: 32767);
168 return true;
169 case 'A':
170 case 'B':
171 case 'C':
172 Info.setRequiresImmediate();
173 return true;
174 default:
175 break;
176 }
177
178 StringRef S(Name);
179
180 if (S == "DA" || S == "DB") {
181 Name++;
182 Info.setRequiresImmediate();
183 return true;
184 }
185
186 bool HasLeftParen = S.consume_front(Prefix: "{");
187 if (S.empty())
188 return false;
189 if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') {
190 if (!HasLeftParen)
191 return false;
192 auto E = S.find(C: '}');
193 if (!SpecialRegs.count(Key: S.substr(Start: 0, N: E)))
194 return false;
195 S = S.drop_front(N: E + 1);
196 if (!S.empty())
197 return false;
198 // Found {S} where S is a special register.
199 Info.setAllowsRegister();
200 Name = S.data() - 1;
201 return true;
202 }
203 S = S.drop_front();
204 if (!HasLeftParen) {
205 if (!S.empty())
206 return false;
207 // Found s, v or a.
208 Info.setAllowsRegister();
209 Name = S.data() - 1;
210 return true;
211 }
212 bool HasLeftBracket = S.consume_front(Prefix: "[");
213 unsigned long long N;
214 if (S.empty() || consumeUnsignedInteger(Str&: S, Radix: 10, Result&: N))
215 return false;
216 if (S.consume_front(Prefix: ":")) {
217 if (!HasLeftBracket)
218 return false;
219 unsigned long long M;
220 if (consumeUnsignedInteger(Str&: S, Radix: 10, Result&: M) || N >= M)
221 return false;
222 }
223 if (HasLeftBracket) {
224 if (!S.consume_front(Prefix: "]"))
225 return false;
226 }
227 if (!S.consume_front(Prefix: "}"))
228 return false;
229 if (!S.empty())
230 return false;
231 // Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]}
232 // or {a[n:m]}.
233 Info.setAllowsRegister();
234 Name = S.data() - 1;
235 return true;
236 }
237
238 // \p Constraint will be left pointing at the last character of
239 // the constraint. In practice, it won't be changed unless the
240 // constraint is longer than one character.
241 std::string convertConstraint(const char *&Constraint) const override {
242
243 StringRef S(Constraint);
244 if (S == "DA" || S == "DB") {
245 return std::string("^") + std::string(Constraint++, 2);
246 }
247
248 const char *Begin = Constraint;
249 TargetInfo::ConstraintInfo Info("", "");
250 if (validateAsmConstraint(Name&: Constraint, Info))
251 return std::string(Begin).substr(pos: 0, n: Constraint - Begin + 1);
252
253 Constraint = Begin;
254 return std::string(1, *Constraint);
255 }
256
257 bool
258 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
259 StringRef CPU,
260 const std::vector<std::string> &FeatureVec) const override;
261
262 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
263
264 void getTargetDefines(const LangOptions &Opts,
265 MacroBuilder &Builder) const override;
266
267 BuiltinVaListKind getBuiltinVaListKind() const override {
268 return TargetInfo::CharPtrBuiltinVaList;
269 }
270
271 bool isValidCPUName(StringRef Name) const override {
272 if (getTriple().isAMDGCN()) {
273 return llvm::AMDGPU::isCPUValidForSubArch(SubArch: getTriple().getSubArch(),
274 CPU: Name) &&
275 !llvm::AMDGPU::isPseudoTarget(CPU: Name);
276 }
277 return llvm::AMDGPU::parseArchR600(CPU: Name) != llvm::AMDGPU::GK_NONE;
278 }
279
280 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
281
282 bool setCPU(StringRef Name) override {
283 if (getTriple().isAMDGCN()) {
284 GPUKind = llvm::AMDGPU::parseArchAMDGCN(CPU: Name);
285 return llvm::AMDGPU::isCPUValidForSubArch(SubArch: getTriple().getSubArch(),
286 AK: GPUKind) &&
287 !llvm::AMDGPU::isPseudoTarget(AK: GPUKind);
288 }
289 GPUKind = llvm::AMDGPU::parseArchR600(CPU: Name);
290 return GPUKind != llvm::AMDGPU::GK_NONE;
291 }
292
293 void setSupportedOpenCLOpts() override {
294 auto &Opts = getSupportedOpenCLOpts();
295 Opts["cl_clang_storage_class_specifiers"] = true;
296 Opts["__cl_clang_variadic_functions"] = true;
297 Opts["__cl_clang_function_pointers"] = true;
298 Opts["__cl_clang_function_scope_local_variables"] = true;
299 Opts["__cl_clang_non_portable_kernel_param_types"] = true;
300 Opts["__cl_clang_bitfields"] = true;
301
302 bool IsAMDGCN = getTriple().isAMDGCN();
303
304 Opts["cl_khr_fp64"] = hasFP64();
305 Opts["__opencl_c_fp64"] = hasFP64();
306
307 if (IsAMDGCN || GPUKind >= llvm::AMDGPU::GK_CEDAR) {
308 Opts["cl_khr_byte_addressable_store"] = true;
309 Opts["cl_khr_global_int32_base_atomics"] = true;
310 Opts["cl_khr_global_int32_extended_atomics"] = true;
311 Opts["cl_khr_local_int32_base_atomics"] = true;
312 Opts["cl_khr_local_int32_extended_atomics"] = true;
313 }
314
315 if (IsAMDGCN) {
316 Opts["cl_khr_fp16"] = true;
317 Opts["cl_khr_int64_base_atomics"] = true;
318 Opts["cl_khr_int64_extended_atomics"] = true;
319 Opts["cl_khr_mipmap_image"] = true;
320 Opts["cl_khr_mipmap_image_writes"] = true;
321 Opts["cl_khr_subgroups"] = true;
322 Opts["cl_amd_media_ops"] = true;
323 Opts["cl_amd_media_ops2"] = true;
324
325 // FIXME: Check subtarget for image support.
326 Opts["__opencl_c_images"] = true;
327 Opts["__opencl_c_3d_image_writes"] = true;
328 Opts["__opencl_c_read_write_images"] = true;
329 Opts["cl_khr_3d_image_writes"] = true;
330 Opts["__opencl_c_program_scope_global_variables"] = true;
331 Opts["__opencl_c_atomic_order_acq_rel"] = true;
332 Opts["__opencl_c_atomic_order_seq_cst"] = true;
333 Opts["__opencl_c_atomic_scope_device"] = true;
334 Opts["__opencl_c_atomic_scope_all_devices"] = true;
335 Opts["__opencl_c_work_group_collective_functions"] = true;
336
337 if (hasFlatSupport()) {
338 Opts["__opencl_c_generic_address_space"] = true;
339 Opts["__opencl_c_device_enqueue"] = true;
340 Opts["__opencl_c_pipes"] = true;
341 }
342
343 if (getTriple().getEnvironment() == llvm::Triple::LLVM) {
344 Opts["cl_khr_subgroup_extended_types"] = true;
345 }
346 }
347 }
348
349 LangAS getOpenCLTypeAddrSpace(OpenCLTypeKind TK) const override {
350 switch (TK) {
351 case OCLTK_Image:
352 return LangAS::opencl_constant;
353
354 case OCLTK_ClkEvent:
355 case OCLTK_Queue:
356 case OCLTK_ReserveID:
357 return LangAS::opencl_global;
358
359 default:
360 return TargetInfo::getOpenCLTypeAddrSpace(TK);
361 }
362 }
363
364 LangAS getOpenCLBuiltinAddressSpace(unsigned AS) const override {
365 switch (AS) {
366 case 0:
367 return LangAS::opencl_generic;
368 case 1:
369 return LangAS::opencl_global;
370 case 3:
371 return LangAS::opencl_local;
372 case 4:
373 return LangAS::opencl_constant;
374 case 5:
375 return LangAS::opencl_private;
376 default:
377 return getLangASFromTargetAS(TargetAS: AS);
378 }
379 }
380
381 LangAS getCUDABuiltinAddressSpace(unsigned AS) const override {
382 switch (AS) {
383 case 0:
384 return LangAS::Default;
385 case 1:
386 return LangAS::cuda_device;
387 case 3:
388 return LangAS::cuda_shared;
389 case 4:
390 return LangAS::cuda_constant;
391 default:
392 return getLangASFromTargetAS(TargetAS: AS);
393 }
394 }
395
396 std::optional<LangAS> getConstantAddressSpace() const override {
397 return getLangASFromTargetAS(TargetAS: llvm::AMDGPUAS::CONSTANT_ADDRESS);
398 }
399
400 const llvm::omp::GV &getGridValue() const override {
401 switch (WavefrontSize) {
402 case 32:
403 return llvm::omp::getAMDGPUGridValues<32>();
404 case 64:
405 return llvm::omp::getAMDGPUGridValues<64>();
406 default:
407 llvm_unreachable("getGridValue not implemented for this wavesize");
408 }
409 }
410
411 /// \returns Target specific vtbl ptr address space.
412 unsigned getVtblPtrAddressSpace() const override {
413 return static_cast<unsigned>(llvm::AMDGPUAS::CONSTANT_ADDRESS);
414 }
415
416 /// \returns If a target requires an address within a target specific address
417 /// space \p AddressSpace to be converted in order to be used, then return the
418 /// corresponding target specific DWARF address space.
419 ///
420 /// \returns Otherwise return std::nullopt and no conversion will be emitted
421 /// in the DWARF.
422 std::optional<unsigned>
423 getDWARFAddressSpace(unsigned AddressSpace) const override {
424 int DWARFAS = llvm::AMDGPU::mapToDWARFAddrSpace(LLVMAddrSpace: AddressSpace);
425 // If there is no corresponding address space identifier, or it would be
426 // the default, then don't emit the attribute.
427 if (DWARFAS == -1 || DWARFAS == llvm::AMDGPU::DWARFAS::DEFAULT)
428 return std::nullopt;
429 return DWARFAS;
430 }
431
432 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
433 switch (CC) {
434 default:
435 return CCCR_Warning;
436 case CC_C:
437 case CC_DeviceKernel:
438 return CCCR_OK;
439 }
440 }
441
442 // In amdgcn target the null pointer in global, constant, and generic
443 // address space has value 0 but in private and local address space has
444 // value ~0.
445 uint64_t getNullPointerValue(LangAS AS) const override {
446 // Check language-specific address spaces
447 if (AS == LangAS::opencl_local || AS == LangAS::opencl_private ||
448 AS == LangAS::sycl_local || AS == LangAS::sycl_private)
449 return ~0;
450 if (isTargetAddressSpace(AS))
451 return llvm::AMDGPU::getNullPointerValue(AS: toTargetAddressSpace(AS));
452 return 0;
453 }
454
455 void setAuxTarget(const TargetInfo *Aux) override;
456
457 bool hasBitIntType() const override { return true; }
458
459 // Record offload arch features since they are needed for defining the
460 // pre-defined macros.
461 bool handleTargetFeatures(std::vector<std::string> &Features,
462 DiagnosticsEngine &Diags) override {
463 HasFullBFloat16 = true;
464 auto TargetIDFeatures =
465 getAllPossibleTargetIDFeatures(T: getTriple(), Processor: getArchNameAMDGCN(AK: GPUKind));
466 for (const auto &F : Features) {
467 assert(F.front() == '+' || F.front() == '-');
468 if (F == "+wavefrontsize64")
469 WavefrontSize = 64;
470 else if (F == "+cumode")
471 CUMode = true;
472 else if (F == "-cumode")
473 CUMode = false;
474 else if (F == "+image-insts")
475 HasImage = true;
476 bool IsOn = F.front() == '+';
477 StringRef Name = StringRef(F).drop_front();
478 if (!llvm::is_contained(Range&: TargetIDFeatures, Element: Name))
479 continue;
480 assert(!OffloadArchFeatures.contains(Name));
481 OffloadArchFeatures[Name] = IsOn;
482 }
483 return true;
484 }
485
486 bool isProcessorName(StringRef Name) const override {
487 llvm::AMDGPU::GPUKind NameKind = getTriple().isAMDGCN()
488 ? llvm::AMDGPU::parseArchAMDGCN(CPU: Name)
489 : llvm::AMDGPU::parseArchR600(CPU: Name);
490 return NameKind == GPUKind;
491 }
492
493 bool hasHIPImageSupport() const override { return HasImage; }
494
495 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
496 // This is imprecise as the value can vary between 64, 128 (even 256!) bytes
497 // depending on the level of cache and the target architecture. We select
498 // the size that corresponds to the largest L1 cache line for all
499 // architectures.
500 return std::make_pair(x: 128, y: 128);
501 }
502};
503
504} // namespace targets
505} // namespace clang
506
507#endif // LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
508