1//===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares Hexagon TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
15
16#include "clang/Basic/TargetInfo.h"
17#include "clang/Basic/TargetOptions.h"
18#include "llvm/Support/Compiler.h"
19#include "llvm/TargetParser/Triple.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// Hexagon abstract base class
26class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
27
28 static const char *const GCCRegNames[];
29 static const TargetInfo::GCCRegAlias GCCRegAliases[];
30 std::string CPU;
31 std::string HVXVersion;
32 bool HasHVX = false;
33 bool HasHVX64B = false;
34 bool HasHVX128B = false;
35 bool HasHVXIeeeFp = false;
36 bool HasAudio = false;
37 bool UseLongCalls = false;
38
39public:
40 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
41 : TargetInfo(Triple) {
42 resetDataLayout();
43 SizeType = UnsignedInt;
44 PtrDiffType = SignedInt;
45 IntPtrType = SignedInt;
46
47 // {} in inline assembly are packet specifiers, not assembly variant
48 // specifiers.
49 NoAsmVariants = true;
50
51 LargeArrayMinWidth = 64;
52 LargeArrayAlign = 64;
53 UseBitFieldTypeAlignment = true;
54 ZeroLengthBitfieldBoundary = 32;
55 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
56
57 // These are the default values anyway, but explicitly make sure
58 // that the size of the boolean type is 8 bits. Bool vectors are used
59 // for modeling predicate registers in HVX, and the bool -> byte
60 // correspondence matches the HVX architecture.
61 BoolWidth = BoolAlign = 8;
62 BFloat16Width = BFloat16Align = 16;
63 BFloat16Format = &llvm::APFloat::BFloat();
64 }
65
66 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
67
68 bool validateAsmConstraint(const char *&Name,
69 TargetInfo::ConstraintInfo &Info) const override {
70 switch (*Name) {
71 case 'v':
72 case 'q':
73 if (HasHVX) {
74 Info.setAllowsRegister();
75 return true;
76 }
77 break;
78 case 'a': // Modifier register m0-m1.
79 Info.setAllowsRegister();
80 return true;
81 case 's':
82 // Relocatable constant.
83 return true;
84 }
85 return false;
86 }
87
88 void getTargetDefines(const LangOptions &Opts,
89 MacroBuilder &Builder) const override;
90
91 bool isCLZForZeroUndef() const override { return false; }
92
93 bool hasFeature(StringRef Feature) const override;
94
95 bool hasBFloat16Type() const override;
96
97 bool
98 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
99 StringRef CPU,
100 const std::vector<std::string> &FeaturesVec) const override;
101
102 bool handleTargetFeatures(std::vector<std::string> &Features,
103 DiagnosticsEngine &Diags) override;
104
105 BuiltinVaListKind getBuiltinVaListKind() const override {
106 if (getTriple().isMusl())
107 return TargetInfo::HexagonBuiltinVaList;
108 return TargetInfo::CharPtrBuiltinVaList;
109 }
110
111 ArrayRef<const char *> getGCCRegNames() const override;
112
113 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
114
115 std::string_view getClobbers() const override { return ""; }
116
117 static const char *getHexagonCPUSuffix(StringRef Name);
118 static std::optional<unsigned> getHexagonCPURev(StringRef Name);
119
120 bool isValidCPUName(StringRef Name) const override {
121 return getHexagonCPUSuffix(Name);
122 }
123
124 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
125
126 bool setCPU(const std::string &Name) override {
127 if (!isValidCPUName(Name))
128 return false;
129 CPU = Name;
130 return true;
131 }
132
133 int getEHDataRegisterNumber(unsigned RegNo) const override {
134 return RegNo < 2 ? RegNo : -1;
135 }
136
137 bool isTinyCore() const {
138 // We can write more stricter checks later.
139 return CPU.find(c: 't') != std::string::npos;
140 }
141
142 bool hasBitIntType() const override { return true; }
143
144 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
145 std::optional<unsigned> Rev = getHexagonCPURev(Name: CPU);
146
147 // V73 and later have 64-byte cache lines.
148 unsigned CacheLineSizeBytes = Rev >= 73U ? 64 : 32;
149 return std::make_pair(x&: CacheLineSizeBytes, y&: CacheLineSizeBytes);
150 }
151};
152} // namespace targets
153} // namespace clang
154#endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
155