1//===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares Hexagon TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
15
16#include "clang/Basic/TargetInfo.h"
17#include "clang/Basic/TargetOptions.h"
18#include "llvm/Support/Compiler.h"
19#include "llvm/TargetParser/Triple.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// Hexagon abstract base class
26class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
27
28 static const char *const GCCRegNames[];
29 static const TargetInfo::GCCRegAlias GCCRegAliases[];
30 std::string CPU;
31 std::string HVXVersion;
32 bool HasHVX = false;
33 bool HasHVX64B = false;
34 bool HasHVX128B = false;
35 bool HasAudio = false;
36 bool UseLongCalls = false;
37
38public:
39 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
40 : TargetInfo(Triple) {
41 resetDataLayout();
42 SizeType = UnsignedInt;
43 PtrDiffType = SignedInt;
44 IntPtrType = SignedInt;
45
46 // {} in inline assembly are packet specifiers, not assembly variant
47 // specifiers.
48 NoAsmVariants = true;
49
50 LargeArrayMinWidth = 64;
51 LargeArrayAlign = 64;
52 UseBitFieldTypeAlignment = true;
53 ZeroLengthBitfieldBoundary = 32;
54 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
55
56 // These are the default values anyway, but explicitly make sure
57 // that the size of the boolean type is 8 bits. Bool vectors are used
58 // for modeling predicate registers in HVX, and the bool -> byte
59 // correspondence matches the HVX architecture.
60 BoolWidth = BoolAlign = 8;
61 BFloat16Width = BFloat16Align = 16;
62 BFloat16Format = &llvm::APFloat::BFloat();
63 }
64
65 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
66
67 bool validateAsmConstraint(const char *&Name,
68 TargetInfo::ConstraintInfo &Info) const override {
69 switch (*Name) {
70 case 'v':
71 case 'q':
72 if (HasHVX) {
73 Info.setAllowsRegister();
74 return true;
75 }
76 break;
77 case 'a': // Modifier register m0-m1.
78 Info.setAllowsRegister();
79 return true;
80 case 's':
81 // Relocatable constant.
82 return true;
83 }
84 return false;
85 }
86
87 void getTargetDefines(const LangOptions &Opts,
88 MacroBuilder &Builder) const override;
89
90 bool isCLZForZeroUndef() const override { return false; }
91
92 bool hasFeature(StringRef Feature) const override;
93
94 bool hasBFloat16Type() const override;
95
96 bool
97 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
98 StringRef CPU,
99 const std::vector<std::string> &FeaturesVec) const override;
100
101 bool handleTargetFeatures(std::vector<std::string> &Features,
102 DiagnosticsEngine &Diags) override;
103
104 BuiltinVaListKind getBuiltinVaListKind() const override {
105 if (getTriple().isMusl())
106 return TargetInfo::HexagonBuiltinVaList;
107 return TargetInfo::CharPtrBuiltinVaList;
108 }
109
110 ArrayRef<const char *> getGCCRegNames() const override;
111
112 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
113
114 std::string_view getClobbers() const override { return ""; }
115
116 static const char *getHexagonCPUSuffix(StringRef Name);
117 static std::optional<unsigned> getHexagonCPURev(StringRef Name);
118
119 bool isValidCPUName(StringRef Name) const override {
120 return getHexagonCPUSuffix(Name);
121 }
122
123 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
124
125 bool setCPU(const std::string &Name) override {
126 if (!isValidCPUName(Name))
127 return false;
128 CPU = Name;
129 return true;
130 }
131
132 int getEHDataRegisterNumber(unsigned RegNo) const override {
133 return RegNo < 2 ? RegNo : -1;
134 }
135
136 bool isTinyCore() const {
137 // We can write more stricter checks later.
138 return CPU.find(c: 't') != std::string::npos;
139 }
140
141 bool hasBitIntType() const override { return true; }
142
143 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
144 std::optional<unsigned> Rev = getHexagonCPURev(Name: CPU);
145
146 // V73 and later have 64-byte cache lines.
147 unsigned CacheLineSizeBytes = Rev >= 73U ? 64 : 32;
148 return std::make_pair(x&: CacheLineSizeBytes, y&: CacheLineSizeBytes);
149 }
150};
151} // namespace targets
152} // namespace clang
153#endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
154