1//===--- LoongArch.cpp - Implement LoongArch target feature support -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements LoongArch TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArch.h"
14#include "clang/Basic/Diagnostic.h"
15#include "clang/Basic/MacroBuilder.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/TargetParser/LoongArchTargetParser.h"
18
19using namespace clang;
20using namespace clang::targets;
21
22ArrayRef<const char *> LoongArchTargetInfo::getGCCRegNames() const {
23 static const char *const GCCRegNames[] = {
24 // General purpose registers.
25 "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", "$r8", "$r9",
26 "$r10", "$r11", "$r12", "$r13", "$r14", "$r15", "$r16", "$r17", "$r18",
27 "$r19", "$r20", "$r21", "$r22", "$r23", "$r24", "$r25", "$r26", "$r27",
28 "$r28", "$r29", "$r30", "$r31",
29 // Floating point registers.
30 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
31 "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
32 "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
33 "$f28", "$f29", "$f30", "$f31",
34 // Condition flag registers.
35 "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7",
36 // 128-bit vector registers.
37 "$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6", "$vr7", "$vr8",
38 "$vr9", "$vr10", "$vr11", "$vr12", "$vr13", "$vr14", "$vr15", "$vr16",
39 "$vr17", "$vr18", "$vr19", "$vr20", "$vr21", "$vr22", "$vr23", "$vr24",
40 "$vr25", "$vr26", "$vr27", "$vr28", "$vr29", "$vr30", "$vr31",
41 // 256-bit vector registers.
42 "$xr0", "$xr1", "$xr2", "$xr3", "$xr4", "$xr5", "$xr6", "$xr7", "$xr8",
43 "$xr9", "$xr10", "$xr11", "$xr12", "$xr13", "$xr14", "$xr15", "$xr16",
44 "$xr17", "$xr18", "$xr19", "$xr20", "$xr21", "$xr22", "$xr23", "$xr24",
45 "$xr25", "$xr26", "$xr27", "$xr28", "$xr29", "$xr30", "$xr31"};
46 return llvm::ArrayRef(GCCRegNames);
47}
48
49ArrayRef<TargetInfo::GCCRegAlias>
50LoongArchTargetInfo::getGCCRegAliases() const {
51 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
52 {.Aliases: {"zero", "$zero", "r0"}, .Register: "$r0"},
53 {.Aliases: {"ra", "$ra", "r1"}, .Register: "$r1"},
54 {.Aliases: {"tp", "$tp", "r2"}, .Register: "$r2"},
55 {.Aliases: {"sp", "$sp", "r3"}, .Register: "$r3"},
56 {.Aliases: {"a0", "$a0", "r4"}, .Register: "$r4"},
57 {.Aliases: {"a1", "$a1", "r5"}, .Register: "$r5"},
58 {.Aliases: {"a2", "$a2", "r6"}, .Register: "$r6"},
59 {.Aliases: {"a3", "$a3", "r7"}, .Register: "$r7"},
60 {.Aliases: {"a4", "$a4", "r8"}, .Register: "$r8"},
61 {.Aliases: {"a5", "$a5", "r9"}, .Register: "$r9"},
62 {.Aliases: {"a6", "$a6", "r10"}, .Register: "$r10"},
63 {.Aliases: {"a7", "$a7", "r11"}, .Register: "$r11"},
64 {.Aliases: {"t0", "$t0", "r12"}, .Register: "$r12"},
65 {.Aliases: {"t1", "$t1", "r13"}, .Register: "$r13"},
66 {.Aliases: {"t2", "$t2", "r14"}, .Register: "$r14"},
67 {.Aliases: {"t3", "$t3", "r15"}, .Register: "$r15"},
68 {.Aliases: {"t4", "$t4", "r16"}, .Register: "$r16"},
69 {.Aliases: {"t5", "$t5", "r17"}, .Register: "$r17"},
70 {.Aliases: {"t6", "$t6", "r18"}, .Register: "$r18"},
71 {.Aliases: {"t7", "$t7", "r19"}, .Register: "$r19"},
72 {.Aliases: {"t8", "$t8", "r20"}, .Register: "$r20"},
73 {.Aliases: {"r21"}, .Register: "$r21"},
74 {.Aliases: {"s9", "$s9", "r22", "fp", "$fp"}, .Register: "$r22"},
75 {.Aliases: {"s0", "$s0", "r23"}, .Register: "$r23"},
76 {.Aliases: {"s1", "$s1", "r24"}, .Register: "$r24"},
77 {.Aliases: {"s2", "$s2", "r25"}, .Register: "$r25"},
78 {.Aliases: {"s3", "$s3", "r26"}, .Register: "$r26"},
79 {.Aliases: {"s4", "$s4", "r27"}, .Register: "$r27"},
80 {.Aliases: {"s5", "$s5", "r28"}, .Register: "$r28"},
81 {.Aliases: {"s6", "$s6", "r29"}, .Register: "$r29"},
82 {.Aliases: {"s7", "$s7", "r30"}, .Register: "$r30"},
83 {.Aliases: {"s8", "$s8", "r31"}, .Register: "$r31"},
84 {.Aliases: {"fa0", "$fa0", "f0"}, .Register: "$f0"},
85 {.Aliases: {"fa1", "$fa1", "f1"}, .Register: "$f1"},
86 {.Aliases: {"fa2", "$fa2", "f2"}, .Register: "$f2"},
87 {.Aliases: {"fa3", "$fa3", "f3"}, .Register: "$f3"},
88 {.Aliases: {"fa4", "$fa4", "f4"}, .Register: "$f4"},
89 {.Aliases: {"fa5", "$fa5", "f5"}, .Register: "$f5"},
90 {.Aliases: {"fa6", "$fa6", "f6"}, .Register: "$f6"},
91 {.Aliases: {"fa7", "$fa7", "f7"}, .Register: "$f7"},
92 {.Aliases: {"ft0", "$ft0", "f8"}, .Register: "$f8"},
93 {.Aliases: {"ft1", "$ft1", "f9"}, .Register: "$f9"},
94 {.Aliases: {"ft2", "$ft2", "f10"}, .Register: "$f10"},
95 {.Aliases: {"ft3", "$ft3", "f11"}, .Register: "$f11"},
96 {.Aliases: {"ft4", "$ft4", "f12"}, .Register: "$f12"},
97 {.Aliases: {"ft5", "$ft5", "f13"}, .Register: "$f13"},
98 {.Aliases: {"ft6", "$ft6", "f14"}, .Register: "$f14"},
99 {.Aliases: {"ft7", "$ft7", "f15"}, .Register: "$f15"},
100 {.Aliases: {"ft8", "$ft8", "f16"}, .Register: "$f16"},
101 {.Aliases: {"ft9", "$ft9", "f17"}, .Register: "$f17"},
102 {.Aliases: {"ft10", "$ft10", "f18"}, .Register: "$f18"},
103 {.Aliases: {"ft11", "$ft11", "f19"}, .Register: "$f19"},
104 {.Aliases: {"ft12", "$ft12", "f20"}, .Register: "$f20"},
105 {.Aliases: {"ft13", "$ft13", "f21"}, .Register: "$f21"},
106 {.Aliases: {"ft14", "$ft14", "f22"}, .Register: "$f22"},
107 {.Aliases: {"ft15", "$ft15", "f23"}, .Register: "$f23"},
108 {.Aliases: {"fs0", "$fs0", "f24"}, .Register: "$f24"},
109 {.Aliases: {"fs1", "$fs1", "f25"}, .Register: "$f25"},
110 {.Aliases: {"fs2", "$fs2", "f26"}, .Register: "$f26"},
111 {.Aliases: {"fs3", "$fs3", "f27"}, .Register: "$f27"},
112 {.Aliases: {"fs4", "$fs4", "f28"}, .Register: "$f28"},
113 {.Aliases: {"fs5", "$fs5", "f29"}, .Register: "$f29"},
114 {.Aliases: {"fs6", "$fs6", "f30"}, .Register: "$f30"},
115 {.Aliases: {"fs7", "$fs7", "f31"}, .Register: "$f31"},
116 {.Aliases: {"fcc0"}, .Register: "$fcc0"},
117 {.Aliases: {"fcc1"}, .Register: "$fcc1"},
118 {.Aliases: {"fcc2"}, .Register: "$fcc2"},
119 {.Aliases: {"fcc3"}, .Register: "$fcc3"},
120 {.Aliases: {"fcc4"}, .Register: "$fcc4"},
121 {.Aliases: {"fcc5"}, .Register: "$fcc5"},
122 {.Aliases: {"fcc6"}, .Register: "$fcc6"},
123 {.Aliases: {"fcc7"}, .Register: "$fcc7"},
124 };
125 return llvm::ArrayRef(GCCRegAliases);
126}
127
128bool LoongArchTargetInfo::validateAsmConstraint(
129 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
130 // See the GCC definitions here:
131 // https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html
132 // Note that the 'm' constraint is handled in TargetInfo.
133 switch (*Name) {
134 default:
135 return false;
136 case 'f':
137 // A floating-point register (if available).
138 Info.setAllowsRegister();
139 return true;
140 case 'k':
141 // A memory operand whose address is formed by a base register and
142 // (optionally scaled) index register.
143 Info.setAllowsMemory();
144 return true;
145 case 'l':
146 // A signed 16-bit constant.
147 Info.setRequiresImmediate(Min: -32768, Max: 32767);
148 return true;
149 case 'q':
150 // A general-purpose register except for $r0 and $r1 (for the csrxchg
151 // instruction)
152 Info.setAllowsRegister();
153 return true;
154 case 'I':
155 // A signed 12-bit constant (for arithmetic instructions).
156 Info.setRequiresImmediate(Min: -2048, Max: 2047);
157 return true;
158 case 'J':
159 // Integer zero.
160 Info.setRequiresImmediate(0);
161 return true;
162 case 'K':
163 // An unsigned 12-bit constant (for logic instructions).
164 Info.setRequiresImmediate(Min: 0, Max: 4095);
165 return true;
166 case 'Z':
167 // ZB: An address that is held in a general-purpose register. The offset is
168 // zero.
169 // ZC: A memory operand whose address is formed by a base register
170 // and offset that is suitable for use in instructions with the same
171 // addressing mode as ll.w and sc.w.
172 if (Name[1] == 'C' || Name[1] == 'B') {
173 Info.setAllowsMemory();
174 ++Name; // Skip over 'Z'.
175 return true;
176 }
177 return false;
178 }
179}
180
181std::string
182LoongArchTargetInfo::convertConstraint(const char *&Constraint) const {
183 std::string R;
184 switch (*Constraint) {
185 case 'Z':
186 // "ZC"/"ZB" are two-character constraints; add "^" hint for later
187 // parsing.
188 R = "^" + std::string(Constraint, 2);
189 ++Constraint;
190 break;
191 default:
192 R = TargetInfo::convertConstraint(Constraint);
193 break;
194 }
195 return R;
196}
197
198void LoongArchTargetInfo::getTargetDefines(const LangOptions &Opts,
199 MacroBuilder &Builder) const {
200 Builder.defineMacro(Name: "__loongarch__");
201 unsigned GRLen = getRegisterWidth();
202 Builder.defineMacro(Name: "__loongarch_grlen", Value: Twine(GRLen));
203 if (GRLen == 64)
204 Builder.defineMacro(Name: "__loongarch64");
205
206 if (HasFeatureD)
207 Builder.defineMacro(Name: "__loongarch_frlen", Value: "64");
208 else if (HasFeatureF)
209 Builder.defineMacro(Name: "__loongarch_frlen", Value: "32");
210 else
211 Builder.defineMacro(Name: "__loongarch_frlen", Value: "0");
212
213 // Define __loongarch_arch.
214 StringRef ArchName = getCPU();
215 if (ArchName == "loongarch64") {
216 if (HasFeatureLSX) {
217 // TODO: As more features of the V1.1 ISA are supported, a unified "v1.1"
218 // arch feature set will be used to include all sub-features belonging to
219 // the V1.1 ISA version.
220 if (HasFeatureFrecipe && HasFeatureLAM_BH && HasFeatureLAMCAS &&
221 HasFeatureLD_SEQ_SA && HasFeatureDiv32 && HasFeatureSCQ)
222 Builder.defineMacro(Name: "__loongarch_arch",
223 Value: Twine('"') + "la64v1.1" + Twine('"'));
224 else
225 Builder.defineMacro(Name: "__loongarch_arch",
226 Value: Twine('"') + "la64v1.0" + Twine('"'));
227 } else {
228 Builder.defineMacro(Name: "__loongarch_arch",
229 Value: Twine('"') + ArchName + Twine('"'));
230 }
231 } else if (ArchName == "loongarch32") {
232 if (HasFeature32S)
233 Builder.defineMacro(Name: "__loongarch_arch",
234 Value: Twine('"') + "la32v1.0" + Twine('"'));
235 else
236 Builder.defineMacro(Name: "__loongarch_arch",
237 Value: Twine('"') + "la32rv1.0" + Twine('"'));
238 } else {
239 Builder.defineMacro(Name: "__loongarch_arch", Value: Twine('"') + ArchName + Twine('"'));
240 }
241
242 // Define __loongarch_tune.
243 StringRef TuneCPU = getTargetOpts().TuneCPU;
244 if (TuneCPU.empty())
245 TuneCPU = ArchName;
246 Builder.defineMacro(Name: "__loongarch_tune", Value: Twine('"') + TuneCPU + Twine('"'));
247
248 if (HasFeatureLASX) {
249 Builder.defineMacro(Name: "__loongarch_simd_width", Value: "256");
250 Builder.defineMacro(Name: "__loongarch_sx", Value: Twine(1));
251 Builder.defineMacro(Name: "__loongarch_asx", Value: Twine(1));
252 Builder.defineMacro(Name: "__loongarch_asx_sx_conv", Value: Twine(1));
253 } else if (HasFeatureLSX) {
254 Builder.defineMacro(Name: "__loongarch_simd_width", Value: "128");
255 Builder.defineMacro(Name: "__loongarch_sx", Value: Twine(1));
256 }
257 if (HasFeatureFrecipe)
258 Builder.defineMacro(Name: "__loongarch_frecipe", Value: Twine(1));
259
260 if (HasFeatureLAM_BH)
261 Builder.defineMacro(Name: "__loongarch_lam_bh", Value: Twine(1));
262
263 if (HasFeatureLAMCAS)
264 Builder.defineMacro(Name: "__loongarch_lamcas", Value: Twine(1));
265
266 if (HasFeatureLD_SEQ_SA)
267 Builder.defineMacro(Name: "__loongarch_ld_seq_sa", Value: Twine(1));
268
269 if (HasFeatureDiv32)
270 Builder.defineMacro(Name: "__loongarch_div32", Value: Twine(1));
271
272 if (HasFeatureSCQ)
273 Builder.defineMacro(Name: "__loongarch_scq", Value: Twine(1));
274
275 StringRef ABI = getABI();
276 if (ABI == "lp64d" || ABI == "lp64f" || ABI == "lp64s")
277 Builder.defineMacro(Name: "__loongarch_lp64");
278 else if (ABI == "ilp32d" || ABI == "ilp32f" || ABI == "ilp32s")
279 Builder.defineMacro(Name: "__loongarch_ilp32");
280
281 if (ABI == "lp64d" || ABI == "ilp32d") {
282 Builder.defineMacro(Name: "__loongarch_hard_float");
283 Builder.defineMacro(Name: "__loongarch_double_float");
284 } else if (ABI == "lp64f" || ABI == "ilp32f") {
285 Builder.defineMacro(Name: "__loongarch_hard_float");
286 Builder.defineMacro(Name: "__loongarch_single_float");
287 } else if (ABI == "lp64s" || ABI == "ilp32s") {
288 Builder.defineMacro(Name: "__loongarch_soft_float");
289 }
290
291 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
292 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
293 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
294 if (GRLen == 64)
295 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
296}
297
298static constexpr int NumBaseBuiltins =
299 LoongArch::FirstLSXBuiltin - Builtin::FirstTSBuiltin;
300static constexpr int NumLSXBuiltins =
301 LoongArch::FirstLASXBuiltin - LoongArch::FirstLSXBuiltin;
302static constexpr int NumLASXBuiltins =
303 LoongArch::LastTSBuiltin - LoongArch::FirstLASXBuiltin;
304static constexpr int NumBuiltins =
305 LoongArch::LastTSBuiltin - Builtin::FirstTSBuiltin;
306static_assert(NumBuiltins ==
307 (NumBaseBuiltins + NumLSXBuiltins + NumLASXBuiltins));
308
309static constexpr llvm::StringTable BuiltinBaseStrings =
310 CLANG_BUILTIN_STR_TABLE_START
311#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
312#include "clang/Basic/BuiltinsLoongArchBase.def"
313#undef TARGET_BUILTIN
314 ;
315
316static constexpr auto BuiltinBaseInfos = Builtin::MakeInfos<NumBaseBuiltins>(Infos: {
317#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
318#include "clang/Basic/BuiltinsLoongArchBase.def"
319#undef TARGET_BUILTIN
320});
321
322static constexpr llvm::StringTable BuiltinLSXStrings =
323 CLANG_BUILTIN_STR_TABLE_START
324#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
325#include "clang/Basic/BuiltinsLoongArchLSX.def"
326#undef TARGET_BUILTIN
327 ;
328
329static constexpr auto BuiltinLSXInfos = Builtin::MakeInfos<NumLSXBuiltins>(Infos: {
330#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
331#include "clang/Basic/BuiltinsLoongArchLSX.def"
332#undef TARGET_BUILTIN
333});
334
335static constexpr llvm::StringTable BuiltinLASXStrings =
336 CLANG_BUILTIN_STR_TABLE_START
337#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
338#include "clang/Basic/BuiltinsLoongArchLASX.def"
339#undef TARGET_BUILTIN
340 ;
341
342static constexpr auto BuiltinLASXInfos = Builtin::MakeInfos<NumLASXBuiltins>(Infos: {
343#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
344#include "clang/Basic/BuiltinsLoongArchLASX.def"
345#undef TARGET_BUILTIN
346});
347
348bool LoongArchTargetInfo::initFeatureMap(
349 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
350 const std::vector<std::string> &FeaturesVec) const {
351 if (getTriple().getArch() == llvm::Triple::loongarch64)
352 Features["64bit"] = true;
353 if (getTriple().getArch() == llvm::Triple::loongarch32)
354 Features["32bit"] = true;
355
356 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec: FeaturesVec);
357}
358
359/// Return true if has this feature.
360bool LoongArchTargetInfo::hasFeature(StringRef Feature) const {
361 bool Is64Bit = getTriple().getArch() == llvm::Triple::loongarch64;
362 // TODO: Handle more features.
363 return llvm::StringSwitch<bool>(Feature)
364 .Case(S: "loongarch32", Value: !Is64Bit)
365 .Case(S: "loongarch64", Value: Is64Bit)
366 .Case(S: "32bit", Value: !Is64Bit)
367 .Case(S: "64bit", Value: Is64Bit)
368 .Case(S: "32s", Value: HasFeature32S)
369 .Case(S: "lsx", Value: HasFeatureLSX)
370 .Case(S: "lasx", Value: HasFeatureLASX)
371 .Default(Value: false);
372}
373
374llvm::SmallVector<Builtin::InfosShard>
375LoongArchTargetInfo::getTargetBuiltins() const {
376 return {
377 {.Strings: &BuiltinBaseStrings, .Infos: BuiltinBaseInfos},
378 {.Strings: &BuiltinLSXStrings, .Infos: BuiltinLSXInfos},
379 {.Strings: &BuiltinLASXStrings, .Infos: BuiltinLASXInfos},
380 };
381}
382
383bool LoongArchTargetInfo::handleTargetFeatures(
384 std::vector<std::string> &Features, DiagnosticsEngine &Diags) {
385 for (const auto &Feature : Features) {
386 if (Feature == "+32s") {
387 HasFeature32S = true;
388 } else if (Feature == "+d" || Feature == "+f") {
389 // "d" implies "f".
390 HasFeatureF = true;
391 if (Feature == "+d") {
392 HasFeatureD = true;
393 }
394 } else if (Feature == "+lsx")
395 HasFeatureLSX = true;
396 else if (Feature == "+lasx")
397 HasFeatureLASX = true;
398 else if (Feature == "-ual")
399 HasUnalignedAccess = false;
400 else if (Feature == "+frecipe")
401 HasFeatureFrecipe = true;
402 else if (Feature == "+lam-bh")
403 HasFeatureLAM_BH = true;
404 else if (Feature == "+lamcas")
405 HasFeatureLAMCAS = true;
406 else if (Feature == "+ld-seq-sa")
407 HasFeatureLD_SEQ_SA = true;
408 else if (Feature == "+div32")
409 HasFeatureDiv32 = true;
410 else if (Feature == "+scq")
411 HasFeatureSCQ = true;
412 }
413 return true;
414}
415
416enum class AttrFeatureKind { Arch, Tune, NoFeature, Feature };
417
418static std::pair<AttrFeatureKind, llvm::StringRef>
419getAttrFeatureTypeAndValue(llvm::StringRef AttrFeature) {
420 if (auto Split = AttrFeature.split(Separator: "="); !Split.second.empty()) {
421 if (Split.first.trim() == "arch")
422 return {AttrFeatureKind::Arch, Split.second.trim()};
423 if (Split.first.trim() == "tune")
424 return {AttrFeatureKind::Tune, Split.second.trim()};
425 }
426 if (AttrFeature.starts_with(Prefix: "no-"))
427 return {AttrFeatureKind::NoFeature, AttrFeature.drop_front(N: 3)};
428 return {AttrFeatureKind::Feature, AttrFeature};
429}
430
431ParsedTargetAttr
432LoongArchTargetInfo::parseTargetAttr(StringRef Features) const {
433 ParsedTargetAttr Ret;
434 if (Features == "default")
435 return Ret;
436 SmallVector<StringRef, 1> AttrFeatures;
437 Features.split(A&: AttrFeatures, Separator: ",");
438
439 for (auto &Feature : AttrFeatures) {
440 auto [Kind, Value] = getAttrFeatureTypeAndValue(AttrFeature: Feature.trim());
441
442 switch (Kind) {
443 case AttrFeatureKind::Arch: {
444 if (llvm::LoongArch::isValidArchName(Arch: Value) || Value == "la64v1.0" ||
445 Value == "la64v1.1" || Value == "la32v1.0" || Value == "la32rv1.0") {
446 std::vector<llvm::StringRef> ArchFeatures;
447 if (llvm::LoongArch::getArchFeatures(Arch: Value, Features&: ArchFeatures)) {
448 Ret.Features.insert(position: Ret.Features.end(), first: ArchFeatures.begin(),
449 last: ArchFeatures.end());
450 }
451
452 if (!Ret.CPU.empty())
453 Ret.Duplicate = "arch=";
454 else if (Value == "la64v1.0" || Value == "la64v1.1")
455 Ret.CPU = "loongarch64";
456 else if (Value == "la32v1.0" || Value == "la32rv1.0")
457 Ret.CPU = "loongarch32";
458 else
459 Ret.CPU = Value;
460 } else {
461 Ret.Features.push_back(x: "!arch=" + Value.str());
462 }
463 break;
464 }
465
466 case AttrFeatureKind::Tune:
467 if (!Ret.Tune.empty())
468 Ret.Duplicate = "tune=";
469 else
470 Ret.Tune = Value;
471 break;
472
473 case AttrFeatureKind::NoFeature:
474 Ret.Features.push_back(x: "-" + Value.str());
475 break;
476
477 case AttrFeatureKind::Feature:
478 Ret.Features.push_back(x: "+" + Value.str());
479 if (Value == "lasx")
480 Ret.Features.push_back(x: "+lsx");
481 break;
482 }
483 }
484 return Ret;
485}
486
487bool LoongArchTargetInfo::isValidCPUName(StringRef Name) const {
488 return llvm::LoongArch::isValidCPUName(TuneCPU: Name);
489}
490
491void LoongArchTargetInfo::fillValidCPUList(
492 SmallVectorImpl<StringRef> &Values) const {
493 llvm::LoongArch::fillValidCPUList(Values);
494}
495
496bool LoongArchTargetInfo::isValidFeatureName(StringRef Name) const {
497 return llvm::LoongArch::isValidFeatureName(Feature: Name);
498}
499