1//===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares Mips TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
15
16#include "OSTargets.h"
17#include "clang/Basic/TargetInfo.h"
18#include "clang/Basic/TargetOptions.h"
19#include "llvm/Support/Compiler.h"
20#include "llvm/TargetParser/Triple.h"
21
22namespace clang {
23namespace targets {
24
25class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
26 std::string CPU;
27 bool IsMips16;
28 bool IsMicromips;
29 bool IsNan2008;
30 bool IsAbs2008;
31 bool IsSingleFloat;
32 bool IsNoABICalls;
33 bool CanUseBSDABICalls;
34 enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
35 enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
36 bool HasMSA;
37 bool DisableMadd4;
38 bool UseIndirectJumpHazard;
39 bool NoOddSpreg;
40
41protected:
42 enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
43 std::string ABI;
44
45public:
46 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
47 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
48 IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
49 IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
50 DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
51 UseIndirectJumpHazard(false), FPMode(FPXX) {
52 TheCXXABI.set(TargetCXXABI::GenericMIPS);
53
54 if (Triple.isMIPS32())
55 setABI("o32");
56 else if (Triple.isABIN32())
57 setABI("n32");
58 else
59 setABI("n64");
60
61 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
62
63 CanUseBSDABICalls = Triple.isOSFreeBSD() ||
64 Triple.isOSOpenBSD();
65 }
66
67 bool isIEEE754_2008Default() const {
68 return CPU == "mips32r6" || CPU == "mips64r6" || CPU == "i6400" ||
69 CPU == "i6500";
70 }
71
72 enum FPModeEnum getDefaultFPMode() const {
73 if (CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64")
74 return FP64;
75 else if (CPU == "mips1")
76 return FP32;
77 else
78 return FPXX;
79 }
80
81 bool isNan2008() const override { return IsNan2008; }
82
83 bool processorSupportsGPR64() const;
84
85 StringRef getABI() const override { return ABI; }
86
87 bool setABI(const std::string &Name) override {
88 if (Name == "o32") {
89 setO32ABITypes();
90 ABI = Name;
91 return true;
92 }
93
94 if (Name == "n32") {
95 setN32ABITypes();
96 ABI = Name;
97 return true;
98 }
99 if (Name == "n64") {
100 setN64ABITypes();
101 ABI = Name;
102 return true;
103 }
104 return false;
105 }
106
107 void setO32ABITypes() {
108 Int64Type = SignedLongLong;
109 IntMaxType = Int64Type;
110 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
111 LongDoubleWidth = LongDoubleAlign = 64;
112 LongWidth = LongAlign = 32;
113 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
114 PointerWidth = PointerAlign = 32;
115 PtrDiffType = IntPtrType = SignedInt;
116 SizeType = UnsignedInt;
117 SuitableAlign = 64;
118 }
119
120 void setN32N64ABITypes() {
121 LongDoubleWidth = LongDoubleAlign = 128;
122 LongDoubleFormat = &llvm::APFloat::IEEEquad();
123 if (getTriple().isOSFreeBSD()) {
124 LongDoubleWidth = LongDoubleAlign = 64;
125 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
126 }
127 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
128 SuitableAlign = 128;
129 }
130
131 void setN64ABITypes() {
132 setN32N64ABITypes();
133 if (getTriple().isOSOpenBSD()) {
134 Int64Type = SignedLongLong;
135 } else {
136 Int64Type = SignedLong;
137 }
138 IntMaxType = Int64Type;
139 LongWidth = LongAlign = 64;
140 PointerWidth = PointerAlign = 64;
141 PtrDiffType = IntPtrType = SignedLong;
142 SizeType = UnsignedLong;
143 }
144
145 void setN32ABITypes() {
146 setN32N64ABITypes();
147 Int64Type = SignedLongLong;
148 IntMaxType = Int64Type;
149 LongWidth = LongAlign = 32;
150 PointerWidth = PointerAlign = 32;
151 PtrDiffType = IntPtrType = SignedInt;
152 SizeType = UnsignedInt;
153 }
154
155 bool isValidCPUName(StringRef Name) const override;
156 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
157
158 bool setCPU(const std::string &Name) override {
159 CPU = Name;
160 return isValidCPUName(Name);
161 }
162
163 const std::string &getCPU() const { return CPU; }
164 bool
165 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
166 StringRef CPU,
167 const std::vector<std::string> &FeaturesVec) const override {
168 if (CPU.empty())
169 CPU = getCPU();
170 if (CPU == "octeon")
171 Features["mips64r2"] = Features["cnmips"] = true;
172 else if (CPU == "octeon+")
173 Features["mips64r2"] = Features["cnmips"] = Features["cnmipsp"] = true;
174 else
175 Features[CPU] = true;
176 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec: FeaturesVec);
177 }
178
179 unsigned getISARev() const;
180
181 void getTargetDefines(const LangOptions &Opts,
182 MacroBuilder &Builder) const override;
183
184 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
185
186 bool hasFeature(StringRef Feature) const override;
187
188 BuiltinVaListKind getBuiltinVaListKind() const override {
189 return TargetInfo::VoidPtrBuiltinVaList;
190 }
191
192 ArrayRef<const char *> getGCCRegNames() const override {
193 static const char *const GCCRegNames[] = {
194 // CPU register names
195 // Must match second column of GCCRegAliases
196 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
197 "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20",
198 "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30",
199 "$31",
200 // Floating point register names
201 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
202 "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
203 "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
204 "$f28", "$f29", "$f30", "$f31",
205 // Hi/lo and condition register names
206 "hi", "lo", "", "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5",
207 "$fcc6", "$fcc7", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi",
208 "$ac3lo",
209 // MSA register names
210 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9",
211 "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", "$w16", "$w17", "$w18",
212 "$w19", "$w20", "$w21", "$w22", "$w23", "$w24", "$w25", "$w26", "$w27",
213 "$w28", "$w29", "$w30", "$w31",
214 // MSA control register names
215 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
216 "$msarequest", "$msamap", "$msaunmap"
217 };
218 return llvm::ArrayRef(GCCRegNames);
219 }
220
221 bool validateAsmConstraint(const char *&Name,
222 TargetInfo::ConstraintInfo &Info) const override {
223 switch (*Name) {
224 default:
225 return false;
226 case 'r': // CPU registers.
227 case 'd': // Equivalent to "r" unless generating MIPS16 code.
228 case 'y': // Equivalent to "r", backward compatibility only.
229 case 'c': // $25 for indirect jumps
230 case 'l': // lo register
231 case 'x': // hilo register pair
232 Info.setAllowsRegister();
233 return true;
234 case 'f': // floating-point registers.
235 Info.setAllowsRegister();
236 return FloatABI != SoftFloat;
237 case 'I': // Signed 16-bit constant
238 case 'J': // Integer 0
239 case 'K': // Unsigned 16-bit constant
240 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
241 case 'M': // Constants not loadable via lui, addiu, or ori
242 case 'N': // Constant -1 to -65535
243 case 'O': // A signed 15-bit constant
244 case 'P': // A constant between 1 go 65535
245 return true;
246 case 'R': // An address that can be used in a non-macro load or store
247 Info.setAllowsMemory();
248 return true;
249 case 'Z':
250 if (Name[1] == 'C') { // An address usable by ll, and sc.
251 Info.setAllowsMemory();
252 Name++; // Skip over 'Z'.
253 return true;
254 }
255 return false;
256 }
257 }
258
259 std::string convertConstraint(const char *&Constraint) const override {
260 std::string R;
261 switch (*Constraint) {
262 case 'Z': // Two-character constraint; add "^" hint for later parsing.
263 if (Constraint[1] == 'C') {
264 R = std::string("^") + std::string(Constraint, 2);
265 Constraint++;
266 return R;
267 }
268 break;
269 }
270 return TargetInfo::convertConstraint(Constraint);
271 }
272
273 std::string_view getClobbers() const override {
274 // In GCC, $1 is not widely used in generated code (it's used only in a few
275 // specific situations), so there is no real need for users to add it to
276 // the clobbers list if they want to use it in their inline assembly code.
277 //
278 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
279 // code generation, so using it in inline assembly without adding it to the
280 // clobbers list can cause conflicts between the inline assembly code and
281 // the surrounding generated code.
282 //
283 // Another problem is that LLVM is allowed to choose $1 for inline assembly
284 // operands, which will conflict with the ".set at" assembler option (which
285 // we use only for inline assembly, in order to maintain compatibility with
286 // GCC) and will also conflict with the user's usage of $1.
287 //
288 // The easiest way to avoid these conflicts and keep $1 as an allocatable
289 // register for generated code is to automatically clobber $1 for all inline
290 // assembly code.
291 //
292 // FIXME: We should automatically clobber $1 only for inline assembly code
293 // which actually uses it. This would allow LLVM to use $1 for inline
294 // assembly operands if the user's assembly code doesn't use it.
295 return "~{$1}";
296 }
297
298 bool handleTargetFeatures(std::vector<std::string> &Features,
299 DiagnosticsEngine &Diags) override {
300 IsMips16 = false;
301 IsMicromips = false;
302 IsNan2008 = isIEEE754_2008Default();
303 IsAbs2008 = isIEEE754_2008Default();
304 IsSingleFloat = false;
305 FloatABI = HardFloat;
306 DspRev = NoDSP;
307 NoOddSpreg = false;
308 FPMode = getDefaultFPMode();
309 bool OddSpregGiven = false;
310 bool StrictAlign = false;
311 bool FpGiven = false;
312
313 for (const auto &Feature : Features) {
314 if (Feature == "+single-float")
315 IsSingleFloat = true;
316 else if (Feature == "+soft-float")
317 FloatABI = SoftFloat;
318 else if (Feature == "+mips16")
319 IsMips16 = true;
320 else if (Feature == "+micromips")
321 IsMicromips = true;
322 else if (Feature == "+mips32r6" || Feature == "+mips64r6")
323 HasUnalignedAccess = true;
324 // We cannot be sure that the order of strict-align vs mips32r6.
325 // Thus we need an extra variable here.
326 else if (Feature == "+strict-align")
327 StrictAlign = true;
328 else if (Feature == "+dsp")
329 DspRev = std::max(a: DspRev, b: DSP1);
330 else if (Feature == "+dspr2")
331 DspRev = std::max(a: DspRev, b: DSP2);
332 else if (Feature == "+msa")
333 HasMSA = true;
334 else if (Feature == "+nomadd4")
335 DisableMadd4 = true;
336 else if (Feature == "+fp64") {
337 FPMode = FP64;
338 FpGiven = true;
339 } else if (Feature == "-fp64") {
340 FPMode = FP32;
341 FpGiven = true;
342 } else if (Feature == "+fpxx") {
343 FPMode = FPXX;
344 FpGiven = true;
345 } else if (Feature == "+nan2008")
346 IsNan2008 = true;
347 else if (Feature == "-nan2008")
348 IsNan2008 = false;
349 else if (Feature == "+abs2008")
350 IsAbs2008 = true;
351 else if (Feature == "-abs2008")
352 IsAbs2008 = false;
353 else if (Feature == "+noabicalls")
354 IsNoABICalls = true;
355 else if (Feature == "+use-indirect-jump-hazard")
356 UseIndirectJumpHazard = true;
357 else if (Feature == "+nooddspreg") {
358 NoOddSpreg = true;
359 OddSpregGiven = false;
360 } else if (Feature == "-nooddspreg") {
361 NoOddSpreg = false;
362 OddSpregGiven = true;
363 }
364 }
365
366 if (FPMode == FPXX && !OddSpregGiven)
367 NoOddSpreg = true;
368
369 if (StrictAlign)
370 HasUnalignedAccess = false;
371
372 if (HasMSA && !FpGiven) {
373 FPMode = FP64;
374 Features.push_back(x: "+fp64");
375 }
376
377 resetDataLayout();
378
379 return true;
380 }
381
382 int getEHDataRegisterNumber(unsigned RegNo) const override {
383 if (RegNo == 0)
384 return 4;
385 if (RegNo == 1)
386 return 5;
387 return -1;
388 }
389
390 bool isCLZForZeroUndef() const override { return false; }
391
392 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
393 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
394 {.Aliases: {"at"}, .Register: "$1"}, {.Aliases: {"v0"}, .Register: "$2"}, {.Aliases: {"v1"}, .Register: "$3"},
395 {.Aliases: {"a0"}, .Register: "$4"}, {.Aliases: {"a1"}, .Register: "$5"}, {.Aliases: {"a2"}, .Register: "$6"},
396 {.Aliases: {"a3"}, .Register: "$7"}, {.Aliases: {"t0"}, .Register: "$8"}, {.Aliases: {"t1"}, .Register: "$9"},
397 {.Aliases: {"t2"}, .Register: "$10"}, {.Aliases: {"t3"}, .Register: "$11"}, {.Aliases: {"t4"}, .Register: "$12"},
398 {.Aliases: {"t5"}, .Register: "$13"}, {.Aliases: {"t6"}, .Register: "$14"}, {.Aliases: {"t7"}, .Register: "$15"},
399 {.Aliases: {"s0"}, .Register: "$16"}, {.Aliases: {"s1"}, .Register: "$17"}, {.Aliases: {"s2"}, .Register: "$18"},
400 {.Aliases: {"s3"}, .Register: "$19"}, {.Aliases: {"s4"}, .Register: "$20"}, {.Aliases: {"s5"}, .Register: "$21"},
401 {.Aliases: {"s6"}, .Register: "$22"}, {.Aliases: {"s7"}, .Register: "$23"}, {.Aliases: {"t8"}, .Register: "$24"},
402 {.Aliases: {"t9"}, .Register: "$25"}, {.Aliases: {"k0"}, .Register: "$26"}, {.Aliases: {"k1"}, .Register: "$27"},
403 {.Aliases: {"gp"}, .Register: "$28"}, {.Aliases: {"sp", "$sp"}, .Register: "$29"}, {.Aliases: {"fp", "$fp"}, .Register: "$30"},
404 {.Aliases: {"ra"}, .Register: "$31"}
405 };
406 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
407 {.Aliases: {"at"}, .Register: "$1"}, {.Aliases: {"v0"}, .Register: "$2"}, {.Aliases: {"v1"}, .Register: "$3"},
408 {.Aliases: {"a0"}, .Register: "$4"}, {.Aliases: {"a1"}, .Register: "$5"}, {.Aliases: {"a2"}, .Register: "$6"},
409 {.Aliases: {"a3"}, .Register: "$7"}, {.Aliases: {"a4"}, .Register: "$8"}, {.Aliases: {"a5"}, .Register: "$9"},
410 {.Aliases: {"a6"}, .Register: "$10"}, {.Aliases: {"a7"}, .Register: "$11"}, {.Aliases: {"t0"}, .Register: "$12"},
411 {.Aliases: {"t1"}, .Register: "$13"}, {.Aliases: {"t2"}, .Register: "$14"}, {.Aliases: {"t3"}, .Register: "$15"},
412 {.Aliases: {"s0"}, .Register: "$16"}, {.Aliases: {"s1"}, .Register: "$17"}, {.Aliases: {"s2"}, .Register: "$18"},
413 {.Aliases: {"s3"}, .Register: "$19"}, {.Aliases: {"s4"}, .Register: "$20"}, {.Aliases: {"s5"}, .Register: "$21"},
414 {.Aliases: {"s6"}, .Register: "$22"}, {.Aliases: {"s7"}, .Register: "$23"}, {.Aliases: {"t8"}, .Register: "$24"},
415 {.Aliases: {"t9"}, .Register: "$25"}, {.Aliases: {"k0"}, .Register: "$26"}, {.Aliases: {"k1"}, .Register: "$27"},
416 {.Aliases: {"gp"}, .Register: "$28"}, {.Aliases: {"sp", "$sp"}, .Register: "$29"}, {.Aliases: {"fp", "$fp"}, .Register: "$30"},
417 {.Aliases: {"ra"}, .Register: "$31"}
418 };
419 if (ABI == "o32")
420 return llvm::ArrayRef(O32RegAliases);
421 return llvm::ArrayRef(NewABIRegAliases);
422 }
423
424 bool hasInt128Type() const override {
425 return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
426 }
427
428 unsigned getUnwindWordWidth() const override;
429
430 bool validateTarget(DiagnosticsEngine &Diags) const override;
431 bool hasBitIntType() const override { return true; }
432
433 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
434 return std::make_pair(x: 32, y: 32);
435 }
436};
437
438class LLVM_LIBRARY_VISIBILITY WindowsMipsTargetInfo
439 : public WindowsTargetInfo<MipsTargetInfo> {
440 const llvm::Triple Triple;
441
442public:
443 WindowsMipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
444
445 void getVisualStudioDefines(const LangOptions &Opts,
446 MacroBuilder &Builder) const;
447
448 BuiltinVaListKind getBuiltinVaListKind() const override;
449
450 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
451};
452
453// Windows MIPS, MS (C++) ABI
454class LLVM_LIBRARY_VISIBILITY MicrosoftMipsTargetInfo
455 : public WindowsMipsTargetInfo {
456public:
457 MicrosoftMipsTargetInfo(const llvm::Triple &Triple,
458 const TargetOptions &Opts);
459
460 void getTargetDefines(const LangOptions &Opts,
461 MacroBuilder &Builder) const override;
462};
463
464// MIPS MinGW target
465class LLVM_LIBRARY_VISIBILITY MinGWMipsTargetInfo
466 : public WindowsMipsTargetInfo {
467public:
468 MinGWMipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
469
470 void getTargetDefines(const LangOptions &Opts,
471 MacroBuilder &Builder) const override;
472};
473} // namespace targets
474} // namespace clang
475
476#endif // LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
477