1//===--- NVPTX.h - Declare NVPTX target feature support ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares NVPTX TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_NVPTX_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_NVPTX_H
15
16#include "clang/Basic/Cuda.h"
17#include "clang/Basic/TargetInfo.h"
18#include "clang/Basic/TargetOptions.h"
19#include "llvm/Support/Compiler.h"
20#include "llvm/Support/NVPTXAddrSpace.h"
21#include "llvm/TargetParser/Triple.h"
22#include <optional>
23
24namespace clang {
25namespace targets {
26
27static constexpr LangASMap NVPTXAddrSpaceMap = {
28 {LangAS::opencl_global, 1},
29 {LangAS::opencl_local, 3},
30 {LangAS::opencl_constant, 4},
31 // FIXME: generic has to be added to the target
32 {LangAS::opencl_generic, 0},
33 {LangAS::opencl_global_device, 1},
34 {LangAS::opencl_global_host, 1},
35 {LangAS::cuda_device, 1},
36 {LangAS::cuda_constant, 4},
37 {LangAS::cuda_shared, 3},
38 {LangAS::sycl_global, 1},
39 {LangAS::sycl_global_device, 1},
40 {LangAS::sycl_global_host, 1},
41 {LangAS::sycl_local, 3},
42};
43
44/// The DWARF address class. Taken from
45/// https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf
46static const int NVPTXDWARFAddrSpaceMap[] = {
47 -1, // Default, opencl_private or opencl_generic - not defined
48 5, // opencl_global
49 -1,
50 8, // opencl_local or cuda_shared
51 4, // opencl_constant or cuda_constant
52};
53
54class LLVM_LIBRARY_VISIBILITY NVPTXTargetInfo : public TargetInfo {
55 static const char *const GCCRegNames[];
56 OffloadArch GPU;
57 uint32_t PTXVersion;
58 std::unique_ptr<TargetInfo> HostTarget;
59
60public:
61 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
62 unsigned TargetPointerWidth);
63
64 void getTargetDefines(const LangOptions &Opts,
65 MacroBuilder &Builder) const override;
66
67 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
68
69 bool isCLZForZeroUndef() const override { return false; }
70
71 bool
72 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
73 StringRef CPU,
74 const std::vector<std::string> &FeaturesVec) const override {
75 if (GPU != OffloadArch::Unused)
76 Features[OffloadArchToString(A: GPU)] = true;
77 // Only add PTX feature if explicitly requested. Otherwise, let the backend
78 // use the minimum required PTX version for the target SM.
79 if (PTXVersion != 0)
80 Features["ptx" + std::to_string(val: PTXVersion)] = true;
81 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec: FeaturesVec);
82 }
83
84 bool hasFeature(StringRef Feature) const override;
85
86 virtual bool isAddressSpaceSupersetOf(LangAS A, LangAS B) const override {
87 // The generic address space AS(0) is a superset of all the other address
88 // spaces used by the backend target.
89 return A == B ||
90 ((A == LangAS::Default ||
91 (isTargetAddressSpace(AS: A) &&
92 toTargetAddressSpace(AS: A) ==
93 llvm::NVPTXAS::ADDRESS_SPACE_GENERIC)) &&
94 isTargetAddressSpace(AS: B) &&
95 toTargetAddressSpace(AS: B) >= llvm::NVPTXAS::ADDRESS_SPACE_GENERIC &&
96 toTargetAddressSpace(AS: B) <= llvm::NVPTXAS::ADDRESS_SPACE_LOCAL &&
97 toTargetAddressSpace(AS: B) != 2);
98 }
99
100 ArrayRef<const char *> getGCCRegNames() const override;
101
102 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
103 // No aliases.
104 return {};
105 }
106
107 bool validateAsmConstraint(const char *&Name,
108 TargetInfo::ConstraintInfo &Info) const override {
109 switch (*Name) {
110 default:
111 return false;
112 case 'c':
113 case 'h':
114 case 'r':
115 case 'l':
116 case 'f':
117 case 'd':
118 case 'q':
119 Info.setAllowsRegister();
120 return true;
121 }
122 }
123
124 std::string_view getClobbers() const override {
125 // FIXME: Is this really right?
126 return "";
127 }
128
129 BuiltinVaListKind getBuiltinVaListKind() const override {
130 return TargetInfo::CharPtrBuiltinVaList;
131 }
132
133 bool isValidCPUName(StringRef Name) const override {
134 return StringToOffloadArch(S: Name) != OffloadArch::Unknown;
135 }
136
137 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override {
138 for (int i = static_cast<int>(OffloadArch::SM_20);
139 i < static_cast<int>(OffloadArch::Generic); ++i)
140 Values.emplace_back(Args: OffloadArchToString(A: static_cast<OffloadArch>(i)));
141 }
142
143 bool setCPU(StringRef Name) override {
144 GPU = StringToOffloadArch(S: Name);
145 return GPU != OffloadArch::Unknown;
146 }
147
148 void setSupportedOpenCLOpts() override {
149 auto &Opts = getSupportedOpenCLOpts();
150 Opts["cl_clang_storage_class_specifiers"] = true;
151 Opts["__cl_clang_function_pointers"] = true;
152 Opts["__cl_clang_variadic_functions"] = true;
153 Opts["__cl_clang_function_scope_local_variables"] = true;
154 Opts["__cl_clang_non_portable_kernel_param_types"] = true;
155 Opts["__cl_clang_bitfields"] = true;
156
157 Opts["cl_khr_fp64"] = true;
158 Opts["__opencl_c_fp64"] = true;
159 Opts["cl_khr_byte_addressable_store"] = true;
160 Opts["cl_khr_global_int32_base_atomics"] = true;
161 Opts["cl_khr_global_int32_extended_atomics"] = true;
162 Opts["cl_khr_local_int32_base_atomics"] = true;
163 Opts["cl_khr_local_int32_extended_atomics"] = true;
164
165 Opts["__opencl_c_images"] = true;
166 Opts["__opencl_c_3d_image_writes"] = true;
167 Opts["cl_khr_3d_image_writes"] = true;
168
169 Opts["__opencl_c_generic_address_space"] = true;
170 }
171
172 const llvm::omp::GV &getGridValue() const override {
173 return llvm::omp::NVPTXGridValues;
174 }
175
176 /// \returns If a target requires an address within a target specific address
177 /// space \p AddressSpace to be converted in order to be used, then return the
178 /// corresponding target specific DWARF address space.
179 ///
180 /// \returns Otherwise return std::nullopt and no conversion will be emitted
181 /// in the DWARF.
182 std::optional<unsigned>
183 getDWARFAddressSpace(unsigned AddressSpace) const override {
184 if (AddressSpace >= std::size(NVPTXDWARFAddrSpaceMap) ||
185 NVPTXDWARFAddrSpaceMap[AddressSpace] < 0)
186 return std::nullopt;
187 return NVPTXDWARFAddrSpaceMap[AddressSpace];
188 }
189
190 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
191 // CUDA compilations support all of the host's calling conventions.
192 //
193 // TODO: We should warn if you apply a non-default CC to anything other than
194 // a host function.
195 if (HostTarget)
196 return HostTarget->checkCallingConvention(CC);
197 return CC == CC_DeviceKernel ? CCCR_OK : CCCR_Warning;
198 }
199
200 bool hasBitIntType() const override { return true; }
201 bool hasBFloat16Type() const override { return true; }
202
203 OffloadArch getGPU() const { return GPU; }
204};
205} // namespace targets
206} // namespace clang
207#endif // LLVM_CLANG_LIB_BASIC_TARGETS_NVPTX_H
208