1//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares PPC TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16#include "OSTargets.h"
17#include "clang/Basic/TargetInfo.h"
18#include "clang/Basic/TargetOptions.h"
19#include "llvm/ADT/StringSwitch.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/TargetParser/Triple.h"
22
23namespace clang {
24namespace targets {
25
26// PPC abstract base class
27class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29 /// Flags for architecture specific defines.
30 typedef enum {
31 ArchDefineNone = 0,
32 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33 ArchDefinePpcgr = 1 << 1,
34 ArchDefinePpcsq = 1 << 2,
35 ArchDefine440 = 1 << 3,
36 ArchDefine603 = 1 << 4,
37 ArchDefine604 = 1 << 5,
38 ArchDefinePwr4 = 1 << 6,
39 ArchDefinePwr5 = 1 << 7,
40 ArchDefinePwr5x = 1 << 8,
41 ArchDefinePwr6 = 1 << 9,
42 ArchDefinePwr6x = 1 << 10,
43 ArchDefinePwr7 = 1 << 11,
44 ArchDefinePwr8 = 1 << 12,
45 ArchDefinePwr9 = 1 << 13,
46 ArchDefinePwr10 = 1 << 14,
47 ArchDefinePwr11 = 1 << 15,
48 ArchDefineFuture = 1 << 16,
49 ArchDefineA2 = 1 << 17,
50 ArchDefineE500 = 1 << 18
51 } ArchDefineTypes;
52
53 ArchDefineTypes ArchDefs = ArchDefineNone;
54 static const char *const GCCRegNames[];
55 static const TargetInfo::GCCRegAlias GCCRegAliases[];
56 std::string CPU;
57 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
58
59 // Target cpu features.
60 bool HasAltivec = false;
61 bool HasMMA = false;
62 bool HasROPProtect = false;
63 bool HasVSX = false;
64 bool HasP8Vector = false;
65 bool HasP8Crypto = false;
66 bool HasHTM = false;
67 bool HasP9Vector = false;
68 bool HasSPE = false;
69 bool HasFrsqrte = false;
70 bool HasFrsqrtes = false;
71 bool HasP10Vector = false;
72 bool HasPCRelativeMemops = false;
73 bool HasQuadwordAtomics = false;
74 bool UseLongCalls = false;
75
76protected:
77 std::string ABI;
78
79public:
80 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
81 : TargetInfo(Triple) {
82 SuitableAlign = 128;
83 LongDoubleWidth = LongDoubleAlign = 128;
84 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
85 HasStrictFP = true;
86 HasIbm128 = true;
87 HasUnalignedAccess = true;
88 }
89
90 // Set the language option for altivec based on our value.
91 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts,
92 const TargetInfo *Aux) override;
93
94 // Note: GCC recognizes the following additional cpus:
95 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
96 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
97 bool isValidCPUName(StringRef Name) const override;
98 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
99
100 bool setCPU(const std::string &Name) override {
101 bool CPUKnown = isValidCPUName(Name);
102 if (CPUKnown) {
103 CPU = Name;
104
105 // CPU identification.
106 ArchDefs =
107 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
108 .Case(S: "440", Value: ArchDefineName)
109 .Case(S: "450", Value: ArchDefineName | ArchDefine440)
110 .Case(S: "601", Value: ArchDefineName)
111 .Case(S: "602", Value: ArchDefineName | ArchDefinePpcgr)
112 .Case(S: "603", Value: ArchDefineName | ArchDefinePpcgr)
113 .Case(S: "603e", Value: ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
114 .Case(S: "603ev", Value: ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
115 .Case(S: "604", Value: ArchDefineName | ArchDefinePpcgr)
116 .Case(S: "604e", Value: ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
117 .Case(S: "620", Value: ArchDefineName | ArchDefinePpcgr)
118 .Case(S: "630", Value: ArchDefineName | ArchDefinePpcgr)
119 .Case(S: "7400", Value: ArchDefineName | ArchDefinePpcgr)
120 .Case(S: "7450", Value: ArchDefineName | ArchDefinePpcgr)
121 .Case(S: "750", Value: ArchDefineName | ArchDefinePpcgr)
122 .Case(S: "970", Value: ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
123 ArchDefinePpcsq)
124 .Case(S: "a2", Value: ArchDefineA2)
125 .Cases(CaseStrings: {"power3", "pwr3"}, Value: ArchDefinePpcgr)
126 .Cases(CaseStrings: {"power4", "pwr4"},
127 Value: ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
128 .Cases(CaseStrings: {"power5", "pwr5"}, Value: ArchDefinePwr5 | ArchDefinePwr4 |
129 ArchDefinePpcgr | ArchDefinePpcsq)
130 .Cases(CaseStrings: {"power5x", "pwr5x"},
131 Value: ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
132 ArchDefinePpcgr | ArchDefinePpcsq)
133 .Cases(CaseStrings: {"power6", "pwr6"}, Value: ArchDefinePwr6 | ArchDefinePwr5x |
134 ArchDefinePwr5 | ArchDefinePwr4 |
135 ArchDefinePpcgr | ArchDefinePpcsq)
136 .Cases(CaseStrings: {"power6x", "pwr6x"},
137 Value: ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
138 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
139 ArchDefinePpcsq)
140 .Cases(CaseStrings: {"power7", "pwr7"}, Value: ArchDefinePwr7 | ArchDefinePwr6 |
141 ArchDefinePwr5x | ArchDefinePwr5 |
142 ArchDefinePwr4 | ArchDefinePpcgr |
143 ArchDefinePpcsq)
144 // powerpc64le automatically defaults to at least power8.
145 .Cases(CaseStrings: {"power8", "pwr8", "ppc64le"},
146 Value: ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
147 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
148 ArchDefinePpcgr | ArchDefinePpcsq)
149 .Cases(CaseStrings: {"power9", "pwr9"},
150 Value: ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
151 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
152 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
153 .Cases(CaseStrings: {"power10", "pwr10"},
154 Value: ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
155 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
156 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
157 ArchDefinePpcsq)
158 .Cases(CaseStrings: {"power11", "pwr11"},
159 Value: ArchDefinePwr11 | ArchDefinePwr10 | ArchDefinePwr9 |
160 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
161 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
162 ArchDefinePpcgr | ArchDefinePpcsq)
163 .Case(S: "future",
164 Value: ArchDefineFuture | ArchDefinePwr11 | ArchDefinePwr10 |
165 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
166 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
167 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
168 .Cases(CaseStrings: {"8548", "e500"}, Value: ArchDefineE500)
169 .Default(Value: ArchDefineNone);
170 }
171 return CPUKnown;
172 }
173
174 StringRef getABI() const override { return ABI; }
175
176 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
177
178 bool isCLZForZeroUndef() const override { return false; }
179
180 void getTargetDefines(const LangOptions &Opts,
181 MacroBuilder &Builder) const override;
182
183 bool
184 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
185 StringRef CPU,
186 const std::vector<std::string> &FeaturesVec) const override;
187
188 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
189 void addP11SpecificFeatures(llvm::StringMap<bool> &Features) const;
190 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
191
192 bool handleTargetFeatures(std::vector<std::string> &Features,
193 DiagnosticsEngine &Diags) override;
194
195 bool hasFeature(StringRef Feature) const override;
196
197 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
198 bool Enabled) const override;
199
200 bool supportsTargetAttributeTune() const override { return true; }
201
202 ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
203
204 llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override;
205
206 ArrayRef<const char *> getGCCRegNames() const override;
207
208 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
209
210 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
211
212 bool validateAsmConstraint(const char *&Name,
213 TargetInfo::ConstraintInfo &Info) const override {
214 switch (*Name) {
215 default:
216 return false;
217 case 'O': // Zero
218 break;
219 case 'f': // Floating point register
220 // Don't use floating point registers on soft float ABI.
221 if (FloatABI == SoftFloat)
222 return false;
223 [[fallthrough]];
224 case 'b': // Base register
225 Info.setAllowsRegister();
226 break;
227 // FIXME: The following are added to allow parsing.
228 // I just took a guess at what the actions should be.
229 // Also, is more specific checking needed? I.e. specific registers?
230 case 'd': // Floating point register (containing 64-bit value)
231 case 'v': // Altivec vector register
232 // Don't use floating point and altivec vector registers
233 // on soft float ABI
234 if (FloatABI == SoftFloat)
235 return false;
236 Info.setAllowsRegister();
237 break;
238 case 'w':
239 switch (Name[1]) {
240 case 'd': // VSX vector register to hold vector double data
241 case 'f': // VSX vector register to hold vector float data
242 case 's': // VSX vector register to hold scalar double data
243 case 'w': // VSX vector register to hold scalar double data
244 case 'a': // Any VSX register
245 case 'c': // An individual CR bit
246 case 'i': // FP or VSX register to hold 64-bit integers data
247 break;
248 default:
249 return false;
250 }
251 Info.setAllowsRegister();
252 Name++; // Skip over 'w'.
253 break;
254 case 'h': // `MQ', `CTR', or `LINK' register
255 case 'q': // `MQ' register
256 case 'c': // `CTR' register
257 case 'l': // `LINK' register
258 case 'x': // `CR' register (condition register) number 0
259 case 'y': // `CR' register (condition register)
260 case 'z': // `XER[CA]' carry bit (part of the XER register)
261 Info.setAllowsRegister();
262 break;
263 case 'I': // Signed 16-bit constant
264 case 'J': // Unsigned 16-bit constant shifted left 16 bits
265 // (use `L' instead for SImode constants)
266 case 'K': // Unsigned 16-bit constant
267 case 'L': // Signed 16-bit constant shifted left 16 bits
268 case 'M': // Constant larger than 31
269 case 'N': // Exact power of 2
270 case 'P': // Constant whose negation is a signed 16-bit constant
271 case 'G': // Floating point constant that can be loaded into a
272 // register with one instruction per word
273 case 'H': // Integer/Floating point constant that can be loaded
274 // into a register using three instructions
275 break;
276 case 'm': // Memory operand. Note that on PowerPC targets, m can
277 // include addresses that update the base register. It
278 // is therefore only safe to use `m' in an asm statement
279 // if that asm statement accesses the operand exactly once.
280 // The asm statement must also use `%U<opno>' as a
281 // placeholder for the "update" flag in the corresponding
282 // load or store instruction. For example:
283 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
284 // is correct but:
285 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
286 // is not. Use es rather than m if you don't want the base
287 // register to be updated.
288 case 'e':
289 if (Name[1] != 's')
290 return false;
291 // es: A "stable" memory operand; that is, one which does not
292 // include any automodification of the base register. Unlike
293 // `m', this constraint can be used in asm statements that
294 // might access the operand several times, or that might not
295 // access it at all.
296 Info.setAllowsMemory();
297 Name++; // Skip over 'e'.
298 break;
299 case 'Q': // Memory operand that is an offset from a register (it is
300 // usually better to use `m' or `es' in asm statements)
301 Info.setAllowsRegister();
302 [[fallthrough]];
303 case 'Z': // Memory operand that is an indexed or indirect from a
304 // register (it is usually better to use `m' or `es' in
305 // asm statements)
306 Info.setAllowsMemory();
307 break;
308 case 'a': // Address operand that is an indexed or indirect from a
309 // register (`p' is preferable for asm statements)
310 // TODO: Add full support for this constraint
311 return false;
312 case 'R': // AIX TOC entry
313 case 'S': // Constant suitable as a 64-bit mask operand
314 case 'T': // Constant suitable as a 32-bit mask operand
315 case 'U': // System V Release 4 small data area reference
316 case 't': // AND masks that can be performed by two rldic{l, r}
317 // instructions
318 case 'W': // Vector constant that does not require memory
319 case 'j': // Vector constant that is all zeros.
320 break;
321 // End FIXME.
322 }
323 return true;
324 }
325
326 std::string convertConstraint(const char *&Constraint) const override {
327 std::string R;
328 switch (*Constraint) {
329 case 'e':
330 case 'w':
331 // Two-character constraint; add "^" hint for later parsing.
332 R = std::string("^") + std::string(Constraint, 2);
333 Constraint++;
334 break;
335 default:
336 return TargetInfo::convertConstraint(Constraint);
337 }
338 return R;
339 }
340
341 std::string_view getClobbers() const override { return ""; }
342 int getEHDataRegisterNumber(unsigned RegNo) const override {
343 if (RegNo == 0)
344 return 3;
345 if (RegNo == 1)
346 return 4;
347 return -1;
348 }
349
350 bool hasSjLjLowering() const override { return true; }
351
352 const char *getLongDoubleMangling() const override {
353 if (LongDoubleWidth == 64)
354 return "e";
355 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
356 ? "g"
357 : "u9__ieee128";
358 }
359 const char *getFloat128Mangling() const override { return "u9__ieee128"; }
360 const char *getIbm128Mangling() const override { return "g"; }
361
362 bool hasBitIntType() const override { return true; }
363
364 bool isSPRegName(StringRef RegName) const override {
365 return RegName == "r1" || RegName == "x1";
366 }
367
368 // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
369 // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
370 static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
371 static constexpr int MINIMUM_AIX_OS_MINOR = 2;
372 bool supportsCpuSupports() const override {
373 llvm::Triple Triple = getTriple();
374 // AIX 7.2 is the minimum requirement to support __builtin_cpu_supports().
375 return Triple.isOSGlibc() || Triple.isMusl() ||
376 (Triple.isOSAIX() &&
377 !Triple.isOSVersionLT(Major: MINIMUM_AIX_OS_MAJOR, Minor: MINIMUM_AIX_OS_MINOR));
378 }
379
380 bool supportsCpuIs() const override {
381 llvm::Triple Triple = getTriple();
382 // AIX 7.2 is the minimum requirement to support __builtin_cpu_is().
383 return Triple.isOSGlibc() || Triple.isMusl() ||
384 (Triple.isOSAIX() &&
385 !Triple.isOSVersionLT(Major: MINIMUM_AIX_OS_MAJOR, Minor: MINIMUM_AIX_OS_MINOR));
386 }
387 bool validateCpuSupports(StringRef Feature) const override;
388 bool validateCpuIs(StringRef Name) const override;
389};
390
391class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
392public:
393 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
394 : PPCTargetInfo(Triple, Opts) {
395 resetDataLayout();
396
397 switch (getTriple().getOS()) {
398 case llvm::Triple::Linux:
399 case llvm::Triple::FreeBSD:
400 case llvm::Triple::NetBSD:
401 SizeType = UnsignedInt;
402 PtrDiffType = SignedInt;
403 IntPtrType = SignedInt;
404 break;
405 case llvm::Triple::AIX:
406 SizeType = UnsignedLong;
407 PtrDiffType = SignedLong;
408 IntPtrType = SignedLong;
409 LongDoubleWidth = 64;
410 LongDoubleAlign = DoubleAlign = 32;
411 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
412 break;
413 default:
414 break;
415 }
416
417 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
418 Triple.isMusl()) {
419 LongDoubleWidth = LongDoubleAlign = 64;
420 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
421 }
422
423 // PPC32 supports atomics up to 4 bytes.
424 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
425 }
426
427 BuiltinVaListKind getBuiltinVaListKind() const override {
428 // This is the ELF definition
429 return TargetInfo::PowerABIBuiltinVaList;
430 }
431
432 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
433 return std::make_pair(x: 32, y: 32);
434 }
435};
436
437// Note: ABI differences may eventually require us to have a separate
438// TargetInfo for little endian.
439class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
440public:
441 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
442 : PPCTargetInfo(Triple, Opts) {
443 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
444 IntMaxType = SignedLong;
445 Int64Type = SignedLong;
446
447 if (Triple.isOSAIX()) {
448 // TODO: Set appropriate ABI for AIX platform.
449 LongDoubleWidth = 64;
450 LongDoubleAlign = DoubleAlign = 32;
451 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
452 } else if ((Triple.getArch() == llvm::Triple::ppc64le) ||
453 Triple.isPPC64ELFv2ABI()) {
454 ABI = "elfv2";
455 } else {
456 ABI = "elfv1";
457 }
458
459 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
460 LongDoubleWidth = LongDoubleAlign = 64;
461 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
462 }
463
464 // Newer PPC64 instruction sets support atomics up to 16 bytes.
465 MaxAtomicPromoteWidth = 128;
466 // Baseline PPC64 supports inlining atomics up to 8 bytes.
467 MaxAtomicInlineWidth = 64;
468
469 resetDataLayout();
470 }
471
472 void setMaxAtomicWidth() override {
473 // For power8 and up, backend is able to inline 16-byte atomic lock free
474 // code.
475 // TODO: We should allow AIX to inline quadword atomics in the future.
476 if (!getTriple().isOSAIX() && hasFeature(Feature: "quadword-atomics"))
477 MaxAtomicInlineWidth = 128;
478 }
479
480 BuiltinVaListKind getBuiltinVaListKind() const override {
481 return TargetInfo::CharPtrBuiltinVaList;
482 }
483
484 // PPC64 Linux-specific ABI options.
485 bool setABI(const std::string &Name) override {
486 if (Name == "elfv1" || Name == "elfv2") {
487 ABI = Name;
488 resetDataLayout();
489 return true;
490 }
491 return false;
492 }
493
494 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
495 switch (CC) {
496 case CC_Swift:
497 return CCCR_OK;
498 case CC_SwiftAsync:
499 return CCCR_Error;
500 default:
501 return CCCR_Warning;
502 }
503 }
504
505 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
506 return std::make_pair(x: 128, y: 128);
507 }
508};
509
510class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
511 public AIXTargetInfo<PPC32TargetInfo> {
512public:
513 using AIXTargetInfo::AIXTargetInfo;
514 BuiltinVaListKind getBuiltinVaListKind() const override {
515 return TargetInfo::CharPtrBuiltinVaList;
516 }
517};
518
519class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
520 public AIXTargetInfo<PPC64TargetInfo> {
521public:
522 using AIXTargetInfo::AIXTargetInfo;
523};
524
525} // namespace targets
526} // namespace clang
527#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
528