1//===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISC-V TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
15
16#include "clang/Basic/TargetInfo.h"
17#include "clang/Basic/TargetOptions.h"
18#include "llvm/Support/Compiler.h"
19#include "llvm/TargetParser/RISCVISAInfo.h"
20#include "llvm/TargetParser/Triple.h"
21#include <optional>
22
23namespace clang {
24namespace targets {
25
26// RISC-V Target
27class RISCVTargetInfo : public TargetInfo {
28protected:
29 std::string ABI, CPU;
30 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
31
32private:
33 bool FastScalarUnalignedAccess;
34 bool HasExperimental = false;
35
36public:
37 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
38 : TargetInfo(Triple) {
39 BFloat16Width = 16;
40 BFloat16Align = 16;
41 BFloat16Format = &llvm::APFloat::BFloat();
42 LongDoubleWidth = 128;
43 LongDoubleAlign = 128;
44 LongDoubleFormat = &llvm::APFloat::IEEEquad();
45 SuitableAlign = 128;
46 WCharType = SignedInt;
47 WIntType = UnsignedInt;
48 HasRISCVVTypes = true;
49 MCountName = "_mcount";
50 HasFloat16 = true;
51 HasStrictFP = true;
52 }
53
54 bool setCPU(StringRef Name) override {
55 if (!isValidCPUName(Name))
56 return false;
57 CPU = Name;
58 return true;
59 }
60
61 StringRef getABI() const override { return ABI; }
62 void getTargetDefines(const LangOptions &Opts,
63 MacroBuilder &Builder) const override;
64
65 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
66
67 BuiltinVaListKind getBuiltinVaListKind() const override {
68 return TargetInfo::VoidPtrBuiltinVaList;
69 }
70
71 std::string_view getClobbers() const override { return ""; }
72
73 StringRef getConstraintRegister(StringRef Constraint,
74 StringRef Expression) const override {
75 return Expression;
76 }
77
78 ArrayRef<const char *> getGCCRegNames() const override;
79
80 int getEHDataRegisterNumber(unsigned RegNo) const override {
81 if (RegNo == 0)
82 return 10;
83 else if (RegNo == 1)
84 return 11;
85 else
86 return -1;
87 }
88
89 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
90
91 bool validateAsmConstraint(const char *&Name,
92 TargetInfo::ConstraintInfo &Info) const override;
93
94 std::string convertConstraint(const char *&Constraint) const override;
95
96 bool
97 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
98 StringRef CPU,
99 const std::vector<std::string> &FeaturesVec) const override;
100
101 std::optional<std::pair<unsigned, unsigned>>
102 getVScaleRange(const LangOptions &LangOpts, ArmStreamingKind Mode,
103 llvm::StringMap<bool> *FeatureMap = nullptr) const override;
104
105 bool hasFeature(StringRef Feature) const override;
106
107 bool handleTargetFeatures(std::vector<std::string> &Features,
108 DiagnosticsEngine &Diags) override;
109
110 bool hasBitIntType() const override { return true; }
111
112 size_t getMaxBitIntWidth() const override {
113 return llvm::IntegerType::MAX_INT_BITS;
114 }
115
116 bool hasBFloat16Type() const override { return true; }
117
118 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
119
120 bool isValidCPUName(StringRef Name) const override;
121 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
122 bool isValidTuneCPUName(StringRef Name) const override;
123 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
124 bool supportsTargetAttributeTune() const override { return true; }
125 ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
126 llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override;
127
128 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
129 return std::make_pair(x: 64, y: 64);
130 }
131
132 bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
133 bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
134 bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
135 bool validateCpuSupports(StringRef Feature) const override;
136 bool validateCpuIs(StringRef CPUName) const override;
137 bool isValidFeatureName(StringRef Name) const override;
138
139 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
140 bool &HasSizeMismatch) const override;
141
142 bool checkCFProtectionBranchSupported(DiagnosticsEngine &) const override {
143 // Always generate Zicfilp lpad insns
144 // Non-zicfilp CPUs would read them as NOP
145 return true;
146 }
147
148 bool
149 checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const override {
150 if (ISAInfo->hasExtension(Ext: "zimop"))
151 return true;
152 return TargetInfo::checkCFProtectionReturnSupported(Diags);
153 }
154
155 CFBranchLabelSchemeKind getDefaultCFBranchLabelScheme() const override {
156 return CFBranchLabelSchemeKind::FuncSig;
157 }
158
159 bool
160 checkCFBranchLabelSchemeSupported(const CFBranchLabelSchemeKind Scheme,
161 DiagnosticsEngine &Diags) const override;
162};
163class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
164public:
165 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
166 : RISCVTargetInfo(Triple, Opts) {
167 IntPtrType = SignedInt;
168 PtrDiffType = SignedInt;
169 SizeType = UnsignedInt;
170 resetDataLayout();
171 }
172
173 bool setABI(const std::string &Name) override {
174 if (Name == "ilp32e") {
175 ABI = Name;
176 resetDataLayout();
177 return true;
178 }
179
180 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
181 ABI = Name;
182 return true;
183 }
184 return false;
185 }
186
187 void setMaxAtomicWidth() override {
188 MaxAtomicPromoteWidth = 128;
189
190 // "a" implies "zalrsc" which is sufficient to inline atomics
191 if (ISAInfo->hasExtension(Ext: "zalrsc"))
192 MaxAtomicInlineWidth = 32;
193 }
194};
195class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
196public:
197 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
198 : RISCVTargetInfo(Triple, Opts) {
199 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
200 IntMaxType = Int64Type = SignedLong;
201 resetDataLayout();
202 }
203
204 bool setABI(const std::string &Name) override {
205 if (Name == "lp64e") {
206 ABI = Name;
207 resetDataLayout();
208 return true;
209 }
210
211 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
212 ABI = Name;
213 return true;
214 }
215 return false;
216 }
217
218 void setMaxAtomicWidth() override {
219 MaxAtomicPromoteWidth = 128;
220
221 // "a" implies "zalrsc" which is sufficient to inline atomics
222 if (ISAInfo->hasExtension(Ext: "zalrsc"))
223 MaxAtomicInlineWidth = 64;
224 }
225};
226} // namespace targets
227} // namespace clang
228
229#endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
230