1//===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISC-V TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
15
16#include "clang/Basic/TargetInfo.h"
17#include "clang/Basic/TargetOptions.h"
18#include "llvm/IR/DerivedTypes.h"
19#include "llvm/Support/Compiler.h"
20#include "llvm/TargetParser/RISCVISAInfo.h"
21#include "llvm/TargetParser/Triple.h"
22#include <optional>
23
24namespace clang {
25namespace targets {
26
27// RISC-V Target
28class RISCVTargetInfo : public TargetInfo {
29protected:
30 std::string ABI, CPU;
31 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
32
33private:
34 bool FastScalarUnalignedAccess;
35 bool HasExperimental = false;
36
37public:
38 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
39 : TargetInfo(Triple) {
40 BFloat16Width = 16;
41 BFloat16Align = 16;
42 BFloat16Format = &llvm::APFloat::BFloat();
43 LongDoubleWidth = 128;
44 LongDoubleAlign = 128;
45 LongDoubleFormat = &llvm::APFloat::IEEEquad();
46 SuitableAlign = 128;
47 WCharType = SignedInt;
48 WIntType = UnsignedInt;
49 HasRISCVVTypes = true;
50 MCountName = "_mcount";
51 HasFloat16 = true;
52 HasStrictFP = true;
53 }
54
55 bool setCPU(StringRef Name) override {
56 if (!isValidCPUName(Name))
57 return false;
58 CPU = Name;
59 return true;
60 }
61
62 StringRef getABI() const override { return ABI; }
63 void getTargetDefines(const LangOptions &Opts,
64 MacroBuilder &Builder) const override;
65
66 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
67
68 BuiltinVaListKind getBuiltinVaListKind() const override {
69 return TargetInfo::VoidPtrBuiltinVaList;
70 }
71
72 std::string_view getClobbers() const override { return ""; }
73
74 StringRef getConstraintRegister(StringRef Constraint,
75 StringRef Expression) const override {
76 return Expression;
77 }
78
79 ArrayRef<const char *> getGCCRegNames() const override;
80
81 int getEHDataRegisterNumber(unsigned RegNo) const override {
82 if (RegNo == 0)
83 return 10;
84 else if (RegNo == 1)
85 return 11;
86 else
87 return -1;
88 }
89
90 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
91
92 bool validateAsmConstraint(const char *&Name,
93 TargetInfo::ConstraintInfo &Info) const override;
94
95 std::string convertConstraint(const char *&Constraint) const override;
96
97 bool
98 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
99 StringRef CPU,
100 const std::vector<std::string> &FeaturesVec) const override;
101
102 std::optional<std::pair<unsigned, unsigned>>
103 getVScaleRange(const LangOptions &LangOpts, ArmStreamingKind Mode,
104 llvm::StringMap<bool> *FeatureMap = nullptr) const override;
105
106 bool hasFeature(StringRef Feature) const override;
107
108 bool handleTargetFeatures(std::vector<std::string> &Features,
109 DiagnosticsEngine &Diags) override;
110
111 bool hasBitIntType() const override { return true; }
112
113 size_t getMaxBitIntWidth() const override {
114 return llvm::IntegerType::MAX_INT_BITS;
115 }
116
117 bool hasBFloat16Type() const override { return true; }
118
119 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
120
121 bool isValidCPUName(StringRef Name) const override;
122 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
123 bool isValidTuneCPUName(StringRef Name) const override;
124 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
125 bool supportsTargetAttributeTune() const override { return true; }
126 ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
127 llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override;
128
129 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
130 return std::make_pair(x: 64, y: 64);
131 }
132
133 bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
134 bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
135 bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
136 bool validateCpuSupports(StringRef Feature) const override;
137 bool validateCpuIs(StringRef CPUName) const override;
138 bool isValidFeatureName(StringRef Name) const override;
139
140 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
141 bool &HasSizeMismatch) const override;
142
143 bool checkCFProtectionBranchSupported(DiagnosticsEngine &) const override {
144 // Always generate Zicfilp lpad insns
145 // Non-zicfilp CPUs would read them as NOP
146 return true;
147 }
148
149 bool
150 checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const override {
151 if (ISAInfo->hasExtension(Ext: "zimop"))
152 return true;
153 return TargetInfo::checkCFProtectionReturnSupported(Diags);
154 }
155
156 CFBranchLabelSchemeKind getDefaultCFBranchLabelScheme() const override {
157 return CFBranchLabelSchemeKind::FuncSig;
158 }
159
160 bool
161 checkCFBranchLabelSchemeSupported(const CFBranchLabelSchemeKind Scheme,
162 DiagnosticsEngine &Diags) const override;
163};
164class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
165public:
166 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
167 : RISCVTargetInfo(Triple, Opts) {
168 IntPtrType = SignedInt;
169 PtrDiffType = SignedInt;
170 SizeType = UnsignedInt;
171 resetDataLayout();
172 }
173
174 bool setABI(const std::string &Name) override {
175 if (Name == "ilp32e") {
176 ABI = Name;
177 resetDataLayout();
178 return true;
179 }
180
181 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
182 ABI = Name;
183 return true;
184 }
185 return false;
186 }
187
188 void setMaxAtomicWidth() override {
189 MaxAtomicPromoteWidth = 128;
190
191 // "a" implies "zalrsc" which is sufficient to inline atomics
192 if (ISAInfo->hasExtension(Ext: "zalrsc"))
193 MaxAtomicInlineWidth = 32;
194 }
195};
196class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
197public:
198 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
199 : RISCVTargetInfo(Triple, Opts) {
200 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
201 IntMaxType = Int64Type = SignedLong;
202 resetDataLayout();
203 }
204
205 bool setABI(const std::string &Name) override {
206 if (Name == "lp64e") {
207 ABI = Name;
208 resetDataLayout();
209 return true;
210 }
211
212 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
213 ABI = Name;
214 return true;
215 }
216 return false;
217 }
218
219 void setMaxAtomicWidth() override {
220 MaxAtomicPromoteWidth = 128;
221
222 // "a" implies "zalrsc" which is sufficient to inline atomics
223 if (ISAInfo->hasExtension(Ext: "zalrsc"))
224 MaxAtomicInlineWidth = 64;
225 }
226};
227} // namespace targets
228} // namespace clang
229
230#endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
231