1//===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISC-V TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
15
16#include "clang/Basic/TargetInfo.h"
17#include "clang/Basic/TargetOptions.h"
18#include "llvm/Support/Compiler.h"
19#include "llvm/TargetParser/RISCVISAInfo.h"
20#include "llvm/TargetParser/Triple.h"
21#include <optional>
22
23namespace clang {
24namespace targets {
25
26// RISC-V Target
27class RISCVTargetInfo : public TargetInfo {
28protected:
29 std::string ABI, CPU;
30 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
31
32private:
33 bool FastScalarUnalignedAccess;
34 bool HasExperimental = false;
35
36public:
37 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
38 : TargetInfo(Triple) {
39 BFloat16Width = 16;
40 BFloat16Align = 16;
41 BFloat16Format = &llvm::APFloat::BFloat();
42 LongDoubleWidth = 128;
43 LongDoubleAlign = 128;
44 LongDoubleFormat = &llvm::APFloat::IEEEquad();
45 SuitableAlign = 128;
46 WCharType = SignedInt;
47 WIntType = UnsignedInt;
48 HasRISCVVTypes = true;
49 MCountName = "_mcount";
50 HasFloat16 = true;
51 HasStrictFP = true;
52 }
53
54 bool setCPU(StringRef Name) override {
55 if (!isValidCPUName(Name))
56 return false;
57 CPU = Name;
58 return true;
59 }
60
61 StringRef getABI() const override { return ABI; }
62 void getTargetDefines(const LangOptions &Opts,
63 MacroBuilder &Builder) const override;
64
65 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
66
67 BuiltinVaListKind getBuiltinVaListKind() const override {
68 return TargetInfo::VoidPtrBuiltinVaList;
69 }
70
71 std::string_view getClobbers() const override { return ""; }
72
73 StringRef getConstraintRegister(StringRef Constraint,
74 StringRef Expression) const override {
75 return Expression;
76 }
77
78 ArrayRef<const char *> getGCCRegNames() const override;
79
80 int getEHDataRegisterNumber(unsigned RegNo) const override {
81 if (RegNo == 0)
82 return 10;
83 else if (RegNo == 1)
84 return 11;
85 else
86 return -1;
87 }
88
89 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
90
91 bool validateAsmConstraint(const char *&Name,
92 TargetInfo::ConstraintInfo &Info) const override;
93
94 std::string convertConstraint(const char *&Constraint) const override;
95
96 bool
97 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
98 StringRef CPU,
99 const std::vector<std::string> &FeaturesVec) const override;
100
101 std::optional<std::pair<unsigned, unsigned>>
102 getVScaleRange(const LangOptions &LangOpts, ArmStreamingKind Mode,
103 llvm::StringMap<bool> *FeatureMap = nullptr) const override;
104
105 bool hasFeature(StringRef Feature) const override;
106
107 bool handleTargetFeatures(std::vector<std::string> &Features,
108 DiagnosticsEngine &Diags) override;
109
110 bool hasBitIntType() const override { return true; }
111
112 size_t getMaxBitIntWidth() const override {
113 return llvm::IntegerType::MAX_INT_BITS;
114 }
115
116 bool hasBFloat16Type() const override { return true; }
117
118 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
119
120 bool useFP16ConversionIntrinsics() const override {
121 return false;
122 }
123
124 bool isValidCPUName(StringRef Name) const override;
125 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
126 bool isValidTuneCPUName(StringRef Name) const override;
127 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
128 bool supportsTargetAttributeTune() const override { return true; }
129 ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
130 llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override;
131
132 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
133 return std::make_pair(x: 64, y: 64);
134 }
135
136 bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
137 bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
138 bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
139 bool validateCpuSupports(StringRef Feature) const override;
140 bool validateCpuIs(StringRef CPUName) const override;
141 bool isValidFeatureName(StringRef Name) const override;
142
143 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
144 bool &HasSizeMismatch) const override;
145
146 bool checkCFProtectionBranchSupported(DiagnosticsEngine &) const override {
147 // Always generate Zicfilp lpad insns
148 // Non-zicfilp CPUs would read them as NOP
149 return true;
150 }
151
152 bool
153 checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const override {
154 if (ISAInfo->hasExtension(Ext: "zimop"))
155 return true;
156 return TargetInfo::checkCFProtectionReturnSupported(Diags);
157 }
158
159 CFBranchLabelSchemeKind getDefaultCFBranchLabelScheme() const override {
160 return CFBranchLabelSchemeKind::FuncSig;
161 }
162
163 bool
164 checkCFBranchLabelSchemeSupported(const CFBranchLabelSchemeKind Scheme,
165 DiagnosticsEngine &Diags) const override;
166};
167class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
168public:
169 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
170 : RISCVTargetInfo(Triple, Opts) {
171 IntPtrType = SignedInt;
172 PtrDiffType = SignedInt;
173 SizeType = UnsignedInt;
174 resetDataLayout();
175 }
176
177 bool setABI(const std::string &Name) override {
178 if (Name == "ilp32e") {
179 ABI = Name;
180 resetDataLayout();
181 return true;
182 }
183
184 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
185 ABI = Name;
186 return true;
187 }
188 return false;
189 }
190
191 void setMaxAtomicWidth() override {
192 MaxAtomicPromoteWidth = 128;
193
194 // "a" implies "zalrsc" which is sufficient to inline atomics
195 if (ISAInfo->hasExtension(Ext: "zalrsc"))
196 MaxAtomicInlineWidth = 32;
197 }
198};
199class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
200public:
201 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
202 : RISCVTargetInfo(Triple, Opts) {
203 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
204 IntMaxType = Int64Type = SignedLong;
205 resetDataLayout();
206 }
207
208 bool setABI(const std::string &Name) override {
209 if (Name == "lp64e") {
210 ABI = Name;
211 resetDataLayout();
212 return true;
213 }
214
215 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
216 ABI = Name;
217 return true;
218 }
219 return false;
220 }
221
222 void setMaxAtomicWidth() override {
223 MaxAtomicPromoteWidth = 128;
224
225 // "a" implies "zalrsc" which is sufficient to inline atomics
226 if (ISAInfo->hasExtension(Ext: "zalrsc"))
227 MaxAtomicInlineWidth = 64;
228 }
229};
230} // namespace targets
231} // namespace clang
232
233#endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
234