1//===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements SystemZ TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SystemZ.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/LangOptions.h"
16#include "clang/Basic/MacroBuilder.h"
17#include "clang/Basic/TargetBuiltins.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/ADT/StringSwitch.h"
20
21using namespace clang;
22using namespace clang::targets;
23
24static constexpr int NumBuiltins =
25 clang::SystemZ::LastTSBuiltin - Builtin::FirstTSBuiltin;
26
27static constexpr llvm::StringTable BuiltinStrings =
28 CLANG_BUILTIN_STR_TABLE_START
29#define BUILTIN CLANG_BUILTIN_STR_TABLE
30#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
31#include "clang/Basic/BuiltinsSystemZ.def"
32 ;
33
34static constexpr auto BuiltinInfos = Builtin::MakeInfos<NumBuiltins>(Infos: {
35#define BUILTIN CLANG_BUILTIN_ENTRY
36#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
37#include "clang/Basic/BuiltinsSystemZ.def"
38});
39
40const char *const SystemZTargetInfo::GCCRegNames[] = {
41 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
42 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
43 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
44 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15",
45 /*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0", "a1",
46 "v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23",
47 "v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31"
48};
49
50const TargetInfo::AddlRegName GCCAddlRegNames[] = {
51 {.Names: {"v0"}, .RegNum: 16}, {.Names: {"v2"}, .RegNum: 17}, {.Names: {"v4"}, .RegNum: 18}, {.Names: {"v6"}, .RegNum: 19},
52 {.Names: {"v1"}, .RegNum: 20}, {.Names: {"v3"}, .RegNum: 21}, {.Names: {"v5"}, .RegNum: 22}, {.Names: {"v7"}, .RegNum: 23},
53 {.Names: {"v8"}, .RegNum: 24}, {.Names: {"v10"}, .RegNum: 25}, {.Names: {"v12"}, .RegNum: 26}, {.Names: {"v14"}, .RegNum: 27},
54 {.Names: {"v9"}, .RegNum: 28}, {.Names: {"v11"}, .RegNum: 29}, {.Names: {"v13"}, .RegNum: 30}, {.Names: {"v15"}, .RegNum: 31}
55};
56
57ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
58 return llvm::ArrayRef(GCCRegNames);
59}
60
61ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const {
62 return llvm::ArrayRef(GCCAddlRegNames);
63}
64
65bool SystemZTargetInfo::validateAsmConstraint(
66 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
67 switch (*Name) {
68 default:
69 return false;
70
71 case 'Z':
72 switch (Name[1]) {
73 default:
74 return false;
75 case 'Q': // Address with base and unsigned 12-bit displacement
76 case 'R': // Likewise, plus an index
77 case 'S': // Address with base and signed 20-bit displacement
78 case 'T': // Likewise, plus an index
79 break;
80 }
81 [[fallthrough]];
82 case 'a': // Address register
83 case 'd': // Data register (equivalent to 'r')
84 case 'f': // Floating-point register
85 case 'v': // Vector register
86 Info.setAllowsRegister();
87 return true;
88
89 case 'I': // Unsigned 8-bit constant
90 case 'J': // Unsigned 12-bit constant
91 case 'K': // Signed 16-bit constant
92 case 'L': // Signed 20-bit displacement (on all targets we support)
93 case 'M': // 0x7fffffff
94 return true;
95
96 case 'Q': // Memory with base and unsigned 12-bit displacement
97 case 'R': // Likewise, plus an index
98 case 'S': // Memory with base and signed 20-bit displacement
99 case 'T': // Likewise, plus an index
100 Info.setAllowsMemory();
101 return true;
102 case '@':
103 // CC condition changes.
104 if (StringRef(Name) == "@cc") {
105 Name += 2;
106 Info.setAllowsRegister();
107 // SystemZ has 2-bits CC, and hence Interval [0, 4).
108 Info.setOutputOperandBounds(Min: 0, Max: 4);
109 return true;
110 }
111 return false;
112 }
113}
114
115struct ISANameRevision {
116 llvm::StringLiteral Name;
117 int ISARevisionID;
118};
119static constexpr ISANameRevision ISARevisions[] = {
120 {.Name: {"arch8"}, .ISARevisionID: 8}, {.Name: {"z10"}, .ISARevisionID: 8},
121 {.Name: {"arch9"}, .ISARevisionID: 9}, {.Name: {"z196"}, .ISARevisionID: 9},
122 {.Name: {"arch10"}, .ISARevisionID: 10}, {.Name: {"zEC12"}, .ISARevisionID: 10},
123 {.Name: {"arch11"}, .ISARevisionID: 11}, {.Name: {"z13"}, .ISARevisionID: 11},
124 {.Name: {"arch12"}, .ISARevisionID: 12}, {.Name: {"z14"}, .ISARevisionID: 12},
125 {.Name: {"arch13"}, .ISARevisionID: 13}, {.Name: {"z15"}, .ISARevisionID: 13},
126 {.Name: {"arch14"}, .ISARevisionID: 14}, {.Name: {"z16"}, .ISARevisionID: 14},
127 {.Name: {"arch15"}, .ISARevisionID: 15}, {.Name: {"z17"}, .ISARevisionID: 15},
128};
129
130int SystemZTargetInfo::getISARevision(StringRef Name) const {
131 const auto Rev =
132 llvm::find_if(Range: ISARevisions, P: [Name](const ISANameRevision &CR) {
133 return CR.Name == Name;
134 });
135 if (Rev == std::end(arr: ISARevisions))
136 return -1;
137 return Rev->ISARevisionID;
138}
139
140void SystemZTargetInfo::fillValidCPUList(
141 SmallVectorImpl<StringRef> &Values) const {
142 for (const ISANameRevision &Rev : ISARevisions)
143 Values.push_back(Elt: Rev.Name);
144}
145
146bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
147 return llvm::StringSwitch<bool>(Feature)
148 .Case(S: "systemz", Value: true)
149 .Case(S: "arch8", Value: ISARevision >= 8)
150 .Case(S: "arch9", Value: ISARevision >= 9)
151 .Case(S: "arch10", Value: ISARevision >= 10)
152 .Case(S: "arch11", Value: ISARevision >= 11)
153 .Case(S: "arch12", Value: ISARevision >= 12)
154 .Case(S: "arch13", Value: ISARevision >= 13)
155 .Case(S: "arch14", Value: ISARevision >= 14)
156 .Case(S: "arch15", Value: ISARevision >= 15)
157 .Case(S: "htm", Value: HasTransactionalExecution)
158 .Case(S: "vx", Value: HasVector)
159 .Default(Value: false);
160}
161
162unsigned SystemZTargetInfo::getMinGlobalAlign(uint64_t Size,
163 bool HasNonWeakDef) const {
164 // Don't enforce the minimum alignment on an external or weak symbol if
165 // -munaligned-symbols is passed.
166 if (UnalignedSymbols && !HasNonWeakDef)
167 return 0;
168
169 return MinGlobalAlign;
170}
171
172void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
173 MacroBuilder &Builder) const {
174 // Inline assembly supports SystemZ flag outputs.
175 Builder.defineMacro(Name: "__GCC_ASM_FLAG_OUTPUTS__");
176
177 Builder.defineMacro(Name: "__s390__");
178 Builder.defineMacro(Name: "__s390x__");
179 Builder.defineMacro(Name: "__zarch__");
180 Builder.defineMacro(Name: "__LONG_DOUBLE_128__");
181
182 Builder.defineMacro(Name: "__ARCH__", Value: Twine(ISARevision));
183
184 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
185 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
186 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
187 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
188
189 if (HasTransactionalExecution)
190 Builder.defineMacro(Name: "__HTM__");
191 if (HasVector)
192 Builder.defineMacro(Name: "__VX__");
193 if (Opts.ZVector)
194 Builder.defineMacro(Name: "__VEC__", Value: "10305");
195
196 /* Set __TARGET_LIB__ only if a value was given. If no value was given */
197 /* we rely on the LE headers to define __TARGET_LIB__. */
198 if (!getTriple().getOSVersion().empty()) {
199 llvm::VersionTuple V = getTriple().getOSVersion();
200 // Create string with form: 0xPVRRMMMM, where P=4
201 std::string Str("0x");
202 unsigned int Librel = 0x40000000;
203 Librel |= V.getMajor() << 24;
204 Librel |= V.getMinor().value_or(u: 1) << 16;
205 Librel |= V.getSubminor().value_or(u: 0);
206 Str += llvm::utohexstr(X: Librel);
207
208 Builder.defineMacro(Name: "__TARGET_LIB__", Value: Str);
209 }
210}
211
212llvm::SmallVector<Builtin::InfosShard>
213SystemZTargetInfo::getTargetBuiltins() const {
214 return {{.Strings: &BuiltinStrings, .Infos: BuiltinInfos}};
215}
216