1//===--- X86.h - Declare X86 target feature support -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_X86_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_X86_H
15
16#include "OSTargets.h"
17#include "clang/Basic/BitmaskEnum.h"
18#include "clang/Basic/TargetInfo.h"
19#include "clang/Basic/TargetOptions.h"
20#include "llvm/IR/DerivedTypes.h"
21#include "llvm/Support/Compiler.h"
22#include "llvm/TargetParser/Triple.h"
23#include "llvm/TargetParser/X86TargetParser.h"
24#include <optional>
25
26namespace clang {
27namespace targets {
28
29static constexpr LangASMap X86AddrSpaceMap = {
30 {LangAS::ptr32_sptr, 270},
31 {LangAS::ptr32_uptr, 271},
32 {LangAS::ptr64, 272},
33};
34
35// X86 target abstract base class; x86-32 and x86-64 are very close, so
36// most of the implementation can be shared.
37class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
38
39 enum X86SSEEnum {
40 NoSSE,
41 SSE1,
42 SSE2,
43 SSE3,
44 SSSE3,
45 SSE41,
46 SSE42,
47 AVX,
48 AVX2,
49 AVX512F
50 } SSELevel = NoSSE;
51 bool HasMMX = false;
52 enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP;
53 enum AddrSpace { ptr32_sptr = 270, ptr32_uptr = 271, ptr64 = 272 };
54
55 bool HasAES = false;
56 bool HasVAES = false;
57 bool HasPCLMUL = false;
58 bool HasVPCLMULQDQ = false;
59 bool HasGFNI = false;
60 bool HasLZCNT = false;
61 bool HasRDRND = false;
62 bool HasFSGSBASE = false;
63 bool HasBMI = false;
64 bool HasBMI2 = false;
65 bool HasPOPCNT = false;
66 bool HasRTM = false;
67 bool HasPRFCHW = false;
68 bool HasRDSEED = false;
69 bool HasADX = false;
70 bool HasTBM = false;
71 bool HasLWP = false;
72 bool HasFMA = false;
73 bool HasF16C = false;
74 bool HasAVX10_1 = false;
75 bool HasAVX10_2 = false;
76 bool HasAVX512CD = false;
77 bool HasAVX512VPOPCNTDQ = false;
78 bool HasAVX512VNNI = false;
79 bool HasAVX512FP16 = false;
80 bool HasAVX512BF16 = false;
81 bool HasAVX512DQ = false;
82 bool HasAVX512BITALG = false;
83 bool HasAVX512BMM = false;
84 bool HasAVX512BW = false;
85 bool HasAVX512VL = false;
86 bool HasAVX512VBMI = false;
87 bool HasAVX512VBMI2 = false;
88 bool HasAVXIFMA = false;
89 bool HasAVX512IFMA = false;
90 bool HasAVX512VP2INTERSECT = false;
91 bool HasSHA = false;
92 bool HasSHA512 = false;
93 bool HasSHSTK = false;
94 bool HasSM3 = false;
95 bool HasSGX = false;
96 bool HasSM4 = false;
97 bool HasCX8 = false;
98 bool HasCX16 = false;
99 bool HasFXSR = false;
100 bool HasXSAVE = false;
101 bool HasXSAVEOPT = false;
102 bool HasXSAVEC = false;
103 bool HasXSAVES = false;
104 bool HasMWAITX = false;
105 bool HasCLZERO = false;
106 bool HasCLDEMOTE = false;
107 bool HasPCONFIG = false;
108 bool HasPKU = false;
109 bool HasCLFLUSHOPT = false;
110 bool HasCLWB = false;
111 bool HasMOVBE = false;
112 bool HasMOVRS = false;
113 bool HasPREFETCHI = false;
114 bool HasRDPID = false;
115 bool HasRDPRU = false;
116 bool HasRetpolineExternalThunk = false;
117 bool HasLAHFSAHF = false;
118 bool HasWBNOINVD = false;
119 bool HasWAITPKG = false;
120 bool HasMOVDIRI = false;
121 bool HasMOVDIR64B = false;
122 bool HasPTWRITE = false;
123 bool HasINVPCID = false;
124 bool HasENQCMD = false;
125 bool HasAVXVNNIINT16 = false;
126 bool HasAMXFP16 = false;
127 bool HasCMPCCXADD = false;
128 bool HasRAOINT = false;
129 bool HasAVXVNNIINT8 = false;
130 bool HasAVXNECONVERT = false;
131 bool HasKL = false; // For key locker
132 bool HasWIDEKL = false; // For wide key locker
133 bool HasHRESET = false;
134 bool HasAVXVNNI = false;
135 bool HasAMXTILE = false;
136 bool HasAMXINT8 = false;
137 bool HasAMXBF16 = false;
138 bool HasAMXCOMPLEX = false;
139 bool HasAMXFP8 = false;
140 bool HasAMXMOVRS = false;
141 bool HasAMXAVX512 = false;
142 bool HasSERIALIZE = false;
143 bool HasTSXLDTRK = false;
144 bool HasUSERMSR = false;
145 bool HasUINTR = false;
146 bool HasCRC32 = false;
147 bool HasX87 = false;
148 bool HasEGPR = false;
149 bool HasPush2Pop2 = false;
150 bool HasPPX = false;
151 bool HasNDD = false;
152 bool HasCCMP = false;
153 bool HasNF = false;
154 bool HasCF = false;
155 bool HasZU = false;
156 bool HasJMPABS = false;
157 bool HasInlineAsmUseGPR32 = false;
158 bool HasBranchHint = false;
159
160protected:
161 llvm::X86::CPUKind CPU = llvm::X86::CK_None;
162
163 enum FPMathKind { FP_Default, FP_SSE, FP_387 } FPMath = FP_Default;
164
165public:
166 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
167 : TargetInfo(Triple) {
168 BFloat16Width = BFloat16Align = 16;
169 BFloat16Format = &llvm::APFloat::BFloat();
170 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
171 AddrSpaceMap = &X86AddrSpaceMap;
172 HasStrictFP = true;
173 HasUnalignedAccess = true;
174
175 bool IsWinCOFF =
176 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
177 if (IsWinCOFF)
178 MaxVectorAlign = MaxTLSAlign = 8192u * getCharWidth();
179 }
180
181 const char *getLongDoubleMangling() const override {
182 return LongDoubleFormat == &llvm::APFloat::IEEEquad() ? "g" : "e";
183 }
184
185 LangOptions::FPEvalMethodKind getFPEvalMethod() const override {
186 // X87 evaluates with 80 bits "long double" precision.
187 return SSELevel == NoSSE ? LangOptions::FPEvalMethodKind::FEM_Extended
188 : LangOptions::FPEvalMethodKind::FEM_Source;
189 }
190
191 // EvalMethod `source` is not supported for targets with `NoSSE` feature.
192 bool supportSourceEvalMethod() const override { return SSELevel > NoSSE; }
193
194 ArrayRef<const char *> getGCCRegNames() const override;
195
196 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
197 return {};
198 }
199
200 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
201
202 bool isSPRegName(StringRef RegName) const override {
203 return RegName == "esp" || RegName == "rsp";
204 }
205
206 bool supportsCpuSupports() const override { return true; }
207 bool supportsCpuIs() const override { return true; }
208 bool supportsCpuInit() const override { return true; }
209
210 bool validateCpuSupports(StringRef FeatureStr) const override;
211
212 bool validateCpuIs(StringRef FeatureStr) const override;
213
214 bool validateCPUSpecificCPUDispatch(StringRef Name) const override;
215
216 char CPUSpecificManglingCharacter(StringRef Name) const override;
217
218 void getCPUSpecificCPUDispatchFeatures(
219 StringRef Name,
220 llvm::SmallVectorImpl<StringRef> &Features) const override;
221
222 std::optional<unsigned> getCPUCacheLineSize() const override;
223
224 bool validateAsmConstraint(const char *&Name,
225 TargetInfo::ConstraintInfo &info) const override;
226
227 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
228 bool &HasSizeMismatch) const override {
229 // esp and ebp are the only 32-bit registers the x86 backend can currently
230 // handle.
231 if (RegName == "esp" || RegName == "ebp") {
232 // Check that the register size is 32-bit.
233 HasSizeMismatch = RegSize != 32;
234 return true;
235 }
236 if (RegName.ends_with(Suffix: "di")) {
237 if (getTargetOpts().FeatureMap.lookup(Key: "reserve-edi")) {
238 if (RegName == "edi") {
239 HasSizeMismatch = RegSize != 32;
240 } else if (RegName == "di") {
241 HasSizeMismatch = RegSize != 16;
242 }
243 return true;
244 }
245 }
246
247 return false;
248 }
249
250 bool validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
251 StringRef Constraint, unsigned Size) const override;
252
253 bool validateInputSize(const llvm::StringMap<bool> &FeatureMap,
254 StringRef Constraint, unsigned Size) const override;
255
256 bool
257 checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const override {
258 if (CPU == llvm::X86::CK_None || CPU >= llvm::X86::CK_PentiumPro)
259 return true;
260 return TargetInfo::checkCFProtectionReturnSupported(Diags);
261 };
262
263 bool
264 checkCFProtectionBranchSupported(DiagnosticsEngine &Diags) const override {
265 if (CPU == llvm::X86::CK_None || CPU >= llvm::X86::CK_PentiumPro)
266 return true;
267 return TargetInfo::checkCFProtectionBranchSupported(Diags);
268 };
269
270 virtual bool validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
271 StringRef Constraint, unsigned Size) const;
272
273 std::string convertConstraint(const char *&Constraint) const override;
274 std::string_view getClobbers() const override {
275 return "~{dirflag},~{fpsr},~{flags}";
276 }
277
278 StringRef getConstraintRegister(StringRef Constraint,
279 StringRef Expression) const override {
280 StringRef::iterator I, E;
281 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
282 if (isalpha(*I) || *I == '@')
283 break;
284 }
285 if (I == E)
286 return "";
287 switch (*I) {
288 // For the register constraints, return the matching register name
289 case 'a':
290 return "ax";
291 case 'b':
292 return "bx";
293 case 'c':
294 return "cx";
295 case 'd':
296 return "dx";
297 case 'S':
298 return "si";
299 case 'D':
300 return "di";
301 // In case the constraint is 'r' we need to return Expression
302 case 'r':
303 return Expression;
304 // Double letters Y<x> constraints
305 case 'Y':
306 if ((++I != E) && ((*I == '0') || (*I == 'z')))
307 return "xmm0";
308 break;
309 default:
310 break;
311 }
312 return "";
313 }
314
315 void getTargetDefines(const LangOptions &Opts,
316 MacroBuilder &Builder) const override;
317
318 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
319 bool Enabled) const final;
320
321 bool
322 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
323 StringRef CPU,
324 const std::vector<std::string> &FeaturesVec) const override;
325
326 bool isValidFeatureName(StringRef Name) const override;
327
328 bool hasFeature(StringRef Feature) const final;
329
330 bool handleTargetFeatures(std::vector<std::string> &Features,
331 DiagnosticsEngine &Diags) override;
332
333 StringRef getABI() const override {
334 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
335 return "avx512";
336 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
337 return "avx";
338 if (getTriple().getArch() == llvm::Triple::x86 && !HasMMX)
339 return "no-mmx";
340 return "";
341 }
342
343 bool supportsTargetAttributeTune() const override {
344 return true;
345 }
346
347 bool isValidCPUName(StringRef Name) const override {
348 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
349 return llvm::X86::parseArchX86(CPU: Name, Only64Bit) != llvm::X86::CK_None;
350 }
351
352 bool isValidTuneCPUName(StringRef Name) const override {
353 if (Name == "generic")
354 return true;
355
356 // Allow 32-bit only CPUs regardless of 64-bit mode unlike isValidCPUName.
357 // NOTE: gcc rejects 32-bit mtune CPUs in 64-bit mode. But being lenient
358 // since mtune was ignored by clang for so long.
359 return llvm::X86::parseTuneCPU(CPU: Name) != llvm::X86::CK_None;
360 }
361
362 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
363 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
364
365 bool setCPU(StringRef Name) override {
366 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
367 CPU = llvm::X86::parseArchX86(CPU: Name, Only64Bit);
368 return CPU != llvm::X86::CK_None;
369 }
370
371 llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override;
372
373 bool setFPMath(StringRef Name) override;
374
375 bool supportsExtendIntArgs() const override {
376 return getTriple().getArch() != llvm::Triple::x86;
377 }
378
379 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
380 // Most of the non-ARM calling conventions are i386 conventions.
381 switch (CC) {
382 case CC_X86ThisCall:
383 case CC_X86FastCall:
384 case CC_X86StdCall:
385 case CC_X86VectorCall:
386 case CC_X86RegCall:
387 case CC_C:
388 case CC_PreserveMost:
389 case CC_Swift:
390 case CC_X86Pascal:
391 case CC_IntelOclBicc:
392 return CCCR_OK;
393 case CC_SwiftAsync:
394 return CCCR_Error;
395 case CC_DeviceKernel:
396 return IsOpenCL ? CCCR_OK : CCCR_Warning;
397 default:
398 return CCCR_Warning;
399 }
400 }
401
402 bool checkArithmeticFenceSupported() const override { return true; }
403
404 CallingConv getDefaultCallingConv() const override {
405 return CC_C;
406 }
407
408 bool hasSjLjLowering() const override { return true; }
409
410 void setSupportedOpenCLOpts() override { supportAllOpenCLOpts(); }
411
412 uint64_t getPointerWidthV(LangAS AS) const override {
413 unsigned TargetAddrSpace = getTargetAddressSpace(AS);
414 if (TargetAddrSpace == ptr32_sptr || TargetAddrSpace == ptr32_uptr)
415 return 32;
416 if (TargetAddrSpace == ptr64)
417 return 64;
418 return PointerWidth;
419 }
420
421 uint64_t getPointerAlignV(LangAS AddrSpace) const override {
422 return getPointerWidthV(AS: AddrSpace);
423 }
424 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts,
425 const TargetInfo *Aux) override {
426 TargetInfo::adjust(Diags, Opts, Aux);
427 IsOpenCL = Opts.OpenCL;
428 }
429
430private:
431 bool IsOpenCL = false;
432};
433
434// X86-32 generic target
435class LLVM_LIBRARY_VISIBILITY X86_32TargetInfo : public X86TargetInfo {
436public:
437 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
438 : X86TargetInfo(Triple, Opts) {
439 DoubleAlign = LongLongAlign = 32;
440 LongDoubleWidth = 96;
441 LongDoubleAlign = 32;
442 SuitableAlign = 128;
443 resetDataLayout();
444 SizeType = UnsignedInt;
445 PtrDiffType = SignedInt;
446 IntPtrType = SignedInt;
447 RegParmMax = 3;
448
449 // Use fpret for all types.
450 RealTypeUsesObjCFPRetMask =
451 (unsigned)(FloatModeKind::Float | FloatModeKind::Double |
452 FloatModeKind::LongDouble);
453
454 // x86-32 has atomics up to 8 bytes
455 MaxAtomicPromoteWidth = 64;
456 MaxAtomicInlineWidth = 32;
457 }
458
459 BuiltinVaListKind getBuiltinVaListKind() const override {
460 return TargetInfo::CharPtrBuiltinVaList;
461 }
462
463 int getEHDataRegisterNumber(unsigned RegNo) const override {
464 if (RegNo == 0)
465 return 0;
466 if (RegNo == 1)
467 return 2;
468 return -1;
469 }
470
471 bool validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
472 StringRef Constraint, unsigned Size) const override {
473 switch (Constraint[0]) {
474 default:
475 break;
476 case 'R':
477 case 'q':
478 case 'Q':
479 case 'a':
480 case 'b':
481 case 'c':
482 case 'd':
483 case 'S':
484 case 'D':
485 return Size <= 32;
486 case 'A':
487 return Size <= 64;
488 }
489
490 return X86TargetInfo::validateOperandSize(FeatureMap, Constraint, Size);
491 }
492
493 void setMaxAtomicWidth() override {
494 if (hasFeature(Feature: "cx8"))
495 MaxAtomicInlineWidth = 64;
496 }
497
498 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
499
500 bool hasBitIntType() const override { return true; }
501 size_t getMaxBitIntWidth() const override {
502 return llvm::IntegerType::MAX_INT_BITS;
503 }
504};
505
506class LLVM_LIBRARY_VISIBILITY NetBSDI386TargetInfo
507 : public NetBSDTargetInfo<X86_32TargetInfo> {
508public:
509 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
510 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
511};
512
513class LLVM_LIBRARY_VISIBILITY OpenBSDI386TargetInfo
514 : public OpenBSDTargetInfo<X86_32TargetInfo> {
515public:
516 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
517 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
518 SizeType = UnsignedLong;
519 IntPtrType = SignedLong;
520 PtrDiffType = SignedLong;
521 }
522};
523
524class LLVM_LIBRARY_VISIBILITY AppleMachOI386TargetInfo
525 : public AppleMachOTargetInfo<X86_32TargetInfo> {
526public:
527 AppleMachOI386TargetInfo(const llvm::Triple &Triple,
528 const TargetOptions &Opts)
529 : AppleMachOTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
530};
531
532class LLVM_LIBRARY_VISIBILITY DarwinI386TargetInfo
533 : public DarwinTargetInfo<X86_32TargetInfo> {
534public:
535 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
536 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
537 LongDoubleWidth = 128;
538 LongDoubleAlign = 128;
539 SuitableAlign = 128;
540 MaxVectorAlign = 256;
541 // The watchOS simulator uses the builtin bool type for Objective-C.
542 llvm::Triple T = llvm::Triple(Triple);
543 if (T.isWatchOS())
544 UseSignedCharForObjCBool = false;
545 SizeType = UnsignedLong;
546 IntPtrType = SignedLong;
547 resetDataLayout();
548 HasAlignMac68kSupport = true;
549 }
550
551 bool handleTargetFeatures(std::vector<std::string> &Features,
552 DiagnosticsEngine &Diags) override {
553 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
554 Diags))
555 return false;
556 // We now know the features we have: we can decide how to align vectors.
557 MaxVectorAlign =
558 hasFeature(Feature: "avx512f") ? 512 : hasFeature(Feature: "avx") ? 256 : 128;
559 return true;
560 }
561};
562
563// x86-32 Windows target
564class LLVM_LIBRARY_VISIBILITY WindowsX86_32TargetInfo
565 : public WindowsTargetInfo<X86_32TargetInfo> {
566public:
567 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
568 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
569 DoubleAlign = LongLongAlign = 64;
570 bool IsWinCOFF =
571 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
572 bool IsMSVC = getTriple().isWindowsMSVCEnvironment();
573 std::string Layout = IsWinCOFF ? "e-m:x" : "e-m:e";
574 Layout += "-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-";
575 Layout += IsMSVC ? "f80:128" : "f80:32";
576 Layout += "-n8:16:32-a:0:32-S32";
577 if (IsWinCOFF)
578 UserLabelPrefix = "_";
579 resetDataLayout();
580 }
581};
582
583// x86-32 Windows Visual Studio target
584class LLVM_LIBRARY_VISIBILITY MicrosoftX86_32TargetInfo
585 : public WindowsX86_32TargetInfo {
586public:
587 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
588 const TargetOptions &Opts)
589 : WindowsX86_32TargetInfo(Triple, Opts) {
590 LongDoubleWidth = LongDoubleAlign = 64;
591 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
592 }
593
594 void getTargetDefines(const LangOptions &Opts,
595 MacroBuilder &Builder) const override {
596 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
597 // The value of the following reflects processor type.
598 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
599 // We lost the original triple, so we use the default.
600 Builder.defineMacro(Name: "_M_IX86", Value: "600");
601 }
602};
603
604// x86-32 MinGW target
605class LLVM_LIBRARY_VISIBILITY MinGWX86_32TargetInfo
606 : public WindowsX86_32TargetInfo {
607public:
608 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
609 : WindowsX86_32TargetInfo(Triple, Opts) {
610 HasFloat128 = true;
611 }
612
613 void getTargetDefines(const LangOptions &Opts,
614 MacroBuilder &Builder) const override {
615 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
616 Builder.defineMacro(Name: "_X86_");
617 }
618};
619
620// x86-32 Cygwin target
621class LLVM_LIBRARY_VISIBILITY CygwinX86_32TargetInfo : public X86_32TargetInfo {
622public:
623 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
624 : X86_32TargetInfo(Triple, Opts) {
625 this->WCharType = TargetInfo::UnsignedShort;
626 this->WIntType = TargetInfo::UnsignedInt;
627 this->UseMicrosoftManglingForC = true;
628 DoubleAlign = LongLongAlign = 64;
629 UserLabelPrefix = "_";
630 resetDataLayout();
631 }
632
633 void getTargetDefines(const LangOptions &Opts,
634 MacroBuilder &Builder) const override {
635 X86_32TargetInfo::getTargetDefines(Opts, Builder);
636 Builder.defineMacro(Name: "_X86_");
637 Builder.defineMacro(Name: "__CYGWIN__");
638 Builder.defineMacro(Name: "__CYGWIN32__");
639 addCygMingDefines(Opts, Builder);
640 DefineStd(Builder, MacroName: "unix", Opts);
641 if (Opts.CPlusPlus)
642 Builder.defineMacro(Name: "_GNU_SOURCE");
643 }
644};
645
646// x86-32 Haiku target
647class LLVM_LIBRARY_VISIBILITY HaikuX86_32TargetInfo
648 : public HaikuTargetInfo<X86_32TargetInfo> {
649public:
650 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
651 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
652
653 void getTargetDefines(const LangOptions &Opts,
654 MacroBuilder &Builder) const override {
655 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
656 Builder.defineMacro(Name: "__INTEL__");
657 }
658};
659
660// X86-32 MCU target
661class LLVM_LIBRARY_VISIBILITY MCUX86_32TargetInfo : public X86_32TargetInfo {
662public:
663 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
664 : X86_32TargetInfo(Triple, Opts) {
665 LongDoubleWidth = 64;
666 DefaultAlignForAttributeAligned = 32;
667 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
668 resetDataLayout();
669 WIntType = UnsignedInt;
670 }
671
672 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
673 // On MCU we support only C calling convention.
674 return CC == CC_C ? CCCR_OK : CCCR_Warning;
675 }
676
677 void getTargetDefines(const LangOptions &Opts,
678 MacroBuilder &Builder) const override {
679 X86_32TargetInfo::getTargetDefines(Opts, Builder);
680 Builder.defineMacro(Name: "__iamcu");
681 Builder.defineMacro(Name: "__iamcu__");
682 }
683
684 bool allowsLargerPreferedTypeAlignment() const override { return false; }
685};
686
687// x86-32 RTEMS target
688class LLVM_LIBRARY_VISIBILITY RTEMSX86_32TargetInfo : public X86_32TargetInfo {
689public:
690 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
691 : X86_32TargetInfo(Triple, Opts) {
692 SizeType = UnsignedLong;
693 IntPtrType = SignedLong;
694 PtrDiffType = SignedLong;
695 }
696
697 void getTargetDefines(const LangOptions &Opts,
698 MacroBuilder &Builder) const override {
699 X86_32TargetInfo::getTargetDefines(Opts, Builder);
700 Builder.defineMacro(Name: "__INTEL__");
701 Builder.defineMacro(Name: "__rtems__");
702 }
703};
704
705// x86-64 generic target
706class LLVM_LIBRARY_VISIBILITY X86_64TargetInfo : public X86TargetInfo {
707public:
708 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
709 : X86TargetInfo(Triple, Opts) {
710 const bool IsX32 = getTriple().isX32();
711 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
712 LongDoubleWidth = 128;
713 LongDoubleAlign = 128;
714 LargeArrayMinWidth = 128;
715 LargeArrayAlign = 128;
716 SuitableAlign = 128;
717 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
718 PtrDiffType = IsX32 ? SignedInt : SignedLong;
719 IntPtrType = IsX32 ? SignedInt : SignedLong;
720 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
721 Int64Type = IsX32 ? SignedLongLong : SignedLong;
722 RegParmMax = 6;
723
724 resetDataLayout();
725
726 // Use fpret only for long double.
727 RealTypeUsesObjCFPRetMask = (unsigned)FloatModeKind::LongDouble;
728
729 // Use fp2ret for _Complex long double.
730 ComplexLongDoubleUsesFP2Ret = true;
731
732 // Make __builtin_ms_va_list available.
733 HasBuiltinMSVaList = true;
734
735 // x86-64 has atomics up to 16 bytes.
736 MaxAtomicPromoteWidth = 128;
737 MaxAtomicInlineWidth = 64;
738 }
739
740 BuiltinVaListKind getBuiltinVaListKind() const override {
741 return TargetInfo::X86_64ABIBuiltinVaList;
742 }
743
744 int getEHDataRegisterNumber(unsigned RegNo) const override {
745 if (RegNo == 0)
746 return 0;
747 if (RegNo == 1)
748 return 1;
749 return -1;
750 }
751
752 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
753 switch (CC) {
754 case CC_C:
755 case CC_Swift:
756 case CC_SwiftAsync:
757 case CC_X86VectorCall:
758 case CC_IntelOclBicc:
759 case CC_Win64:
760 case CC_PreserveMost:
761 case CC_PreserveAll:
762 case CC_PreserveNone:
763 case CC_X86RegCall:
764 return CCCR_OK;
765 case CC_DeviceKernel:
766 return IsOpenCL ? CCCR_OK : CCCR_Warning;
767 default:
768 return CCCR_Warning;
769 }
770 }
771
772 CallingConv getDefaultCallingConv() const override {
773 return CC_C;
774 }
775
776 // for x32 we need it here explicitly
777 bool hasInt128Type() const override { return true; }
778
779 unsigned getUnwindWordWidth() const override { return 64; }
780
781 unsigned getRegisterWidth() const override { return 64; }
782
783 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
784 bool &HasSizeMismatch) const override {
785 // rsp and rbp are the only 64-bit registers the x86 backend can currently
786 // handle.
787 if (RegName == "rsp" || RegName == "rbp") {
788 // Check that the register size is 64-bit.
789 HasSizeMismatch = RegSize != 64;
790 return true;
791 }
792
793 // -ffixed-r8 through -ffixed-r31 are lowered to reserve-r8 through
794 // reserve-r31 target features, so canonicalize subregister spellings
795 // like r15d/r15w/r15b back to the corresponding 64-bit register first.
796 StringRef Reg64 = RegName;
797 if (Reg64.back() == 'd' || Reg64.back() == 'w' || Reg64.back() == 'b') {
798 Reg64 = Reg64.substr(Start: 0, N: Reg64.size() - 1);
799 }
800 if (getTargetOpts().FeatureMap.lookup(Key: ("reserve-" + Reg64).str())) {
801 switch (RegName.back()) {
802 case 'd':
803 HasSizeMismatch = RegSize != 32;
804 break;
805 case 'w':
806 HasSizeMismatch = RegSize != 16;
807 break;
808 case 'b':
809 HasSizeMismatch = RegSize != 8;
810 break;
811 default:
812 HasSizeMismatch = RegSize != 64;
813 }
814 return true;
815 }
816
817 // Check if the register is a 32-bit register the backend can handle.
818 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
819 HasSizeMismatch);
820 }
821 void setMaxAtomicWidth() override {
822 if (hasFeature(Feature: "cx16"))
823 MaxAtomicInlineWidth = 128;
824 }
825
826 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
827
828 bool hasBitIntType() const override { return true; }
829 size_t getMaxBitIntWidth() const override {
830 return llvm::IntegerType::MAX_INT_BITS;
831 }
832
833 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts,
834 const TargetInfo *Aux) override {
835 TargetInfo::adjust(Diags, Opts, Aux);
836 IsOpenCL = Opts.OpenCL;
837 }
838
839private:
840 bool IsOpenCL = false;
841};
842
843// x86-64 UEFI target
844class LLVM_LIBRARY_VISIBILITY UEFIX86_64TargetInfo
845 : public UEFITargetInfo<X86_64TargetInfo> {
846public:
847 UEFIX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
848 : UEFITargetInfo<X86_64TargetInfo>(Triple, Opts) {
849 // The UEFI spec does not mandate specific C++ ABI, integer widths, or
850 // alignment. We are setting these defaults to match the Windows target as
851 // it is the only way to build EFI applications with Clang/LLVM today. We
852 // intend to offer flexibility by supporting choices that are not default in
853 // Windows target in the future.
854 this->TheCXXABI.set(TargetCXXABI::Microsoft);
855 LongWidth = LongAlign = 32;
856 DoubleAlign = LongLongAlign = 64;
857 LongDoubleWidth = LongDoubleAlign = 64;
858 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
859 IntMaxType = SignedLongLong;
860 Int64Type = SignedLongLong;
861 SizeType = UnsignedLongLong;
862 PtrDiffType = SignedLongLong;
863 IntPtrType = SignedLongLong;
864 WCharType = UnsignedShort;
865 WIntType = UnsignedShort;
866 this->resetDataLayout();
867 }
868
869 BuiltinVaListKind getBuiltinVaListKind() const override {
870 return TargetInfo::CharPtrBuiltinVaList;
871 }
872
873 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
874 switch (CC) {
875 case CC_C:
876 case CC_Win64:
877 case CC_X86_64SysV:
878 return CCCR_OK;
879 default:
880 return CCCR_Warning;
881 }
882 }
883
884 TargetInfo::CallingConvKind
885 getCallingConvKind(bool ClangABICompat4) const override {
886 return CCK_MicrosoftWin64;
887 }
888};
889
890// x86-64 Windows target
891class LLVM_LIBRARY_VISIBILITY WindowsX86_64TargetInfo
892 : public WindowsTargetInfo<X86_64TargetInfo> {
893public:
894 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
895 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
896 LongWidth = LongAlign = 32;
897 DoubleAlign = LongLongAlign = 64;
898 IntMaxType = SignedLongLong;
899 Int64Type = SignedLongLong;
900 SizeType = UnsignedLongLong;
901 PtrDiffType = SignedLongLong;
902 IntPtrType = SignedLongLong;
903 }
904
905 BuiltinVaListKind getBuiltinVaListKind() const override {
906 return TargetInfo::CharPtrBuiltinVaList;
907 }
908
909 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
910 switch (CC) {
911 case CC_X86StdCall:
912 case CC_X86ThisCall:
913 case CC_X86FastCall:
914 return CCCR_Ignore;
915 case CC_C:
916 case CC_X86VectorCall:
917 case CC_IntelOclBicc:
918 case CC_PreserveMost:
919 case CC_PreserveAll:
920 case CC_PreserveNone:
921 case CC_X86_64SysV:
922 case CC_Swift:
923 case CC_SwiftAsync:
924 case CC_X86RegCall:
925 case CC_DeviceKernel:
926 return CCCR_OK;
927 default:
928 return CCCR_Warning;
929 }
930 }
931};
932
933// x86-64 Windows Visual Studio target
934class LLVM_LIBRARY_VISIBILITY MicrosoftX86_64TargetInfo
935 : public WindowsX86_64TargetInfo {
936public:
937 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
938 const TargetOptions &Opts)
939 : WindowsX86_64TargetInfo(Triple, Opts) {
940 LongDoubleWidth = LongDoubleAlign = 64;
941 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
942 LargeArrayMinWidth = 0;
943 LargeArrayAlign = 0;
944 }
945
946 void getTargetDefines(const LangOptions &Opts,
947 MacroBuilder &Builder) const override {
948 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
949 Builder.defineMacro(Name: "_M_X64", Value: "100");
950 Builder.defineMacro(Name: "_M_AMD64", Value: "100");
951 }
952
953 TargetInfo::CallingConvKind
954 getCallingConvKind(bool ClangABICompat4) const override {
955 return CCK_MicrosoftWin64;
956 }
957
958 unsigned getMinGlobalAlign(uint64_t TypeSize,
959 bool HasNonWeakDef) const override;
960
961 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts,
962 const TargetInfo *Aux) override;
963
964private:
965 // Whether to apply the MSVC size-based global-alignment scheme. Disabled by
966 // -fclang-abi-compat<=22 to restore prior x86_64-windows-msvc behavior.
967 bool UseMSVCCompatGlobalAlign = true;
968};
969
970// x86-64 MinGW target
971class LLVM_LIBRARY_VISIBILITY MinGWX86_64TargetInfo
972 : public WindowsX86_64TargetInfo {
973public:
974 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
975 : WindowsX86_64TargetInfo(Triple, Opts) {
976 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
977 // with x86 FP ops. Weird.
978 LongDoubleWidth = LongDoubleAlign = 128;
979 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
980 HasFloat128 = true;
981 }
982};
983
984// x86-64 Cygwin target
985class LLVM_LIBRARY_VISIBILITY CygwinX86_64TargetInfo : public X86_64TargetInfo {
986public:
987 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
988 : X86_64TargetInfo(Triple, Opts) {
989 this->WCharType = TargetInfo::UnsignedShort;
990 this->WIntType = TargetInfo::UnsignedInt;
991 this->UseMicrosoftManglingForC = true;
992 }
993
994 void getTargetDefines(const LangOptions &Opts,
995 MacroBuilder &Builder) const override {
996 X86_64TargetInfo::getTargetDefines(Opts, Builder);
997 Builder.defineMacro(Name: "__x86_64__");
998 Builder.defineMacro(Name: "__CYGWIN__");
999 Builder.defineMacro(Name: "__CYGWIN64__");
1000 addCygMingDefines(Opts, Builder);
1001 DefineStd(Builder, MacroName: "unix", Opts);
1002 if (Opts.CPlusPlus)
1003 Builder.defineMacro(Name: "_GNU_SOURCE");
1004 }
1005
1006 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
1007 switch (CC) {
1008 case CC_X86StdCall:
1009 case CC_X86ThisCall:
1010 case CC_X86FastCall:
1011 return CCCR_Ignore;
1012 case CC_C:
1013 case CC_X86VectorCall:
1014 case CC_IntelOclBicc:
1015 case CC_PreserveMost:
1016 case CC_PreserveAll:
1017 case CC_PreserveNone:
1018 case CC_X86_64SysV:
1019 case CC_Swift:
1020 case CC_SwiftAsync:
1021 case CC_X86RegCall:
1022 case CC_DeviceKernel:
1023 return CCCR_OK;
1024 default:
1025 return CCCR_Warning;
1026 }
1027 }
1028
1029 BuiltinVaListKind getBuiltinVaListKind() const override {
1030 return TargetInfo::CharPtrBuiltinVaList;
1031 }
1032};
1033
1034class LLVM_LIBRARY_VISIBILITY DarwinX86_64TargetInfo
1035 : public DarwinTargetInfo<X86_64TargetInfo> {
1036public:
1037 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1038 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
1039 Int64Type = SignedLongLong;
1040 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
1041 llvm::Triple T = llvm::Triple(Triple);
1042 if (T.isiOS())
1043 UseSignedCharForObjCBool = false;
1044 resetDataLayout();
1045 }
1046
1047 bool handleTargetFeatures(std::vector<std::string> &Features,
1048 DiagnosticsEngine &Diags) override {
1049 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
1050 Diags))
1051 return false;
1052 // We now know the features we have: we can decide how to align vectors.
1053 MaxVectorAlign =
1054 hasFeature(Feature: "avx512f") ? 512 : hasFeature(Feature: "avx") ? 256 : 128;
1055 return true;
1056 }
1057};
1058
1059class LLVM_LIBRARY_VISIBILITY OpenBSDX86_64TargetInfo
1060 : public OpenBSDTargetInfo<X86_64TargetInfo> {
1061public:
1062 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1063 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
1064 IntMaxType = SignedLongLong;
1065 Int64Type = SignedLongLong;
1066 }
1067};
1068
1069// x86_32 Android target
1070class LLVM_LIBRARY_VISIBILITY AndroidX86_32TargetInfo
1071 : public LinuxTargetInfo<X86_32TargetInfo> {
1072public:
1073 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1074 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
1075 SuitableAlign = 32;
1076 LongDoubleWidth = 64;
1077 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1078 }
1079};
1080
1081// x86_64 Android target
1082class LLVM_LIBRARY_VISIBILITY AndroidX86_64TargetInfo
1083 : public LinuxTargetInfo<X86_64TargetInfo> {
1084public:
1085 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1086 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
1087 LongDoubleFormat = &llvm::APFloat::IEEEquad();
1088 }
1089};
1090
1091// x86_32 OHOS target
1092class LLVM_LIBRARY_VISIBILITY OHOSX86_32TargetInfo
1093 : public OHOSTargetInfo<X86_32TargetInfo> {
1094public:
1095 OHOSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1096 : OHOSTargetInfo<X86_32TargetInfo>(Triple, Opts) {
1097 SuitableAlign = 32;
1098 LongDoubleWidth = 64;
1099 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1100 }
1101};
1102
1103// x86_64 OHOS target
1104class LLVM_LIBRARY_VISIBILITY OHOSX86_64TargetInfo
1105 : public OHOSTargetInfo<X86_64TargetInfo> {
1106public:
1107 OHOSX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1108 : OHOSTargetInfo<X86_64TargetInfo>(Triple, Opts) {
1109 LongDoubleFormat = &llvm::APFloat::IEEEquad();
1110 }
1111};
1112} // namespace targets
1113} // namespace clang
1114#endif // LLVM_CLANG_LIB_BASIC_TARGETS_X86_H
1115