1//===- ABIInfo.cpp --------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ABIInfo.h"
10#include "ABIInfoImpl.h"
11
12using namespace clang;
13using namespace clang::CodeGen;
14
15// Pin the vtable to this file.
16ABIInfo::~ABIInfo() = default;
17
18CGCXXABI &ABIInfo::getCXXABI() const { return CGT.getCXXABI(); }
19
20ASTContext &ABIInfo::getContext() const { return CGT.getContext(); }
21
22llvm::LLVMContext &ABIInfo::getVMContext() const {
23 return CGT.getLLVMContext();
24}
25
26const llvm::DataLayout &ABIInfo::getDataLayout() const {
27 return CGT.getDataLayout();
28}
29
30const TargetInfo &ABIInfo::getTarget() const { return CGT.getTarget(); }
31
32const CodeGenOptions &ABIInfo::getCodeGenOpts() const {
33 return CGT.getCodeGenOpts();
34}
35
36bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
37
38bool ABIInfo::isOHOSFamily() const {
39 return getTarget().getTriple().isOHOSFamily();
40}
41
42RValue ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
43 QualType Ty, AggValueSlot Slot) const {
44 return RValue::getIgnored();
45}
46
47RValue ABIInfo::EmitZOSVAArg(CodeGenFunction &CGF, Address VAListAddr,
48 QualType Ty, AggValueSlot Slot) const {
49 return RValue::getIgnored();
50}
51
52bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
53 return false;
54}
55
56bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
57 uint64_t Members) const {
58 return false;
59}
60
61bool ABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate() const {
62 // For compatibility with GCC, ignore empty bitfields in C++ mode.
63 return getContext().getLangOpts().CPlusPlus;
64}
65
66bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
67 uint64_t &Members) const {
68 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(T: Ty)) {
69 uint64_t NElements = AT->getZExtSize();
70 if (NElements == 0)
71 return false;
72 if (!isHomogeneousAggregate(Ty: AT->getElementType(), Base, Members))
73 return false;
74 Members *= NElements;
75 } else if (Ty->isConstantMatrixType() &&
76 getContext().getLangOpts().getClangABICompat() >
77 LangOptions::ClangABI::Ver23) {
78 const ConstantMatrixType *MT = Ty->castAs<ConstantMatrixType>();
79 uint64_t NElements = MT->getNumElementsFlattened();
80 if (NElements == 0)
81 return false;
82 if (!isHomogeneousAggregate(Ty: MT->getElementType(), Base, Members))
83 return false;
84 Members *= NElements;
85 } else if (const auto *RD = Ty->getAsRecordDecl()) {
86 if (RD->hasFlexibleArrayMember())
87 return false;
88
89 Members = 0;
90
91 // If this is a C++ record, check the properties of the record such as
92 // bases and ABI specific restrictions
93 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(Val: RD)) {
94 if (!getCXXABI().isPermittedToBeHomogeneousAggregate(RD: CXXRD))
95 return false;
96
97 for (const auto &I : CXXRD->bases()) {
98 // Ignore empty records.
99 if (isEmptyRecord(Context&: getContext(), T: I.getType(), AllowArrays: true))
100 continue;
101
102 uint64_t FldMembers;
103 if (!isHomogeneousAggregate(Ty: I.getType(), Base, Members&: FldMembers))
104 return false;
105
106 Members += FldMembers;
107 }
108 }
109
110 for (const auto *FD : RD->fields()) {
111 // Ignore (non-zero arrays of) empty records.
112 QualType FT = FD->getType();
113 while (const ConstantArrayType *AT =
114 getContext().getAsConstantArrayType(T: FT)) {
115 if (AT->isZeroSize())
116 return false;
117 FT = AT->getElementType();
118 }
119 if (isEmptyRecord(Context&: getContext(), T: FT, AllowArrays: true))
120 continue;
121
122 if (isZeroLengthBitfieldPermittedInHomogeneousAggregate() &&
123 FD->isZeroLengthBitField())
124 continue;
125
126 uint64_t FldMembers;
127 if (!isHomogeneousAggregate(Ty: FD->getType(), Base, Members&: FldMembers))
128 return false;
129
130 Members = (RD->isUnion() ?
131 std::max(a: Members, b: FldMembers) : Members + FldMembers);
132 }
133
134 if (!Base)
135 return false;
136
137 // Ensure there is no padding.
138 if (getContext().getTypeSize(T: Base) * Members !=
139 getContext().getTypeSize(T: Ty))
140 return false;
141 } else {
142 Members = 1;
143 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
144 Members = 2;
145 Ty = CT->getElementType();
146 }
147
148 // Most ABIs only support float, double, and some vector type widths.
149 if (!isHomogeneousAggregateBaseType(Ty))
150 return false;
151
152 // The base type must be the same for all members. Types that
153 // agree in both total size and mode (float vs. vector) are
154 // treated as being equivalent here.
155 const Type *TyPtr = Ty.getTypePtr();
156 if (!Base) {
157 Base = TyPtr;
158 // If it's a non-power-of-2 vector, its size is already a power-of-2,
159 // so make sure to widen it explicitly.
160 if (const VectorType *VT = Base->getAs<VectorType>()) {
161 QualType EltTy = VT->getElementType();
162 unsigned NumElements =
163 getContext().getTypeSize(T: VT) / getContext().getTypeSize(T: EltTy);
164 Base = getContext()
165 .getVectorType(VectorType: EltTy, NumElts: NumElements, VecKind: VT->getVectorKind())
166 .getTypePtr();
167 }
168 }
169
170 if (Base->isVectorType() != TyPtr->isVectorType() ||
171 getContext().getTypeSize(T: Base) != getContext().getTypeSize(T: TyPtr))
172 return false;
173 }
174 return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
175}
176
177bool ABIInfo::isPromotableIntegerTypeForABI(QualType Ty) const {
178 if (getContext().isPromotableIntegerType(T: Ty))
179 return true;
180
181 if (const auto *EIT = Ty->getAs<BitIntType>())
182 if (EIT->getNumBits() < getContext().getTypeSize(T: getContext().IntTy))
183 return true;
184
185 return false;
186}
187
188ABIArgInfo ABIInfo::getNaturalAlignIndirect(QualType Ty, unsigned AddrSpace,
189 bool ByVal, bool Realign,
190 llvm::Type *Padding) const {
191 return ABIArgInfo::getIndirect(Alignment: getContext().getTypeAlignInChars(T: Ty),
192 AddrSpace, ByVal, Realign, Padding);
193}
194
195ABIArgInfo ABIInfo::getNaturalAlignIndirectInReg(QualType Ty,
196 bool Realign) const {
197 return ABIArgInfo::getIndirectInReg(Alignment: getContext().getTypeAlignInChars(T: Ty),
198 /*ByVal*/ false, Realign);
199}
200
201void ABIInfo::appendAttributeMangling(TargetAttr *Attr,
202 raw_ostream &Out) const {
203 if (Attr->isDefaultVersion())
204 return;
205 appendAttributeMangling(AttrStr: Attr->getFeaturesStr(), Out);
206}
207
208void ABIInfo::appendAttributeMangling(TargetVersionAttr *Attr,
209 raw_ostream &Out) const {
210 appendAttributeMangling(AttrStr: Attr->getNamesStr(), Out);
211}
212
213void ABIInfo::appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
214 raw_ostream &Out) const {
215 appendAttributeMangling(AttrStr: Attr->getFeatureStr(Index), Out);
216 Out << '.' << Attr->getMangledIndex(Index);
217}
218
219void ABIInfo::appendAttributeMangling(StringRef AttrStr,
220 raw_ostream &Out) const {
221 if (AttrStr == "default") {
222 Out << ".default";
223 return;
224 }
225
226 Out << '.';
227 const TargetInfo &TI = CGT.getTarget();
228 ParsedTargetAttr Info = TI.parseTargetAttr(Str: AttrStr);
229
230 llvm::sort(C&: Info.Features, Comp: [&TI](StringRef LHS, StringRef RHS) {
231 // Multiversioning doesn't allow "no-${feature}", so we can
232 // only have "+" prefixes here.
233 assert(LHS.starts_with("+") && RHS.starts_with("+") &&
234 "Features should always have a prefix.");
235 return TI.getFMVPriority(Features: {LHS.substr(Start: 1)})
236 .ugt(RHS: TI.getFMVPriority(Features: {RHS.substr(Start: 1)}));
237 });
238
239 bool IsFirst = true;
240 if (!Info.CPU.empty()) {
241 IsFirst = false;
242 Out << "arch_" << Info.CPU;
243 }
244
245 for (StringRef Feat : Info.Features) {
246 if (!IsFirst)
247 Out << '_';
248 IsFirst = false;
249 Out << Feat.substr(Start: 1);
250 }
251}
252
253llvm::FixedVectorType *
254ABIInfo::getOptimalVectorMemoryType(llvm::FixedVectorType *T,
255 const LangOptions &Opt) const {
256 if (T->getNumElements() == 3 && !Opt.PreserveVec3Type)
257 return llvm::FixedVectorType::get(ElementType: T->getElementType(), NumElts: 4);
258 return T;
259}
260
261llvm::Value *ABIInfo::createCoercedLoad(Address SrcAddr, const ABIArgInfo &AI,
262 CodeGenFunction &CGF) const {
263 return nullptr;
264}
265
266void ABIInfo::createCoercedStore(llvm::Value *Val, Address DstAddr,
267 const ABIArgInfo &AI, bool DestIsVolatile,
268 CodeGenFunction &CGF) const {}
269
270ABIArgInfo ABIInfo::classifyArgForArm64ECVarArg(QualType Ty,
271 bool IsNamedArg) const {
272 llvm_unreachable("Only implemented for x86");
273}
274
275// Pin the vtable to this file.
276SwiftABIInfo::~SwiftABIInfo() = default;
277
278/// Does the given lowering require more than the given number of
279/// registers when expanded?
280///
281/// This is intended to be the basis of a reasonable basic implementation
282/// of should{Pass,Return}Indirectly.
283///
284/// For most targets, a limit of four total registers is reasonable; this
285/// limits the amount of code required in order to move around the value
286/// in case it wasn't produced immediately prior to the call by the caller
287/// (or wasn't produced in exactly the right registers) or isn't used
288/// immediately within the callee. But some targets may need to further
289/// limit the register count due to an inability to support that many
290/// return registers.
291bool SwiftABIInfo::occupiesMoreThan(ArrayRef<llvm::Type *> scalarTypes,
292 unsigned maxAllRegisters) const {
293 unsigned intCount = 0, fpCount = 0;
294 for (llvm::Type *type : scalarTypes) {
295 if (type->isPointerTy()) {
296 intCount++;
297 } else if (auto intTy = dyn_cast<llvm::IntegerType>(Val: type)) {
298 auto ptrWidth = CGT.getTarget().getPointerWidth(AddrSpace: LangAS::Default);
299 intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
300 } else {
301 assert(type->isVectorTy() || type->isFloatingPointTy());
302 fpCount++;
303 }
304 }
305
306 return (intCount + fpCount > maxAllRegisters);
307}
308
309bool SwiftABIInfo::shouldPassIndirectly(ArrayRef<llvm::Type *> ComponentTys,
310 bool AsReturnValue) const {
311 return occupiesMoreThan(scalarTypes: ComponentTys, /*total=*/maxAllRegisters: 4);
312}
313
314bool SwiftABIInfo::isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy,
315 unsigned NumElts) const {
316 // The default implementation of this assumes that the target guarantees
317 // 128-bit SIMD support but nothing more.
318 return (VectorSize.getQuantity() > 8 && VectorSize.getQuantity() <= 16);
319}
320