1//===- AMDGPU.cpp ---------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ABIInfoImpl.h"
10#include "TargetInfo.h"
11#include "llvm/ADT/StringExtras.h"
12#include "llvm/Support/AMDGPUAddrSpace.h"
13
14using namespace clang;
15using namespace clang::CodeGen;
16
17//===----------------------------------------------------------------------===//
18// AMDGPU ABI Implementation
19//===----------------------------------------------------------------------===//
20
21namespace {
22
23class AMDGPUABIInfo final : public DefaultABIInfo {
24private:
25 static const unsigned MaxNumRegsForArgsRet = 16;
26
27 uint64_t numRegsForType(QualType Ty) const;
28
29 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
30 bool isHomogeneousAggregateSmallEnough(const Type *Base,
31 uint64_t Members) const override;
32
33 // Coerce HIP scalar pointer arguments from generic pointers to global ones.
34 llvm::Type *coerceKernelArgumentType(llvm::Type *Ty, unsigned FromAS,
35 unsigned ToAS) const {
36 // Single value types.
37 auto *PtrTy = llvm::dyn_cast<llvm::PointerType>(Val: Ty);
38 if (PtrTy && PtrTy->getAddressSpace() == FromAS)
39 return llvm::PointerType::get(C&: Ty->getContext(), AddressSpace: ToAS);
40 return Ty;
41 }
42
43public:
44 explicit AMDGPUABIInfo(CodeGen::CodeGenTypes &CGT) :
45 DefaultABIInfo(CGT) {}
46
47 ABIArgInfo classifyReturnType(QualType RetTy) const;
48 ABIArgInfo classifyKernelArgumentType(QualType Ty) const;
49 ABIArgInfo classifyArgumentType(QualType Ty, bool Variadic,
50 unsigned &NumRegsLeft) const;
51
52 void computeInfo(CGFunctionInfo &FI) const override;
53 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
54 AggValueSlot Slot) const override;
55
56 llvm::FixedVectorType *
57 getOptimalVectorMemoryType(llvm::FixedVectorType *T,
58 const LangOptions &Opt) const override {
59 // We have legal instructions for 96-bit so 3x32 can be supported.
60 // FIXME: This check should be a subtarget feature as technically SI doesn't
61 // support it.
62 if (T->getNumElements() == 3 && getDataLayout().getTypeSizeInBits(Ty: T) == 96)
63 return T;
64 return DefaultABIInfo::getOptimalVectorMemoryType(T, Opt);
65 }
66};
67
68bool AMDGPUABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
69 return true;
70}
71
72bool AMDGPUABIInfo::isHomogeneousAggregateSmallEnough(
73 const Type *Base, uint64_t Members) const {
74 uint32_t NumRegs = (getContext().getTypeSize(T: Base) + 31) / 32;
75
76 // Homogeneous Aggregates may occupy at most 16 registers.
77 return Members * NumRegs <= MaxNumRegsForArgsRet;
78}
79
80/// Estimate number of registers the type will use when passed in registers.
81uint64_t AMDGPUABIInfo::numRegsForType(QualType Ty) const {
82 uint64_t NumRegs = 0;
83
84 if (const VectorType *VT = Ty->getAs<VectorType>()) {
85 // Compute from the number of elements. The reported size is based on the
86 // in-memory size, which includes the padding 4th element for 3-vectors.
87 QualType EltTy = VT->getElementType();
88 uint64_t EltSize = getContext().getTypeSize(T: EltTy);
89
90 // 16-bit element vectors should be passed as packed.
91 if (EltSize == 16)
92 return (VT->getNumElements() + 1) / 2;
93
94 uint64_t EltNumRegs = (EltSize + 31) / 32;
95 return EltNumRegs * VT->getNumElements();
96 }
97
98 if (const auto *RD = Ty->getAsRecordDecl()) {
99 assert(!RD->hasFlexibleArrayMember());
100
101 for (const FieldDecl *Field : RD->fields()) {
102 QualType FieldTy = Field->getType();
103 NumRegs += numRegsForType(Ty: FieldTy);
104 }
105
106 return NumRegs;
107 }
108
109 return (getContext().getTypeSize(T: Ty) + 31) / 32;
110}
111
112void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
113 llvm::CallingConv::ID CC = FI.getCallingConvention();
114
115 if (!getCXXABI().classifyReturnType(FI))
116 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
117
118 unsigned ArgumentIndex = 0;
119 const unsigned numFixedArguments = FI.getNumRequiredArgs();
120
121 unsigned NumRegsLeft = MaxNumRegsForArgsRet;
122 for (auto &Arg : FI.arguments()) {
123 if (CC == llvm::CallingConv::AMDGPU_KERNEL) {
124 Arg.info = classifyKernelArgumentType(Ty: Arg.type);
125 } else {
126 bool FixedArgument = ArgumentIndex++ < numFixedArguments;
127 Arg.info = classifyArgumentType(Ty: Arg.type, Variadic: !FixedArgument, NumRegsLeft);
128 }
129 }
130}
131
132RValue AMDGPUABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
133 QualType Ty, AggValueSlot Slot) const {
134 const bool IsIndirect = false;
135 const bool AllowHigherAlign = false;
136 return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy: Ty, IsIndirect,
137 ValueInfo: getContext().getTypeInfoInChars(T: Ty),
138 SlotSizeAndAlign: CharUnits::fromQuantity(Quantity: 4), AllowHigherAlign, Slot);
139}
140
141ABIArgInfo AMDGPUABIInfo::classifyReturnType(QualType RetTy) const {
142 if (isAggregateTypeForABI(T: RetTy)) {
143 // Records with non-trivial destructors/copy-constructors should not be
144 // returned by value.
145 if (!getRecordArgABI(T: RetTy, CXXABI&: getCXXABI())) {
146 // Ignore empty structs/unions.
147 if (isEmptyRecord(Context&: getContext(), T: RetTy, AllowArrays: true))
148 return ABIArgInfo::getIgnore();
149
150 // Lower single-element structs to just return a regular value.
151 if (const Type *SeltTy = isSingleElementStruct(T: RetTy, Context&: getContext()))
152 return ABIArgInfo::getDirect(T: CGT.ConvertType(T: QualType(SeltTy, 0)));
153
154 if (const auto *RD = RetTy->getAsRecordDecl();
155 RD && RD->hasFlexibleArrayMember())
156 return DefaultABIInfo::classifyReturnType(RetTy);
157
158 // Pack aggregates <= 4 bytes into single VGPR or pair.
159 uint64_t Size = getContext().getTypeSize(T: RetTy);
160 if (Size <= 16)
161 return ABIArgInfo::getDirect(T: llvm::Type::getInt16Ty(C&: getVMContext()));
162
163 if (Size <= 32)
164 return ABIArgInfo::getDirect(T: llvm::Type::getInt32Ty(C&: getVMContext()));
165
166 if (Size <= 64) {
167 llvm::Type *I32Ty = llvm::Type::getInt32Ty(C&: getVMContext());
168 return ABIArgInfo::getDirect(T: llvm::ArrayType::get(ElementType: I32Ty, NumElements: 2));
169 }
170
171 if (numRegsForType(Ty: RetTy) <= MaxNumRegsForArgsRet)
172 return ABIArgInfo::getDirect();
173 }
174 }
175
176 // Otherwise just do the default thing.
177 return DefaultABIInfo::classifyReturnType(RetTy);
178}
179
180/// For kernels all parameters are really passed in a special buffer. It doesn't
181/// make sense to pass anything byval, so everything must be direct.
182ABIArgInfo AMDGPUABIInfo::classifyKernelArgumentType(QualType Ty) const {
183 Ty = useFirstFieldIfTransparentUnion(Ty);
184
185 // TODO: Can we omit empty structs?
186
187 if (const Type *SeltTy = isSingleElementStruct(T: Ty, Context&: getContext()))
188 Ty = QualType(SeltTy, 0);
189
190 llvm::Type *OrigLTy = CGT.ConvertType(T: Ty);
191 llvm::Type *LTy = OrigLTy;
192 if (getContext().getLangOpts().HIP) {
193 LTy = coerceKernelArgumentType(
194 Ty: OrigLTy, /*FromAS=*/getContext().getTargetAddressSpace(AS: LangAS::Default),
195 /*ToAS=*/getContext().getTargetAddressSpace(AS: LangAS::cuda_device));
196 }
197
198 // FIXME: This doesn't apply the optimization of coercing pointers in structs
199 // to global address space when using byref. This would require implementing a
200 // new kind of coercion of the in-memory type when for indirect arguments.
201 if (LTy == OrigLTy && isAggregateTypeForABI(T: Ty)) {
202 return ABIArgInfo::getIndirectAliased(
203 Alignment: getContext().getTypeAlignInChars(T: Ty),
204 AddrSpace: getContext().getTargetAddressSpace(AS: LangAS::opencl_constant),
205 Realign: false /*Realign*/, Padding: nullptr /*Padding*/);
206 }
207
208 // If we set CanBeFlattened to true, CodeGen will expand the struct to its
209 // individual elements, which confuses the Clover OpenCL backend; therefore we
210 // have to set it to false here. Other args of getDirect() are just defaults.
211 return ABIArgInfo::getDirect(T: LTy, Offset: 0, Padding: nullptr, CanBeFlattened: false);
212}
213
214ABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty, bool Variadic,
215 unsigned &NumRegsLeft) const {
216 assert(NumRegsLeft <= MaxNumRegsForArgsRet && "register estimate underflow");
217
218 Ty = useFirstFieldIfTransparentUnion(Ty);
219
220 if (Variadic) {
221 return ABIArgInfo::getDirect(/*T=*/nullptr,
222 /*Offset=*/0,
223 /*Padding=*/nullptr,
224 /*CanBeFlattened=*/false,
225 /*Align=*/0);
226 }
227
228 if (isAggregateTypeForABI(T: Ty)) {
229 // Records with non-trivial destructors/copy-constructors should not be
230 // passed by value.
231 if (auto RAA = getRecordArgABI(T: Ty, CXXABI&: getCXXABI()))
232 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
233 ByVal: RAA == CGCXXABI::RAA_DirectInMemory);
234
235 // Ignore empty structs/unions.
236 if (isEmptyRecord(Context&: getContext(), T: Ty, AllowArrays: true))
237 return ABIArgInfo::getIgnore();
238
239 // Lower single-element structs to just pass a regular value. TODO: We
240 // could do reasonable-size multiple-element structs too, using getExpand(),
241 // though watch out for things like bitfields.
242 if (const Type *SeltTy = isSingleElementStruct(T: Ty, Context&: getContext()))
243 return ABIArgInfo::getDirect(T: CGT.ConvertType(T: QualType(SeltTy, 0)));
244
245 if (const auto *RD = Ty->getAsRecordDecl();
246 RD && RD->hasFlexibleArrayMember())
247 return DefaultABIInfo::classifyArgumentType(RetTy: Ty);
248
249 // Pack aggregates <= 8 bytes into single VGPR or pair.
250 uint64_t Size = getContext().getTypeSize(T: Ty);
251 if (Size <= 64) {
252 unsigned NumRegs = (Size + 31) / 32;
253 NumRegsLeft -= std::min(a: NumRegsLeft, b: NumRegs);
254
255 if (Size <= 16)
256 return ABIArgInfo::getDirect(T: llvm::Type::getInt16Ty(C&: getVMContext()));
257
258 if (Size <= 32)
259 return ABIArgInfo::getDirect(T: llvm::Type::getInt32Ty(C&: getVMContext()));
260
261 // XXX: Should this be i64 instead, and should the limit increase?
262 llvm::Type *I32Ty = llvm::Type::getInt32Ty(C&: getVMContext());
263 return ABIArgInfo::getDirect(T: llvm::ArrayType::get(ElementType: I32Ty, NumElements: 2));
264 }
265
266 if (NumRegsLeft > 0) {
267 uint64_t NumRegs = numRegsForType(Ty);
268 if (NumRegsLeft >= NumRegs) {
269 NumRegsLeft -= NumRegs;
270 return ABIArgInfo::getDirect();
271 }
272 }
273
274 // Use pass-by-reference in stead of pass-by-value for struct arguments in
275 // function ABI.
276 return ABIArgInfo::getIndirectAliased(
277 Alignment: getContext().getTypeAlignInChars(T: Ty),
278 AddrSpace: getContext().getTargetAddressSpace(AS: LangAS::opencl_private));
279 }
280
281 // Otherwise just do the default thing.
282 ABIArgInfo ArgInfo = DefaultABIInfo::classifyArgumentType(RetTy: Ty);
283 if (!ArgInfo.isIndirect()) {
284 uint64_t NumRegs = numRegsForType(Ty);
285 NumRegsLeft -= std::min(a: NumRegs, b: uint64_t{NumRegsLeft});
286 }
287
288 return ArgInfo;
289}
290
291class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
292public:
293 AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
294 : TargetCodeGenInfo(std::make_unique<AMDGPUABIInfo>(args&: CGT)) {}
295
296 bool supportsLibCall() const override { return false; }
297 void setFunctionDeclAttributes(const FunctionDecl *FD, llvm::Function *F,
298 CodeGenModule &CGM) const;
299
300 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
301 CodeGen::CodeGenModule &M) const override;
302 unsigned getDeviceKernelCallingConv() const override;
303
304 llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM,
305 llvm::PointerType *T, QualType QT) const override;
306
307 LangAS getASTAllocaAddressSpace() const override {
308 return getLangASFromTargetAS(
309 TargetAS: getABIInfo().getDataLayout().getAllocaAddrSpace());
310 }
311 LangAS getGlobalVarAddressSpace(CodeGenModule &CGM,
312 const VarDecl *D) const override;
313 StringRef getLLVMSyncScopeStr(const LangOptions &LangOpts, SyncScope Scope,
314 llvm::AtomicOrdering Ordering) const override;
315 void setTargetAtomicMetadata(CodeGenFunction &CGF,
316 llvm::Instruction &AtomicInst,
317 const AtomicExpr *Expr = nullptr) const override;
318 llvm::Value *createEnqueuedBlockKernel(CodeGenFunction &CGF,
319 llvm::Function *BlockInvokeFunc,
320 llvm::Type *BlockTy) const override;
321 bool shouldEmitStaticExternCAliases() const override;
322 bool shouldEmitDWARFBitFieldSeparators() const override;
323 void setCUDAKernelCallingConvention(const FunctionType *&FT) const override;
324};
325}
326
327static bool requiresAMDGPUProtectedVisibility(const Decl *D,
328 llvm::GlobalValue *GV) {
329 if (GV->getVisibility() != llvm::GlobalValue::HiddenVisibility)
330 return false;
331
332 return !D->hasAttr<OMPDeclareTargetDeclAttr>() &&
333 (D->hasAttr<DeviceKernelAttr>() ||
334 (isa<FunctionDecl>(Val: D) && D->hasAttr<CUDAGlobalAttr>()) ||
335 (isa<VarDecl>(Val: D) &&
336 (D->hasAttr<CUDADeviceAttr>() || D->hasAttr<CUDAConstantAttr>() ||
337 cast<VarDecl>(Val: D)->getType()->isCUDADeviceBuiltinSurfaceType() ||
338 cast<VarDecl>(Val: D)->getType()->isCUDADeviceBuiltinTextureType())));
339}
340
341void AMDGPUTargetCodeGenInfo::setFunctionDeclAttributes(
342 const FunctionDecl *FD, llvm::Function *F, CodeGenModule &M) const {
343 const auto *ReqdWGS =
344 M.getLangOpts().OpenCL ? FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr;
345 const bool IsOpenCLKernel =
346 M.getLangOpts().OpenCL && FD->hasAttr<DeviceKernelAttr>();
347 const bool IsHIPKernel = M.getLangOpts().HIP && FD->hasAttr<CUDAGlobalAttr>();
348
349 const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
350 if (ReqdWGS || FlatWGS) {
351 M.handleAMDGPUFlatWorkGroupSizeAttr(F, A: FlatWGS, ReqdWGS);
352 } else if (IsOpenCLKernel || IsHIPKernel) {
353 // By default, restrict the maximum size to a value specified by
354 // --gpu-max-threads-per-block=n or its default value for HIP.
355 const unsigned OpenCLDefaultMaxWorkGroupSize = 256;
356 const unsigned DefaultMaxWorkGroupSize =
357 IsOpenCLKernel ? OpenCLDefaultMaxWorkGroupSize
358 : M.getLangOpts().GPUMaxThreadsPerBlock;
359 std::string AttrVal =
360 std::string("1,") + llvm::utostr(X: DefaultMaxWorkGroupSize);
361 F->addFnAttr(Kind: "amdgpu-flat-work-group-size", Val: AttrVal);
362 }
363
364 if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>())
365 M.handleAMDGPUWavesPerEUAttr(F, A: Attr);
366
367 if (const auto *Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
368 unsigned NumSGPR = Attr->getNumSGPR();
369
370 if (NumSGPR != 0)
371 F->addFnAttr(Kind: "amdgpu-num-sgpr", Val: llvm::utostr(X: NumSGPR));
372 }
373
374 if (const auto *Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
375 uint32_t NumVGPR = Attr->getNumVGPR();
376
377 if (NumVGPR != 0)
378 F->addFnAttr(Kind: "amdgpu-num-vgpr", Val: llvm::utostr(X: NumVGPR));
379 }
380
381 if (const auto *Attr = FD->getAttr<AMDGPUMaxNumWorkGroupsAttr>()) {
382 uint32_t X = Attr->getMaxNumWorkGroupsX()
383 ->EvaluateKnownConstInt(Ctx: M.getContext())
384 .getExtValue();
385 // Y and Z dimensions default to 1 if not specified
386 uint32_t Y = Attr->getMaxNumWorkGroupsY()
387 ? Attr->getMaxNumWorkGroupsY()
388 ->EvaluateKnownConstInt(Ctx: M.getContext())
389 .getExtValue()
390 : 1;
391 uint32_t Z = Attr->getMaxNumWorkGroupsZ()
392 ? Attr->getMaxNumWorkGroupsZ()
393 ->EvaluateKnownConstInt(Ctx: M.getContext())
394 .getExtValue()
395 : 1;
396
397 llvm::SmallString<32> AttrVal;
398 llvm::raw_svector_ostream OS(AttrVal);
399 OS << X << ',' << Y << ',' << Z;
400
401 F->addFnAttr(Kind: "amdgpu-max-num-workgroups", Val: AttrVal.str());
402 }
403
404 if (auto *Attr = FD->getAttr<CUDAClusterDimsAttr>()) {
405 auto GetExprVal = [&](const auto &E) {
406 return E ? E->EvaluateKnownConstInt(M.getContext()).getExtValue() : 1;
407 };
408 unsigned X = GetExprVal(Attr->getX());
409 unsigned Y = GetExprVal(Attr->getY());
410 unsigned Z = GetExprVal(Attr->getZ());
411 llvm::SmallString<32> AttrVal;
412 llvm::raw_svector_ostream OS(AttrVal);
413 OS << X << ',' << Y << ',' << Z;
414 F->addFnAttr(Kind: "amdgpu-cluster-dims", Val: AttrVal.str());
415 }
416
417 // OpenCL doesn't support cluster feature.
418 const TargetInfo &TTI = M.getContext().getTargetInfo();
419 if ((IsOpenCLKernel &&
420 TTI.hasFeatureEnabled(Features: TTI.getTargetOpts().FeatureMap, Name: "clusters")) ||
421 FD->hasAttr<CUDANoClusterAttr>())
422 F->addFnAttr(Kind: "amdgpu-cluster-dims", Val: "0,0,0");
423}
424
425void AMDGPUTargetCodeGenInfo::setTargetAttributes(
426 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
427 if (requiresAMDGPUProtectedVisibility(D, GV)) {
428 GV->setVisibility(llvm::GlobalValue::ProtectedVisibility);
429 GV->setDSOLocal(true);
430 }
431
432 if (GV->isDeclaration())
433 return;
434
435 llvm::Function *F = dyn_cast<llvm::Function>(Val: GV);
436 if (!F)
437 return;
438
439 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(Val: D);
440 if (FD)
441 setFunctionDeclAttributes(FD, F, M);
442 if (!getABIInfo().getCodeGenOpts().EmitIEEENaNCompliantInsts)
443 F->addFnAttr(Kind: "amdgpu-ieee", Val: "false");
444 if (getABIInfo().getCodeGenOpts().AMDGPUExpandWaitcntProfiling)
445 F->addFnAttr(Kind: "amdgpu-expand-waitcnt-profiling");
446}
447
448unsigned AMDGPUTargetCodeGenInfo::getDeviceKernelCallingConv() const {
449 return llvm::CallingConv::AMDGPU_KERNEL;
450}
451
452// Currently LLVM assumes null pointers always have value 0,
453// which results in incorrectly transformed IR. Therefore, instead of
454// emitting null pointers in private and local address spaces, a null
455// pointer in generic address space is emitted which is casted to a
456// pointer in local or private address space.
457llvm::Constant *AMDGPUTargetCodeGenInfo::getNullPointer(
458 const CodeGen::CodeGenModule &CGM, llvm::PointerType *PT,
459 QualType QT) const {
460 if (CGM.getContext().getTargetNullPointerValue(QT) == 0)
461 return llvm::ConstantPointerNull::get(T: PT);
462
463 auto &Ctx = CGM.getContext();
464 auto NPT = llvm::PointerType::get(
465 C&: PT->getContext(), AddressSpace: Ctx.getTargetAddressSpace(AS: LangAS::opencl_generic));
466 return llvm::ConstantExpr::getAddrSpaceCast(
467 C: llvm::ConstantPointerNull::get(T: NPT), Ty: PT);
468}
469
470LangAS
471AMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
472 const VarDecl *D) const {
473 assert(!CGM.getLangOpts().OpenCL &&
474 !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
475 "Address space agnostic languages only");
476 LangAS DefaultGlobalAS = getLangASFromTargetAS(
477 TargetAS: CGM.getContext().getTargetAddressSpace(AS: LangAS::opencl_global));
478 if (!D)
479 return DefaultGlobalAS;
480
481 LangAS AddrSpace = D->getType().getAddressSpace();
482 if (AddrSpace != LangAS::Default)
483 return AddrSpace;
484
485 // Only promote to address space 4 if VarDecl has constant initialization.
486 if (D->getType().isConstantStorage(Ctx: CGM.getContext(), ExcludeCtor: false, ExcludeDtor: false) &&
487 D->hasConstantInitialization()) {
488 if (auto ConstAS = CGM.getTarget().getConstantAddressSpace())
489 return *ConstAS;
490 }
491 return DefaultGlobalAS;
492}
493
494StringRef AMDGPUTargetCodeGenInfo::getLLVMSyncScopeStr(
495 const LangOptions &LangOpts, SyncScope Scope,
496 llvm::AtomicOrdering Ordering) const {
497
498 // OpenCL assumes by default that atomic scopes are per-address space for
499 // non-sequentially consistent operations.
500 bool IsOneAs = (Scope >= SyncScope::OpenCLWorkGroup &&
501 Scope <= SyncScope::OpenCLSubGroup &&
502 Ordering != llvm::AtomicOrdering::SequentiallyConsistent);
503
504 switch (Scope) {
505 case SyncScope::HIPSingleThread:
506 case SyncScope::SingleScope:
507 return IsOneAs ? "singlethread-one-as" : "singlethread";
508 case SyncScope::HIPWavefront:
509 case SyncScope::OpenCLSubGroup:
510 case SyncScope::WavefrontScope:
511 return IsOneAs ? "wavefront-one-as" : "wavefront";
512 case SyncScope::HIPCluster:
513 case SyncScope::ClusterScope:
514 return IsOneAs ? "cluster-one-as" : "cluster";
515 case SyncScope::HIPWorkgroup:
516 case SyncScope::OpenCLWorkGroup:
517 case SyncScope::WorkgroupScope:
518 return IsOneAs ? "workgroup-one-as" : "workgroup";
519 case SyncScope::HIPAgent:
520 case SyncScope::OpenCLDevice:
521 case SyncScope::DeviceScope:
522 return IsOneAs ? "agent-one-as" : "agent";
523 case SyncScope::SystemScope:
524 case SyncScope::HIPSystem:
525 case SyncScope::OpenCLAllSVMDevices:
526 return IsOneAs ? "one-as" : "";
527 }
528 llvm_unreachable("Unknown SyncScope enum");
529}
530
531void AMDGPUTargetCodeGenInfo::setTargetAtomicMetadata(
532 CodeGenFunction &CGF, llvm::Instruction &AtomicInst,
533 const AtomicExpr *AE) const {
534 auto *RMW = dyn_cast<llvm::AtomicRMWInst>(Val: &AtomicInst);
535 auto *CmpX = dyn_cast<llvm::AtomicCmpXchgInst>(Val: &AtomicInst);
536
537 // OpenCL and old style HIP atomics consider atomics targeting thread private
538 // memory to be undefined.
539 //
540 // TODO: This is probably undefined for atomic load/store, but there's not
541 // much direct codegen benefit to knowing this.
542 if (((RMW && RMW->getPointerAddressSpace() == llvm::AMDGPUAS::FLAT_ADDRESS) ||
543 (CmpX &&
544 CmpX->getPointerAddressSpace() == llvm::AMDGPUAS::FLAT_ADDRESS)) &&
545 AE && AE->threadPrivateMemoryAtomicsAreUndefined()) {
546 llvm::MDBuilder MDHelper(CGF.getLLVMContext());
547 llvm::MDNode *ASRange = MDHelper.createRange(
548 Lo: llvm::APInt(32, llvm::AMDGPUAS::PRIVATE_ADDRESS),
549 Hi: llvm::APInt(32, llvm::AMDGPUAS::PRIVATE_ADDRESS + 1));
550 AtomicInst.setMetadata(KindID: llvm::LLVMContext::MD_noalias_addrspace, Node: ASRange);
551 }
552
553 if (!RMW)
554 return;
555
556 AtomicOptions AO = CGF.CGM.getAtomicOpts();
557 llvm::MDNode *Empty = llvm::MDNode::get(Context&: CGF.getLLVMContext(), MDs: {});
558 if (!AO.getOption(Kind: clang::AtomicOptionKind::FineGrainedMemory))
559 RMW->setMetadata(Kind: "amdgpu.no.fine.grained.memory", Node: Empty);
560 if (!AO.getOption(Kind: clang::AtomicOptionKind::RemoteMemory))
561 RMW->setMetadata(Kind: "amdgpu.no.remote.memory", Node: Empty);
562 if (AO.getOption(Kind: clang::AtomicOptionKind::IgnoreDenormalMode) &&
563 RMW->getOperation() == llvm::AtomicRMWInst::FAdd &&
564 RMW->getType()->isFloatTy())
565 RMW->setMetadata(Kind: "amdgpu.ignore.denormal.mode", Node: Empty);
566}
567
568bool AMDGPUTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
569 return false;
570}
571
572bool AMDGPUTargetCodeGenInfo::shouldEmitDWARFBitFieldSeparators() const {
573 return true;
574}
575
576void AMDGPUTargetCodeGenInfo::setCUDAKernelCallingConvention(
577 const FunctionType *&FT) const {
578 FT = getABIInfo().getContext().adjustFunctionType(
579 Fn: FT, EInfo: FT->getExtInfo().withCallingConv(cc: CC_DeviceKernel));
580}
581
582/// Return IR struct type for rtinfo struct in rocm-device-libs used for device
583/// enqueue.
584///
585/// ptr addrspace(1) kernel_object, i32 private_segment_size,
586/// i32 group_segment_size
587
588static llvm::StructType *
589getAMDGPURuntimeHandleType(llvm::LLVMContext &C,
590 llvm::Type *KernelDescriptorPtrTy) {
591 llvm::Type *Int32 = llvm::Type::getInt32Ty(C);
592 return llvm::StructType::create(Context&: C, Elements: {KernelDescriptorPtrTy, Int32, Int32},
593 Name: "block.runtime.handle.t");
594}
595
596/// Create an OpenCL kernel for an enqueued block.
597///
598/// The type of the first argument (the block literal) is the struct type
599/// of the block literal instead of a pointer type. The first argument
600/// (block literal) is passed directly by value to the kernel. The kernel
601/// allocates the same type of struct on stack and stores the block literal
602/// to it and passes its pointer to the block invoke function. The kernel
603/// has "enqueued-block" function attribute and kernel argument metadata.
604llvm::Value *AMDGPUTargetCodeGenInfo::createEnqueuedBlockKernel(
605 CodeGenFunction &CGF, llvm::Function *Invoke, llvm::Type *BlockTy) const {
606 auto &Builder = CGF.Builder;
607 auto &C = CGF.getLLVMContext();
608
609 auto *InvokeFT = Invoke->getFunctionType();
610 llvm::SmallVector<llvm::Type *, 2> ArgTys;
611 llvm::SmallVector<llvm::Metadata *, 8> AddressQuals;
612 llvm::SmallVector<llvm::Metadata *, 8> AccessQuals;
613 llvm::SmallVector<llvm::Metadata *, 8> ArgTypeNames;
614 llvm::SmallVector<llvm::Metadata *, 8> ArgBaseTypeNames;
615 llvm::SmallVector<llvm::Metadata *, 8> ArgTypeQuals;
616 llvm::SmallVector<llvm::Metadata *, 8> ArgNames;
617
618 ArgTys.push_back(Elt: BlockTy);
619 ArgTypeNames.push_back(Elt: llvm::MDString::get(Context&: C, Str: "__block_literal"));
620 AddressQuals.push_back(Elt: llvm::ConstantAsMetadata::get(C: Builder.getInt32(C: 0)));
621 ArgBaseTypeNames.push_back(Elt: llvm::MDString::get(Context&: C, Str: "__block_literal"));
622 ArgTypeQuals.push_back(Elt: llvm::MDString::get(Context&: C, Str: ""));
623 AccessQuals.push_back(Elt: llvm::MDString::get(Context&: C, Str: "none"));
624 ArgNames.push_back(Elt: llvm::MDString::get(Context&: C, Str: "block_literal"));
625 for (unsigned I = 1, E = InvokeFT->getNumParams(); I < E; ++I) {
626 ArgTys.push_back(Elt: InvokeFT->getParamType(i: I));
627 ArgTypeNames.push_back(Elt: llvm::MDString::get(Context&: C, Str: "void*"));
628 AddressQuals.push_back(Elt: llvm::ConstantAsMetadata::get(C: Builder.getInt32(C: 3)));
629 AccessQuals.push_back(Elt: llvm::MDString::get(Context&: C, Str: "none"));
630 ArgBaseTypeNames.push_back(Elt: llvm::MDString::get(Context&: C, Str: "void*"));
631 ArgTypeQuals.push_back(Elt: llvm::MDString::get(Context&: C, Str: ""));
632 ArgNames.push_back(
633 Elt: llvm::MDString::get(Context&: C, Str: (Twine("local_arg") + Twine(I)).str()));
634 }
635
636 llvm::Module &Mod = CGF.CGM.getModule();
637 const llvm::DataLayout &DL = Mod.getDataLayout();
638
639 llvm::Twine Name = Invoke->getName() + "_kernel";
640 auto *FT = llvm::FunctionType::get(Result: llvm::Type::getVoidTy(C), Params: ArgTys, isVarArg: false);
641
642 // The kernel itself can be internal, the runtime does not directly access the
643 // kernel address (only the kernel descriptor).
644 auto *F = llvm::Function::Create(Ty: FT, Linkage: llvm::GlobalValue::InternalLinkage, N: Name,
645 M: &Mod);
646 F->setCallingConv(getDeviceKernelCallingConv());
647
648 llvm::AttrBuilder KernelAttrs(C);
649 // FIXME: The invoke isn't applying the right attributes either
650 // FIXME: This is missing setTargetAttributes
651 CGF.CGM.addDefaultFunctionDefinitionAttributes(attrs&: KernelAttrs);
652 F->addFnAttrs(Attrs: KernelAttrs);
653
654 auto IP = CGF.Builder.saveIP();
655 auto *BB = llvm::BasicBlock::Create(Context&: C, Name: "entry", Parent: F);
656 Builder.SetInsertPoint(BB);
657 const auto BlockAlign = DL.getPrefTypeAlign(Ty: BlockTy);
658 auto *BlockPtr = Builder.CreateAlloca(Ty: BlockTy, ArraySize: nullptr);
659 BlockPtr->setAlignment(BlockAlign);
660 Builder.CreateAlignedStore(Val: F->arg_begin(), Ptr: BlockPtr, Align: BlockAlign);
661 auto *Cast = Builder.CreatePointerCast(V: BlockPtr, DestTy: InvokeFT->getParamType(i: 0));
662 llvm::SmallVector<llvm::Value *, 2> Args;
663 Args.push_back(Elt: Cast);
664 for (llvm::Argument &A : llvm::drop_begin(RangeOrContainer: F->args()))
665 Args.push_back(Elt: &A);
666 llvm::CallInst *call = Builder.CreateCall(Callee: Invoke, Args);
667 call->setCallingConv(Invoke->getCallingConv());
668 Builder.CreateRetVoid();
669 Builder.restoreIP(IP);
670
671 F->setMetadata(Kind: "kernel_arg_addr_space", Node: llvm::MDNode::get(Context&: C, MDs: AddressQuals));
672 F->setMetadata(Kind: "kernel_arg_access_qual", Node: llvm::MDNode::get(Context&: C, MDs: AccessQuals));
673 F->setMetadata(Kind: "kernel_arg_type", Node: llvm::MDNode::get(Context&: C, MDs: ArgTypeNames));
674 F->setMetadata(Kind: "kernel_arg_base_type",
675 Node: llvm::MDNode::get(Context&: C, MDs: ArgBaseTypeNames));
676 F->setMetadata(Kind: "kernel_arg_type_qual", Node: llvm::MDNode::get(Context&: C, MDs: ArgTypeQuals));
677 if (CGF.CGM.getCodeGenOpts().EmitOpenCLArgMetadata)
678 F->setMetadata(Kind: "kernel_arg_name", Node: llvm::MDNode::get(Context&: C, MDs: ArgNames));
679
680 llvm::StructType *HandleTy = getAMDGPURuntimeHandleType(
681 C, KernelDescriptorPtrTy: llvm::PointerType::get(C, AddressSpace: DL.getDefaultGlobalsAddressSpace()));
682 llvm::Constant *RuntimeHandleInitializer =
683 llvm::ConstantAggregateZero::get(Ty: HandleTy);
684
685 llvm::Twine RuntimeHandleName = F->getName() + ".runtime.handle";
686
687 // The runtime needs access to the runtime handle as an external symbol. The
688 // runtime handle will need to be made external later, in
689 // AMDGPUExportOpenCLEnqueuedBlocks. The kernel itself has a hidden reference
690 // inside the runtime handle, and is not directly referenced.
691
692 // TODO: We would initialize the first field by declaring F->getName() + ".kd"
693 // to reference the kernel descriptor. The runtime wouldn't need to bother
694 // setting it. We would need to have a final symbol name though.
695 // TODO: Can we directly use an external symbol with getGlobalIdentifier?
696 auto *RuntimeHandle = new llvm::GlobalVariable(
697 Mod, HandleTy,
698 /*isConstant=*/true, llvm::GlobalValue::InternalLinkage,
699 /*Initializer=*/RuntimeHandleInitializer, RuntimeHandleName,
700 /*InsertBefore=*/nullptr, llvm::GlobalValue::NotThreadLocal,
701 DL.getDefaultGlobalsAddressSpace(),
702 /*isExternallyInitialized=*/true);
703
704 llvm::MDNode *HandleAsMD =
705 llvm::MDNode::get(Context&: C, MDs: llvm::ValueAsMetadata::get(V: RuntimeHandle));
706 F->setMetadata(KindID: llvm::LLVMContext::MD_associated, Node: HandleAsMD);
707
708 RuntimeHandle->setSection(".amdgpu.kernel.runtime.handle");
709
710 CGF.CGM.addUsedGlobal(GV: F);
711 CGF.CGM.addUsedGlobal(GV: RuntimeHandle);
712 return RuntimeHandle;
713}
714
715void CodeGenModule::handleAMDGPUFlatWorkGroupSizeAttr(
716 llvm::Function *F, const AMDGPUFlatWorkGroupSizeAttr *FlatWGS,
717 const ReqdWorkGroupSizeAttr *ReqdWGS, int32_t *MinThreadsVal,
718 int32_t *MaxThreadsVal) {
719 unsigned Min = 0;
720 unsigned Max = 0;
721 auto Eval = [&](Expr *E) {
722 return E->EvaluateKnownConstInt(Ctx: getContext()).getExtValue();
723 };
724 if (FlatWGS) {
725 Min = Eval(FlatWGS->getMin());
726 Max = Eval(FlatWGS->getMax());
727 }
728 if (ReqdWGS && Min == 0 && Max == 0)
729 Min = Max = Eval(ReqdWGS->getXDim()) * Eval(ReqdWGS->getYDim()) *
730 Eval(ReqdWGS->getZDim());
731
732 if (Min != 0) {
733 assert(Min <= Max && "Min must be less than or equal Max");
734
735 if (MinThreadsVal)
736 *MinThreadsVal = Min;
737 if (MaxThreadsVal)
738 *MaxThreadsVal = Max;
739 std::string AttrVal = llvm::utostr(X: Min) + "," + llvm::utostr(X: Max);
740 if (F)
741 F->addFnAttr(Kind: "amdgpu-flat-work-group-size", Val: AttrVal);
742 } else
743 assert(Max == 0 && "Max must be zero");
744}
745
746void CodeGenModule::handleAMDGPUWavesPerEUAttr(
747 llvm::Function *F, const AMDGPUWavesPerEUAttr *Attr) {
748 unsigned Min =
749 Attr->getMin()->EvaluateKnownConstInt(Ctx: getContext()).getExtValue();
750 unsigned Max =
751 Attr->getMax()
752 ? Attr->getMax()->EvaluateKnownConstInt(Ctx: getContext()).getExtValue()
753 : 0;
754
755 if (Min != 0) {
756 assert((Max == 0 || Min <= Max) && "Min must be less than or equal Max");
757
758 std::string AttrVal = llvm::utostr(X: Min);
759 if (Max != 0)
760 AttrVal = AttrVal + "," + llvm::utostr(X: Max);
761 F->addFnAttr(Kind: "amdgpu-waves-per-eu", Val: AttrVal);
762 } else
763 assert(Max == 0 && "Max must be zero");
764}
765
766std::unique_ptr<TargetCodeGenInfo>
767CodeGen::createAMDGPUTargetCodeGenInfo(CodeGenModule &CGM) {
768 return std::make_unique<AMDGPUTargetCodeGenInfo>(args&: CGM.getTypes());
769}
770