1//===- PPC.cpp ------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ABIInfoImpl.h"
10#include "TargetInfo.h"
11#include "clang/Basic/DiagnosticFrontend.h"
12#include "llvm/Support/CodeGen.h"
13
14using namespace clang;
15using namespace clang::CodeGen;
16
17static RValue complexTempStructure(CodeGenFunction &CGF, Address VAListAddr,
18 QualType Ty, CharUnits SlotSize,
19 CharUnits EltSize, const ComplexType *CTy) {
20 Address Addr =
21 emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy: CGF.Int8Ty, DirectSize: SlotSize * 2,
22 DirectAlign: SlotSize, SlotSize, /*AllowHigher*/ AllowHigherAlign: true);
23
24 Address RealAddr = Addr;
25 Address ImagAddr = RealAddr;
26 if (CGF.CGM.getDataLayout().isBigEndian()) {
27 RealAddr =
28 CGF.Builder.CreateConstInBoundsByteGEP(Addr: RealAddr, Offset: SlotSize - EltSize);
29 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(Addr: ImagAddr,
30 Offset: 2 * SlotSize - EltSize);
31 } else {
32 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(Addr: RealAddr, Offset: SlotSize);
33 }
34
35 llvm::Type *EltTy = CGF.ConvertTypeForMem(T: CTy->getElementType());
36 RealAddr = RealAddr.withElementType(ElemTy: EltTy);
37 ImagAddr = ImagAddr.withElementType(ElemTy: EltTy);
38 llvm::Value *Real = CGF.Builder.CreateLoad(Addr: RealAddr, Name: ".vareal");
39 llvm::Value *Imag = CGF.Builder.CreateLoad(Addr: ImagAddr, Name: ".vaimag");
40
41 return RValue::getComplex(V1: Real, V2: Imag);
42}
43
44static bool PPC_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
45 llvm::Value *Address, bool Is64Bit,
46 bool IsAIX) {
47 // This is calculated from the LLVM and GCC tables and verified
48 // against gcc output. AFAIK all PPC ABIs use the same encoding.
49
50 CodeGen::CGBuilderTy &Builder = CGF.Builder;
51
52 llvm::IntegerType *i8 = CGF.Int8Ty;
53 llvm::Value *Four8 = llvm::ConstantInt::get(Ty: i8, V: 4);
54 llvm::Value *Eight8 = llvm::ConstantInt::get(Ty: i8, V: 8);
55 llvm::Value *Sixteen8 = llvm::ConstantInt::get(Ty: i8, V: 16);
56
57 // 0-31: r0-31, the 4-byte or 8-byte general-purpose registers
58 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 0, LastIndex: 31);
59
60 // 32-63: fp0-31, the 8-byte floating-point registers
61 AssignToArrayRange(Builder, Array: Address, Value: Eight8, FirstIndex: 32, LastIndex: 63);
62
63 // 64-67 are various 4-byte or 8-byte special-purpose registers:
64 // 64: mq
65 // 65: lr
66 // 66: ctr
67 // 67: ap
68 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 64, LastIndex: 67);
69
70 // 68-76 are various 4-byte special-purpose registers:
71 // 68-75 cr0-7
72 // 76: xer
73 AssignToArrayRange(Builder, Array: Address, Value: Four8, FirstIndex: 68, LastIndex: 76);
74
75 // 77-108: v0-31, the 16-byte vector registers
76 AssignToArrayRange(Builder, Array: Address, Value: Sixteen8, FirstIndex: 77, LastIndex: 108);
77
78 // 109: vrsave
79 // 110: vscr
80 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 109, LastIndex: 110);
81
82 // AIX does not utilize the rest of the registers.
83 if (IsAIX)
84 return false;
85
86 // 111: spe_acc
87 // 112: spefscr
88 // 113: sfp
89 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 111, LastIndex: 113);
90
91 if (!Is64Bit)
92 return false;
93
94 // TODO: Need to verify if these registers are used on 64 bit AIX with Power8
95 // or above CPU.
96 // 64-bit only registers:
97 // 114: tfhar
98 // 115: tfiar
99 // 116: texasr
100 AssignToArrayRange(Builder, Array: Address, Value: Eight8, FirstIndex: 114, LastIndex: 116);
101
102 return false;
103}
104
105// AIX
106namespace {
107/// AIXABIInfo - The AIX XCOFF ABI information.
108class AIXABIInfo : public ABIInfo {
109 const bool Is64Bit;
110 const unsigned PtrByteSize;
111 CharUnits getParamTypeAlignment(QualType Ty) const;
112
113public:
114 AIXABIInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
115 : ABIInfo(CGT), Is64Bit(Is64Bit), PtrByteSize(Is64Bit ? 8 : 4) {}
116
117 bool isPromotableTypeForABI(QualType Ty) const;
118
119 ABIArgInfo classifyReturnType(QualType RetTy) const;
120 ABIArgInfo classifyArgumentType(QualType Ty) const;
121
122 void computeInfo(CGFunctionInfo &FI) const override {
123 if (!getCXXABI().classifyReturnType(FI))
124 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
125
126 for (auto &I : FI.arguments())
127 I.info = classifyArgumentType(Ty: I.type);
128 }
129
130 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
131 AggValueSlot Slot) const override;
132
133 using ABIInfo::appendAttributeMangling;
134 void appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
135 raw_ostream &Out) const override;
136 void appendAttributeMangling(StringRef AttrStr,
137 raw_ostream &Out) const override;
138};
139
140void AIXABIInfo::appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
141 raw_ostream &Out) const {
142 appendAttributeMangling(AttrStr: Attr->getFeatureStr(Index), Out);
143}
144
145void AIXABIInfo::appendAttributeMangling(StringRef AttrStr,
146 raw_ostream &Out) const {
147 if (AttrStr == "default") {
148 Out << ".default";
149 return;
150 }
151
152 const TargetInfo &TI = CGT.getTarget();
153 ParsedTargetAttr Info = TI.parseTargetAttr(Str: AttrStr);
154
155 if (!Info.CPU.empty()) {
156 assert(Info.Features.empty() && "cannot have both a CPU and a feature");
157 Out << ".cpu_" << Info.CPU;
158 return;
159 }
160
161 // Handle feature strings
162 if (Info.Features.size() == 1) {
163 StringRef Feature = Info.Features[0];
164 assert(Feature.starts_with("+") || Feature.starts_with("-"));
165
166 // replace hyphens with underscores
167 std::string MangledName(Feature.drop_front(N: 1));
168 std::replace(first: MangledName.begin(), last: MangledName.end(), old_value: '-', new_value: '_');
169
170 Out << "." << (Feature.starts_with(Prefix: "-") ? "no_" : "") << MangledName;
171 return;
172 }
173
174 llvm_unreachable("Invalid target_clones parameter");
175}
176
177class AIXTargetCodeGenInfo : public TargetCodeGenInfo {
178 const bool Is64Bit;
179
180public:
181 AIXTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
182 : TargetCodeGenInfo(std::make_unique<AIXABIInfo>(args&: CGT, args&: Is64Bit)),
183 Is64Bit(Is64Bit) {}
184 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
185 return 1; // r1 is the dedicated stack pointer
186 }
187
188 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
189 llvm::Value *Address) const override;
190
191 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
192 CodeGen::CodeGenModule &M) const override;
193};
194} // namespace
195
196// Return true if the ABI requires Ty to be passed sign- or zero-
197// extended to 32/64 bits.
198bool AIXABIInfo::isPromotableTypeForABI(QualType Ty) const {
199 // Treat an enum type as its underlying type.
200 if (const auto *ED = Ty->getAsEnumDecl())
201 Ty = ED->getIntegerType();
202
203 // Promotable integer types are required to be promoted by the ABI.
204 if (getContext().isPromotableIntegerType(T: Ty))
205 return true;
206
207 if (!Is64Bit)
208 return false;
209
210 // For 64 bit mode, in addition to the usual promotable integer types, we also
211 // need to extend all 32-bit types, since the ABI requires promotion to 64
212 // bits.
213 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
214 switch (BT->getKind()) {
215 case BuiltinType::Int:
216 case BuiltinType::UInt:
217 return true;
218 default:
219 break;
220 }
221
222 return false;
223}
224
225ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy) const {
226 if (RetTy->isAnyComplexType())
227 return ABIArgInfo::getDirect();
228
229 if (RetTy->isVectorType())
230 return ABIArgInfo::getDirect();
231
232 if (RetTy->isVoidType())
233 return ABIArgInfo::getIgnore();
234
235 if (isAggregateTypeForABI(T: RetTy))
236 return getNaturalAlignIndirect(Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace());
237
238 return (isPromotableTypeForABI(Ty: RetTy) ? ABIArgInfo::getExtend(Ty: RetTy)
239 : ABIArgInfo::getDirect());
240}
241
242ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
243 Ty = useFirstFieldIfTransparentUnion(Ty);
244
245 if (Ty->isAnyComplexType())
246 return ABIArgInfo::getDirect();
247
248 if (Ty->isVectorType())
249 return ABIArgInfo::getDirect();
250
251 if (isAggregateTypeForABI(T: Ty)) {
252 // Records with non-trivial destructors/copy-constructors should not be
253 // passed by value.
254 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(T: Ty, CXXABI&: getCXXABI()))
255 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
256 ByVal: RAA == CGCXXABI::RAA_DirectInMemory);
257
258 CharUnits CCAlign = getParamTypeAlignment(Ty);
259 CharUnits TyAlign = getContext().getTypeAlignInChars(T: Ty);
260
261 return ABIArgInfo::getIndirect(
262 Alignment: CCAlign, /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),
263 /*ByVal=*/true,
264 /*Realign=*/TyAlign > CCAlign);
265 }
266
267 return (isPromotableTypeForABI(Ty)
268 ? ABIArgInfo::getExtend(Ty, T: CGT.ConvertType(T: Ty))
269 : ABIArgInfo::getDirect());
270}
271
272CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
273 // Complex types are passed just like their elements.
274 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
275 Ty = CTy->getElementType();
276
277 if (Ty->isVectorType())
278 return CharUnits::fromQuantity(Quantity: 16);
279
280 // If the structure contains a vector type, the alignment is 16.
281 if (isRecordWithSIMDVectorType(Context&: getContext(), Ty))
282 return CharUnits::fromQuantity(Quantity: 16);
283
284 return CharUnits::fromQuantity(Quantity: PtrByteSize);
285}
286
287RValue AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
288 QualType Ty, AggValueSlot Slot) const {
289
290 auto TypeInfo = getContext().getTypeInfoInChars(T: Ty);
291 TypeInfo.Align = getParamTypeAlignment(Ty);
292
293 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: PtrByteSize);
294
295 // If we have a complex type and the base type is smaller than the register
296 // size, the ABI calls for the real and imaginary parts to be right-adjusted
297 // in separate words in 32bit mode or doublewords in 64bit mode. However,
298 // Clang expects us to produce a pointer to a structure with the two parts
299 // packed tightly. So generate loads of the real and imaginary parts relative
300 // to the va_list pointer, and store them to a temporary structure. We do the
301 // same as the PPC64ABI here.
302 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
303 CharUnits EltSize = TypeInfo.Width / 2;
304 if (EltSize < SlotSize)
305 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
306 }
307
308 return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy: Ty, /*Indirect*/ IsIndirect: false, ValueInfo: TypeInfo,
309 SlotSizeAndAlign: SlotSize, /*AllowHigher*/ AllowHigherAlign: true, Slot);
310}
311
312bool AIXTargetCodeGenInfo::initDwarfEHRegSizeTable(
313 CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const {
314 return PPC_initDwarfEHRegSizeTable(CGF, Address, Is64Bit, /*IsAIX*/ true);
315}
316
317void AIXTargetCodeGenInfo::setTargetAttributes(
318 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
319 if (!isa<llvm::GlobalVariable>(Val: GV))
320 return;
321
322 auto *GVar = cast<llvm::GlobalVariable>(Val: GV);
323 auto GVId = GV->getName();
324
325 // Is this a global variable specified by the user as toc-data?
326 bool UserSpecifiedTOC =
327 llvm::binary_search(Range: M.getCodeGenOpts().TocDataVarsUserSpecified, Value&: GVId);
328 // Assumes the same variable cannot be in both TocVarsUserSpecified and
329 // NoTocVars.
330 if (UserSpecifiedTOC ||
331 ((M.getCodeGenOpts().AllTocData) &&
332 !llvm::binary_search(Range: M.getCodeGenOpts().NoTocDataVars, Value&: GVId))) {
333 const unsigned long PointerSize =
334 GV->getParent()->getDataLayout().getPointerSizeInBits() / 8;
335 auto *VarD = dyn_cast<VarDecl>(Val: D);
336 assert(VarD && "Invalid declaration of global variable.");
337
338 ASTContext &Context = D->getASTContext();
339 unsigned Alignment = Context.toBits(CharSize: Context.getDeclAlign(D)) / 8;
340 const auto *Ty = VarD->getType().getTypePtr();
341 const RecordDecl *RDecl = Ty->getAsRecordDecl();
342
343 bool EmitDiagnostic = UserSpecifiedTOC && GV->hasExternalLinkage();
344 auto reportUnsupportedWarning = [&](bool ShouldEmitWarning, StringRef Msg) {
345 if (ShouldEmitWarning)
346 M.getDiags().Report(Loc: D->getLocation(), DiagID: diag::warn_toc_unsupported_type)
347 << GVId << Msg;
348 };
349 if (!Ty || Ty->isIncompleteType())
350 reportUnsupportedWarning(EmitDiagnostic, "of incomplete type");
351 else if (RDecl && RDecl->hasFlexibleArrayMember())
352 reportUnsupportedWarning(EmitDiagnostic,
353 "it contains a flexible array member");
354 else if (VarD->getTLSKind() != VarDecl::TLS_None)
355 reportUnsupportedWarning(EmitDiagnostic, "of thread local storage");
356 else if (PointerSize < Context.getTypeInfo(T: VarD->getType()).Width / 8)
357 reportUnsupportedWarning(EmitDiagnostic,
358 "variable is larger than a pointer");
359 else if (PointerSize < Alignment)
360 reportUnsupportedWarning(EmitDiagnostic,
361 "variable is aligned wider than a pointer");
362 else if (D->hasAttr<SectionAttr>())
363 reportUnsupportedWarning(EmitDiagnostic,
364 "variable has a section attribute");
365 else if (GV->hasExternalLinkage() ||
366 (M.getCodeGenOpts().AllTocData && !GV->hasLocalLinkage()))
367 GVar->addAttribute(Kind: "toc-data");
368 }
369}
370
371// PowerPC-32
372namespace {
373/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
374class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
375 bool IsSoftFloatABI;
376 bool IsRetSmallStructInRegABI;
377
378 CharUnits getParamTypeAlignment(QualType Ty) const;
379
380public:
381 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI,
382 bool RetSmallStructInRegABI)
383 : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),
384 IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}
385
386 ABIArgInfo classifyReturnType(QualType RetTy) const;
387
388 void computeInfo(CGFunctionInfo &FI) const override {
389 if (!getCXXABI().classifyReturnType(FI))
390 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
391 for (auto &I : FI.arguments())
392 I.info = classifyArgumentType(RetTy: I.type);
393 }
394
395 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
396 AggValueSlot Slot) const override;
397};
398
399class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
400public:
401 PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI,
402 bool RetSmallStructInRegABI)
403 : TargetCodeGenInfo(std::make_unique<PPC32_SVR4_ABIInfo>(
404 args&: CGT, args&: SoftFloatABI, args&: RetSmallStructInRegABI)) {}
405
406 static bool isStructReturnInRegABI(const llvm::Triple &Triple,
407 const CodeGenOptions &Opts);
408
409 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
410 // This is recovered from gcc output.
411 return 1; // r1 is the dedicated stack pointer
412 }
413
414 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
415 llvm::Value *Address) const override;
416};
417}
418
419CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
420 // Complex types are passed just like their elements.
421 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
422 Ty = CTy->getElementType();
423
424 if (Ty->isVectorType())
425 return CharUnits::fromQuantity(Quantity: getContext().getTypeSize(T: Ty) == 128 ? 16
426 : 4);
427
428 // For single-element float/vector structs, we consider the whole type
429 // to have the same alignment requirements as its single element.
430 const Type *AlignTy = nullptr;
431 if (const Type *EltType = isSingleElementStruct(T: Ty, Context&: getContext())) {
432 const BuiltinType *BT = EltType->getAs<BuiltinType>();
433 if ((EltType->isVectorType() && getContext().getTypeSize(T: EltType) == 128) ||
434 (BT && BT->isFloatingPoint()))
435 AlignTy = EltType;
436 }
437
438 if (AlignTy)
439 return CharUnits::fromQuantity(Quantity: AlignTy->isVectorType() ? 16 : 4);
440 return CharUnits::fromQuantity(Quantity: 4);
441}
442
443ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
444 uint64_t Size;
445
446 // -msvr4-struct-return puts small aggregates in GPR3 and GPR4.
447 if (isAggregateTypeForABI(T: RetTy) && IsRetSmallStructInRegABI &&
448 (Size = getContext().getTypeSize(T: RetTy)) <= 64) {
449 // System V ABI (1995), page 3-22, specified:
450 // > A structure or union whose size is less than or equal to 8 bytes
451 // > shall be returned in r3 and r4, as if it were first stored in the
452 // > 8-byte aligned memory area and then the low addressed word were
453 // > loaded into r3 and the high-addressed word into r4. Bits beyond
454 // > the last member of the structure or union are not defined.
455 //
456 // GCC for big-endian PPC32 inserts the pad before the first member,
457 // not "beyond the last member" of the struct. To stay compatible
458 // with GCC, we coerce the struct to an integer of the same size.
459 // LLVM will extend it and return i32 in r3, or i64 in r3:r4.
460 if (Size == 0)
461 return ABIArgInfo::getIgnore();
462 else {
463 llvm::Type *CoerceTy = llvm::Type::getIntNTy(C&: getVMContext(), N: Size);
464 return ABIArgInfo::getDirect(T: CoerceTy);
465 }
466 }
467
468 return DefaultABIInfo::classifyReturnType(RetTy);
469}
470
471// TODO: this implementation is now likely redundant with
472// DefaultABIInfo::EmitVAArg.
473RValue PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
474 QualType Ty, AggValueSlot Slot) const {
475 if (getTarget().getTriple().isOSDarwin()) {
476 auto TI = getContext().getTypeInfoInChars(T: Ty);
477 TI.Align = getParamTypeAlignment(Ty);
478
479 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: 4);
480 return emitVoidPtrVAArg(CGF, VAListAddr: VAList, ValueTy: Ty,
481 IsIndirect: classifyArgumentType(RetTy: Ty).isIndirect(), ValueInfo: TI, SlotSizeAndAlign: SlotSize,
482 /*AllowHigherAlign=*/true, Slot);
483 }
484
485 const unsigned OverflowLimit = 8;
486 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
487 // TODO: Implement this. For now ignore.
488 (void)CTy;
489 return RValue::getAggregate(addr: Address::invalid()); // FIXME?
490 }
491
492 // struct __va_list_tag {
493 // unsigned char gpr;
494 // unsigned char fpr;
495 // unsigned short reserved;
496 // void *overflow_arg_area;
497 // void *reg_save_area;
498 // };
499
500 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(T: Ty) == 64;
501 bool isInt = !Ty->isFloatingType();
502 bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(T: Ty) == 64;
503
504 // All aggregates are passed indirectly? That doesn't seem consistent
505 // with the argument-lowering code.
506 bool isIndirect = isAggregateTypeForABI(T: Ty);
507
508 CGBuilderTy &Builder = CGF.Builder;
509
510 // The calling convention either uses 1-2 GPRs or 1 FPR.
511 Address NumRegsAddr = Address::invalid();
512 if (isInt || IsSoftFloatABI) {
513 NumRegsAddr = Builder.CreateStructGEP(Addr: VAList, Index: 0, Name: "gpr");
514 } else {
515 NumRegsAddr = Builder.CreateStructGEP(Addr: VAList, Index: 1, Name: "fpr");
516 }
517
518 llvm::Value *NumRegs = Builder.CreateLoad(Addr: NumRegsAddr, Name: "numUsedRegs");
519
520 // "Align" the register count when TY is i64.
521 if (isI64 || (isF64 && IsSoftFloatABI)) {
522 NumRegs = Builder.CreateAdd(LHS: NumRegs, RHS: Builder.getInt8(C: 1));
523 NumRegs = Builder.CreateAnd(LHS: NumRegs, RHS: Builder.getInt8(C: (uint8_t) ~1U));
524 }
525
526 llvm::Value *CC =
527 Builder.CreateICmpULT(LHS: NumRegs, RHS: Builder.getInt8(C: OverflowLimit), Name: "cond");
528
529 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock(name: "using_regs");
530 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock(name: "using_overflow");
531 llvm::BasicBlock *Cont = CGF.createBasicBlock(name: "cont");
532
533 Builder.CreateCondBr(Cond: CC, True: UsingRegs, False: UsingOverflow);
534
535 llvm::Type *DirectTy = CGF.ConvertType(T: Ty), *ElementTy = DirectTy;
536 if (isIndirect)
537 DirectTy = CGF.DefaultPtrTy;
538
539 // Case 1: consume registers.
540 Address RegAddr = Address::invalid();
541 {
542 CGF.EmitBlock(BB: UsingRegs);
543
544 Address RegSaveAreaPtr = Builder.CreateStructGEP(Addr: VAList, Index: 4);
545 RegAddr = Address(Builder.CreateLoad(Addr: RegSaveAreaPtr), CGF.Int8Ty,
546 CharUnits::fromQuantity(Quantity: 8));
547 assert(RegAddr.getElementType() == CGF.Int8Ty);
548
549 // Floating-point registers start after the general-purpose registers.
550 if (!(isInt || IsSoftFloatABI)) {
551 RegAddr = Builder.CreateConstInBoundsByteGEP(Addr: RegAddr,
552 Offset: CharUnits::fromQuantity(Quantity: 32));
553 }
554
555 // Get the address of the saved value by scaling the number of
556 // registers we've used by the number of
557 CharUnits RegSize = CharUnits::fromQuantity(Quantity: (isInt || IsSoftFloatABI) ? 4 : 8);
558 llvm::Value *RegOffset =
559 Builder.CreateMul(LHS: NumRegs, RHS: Builder.getInt8(C: RegSize.getQuantity()));
560 RegAddr = Address(Builder.CreateInBoundsGEP(
561 Ty: CGF.Int8Ty, Ptr: RegAddr.emitRawPointer(CGF), IdxList: RegOffset),
562 DirectTy,
563 RegAddr.getAlignment().alignmentOfArrayElement(elementSize: RegSize));
564
565 // Increase the used-register count.
566 NumRegs =
567 Builder.CreateAdd(LHS: NumRegs,
568 RHS: Builder.getInt8(C: (isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
569 Builder.CreateStore(Val: NumRegs, Addr: NumRegsAddr);
570
571 CGF.EmitBranch(Block: Cont);
572 }
573
574 // Case 2: consume space in the overflow area.
575 Address MemAddr = Address::invalid();
576 {
577 CGF.EmitBlock(BB: UsingOverflow);
578
579 Builder.CreateStore(Val: Builder.getInt8(C: OverflowLimit), Addr: NumRegsAddr);
580
581 // Everything in the overflow area is rounded up to a size of at least 4.
582 CharUnits OverflowAreaAlign = CharUnits::fromQuantity(Quantity: 4);
583
584 CharUnits Size;
585 if (!isIndirect) {
586 auto TypeInfo = CGF.getContext().getTypeInfoInChars(T: Ty);
587 Size = TypeInfo.Width.alignTo(Align: OverflowAreaAlign);
588 } else {
589 Size = CGF.getPointerSize();
590 }
591
592 Address OverflowAreaAddr = Builder.CreateStructGEP(Addr: VAList, Index: 3);
593 Address OverflowArea =
594 Address(Builder.CreateLoad(Addr: OverflowAreaAddr, Name: "argp.cur"), CGF.Int8Ty,
595 OverflowAreaAlign);
596 // Round up address of argument to alignment
597 CharUnits Align = CGF.getContext().getTypeAlignInChars(T: Ty);
598 if (Align > OverflowAreaAlign) {
599 llvm::Value *Ptr = OverflowArea.emitRawPointer(CGF);
600 OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
601 OverflowArea.getElementType(), Align);
602 }
603
604 MemAddr = OverflowArea.withElementType(ElemTy: DirectTy);
605
606 // Increase the overflow area.
607 OverflowArea = Builder.CreateConstInBoundsByteGEP(Addr: OverflowArea, Offset: Size);
608 Builder.CreateStore(Val: OverflowArea.emitRawPointer(CGF), Addr: OverflowAreaAddr);
609 CGF.EmitBranch(Block: Cont);
610 }
611
612 CGF.EmitBlock(BB: Cont);
613
614 // Merge the cases with a phi.
615 Address Result = emitMergePHI(CGF, Addr1: RegAddr, Block1: UsingRegs, Addr2: MemAddr, Block2: UsingOverflow,
616 Name: "vaarg.addr");
617
618 // Load the pointer if the argument was passed indirectly.
619 if (isIndirect) {
620 Result = Address(Builder.CreateLoad(Addr: Result, Name: "aggr"), ElementTy,
621 getContext().getTypeAlignInChars(T: Ty));
622 }
623
624 return CGF.EmitLoadOfAnyValue(V: CGF.MakeAddrLValue(Addr: Result, T: Ty), Slot);
625}
626
627bool PPC32TargetCodeGenInfo::isStructReturnInRegABI(
628 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
629 assert(Triple.isPPC32());
630
631 switch (Opts.getStructReturnConvention()) {
632 case CodeGenOptions::SRCK_Default:
633 break;
634 case CodeGenOptions::SRCK_OnStack: // -maix-struct-return
635 return false;
636 case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return
637 return true;
638 }
639
640 if (Triple.isOSBinFormatELF() && !Triple.isOSLinux())
641 return true;
642
643 return false;
644}
645
646bool
647PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
648 llvm::Value *Address) const {
649 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ false,
650 /*IsAIX*/ false);
651}
652
653// PowerPC-64
654
655namespace {
656
657/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
658class PPC64_SVR4_ABIInfo : public ABIInfo {
659 static const unsigned GPRBits = 64;
660 PPC64_SVR4_ABIKind Kind;
661 bool IsSoftFloatABI;
662
663public:
664 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, PPC64_SVR4_ABIKind Kind,
665 bool SoftFloatABI)
666 : ABIInfo(CGT), Kind(Kind), IsSoftFloatABI(SoftFloatABI) {}
667
668 bool isPromotableTypeForABI(QualType Ty) const;
669 CharUnits getParamTypeAlignment(QualType Ty) const;
670
671 ABIArgInfo classifyReturnType(QualType RetTy) const;
672 ABIArgInfo classifyArgumentType(QualType Ty) const;
673
674 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
675 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
676 uint64_t Members) const override;
677
678 // TODO: We can add more logic to computeInfo to improve performance.
679 // Example: For aggregate arguments that fit in a register, we could
680 // use getDirectInReg (as is done below for structs containing a single
681 // floating-point value) to avoid pushing them to memory on function
682 // entry. This would require changing the logic in PPCISelLowering
683 // when lowering the parameters in the caller and args in the callee.
684 void computeInfo(CGFunctionInfo &FI) const override {
685 if (!getCXXABI().classifyReturnType(FI))
686 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
687 for (auto &I : FI.arguments()) {
688 // We rely on the default argument classification for the most part.
689 // One exception: An aggregate containing a single floating-point
690 // or vector item must be passed in a register if one is available.
691 const Type *T = isSingleElementStruct(T: I.type, Context&: getContext());
692 if (T) {
693 const BuiltinType *BT = T->getAs<BuiltinType>();
694 if ((T->isVectorType() && getContext().getTypeSize(T) == 128) ||
695 (BT && BT->isFloatingPoint())) {
696 QualType QT(T, 0);
697 I.info = ABIArgInfo::getDirectInReg(T: CGT.ConvertType(T: QT));
698 continue;
699 }
700 }
701 I.info = classifyArgumentType(Ty: I.type);
702 }
703 }
704
705 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
706 AggValueSlot Slot) const override;
707};
708
709class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
710
711public:
712 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT, PPC64_SVR4_ABIKind Kind,
713 bool SoftFloatABI)
714 : TargetCodeGenInfo(
715 std::make_unique<PPC64_SVR4_ABIInfo>(args&: CGT, args&: Kind, args&: SoftFloatABI)) {
716 SwiftInfo =
717 std::make_unique<SwiftABIInfo>(args&: CGT, /*SwiftErrorInRegister=*/args: false);
718 }
719
720 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
721 // This is recovered from gcc output.
722 return 1; // r1 is the dedicated stack pointer
723 }
724
725 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
726 llvm::Value *Address) const override;
727};
728
729class PPC64TargetCodeGenInfo : public TargetCodeGenInfo {
730public:
731 PPC64TargetCodeGenInfo(CodeGenTypes &CGT)
732 : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(args&: CGT)) {}
733
734 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
735 // This is recovered from gcc output.
736 return 1; // r1 is the dedicated stack pointer
737 }
738
739 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
740 llvm::Value *Address) const override;
741};
742}
743
744// Return true if the ABI requires Ty to be passed sign- or zero-
745// extended to 64 bits.
746bool
747PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
748 // Treat an enum type as its underlying type.
749 if (const auto *ED = Ty->getAsEnumDecl())
750 Ty = ED->getIntegerType();
751
752 // Promotable integer types are required to be promoted by the ABI.
753 if (isPromotableIntegerTypeForABI(Ty))
754 return true;
755
756 // In addition to the usual promotable integer types, we also need to
757 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
758 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
759 switch (BT->getKind()) {
760 case BuiltinType::Int:
761 case BuiltinType::UInt:
762 return true;
763 default:
764 break;
765 }
766
767 if (const auto *EIT = Ty->getAs<BitIntType>())
768 if (EIT->getNumBits() < 64)
769 return true;
770
771 return false;
772}
773
774/// isAlignedParamType - Determine whether a type requires 16-byte or
775/// higher alignment in the parameter area. Always returns at least 8.
776CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
777 // Complex types are passed just like their elements.
778 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
779 Ty = CTy->getElementType();
780
781 auto FloatUsesVector = [this](QualType Ty){
782 return Ty->isRealFloatingType() && &getContext().getFloatTypeSemantics(
783 T: Ty) == &llvm::APFloat::IEEEquad();
784 };
785
786 // Only vector types of size 16 bytes need alignment (larger types are
787 // passed via reference, smaller types are not aligned).
788 if (Ty->isVectorType()) {
789 return CharUnits::fromQuantity(Quantity: getContext().getTypeSize(T: Ty) == 128 ? 16 : 8);
790 } else if (FloatUsesVector(Ty)) {
791 // According to ABI document section 'Optional Save Areas': If extended
792 // precision floating-point values in IEEE BINARY 128 QUADRUPLE PRECISION
793 // format are supported, map them to a single quadword, quadword aligned.
794 return CharUnits::fromQuantity(Quantity: 16);
795 }
796
797 // For single-element float/vector structs, we consider the whole type
798 // to have the same alignment requirements as its single element.
799 const Type *AlignAsType = nullptr;
800 const Type *EltType = isSingleElementStruct(T: Ty, Context&: getContext());
801 if (EltType) {
802 const BuiltinType *BT = EltType->getAs<BuiltinType>();
803 if ((EltType->isVectorType() && getContext().getTypeSize(T: EltType) == 128) ||
804 (BT && BT->isFloatingPoint()))
805 AlignAsType = EltType;
806 }
807
808 // Likewise for ELFv2 homogeneous aggregates.
809 const Type *Base = nullptr;
810 uint64_t Members = 0;
811 if (!AlignAsType && Kind == PPC64_SVR4_ABIKind::ELFv2 &&
812 isAggregateTypeForABI(T: Ty) && isHomogeneousAggregate(Ty, Base, Members))
813 AlignAsType = Base;
814
815 // With special case aggregates, only vector base types need alignment.
816 if (AlignAsType) {
817 bool UsesVector = AlignAsType->isVectorType() ||
818 FloatUsesVector(QualType(AlignAsType, 0));
819 return CharUnits::fromQuantity(Quantity: UsesVector ? 16 : 8);
820 }
821
822 // Otherwise, we only need alignment for any aggregate type that
823 // has an alignment requirement of >= 16 bytes.
824 if (isAggregateTypeForABI(T: Ty) && getContext().getTypeAlign(T: Ty) >= 128) {
825 return CharUnits::fromQuantity(Quantity: 16);
826 }
827
828 return CharUnits::fromQuantity(Quantity: 8);
829}
830
831bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
832 // Homogeneous aggregates for ELFv2 must have base types of float,
833 // double, long double, or 128-bit vectors.
834 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
835 if (BT->getKind() == BuiltinType::Float ||
836 BT->getKind() == BuiltinType::Double ||
837 BT->getKind() == BuiltinType::LongDouble ||
838 BT->getKind() == BuiltinType::Ibm128 ||
839 (getContext().getTargetInfo().hasFloat128Type() &&
840 (BT->getKind() == BuiltinType::Float128))) {
841 if (IsSoftFloatABI)
842 return false;
843 return true;
844 }
845 }
846 if (const VectorType *VT = Ty->getAs<VectorType>()) {
847 if (getContext().getTypeSize(T: VT) == 128)
848 return true;
849 }
850 return false;
851}
852
853bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
854 const Type *Base, uint64_t Members) const {
855 // Vector and fp128 types require one register, other floating point types
856 // require one or two registers depending on their size.
857 uint32_t NumRegs =
858 ((getContext().getTargetInfo().hasFloat128Type() &&
859 Base->isFloat128Type()) ||
860 Base->isVectorType()) ? 1
861 : (getContext().getTypeSize(T: Base) + 63) / 64;
862
863 // Homogeneous Aggregates may occupy at most 8 registers.
864 return Members * NumRegs <= 8;
865}
866
867ABIArgInfo
868PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
869 Ty = useFirstFieldIfTransparentUnion(Ty);
870
871 if (Ty->isAnyComplexType())
872 return ABIArgInfo::getDirect();
873
874 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
875 // or via reference (larger than 16 bytes).
876 if (Ty->isVectorType()) {
877 uint64_t Size = getContext().getTypeSize(T: Ty);
878 if (Size > 128)
879 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
880 /*ByVal=*/false);
881 else if (Size < 128) {
882 llvm::Type *CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: Size);
883 return ABIArgInfo::getDirect(T: CoerceTy);
884 }
885 }
886
887 if (const auto *EIT = Ty->getAs<BitIntType>())
888 if (EIT->getNumBits() > 128)
889 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
890 /*ByVal=*/true);
891
892 if (isAggregateTypeForABI(T: Ty)) {
893 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(T: Ty, CXXABI&: getCXXABI()))
894 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
895 ByVal: RAA == CGCXXABI::RAA_DirectInMemory);
896
897 uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
898 uint64_t TyAlign = getContext().getTypeAlignInChars(T: Ty).getQuantity();
899
900 // ELFv2 homogeneous aggregates are passed as array types.
901 const Type *Base = nullptr;
902 uint64_t Members = 0;
903 if (Kind == PPC64_SVR4_ABIKind::ELFv2 &&
904 isHomogeneousAggregate(Ty, Base, Members)) {
905 llvm::Type *BaseTy = CGT.ConvertType(T: QualType(Base, 0));
906 llvm::Type *CoerceTy = llvm::ArrayType::get(ElementType: BaseTy, NumElements: Members);
907 return ABIArgInfo::getDirect(T: CoerceTy);
908 }
909
910 // If an aggregate may end up fully in registers, we do not
911 // use the ByVal method, but pass the aggregate as array.
912 // This is usually beneficial since we avoid forcing the
913 // back-end to store the argument to memory.
914 uint64_t Bits = getContext().getTypeSize(T: Ty);
915 if (Bits > 0 && Bits <= 8 * GPRBits) {
916 llvm::Type *CoerceTy;
917
918 // Types up to 8 bytes are passed as integer type (which will be
919 // properly aligned in the argument save area doubleword).
920 if (Bits <= GPRBits)
921 CoerceTy =
922 llvm::IntegerType::get(C&: getVMContext(), NumBits: llvm::alignTo(Value: Bits, Align: 8));
923 // Larger types are passed as arrays, with the base type selected
924 // according to the required alignment in the save area.
925 else {
926 uint64_t RegBits = ABIAlign * 8;
927 uint64_t NumRegs = llvm::alignTo(Value: Bits, Align: RegBits) / RegBits;
928 llvm::Type *RegTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: RegBits);
929 CoerceTy = llvm::ArrayType::get(ElementType: RegTy, NumElements: NumRegs);
930 }
931
932 return ABIArgInfo::getDirect(T: CoerceTy);
933 }
934
935 // All other aggregates are passed ByVal.
936 return ABIArgInfo::getIndirect(
937 Alignment: CharUnits::fromQuantity(Quantity: ABIAlign),
938 /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),
939 /*ByVal=*/true, /*Realign=*/TyAlign > ABIAlign);
940 }
941
942 return (isPromotableTypeForABI(Ty)
943 ? ABIArgInfo::getExtend(Ty, T: CGT.ConvertType(T: Ty))
944 : ABIArgInfo::getDirect());
945}
946
947ABIArgInfo
948PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
949 if (RetTy->isVoidType())
950 return ABIArgInfo::getIgnore();
951
952 if (RetTy->isAnyComplexType())
953 return ABIArgInfo::getDirect();
954
955 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
956 // or via reference (larger than 16 bytes).
957 if (RetTy->isVectorType()) {
958 uint64_t Size = getContext().getTypeSize(T: RetTy);
959 if (Size > 128)
960 return getNaturalAlignIndirect(Ty: RetTy,
961 AddrSpace: getDataLayout().getAllocaAddrSpace());
962 else if (Size < 128) {
963 llvm::Type *CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: Size);
964 return ABIArgInfo::getDirect(T: CoerceTy);
965 }
966 }
967
968 if (const auto *EIT = RetTy->getAs<BitIntType>())
969 if (EIT->getNumBits() > 128)
970 return getNaturalAlignIndirect(
971 Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace(), /*ByVal=*/false);
972
973 if (isAggregateTypeForABI(T: RetTy)) {
974 // ELFv2 homogeneous aggregates are returned as array types.
975 const Type *Base = nullptr;
976 uint64_t Members = 0;
977 if (Kind == PPC64_SVR4_ABIKind::ELFv2 &&
978 isHomogeneousAggregate(Ty: RetTy, Base, Members)) {
979 llvm::Type *BaseTy = CGT.ConvertType(T: QualType(Base, 0));
980 llvm::Type *CoerceTy = llvm::ArrayType::get(ElementType: BaseTy, NumElements: Members);
981 return ABIArgInfo::getDirect(T: CoerceTy);
982 }
983
984 // ELFv2 small aggregates are returned in up to two registers.
985 uint64_t Bits = getContext().getTypeSize(T: RetTy);
986 if (Kind == PPC64_SVR4_ABIKind::ELFv2 && Bits <= 2 * GPRBits) {
987 if (Bits == 0)
988 return ABIArgInfo::getIgnore();
989
990 llvm::Type *CoerceTy;
991 if (Bits > GPRBits) {
992 CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: GPRBits);
993 CoerceTy = llvm::StructType::get(elt1: CoerceTy, elts: CoerceTy);
994 } else
995 CoerceTy =
996 llvm::IntegerType::get(C&: getVMContext(), NumBits: llvm::alignTo(Value: Bits, Align: 8));
997 return ABIArgInfo::getDirect(T: CoerceTy);
998 }
999
1000 // All other aggregates are returned indirectly.
1001 return getNaturalAlignIndirect(Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace());
1002 }
1003
1004 return (isPromotableTypeForABI(Ty: RetTy) ? ABIArgInfo::getExtend(Ty: RetTy)
1005 : ABIArgInfo::getDirect());
1006}
1007
1008// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
1009RValue PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1010 QualType Ty, AggValueSlot Slot) const {
1011 auto TypeInfo = getContext().getTypeInfoInChars(T: Ty);
1012 TypeInfo.Align = getParamTypeAlignment(Ty);
1013
1014 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: 8);
1015
1016 // If we have a complex type and the base type is smaller than 8 bytes,
1017 // the ABI calls for the real and imaginary parts to be right-adjusted
1018 // in separate doublewords. However, Clang expects us to produce a
1019 // pointer to a structure with the two parts packed tightly. So generate
1020 // loads of the real and imaginary parts relative to the va_list pointer,
1021 // and store them to a temporary structure.
1022 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
1023 CharUnits EltSize = TypeInfo.Width / 2;
1024 if (EltSize < SlotSize)
1025 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
1026 }
1027
1028 // Otherwise, just use the general rule.
1029 //
1030 // The PPC64 ABI passes some arguments in integer registers, even to variadic
1031 // functions. To allow va_list to use the simple "void*" representation,
1032 // variadic calls allocate space in the argument area for the integer argument
1033 // registers, and variadic functions spill their integer argument registers to
1034 // this area in their prologues. When aggregates smaller than a register are
1035 // passed this way, they are passed in the least significant bits of the
1036 // register, which means that after spilling on big-endian targets they will
1037 // be right-aligned in their argument slot. This is uncommon; for a variety of
1038 // reasons, other big-endian targets don't end up right-aligning aggregate
1039 // types this way, and so right-alignment only applies to fundamental types.
1040 // So on PPC64, we must force the use of right-alignment even for aggregates.
1041 return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy: Ty, /*Indirect*/ IsIndirect: false, ValueInfo: TypeInfo,
1042 SlotSizeAndAlign: SlotSize, /*AllowHigher*/ AllowHigherAlign: true, Slot,
1043 /*ForceRightAdjust*/ true);
1044}
1045
1046bool
1047PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
1048 CodeGen::CodeGenFunction &CGF,
1049 llvm::Value *Address) const {
1050 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
1051 /*IsAIX*/ false);
1052}
1053
1054bool
1055PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1056 llvm::Value *Address) const {
1057 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
1058 /*IsAIX*/ false);
1059}
1060
1061std::unique_ptr<TargetCodeGenInfo>
1062CodeGen::createAIXTargetCodeGenInfo(CodeGenModule &CGM, bool Is64Bit) {
1063 return std::make_unique<AIXTargetCodeGenInfo>(args&: CGM.getTypes(), args&: Is64Bit);
1064}
1065
1066std::unique_ptr<TargetCodeGenInfo>
1067CodeGen::createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI) {
1068 bool RetSmallStructInRegABI = PPC32TargetCodeGenInfo::isStructReturnInRegABI(
1069 Triple: CGM.getTriple(), Opts: CGM.getCodeGenOpts());
1070 return std::make_unique<PPC32TargetCodeGenInfo>(args&: CGM.getTypes(), args&: SoftFloatABI,
1071 args&: RetSmallStructInRegABI);
1072}
1073
1074std::unique_ptr<TargetCodeGenInfo>
1075CodeGen::createPPC64TargetCodeGenInfo(CodeGenModule &CGM) {
1076 return std::make_unique<PPC64TargetCodeGenInfo>(args&: CGM.getTypes());
1077}
1078
1079std::unique_ptr<TargetCodeGenInfo> CodeGen::createPPC64_SVR4_TargetCodeGenInfo(
1080 CodeGenModule &CGM, PPC64_SVR4_ABIKind Kind, bool SoftFloatABI) {
1081 return std::make_unique<PPC64_SVR4_TargetCodeGenInfo>(args&: CGM.getTypes(), args&: Kind,
1082 args&: SoftFloatABI);
1083}
1084