1//===- PPC.cpp ------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ABIInfoImpl.h"
10#include "TargetInfo.h"
11#include "clang/Basic/DiagnosticFrontend.h"
12#include "llvm/Support/CodeGen.h"
13
14using namespace clang;
15using namespace clang::CodeGen;
16
17static RValue complexTempStructure(CodeGenFunction &CGF, Address VAListAddr,
18 QualType Ty, CharUnits SlotSize,
19 CharUnits EltSize, const ComplexType *CTy) {
20 Address Addr =
21 emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy: CGF.Int8Ty, DirectSize: SlotSize * 2,
22 DirectAlign: SlotSize, SlotSize, /*AllowHigher*/ AllowHigherAlign: true);
23
24 Address RealAddr = Addr;
25 Address ImagAddr = RealAddr;
26 if (CGF.CGM.getDataLayout().isBigEndian()) {
27 RealAddr =
28 CGF.Builder.CreateConstInBoundsByteGEP(Addr: RealAddr, Offset: SlotSize - EltSize);
29 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(Addr: ImagAddr,
30 Offset: 2 * SlotSize - EltSize);
31 } else {
32 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(Addr: RealAddr, Offset: SlotSize);
33 }
34
35 llvm::Type *EltTy = CGF.ConvertTypeForMem(T: CTy->getElementType());
36 RealAddr = RealAddr.withElementType(ElemTy: EltTy);
37 ImagAddr = ImagAddr.withElementType(ElemTy: EltTy);
38 llvm::Value *Real = CGF.Builder.CreateLoad(Addr: RealAddr, Name: ".vareal");
39 llvm::Value *Imag = CGF.Builder.CreateLoad(Addr: ImagAddr, Name: ".vaimag");
40
41 return RValue::getComplex(V1: Real, V2: Imag);
42}
43
44static bool PPC_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
45 llvm::Value *Address, bool Is64Bit,
46 bool IsAIX) {
47 // This is calculated from the LLVM and GCC tables and verified
48 // against gcc output. AFAIK all PPC ABIs use the same encoding.
49
50 CodeGen::CGBuilderTy &Builder = CGF.Builder;
51
52 llvm::IntegerType *i8 = CGF.Int8Ty;
53 llvm::Value *Four8 = llvm::ConstantInt::get(Ty: i8, V: 4);
54 llvm::Value *Eight8 = llvm::ConstantInt::get(Ty: i8, V: 8);
55 llvm::Value *Sixteen8 = llvm::ConstantInt::get(Ty: i8, V: 16);
56
57 // 0-31: r0-31, the 4-byte or 8-byte general-purpose registers
58 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 0, LastIndex: 31);
59
60 // 32-63: fp0-31, the 8-byte floating-point registers
61 AssignToArrayRange(Builder, Array: Address, Value: Eight8, FirstIndex: 32, LastIndex: 63);
62
63 // 64-67 are various 4-byte or 8-byte special-purpose registers:
64 // 64: mq
65 // 65: lr
66 // 66: ctr
67 // 67: ap
68 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 64, LastIndex: 67);
69
70 // 68-76 are various 4-byte special-purpose registers:
71 // 68-75 cr0-7
72 // 76: xer
73 AssignToArrayRange(Builder, Array: Address, Value: Four8, FirstIndex: 68, LastIndex: 76);
74
75 // 77-108: v0-31, the 16-byte vector registers
76 AssignToArrayRange(Builder, Array: Address, Value: Sixteen8, FirstIndex: 77, LastIndex: 108);
77
78 // 109: vrsave
79 // 110: vscr
80 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 109, LastIndex: 110);
81
82 // AIX does not utilize the rest of the registers.
83 if (IsAIX)
84 return false;
85
86 // 111: spe_acc
87 // 112: spefscr
88 // 113: sfp
89 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 111, LastIndex: 113);
90
91 if (!Is64Bit)
92 return false;
93
94 // TODO: Need to verify if these registers are used on 64 bit AIX with Power8
95 // or above CPU.
96 // 64-bit only registers:
97 // 114: tfhar
98 // 115: tfiar
99 // 116: texasr
100 AssignToArrayRange(Builder, Array: Address, Value: Eight8, FirstIndex: 114, LastIndex: 116);
101
102 return false;
103}
104
105// AIX
106namespace {
107/// AIXABIInfo - The AIX XCOFF ABI information.
108class AIXABIInfo : public ABIInfo {
109 const bool Is64Bit;
110 const unsigned PtrByteSize;
111 CharUnits getParamTypeAlignment(QualType Ty) const;
112
113public:
114 AIXABIInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
115 : ABIInfo(CGT), Is64Bit(Is64Bit), PtrByteSize(Is64Bit ? 8 : 4) {}
116
117 bool isPromotableTypeForABI(QualType Ty) const;
118
119 ABIArgInfo classifyReturnType(QualType RetTy) const;
120 ABIArgInfo classifyArgumentType(QualType Ty) const;
121
122 void computeInfo(CGFunctionInfo &FI) const override {
123 if (!getCXXABI().classifyReturnType(FI))
124 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
125
126 for (auto &I : FI.arguments())
127 I.info = classifyArgumentType(Ty: I.type);
128 }
129
130 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
131 AggValueSlot Slot) const override;
132
133 using ABIInfo::appendAttributeMangling;
134 void appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
135 raw_ostream &Out) const override;
136 void appendAttributeMangling(StringRef AttrStr,
137 raw_ostream &Out) const override;
138};
139
140void AIXABIInfo::appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
141 raw_ostream &Out) const {
142 appendAttributeMangling(AttrStr: Attr->getFeatureStr(Index), Out);
143}
144
145void AIXABIInfo::appendAttributeMangling(StringRef AttrStr,
146 raw_ostream &Out) const {
147 if (AttrStr == "default") {
148 Out << ".default";
149 return;
150 }
151
152 const TargetInfo &TI = CGT.getTarget();
153 ParsedTargetAttr Info = TI.parseTargetAttr(Str: AttrStr);
154
155 if (!Info.CPU.empty()) {
156 assert(Info.Features.empty() && "cannot have both a CPU and a feature");
157 Out << ".cpu_" << Info.CPU;
158 return;
159 }
160
161 assert(0 && "specifying target features on an FMV is unsupported on AIX");
162}
163
164class AIXTargetCodeGenInfo : public TargetCodeGenInfo {
165 const bool Is64Bit;
166
167public:
168 AIXTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
169 : TargetCodeGenInfo(std::make_unique<AIXABIInfo>(args&: CGT, args&: Is64Bit)),
170 Is64Bit(Is64Bit) {}
171 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
172 return 1; // r1 is the dedicated stack pointer
173 }
174
175 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
176 llvm::Value *Address) const override;
177
178 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
179 CodeGen::CodeGenModule &M) const override;
180};
181} // namespace
182
183// Return true if the ABI requires Ty to be passed sign- or zero-
184// extended to 32/64 bits.
185bool AIXABIInfo::isPromotableTypeForABI(QualType Ty) const {
186 // Treat an enum type as its underlying type.
187 if (const auto *ED = Ty->getAsEnumDecl())
188 Ty = ED->getIntegerType();
189
190 // Promotable integer types are required to be promoted by the ABI.
191 if (getContext().isPromotableIntegerType(T: Ty))
192 return true;
193
194 if (!Is64Bit)
195 return false;
196
197 // For 64 bit mode, in addition to the usual promotable integer types, we also
198 // need to extend all 32-bit types, since the ABI requires promotion to 64
199 // bits.
200 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
201 switch (BT->getKind()) {
202 case BuiltinType::Int:
203 case BuiltinType::UInt:
204 return true;
205 default:
206 break;
207 }
208
209 return false;
210}
211
212ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy) const {
213 if (RetTy->isAnyComplexType())
214 return ABIArgInfo::getDirect();
215
216 if (RetTy->isVectorType())
217 return ABIArgInfo::getDirect();
218
219 if (RetTy->isVoidType())
220 return ABIArgInfo::getIgnore();
221
222 if (isAggregateTypeForABI(T: RetTy))
223 return getNaturalAlignIndirect(Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace());
224
225 return (isPromotableTypeForABI(Ty: RetTy) ? ABIArgInfo::getExtend(Ty: RetTy)
226 : ABIArgInfo::getDirect());
227}
228
229ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
230 Ty = useFirstFieldIfTransparentUnion(Ty);
231
232 if (Ty->isAnyComplexType())
233 return ABIArgInfo::getDirect();
234
235 if (Ty->isVectorType())
236 return ABIArgInfo::getDirect();
237
238 if (isAggregateTypeForABI(T: Ty)) {
239 // Records with non-trivial destructors/copy-constructors should not be
240 // passed by value.
241 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(T: Ty, CXXABI&: getCXXABI()))
242 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
243 ByVal: RAA == CGCXXABI::RAA_DirectInMemory);
244
245 CharUnits CCAlign = getParamTypeAlignment(Ty);
246 CharUnits TyAlign = getContext().getTypeAlignInChars(T: Ty);
247
248 return ABIArgInfo::getIndirect(
249 Alignment: CCAlign, /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),
250 /*ByVal=*/true,
251 /*Realign=*/TyAlign > CCAlign);
252 }
253
254 return (isPromotableTypeForABI(Ty)
255 ? ABIArgInfo::getExtend(Ty, T: CGT.ConvertType(T: Ty))
256 : ABIArgInfo::getDirect());
257}
258
259CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
260 // Complex types are passed just like their elements.
261 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
262 Ty = CTy->getElementType();
263
264 if (Ty->isVectorType())
265 return CharUnits::fromQuantity(Quantity: 16);
266
267 // If the structure contains a vector type, the alignment is 16.
268 if (isRecordWithSIMDVectorType(Context&: getContext(), Ty))
269 return CharUnits::fromQuantity(Quantity: 16);
270
271 return CharUnits::fromQuantity(Quantity: PtrByteSize);
272}
273
274RValue AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
275 QualType Ty, AggValueSlot Slot) const {
276
277 auto TypeInfo = getContext().getTypeInfoInChars(T: Ty);
278 TypeInfo.Align = getParamTypeAlignment(Ty);
279
280 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: PtrByteSize);
281
282 // If we have a complex type and the base type is smaller than the register
283 // size, the ABI calls for the real and imaginary parts to be right-adjusted
284 // in separate words in 32bit mode or doublewords in 64bit mode. However,
285 // Clang expects us to produce a pointer to a structure with the two parts
286 // packed tightly. So generate loads of the real and imaginary parts relative
287 // to the va_list pointer, and store them to a temporary structure. We do the
288 // same as the PPC64ABI here.
289 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
290 CharUnits EltSize = TypeInfo.Width / 2;
291 if (EltSize < SlotSize)
292 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
293 }
294
295 return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy: Ty, /*Indirect*/ IsIndirect: false, ValueInfo: TypeInfo,
296 SlotSizeAndAlign: SlotSize, /*AllowHigher*/ AllowHigherAlign: true, Slot);
297}
298
299bool AIXTargetCodeGenInfo::initDwarfEHRegSizeTable(
300 CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const {
301 return PPC_initDwarfEHRegSizeTable(CGF, Address, Is64Bit, /*IsAIX*/ true);
302}
303
304void AIXTargetCodeGenInfo::setTargetAttributes(
305 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
306 if (!isa<llvm::GlobalVariable>(Val: GV))
307 return;
308
309 auto *GVar = cast<llvm::GlobalVariable>(Val: GV);
310 auto GVId = GV->getName();
311
312 // Is this a global variable specified by the user as toc-data?
313 bool UserSpecifiedTOC =
314 llvm::binary_search(Range: M.getCodeGenOpts().TocDataVarsUserSpecified, Value&: GVId);
315 // Assumes the same variable cannot be in both TocVarsUserSpecified and
316 // NoTocVars.
317 if (UserSpecifiedTOC ||
318 ((M.getCodeGenOpts().AllTocData) &&
319 !llvm::binary_search(Range: M.getCodeGenOpts().NoTocDataVars, Value&: GVId))) {
320 const unsigned long PointerSize =
321 GV->getParent()->getDataLayout().getPointerSizeInBits() / 8;
322 auto *VarD = dyn_cast<VarDecl>(Val: D);
323 assert(VarD && "Invalid declaration of global variable.");
324
325 ASTContext &Context = D->getASTContext();
326 unsigned Alignment = Context.toBits(CharSize: Context.getDeclAlign(D)) / 8;
327 const auto *Ty = VarD->getType().getTypePtr();
328 const RecordDecl *RDecl = Ty->getAsRecordDecl();
329
330 bool EmitDiagnostic = UserSpecifiedTOC && GV->hasExternalLinkage();
331 auto reportUnsupportedWarning = [&](bool ShouldEmitWarning, StringRef Msg) {
332 if (ShouldEmitWarning)
333 M.getDiags().Report(Loc: D->getLocation(), DiagID: diag::warn_toc_unsupported_type)
334 << GVId << Msg;
335 };
336 if (!Ty || Ty->isIncompleteType())
337 reportUnsupportedWarning(EmitDiagnostic, "of incomplete type");
338 else if (RDecl && RDecl->hasFlexibleArrayMember())
339 reportUnsupportedWarning(EmitDiagnostic,
340 "it contains a flexible array member");
341 else if (VarD->getTLSKind() != VarDecl::TLS_None)
342 reportUnsupportedWarning(EmitDiagnostic, "of thread local storage");
343 else if (PointerSize < Context.getTypeInfo(T: VarD->getType()).Width / 8)
344 reportUnsupportedWarning(EmitDiagnostic,
345 "variable is larger than a pointer");
346 else if (PointerSize < Alignment)
347 reportUnsupportedWarning(EmitDiagnostic,
348 "variable is aligned wider than a pointer");
349 else if (D->hasAttr<SectionAttr>())
350 reportUnsupportedWarning(EmitDiagnostic,
351 "variable has a section attribute");
352 else if (GV->hasExternalLinkage() ||
353 (M.getCodeGenOpts().AllTocData && !GV->hasLocalLinkage()))
354 GVar->addAttribute(Kind: "toc-data");
355 }
356}
357
358// PowerPC-32
359namespace {
360/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
361class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
362 bool IsSoftFloatABI;
363 bool IsRetSmallStructInRegABI;
364
365 CharUnits getParamTypeAlignment(QualType Ty) const;
366
367public:
368 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI,
369 bool RetSmallStructInRegABI)
370 : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),
371 IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}
372
373 ABIArgInfo classifyReturnType(QualType RetTy) const;
374
375 void computeInfo(CGFunctionInfo &FI) const override {
376 if (!getCXXABI().classifyReturnType(FI))
377 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
378 for (auto &I : FI.arguments())
379 I.info = classifyArgumentType(RetTy: I.type);
380 }
381
382 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
383 AggValueSlot Slot) const override;
384};
385
386class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
387public:
388 PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI,
389 bool RetSmallStructInRegABI)
390 : TargetCodeGenInfo(std::make_unique<PPC32_SVR4_ABIInfo>(
391 args&: CGT, args&: SoftFloatABI, args&: RetSmallStructInRegABI)) {}
392
393 static bool isStructReturnInRegABI(const llvm::Triple &Triple,
394 const CodeGenOptions &Opts);
395
396 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
397 // This is recovered from gcc output.
398 return 1; // r1 is the dedicated stack pointer
399 }
400
401 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
402 llvm::Value *Address) const override;
403};
404}
405
406CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
407 // Complex types are passed just like their elements.
408 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
409 Ty = CTy->getElementType();
410
411 if (Ty->isVectorType())
412 return CharUnits::fromQuantity(Quantity: getContext().getTypeSize(T: Ty) == 128 ? 16
413 : 4);
414
415 // For single-element float/vector structs, we consider the whole type
416 // to have the same alignment requirements as its single element.
417 const Type *AlignTy = nullptr;
418 if (const Type *EltType = isSingleElementStruct(T: Ty, Context&: getContext())) {
419 const BuiltinType *BT = EltType->getAs<BuiltinType>();
420 if ((EltType->isVectorType() && getContext().getTypeSize(T: EltType) == 128) ||
421 (BT && BT->isFloatingPoint()))
422 AlignTy = EltType;
423 }
424
425 if (AlignTy)
426 return CharUnits::fromQuantity(Quantity: AlignTy->isVectorType() ? 16 : 4);
427 return CharUnits::fromQuantity(Quantity: 4);
428}
429
430ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
431 uint64_t Size;
432
433 // -msvr4-struct-return puts small aggregates in GPR3 and GPR4.
434 if (isAggregateTypeForABI(T: RetTy) && IsRetSmallStructInRegABI &&
435 (Size = getContext().getTypeSize(T: RetTy)) <= 64) {
436 // System V ABI (1995), page 3-22, specified:
437 // > A structure or union whose size is less than or equal to 8 bytes
438 // > shall be returned in r3 and r4, as if it were first stored in the
439 // > 8-byte aligned memory area and then the low addressed word were
440 // > loaded into r3 and the high-addressed word into r4. Bits beyond
441 // > the last member of the structure or union are not defined.
442 //
443 // GCC for big-endian PPC32 inserts the pad before the first member,
444 // not "beyond the last member" of the struct. To stay compatible
445 // with GCC, we coerce the struct to an integer of the same size.
446 // LLVM will extend it and return i32 in r3, or i64 in r3:r4.
447 if (Size == 0)
448 return ABIArgInfo::getIgnore();
449 else {
450 llvm::Type *CoerceTy = llvm::Type::getIntNTy(C&: getVMContext(), N: Size);
451 return ABIArgInfo::getDirect(T: CoerceTy);
452 }
453 }
454
455 return DefaultABIInfo::classifyReturnType(RetTy);
456}
457
458// TODO: this implementation is now likely redundant with
459// DefaultABIInfo::EmitVAArg.
460RValue PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
461 QualType Ty, AggValueSlot Slot) const {
462 if (getTarget().getTriple().isOSDarwin()) {
463 auto TI = getContext().getTypeInfoInChars(T: Ty);
464 TI.Align = getParamTypeAlignment(Ty);
465
466 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: 4);
467 return emitVoidPtrVAArg(CGF, VAListAddr: VAList, ValueTy: Ty,
468 IsIndirect: classifyArgumentType(RetTy: Ty).isIndirect(), ValueInfo: TI, SlotSizeAndAlign: SlotSize,
469 /*AllowHigherAlign=*/true, Slot);
470 }
471
472 const unsigned OverflowLimit = 8;
473 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
474 // TODO: Implement this. For now ignore.
475 (void)CTy;
476 return RValue::getAggregate(addr: Address::invalid()); // FIXME?
477 }
478
479 // struct __va_list_tag {
480 // unsigned char gpr;
481 // unsigned char fpr;
482 // unsigned short reserved;
483 // void *overflow_arg_area;
484 // void *reg_save_area;
485 // };
486
487 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(T: Ty) == 64;
488 bool isInt = !Ty->isFloatingType();
489 bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(T: Ty) == 64;
490
491 // All aggregates are passed indirectly? That doesn't seem consistent
492 // with the argument-lowering code.
493 bool isIndirect = isAggregateTypeForABI(T: Ty);
494
495 CGBuilderTy &Builder = CGF.Builder;
496
497 // The calling convention either uses 1-2 GPRs or 1 FPR.
498 Address NumRegsAddr = Address::invalid();
499 if (isInt || IsSoftFloatABI) {
500 NumRegsAddr = Builder.CreateStructGEP(Addr: VAList, Index: 0, Name: "gpr");
501 } else {
502 NumRegsAddr = Builder.CreateStructGEP(Addr: VAList, Index: 1, Name: "fpr");
503 }
504
505 llvm::Value *NumRegs = Builder.CreateLoad(Addr: NumRegsAddr, Name: "numUsedRegs");
506
507 // "Align" the register count when TY is i64.
508 if (isI64 || (isF64 && IsSoftFloatABI)) {
509 NumRegs = Builder.CreateAdd(LHS: NumRegs, RHS: Builder.getInt8(C: 1));
510 NumRegs = Builder.CreateAnd(LHS: NumRegs, RHS: Builder.getInt8(C: (uint8_t) ~1U));
511 }
512
513 llvm::Value *CC =
514 Builder.CreateICmpULT(LHS: NumRegs, RHS: Builder.getInt8(C: OverflowLimit), Name: "cond");
515
516 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock(name: "using_regs");
517 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock(name: "using_overflow");
518 llvm::BasicBlock *Cont = CGF.createBasicBlock(name: "cont");
519
520 Builder.CreateCondBr(Cond: CC, True: UsingRegs, False: UsingOverflow);
521
522 llvm::Type *DirectTy = CGF.ConvertType(T: Ty), *ElementTy = DirectTy;
523 if (isIndirect)
524 DirectTy = CGF.DefaultPtrTy;
525
526 // Case 1: consume registers.
527 Address RegAddr = Address::invalid();
528 {
529 CGF.EmitBlock(BB: UsingRegs);
530
531 Address RegSaveAreaPtr = Builder.CreateStructGEP(Addr: VAList, Index: 4);
532 RegAddr = Address(Builder.CreateLoad(Addr: RegSaveAreaPtr), CGF.Int8Ty,
533 CharUnits::fromQuantity(Quantity: 8));
534 assert(RegAddr.getElementType() == CGF.Int8Ty);
535
536 // Floating-point registers start after the general-purpose registers.
537 if (!(isInt || IsSoftFloatABI)) {
538 RegAddr = Builder.CreateConstInBoundsByteGEP(Addr: RegAddr,
539 Offset: CharUnits::fromQuantity(Quantity: 32));
540 }
541
542 // Get the address of the saved value by scaling the number of
543 // registers we've used by the number of
544 CharUnits RegSize = CharUnits::fromQuantity(Quantity: (isInt || IsSoftFloatABI) ? 4 : 8);
545 llvm::Value *RegOffset =
546 Builder.CreateMul(LHS: NumRegs, RHS: Builder.getInt8(C: RegSize.getQuantity()));
547 RegAddr = Address(Builder.CreateInBoundsGEP(
548 Ty: CGF.Int8Ty, Ptr: RegAddr.emitRawPointer(CGF), IdxList: RegOffset),
549 DirectTy,
550 RegAddr.getAlignment().alignmentOfArrayElement(elementSize: RegSize));
551
552 // Increase the used-register count.
553 NumRegs =
554 Builder.CreateAdd(LHS: NumRegs,
555 RHS: Builder.getInt8(C: (isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
556 Builder.CreateStore(Val: NumRegs, Addr: NumRegsAddr);
557
558 CGF.EmitBranch(Block: Cont);
559 }
560
561 // Case 2: consume space in the overflow area.
562 Address MemAddr = Address::invalid();
563 {
564 CGF.EmitBlock(BB: UsingOverflow);
565
566 Builder.CreateStore(Val: Builder.getInt8(C: OverflowLimit), Addr: NumRegsAddr);
567
568 // Everything in the overflow area is rounded up to a size of at least 4.
569 CharUnits OverflowAreaAlign = CharUnits::fromQuantity(Quantity: 4);
570
571 CharUnits Size;
572 if (!isIndirect) {
573 auto TypeInfo = CGF.getContext().getTypeInfoInChars(T: Ty);
574 Size = TypeInfo.Width.alignTo(Align: OverflowAreaAlign);
575 } else {
576 Size = CGF.getPointerSize();
577 }
578
579 Address OverflowAreaAddr = Builder.CreateStructGEP(Addr: VAList, Index: 3);
580 Address OverflowArea =
581 Address(Builder.CreateLoad(Addr: OverflowAreaAddr, Name: "argp.cur"), CGF.Int8Ty,
582 OverflowAreaAlign);
583 // Round up address of argument to alignment
584 CharUnits Align = CGF.getContext().getTypeAlignInChars(T: Ty);
585 if (Align > OverflowAreaAlign) {
586 llvm::Value *Ptr = OverflowArea.emitRawPointer(CGF);
587 OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
588 OverflowArea.getElementType(), Align);
589 }
590
591 MemAddr = OverflowArea.withElementType(ElemTy: DirectTy);
592
593 // Increase the overflow area.
594 OverflowArea = Builder.CreateConstInBoundsByteGEP(Addr: OverflowArea, Offset: Size);
595 Builder.CreateStore(Val: OverflowArea.emitRawPointer(CGF), Addr: OverflowAreaAddr);
596 CGF.EmitBranch(Block: Cont);
597 }
598
599 CGF.EmitBlock(BB: Cont);
600
601 // Merge the cases with a phi.
602 Address Result = emitMergePHI(CGF, Addr1: RegAddr, Block1: UsingRegs, Addr2: MemAddr, Block2: UsingOverflow,
603 Name: "vaarg.addr");
604
605 // Load the pointer if the argument was passed indirectly.
606 if (isIndirect) {
607 Result = Address(Builder.CreateLoad(Addr: Result, Name: "aggr"), ElementTy,
608 getContext().getTypeAlignInChars(T: Ty));
609 }
610
611 return CGF.EmitLoadOfAnyValue(V: CGF.MakeAddrLValue(Addr: Result, T: Ty), Slot);
612}
613
614bool PPC32TargetCodeGenInfo::isStructReturnInRegABI(
615 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
616 assert(Triple.isPPC32());
617
618 switch (Opts.getStructReturnConvention()) {
619 case CodeGenOptions::SRCK_Default:
620 break;
621 case CodeGenOptions::SRCK_OnStack: // -maix-struct-return
622 return false;
623 case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return
624 return true;
625 }
626
627 if (Triple.isOSBinFormatELF() && !Triple.isOSLinux())
628 return true;
629
630 return false;
631}
632
633bool
634PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
635 llvm::Value *Address) const {
636 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ false,
637 /*IsAIX*/ false);
638}
639
640// PowerPC-64
641
642namespace {
643
644/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
645class PPC64_SVR4_ABIInfo : public ABIInfo {
646 static const unsigned GPRBits = 64;
647 PPC64_SVR4_ABIKind Kind;
648 bool IsSoftFloatABI;
649
650public:
651 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, PPC64_SVR4_ABIKind Kind,
652 bool SoftFloatABI)
653 : ABIInfo(CGT), Kind(Kind), IsSoftFloatABI(SoftFloatABI) {}
654
655 bool isPromotableTypeForABI(QualType Ty) const;
656 CharUnits getParamTypeAlignment(QualType Ty) const;
657
658 ABIArgInfo classifyReturnType(QualType RetTy) const;
659 ABIArgInfo classifyArgumentType(QualType Ty) const;
660
661 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
662 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
663 uint64_t Members) const override;
664
665 // TODO: We can add more logic to computeInfo to improve performance.
666 // Example: For aggregate arguments that fit in a register, we could
667 // use getDirectInReg (as is done below for structs containing a single
668 // floating-point value) to avoid pushing them to memory on function
669 // entry. This would require changing the logic in PPCISelLowering
670 // when lowering the parameters in the caller and args in the callee.
671 void computeInfo(CGFunctionInfo &FI) const override {
672 if (!getCXXABI().classifyReturnType(FI))
673 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
674 for (auto &I : FI.arguments()) {
675 // We rely on the default argument classification for the most part.
676 // One exception: An aggregate containing a single floating-point
677 // or vector item must be passed in a register if one is available.
678 const Type *T = isSingleElementStruct(T: I.type, Context&: getContext());
679 if (T) {
680 const BuiltinType *BT = T->getAs<BuiltinType>();
681 if ((T->isVectorType() && getContext().getTypeSize(T) == 128) ||
682 (BT && BT->isFloatingPoint())) {
683 QualType QT(T, 0);
684 I.info = ABIArgInfo::getDirectInReg(T: CGT.ConvertType(T: QT));
685 continue;
686 }
687 }
688 I.info = classifyArgumentType(Ty: I.type);
689 }
690 }
691
692 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
693 AggValueSlot Slot) const override;
694};
695
696class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
697
698public:
699 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT, PPC64_SVR4_ABIKind Kind,
700 bool SoftFloatABI)
701 : TargetCodeGenInfo(
702 std::make_unique<PPC64_SVR4_ABIInfo>(args&: CGT, args&: Kind, args&: SoftFloatABI)) {
703 SwiftInfo =
704 std::make_unique<SwiftABIInfo>(args&: CGT, /*SwiftErrorInRegister=*/args: false);
705 }
706
707 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
708 // This is recovered from gcc output.
709 return 1; // r1 is the dedicated stack pointer
710 }
711
712 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
713 llvm::Value *Address) const override;
714};
715
716class PPC64TargetCodeGenInfo : public TargetCodeGenInfo {
717public:
718 PPC64TargetCodeGenInfo(CodeGenTypes &CGT)
719 : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(args&: CGT)) {}
720
721 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
722 // This is recovered from gcc output.
723 return 1; // r1 is the dedicated stack pointer
724 }
725
726 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
727 llvm::Value *Address) const override;
728};
729}
730
731// Return true if the ABI requires Ty to be passed sign- or zero-
732// extended to 64 bits.
733bool
734PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
735 // Treat an enum type as its underlying type.
736 if (const auto *ED = Ty->getAsEnumDecl())
737 Ty = ED->getIntegerType();
738
739 // Promotable integer types are required to be promoted by the ABI.
740 if (isPromotableIntegerTypeForABI(Ty))
741 return true;
742
743 // In addition to the usual promotable integer types, we also need to
744 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
745 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
746 switch (BT->getKind()) {
747 case BuiltinType::Int:
748 case BuiltinType::UInt:
749 return true;
750 default:
751 break;
752 }
753
754 if (const auto *EIT = Ty->getAs<BitIntType>())
755 if (EIT->getNumBits() < 64)
756 return true;
757
758 return false;
759}
760
761/// isAlignedParamType - Determine whether a type requires 16-byte or
762/// higher alignment in the parameter area. Always returns at least 8.
763CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
764 // Complex types are passed just like their elements.
765 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
766 Ty = CTy->getElementType();
767
768 auto FloatUsesVector = [this](QualType Ty){
769 return Ty->isRealFloatingType() && &getContext().getFloatTypeSemantics(
770 T: Ty) == &llvm::APFloat::IEEEquad();
771 };
772
773 // Only vector types of size 16 bytes need alignment (larger types are
774 // passed via reference, smaller types are not aligned).
775 if (Ty->isVectorType()) {
776 return CharUnits::fromQuantity(Quantity: getContext().getTypeSize(T: Ty) == 128 ? 16 : 8);
777 } else if (FloatUsesVector(Ty)) {
778 // According to ABI document section 'Optional Save Areas': If extended
779 // precision floating-point values in IEEE BINARY 128 QUADRUPLE PRECISION
780 // format are supported, map them to a single quadword, quadword aligned.
781 return CharUnits::fromQuantity(Quantity: 16);
782 }
783
784 // For single-element float/vector structs, we consider the whole type
785 // to have the same alignment requirements as its single element.
786 const Type *AlignAsType = nullptr;
787 const Type *EltType = isSingleElementStruct(T: Ty, Context&: getContext());
788 if (EltType) {
789 const BuiltinType *BT = EltType->getAs<BuiltinType>();
790 if ((EltType->isVectorType() && getContext().getTypeSize(T: EltType) == 128) ||
791 (BT && BT->isFloatingPoint()))
792 AlignAsType = EltType;
793 }
794
795 // Likewise for ELFv2 homogeneous aggregates.
796 const Type *Base = nullptr;
797 uint64_t Members = 0;
798 if (!AlignAsType && Kind == PPC64_SVR4_ABIKind::ELFv2 &&
799 isAggregateTypeForABI(T: Ty) && isHomogeneousAggregate(Ty, Base, Members))
800 AlignAsType = Base;
801
802 // With special case aggregates, only vector base types need alignment.
803 if (AlignAsType) {
804 bool UsesVector = AlignAsType->isVectorType() ||
805 FloatUsesVector(QualType(AlignAsType, 0));
806 return CharUnits::fromQuantity(Quantity: UsesVector ? 16 : 8);
807 }
808
809 // Otherwise, we only need alignment for any aggregate type that
810 // has an alignment requirement of >= 16 bytes.
811 if (isAggregateTypeForABI(T: Ty) && getContext().getTypeAlign(T: Ty) >= 128) {
812 return CharUnits::fromQuantity(Quantity: 16);
813 }
814
815 return CharUnits::fromQuantity(Quantity: 8);
816}
817
818bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
819 // Homogeneous aggregates for ELFv2 must have base types of float,
820 // double, long double, or 128-bit vectors.
821 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
822 if (BT->getKind() == BuiltinType::Float ||
823 BT->getKind() == BuiltinType::Double ||
824 BT->getKind() == BuiltinType::LongDouble ||
825 BT->getKind() == BuiltinType::Ibm128 ||
826 (getContext().getTargetInfo().hasFloat128Type() &&
827 (BT->getKind() == BuiltinType::Float128))) {
828 if (IsSoftFloatABI)
829 return false;
830 return true;
831 }
832 }
833 if (const VectorType *VT = Ty->getAs<VectorType>()) {
834 if (getContext().getTypeSize(T: VT) == 128)
835 return true;
836 }
837 return false;
838}
839
840bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
841 const Type *Base, uint64_t Members) const {
842 // Vector and fp128 types require one register, other floating point types
843 // require one or two registers depending on their size.
844 uint32_t NumRegs =
845 ((getContext().getTargetInfo().hasFloat128Type() &&
846 Base->isFloat128Type()) ||
847 Base->isVectorType()) ? 1
848 : (getContext().getTypeSize(T: Base) + 63) / 64;
849
850 // Homogeneous Aggregates may occupy at most 8 registers.
851 return Members * NumRegs <= 8;
852}
853
854ABIArgInfo
855PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
856 Ty = useFirstFieldIfTransparentUnion(Ty);
857
858 if (Ty->isAnyComplexType())
859 return ABIArgInfo::getDirect();
860
861 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
862 // or via reference (larger than 16 bytes).
863 if (Ty->isVectorType()) {
864 uint64_t Size = getContext().getTypeSize(T: Ty);
865 if (Size > 128)
866 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
867 /*ByVal=*/false);
868 else if (Size < 128) {
869 llvm::Type *CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: Size);
870 return ABIArgInfo::getDirect(T: CoerceTy);
871 }
872 }
873
874 if (const auto *EIT = Ty->getAs<BitIntType>())
875 if (EIT->getNumBits() > 128)
876 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
877 /*ByVal=*/true);
878
879 if (isAggregateTypeForABI(T: Ty)) {
880 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(T: Ty, CXXABI&: getCXXABI()))
881 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
882 ByVal: RAA == CGCXXABI::RAA_DirectInMemory);
883
884 uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
885 uint64_t TyAlign = getContext().getTypeAlignInChars(T: Ty).getQuantity();
886
887 // ELFv2 homogeneous aggregates are passed as array types.
888 const Type *Base = nullptr;
889 uint64_t Members = 0;
890 if (Kind == PPC64_SVR4_ABIKind::ELFv2 &&
891 isHomogeneousAggregate(Ty, Base, Members)) {
892 llvm::Type *BaseTy = CGT.ConvertType(T: QualType(Base, 0));
893 llvm::Type *CoerceTy = llvm::ArrayType::get(ElementType: BaseTy, NumElements: Members);
894 return ABIArgInfo::getDirect(T: CoerceTy);
895 }
896
897 // If an aggregate may end up fully in registers, we do not
898 // use the ByVal method, but pass the aggregate as array.
899 // This is usually beneficial since we avoid forcing the
900 // back-end to store the argument to memory.
901 uint64_t Bits = getContext().getTypeSize(T: Ty);
902 if (Bits > 0 && Bits <= 8 * GPRBits) {
903 llvm::Type *CoerceTy;
904
905 // Types up to 8 bytes are passed as integer type (which will be
906 // properly aligned in the argument save area doubleword).
907 if (Bits <= GPRBits)
908 CoerceTy =
909 llvm::IntegerType::get(C&: getVMContext(), NumBits: llvm::alignTo(Value: Bits, Align: 8));
910 // Larger types are passed as arrays, with the base type selected
911 // according to the required alignment in the save area.
912 else {
913 uint64_t RegBits = ABIAlign * 8;
914 uint64_t NumRegs = llvm::alignTo(Value: Bits, Align: RegBits) / RegBits;
915 llvm::Type *RegTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: RegBits);
916 CoerceTy = llvm::ArrayType::get(ElementType: RegTy, NumElements: NumRegs);
917 }
918
919 return ABIArgInfo::getDirect(T: CoerceTy);
920 }
921
922 // All other aggregates are passed ByVal.
923 return ABIArgInfo::getIndirect(
924 Alignment: CharUnits::fromQuantity(Quantity: ABIAlign),
925 /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),
926 /*ByVal=*/true, /*Realign=*/TyAlign > ABIAlign);
927 }
928
929 return (isPromotableTypeForABI(Ty)
930 ? ABIArgInfo::getExtend(Ty, T: CGT.ConvertType(T: Ty))
931 : ABIArgInfo::getDirect());
932}
933
934ABIArgInfo
935PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
936 if (RetTy->isVoidType())
937 return ABIArgInfo::getIgnore();
938
939 if (RetTy->isAnyComplexType())
940 return ABIArgInfo::getDirect();
941
942 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
943 // or via reference (larger than 16 bytes).
944 if (RetTy->isVectorType()) {
945 uint64_t Size = getContext().getTypeSize(T: RetTy);
946 if (Size > 128)
947 return getNaturalAlignIndirect(Ty: RetTy,
948 AddrSpace: getDataLayout().getAllocaAddrSpace());
949 else if (Size < 128) {
950 llvm::Type *CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: Size);
951 return ABIArgInfo::getDirect(T: CoerceTy);
952 }
953 }
954
955 if (const auto *EIT = RetTy->getAs<BitIntType>())
956 if (EIT->getNumBits() > 128)
957 return getNaturalAlignIndirect(
958 Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace(), /*ByVal=*/false);
959
960 if (isAggregateTypeForABI(T: RetTy)) {
961 // ELFv2 homogeneous aggregates are returned as array types.
962 const Type *Base = nullptr;
963 uint64_t Members = 0;
964 if (Kind == PPC64_SVR4_ABIKind::ELFv2 &&
965 isHomogeneousAggregate(Ty: RetTy, Base, Members)) {
966 llvm::Type *BaseTy = CGT.ConvertType(T: QualType(Base, 0));
967 llvm::Type *CoerceTy = llvm::ArrayType::get(ElementType: BaseTy, NumElements: Members);
968 return ABIArgInfo::getDirect(T: CoerceTy);
969 }
970
971 // ELFv2 small aggregates are returned in up to two registers.
972 uint64_t Bits = getContext().getTypeSize(T: RetTy);
973 if (Kind == PPC64_SVR4_ABIKind::ELFv2 && Bits <= 2 * GPRBits) {
974 if (Bits == 0)
975 return ABIArgInfo::getIgnore();
976
977 llvm::Type *CoerceTy;
978 if (Bits > GPRBits) {
979 CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: GPRBits);
980 CoerceTy = llvm::StructType::get(elt1: CoerceTy, elts: CoerceTy);
981 } else
982 CoerceTy =
983 llvm::IntegerType::get(C&: getVMContext(), NumBits: llvm::alignTo(Value: Bits, Align: 8));
984 return ABIArgInfo::getDirect(T: CoerceTy);
985 }
986
987 // All other aggregates are returned indirectly.
988 return getNaturalAlignIndirect(Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace());
989 }
990
991 return (isPromotableTypeForABI(Ty: RetTy) ? ABIArgInfo::getExtend(Ty: RetTy)
992 : ABIArgInfo::getDirect());
993}
994
995// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
996RValue PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
997 QualType Ty, AggValueSlot Slot) const {
998 auto TypeInfo = getContext().getTypeInfoInChars(T: Ty);
999 TypeInfo.Align = getParamTypeAlignment(Ty);
1000
1001 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: 8);
1002
1003 // If we have a complex type and the base type is smaller than 8 bytes,
1004 // the ABI calls for the real and imaginary parts to be right-adjusted
1005 // in separate doublewords. However, Clang expects us to produce a
1006 // pointer to a structure with the two parts packed tightly. So generate
1007 // loads of the real and imaginary parts relative to the va_list pointer,
1008 // and store them to a temporary structure.
1009 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
1010 CharUnits EltSize = TypeInfo.Width / 2;
1011 if (EltSize < SlotSize)
1012 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
1013 }
1014
1015 // Otherwise, just use the general rule.
1016 //
1017 // The PPC64 ABI passes some arguments in integer registers, even to variadic
1018 // functions. To allow va_list to use the simple "void*" representation,
1019 // variadic calls allocate space in the argument area for the integer argument
1020 // registers, and variadic functions spill their integer argument registers to
1021 // this area in their prologues. When aggregates smaller than a register are
1022 // passed this way, they are passed in the least significant bits of the
1023 // register, which means that after spilling on big-endian targets they will
1024 // be right-aligned in their argument slot. This is uncommon; for a variety of
1025 // reasons, other big-endian targets don't end up right-aligning aggregate
1026 // types this way, and so right-alignment only applies to fundamental types.
1027 // So on PPC64, we must force the use of right-alignment even for aggregates.
1028 return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy: Ty, /*Indirect*/ IsIndirect: false, ValueInfo: TypeInfo,
1029 SlotSizeAndAlign: SlotSize, /*AllowHigher*/ AllowHigherAlign: true, Slot,
1030 /*ForceRightAdjust*/ true);
1031}
1032
1033bool
1034PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
1035 CodeGen::CodeGenFunction &CGF,
1036 llvm::Value *Address) const {
1037 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
1038 /*IsAIX*/ false);
1039}
1040
1041bool
1042PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1043 llvm::Value *Address) const {
1044 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
1045 /*IsAIX*/ false);
1046}
1047
1048std::unique_ptr<TargetCodeGenInfo>
1049CodeGen::createAIXTargetCodeGenInfo(CodeGenModule &CGM, bool Is64Bit) {
1050 return std::make_unique<AIXTargetCodeGenInfo>(args&: CGM.getTypes(), args&: Is64Bit);
1051}
1052
1053std::unique_ptr<TargetCodeGenInfo>
1054CodeGen::createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI) {
1055 bool RetSmallStructInRegABI = PPC32TargetCodeGenInfo::isStructReturnInRegABI(
1056 Triple: CGM.getTriple(), Opts: CGM.getCodeGenOpts());
1057 return std::make_unique<PPC32TargetCodeGenInfo>(args&: CGM.getTypes(), args&: SoftFloatABI,
1058 args&: RetSmallStructInRegABI);
1059}
1060
1061std::unique_ptr<TargetCodeGenInfo>
1062CodeGen::createPPC64TargetCodeGenInfo(CodeGenModule &CGM) {
1063 return std::make_unique<PPC64TargetCodeGenInfo>(args&: CGM.getTypes());
1064}
1065
1066std::unique_ptr<TargetCodeGenInfo> CodeGen::createPPC64_SVR4_TargetCodeGenInfo(
1067 CodeGenModule &CGM, PPC64_SVR4_ABIKind Kind, bool SoftFloatABI) {
1068 return std::make_unique<PPC64_SVR4_TargetCodeGenInfo>(args&: CGM.getTypes(), args&: Kind,
1069 args&: SoftFloatABI);
1070}
1071