1//===--- Mips.cpp - Tools Implementations -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "Mips.h"
10#include "clang/Driver/CommonArgs.h"
11#include "clang/Driver/Driver.h"
12#include "clang/Options/Options.h"
13#include "llvm/ADT/StringSwitch.h"
14#include "llvm/Option/ArgList.h"
15
16using namespace clang::driver;
17using namespace clang::driver::tools;
18using namespace clang;
19using namespace llvm::opt;
20
21// Get CPU and ABI names. They are not independent
22// so we have to calculate them together.
23void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
24 StringRef &CPUName, StringRef &ABIName) {
25 const char *DefMips32CPU = "mips32r2";
26 const char *DefMips64CPU = "mips64r2";
27
28 // MIPS32r6 is the default for mips(el)?-img-linux-gnu and MIPS64r6 is the
29 // default for mips64(el)?-img-linux-gnu.
30 if (Triple.getVendor() == llvm::Triple::ImaginationTechnologies &&
31 Triple.isGNUEnvironment()) {
32 DefMips32CPU = "mips32r6";
33 DefMips64CPU = "mips64r6";
34 }
35
36 if (Triple.getSubArch() == llvm::Triple::MipsSubArch_r6) {
37 DefMips32CPU = "mips32r6";
38 DefMips64CPU = "mips64r6";
39 }
40
41 // MIPS3 is the default for mips64*-unknown-openbsd.
42 if (Triple.isOSOpenBSD())
43 DefMips64CPU = "mips3";
44
45 // MIPS2 is the default for mips(el)?-unknown-freebsd.
46 // MIPS3 is the default for mips64(el)?-unknown-freebsd.
47 if (Triple.isOSFreeBSD()) {
48 DefMips32CPU = "mips2";
49 DefMips64CPU = "mips3";
50 }
51
52 if (Arg *A = Args.getLastArg(Ids: options::OPT_march_EQ, Ids: options::OPT_mcpu_EQ))
53 CPUName = A->getValue();
54
55 if (Arg *A = Args.getLastArg(Ids: options::OPT_mabi_EQ)) {
56 ABIName = A->getValue();
57 // Convert a GNU style Mips ABI name to the name
58 // accepted by LLVM Mips backend.
59 ABIName = llvm::StringSwitch<llvm::StringRef>(ABIName)
60 .Case(S: "32", Value: "o32")
61 .Case(S: "64", Value: "n64")
62 .Default(Value: ABIName);
63 }
64
65 // Setup default CPU and ABI names.
66 if (CPUName.empty() && ABIName.empty()) {
67 switch (Triple.getArch()) {
68 default:
69 llvm_unreachable("Unexpected triple arch name");
70 case llvm::Triple::mips:
71 case llvm::Triple::mipsel:
72 CPUName = DefMips32CPU;
73 break;
74 case llvm::Triple::mips64:
75 case llvm::Triple::mips64el:
76 CPUName = DefMips64CPU;
77 break;
78 }
79 }
80
81 if (ABIName.empty() && Triple.isABIN32())
82 ABIName = "n32";
83
84 if (ABIName.empty() &&
85 (Triple.getVendor() == llvm::Triple::MipsTechnologies ||
86 Triple.getVendor() == llvm::Triple::ImaginationTechnologies)) {
87 ABIName = llvm::StringSwitch<const char *>(CPUName)
88 .Case(S: "mips1", Value: "o32")
89 .Case(S: "mips2", Value: "o32")
90 .Case(S: "mips3", Value: "n64")
91 .Case(S: "mips4", Value: "n64")
92 .Case(S: "mips5", Value: "n64")
93 .Case(S: "mips32", Value: "o32")
94 .Case(S: "mips32r2", Value: "o32")
95 .Case(S: "mips32r3", Value: "o32")
96 .Case(S: "mips32r5", Value: "o32")
97 .Case(S: "mips32r6", Value: "o32")
98 .Case(S: "mips64", Value: "n64")
99 .Case(S: "mips64r2", Value: "n64")
100 .Case(S: "mips64r3", Value: "n64")
101 .Case(S: "mips64r5", Value: "n64")
102 .Case(S: "mips64r6", Value: "n64")
103 .Case(S: "octeon", Value: "n64")
104 .Case(S: "p5600", Value: "o32")
105 .Case(S: "i6400", Value: "n64")
106 .Case(S: "i6500", Value: "n64")
107 .Default(Value: "");
108 }
109
110 if (ABIName.empty()) {
111 // Deduce ABI name from the target triple.
112 ABIName = Triple.isMIPS32() ? "o32" : "n64";
113 }
114
115 if (CPUName.empty()) {
116 // Deduce CPU name from ABI name.
117 CPUName = llvm::StringSwitch<const char *>(ABIName)
118 .Case(S: "o32", Value: DefMips32CPU)
119 .Cases(CaseStrings: {"n32", "n64"}, Value: DefMips64CPU)
120 .Default(Value: "");
121 }
122
123 // FIXME: Warn on inconsistent use of -march and -mabi.
124}
125
126std::string mips::getMipsABILibSuffix(const ArgList &Args,
127 const llvm::Triple &Triple) {
128 StringRef CPUName, ABIName;
129 tools::mips::getMipsCPUAndABI(Args, Triple, CPUName, ABIName);
130 return llvm::StringSwitch<std::string>(ABIName)
131 .Case(S: "o32", Value: "")
132 .Case(S: "n32", Value: "32")
133 .Case(S: "n64", Value: "64");
134}
135
136// Convert ABI name to the GNU tools acceptable variant.
137StringRef mips::getGnuCompatibleMipsABIName(StringRef ABI) {
138 return llvm::StringSwitch<llvm::StringRef>(ABI)
139 .Case(S: "o32", Value: "32")
140 .Case(S: "n64", Value: "64")
141 .Default(Value: ABI);
142}
143
144// Select the MIPS float ABI as determined by -msoft-float, -mhard-float,
145// and -mfloat-abi=.
146mips::FloatABI mips::getMipsFloatABI(const Driver &D, const ArgList &Args,
147 const llvm::Triple &Triple) {
148 mips::FloatABI ABI = mips::FloatABI::Invalid;
149 if (Arg *A =
150 Args.getLastArg(Ids: options::OPT_msoft_float, Ids: options::OPT_mhard_float,
151 Ids: options::OPT_mfloat_abi_EQ)) {
152 if (A->getOption().matches(ID: options::OPT_msoft_float))
153 ABI = mips::FloatABI::Soft;
154 else if (A->getOption().matches(ID: options::OPT_mhard_float))
155 ABI = mips::FloatABI::Hard;
156 else {
157 ABI = llvm::StringSwitch<mips::FloatABI>(A->getValue())
158 .Case(S: "soft", Value: mips::FloatABI::Soft)
159 .Case(S: "hard", Value: mips::FloatABI::Hard)
160 .Default(Value: mips::FloatABI::Invalid);
161 if (ABI == mips::FloatABI::Invalid && !StringRef(A->getValue()).empty()) {
162 D.Diag(DiagID: clang::diag::err_drv_invalid_mfloat_abi) << A->getAsString(Args);
163 ABI = mips::FloatABI::Hard;
164 }
165 }
166 }
167
168 // If unspecified, choose the default based on the platform.
169 if (ABI == mips::FloatABI::Invalid) {
170 if (Triple.isOSFreeBSD()) {
171 // For FreeBSD, assume "soft" on all flavors of MIPS.
172 ABI = mips::FloatABI::Soft;
173 } else {
174 // Assume "hard", because it's a default value used by gcc.
175 // When we start to recognize specific target MIPS processors,
176 // we will be able to select the default more correctly.
177 ABI = mips::FloatABI::Hard;
178 }
179 }
180
181 assert(ABI != mips::FloatABI::Invalid && "must select an ABI");
182 return ABI;
183}
184
185void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
186 const ArgList &Args,
187 std::vector<StringRef> &Features) {
188 StringRef CPUName;
189 StringRef ABIName;
190 getMipsCPUAndABI(Args, Triple, CPUName, ABIName);
191 ABIName = getGnuCompatibleMipsABIName(ABI: ABIName);
192
193 // Historically, PIC code for MIPS was associated with -mabicalls, a.k.a
194 // SVR4 abicalls. Static code does not use SVR4 calling sequences. An ABI
195 // extension was developed by Richard Sandiford & Code Sourcery to support
196 // static code calling PIC code (CPIC). For O32 and N32 this means we have
197 // several combinations of PIC/static and abicalls. Pure static, static
198 // with the CPIC extension, and pure PIC code.
199
200 // At final link time, O32 and N32 with CPIC will have another section
201 // added to the binary which contains the stub functions to perform
202 // any fixups required for PIC code.
203
204 // For N64, the situation is more regular: code can either be static
205 // (non-abicalls) or PIC (abicalls). GCC has traditionally picked PIC code
206 // code for N64. Since Clang has already built the relocation model portion
207 // of the commandline, we pick add +noabicalls feature in the N64 static
208 // case.
209
210 // The is another case to be accounted for: -msym32, which enforces that all
211 // symbols have 32 bits in size. In this case, N64 can in theory use CPIC
212 // but it is unsupported.
213
214 // The combinations for N64 are:
215 // a) Static without abicalls and 64bit symbols.
216 // b) Static with abicalls and 32bit symbols.
217 // c) PIC with abicalls and 64bit symbols.
218
219 // For case (a) we need to add +noabicalls for N64.
220
221 bool IsN64 = ABIName == "64";
222 bool IsPIC = false;
223 bool NonPIC = false;
224 bool HasNaN2008Opt = false;
225
226 Arg *LastPICArg = Args.getLastArg(Ids: options::OPT_fPIC, Ids: options::OPT_fno_PIC,
227 Ids: options::OPT_fpic, Ids: options::OPT_fno_pic,
228 Ids: options::OPT_fPIE, Ids: options::OPT_fno_PIE,
229 Ids: options::OPT_fpie, Ids: options::OPT_fno_pie);
230 if (LastPICArg) {
231 Option O = LastPICArg->getOption();
232 NonPIC =
233 (O.matches(ID: options::OPT_fno_PIC) || O.matches(ID: options::OPT_fno_pic) ||
234 O.matches(ID: options::OPT_fno_PIE) || O.matches(ID: options::OPT_fno_pie));
235 IsPIC =
236 (O.matches(ID: options::OPT_fPIC) || O.matches(ID: options::OPT_fpic) ||
237 O.matches(ID: options::OPT_fPIE) || O.matches(ID: options::OPT_fpie));
238 }
239
240 bool UseAbiCalls = false;
241
242 Arg *ABICallsArg =
243 Args.getLastArg(Ids: options::OPT_mabicalls, Ids: options::OPT_mno_abicalls);
244 UseAbiCalls =
245 !ABICallsArg || ABICallsArg->getOption().matches(ID: options::OPT_mabicalls);
246
247 if (IsN64 && NonPIC && (!ABICallsArg || UseAbiCalls)) {
248 D.Diag(DiagID: diag::warn_drv_unsupported_pic_with_mabicalls)
249 << LastPICArg->getAsString(Args) << (!ABICallsArg ? 0 : 1);
250 }
251
252 if (ABICallsArg && !UseAbiCalls && IsPIC) {
253 D.Diag(DiagID: diag::err_drv_unsupported_noabicalls_pic);
254 }
255
256 if (CPUName == "i6500" || CPUName == "i6400") {
257 // MIPS cpu i6400 and i6500 support MSA (Mips SIMD Architecture)
258 // by default.
259 Features.push_back(x: "+msa");
260 }
261
262 if (!UseAbiCalls)
263 Features.push_back(x: "+noabicalls");
264 else
265 Features.push_back(x: "-noabicalls");
266
267 if (Arg *A = Args.getLastArg(Ids: options::OPT_mlong_calls,
268 Ids: options::OPT_mno_long_calls)) {
269 if (A->getOption().matches(ID: options::OPT_mno_long_calls))
270 Features.push_back(x: "-long-calls");
271 else if (!UseAbiCalls)
272 Features.push_back(x: "+long-calls");
273 else
274 D.Diag(DiagID: diag::warn_drv_unsupported_longcalls) << (ABICallsArg ? 0 : 1);
275 }
276
277 if (Arg *A = Args.getLastArg(Ids: options::OPT_mxgot, Ids: options::OPT_mno_xgot)) {
278 if (A->getOption().matches(ID: options::OPT_mxgot))
279 Features.push_back(x: "+xgot");
280 else
281 Features.push_back(x: "-xgot");
282 }
283
284 mips::FloatABI FloatABI = mips::getMipsFloatABI(D, Args, Triple);
285 if (FloatABI == mips::FloatABI::Soft) {
286 // FIXME: Note, this is a hack. We need to pass the selected float
287 // mode to the MipsTargetInfoBase to define appropriate macros there.
288 // Now it is the only method.
289 Features.push_back(x: "+soft-float");
290 }
291
292 if (Arg *A = Args.getLastArg(Ids: options::OPT_mnan_EQ)) {
293 StringRef Val = StringRef(A->getValue());
294 if (Val == "2008") {
295 if (mips::getIEEE754Standard(CPU&: CPUName) & mips::Std2008) {
296 Features.push_back(x: "+nan2008");
297 HasNaN2008Opt = true;
298 } else {
299 Features.push_back(x: "-nan2008");
300 D.Diag(DiagID: diag::warn_target_unsupported_nan2008) << CPUName;
301 }
302 } else if (Val == "legacy") {
303 if (mips::getIEEE754Standard(CPU&: CPUName) & mips::Legacy)
304 Features.push_back(x: "-nan2008");
305 else {
306 Features.push_back(x: "+nan2008");
307 D.Diag(DiagID: diag::warn_target_unsupported_nanlegacy) << CPUName;
308 }
309 } else
310 D.Diag(DiagID: diag::err_drv_unsupported_option_argument)
311 << A->getSpelling() << Val;
312 }
313
314 if (Arg *A = Args.getLastArg(Ids: options::OPT_mabs_EQ)) {
315 StringRef Val = StringRef(A->getValue());
316 if (Val == "2008") {
317 if (mips::getIEEE754Standard(CPU&: CPUName) & mips::Std2008) {
318 Features.push_back(x: "+abs2008");
319 } else {
320 Features.push_back(x: "-abs2008");
321 D.Diag(DiagID: diag::warn_target_unsupported_abs2008) << CPUName;
322 }
323 } else if (Val == "legacy") {
324 if (mips::getIEEE754Standard(CPU&: CPUName) & mips::Legacy) {
325 Features.push_back(x: "-abs2008");
326 } else {
327 Features.push_back(x: "+abs2008");
328 D.Diag(DiagID: diag::warn_target_unsupported_abslegacy) << CPUName;
329 }
330 } else {
331 D.Diag(DiagID: diag::err_drv_unsupported_option_argument)
332 << A->getSpelling() << Val;
333 }
334 } else if (HasNaN2008Opt) {
335 Features.push_back(x: "+abs2008");
336 }
337
338 AddTargetFeature(Args, Features, OnOpt: options::OPT_msingle_float,
339 OffOpt: options::OPT_mdouble_float, FeatureName: "single-float");
340 AddTargetFeature(Args, Features, OnOpt: options::OPT_mips16, OffOpt: options::OPT_mno_mips16,
341 FeatureName: "mips16");
342 AddTargetFeature(Args, Features, OnOpt: options::OPT_mmicromips,
343 OffOpt: options::OPT_mno_micromips, FeatureName: "micromips");
344 AddTargetFeature(Args, Features, OnOpt: options::OPT_mdsp, OffOpt: options::OPT_mno_dsp,
345 FeatureName: "dsp");
346 AddTargetFeature(Args, Features, OnOpt: options::OPT_mdspr2, OffOpt: options::OPT_mno_dspr2,
347 FeatureName: "dspr2");
348 AddTargetFeature(Args, Features, OnOpt: options::OPT_mmsa, OffOpt: options::OPT_mno_msa,
349 FeatureName: "msa");
350 if (Arg *A = Args.getLastArg(
351 Ids: options::OPT_mstrict_align, Ids: options::OPT_mno_strict_align,
352 Ids: options::OPT_mno_unaligned_access, Ids: options::OPT_munaligned_access)) {
353 if (A->getOption().matches(ID: options::OPT_mstrict_align) ||
354 A->getOption().matches(ID: options::OPT_mno_unaligned_access))
355 Features.push_back(x: Args.MakeArgString(Str: "+strict-align"));
356 else
357 Features.push_back(x: Args.MakeArgString(Str: "-strict-align"));
358 }
359
360 // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
361 // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
362 // nooddspreg.
363 if (Arg *A = Args.getLastArg(Ids: options::OPT_mfp32, Ids: options::OPT_mfpxx,
364 Ids: options::OPT_mfp64)) {
365 if (A->getOption().matches(ID: options::OPT_mfp32))
366 Features.push_back(x: "-fp64");
367 else if (A->getOption().matches(ID: options::OPT_mfpxx)) {
368 Features.push_back(x: "+fpxx");
369 Features.push_back(x: "+nooddspreg");
370 } else
371 Features.push_back(x: "+fp64");
372 } else if (mips::shouldUseFPXX(Args, Triple, CPUName, ABIName, FloatABI)) {
373 Features.push_back(x: "+fpxx");
374 Features.push_back(x: "+nooddspreg");
375 } else if (Arg *A = Args.getLastArg(Ids: options::OPT_mmsa)) {
376 if (A->getOption().matches(ID: options::OPT_mmsa))
377 Features.push_back(x: "+fp64");
378 }
379
380 AddTargetFeature(Args, Features, OnOpt: options::OPT_mno_odd_spreg,
381 OffOpt: options::OPT_modd_spreg, FeatureName: "nooddspreg");
382 AddTargetFeature(Args, Features, OnOpt: options::OPT_mno_madd4, OffOpt: options::OPT_mmadd4,
383 FeatureName: "nomadd4");
384 AddTargetFeature(Args, Features, OnOpt: options::OPT_mmt, OffOpt: options::OPT_mno_mt, FeatureName: "mt");
385 AddTargetFeature(Args, Features, OnOpt: options::OPT_mcrc, OffOpt: options::OPT_mno_crc,
386 FeatureName: "crc");
387 AddTargetFeature(Args, Features, OnOpt: options::OPT_mvirt, OffOpt: options::OPT_mno_virt,
388 FeatureName: "virt");
389 AddTargetFeature(Args, Features, OnOpt: options::OPT_mginv, OffOpt: options::OPT_mno_ginv,
390 FeatureName: "ginv");
391 AddTargetFeature(Args, Features, OnOpt: options::OPT_mfix_r5900,
392 OffOpt: options::OPT_mno_fix_r5900, FeatureName: "fix-r5900");
393
394 if (Arg *A = Args.getLastArg(Ids: options::OPT_mindirect_jump_EQ)) {
395 StringRef Val = StringRef(A->getValue());
396 if (Val == "hazard") {
397 Arg *B =
398 Args.getLastArg(Ids: options::OPT_mmicromips, Ids: options::OPT_mno_micromips);
399 Arg *C = Args.getLastArg(Ids: options::OPT_mips16, Ids: options::OPT_mno_mips16);
400
401 if (B && B->getOption().matches(ID: options::OPT_mmicromips))
402 D.Diag(DiagID: diag::err_drv_unsupported_indirect_jump_opt)
403 << "hazard" << "micromips";
404 else if (C && C->getOption().matches(ID: options::OPT_mips16))
405 D.Diag(DiagID: diag::err_drv_unsupported_indirect_jump_opt)
406 << "hazard" << "mips16";
407 else if (mips::supportsIndirectJumpHazardBarrier(CPU&: CPUName))
408 Features.push_back(x: "+use-indirect-jump-hazard");
409 else
410 D.Diag(DiagID: diag::err_drv_unsupported_indirect_jump_opt)
411 << "hazard" << CPUName;
412 } else
413 D.Diag(DiagID: diag::err_drv_unknown_indirect_jump_opt) << Val;
414 }
415}
416
417mips::IEEE754Standard mips::getIEEE754Standard(StringRef &CPU) {
418 // Strictly speaking, mips32r2 and mips64r2 do not conform to the
419 // IEEE754-2008 standard. Support for this standard was first introduced
420 // in Release 3. However, other compilers have traditionally allowed it
421 // for Release 2 so we should do the same.
422 return (IEEE754Standard)llvm::StringSwitch<int>(CPU)
423 .Case(S: "mips1", Value: Legacy)
424 .Case(S: "mips2", Value: Legacy)
425 .Case(S: "mips3", Value: Legacy)
426 .Case(S: "mips4", Value: Legacy)
427 .Case(S: "mips5", Value: Legacy)
428 .Case(S: "mips32", Value: Legacy)
429 .Case(S: "mips32r2", Value: Legacy | Std2008)
430 .Case(S: "mips32r3", Value: Legacy | Std2008)
431 .Case(S: "mips32r5", Value: Legacy | Std2008)
432 .Case(S: "mips32r6", Value: Std2008)
433 .Case(S: "mips64", Value: Legacy)
434 .Case(S: "mips64r2", Value: Legacy | Std2008)
435 .Case(S: "mips64r3", Value: Legacy | Std2008)
436 .Case(S: "mips64r5", Value: Legacy | Std2008)
437 .Case(S: "mips64r6", Value: Std2008)
438 .Default(Value: Std2008);
439}
440
441bool mips::hasCompactBranches(StringRef &CPU) {
442 // mips32r6 and mips64r6 have compact branches.
443 return llvm::StringSwitch<bool>(CPU)
444 .Case(S: "mips32r6", Value: true)
445 .Case(S: "mips64r6", Value: true)
446 .Case(S: "i6400", Value: true)
447 .Case(S: "i6500", Value: true)
448 .Default(Value: false);
449}
450
451bool mips::hasMipsAbiArg(const ArgList &Args, const char *Value) {
452 Arg *A = Args.getLastArg(Ids: options::OPT_mabi_EQ);
453 return A && (A->getValue() == StringRef(Value));
454}
455
456bool mips::isUCLibc(const ArgList &Args) {
457 Arg *A = Args.getLastArg(Ids: options::OPT_m_libc_Group);
458 return A && A->getOption().matches(ID: options::OPT_muclibc);
459}
460
461bool mips::isNaN2008(const Driver &D, const ArgList &Args,
462 const llvm::Triple &Triple) {
463 if (Arg *NaNArg = Args.getLastArg(Ids: options::OPT_mnan_EQ))
464 return llvm::StringSwitch<bool>(NaNArg->getValue())
465 .Case(S: "2008", Value: true)
466 .Case(S: "legacy", Value: false)
467 .Default(Value: false);
468
469 // NaN2008 is the default for MIPS32r6/MIPS64r6.
470 return llvm::StringSwitch<bool>(getCPUName(D, Args, T: Triple))
471 .Cases(CaseStrings: {"mips32r6", "mips64r6"}, Value: true)
472 .Default(Value: false);
473}
474
475bool mips::isFPXXDefault(const llvm::Triple &Triple, StringRef CPUName,
476 StringRef ABIName, mips::FloatABI FloatABI) {
477 if (ABIName != "32")
478 return false;
479
480 // FPXX shouldn't be used if either -msoft-float or -mfloat-abi=soft is
481 // present.
482 if (FloatABI == mips::FloatABI::Soft)
483 return false;
484
485 return llvm::StringSwitch<bool>(CPUName)
486 .Cases(CaseStrings: {"mips2", "mips3", "mips4", "mips5"}, Value: true)
487 .Cases(CaseStrings: {"mips32", "mips32r2", "mips32r3", "mips32r5"}, Value: true)
488 .Cases(CaseStrings: {"mips64", "mips64r2", "mips64r3", "mips64r5"}, Value: true)
489 .Default(Value: false);
490}
491
492bool mips::shouldUseFPXX(const ArgList &Args, const llvm::Triple &Triple,
493 StringRef CPUName, StringRef ABIName,
494 mips::FloatABI FloatABI) {
495 bool UseFPXX = isFPXXDefault(Triple, CPUName, ABIName, FloatABI);
496
497 // FPXX shouldn't be used if -msingle-float is present.
498 if (Arg *A = Args.getLastArg(Ids: options::OPT_msingle_float,
499 Ids: options::OPT_mdouble_float))
500 if (A->getOption().matches(ID: options::OPT_msingle_float))
501 UseFPXX = false;
502 // FP64 should be used for MSA.
503 if (Arg *A = Args.getLastArg(Ids: options::OPT_mmsa))
504 if (A->getOption().matches(ID: options::OPT_mmsa))
505 UseFPXX = llvm::StringSwitch<bool>(CPUName)
506 .Cases(CaseStrings: {"mips32r2", "mips32r3", "mips32r5"}, Value: false)
507 .Cases(CaseStrings: {"mips64r2", "mips64r3", "mips64r5"}, Value: false)
508 .Default(Value: UseFPXX);
509
510 return UseFPXX;
511}
512
513bool mips::supportsIndirectJumpHazardBarrier(StringRef &CPU) {
514 // Supporting the hazard barrier method of dealing with indirect
515 // jumps requires MIPSR2 support.
516 return llvm::StringSwitch<bool>(CPU)
517 .Case(S: "mips32r2", Value: true)
518 .Case(S: "mips32r3", Value: true)
519 .Case(S: "mips32r5", Value: true)
520 .Case(S: "mips32r6", Value: true)
521 .Case(S: "mips64r2", Value: true)
522 .Case(S: "mips64r3", Value: true)
523 .Case(S: "mips64r5", Value: true)
524 .Case(S: "mips64r6", Value: true)
525 .Case(S: "octeon", Value: true)
526 .Case(S: "p5600", Value: true)
527 .Case(S: "i6400", Value: true)
528 .Case(S: "i6500", Value: true)
529 .Default(Value: false);
530}
531