1//===--- RISCV.cpp - RISC-V Helpers for Tools -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCV.h"
10#include "../Clang.h"
11#include "clang/Basic/DiagnosticDriver.h"
12#include "clang/Driver/CommonArgs.h"
13#include "clang/Driver/Driver.h"
14#include "clang/Options/Options.h"
15#include "llvm/Option/ArgList.h"
16#include "llvm/Support/Error.h"
17#include "llvm/TargetParser/Host.h"
18#include "llvm/TargetParser/RISCVISAInfo.h"
19#include "llvm/TargetParser/RISCVTargetParser.h"
20
21using namespace clang::driver;
22using namespace clang::driver::tools;
23using namespace clang;
24using namespace llvm::opt;
25
26// Returns false if an error is diagnosed.
27static bool getArchFeatures(const Driver &D, StringRef Arch,
28 std::vector<StringRef> &Features,
29 const ArgList &Args) {
30 bool EnableExperimentalExtensions =
31 Args.hasArg(Ids: options::OPT_menable_experimental_extensions);
32 auto ISAInfo =
33 llvm::RISCVISAInfo::parseArchString(Arch, EnableExperimentalExtension: EnableExperimentalExtensions);
34 if (!ISAInfo) {
35 handleAllErrors(E: ISAInfo.takeError(), Handlers: [&](llvm::StringError &ErrMsg) {
36 D.Diag(DiagID: diag::err_drv_invalid_riscv_arch_name)
37 << Arch << ErrMsg.getMessage();
38 });
39
40 return false;
41 }
42
43 for (const std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/AddAllExtensions: true,
44 /*IgnoreUnknown=*/false))
45 Features.push_back(x: Args.MakeArgString(Str));
46
47 if (EnableExperimentalExtensions)
48 Features.push_back(x: Args.MakeArgString(Str: "+experimental"));
49
50 return true;
51}
52
53static bool isValidRISCVCPU(const Driver &D, const Arg *A,
54 const llvm::Triple &Triple, StringRef Mcpu) {
55 bool Is64Bit = Triple.isRISCV64();
56 if (!llvm::RISCV::parseCPU(CPU: Mcpu, IsRV64: Is64Bit)) {
57 // Try inverting Is64Bit in case the CPU is valid, but for the wrong target.
58 if (llvm::RISCV::parseCPU(CPU: Mcpu, IsRV64: !Is64Bit))
59 D.Diag(DiagID: clang::diag::err_drv_invalid_riscv_cpu_name_for_target)
60 << Mcpu << Is64Bit;
61 else
62 D.Diag(DiagID: clang::diag::err_drv_unsupported_option_argument)
63 << A->getSpelling() << Mcpu;
64 return false;
65 }
66 return true;
67}
68
69void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
70 const ArgList &Args,
71 std::vector<StringRef> &Features) {
72 std::string MArch = getRISCVArch(Args, Triple);
73
74 if (!getArchFeatures(D, Arch: MArch, Features, Args))
75 return;
76
77 bool CPUFastScalarUnaligned = false;
78 bool CPUFastVectorUnaligned = false;
79
80 // If users give march and mcpu, get std extension feature from MArch
81 // and other features (ex. mirco architecture feature) from mcpu
82 if (Arg *A = Args.getLastArg(Ids: options::OPT_mcpu_EQ)) {
83 StringRef CPU = A->getValue();
84 if (CPU == "native")
85 CPU = llvm::sys::getHostCPUName();
86
87 if (!isValidRISCVCPU(D, A, Triple, Mcpu: CPU))
88 return;
89
90 if (llvm::RISCV::hasFastScalarUnalignedAccess(CPU))
91 CPUFastScalarUnaligned = true;
92 if (llvm::RISCV::hasFastVectorUnalignedAccess(CPU))
93 CPUFastVectorUnaligned = true;
94 }
95
96// Handle features corresponding to "-ffixed-X" options
97#define RESERVE_REG(REG) \
98 if (Args.hasArg(options::OPT_ffixed_##REG)) \
99 Features.push_back("+reserve-" #REG);
100 RESERVE_REG(x1)
101 RESERVE_REG(x2)
102 RESERVE_REG(x3)
103 RESERVE_REG(x4)
104 RESERVE_REG(x5)
105 RESERVE_REG(x6)
106 RESERVE_REG(x7)
107 RESERVE_REG(x8)
108 RESERVE_REG(x9)
109 RESERVE_REG(x10)
110 RESERVE_REG(x11)
111 RESERVE_REG(x12)
112 RESERVE_REG(x13)
113 RESERVE_REG(x14)
114 RESERVE_REG(x15)
115 RESERVE_REG(x16)
116 RESERVE_REG(x17)
117 RESERVE_REG(x18)
118 RESERVE_REG(x19)
119 RESERVE_REG(x20)
120 RESERVE_REG(x21)
121 RESERVE_REG(x22)
122 RESERVE_REG(x23)
123 RESERVE_REG(x24)
124 RESERVE_REG(x25)
125 RESERVE_REG(x26)
126 RESERVE_REG(x27)
127 RESERVE_REG(x28)
128 RESERVE_REG(x29)
129 RESERVE_REG(x30)
130 RESERVE_REG(x31)
131#undef RESERVE_REG
132
133 // -mrelax is default, unless -mno-relax is specified.
134 if (Args.hasFlag(Pos: options::OPT_mrelax, Neg: options::OPT_mno_relax, Default: true))
135 Features.push_back(x: "+relax");
136 else
137 Features.push_back(x: "-relax");
138
139 // If -mstrict-align, -mno-strict-align, -mscalar-strict-align, or
140 // -mno-scalar-strict-align is passed, use it. Otherwise, the
141 // unaligned-scalar-mem is enabled if the CPU supports it or the target is
142 // Android.
143 if (const Arg *A = Args.getLastArg(
144 Ids: options::OPT_mno_strict_align, Ids: options::OPT_mscalar_strict_align,
145 Ids: options::OPT_mstrict_align, Ids: options::OPT_mno_scalar_strict_align)) {
146 if (A->getOption().matches(ID: options::OPT_mno_strict_align) ||
147 A->getOption().matches(ID: options::OPT_mno_scalar_strict_align)) {
148 Features.push_back(x: "+unaligned-scalar-mem");
149 } else {
150 Features.push_back(x: "-unaligned-scalar-mem");
151 }
152 } else if (CPUFastScalarUnaligned || Triple.isAndroid()) {
153 Features.push_back(x: "+unaligned-scalar-mem");
154 }
155
156 // If -mstrict-align, -mno-strict-align, -mvector-strict-align, or
157 // -mno-vector-strict-align is passed, use it. Otherwise, the
158 // unaligned-vector-mem is enabled if the CPU supports it or the target is
159 // Android.
160 if (const Arg *A = Args.getLastArg(
161 Ids: options::OPT_mno_strict_align, Ids: options::OPT_mvector_strict_align,
162 Ids: options::OPT_mstrict_align, Ids: options::OPT_mno_vector_strict_align)) {
163 if (A->getOption().matches(ID: options::OPT_mno_strict_align) ||
164 A->getOption().matches(ID: options::OPT_mno_vector_strict_align)) {
165 Features.push_back(x: "+unaligned-vector-mem");
166 } else {
167 Features.push_back(x: "-unaligned-vector-mem");
168 }
169 } else if (CPUFastVectorUnaligned || Triple.isAndroid()) {
170 Features.push_back(x: "+unaligned-vector-mem");
171 }
172
173 if (Triple.isRISCV32()) {
174 // Handle `-mzilsd-word-align` and `-mzilsd-strict-align` on rv32. These
175 // interact with the scalar alignment options - if unaligned scalar memory
176 // is allowed then that takes precedence over this option, as zilsd accesses
177 // can be 1-byte aligned in this case. Otherwise, the option
178 // `-mzilsd-word-align` option allows zilsd accesses to be 4-byte aligned
179 // rather than the usual 8-byte aligned (`-mzilsd-strict-align`).
180 if (const Arg *A = Args.getLastArg(
181 Ids: options::OPT_mstrict_align, Ids: options::OPT_mscalar_strict_align,
182 Ids: options::OPT_mzilsd_word_align, Ids: options::OPT_mno_strict_align,
183 Ids: options::OPT_mno_scalar_strict_align,
184 Ids: options::OPT_mzilsd_strict_align)) {
185 if (A->getOption().matches(ID: options::OPT_mno_strict_align) ||
186 A->getOption().matches(ID: options::OPT_mno_scalar_strict_align) ||
187 A->getOption().matches(ID: options::OPT_mzilsd_word_align)) {
188 Features.push_back(x: "+zilsd-word-align");
189 } else {
190 Features.push_back(x: "-zilsd-word-align");
191 }
192 }
193 } else {
194 // Zilsd is not available on RV64, so report an error for these options.
195 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mzilsd_word_align,
196 Ids: options::OPT_mzilsd_strict_align)) {
197 D.Diag(DiagID: clang::diag::err_drv_unsupported_opt_for_target)
198 << A->getSpelling() << Triple.getTriple();
199 }
200 }
201
202 SmallVector<std::string, 4> TuneFeatures;
203 if (!riscv::getRISCVTuneCPU(D, Args, TuneFeatures: &TuneFeatures))
204 return;
205 for (const std::string &TF : TuneFeatures)
206 Features.push_back(x: Args.MakeArgString(Str: TF));
207
208 // Now add any that the user explicitly requested on the command line,
209 // which may override the defaults.
210 handleTargetFeaturesGroup(D, Triple, Args, Features,
211 Group: options::OPT_m_riscv_Features_Group);
212}
213
214StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
215 assert(Triple.isRISCV() && "Unexpected triple");
216
217 // GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
218 // configured using `--with-abi=`, then the logic for the default choice is
219 // defined in config.gcc. This function is based on the logic in GCC 9.2.0.
220 //
221 // The logic used in GCC 9.2.0 is the following, in order:
222 // 1. Explicit choices using `--with-abi=`
223 // 2. A default based on `--with-arch=`, if provided
224 // 3. A default based on the target triple's arch
225 //
226 // The logic in config.gcc is a little circular but it is not inconsistent.
227 //
228 // Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
229 // and `-mabi=` respectively instead.
230 //
231 // In order to make chosing logic more clear, Clang uses the following logic,
232 // in order:
233 // 1. Explicit choices using `-mabi=`
234 // 2. A default based on the architecture as determined by getRISCVArch
235 // 3. Choose a default based on the triple
236
237 // 1. If `-mabi=` is specified, use it.
238 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mabi_EQ))
239 return A->getValue();
240
241 // 2. Choose a default based on the target architecture.
242 //
243 // rv32g | rv32*d -> ilp32d
244 // rv32e -> ilp32e
245 // rv32* -> ilp32
246 // rv64g | rv64*d -> lp64d
247 // rv64e -> lp64e
248 // rv64* -> lp64
249 std::string Arch = getRISCVArch(Args, Triple);
250
251 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
252 Arch, /* EnableExperimentalExtension */ true);
253 // Ignore parsing error, just go 3rd step.
254 if (!llvm::errorToBool(Err: ParseResult.takeError()))
255 return (*ParseResult)->computeDefaultABI();
256
257 // 3. Choose a default based on the triple
258 //
259 // We deviate from GCC's defaults here:
260 // - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
261 // - On all other OSs we use the double floating point calling convention.
262 if (Triple.isRISCV32()) {
263 if (Triple.getOS() == llvm::Triple::UnknownOS)
264 return "ilp32";
265 else
266 return "ilp32d";
267 } else {
268 if (Triple.getOS() == llvm::Triple::UnknownOS)
269 return "lp64";
270 else
271 return "lp64d";
272 }
273}
274
275std::string riscv::getRISCVArch(const llvm::opt::ArgList &Args,
276 const llvm::Triple &Triple) {
277 assert(Triple.isRISCV() && "Unexpected triple");
278
279 // GCC's logic around choosing a default `-march=` is complex. If GCC is not
280 // configured using `--with-arch=`, then the logic for the default choice is
281 // defined in config.gcc. This function is based on the logic in GCC 9.2.0. We
282 // deviate from GCC's default on additional `-mcpu` option (GCC does not
283 // support `-mcpu`) and baremetal targets (UnknownOS) where neither `-march`
284 // nor `-mabi` is specified.
285 //
286 // The logic used in GCC 9.2.0 is the following, in order:
287 // 1. Explicit choices using `--with-arch=`
288 // 2. A default based on `--with-abi=`, if provided
289 // 3. A default based on the target triple's arch
290 //
291 // The logic in config.gcc is a little circular but it is not inconsistent.
292 //
293 // Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
294 // and `-mabi=` respectively instead.
295 //
296 // Clang uses the following logic, in order:
297 // 1. Explicit choices using `-march=`
298 // 2. Based on `-mcpu` if the target CPU has a default ISA string
299 // 3. A default based on `-mabi`, if provided
300 // 4. A default based on the target triple's arch
301 //
302 // Clang does not yet support MULTILIB_REUSE, so we use `rv{XLEN}imafdc`
303 // instead of `rv{XLEN}gc` though they are (currently) equivalent.
304
305 // 1. If `-march=` is specified, use it unless the value is "unset".
306 if (const Arg *A = Args.getLastArg(Ids: options::OPT_march_EQ)) {
307 StringRef MArch = A->getValue();
308 if (MArch != "unset")
309 return MArch.str();
310 }
311
312 // 2. Get march (isa string) based on `-mcpu=`
313 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mcpu_EQ)) {
314 StringRef CPU = A->getValue();
315 if (CPU == "native") {
316 CPU = llvm::sys::getHostCPUName();
317 // If the target cpu is unrecognized, use target features.
318 if (CPU.starts_with(Prefix: "generic")) {
319 auto FeatureMap = llvm::sys::getHostCPUFeatures();
320 // hwprobe may be unavailable on older Linux versions.
321 if (!FeatureMap.empty()) {
322 std::vector<std::string> Features;
323 for (auto &F : FeatureMap)
324 Features.push_back(x: ((F.second ? "+" : "-") + F.first()).str());
325 auto ParseResult = llvm::RISCVISAInfo::parseFeatures(
326 XLen: Triple.isRISCV32() ? 32 : 64, Features);
327 if (ParseResult)
328 return (*ParseResult)->toString();
329 }
330 }
331 }
332
333 StringRef MArch = llvm::RISCV::getMArchFromMcpu(CPU);
334 // Bypass if target cpu's default march is empty.
335 if (!MArch.empty())
336 return MArch.str();
337 }
338
339 // 3. Choose a default based on `-mabi=`
340 //
341 // ilp32e -> rv32e
342 // lp64e -> rv64e
343 // ilp32 | ilp32f | ilp32d -> rv32imafdc
344 // lp64 | lp64f | lp64d -> rv64imafdc
345 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mabi_EQ)) {
346 StringRef MABI = A->getValue();
347
348 if (MABI.equals_insensitive(RHS: "ilp32e"))
349 return "rv32e";
350 if (MABI.equals_insensitive(RHS: "lp64e"))
351 return "rv64e";
352 if (MABI.starts_with_insensitive(Prefix: "ilp32"))
353 return "rv32imafdc";
354 if (MABI.starts_with_insensitive(Prefix: "lp64")) {
355 if (Triple.isAndroid())
356 return "rv64imafdcv_zba_zbb_zbs";
357 if (Triple.isOSFuchsia())
358 return "rva22u64_v";
359 return "rv64imafdc";
360 }
361 }
362
363 // 4. Choose a default based on the triple
364 //
365 // We deviate from GCC's defaults here:
366 // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
367 // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
368 if (Triple.isRISCV32()) {
369 if (Triple.getOS() == llvm::Triple::UnknownOS)
370 return "rv32imac";
371 return "rv32imafdc";
372 }
373
374 if (Triple.getOS() == llvm::Triple::UnknownOS)
375 return "rv64imac";
376 if (Triple.isAndroid())
377 return "rv64imafdcv_zba_zbb_zbs";
378 if (Triple.isOSFuchsia())
379 return "rva22u64_v";
380 return "rv64imafdc";
381}
382
383std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args,
384 const llvm::Triple &Triple) {
385 std::string CPU;
386 // If we have -mcpu, use that.
387 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mcpu_EQ))
388 CPU = A->getValue();
389
390 // Handle CPU name is 'native'.
391 if (CPU == "native")
392 CPU = llvm::sys::getHostCPUName();
393
394 if (!CPU.empty())
395 return CPU;
396
397 return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
398}
399
400std::optional<StringRef>
401riscv::getRISCVTuneCPU(const Driver &D, const llvm::opt::ArgList &Args,
402 SmallVectorImpl<std::string> *TuneFeatures) {
403 const Arg *MTuneArg = Args.getLastArg(Ids: options::OPT_mtune_EQ);
404 if (!MTuneArg)
405 return "";
406
407 StringRef MTune = MTuneArg->getValue();
408 // Split the CPU name part from the tune features string.
409 auto [TuneCPU, TFString] = MTune.split(Separator: ':');
410 if (!Args.hasFlag(Pos: options::OPT_mexperimental_mtune_syntax,
411 Neg: options::OPT_mno_experimental_mtune_syntax, Default: false)) {
412 if (!TFString.empty()) {
413 // Only print this diagnostics if it's used for retrieving tune features
414 // to avoid printing the same error message multiple times.
415 if (TuneFeatures)
416 D.Diag(DiagID: diag::err_drv_invalid_riscv_mtune_string)
417 << 0 << MTune
418 << "require '-mexperimental-mtune-syntax' to use with tune feature "
419 "string";
420 return std::nullopt;
421 }
422 return MTune;
423 }
424
425 if (!TuneFeatures || TFString.empty())
426 return TuneCPU;
427 if (auto E = llvm::RISCV::parseTuneFeatureString(ProcName: TuneCPU, TFString,
428 TuneFeatures&: *TuneFeatures)) {
429 D.Diag(DiagID: diag::err_drv_invalid_riscv_mtune_string)
430 << 1 << TFString << llvm::toString(E: std::move(E));
431 return std::nullopt;
432 }
433
434 return TuneCPU;
435}
436