1//===-- Compile time cpu feature detection ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// This file lists target cpu features by introspecting compiler enabled
9// preprocessor definitions.
10//===----------------------------------------------------------------------===//
11
12#ifndef LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H
13#define LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H
14
15#include "architectures.h"
16
17#if defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
18#define LIBC_TARGET_CPU_HAS_FULLFP16
19#endif
20
21#if defined(__ARM_FEATURE_SVE)
22#define LIBC_TARGET_CPU_HAS_SVE
23#endif
24
25#if defined(__ARM_FEATURE_SVE2)
26#define LIBC_TARGET_CPU_HAS_SVE2
27#endif
28
29#if defined(__ARM_FEATURE_MOPS)
30#define LIBC_TARGET_CPU_HAS_MOPS
31#endif
32
33#if defined(__SSE2__)
34#define LIBC_TARGET_CPU_HAS_SSE2
35#define LIBC_TARGET_CPU_HAS_FPU_FLOAT
36#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE
37#endif
38
39#if defined(__SSE4_2__)
40#define LIBC_TARGET_CPU_HAS_SSE4_2
41#endif
42
43#if defined(__AVX__)
44#define LIBC_TARGET_CPU_HAS_AVX
45#endif
46
47#if defined(__AVX2__)
48#define LIBC_TARGET_CPU_HAS_AVX2
49#endif
50
51#if defined(__AVX512F__)
52#define LIBC_TARGET_CPU_HAS_AVX512F
53#endif
54
55#if defined(__AVX512BW__)
56#define LIBC_TARGET_CPU_HAS_AVX512BW
57#endif
58
59#if defined(__ARM_FP)
60#if (__ARM_FP & 0x2)
61#define LIBC_TARGET_CPU_HAS_ARM_FPU_HALF
62#define LIBC_TARGET_CPU_HAS_FPU_HALF
63#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_HALF
64#if (__ARM_FP & 0x4)
65#define LIBC_TARGET_CPU_HAS_ARM_FPU_FLOAT
66#define LIBC_TARGET_CPU_HAS_FPU_FLOAT
67#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_FLOAT
68#if (__ARM_FP & 0x8)
69#define LIBC_TARGET_CPU_HAS_ARM_FPU_DOUBLE
70#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE
71#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_DOUBLE
72#endif // __ARM_FP
73
74#if defined(__ARM_NEON)
75#define LIBC_TARGET_CPU_HAS_ARM_NEON
76#endif
77
78#if defined(__riscv_flen)
79// https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc
80#if defined(__riscv_zfhmin)
81#define LIBC_TARGET_CPU_HAS_RISCV_FPU_HALF
82#define LIBC_TARGET_CPU_HAS_FPU_HALF
83#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_HALF
84#if (__riscv_flen >= 32)
85#define LIBC_TARGET_CPU_HAS_RISCV_FPU_FLOAT
86#define LIBC_TARGET_CPU_HAS_FPU_FLOAT
87#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_FLOAT
88#if (__riscv_flen >= 64)
89#define LIBC_TARGET_CPU_HAS_RISCV_FPU_DOUBLE
90#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE
91#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_DOUBLE
92#endif // __riscv_flen
93
94#if defined(__NVPTX__) || defined(__AMDGPU__)
95#define LIBC_TARGET_CPU_HAS_FPU_FLOAT
96#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE
97#endif
98
99#if defined(__ARM_FEATURE_FMA) || (defined(__AVX2__) && defined(__FMA__)) || \
100 defined(__NVPTX__) || defined(__AMDGPU__) || defined(__riscv_flen)
101#define LIBC_TARGET_CPU_HAS_FMA
102// Provide a more fine-grained control of FMA instruction for ARM targets.
103#if defined(LIBC_TARGET_CPU_HAS_FPU_HALF)
104#define LIBC_TARGET_CPU_HAS_FMA_HALF
105#endif // LIBC_TARGET_CPU_HAS_FMA_HALF
106#if defined(LIBC_TARGET_CPU_HAS_FPU_FLOAT)
107#define LIBC_TARGET_CPU_HAS_FMA_FLOAT
108#endif // LIBC_TARGET_CPU_HAS_FMA_FLOAT
109#if defined(LIBC_TARGET_CPU_HAS_FPU_DOUBLE)
110#define LIBC_TARGET_CPU_HAS_FMA_DOUBLE
111#endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE
112#endif
113
114#if defined(LIBC_TARGET_ARCH_IS_AARCH64) || \
115 (defined(LIBC_TARGET_ARCH_IS_X86_64) && \
116 defined(LIBC_TARGET_CPU_HAS_SSE4_2))
117#define LIBC_TARGET_CPU_HAS_NEAREST_INT
118#endif
119
120#if defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_GPU)
121#define LIBC_TARGET_CPU_HAS_FAST_FLOAT16_OPS
122#endif
123
124#endif // LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H
125