1//===- Chunks.cpp ---------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "Chunks.h"
10#include "COFFLinkerContext.h"
11#include "InputFiles.h"
12#include "SymbolTable.h"
13#include "Symbols.h"
14#include "Writer.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/Twine.h"
18#include "llvm/BinaryFormat/COFF.h"
19#include "llvm/Object/COFF.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/Endian.h"
22#include "llvm/Support/raw_ostream.h"
23#include <algorithm>
24#include <iterator>
25
26using namespace llvm;
27using namespace llvm::object;
28using namespace llvm::support;
29using namespace llvm::support::endian;
30using namespace llvm::COFF;
31using llvm::support::ulittle32_t;
32
33namespace lld::coff {
34
35SectionChunk::SectionChunk(ObjFile *f, const coff_section *h, Kind k)
36 : Chunk(k), file(f), header(h), repl(this) {
37 // Initialize relocs.
38 if (file)
39 setRelocs(file->getCOFFObj()->getRelocations(Sec: header));
40
41 // Initialize sectionName.
42 StringRef sectionName;
43 if (file) {
44 if (Expected<StringRef> e = file->getCOFFObj()->getSectionName(Sec: header))
45 sectionName = *e;
46 }
47 sectionNameData = sectionName.data();
48 sectionNameSize = sectionName.size();
49
50 setAlignment(header->getAlignment());
51
52 hasData = !(header->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA);
53
54 // If linker GC is disabled, every chunk starts out alive. If linker GC is
55 // enabled, treat non-comdat sections as roots. Generally optimized object
56 // files will be built with -ffunction-sections or /Gy, so most things worth
57 // stripping will be in a comdat.
58 if (file)
59 live = !file->symtab.ctx.config.doGC || !isCOMDAT();
60 else
61 live = true;
62}
63
64MachineTypes SectionChunk::getMachine() const {
65 MachineTypes machine = file->getMachineType();
66 // On ARM64EC, the IMAGE_SCN_GPREL flag is repurposed to indicate that section
67 // code is x86_64. This enables embedding x86_64 code within ARM64EC object
68 // files. MSVC uses this for export thunks in .exp files.
69 if (isArm64EC(Machine: machine) && (header->Characteristics & IMAGE_SCN_GPREL))
70 machine = AMD64;
71 return machine;
72}
73
74// SectionChunk is one of the most frequently allocated classes, so it is
75// important to keep it as compact as possible. As of this writing, the number
76// below is the size of this class on x64 platforms.
77static_assert(sizeof(SectionChunk) <= 88, "SectionChunk grew unexpectedly");
78
79static void add16(uint8_t *p, int16_t v) { write16le(P: p, V: read16le(P: p) + v); }
80static void add32(uint8_t *p, int32_t v) { write32le(P: p, V: read32le(P: p) + v); }
81static void add64(uint8_t *p, int64_t v) { write64le(P: p, V: read64le(P: p) + v); }
82static void or16(uint8_t *p, uint16_t v) { write16le(P: p, V: read16le(P: p) | v); }
83static void or32(uint8_t *p, uint32_t v) { write32le(P: p, V: read32le(P: p) | v); }
84
85// Verify that given sections are appropriate targets for SECREL
86// relocations. This check is relaxed because unfortunately debug
87// sections have section-relative relocations against absolute symbols.
88static bool checkSecRel(const SectionChunk *sec, OutputSection *os) {
89 if (os)
90 return true;
91 if (sec->isCodeView())
92 return false;
93 error(msg: "SECREL relocation cannot be applied to absolute symbols");
94 return false;
95}
96
97static void applySecRel(const SectionChunk *sec, uint8_t *off,
98 OutputSection *os, uint64_t s) {
99 if (!checkSecRel(sec, os))
100 return;
101 uint64_t secRel = s - os->getRVA();
102 if (secRel > UINT32_MAX) {
103 error(msg: "overflow in SECREL relocation in section: " + sec->getSectionName());
104 return;
105 }
106 add32(p: off, v: secRel);
107}
108
109static void applySecIdx(uint8_t *off, OutputSection *os,
110 unsigned numOutputSections) {
111 // numOutputSections is the largest valid section index. Make sure that
112 // it fits in 16 bits.
113 assert(numOutputSections <= 0xffff && "size of outputSections is too big");
114
115 // Absolute symbol doesn't have section index, but section index relocation
116 // against absolute symbol should be resolved to one plus the last output
117 // section index. This is required for compatibility with MSVC.
118 if (os)
119 add16(p: off, v: os->sectionIndex);
120 else
121 add16(p: off, v: numOutputSections + 1);
122}
123
124void SectionChunk::applyRelX64(uint8_t *off, uint16_t type, OutputSection *os,
125 uint64_t s, uint64_t p,
126 uint64_t imageBase) const {
127 switch (type) {
128 case IMAGE_REL_AMD64_ADDR32:
129 add32(p: off, v: s + imageBase);
130 break;
131 case IMAGE_REL_AMD64_ADDR64:
132 add64(p: off, v: s + imageBase);
133 break;
134 case IMAGE_REL_AMD64_ADDR32NB: add32(p: off, v: s); break;
135 case IMAGE_REL_AMD64_REL32: add32(p: off, v: s - p - 4); break;
136 case IMAGE_REL_AMD64_REL32_1: add32(p: off, v: s - p - 5); break;
137 case IMAGE_REL_AMD64_REL32_2: add32(p: off, v: s - p - 6); break;
138 case IMAGE_REL_AMD64_REL32_3: add32(p: off, v: s - p - 7); break;
139 case IMAGE_REL_AMD64_REL32_4: add32(p: off, v: s - p - 8); break;
140 case IMAGE_REL_AMD64_REL32_5: add32(p: off, v: s - p - 9); break;
141 case IMAGE_REL_AMD64_SECTION:
142 applySecIdx(off, os, numOutputSections: file->symtab.ctx.outputSections.size());
143 break;
144 case IMAGE_REL_AMD64_SECREL: applySecRel(sec: this, off, os, s); break;
145 default:
146 error(msg: "unsupported relocation type 0x" + Twine::utohexstr(Val: type) + " in " +
147 toString(file));
148 }
149}
150
151void SectionChunk::applyRelX86(uint8_t *off, uint16_t type, OutputSection *os,
152 uint64_t s, uint64_t p,
153 uint64_t imageBase) const {
154 switch (type) {
155 case IMAGE_REL_I386_ABSOLUTE: break;
156 case IMAGE_REL_I386_DIR32:
157 add32(p: off, v: s + imageBase);
158 break;
159 case IMAGE_REL_I386_DIR32NB: add32(p: off, v: s); break;
160 case IMAGE_REL_I386_REL32: add32(p: off, v: s - p - 4); break;
161 case IMAGE_REL_I386_SECTION:
162 applySecIdx(off, os, numOutputSections: file->symtab.ctx.outputSections.size());
163 break;
164 case IMAGE_REL_I386_SECREL: applySecRel(sec: this, off, os, s); break;
165 default:
166 error(msg: "unsupported relocation type 0x" + Twine::utohexstr(Val: type) + " in " +
167 toString(file));
168 }
169}
170
171static void applyMOV(uint8_t *off, uint16_t v) {
172 write16le(P: off, V: (read16le(P: off) & 0xfbf0) | ((v & 0x800) >> 1) | ((v >> 12) & 0xf));
173 write16le(P: off + 2, V: (read16le(P: off + 2) & 0x8f00) | ((v & 0x700) << 4) | (v & 0xff));
174}
175
176static uint16_t readMOV(uint8_t *off, bool movt) {
177 uint16_t op1 = read16le(P: off);
178 if ((op1 & 0xfbf0) != (movt ? 0xf2c0 : 0xf240))
179 error(msg: "unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
180 " instruction in MOV32T relocation");
181 uint16_t op2 = read16le(P: off + 2);
182 if ((op2 & 0x8000) != 0)
183 error(msg: "unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
184 " instruction in MOV32T relocation");
185 return (op2 & 0x00ff) | ((op2 >> 4) & 0x0700) | ((op1 << 1) & 0x0800) |
186 ((op1 & 0x000f) << 12);
187}
188
189void applyMOV32T(uint8_t *off, uint32_t v) {
190 uint16_t immW = readMOV(off, movt: false); // read MOVW operand
191 uint16_t immT = readMOV(off: off + 4, movt: true); // read MOVT operand
192 uint32_t imm = immW | (immT << 16);
193 v += imm; // add the immediate offset
194 applyMOV(off, v); // set MOVW operand
195 applyMOV(off: off + 4, v: v >> 16); // set MOVT operand
196}
197
198static void applyBranch20T(uint8_t *off, int32_t v) {
199 if (!isInt<21>(x: v))
200 error(msg: "relocation out of range");
201 uint32_t s = v < 0 ? 1 : 0;
202 uint32_t j1 = (v >> 19) & 1;
203 uint32_t j2 = (v >> 18) & 1;
204 or16(p: off, v: (s << 10) | ((v >> 12) & 0x3f));
205 or16(p: off + 2, v: (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
206}
207
208void applyBranch24T(uint8_t *off, int32_t v) {
209 if (!isInt<25>(x: v))
210 error(msg: "relocation out of range");
211 uint32_t s = v < 0 ? 1 : 0;
212 uint32_t j1 = ((~v >> 23) & 1) ^ s;
213 uint32_t j2 = ((~v >> 22) & 1) ^ s;
214 or16(p: off, v: (s << 10) | ((v >> 12) & 0x3ff));
215 // Clear out the J1 and J2 bits which may be set.
216 write16le(P: off + 2, V: (read16le(P: off + 2) & 0xd000) | (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
217}
218
219void SectionChunk::applyRelARM(uint8_t *off, uint16_t type, OutputSection *os,
220 uint64_t s, uint64_t p,
221 uint64_t imageBase) const {
222 // Pointer to thumb code must have the LSB set.
223 uint64_t sx = s;
224 if (os && (os->header.Characteristics & IMAGE_SCN_MEM_EXECUTE))
225 sx |= 1;
226 switch (type) {
227 case IMAGE_REL_ARM_ADDR32:
228 add32(p: off, v: sx + imageBase);
229 break;
230 case IMAGE_REL_ARM_ADDR32NB: add32(p: off, v: sx); break;
231 case IMAGE_REL_ARM_MOV32T:
232 applyMOV32T(off, v: sx + imageBase);
233 break;
234 case IMAGE_REL_ARM_BRANCH20T: applyBranch20T(off, v: sx - p - 4); break;
235 case IMAGE_REL_ARM_BRANCH24T: applyBranch24T(off, v: sx - p - 4); break;
236 case IMAGE_REL_ARM_BLX23T: applyBranch24T(off, v: sx - p - 4); break;
237 case IMAGE_REL_ARM_SECTION:
238 applySecIdx(off, os, numOutputSections: file->symtab.ctx.outputSections.size());
239 break;
240 case IMAGE_REL_ARM_SECREL: applySecRel(sec: this, off, os, s); break;
241 case IMAGE_REL_ARM_REL32: add32(p: off, v: sx - p - 4); break;
242 default:
243 error(msg: "unsupported relocation type 0x" + Twine::utohexstr(Val: type) + " in " +
244 toString(file));
245 }
246}
247
248// Interpret the existing immediate value as a byte offset to the
249// target symbol, then update the instruction with the immediate as
250// the page offset from the current instruction to the target.
251void applyArm64Addr(uint8_t *off, uint64_t s, uint64_t p, int shift) {
252 uint32_t orig = read32le(P: off);
253 int64_t imm =
254 SignExtend64<21>(x: ((orig >> 29) & 0x3) | ((orig >> 3) & 0x1FFFFC));
255 s += imm;
256 imm = (s >> shift) - (p >> shift);
257 uint32_t immLo = (imm & 0x3) << 29;
258 uint32_t immHi = (imm & 0x1FFFFC) << 3;
259 uint64_t mask = (0x3 << 29) | (0x1FFFFC << 3);
260 write32le(P: off, V: (orig & ~mask) | immLo | immHi);
261}
262
263// Update the immediate field in a AARCH64 ldr, str, and add instruction.
264// Optionally limit the range of the written immediate by one or more bits
265// (rangeLimit).
266void applyArm64Imm(uint8_t *off, uint64_t imm, uint32_t rangeLimit) {
267 uint32_t orig = read32le(P: off);
268 imm += (orig >> 10) & 0xFFF;
269 orig &= ~(0xFFF << 10);
270 write32le(P: off, V: orig | ((imm & (0xFFF >> rangeLimit)) << 10));
271}
272
273// Add the 12 bit page offset to the existing immediate.
274// Ldr/str instructions store the opcode immediate scaled
275// by the load/store size (giving a larger range for larger
276// loads/stores). The immediate is always (both before and after
277// fixing up the relocation) stored scaled similarly.
278// Even if larger loads/stores have a larger range, limit the
279// effective offset to 12 bit, since it is intended to be a
280// page offset.
281static void applyArm64Ldr(uint8_t *off, uint64_t imm) {
282 uint32_t orig = read32le(P: off);
283 uint32_t size = orig >> 30;
284 // 0x04000000 indicates SIMD/FP registers
285 // 0x00800000 indicates 128 bit
286 if ((orig & 0x4800000) == 0x4800000)
287 size += 4;
288 if ((imm & ((1 << size) - 1)) != 0)
289 error(msg: "misaligned ldr/str offset");
290 applyArm64Imm(off, imm: imm >> size, rangeLimit: size);
291}
292
293static void applySecRelLow12A(const SectionChunk *sec, uint8_t *off,
294 OutputSection *os, uint64_t s) {
295 if (checkSecRel(sec, os))
296 applyArm64Imm(off, imm: (s - os->getRVA()) & 0xfff, rangeLimit: 0);
297}
298
299static void applySecRelHigh12A(const SectionChunk *sec, uint8_t *off,
300 OutputSection *os, uint64_t s) {
301 if (!checkSecRel(sec, os))
302 return;
303 uint64_t secRel = (s - os->getRVA()) >> 12;
304 if (0xfff < secRel) {
305 error(msg: "overflow in SECREL_HIGH12A relocation in section: " +
306 sec->getSectionName());
307 return;
308 }
309 applyArm64Imm(off, imm: secRel & 0xfff, rangeLimit: 0);
310}
311
312static void applySecRelLdr(const SectionChunk *sec, uint8_t *off,
313 OutputSection *os, uint64_t s) {
314 if (checkSecRel(sec, os))
315 applyArm64Ldr(off, imm: (s - os->getRVA()) & 0xfff);
316}
317
318void applyArm64Branch26(uint8_t *off, int64_t v) {
319 if (!isInt<28>(x: v))
320 error(msg: "relocation out of range");
321 or32(p: off, v: (v & 0x0FFFFFFC) >> 2);
322}
323
324static void applyArm64Branch19(uint8_t *off, int64_t v) {
325 if (!isInt<21>(x: v))
326 error(msg: "relocation out of range");
327 or32(p: off, v: (v & 0x001FFFFC) << 3);
328}
329
330static void applyArm64Branch14(uint8_t *off, int64_t v) {
331 if (!isInt<16>(x: v))
332 error(msg: "relocation out of range");
333 or32(p: off, v: (v & 0x0000FFFC) << 3);
334}
335
336void SectionChunk::applyRelARM64(uint8_t *off, uint16_t type, OutputSection *os,
337 uint64_t s, uint64_t p,
338 uint64_t imageBase) const {
339 switch (type) {
340 case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(off, s, p, shift: 12); break;
341 case IMAGE_REL_ARM64_REL21: applyArm64Addr(off, s, p, shift: 0); break;
342 case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(off, imm: s & 0xfff, rangeLimit: 0); break;
343 case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(off, imm: s & 0xfff); break;
344 case IMAGE_REL_ARM64_BRANCH26: applyArm64Branch26(off, v: s - p); break;
345 case IMAGE_REL_ARM64_BRANCH19: applyArm64Branch19(off, v: s - p); break;
346 case IMAGE_REL_ARM64_BRANCH14: applyArm64Branch14(off, v: s - p); break;
347 case IMAGE_REL_ARM64_ADDR32:
348 add32(p: off, v: s + imageBase);
349 break;
350 case IMAGE_REL_ARM64_ADDR32NB: add32(p: off, v: s); break;
351 case IMAGE_REL_ARM64_ADDR64:
352 add64(p: off, v: s + imageBase);
353 break;
354 case IMAGE_REL_ARM64_SECREL: applySecRel(sec: this, off, os, s); break;
355 case IMAGE_REL_ARM64_SECREL_LOW12A: applySecRelLow12A(sec: this, off, os, s); break;
356 case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelHigh12A(sec: this, off, os, s); break;
357 case IMAGE_REL_ARM64_SECREL_LOW12L: applySecRelLdr(sec: this, off, os, s); break;
358 case IMAGE_REL_ARM64_SECTION:
359 applySecIdx(off, os, numOutputSections: file->symtab.ctx.outputSections.size());
360 break;
361 case IMAGE_REL_ARM64_REL32: add32(p: off, v: s - p - 4); break;
362 default:
363 error(msg: "unsupported relocation type 0x" + Twine::utohexstr(Val: type) + " in " +
364 toString(file));
365 }
366}
367
368static void maybeReportRelocationToDiscarded(const SectionChunk *fromChunk,
369 Defined *sym,
370 const coff_relocation &rel,
371 bool isMinGW) {
372 // Don't report these errors when the relocation comes from a debug info
373 // section or in mingw mode. MinGW mode object files (built by GCC) can
374 // have leftover sections with relocations against discarded comdat
375 // sections. Such sections are left as is, with relocations untouched.
376 if (fromChunk->isCodeView() || fromChunk->isDWARF() || isMinGW)
377 return;
378
379 // Get the name of the symbol. If it's null, it was discarded early, so we
380 // have to go back to the object file.
381 ObjFile *file = fromChunk->file;
382 std::string name;
383 if (sym) {
384 name = toString(ctx: file->symtab.ctx, b&: *sym);
385 } else {
386 COFFSymbolRef coffSym =
387 check(e: file->getCOFFObj()->getSymbol(index: rel.SymbolTableIndex));
388 name = maybeDemangleSymbol(
389 ctx: file->symtab.ctx, symName: check(e: file->getCOFFObj()->getSymbolName(Symbol: coffSym)));
390 }
391
392 std::vector<std::string> symbolLocations =
393 getSymbolLocations(file, symIndex: rel.SymbolTableIndex);
394
395 std::string out;
396 llvm::raw_string_ostream os(out);
397 os << "relocation against symbol in discarded section: " + name;
398 for (const std::string &s : symbolLocations)
399 os << s;
400 error(msg: out);
401}
402
403void SectionChunk::writeTo(uint8_t *buf) const {
404 if (!hasData)
405 return;
406 // Copy section contents from source object file to output file.
407 ArrayRef<uint8_t> a = getContents();
408 if (!a.empty())
409 memcpy(dest: buf, src: a.data(), n: a.size());
410
411 // Apply relocations.
412 size_t inputSize = getSize();
413 for (const coff_relocation &rel : getRelocs()) {
414 // Check for an invalid relocation offset. This check isn't perfect, because
415 // we don't have the relocation size, which is only known after checking the
416 // machine and relocation type. As a result, a relocation may overwrite the
417 // beginning of the following input section.
418 if (rel.VirtualAddress >= inputSize) {
419 error(msg: "relocation points beyond the end of its parent section");
420 continue;
421 }
422
423 applyRelocation(off: buf + rel.VirtualAddress, rel);
424 }
425}
426
427void SectionChunk::applyRelocation(uint8_t *off,
428 const coff_relocation &rel) const {
429 auto *sym = dyn_cast_or_null<Defined>(Val: file->getSymbol(symbolIndex: rel.SymbolTableIndex));
430
431 // Get the output section of the symbol for this relocation. The output
432 // section is needed to compute SECREL and SECTION relocations used in debug
433 // info.
434 Chunk *c = sym ? sym->getChunk() : nullptr;
435 COFFLinkerContext &ctx = file->symtab.ctx;
436 OutputSection *os = c ? ctx.getOutputSection(c) : nullptr;
437
438 // Skip the relocation if it refers to a discarded section, and diagnose it
439 // as an error if appropriate. If a symbol was discarded early, it may be
440 // null. If it was discarded late, the output section will be null, unless
441 // it was an absolute or synthetic symbol.
442 if (!sym ||
443 (!os && !isa<DefinedAbsolute>(Val: sym) && !isa<DefinedSynthetic>(Val: sym))) {
444 maybeReportRelocationToDiscarded(fromChunk: this, sym, rel, isMinGW: ctx.config.mingw);
445 return;
446 }
447
448 uint64_t s = sym->getRVA();
449
450 // Compute the RVA of the relocation for relative relocations.
451 uint64_t p = rva + rel.VirtualAddress;
452 uint64_t imageBase = ctx.config.imageBase;
453 switch (getArch()) {
454 case Triple::x86_64:
455 applyRelX64(off, type: rel.Type, os, s, p, imageBase);
456 break;
457 case Triple::x86:
458 applyRelX86(off, type: rel.Type, os, s, p, imageBase);
459 break;
460 case Triple::thumb:
461 applyRelARM(off, type: rel.Type, os, s, p, imageBase);
462 break;
463 case Triple::aarch64:
464 applyRelARM64(off, type: rel.Type, os, s, p, imageBase);
465 break;
466 default:
467 llvm_unreachable("unknown machine type");
468 }
469}
470
471// Defend against unsorted relocations. This may be overly conservative.
472void SectionChunk::sortRelocations() {
473 auto cmpByVa = [](const coff_relocation &l, const coff_relocation &r) {
474 return l.VirtualAddress < r.VirtualAddress;
475 };
476 if (llvm::is_sorted(Range: getRelocs(), C: cmpByVa))
477 return;
478 warn(msg: "some relocations in " + file->getName() + " are not sorted");
479 MutableArrayRef<coff_relocation> newRelocs(
480 bAlloc().Allocate<coff_relocation>(Num: relocsSize), relocsSize);
481 memcpy(dest: newRelocs.data(), src: relocsData, n: relocsSize * sizeof(coff_relocation));
482 llvm::sort(C&: newRelocs, Comp: cmpByVa);
483 setRelocs(newRelocs);
484}
485
486// Similar to writeTo, but suitable for relocating a subsection of the overall
487// section.
488void SectionChunk::writeAndRelocateSubsection(ArrayRef<uint8_t> sec,
489 ArrayRef<uint8_t> subsec,
490 uint32_t &nextRelocIndex,
491 uint8_t *buf) const {
492 assert(!subsec.empty() && !sec.empty());
493 assert(sec.begin() <= subsec.begin() && subsec.end() <= sec.end() &&
494 "subsection is not part of this section");
495 size_t vaBegin = std::distance(first: sec.begin(), last: subsec.begin());
496 size_t vaEnd = std::distance(first: sec.begin(), last: subsec.end());
497 memcpy(dest: buf, src: subsec.data(), n: subsec.size());
498 for (; nextRelocIndex < relocsSize; ++nextRelocIndex) {
499 const coff_relocation &rel = relocsData[nextRelocIndex];
500 // Only apply relocations that apply to this subsection. These checks
501 // assume that all subsections completely contain their relocations.
502 // Relocations must not straddle the beginning or end of a subsection.
503 if (rel.VirtualAddress < vaBegin)
504 continue;
505 if (rel.VirtualAddress + 1 >= vaEnd)
506 break;
507 applyRelocation(off: &buf[rel.VirtualAddress - vaBegin], rel);
508 }
509}
510
511void SectionChunk::addAssociative(SectionChunk *child) {
512 // Insert the child section into the list of associated children. Keep the
513 // list ordered by section name so that ICF does not depend on section order.
514 assert(child->assocChildren == nullptr &&
515 "associated sections cannot have their own associated children");
516 SectionChunk *prev = this;
517 SectionChunk *next = assocChildren;
518 for (; next != nullptr; prev = next, next = next->assocChildren) {
519 if (next->getSectionName() <= child->getSectionName())
520 break;
521 }
522
523 // Insert child between prev and next.
524 assert(prev->assocChildren == next);
525 prev->assocChildren = child;
526 child->assocChildren = next;
527}
528
529static uint8_t getBaserelType(const coff_relocation &rel,
530 Triple::ArchType arch) {
531 switch (arch) {
532 case Triple::x86_64:
533 if (rel.Type == IMAGE_REL_AMD64_ADDR64)
534 return IMAGE_REL_BASED_DIR64;
535 if (rel.Type == IMAGE_REL_AMD64_ADDR32)
536 return IMAGE_REL_BASED_HIGHLOW;
537 return IMAGE_REL_BASED_ABSOLUTE;
538 case Triple::x86:
539 if (rel.Type == IMAGE_REL_I386_DIR32)
540 return IMAGE_REL_BASED_HIGHLOW;
541 return IMAGE_REL_BASED_ABSOLUTE;
542 case Triple::thumb:
543 if (rel.Type == IMAGE_REL_ARM_ADDR32)
544 return IMAGE_REL_BASED_HIGHLOW;
545 if (rel.Type == IMAGE_REL_ARM_MOV32T)
546 return IMAGE_REL_BASED_ARM_MOV32T;
547 return IMAGE_REL_BASED_ABSOLUTE;
548 case Triple::aarch64:
549 if (rel.Type == IMAGE_REL_ARM64_ADDR64)
550 return IMAGE_REL_BASED_DIR64;
551 return IMAGE_REL_BASED_ABSOLUTE;
552 default:
553 llvm_unreachable("unknown machine type");
554 }
555}
556
557// Windows-specific.
558// Collect all locations that contain absolute addresses, which need to be
559// fixed by the loader if load-time relocation is needed.
560// Only called when base relocation is enabled.
561void SectionChunk::getBaserels(std::vector<Baserel> *res) {
562 for (const coff_relocation &rel : getRelocs()) {
563 uint8_t ty = getBaserelType(rel, arch: getArch());
564 if (ty == IMAGE_REL_BASED_ABSOLUTE)
565 continue;
566 Symbol *target = file->getSymbol(symbolIndex: rel.SymbolTableIndex);
567 if (!isa_and_nonnull<Defined>(Val: target) || isa<DefinedAbsolute>(Val: target))
568 continue;
569 res->emplace_back(args: rva + rel.VirtualAddress, args&: ty);
570 }
571
572 // Insert a 64-bit relocation for CHPEMetadataPointer in the native load
573 // config of a hybrid ARM64X image. Its value will be set in prepareLoadConfig
574 // to match the value in the EC load config, which is expected to be
575 // a relocatable pointer to the __chpe_metadata symbol.
576 COFFLinkerContext &ctx = file->symtab.ctx;
577 if (ctx.config.machine == ARM64X && ctx.hybridSymtab->loadConfigSym &&
578 ctx.hybridSymtab->loadConfigSym->getChunk() == this &&
579 ctx.symtab.loadConfigSym &&
580 ctx.hybridSymtab->loadConfigSize >=
581 offsetof(coff_load_configuration64, CHPEMetadataPointer) +
582 sizeof(coff_load_configuration64::CHPEMetadataPointer))
583 res->emplace_back(
584 args: ctx.hybridSymtab->loadConfigSym->getRVA() +
585 offsetof(coff_load_configuration64, CHPEMetadataPointer),
586 args: IMAGE_REL_BASED_DIR64);
587}
588
589// MinGW specific.
590// Check whether a static relocation of type Type can be deferred and
591// handled at runtime as a pseudo relocation (for references to a module
592// local variable, which turned out to actually need to be imported from
593// another DLL) This returns the size the relocation is supposed to update,
594// in bits, or 0 if the relocation cannot be handled as a runtime pseudo
595// relocation.
596static int getRuntimePseudoRelocSize(uint16_t type, Triple::ArchType arch) {
597 // Relocations that either contain an absolute address, or a plain
598 // relative offset, since the runtime pseudo reloc implementation
599 // adds 8/16/32/64 bit values to a memory address.
600 //
601 // Given a pseudo relocation entry,
602 //
603 // typedef struct {
604 // DWORD sym;
605 // DWORD target;
606 // DWORD flags;
607 // } runtime_pseudo_reloc_item_v2;
608 //
609 // the runtime relocation performs this adjustment:
610 // *(base + .target) += *(base + .sym) - (base + .sym)
611 //
612 // This works for both absolute addresses (IMAGE_REL_*_ADDR32/64,
613 // IMAGE_REL_I386_DIR32, where the memory location initially contains
614 // the address of the IAT slot, and for relative addresses (IMAGE_REL*_REL32),
615 // where the memory location originally contains the relative offset to the
616 // IAT slot.
617 //
618 // This requires the target address to be writable, either directly out of
619 // the image, or temporarily changed at runtime with VirtualProtect.
620 // Since this only operates on direct address values, it doesn't work for
621 // ARM/ARM64 relocations, other than the plain ADDR32/ADDR64 relocations.
622 switch (arch) {
623 case Triple::x86_64:
624 switch (type) {
625 case IMAGE_REL_AMD64_ADDR64:
626 return 64;
627 case IMAGE_REL_AMD64_ADDR32:
628 case IMAGE_REL_AMD64_REL32:
629 case IMAGE_REL_AMD64_REL32_1:
630 case IMAGE_REL_AMD64_REL32_2:
631 case IMAGE_REL_AMD64_REL32_3:
632 case IMAGE_REL_AMD64_REL32_4:
633 case IMAGE_REL_AMD64_REL32_5:
634 return 32;
635 default:
636 return 0;
637 }
638 case Triple::x86:
639 switch (type) {
640 case IMAGE_REL_I386_DIR32:
641 case IMAGE_REL_I386_REL32:
642 return 32;
643 default:
644 return 0;
645 }
646 case Triple::thumb:
647 switch (type) {
648 case IMAGE_REL_ARM_ADDR32:
649 return 32;
650 default:
651 return 0;
652 }
653 case Triple::aarch64:
654 switch (type) {
655 case IMAGE_REL_ARM64_ADDR64:
656 return 64;
657 case IMAGE_REL_ARM64_ADDR32:
658 return 32;
659 default:
660 return 0;
661 }
662 default:
663 llvm_unreachable("unknown machine type");
664 }
665}
666
667// MinGW specific.
668// Append information to the provided vector about all relocations that
669// need to be handled at runtime as runtime pseudo relocations (references
670// to a module local variable, which turned out to actually need to be
671// imported from another DLL).
672void SectionChunk::getRuntimePseudoRelocs(
673 std::vector<RuntimePseudoReloc> &res) {
674 for (const coff_relocation &rel : getRelocs()) {
675 auto *target =
676 dyn_cast_or_null<Defined>(Val: file->getSymbol(symbolIndex: rel.SymbolTableIndex));
677 if (!target || !target->isRuntimePseudoReloc)
678 continue;
679 // If the target doesn't have a chunk allocated, it may be a
680 // DefinedImportData symbol which ended up unnecessary after GC.
681 // Normally we wouldn't eliminate section chunks that are referenced, but
682 // references within DWARF sections don't count for keeping section chunks
683 // alive. Thus such dangling references in DWARF sections are expected.
684 if (!target->getChunk())
685 continue;
686 int sizeInBits = getRuntimePseudoRelocSize(type: rel.Type, arch: getArch());
687 if (sizeInBits == 0) {
688 error(msg: "unable to automatically import from " + target->getName() +
689 " with relocation type " +
690 file->getCOFFObj()->getRelocationTypeName(Type: rel.Type) + " in " +
691 toString(file));
692 continue;
693 }
694 int addressSizeInBits = file->symtab.ctx.config.is64() ? 64 : 32;
695 if (sizeInBits < addressSizeInBits) {
696 warn(msg: "runtime pseudo relocation in " + toString(file) + " against " +
697 "symbol " + target->getName() + " is too narrow (only " +
698 Twine(sizeInBits) + " bits wide); this can fail at runtime " +
699 "depending on memory layout");
700 }
701 // sizeInBits is used to initialize the Flags field; currently no
702 // other flags are defined.
703 res.emplace_back(args&: target, args: this, args: rel.VirtualAddress, args&: sizeInBits);
704 }
705}
706
707bool SectionChunk::isCOMDAT() const {
708 return header->Characteristics & IMAGE_SCN_LNK_COMDAT;
709}
710
711void SectionChunk::printDiscardedMessage() const {
712 // Removed by dead-stripping. If it's removed by ICF, ICF already
713 // printed out the name, so don't repeat that here.
714 if (sym && this == repl)
715 log(msg: "Discarded " + sym->getName());
716}
717
718StringRef SectionChunk::getDebugName() const {
719 if (sym)
720 return sym->getName();
721 return "";
722}
723
724ArrayRef<uint8_t> SectionChunk::getContents() const {
725 ArrayRef<uint8_t> a;
726 cantFail(Err: file->getCOFFObj()->getSectionContents(Sec: header, Res&: a));
727 return a;
728}
729
730ArrayRef<uint8_t> SectionChunk::consumeDebugMagic() {
731 assert(isCodeView());
732 return consumeDebugMagic(data: getContents(), sectionName: getSectionName());
733}
734
735ArrayRef<uint8_t> SectionChunk::consumeDebugMagic(ArrayRef<uint8_t> data,
736 StringRef sectionName) {
737 if (data.empty())
738 return {};
739
740 // First 4 bytes are section magic.
741 if (data.size() < 4)
742 fatal(msg: "the section is too short: " + sectionName);
743
744 if (!sectionName.starts_with(Prefix: ".debug$"))
745 fatal(msg: "invalid section: " + sectionName);
746
747 uint32_t magic = support::endian::read32le(P: data.data());
748 uint32_t expectedMagic = sectionName == ".debug$H"
749 ? DEBUG_HASHES_SECTION_MAGIC
750 : DEBUG_SECTION_MAGIC;
751 if (magic != expectedMagic) {
752 warn(msg: "ignoring section " + sectionName + " with unrecognized magic 0x" +
753 utohexstr(X: magic));
754 return {};
755 }
756 return data.slice(N: 4);
757}
758
759SectionChunk *SectionChunk::findByName(ArrayRef<SectionChunk *> sections,
760 StringRef name) {
761 for (SectionChunk *c : sections)
762 if (c->getSectionName() == name)
763 return c;
764 return nullptr;
765}
766
767void SectionChunk::replace(SectionChunk *other) {
768 p2Align = std::max(a: p2Align, b: other->p2Align);
769 other->repl = repl;
770 other->live = false;
771}
772
773uint32_t SectionChunk::getSectionNumber() const {
774 DataRefImpl r;
775 r.p = reinterpret_cast<uintptr_t>(header);
776 SectionRef s(r, file->getCOFFObj());
777 return s.getIndex() + 1;
778}
779
780CommonChunk::CommonChunk(const COFFSymbolRef s) : live(false), sym(s) {
781 // The value of a common symbol is its size. Align all common symbols smaller
782 // than 32 bytes naturally, i.e. round the size up to the next power of two.
783 // This is what MSVC link.exe does.
784 setAlignment(std::min(a: 32U, b: uint32_t(PowerOf2Ceil(A: sym.getValue()))));
785 hasData = false;
786}
787
788uint32_t CommonChunk::getOutputCharacteristics() const {
789 return IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_MEM_READ |
790 IMAGE_SCN_MEM_WRITE;
791}
792
793void StringChunk::writeTo(uint8_t *buf) const {
794 memcpy(dest: buf, src: str.data(), n: str.size());
795 buf[str.size()] = '\0';
796}
797
798ImportThunkChunk::ImportThunkChunk(COFFLinkerContext &ctx, Defined *s)
799 : NonSectionCodeChunk(ImportThunkKind), live(!ctx.config.doGC),
800 impSymbol(s), ctx(ctx) {}
801
802ImportThunkChunkX64::ImportThunkChunkX64(COFFLinkerContext &ctx, Defined *s)
803 : ImportThunkChunk(ctx, s) {
804 // Intel Optimization Manual says that all branch targets
805 // should be 16-byte aligned. MSVC linker does this too.
806 setAlignment(16);
807}
808
809void ImportThunkChunkX64::writeTo(uint8_t *buf) const {
810 memcpy(dest: buf, src: importThunkX86, n: sizeof(importThunkX86));
811 // The first two bytes is a JMP instruction. Fill its operand.
812 write32le(P: buf + 2, V: impSymbol->getRVA() - rva - getSize());
813}
814
815void ImportThunkChunkX86::getBaserels(std::vector<Baserel> *res) {
816 res->emplace_back(args: getRVA() + 2, args&: ctx.config.machine);
817}
818
819void ImportThunkChunkX86::writeTo(uint8_t *buf) const {
820 memcpy(dest: buf, src: importThunkX86, n: sizeof(importThunkX86));
821 // The first two bytes is a JMP instruction. Fill its operand.
822 write32le(P: buf + 2, V: impSymbol->getRVA() + ctx.config.imageBase);
823}
824
825void ImportThunkChunkARM::getBaserels(std::vector<Baserel> *res) {
826 res->emplace_back(args: getRVA(), args: IMAGE_REL_BASED_ARM_MOV32T);
827}
828
829void ImportThunkChunkARM::writeTo(uint8_t *buf) const {
830 memcpy(dest: buf, src: importThunkARM, n: sizeof(importThunkARM));
831 // Fix mov.w and mov.t operands.
832 applyMOV32T(off: buf, v: impSymbol->getRVA() + ctx.config.imageBase);
833}
834
835void ImportThunkChunkARM64::writeTo(uint8_t *buf) const {
836 int64_t off = impSymbol->getRVA() & 0xfff;
837 memcpy(dest: buf, src: importThunkARM64, n: sizeof(importThunkARM64));
838 applyArm64Addr(off: buf, s: impSymbol->getRVA(), p: rva, shift: 12);
839 applyArm64Ldr(off: buf + 4, imm: off);
840}
841
842// A Thumb2, PIC, non-interworking range extension thunk.
843const uint8_t armThunk[] = {
844 0x40, 0xf2, 0x00, 0x0c, // P: movw ip,:lower16:S - (P + (L1-P) + 4)
845 0xc0, 0xf2, 0x00, 0x0c, // movt ip,:upper16:S - (P + (L1-P) + 4)
846 0xe7, 0x44, // L1: add pc, ip
847};
848
849size_t RangeExtensionThunkARM::getSize() const {
850 assert(ctx.config.machine == ARMNT);
851 (void)&ctx;
852 return sizeof(armThunk);
853}
854
855void RangeExtensionThunkARM::writeTo(uint8_t *buf) const {
856 assert(ctx.config.machine == ARMNT);
857 uint64_t offset = target->getRVA() - rva - 12;
858 memcpy(dest: buf, src: armThunk, n: sizeof(armThunk));
859 applyMOV32T(off: buf, v: uint32_t(offset));
860}
861
862// A position independent ARM64 adrp+add thunk, with a maximum range of
863// +/- 4 GB, which is enough for any PE-COFF.
864const uint8_t arm64Thunk[] = {
865 0x10, 0x00, 0x00, 0x90, // adrp x16, Dest
866 0x10, 0x02, 0x00, 0x91, // add x16, x16, :lo12:Dest
867 0x00, 0x02, 0x1f, 0xd6, // br x16
868};
869
870size_t RangeExtensionThunkARM64::getSize() const { return sizeof(arm64Thunk); }
871
872void RangeExtensionThunkARM64::writeTo(uint8_t *buf) const {
873 memcpy(dest: buf, src: arm64Thunk, n: sizeof(arm64Thunk));
874 applyArm64Addr(off: buf + 0, s: target->getRVA(), p: rva, shift: 12);
875 applyArm64Imm(off: buf + 4, imm: target->getRVA() & 0xfff, rangeLimit: 0);
876}
877
878void SameAddressThunkARM64EC::setDynamicRelocs(COFFLinkerContext &ctx) const {
879 // Add ARM64X relocations replacing adrp/add instructions with a version using
880 // the hybrid target.
881 RangeExtensionThunkARM64 hybridView(ARM64EC, hybridTarget);
882 uint8_t buf[sizeof(arm64Thunk)];
883 hybridView.setRVA(rva);
884 hybridView.writeTo(buf);
885 uint32_t addrp = *reinterpret_cast<ulittle32_t *>(buf);
886 uint32_t add = *reinterpret_cast<ulittle32_t *>(buf + sizeof(uint32_t));
887 ctx.dynamicRelocs->set(offset: this, value: addrp);
888 ctx.dynamicRelocs->set(offset: Arm64XRelocVal(this, sizeof(uint32_t)), value: add);
889}
890
891LocalImportChunk::LocalImportChunk(COFFLinkerContext &c, Defined *s)
892 : sym(s), ctx(c) {
893 setAlignment(ctx.config.wordsize);
894}
895
896void LocalImportChunk::getBaserels(std::vector<Baserel> *res) {
897 res->emplace_back(args: getRVA(), args&: ctx.config.machine);
898}
899
900size_t LocalImportChunk::getSize() const { return ctx.config.wordsize; }
901
902void LocalImportChunk::writeTo(uint8_t *buf) const {
903 if (ctx.config.is64()) {
904 write64le(P: buf, V: sym->getRVA() + ctx.config.imageBase);
905 } else {
906 write32le(P: buf, V: sym->getRVA() + ctx.config.imageBase);
907 }
908}
909
910void RVATableChunk::writeTo(uint8_t *buf) const {
911 ulittle32_t *begin = reinterpret_cast<ulittle32_t *>(buf);
912 size_t cnt = 0;
913 for (const ChunkAndOffset &co : syms)
914 begin[cnt++] = co.inputChunk->getRVA() + co.offset;
915 llvm::sort(Start: begin, End: begin + cnt);
916 assert(std::unique(begin, begin + cnt) == begin + cnt &&
917 "RVA tables should be de-duplicated");
918}
919
920void RVAFlagTableChunk::writeTo(uint8_t *buf) const {
921 struct RVAFlag {
922 ulittle32_t rva;
923 uint8_t flag;
924 };
925 auto flags =
926 MutableArrayRef(reinterpret_cast<RVAFlag *>(buf), syms.size());
927 for (auto t : zip(t: syms, u&: flags)) {
928 const auto &sym = std::get<0>(t&: t);
929 auto &flag = std::get<1>(t&: t);
930 flag.rva = sym.inputChunk->getRVA() + sym.offset;
931 flag.flag = 0;
932 }
933 llvm::sort(C&: flags,
934 Comp: [](const RVAFlag &a, const RVAFlag &b) { return a.rva < b.rva; });
935 assert(llvm::unique(flags, [](const RVAFlag &a,
936 const RVAFlag &b) { return a.rva == b.rva; }) ==
937 flags.end() &&
938 "RVA tables should be de-duplicated");
939}
940
941size_t ECCodeMapChunk::getSize() const {
942 return map.size() * sizeof(chpe_range_entry);
943}
944
945void ECCodeMapChunk::writeTo(uint8_t *buf) const {
946 auto table = reinterpret_cast<chpe_range_entry *>(buf);
947 for (uint32_t i = 0; i < map.size(); i++) {
948 const ECCodeMapEntry &entry = map[i];
949 uint32_t start = entry.first->getRVA() & ~0xfff;
950 table[i].StartOffset = start | entry.type;
951 table[i].Length = entry.last->getRVA() + entry.last->getSize() - start;
952 }
953}
954
955// MinGW specific, for the "automatic import of variables from DLLs" feature.
956size_t PseudoRelocTableChunk::getSize() const {
957 if (relocs.empty())
958 return 0;
959 return 12 + 12 * relocs.size();
960}
961
962// MinGW specific.
963void PseudoRelocTableChunk::writeTo(uint8_t *buf) const {
964 if (relocs.empty())
965 return;
966
967 ulittle32_t *table = reinterpret_cast<ulittle32_t *>(buf);
968 // This is the list header, to signal the runtime pseudo relocation v2
969 // format.
970 table[0] = 0;
971 table[1] = 0;
972 table[2] = 1;
973
974 size_t idx = 3;
975 for (const RuntimePseudoReloc &rpr : relocs) {
976 table[idx + 0] = rpr.sym->getRVA();
977 table[idx + 1] = rpr.target->getRVA() + rpr.targetOffset;
978 table[idx + 2] = rpr.flags;
979 idx += 3;
980 }
981}
982
983// Windows-specific. This class represents a block in .reloc section.
984// The format is described here.
985//
986// On Windows, each DLL is linked against a fixed base address and
987// usually loaded to that address. However, if there's already another
988// DLL that overlaps, the loader has to relocate it. To do that, DLLs
989// contain .reloc sections which contain offsets that need to be fixed
990// up at runtime. If the loader finds that a DLL cannot be loaded to its
991// desired base address, it loads it to somewhere else, and add <actual
992// base address> - <desired base address> to each offset that is
993// specified by the .reloc section. In ELF terms, .reloc sections
994// contain relative relocations in REL format (as opposed to RELA.)
995//
996// This already significantly reduces the size of relocations compared
997// to ELF .rel.dyn, but Windows does more to reduce it (probably because
998// it was invented for PCs in the late '80s or early '90s.) Offsets in
999// .reloc are grouped by page where the page size is 12 bits, and
1000// offsets sharing the same page address are stored consecutively to
1001// represent them with less space. This is very similar to the page
1002// table which is grouped by (multiple stages of) pages.
1003//
1004// For example, let's say we have 0x00030, 0x00500, 0x00700, 0x00A00,
1005// 0x20004, and 0x20008 in a .reloc section for x64. The uppermost 4
1006// bits have a type IMAGE_REL_BASED_DIR64 or 0xA. In the section, they
1007// are represented like this:
1008//
1009// 0x00000 -- page address (4 bytes)
1010// 16 -- size of this block (4 bytes)
1011// 0xA030 -- entries (2 bytes each)
1012// 0xA500
1013// 0xA700
1014// 0xAA00
1015// 0x20000 -- page address (4 bytes)
1016// 12 -- size of this block (4 bytes)
1017// 0xA004 -- entries (2 bytes each)
1018// 0xA008
1019//
1020// Usually we have a lot of relocations for each page, so the number of
1021// bytes for one .reloc entry is close to 2 bytes on average.
1022BaserelChunk::BaserelChunk(uint32_t page, Baserel *begin, Baserel *end) {
1023 // Block header consists of 4 byte page RVA and 4 byte block size.
1024 // Each entry is 2 byte. Last entry may be padding.
1025 data.resize(new_size: alignTo(Value: (end - begin) * 2 + 8, Align: 4));
1026 uint8_t *p = data.data();
1027 write32le(P: p, V: page);
1028 write32le(P: p + 4, V: data.size());
1029 p += 8;
1030 for (Baserel *i = begin; i != end; ++i) {
1031 write16le(P: p, V: (i->type << 12) | (i->rva - page));
1032 p += 2;
1033 }
1034}
1035
1036void BaserelChunk::writeTo(uint8_t *buf) const {
1037 memcpy(dest: buf, src: data.data(), n: data.size());
1038}
1039
1040uint8_t Baserel::getDefaultType(llvm::COFF::MachineTypes machine) {
1041 return is64Bit(Machine: machine) ? IMAGE_REL_BASED_DIR64 : IMAGE_REL_BASED_HIGHLOW;
1042}
1043
1044MergeChunk::MergeChunk(uint32_t alignment)
1045 : builder(StringTableBuilder::RAW, llvm::Align(alignment)) {
1046 setAlignment(alignment);
1047}
1048
1049void MergeChunk::addSection(COFFLinkerContext &ctx, SectionChunk *c) {
1050 assert(isPowerOf2_32(c->getAlignment()));
1051 uint8_t p2Align = llvm::Log2_32(Value: c->getAlignment());
1052 assert(p2Align < std::size(ctx.mergeChunkInstances));
1053 auto *&mc = ctx.mergeChunkInstances[p2Align];
1054 if (!mc)
1055 mc = make<MergeChunk>(args: c->getAlignment());
1056 mc->sections.push_back(x: c);
1057}
1058
1059void MergeChunk::finalizeContents() {
1060 assert(!finalized && "should only finalize once");
1061 for (SectionChunk *c : sections)
1062 if (c->live)
1063 builder.add(S: toStringRef(Input: c->getContents()));
1064 builder.finalize();
1065 finalized = true;
1066}
1067
1068void MergeChunk::assignSubsectionRVAs() {
1069 for (SectionChunk *c : sections) {
1070 if (!c->live)
1071 continue;
1072 size_t off = builder.getOffset(S: toStringRef(Input: c->getContents()));
1073 c->setRVA(rva + off);
1074 }
1075}
1076
1077uint32_t MergeChunk::getOutputCharacteristics() const {
1078 return IMAGE_SCN_MEM_READ | IMAGE_SCN_CNT_INITIALIZED_DATA;
1079}
1080
1081size_t MergeChunk::getSize() const {
1082 return builder.getSize();
1083}
1084
1085void MergeChunk::writeTo(uint8_t *buf) const {
1086 builder.write(Buf: buf);
1087}
1088
1089// MinGW specific.
1090size_t AbsolutePointerChunk::getSize() const {
1091 return symtab.ctx.config.wordsize;
1092}
1093
1094void AbsolutePointerChunk::writeTo(uint8_t *buf) const {
1095 if (symtab.ctx.config.is64()) {
1096 write64le(P: buf, V: value);
1097 } else {
1098 write32le(P: buf, V: value);
1099 }
1100}
1101
1102MachineTypes AbsolutePointerChunk::getMachine() const { return symtab.machine; }
1103
1104void ECExportThunkChunk::writeTo(uint8_t *buf) const {
1105 memcpy(dest: buf, src: ECExportThunkCode, n: sizeof(ECExportThunkCode));
1106 write32le(P: buf + 10, V: target->getRVA() - rva - 14);
1107}
1108
1109size_t CHPECodeRangesChunk::getSize() const {
1110 return exportThunks.size() * sizeof(chpe_code_range_entry);
1111}
1112
1113void CHPECodeRangesChunk::writeTo(uint8_t *buf) const {
1114 auto ranges = reinterpret_cast<chpe_code_range_entry *>(buf);
1115
1116 for (uint32_t i = 0; i < exportThunks.size(); i++) {
1117 Chunk *thunk = exportThunks[i].first;
1118 uint32_t start = thunk->getRVA();
1119 ranges[i].StartRva = start;
1120 ranges[i].EndRva = start + thunk->getSize();
1121 ranges[i].EntryPoint = start;
1122 }
1123}
1124
1125size_t CHPERedirectionChunk::getSize() const {
1126 // Add an extra +1 for a terminator entry.
1127 return (exportThunks.size() + 1) * sizeof(chpe_redirection_entry);
1128}
1129
1130void CHPERedirectionChunk::writeTo(uint8_t *buf) const {
1131 auto entries = reinterpret_cast<chpe_redirection_entry *>(buf);
1132
1133 for (uint32_t i = 0; i < exportThunks.size(); i++) {
1134 entries[i].Source = exportThunks[i].first->getRVA();
1135 entries[i].Destination = exportThunks[i].second->getRVA();
1136 }
1137}
1138
1139ImportThunkChunkARM64EC::ImportThunkChunkARM64EC(ImportFile *file)
1140 : ImportThunkChunk(file->symtab.ctx, file->impSym), file(file) {}
1141
1142size_t ImportThunkChunkARM64EC::getSize() const {
1143 if (!extended)
1144 return sizeof(importThunkARM64EC);
1145 // The last instruction is replaced with an inline range extension thunk.
1146 return sizeof(importThunkARM64EC) + sizeof(arm64Thunk) - sizeof(uint32_t);
1147}
1148
1149void ImportThunkChunkARM64EC::writeTo(uint8_t *buf) const {
1150 memcpy(dest: buf, src: importThunkARM64EC, n: sizeof(importThunkARM64EC));
1151 applyArm64Addr(off: buf, s: file->impSym->getRVA(), p: rva, shift: 12);
1152 applyArm64Ldr(off: buf + 4, imm: file->impSym->getRVA() & 0xfff);
1153
1154 // The exit thunk may be missing. This can happen if the application only
1155 // references a function by its address (in which case the thunk is never
1156 // actually used, but is still required to fill the auxiliary IAT), or in
1157 // cases of hand-written assembly calling an imported ARM64EC function (where
1158 // the exit thunk is ignored by __icall_helper_arm64ec). In such cases, MSVC
1159 // link.exe uses 0 as the RVA.
1160 uint32_t exitThunkRVA = exitThunk ? exitThunk->getRVA() : 0;
1161 applyArm64Addr(off: buf + 8, s: exitThunkRVA, p: rva + 8, shift: 12);
1162 applyArm64Imm(off: buf + 12, imm: exitThunkRVA & 0xfff, rangeLimit: 0);
1163
1164 Defined *helper = cast<Defined>(Val: file->symtab.ctx.config.arm64ECIcallHelper);
1165 if (extended) {
1166 // Replace last instruction with an inline range extension thunk.
1167 memcpy(dest: buf + 16, src: arm64Thunk, n: sizeof(arm64Thunk));
1168 applyArm64Addr(off: buf + 16, s: helper->getRVA(), p: rva + 16, shift: 12);
1169 applyArm64Imm(off: buf + 20, imm: helper->getRVA() & 0xfff, rangeLimit: 0);
1170 } else {
1171 applyArm64Branch26(off: buf + 16, v: helper->getRVA() - rva - 16);
1172 }
1173}
1174
1175bool ImportThunkChunkARM64EC::verifyRanges() {
1176 if (extended)
1177 return true;
1178 auto helper = cast<Defined>(Val: file->symtab.ctx.config.arm64ECIcallHelper);
1179 return isInt<28>(x: helper->getRVA() - rva - 16);
1180}
1181
1182uint32_t ImportThunkChunkARM64EC::extendRanges() {
1183 if (extended || verifyRanges())
1184 return 0;
1185 extended = true;
1186 // The last instruction is replaced with an inline range extension thunk.
1187 return sizeof(arm64Thunk) - sizeof(uint32_t);
1188}
1189
1190uint64_t Arm64XRelocVal::get() const {
1191 return (sym ? sym->getRVA() : 0) + (chunk ? chunk->getRVA() : 0) + value;
1192}
1193
1194size_t Arm64XDynamicRelocEntry::getSize() const {
1195 switch (type) {
1196 case IMAGE_DVRT_ARM64X_FIXUP_TYPE_ZEROFILL:
1197 return sizeof(uint16_t); // Just a header.
1198 case IMAGE_DVRT_ARM64X_FIXUP_TYPE_VALUE:
1199 return sizeof(uint16_t) + size; // A header and a payload.
1200 case IMAGE_DVRT_ARM64X_FIXUP_TYPE_DELTA:
1201 return 2 * sizeof(uint16_t); // A header and a delta.
1202 }
1203 llvm_unreachable("invalid type");
1204}
1205
1206void Arm64XDynamicRelocEntry::writeTo(uint8_t *buf) const {
1207 auto out = reinterpret_cast<ulittle16_t *>(buf);
1208 *out = (offset.get() & 0xfff) | (type << 12);
1209
1210 switch (type) {
1211 case IMAGE_DVRT_ARM64X_FIXUP_TYPE_ZEROFILL:
1212 *out |= ((bit_width(Value: size) - 1) << 14); // Encode the size.
1213 break;
1214 case IMAGE_DVRT_ARM64X_FIXUP_TYPE_VALUE:
1215 *out |= ((bit_width(Value: size) - 1) << 14); // Encode the size.
1216 switch (size) {
1217 case 2:
1218 out[1] = value.get();
1219 break;
1220 case 4:
1221 *reinterpret_cast<ulittle32_t *>(out + 1) = value.get();
1222 break;
1223 case 8:
1224 *reinterpret_cast<ulittle64_t *>(out + 1) = value.get();
1225 break;
1226 default:
1227 llvm_unreachable("invalid size");
1228 }
1229 break;
1230 case IMAGE_DVRT_ARM64X_FIXUP_TYPE_DELTA:
1231 int delta = value.get();
1232 // Negative offsets use a sign bit in the header.
1233 if (delta < 0) {
1234 *out |= 1 << 14;
1235 delta = -delta;
1236 }
1237 // Depending on the value, the delta is encoded with a shift of 2 or 3 bits.
1238 if (delta & 7) {
1239 assert(!(delta & 3));
1240 delta >>= 2;
1241 } else {
1242 *out |= (1 << 15);
1243 delta >>= 3;
1244 }
1245 out[1] = delta;
1246 assert(!(delta & ~0xffff));
1247 break;
1248 }
1249}
1250
1251void DynamicRelocsChunk::finalize() {
1252 llvm::stable_sort(Range&: arm64xRelocs, C: [=](const Arm64XDynamicRelocEntry &a,
1253 const Arm64XDynamicRelocEntry &b) {
1254 return a.offset.get() < b.offset.get();
1255 });
1256
1257 size = sizeof(coff_dynamic_reloc_table) + sizeof(coff_dynamic_relocation64);
1258 uint32_t prevPage = 0xfff;
1259
1260 for (const Arm64XDynamicRelocEntry &entry : arm64xRelocs) {
1261 uint32_t page = entry.offset.get() & ~0xfff;
1262 if (page != prevPage) {
1263 size = alignTo(Value: size, Align: sizeof(uint32_t)) +
1264 sizeof(coff_base_reloc_block_header);
1265 prevPage = page;
1266 }
1267 size += entry.getSize();
1268 }
1269
1270 size = alignTo(Value: size, Align: sizeof(uint32_t));
1271}
1272
1273// Set the reloc value. The reloc entry must be allocated beforehand.
1274void DynamicRelocsChunk::set(Arm64XRelocVal offset, Arm64XRelocVal value) {
1275 uint32_t rva = offset.get();
1276 auto entry =
1277 llvm::find_if(Range&: arm64xRelocs, P: [rva](const Arm64XDynamicRelocEntry &e) {
1278 return e.offset.get() == rva;
1279 });
1280 assert(entry != arm64xRelocs.end());
1281 assert(!entry->value.get());
1282 entry->value = value;
1283}
1284
1285void DynamicRelocsChunk::writeTo(uint8_t *buf) const {
1286 auto table = reinterpret_cast<coff_dynamic_reloc_table *>(buf);
1287 table->Version = 1;
1288 table->Size = sizeof(coff_dynamic_relocation64);
1289 buf += sizeof(*table);
1290
1291 auto header = reinterpret_cast<coff_dynamic_relocation64 *>(buf);
1292 header->Symbol = IMAGE_DYNAMIC_RELOCATION_ARM64X;
1293 buf += sizeof(*header);
1294
1295 coff_base_reloc_block_header *pageHeader = nullptr;
1296 size_t relocSize = 0;
1297 for (const Arm64XDynamicRelocEntry &entry : arm64xRelocs) {
1298 uint32_t page = entry.offset.get() & ~0xfff;
1299 if (!pageHeader || page != pageHeader->PageRVA) {
1300 relocSize = alignTo(Value: relocSize, Align: sizeof(uint32_t));
1301 if (pageHeader)
1302 pageHeader->BlockSize =
1303 buf + relocSize - reinterpret_cast<uint8_t *>(pageHeader);
1304 pageHeader =
1305 reinterpret_cast<coff_base_reloc_block_header *>(buf + relocSize);
1306 pageHeader->PageRVA = page;
1307 relocSize += sizeof(*pageHeader);
1308 }
1309
1310 entry.writeTo(buf: buf + relocSize);
1311 relocSize += entry.getSize();
1312 }
1313 relocSize = alignTo(Value: relocSize, Align: sizeof(uint32_t));
1314 pageHeader->BlockSize =
1315 buf + relocSize - reinterpret_cast<uint8_t *>(pageHeader);
1316
1317 header->BaseRelocSize = relocSize;
1318 table->Size += relocSize;
1319 assert(size == sizeof(*table) + sizeof(*header) + relocSize);
1320}
1321
1322} // namespace lld::coff
1323