1//===- Target.h -------------------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLD_ELF_TARGET_H
10#define LLD_ELF_TARGET_H
11
12#include "Config.h"
13#include "InputSection.h"
14#include "lld/Common/ErrorHandler.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/Object/ELF.h"
17#include "llvm/Object/ELFTypes.h"
18#include "llvm/Support/Compiler.h"
19#include "llvm/Support/MathExtras.h"
20#include <array>
21
22namespace lld {
23namespace elf {
24class Defined;
25class InputFile;
26class Symbol;
27template <class RelTy> struct Relocs;
28
29std::string toStr(Ctx &, RelType type);
30
31class TargetInfo {
32public:
33 TargetInfo(Ctx &ctx) : ctx(ctx) {}
34 virtual uint32_t calcEFlags() const { return 0; }
35 // Create target-specific synthetic sections, defined in Arch/ files.
36 virtual void initTargetSpecificSections() {}
37 virtual RelExpr getRelExpr(RelType type, const Symbol &s,
38 const uint8_t *loc) const = 0;
39 virtual RelType getDynRel(RelType type) const { return 0; }
40 virtual void writeGotPltHeader(uint8_t *buf) const {}
41 virtual void writeGotHeader(uint8_t *buf) const {}
42 virtual void writeGotPlt(uint8_t *buf, const Symbol &s) const {}
43 virtual void writeIgotPlt(uint8_t *buf, const Symbol &s) const {}
44 virtual int64_t getImplicitAddend(const uint8_t *buf, RelType type) const;
45
46 // If lazy binding is supported, the first entry of the PLT has code
47 // to call the dynamic linker to resolve PLT entries the first time
48 // they are called. This function writes that code.
49 virtual void writePltHeader(uint8_t *buf) const {}
50
51 virtual void writePlt(uint8_t *buf, const Symbol &sym,
52 uint64_t pltEntryAddr) const {}
53 virtual void writeIplt(uint8_t *buf, const Symbol &sym,
54 uint64_t pltEntryAddr) const {
55 // All but PPC32 and PPC64 use the same format for .plt and .iplt entries.
56 writePlt(buf, sym, pltEntryAddr);
57 }
58 virtual void writeIBTPlt(uint8_t *buf, size_t numEntries) const {}
59 virtual void addPltHeaderSymbols(InputSection &isec) const {}
60 virtual void addPltSymbols(InputSection &isec, uint64_t off) const {}
61
62 // Returns true if a relocation only uses the low bits of a value such that
63 // all those bits are in the same page. For example, if the relocation
64 // only uses the low 12 bits in a system with 4k pages. If this is true, the
65 // bits will always have the same value at runtime and we don't have to emit
66 // a dynamic relocation.
67 virtual bool usesOnlyLowPageBits(RelType type) const;
68
69 // Decide whether a Thunk is needed for the relocation from File
70 // targeting S.
71 virtual bool needsThunk(RelExpr expr, RelType relocType,
72 const InputFile *file, uint64_t branchAddr,
73 const Symbol &s, int64_t a) const;
74
75 // On systems with range extensions we place collections of Thunks at
76 // regular spacings that enable the majority of branches reach the Thunks.
77 // a value of 0 means range extension thunks are not supported.
78 virtual uint32_t getThunkSectionSpacing() const { return 0; }
79
80 // The function with a prologue starting at Loc was compiled with
81 // -fsplit-stack and it calls a function compiled without. Adjust the prologue
82 // to do the right thing. See https://gcc.gnu.org/wiki/SplitStacks.
83 // The symbols st_other flags are needed on PowerPC64 for determining the
84 // offset to the split-stack prologue.
85 virtual bool adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
86 uint8_t stOther) const;
87
88 // Return true if we can reach dst from src with RelType type.
89 virtual bool inBranchRange(RelType type, uint64_t src,
90 uint64_t dst) const;
91
92 // Function for scanning relocation. Typically overridden by targets that
93 // require special type or addend adjustment.
94 virtual void scanSection(InputSectionBase &);
95 // Called by scanSection as a default implementation for specific ELF
96 // relocation types.
97 template <class ELFT> void scanSection1(InputSectionBase &);
98 template <class ELFT, class RelTy>
99 void scanSectionImpl(InputSectionBase &, Relocs<RelTy>);
100
101 // Called after parallel relocation scanning is complete but before
102 // postScanRelocations processes symbol flags. Targets may override this to
103 // perform single-threaded fixups that cannot run during parallel scanning
104 // (e.g. symbol table modifications).
105 virtual void finalizeRelocScan() {}
106
107 virtual void relocate(uint8_t *loc, const Relocation &rel,
108 uint64_t val) const = 0;
109 void relocateNoSym(uint8_t *loc, RelType type, uint64_t val) const {
110 relocate(loc, rel: Relocation{.expr: R_NONE, .type: type, .offset: 0, .addend: 0, .sym: nullptr}, val);
111 }
112 virtual void relocateAlloc(InputSection &sec, uint8_t *buf) const;
113 void relocateEh(EhInputSection &sec, uint8_t *buf) const;
114
115 // Do a linker relaxation pass and return true if we changed something.
116 virtual bool relaxOnce(int pass) const { return false; }
117 // Relax CFI jump tables if implemented by target.
118 virtual void relaxCFIJumpTables() const {}
119 virtual bool synthesizeAlign(uint64_t &dot, InputSection *sec) {
120 return false;
121 }
122 // Do finalize relaxation after collecting relaxation infos.
123 virtual void finalizeRelax(int passes) const {}
124
125 virtual void applyJumpInstrMod(uint8_t *loc, JumpModType type,
126 JumpModType val) const {}
127 virtual void applyBranchToBranchOpt() const {}
128
129 virtual ~TargetInfo();
130
131 // This deletes a jump insn at the end of the section if it is a fall thru to
132 // the next section. Further, if there is a conditional jump and a direct
133 // jump consecutively, it tries to flip the conditional jump to convert the
134 // direct jump into a fall thru and delete it. Returns true if a jump
135 // instruction can be deleted.
136 virtual bool deleteFallThruJmpInsn(InputSection &is,
137 InputSection *nextIS) const {
138 return false;
139 }
140
141 Ctx &ctx;
142 unsigned defaultCommonPageSize = 4096;
143 unsigned defaultMaxPageSize = 4096;
144
145 uint64_t getImageBase() const;
146
147 // True if _GLOBAL_OFFSET_TABLE_ is relative to .got.plt, false if .got.
148 bool gotBaseSymInGotPlt = false;
149
150 static constexpr RelType noneRel = 0;
151 RelType copyRel = 0;
152 RelType gotRel = 0;
153 RelType pltRel = 0;
154 RelType relativeRel = 0;
155 RelType iRelativeRel = 0;
156 RelType symbolicRel = 0;
157 RelType iRelSymbolicRel = 0;
158 RelType tlsDescRel = 0;
159 RelType tlsGotRel = 0;
160 RelType tlsModuleIndexRel = 0;
161 RelType tlsOffsetRel = 0;
162 unsigned gotEntrySize = ctx.arg.wordsize;
163 unsigned pltEntrySize = 0;
164 unsigned pltHeaderSize = 0;
165 unsigned ipltEntrySize = 0;
166
167 // At least on x86_64 positions 1 and 2 are used by the first plt entry
168 // to support lazy loading.
169 unsigned gotPltHeaderEntriesNum = 3;
170
171 // On PPC ELF V2 abi, the first entry in the .got is the .TOC.
172 unsigned gotHeaderEntriesNum = 0;
173
174 // On PPC ELF V2 abi, the dynamic section needs DT_PPC64_OPT (DT_LOPROC + 3)
175 // to be set to 0x2 if there can be multiple TOC's. Although we do not emit
176 // multiple TOC's, there can be a mix of TOC and NOTOC addressing which
177 // is functionally equivalent.
178 int ppc64DynamicSectionOpt = 0;
179
180 bool needsThunks = false;
181
182 // A 4-byte field corresponding to one or more trap instructions, used to pad
183 // executable OutputSections.
184 std::array<uint8_t, 4> trapInstr = {};
185
186 // Stores the NOP instructions of different sizes for the target and is used
187 // to pad sections that are relaxed.
188 std::optional<std::vector<std::vector<uint8_t>>> nopInstrs;
189
190 // If a target needs to rewrite calls to __morestack to instead call
191 // __morestack_non_split when a split-stack enabled caller calls a
192 // non-split-stack callee this will return true. Otherwise returns false.
193 bool needsMoreStackNonSplit = true;
194
195 virtual RelExpr adjustTlsExpr(RelType type, RelExpr expr) const;
196 virtual RelExpr adjustGotPcExpr(RelType type, int64_t addend,
197 const uint8_t *loc) const;
198
199protected:
200 // On FreeBSD x86_64 the first page cannot be mmaped.
201 // On Linux this is controlled by vm.mmap_min_addr. At least on some x86_64
202 // installs this is set to 65536, so the first 15 pages cannot be used.
203 // Given that, the smallest value that can be used in here is 0x10000.
204 uint64_t defaultImageBase = 0x10000;
205};
206
207void setAArch64TargetInfo(Ctx &);
208void setAMDGPUTargetInfo(Ctx &);
209void setARMTargetInfo(Ctx &);
210void setAVRTargetInfo(Ctx &);
211void setHexagonTargetInfo(Ctx &);
212void setLoongArchTargetInfo(Ctx &);
213void setMSP430TargetInfo(Ctx &);
214void setMipsTargetInfo(Ctx &);
215void setPPC64TargetInfo(Ctx &);
216void setPPCTargetInfo(Ctx &);
217void setRISCVTargetInfo(Ctx &);
218void setSPARCV9TargetInfo(Ctx &);
219void setSystemZTargetInfo(Ctx &);
220void setX86TargetInfo(Ctx &);
221void setX86_64TargetInfo(Ctx &);
222
223struct ErrorPlace {
224 InputSectionBase *isec;
225 std::string loc;
226 std::string srcLoc;
227};
228
229// Returns input section and corresponding source string for the given location.
230ErrorPlace getErrorPlace(Ctx &ctx, const uint8_t *loc);
231
232static inline std::string getErrorLoc(Ctx &ctx, const uint8_t *loc) {
233 return getErrorPlace(ctx, loc).loc;
234}
235
236void processArmCmseSymbols(Ctx &);
237
238template <class ELFT> uint32_t calcMipsEFlags(Ctx &);
239uint8_t getMipsFpAbiFlag(Ctx &, InputFile *file, uint8_t oldFlag,
240 uint8_t newFlag);
241uint64_t getMipsPageAddr(uint64_t addr);
242bool isMipsN32Abi(Ctx &, const InputFile &f);
243bool isMicroMips(Ctx &);
244bool isMipsR6(Ctx &);
245
246void writePPC32GlinkSection(Ctx &, uint8_t *buf, size_t numEntries);
247
248unsigned getPPCDFormOp(unsigned secondaryOp);
249unsigned getPPCDSFormOp(unsigned secondaryOp);
250
251// In the PowerPC64 Elf V2 abi a function can have 2 entry points. The first
252// is a global entry point (GEP) which typically is used to initialize the TOC
253// pointer in general purpose register 2. The second is a local entry
254// point (LEP) which bypasses the TOC pointer initialization code. The
255// offset between GEP and LEP is encoded in a function's st_other flags.
256// This function will return the offset (in bytes) from the global entry-point
257// to the local entry-point.
258unsigned getPPC64GlobalEntryToLocalEntryOffset(Ctx &, uint8_t stOther);
259
260// Write a prefixed instruction, which is a 4-byte prefix followed by a 4-byte
261// instruction (regardless of endianness). Therefore, the prefix is always in
262// lower memory than the instruction.
263void writePrefixedInst(Ctx &, uint8_t *loc, uint64_t insn);
264
265void addPPC64SaveRestore(Ctx &);
266uint64_t getPPC64TocBase(Ctx &ctx);
267uint64_t getAArch64Page(uint64_t expr);
268bool isAArch64BTILandingPad(Ctx &, Symbol &s, int64_t a);
269template <typename ELFT> void writeARMCmseImportLib(Ctx &);
270uint64_t getLoongArchPageDelta(uint64_t dest, uint64_t pc, RelType type);
271void riscvFinalizeRelax(int passes);
272void mergeRISCVAttributesSections(Ctx &);
273void mergeHexagonAttributesSections(Ctx &);
274void addArmInputSectionMappingSymbols(Ctx &);
275void addArmSyntheticSectionMappingSymbol(Defined *);
276void sortArmMappingSymbols(Ctx &);
277void convertArmInstructionstoBE8(Ctx &, InputSection *sec, uint8_t *buf);
278void createTaggedSymbols(Ctx &);
279void initSymbolAnchors(Ctx &);
280
281void setTarget(Ctx &);
282
283template <class ELFT> bool isMipsPIC(const Defined *sym);
284
285const ELFSyncStream &operator<<(const ELFSyncStream &, RelType);
286
287void reportRangeError(Ctx &, uint8_t *loc, const Relocation &rel,
288 const Twine &v, int64_t min, uint64_t max);
289void reportRangeError(Ctx &ctx, uint8_t *loc, int64_t v, int n,
290 const Symbol &sym, const Twine &msg);
291
292// Make sure that V can be represented as an N bit signed integer.
293inline void checkInt(Ctx &ctx, uint8_t *loc, int64_t v, int n,
294 const Relocation &rel) {
295 if (v != llvm::SignExtend64(X: v, B: n))
296 reportRangeError(ctx, loc, rel, v: Twine(v), min: llvm::minIntN(N: n),
297 max: llvm::maxIntN(N: n));
298}
299
300// Make sure that V can be represented as an N bit unsigned integer.
301inline void checkUInt(Ctx &ctx, uint8_t *loc, uint64_t v, int n,
302 const Relocation &rel) {
303 if ((v >> n) != 0)
304 reportRangeError(ctx, loc, rel, v: Twine(v), min: 0, max: llvm::maxUIntN(N: n));
305}
306
307// Make sure that V can be represented as an N bit signed or unsigned integer.
308inline void checkIntUInt(Ctx &ctx, uint8_t *loc, uint64_t v, int n,
309 const Relocation &rel) {
310 // For the error message we should cast V to a signed integer so that error
311 // messages show a small negative value rather than an extremely large one
312 if (v != (uint64_t)llvm::SignExtend64(X: v, B: n) && (v >> n) != 0)
313 reportRangeError(ctx, loc, rel, v: Twine((int64_t)v), min: llvm::minIntN(N: n),
314 max: llvm::maxUIntN(N: n));
315}
316
317inline void checkAlignment(Ctx &ctx, uint8_t *loc, uint64_t v, int n,
318 const Relocation &rel) {
319 if ((v & (n - 1)) != 0)
320 Err(ctx) << getErrorLoc(ctx, loc) << "improper alignment for relocation "
321 << rel.type << ": 0x" << llvm::utohexstr(X: v)
322 << " is not aligned to " << n << " bytes";
323}
324
325// Endianness-aware read/write.
326inline uint16_t read16(Ctx &ctx, const void *p) {
327 return llvm::support::endian::read16(P: p, E: ctx.arg.endianness);
328}
329
330inline uint32_t read32(Ctx &ctx, const void *p) {
331 return llvm::support::endian::read32(P: p, E: ctx.arg.endianness);
332}
333
334inline uint64_t read64(Ctx &ctx, const void *p) {
335 return llvm::support::endian::read64(P: p, E: ctx.arg.endianness);
336}
337
338inline void write16(Ctx &ctx, void *p, uint16_t v) {
339 llvm::support::endian::write16(P: p, V: v, E: ctx.arg.endianness);
340}
341
342inline void write32(Ctx &ctx, void *p, uint32_t v) {
343 llvm::support::endian::write32(P: p, V: v, E: ctx.arg.endianness);
344}
345
346inline void write64(Ctx &ctx, void *p, uint64_t v) {
347 llvm::support::endian::write64(P: p, V: v, E: ctx.arg.endianness);
348}
349
350} // namespace elf
351} // namespace lld
352
353#ifdef __clang__
354#pragma clang diagnostic ignored "-Wgnu-zero-variadic-macro-arguments"
355#endif
356#define invokeELFT(f, ...) \
357 do { \
358 switch (ctx.arg.ekind) { \
359 case lld::elf::ELF32LEKind: \
360 f<llvm::object::ELF32LE>(__VA_ARGS__); \
361 break; \
362 case lld::elf::ELF32BEKind: \
363 f<llvm::object::ELF32BE>(__VA_ARGS__); \
364 break; \
365 case lld::elf::ELF64LEKind: \
366 f<llvm::object::ELF64LE>(__VA_ARGS__); \
367 break; \
368 case lld::elf::ELF64BEKind: \
369 f<llvm::object::ELF64BE>(__VA_ARGS__); \
370 break; \
371 default: \
372 llvm_unreachable("unknown ctx.arg.ekind"); \
373 } \
374 } while (0)
375
376#endif
377