1//===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// A set of register units. It is intended for register liveness tracking.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
15#define LLVM_CODEGEN_LIVEREGUNITS_H
16
17#include "llvm/ADT/BitVector.h"
18#include "llvm/CodeGen/MachineInstrBundle.h"
19#include "llvm/CodeGen/TargetRegisterInfo.h"
20#include "llvm/MC/LaneBitmask.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/Support/Compiler.h"
23#include <cstdint>
24
25namespace llvm {
26
27class MachineInstr;
28class MachineBasicBlock;
29
30/// A set of register units used to track register liveness.
31class LiveRegUnits {
32 const TargetRegisterInfo *TRI = nullptr;
33 BitVector Units;
34
35public:
36 /// Constructs a new empty LiveRegUnits set.
37 LiveRegUnits() = default;
38
39 /// Constructs and initialize an empty LiveRegUnits set.
40 LiveRegUnits(const TargetRegisterInfo &TRI) {
41 init(TRI);
42 }
43
44 /// For a machine instruction \p MI, adds all register units used in
45 /// \p UsedRegUnits and defined or clobbered in \p ModifiedRegUnits. This is
46 /// useful when walking over a range of instructions to track registers
47 /// used or defined separately.
48 static void accumulateUsedDefed(const MachineInstr &MI,
49 LiveRegUnits &ModifiedRegUnits,
50 LiveRegUnits &UsedRegUnits,
51 const TargetRegisterInfo *TRI) {
52 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
53 if (O->isRegMask())
54 ModifiedRegUnits.addRegsInMask(RegMask: O->getRegMask());
55 if (!O->isReg())
56 continue;
57 Register Reg = O->getReg();
58 if (!Reg.isPhysical())
59 continue;
60 if (O->isDef()) {
61 // Some architectures (e.g. AArch64 XZR/WZR) have registers that are
62 // constant and may be used as destinations to indicate the generated
63 // value is discarded. No need to track such case as a def.
64 if (!TRI->isConstantPhysReg(PhysReg: Reg))
65 ModifiedRegUnits.addReg(Reg);
66 } else {
67 assert(O->isUse() && "Reg operand not a def and not a use");
68 UsedRegUnits.addReg(Reg);
69 }
70 }
71 }
72
73 /// Initialize and clear the set.
74 void init(const TargetRegisterInfo &TRI) {
75 this->TRI = &TRI;
76 Units.reset();
77 Units.resize(N: TRI.getNumRegUnits());
78 }
79
80 /// Clears the set.
81 void clear() { Units.reset(); }
82
83 /// Returns true if the set is empty.
84 bool empty() const { return Units.none(); }
85
86 /// Adds register units covered by physical register \p Reg.
87 void addReg(MCRegister Reg) {
88 for (MCRegUnit Unit : TRI->regunits(Reg))
89 Units.set(static_cast<unsigned>(Unit));
90 }
91
92 /// Adds register units covered by physical register \p Reg that are
93 /// part of the lanemask \p Mask.
94 void addRegMasked(MCRegister Reg, LaneBitmask Mask) {
95 for (MCRegUnitMaskIterator I(Reg, TRI); I.isValid(); ++I) {
96 auto [Unit, UnitMask] = *I;
97 if ((UnitMask & Mask).any())
98 Units.set(static_cast<unsigned>(Unit));
99 }
100 }
101
102 /// Removes all register units covered by physical register \p Reg.
103 void removeReg(MCRegister Reg) {
104 for (MCRegUnit Unit : TRI->regunits(Reg))
105 Units.reset(Idx: static_cast<unsigned>(Unit));
106 }
107
108 /// Removes register units not preserved by the regmask \p RegMask.
109 /// The regmask has the same format as the one in the RegMask machine operand.
110 LLVM_ABI void removeRegsNotPreserved(const uint32_t *RegMask);
111
112 /// Adds register units not preserved by the regmask \p RegMask.
113 /// The regmask has the same format as the one in the RegMask machine operand.
114 LLVM_ABI void addRegsInMask(const uint32_t *RegMask);
115
116 /// Returns true if no part of physical register \p Reg is live.
117 bool available(MCRegister Reg) const {
118 for (MCRegUnit Unit : TRI->regunits(Reg)) {
119 if (Units.test(Idx: static_cast<unsigned>(Unit)))
120 return false;
121 }
122 return true;
123 }
124
125 /// Updates liveness when stepping backwards over the instruction \p MI.
126 /// This removes all register units defined or clobbered in \p MI and then
127 /// adds the units used (as in use operands) in \p MI.
128 LLVM_ABI void stepBackward(const MachineInstr &MI);
129
130 /// Adds all register units used, defined or clobbered in \p MI.
131 /// This is useful when walking over a range of instruction to find registers
132 /// unused over the whole range.
133 LLVM_ABI void accumulate(const MachineInstr &MI);
134
135 /// Adds registers living out of block \p MBB.
136 /// Live out registers are the union of the live-in registers of the successor
137 /// blocks and pristine registers. Live out registers of the end block are the
138 /// callee saved registers.
139 LLVM_ABI void addLiveOuts(const MachineBasicBlock &MBB);
140
141 /// Adds registers living into block \p MBB.
142 LLVM_ABI void addLiveIns(const MachineBasicBlock &MBB);
143
144 /// Adds all register units marked in the bitvector \p RegUnits.
145 void addUnits(const BitVector &RegUnits) {
146 Units |= RegUnits;
147 }
148 /// Removes all register units marked in the bitvector \p RegUnits.
149 void removeUnits(const BitVector &RegUnits) {
150 Units.reset(RHS: RegUnits);
151 }
152 /// Return the internal bitvector representation of the set.
153 const BitVector &getBitVector() const {
154 return Units;
155 }
156
157private:
158 /// Adds pristine registers. Pristine registers are callee saved registers
159 /// that are unused in the function.
160 void addPristines(const MachineFunction &MF);
161};
162
163/// Returns an iterator range over all physical register and mask operands for
164/// \p MI and bundled instructions. This also skips any debug operands.
165inline iterator_range<
166 filter_iterator<ConstMIBundleOperands, bool (*)(const MachineOperand &)>>
167phys_regs_and_masks(const MachineInstr &MI) {
168 auto Pred = [](const MachineOperand &MOP) {
169 return MOP.isRegMask() ||
170 (MOP.isReg() && !MOP.isDebug() && MOP.getReg().isPhysical());
171 };
172 return make_filter_range(Range: const_mi_bundle_ops(MI),
173 Pred: static_cast<bool (*)(const MachineOperand &)>(Pred));
174}
175
176} // end namespace llvm
177
178#endif // LLVM_CODEGEN_LIVEREGUNITS_H
179