1//===- RegisterPressure.h - Dynamic Register Pressure -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the RegisterPressure class which can be used to track
10// MachineInstr level register pressure.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
15#define LLVM_CODEGEN_REGISTERPRESSURE_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/ADT/SparseSet.h"
20#include "llvm/CodeGen/MachineBasicBlock.h"
21#include "llvm/CodeGen/SlotIndexes.h"
22#include "llvm/CodeGen/TargetRegisterInfo.h"
23#include "llvm/MC/LaneBitmask.h"
24#include "llvm/Support/Compiler.h"
25#include <cassert>
26#include <cstdint>
27#include <cstdlib>
28#include <limits>
29#include <vector>
30
31namespace llvm {
32
33class LiveIntervals;
34class MachineFunction;
35class MachineInstr;
36class MachineRegisterInfo;
37class RegisterClassInfo;
38
39struct VRegMaskOrUnit {
40 VirtRegOrUnit VRegOrUnit;
41 LaneBitmask LaneMask;
42
43 VRegMaskOrUnit(VirtRegOrUnit VRegOrUnit, LaneBitmask LaneMask)
44 : VRegOrUnit(VRegOrUnit), LaneMask(LaneMask) {}
45};
46
47/// Base class for register pressure results.
48struct RegisterPressure {
49 /// Map of max reg pressure indexed by pressure set ID, not class ID.
50 std::vector<unsigned> MaxSetPressure;
51
52 /// List of live in virtual registers or physical register units.
53 SmallVector<VRegMaskOrUnit, 8> LiveInRegs;
54 SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
55
56 LLVM_ABI void dump(const TargetRegisterInfo *TRI) const;
57};
58
59/// RegisterPressure computed within a region of instructions delimited by
60/// TopIdx and BottomIdx. During pressure computation, the maximum pressure per
61/// register pressure set is increased. Once pressure within a region is fully
62/// computed, the live-in and live-out sets are recorded.
63///
64/// This is preferable to RegionPressure when LiveIntervals are available,
65/// because delimiting regions by SlotIndex is more robust and convenient than
66/// holding block iterators. The block contents can change without invalidating
67/// the pressure result.
68struct IntervalPressure : RegisterPressure {
69 /// Record the boundary of the region being tracked.
70 SlotIndex TopIdx;
71 SlotIndex BottomIdx;
72
73 LLVM_ABI void reset();
74
75 LLVM_ABI void openTop(SlotIndex NextTop);
76
77 LLVM_ABI void openBottom(SlotIndex PrevBottom);
78};
79
80/// RegisterPressure computed within a region of instructions delimited by
81/// TopPos and BottomPos. This is a less precise version of IntervalPressure for
82/// use when LiveIntervals are unavailable.
83struct RegionPressure : RegisterPressure {
84 /// Record the boundary of the region being tracked.
85 MachineBasicBlock::const_iterator TopPos;
86 MachineBasicBlock::const_iterator BottomPos;
87
88 LLVM_ABI void reset();
89
90 LLVM_ABI void openTop(MachineBasicBlock::const_iterator PrevTop);
91
92 LLVM_ABI void openBottom(MachineBasicBlock::const_iterator PrevBottom);
93};
94
95/// Capture a change in pressure for a single pressure set. UnitInc may be
96/// expressed in terms of upward or downward pressure depending on the client
97/// and will be dynamically adjusted for current liveness.
98///
99/// Pressure increments are tiny, typically 1-2 units, and this is only for
100/// heuristics, so we don't check UnitInc overflow. Instead, we may have a
101/// higher level assert that pressure is consistent within a region. We also
102/// effectively ignore dead defs which don't affect heuristics much.
103class PressureChange {
104 uint16_t PSetID = 0; // ID+1. 0=Invalid.
105 int16_t UnitInc = 0;
106
107public:
108 PressureChange() = default;
109 PressureChange(unsigned id): PSetID(id + 1) {
110 assert(id < std::numeric_limits<uint16_t>::max() && "PSetID overflow.");
111 }
112
113 bool isValid() const { return PSetID > 0; }
114
115 unsigned getPSet() const {
116 assert(isValid() && "invalid PressureChange");
117 return PSetID - 1;
118 }
119
120 // If PSetID is invalid, return UINT16_MAX to give it lowest priority.
121 unsigned getPSetOrMax() const {
122 return (PSetID - 1) & std::numeric_limits<uint16_t>::max();
123 }
124
125 int getUnitInc() const { return UnitInc; }
126
127 void setUnitInc(int Inc) { UnitInc = Inc; }
128
129 bool operator==(const PressureChange &RHS) const {
130 return PSetID == RHS.PSetID && UnitInc == RHS.UnitInc;
131 }
132
133 LLVM_ABI void dump() const;
134};
135
136/// List of PressureChanges in order of increasing, unique PSetID.
137///
138/// Use a small fixed number, because we can fit more PressureChanges in an
139/// empty SmallVector than ever need to be tracked per register class. If more
140/// PSets are affected, then we only track the most constrained.
141class PressureDiff {
142 // The initial design was for MaxPSets=4, but that requires PSet partitions,
143 // which are not yet implemented. (PSet partitions are equivalent PSets given
144 // the register classes actually in use within the scheduling region.)
145 enum { MaxPSets = 16 };
146
147 PressureChange PressureChanges[MaxPSets];
148
149 using iterator = PressureChange *;
150
151 iterator nonconst_begin() { return &PressureChanges[0]; }
152 iterator nonconst_end() { return &PressureChanges[MaxPSets]; }
153
154public:
155 using const_iterator = const PressureChange *;
156
157 const_iterator begin() const { return &PressureChanges[0]; }
158 const_iterator end() const { return &PressureChanges[MaxPSets]; }
159
160 LLVM_ABI void addPressureChange(VirtRegOrUnit VRegOrUnit, bool IsDec,
161 const MachineRegisterInfo *MRI);
162
163 LLVM_ABI void dump(const TargetRegisterInfo &TRI) const;
164};
165
166/// List of registers defined and used by a machine instruction.
167class RegisterOperands {
168public:
169 /// List of virtual registers and register units read by the instruction.
170 SmallVector<VRegMaskOrUnit, 8> Uses;
171 /// List of virtual registers and register units defined by the
172 /// instruction which are not dead.
173 SmallVector<VRegMaskOrUnit, 8> Defs;
174 /// List of virtual registers and register units defined by the
175 /// instruction but dead. Dead definitions should not necessarily be marked
176 /// with a dead flag. In this context a dead definition is just a definition
177 /// which doesn't define any register lane that remains live after the
178 /// defining instruction.
179 SmallVector<VRegMaskOrUnit, 8> DeadDefs;
180
181 /// Analyze the given instruction \p MI and fill in the Uses, Defs and
182 /// DeadDefs list based on the MachineOperand flags.
183 LLVM_ABI void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
184 const MachineRegisterInfo &MRI, bool TrackLaneMasks,
185 bool IgnoreDead);
186
187 /// Use liveness information to find dead defs at \p MI's dead slot not marked
188 /// with a dead flag and move them to the DeadDefs vector. This only considers
189 /// the merged live interval for defs, not the per-lane sub-ranges.
190 LLVM_ABI void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS,
191 const MachineRegisterInfo &MRI);
192
193 /// Use liveness information to find out which uses/defs are partially
194 /// undefined/dead at \p Pos and adjust the VRegMaskOrUnits accordingly.
195 LLVM_ABI void adjustLaneLiveness(const LiveIntervals &LIS,
196 const MachineRegisterInfo &MRI,
197 SlotIndex Pos);
198
199 /// Use liveness information to find out which uses/defs are partially
200 /// undefined/dead at the \p MI's position and adjust the VRegMaskOrUnits
201 /// accordingly. Missing read-undef and dead flags are added to \p MI.
202 LLVM_ABI void adjustLaneLiveness(const LiveIntervals &LIS,
203 const MachineRegisterInfo &MRI,
204 MachineInstr &MI);
205
206private:
207 /// Adjusts the \p Def based on \p LiveAfterDef. The \p Def is moved from the
208 /// Defs vector to the DeadDefs vector when no defined lane remains live after
209 /// the def. Returns a pointer to the next definition to process in order in
210 /// the Defs vector.
211 VRegMaskOrUnit *adjustDef(VRegMaskOrUnit &Def, LaneBitmask LiveAfterDef);
212
213 /// Use liveness information at \p Pos to adjust the lanemask of all uses.
214 void adjustUses(const LiveIntervals &LIS, const MachineRegisterInfo &MRI,
215 SlotIndex Pos);
216};
217
218/// Array of PressureDiffs.
219class PressureDiffs {
220 PressureDiff *PDiffArray = nullptr;
221 unsigned Size = 0;
222 unsigned Max = 0;
223
224public:
225 PressureDiffs() = default;
226 PressureDiffs &operator=(const PressureDiffs &other) = delete;
227 PressureDiffs(const PressureDiffs &other) = delete;
228 ~PressureDiffs() { free(ptr: PDiffArray); }
229
230 void clear() { Size = 0; }
231
232 LLVM_ABI void init(unsigned N);
233
234 PressureDiff &operator[](unsigned Idx) {
235 assert(Idx < Size && "PressureDiff index out of bounds");
236 return PDiffArray[Idx];
237 }
238 const PressureDiff &operator[](unsigned Idx) const {
239 return const_cast<PressureDiffs*>(this)->operator[](Idx);
240 }
241
242 /// Record pressure difference induced by the given operand list to
243 /// node with index \p Idx.
244 LLVM_ABI void addInstruction(unsigned Idx, const RegisterOperands &RegOpers,
245 const MachineRegisterInfo &MRI);
246};
247
248/// Store the effects of a change in pressure on things that MI scheduler cares
249/// about.
250///
251/// Excess records the value of the largest difference in register units beyond
252/// the target's pressure limits across the affected pressure sets, where
253/// largest is defined as the absolute value of the difference. Negative
254/// ExcessUnits indicates a reduction in pressure that had already exceeded the
255/// target's limits.
256///
257/// CriticalMax records the largest increase in the tracker's max pressure that
258/// exceeds the critical limit for some pressure set determined by the client.
259///
260/// CurrentMax records the largest increase in the tracker's max pressure that
261/// exceeds the current limit for some pressure set determined by the client.
262struct RegPressureDelta {
263 PressureChange Excess;
264 PressureChange CriticalMax;
265 PressureChange CurrentMax;
266
267 RegPressureDelta() = default;
268
269 bool operator==(const RegPressureDelta &RHS) const {
270 return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
271 && CurrentMax == RHS.CurrentMax;
272 }
273 bool operator!=(const RegPressureDelta &RHS) const {
274 return !operator==(RHS);
275 }
276 LLVM_ABI void dump() const;
277};
278
279/// A set of live virtual registers and physical register units.
280///
281/// This is a wrapper around a SparseSet which deals with mapping register unit
282/// and virtual register indexes to an index usable by the sparse set.
283class LiveRegSet {
284private:
285 struct IndexMaskPair {
286 unsigned Index;
287 LaneBitmask LaneMask;
288
289 IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
290 : Index(Index), LaneMask(LaneMask) {}
291
292 unsigned getSparseSetIndex() const {
293 return Index;
294 }
295 };
296
297 using RegSet = SparseSet<IndexMaskPair>;
298 RegSet Regs;
299 unsigned NumRegUnits = 0u;
300
301 unsigned getSparseIndexFromVirtRegOrUnit(VirtRegOrUnit VRegOrUnit) const {
302 if (VRegOrUnit.isVirtualReg())
303 return VRegOrUnit.asVirtualReg().virtRegIndex() + NumRegUnits;
304 assert(static_cast<unsigned>(VRegOrUnit.asMCRegUnit()) < NumRegUnits);
305 return static_cast<unsigned>(VRegOrUnit.asMCRegUnit());
306 }
307
308 VirtRegOrUnit getVirtRegOrUnitFromSparseIndex(unsigned SparseIndex) const {
309 if (SparseIndex >= NumRegUnits)
310 return VirtRegOrUnit(Register::index2VirtReg(Index: SparseIndex - NumRegUnits));
311 return VirtRegOrUnit(static_cast<MCRegUnit>(SparseIndex));
312 }
313
314public:
315 LLVM_ABI void clear();
316 LLVM_ABI void init(const MachineRegisterInfo &MRI);
317
318 LaneBitmask contains(VirtRegOrUnit VRegOrUnit) const {
319 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit);
320 RegSet::const_iterator I = Regs.find(Key: SparseIndex);
321 if (I == Regs.end())
322 return LaneBitmask::getNone();
323 return I->LaneMask;
324 }
325
326 /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
327 /// Returns the previously live lanes of \p Pair.Reg.
328 LaneBitmask insert(VRegMaskOrUnit Pair) {
329 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit: Pair.VRegOrUnit);
330 auto InsertRes = Regs.insert(Val: IndexMaskPair(SparseIndex, Pair.LaneMask));
331 if (!InsertRes.second) {
332 LaneBitmask PrevMask = InsertRes.first->LaneMask;
333 InsertRes.first->LaneMask |= Pair.LaneMask;
334 return PrevMask;
335 }
336 return LaneBitmask::getNone();
337 }
338
339 /// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
340 /// Returns the previously live lanes of \p Pair.Reg.
341 LaneBitmask erase(VRegMaskOrUnit Pair) {
342 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit: Pair.VRegOrUnit);
343 RegSet::iterator I = Regs.find(Key: SparseIndex);
344 if (I == Regs.end())
345 return LaneBitmask::getNone();
346 LaneBitmask PrevMask = I->LaneMask;
347 I->LaneMask &= ~Pair.LaneMask;
348 return PrevMask;
349 }
350
351 size_t size() const {
352 return Regs.size();
353 }
354
355 void appendTo(SmallVectorImpl<VRegMaskOrUnit> &To) const {
356 for (const IndexMaskPair &P : Regs) {
357 VirtRegOrUnit VRegOrUnit = getVirtRegOrUnitFromSparseIndex(SparseIndex: P.Index);
358 if (P.LaneMask.any())
359 To.emplace_back(Args&: VRegOrUnit, Args: P.LaneMask);
360 }
361 }
362};
363
364/// Track the current register pressure at some position in the instruction
365/// stream, and remember the high water mark within the region traversed. This
366/// does not automatically consider live-through ranges. The client may
367/// independently adjust for global liveness.
368///
369/// Each RegPressureTracker only works within a MachineBasicBlock. Pressure can
370/// be tracked across a larger region by storing a RegisterPressure result at
371/// each block boundary and explicitly adjusting pressure to account for block
372/// live-in and live-out register sets.
373///
374/// RegPressureTracker holds a reference to a RegisterPressure result that it
375/// computes incrementally. During downward tracking, P.BottomIdx or P.BottomPos
376/// is invalid until it reaches the end of the block or closeRegion() is
377/// explicitly called. Similarly, P.TopIdx is invalid during upward
378/// tracking. Changing direction has the side effect of closing region, and
379/// traversing past TopIdx or BottomIdx reopens it.
380class RegPressureTracker {
381 const MachineFunction *MF = nullptr;
382 const TargetRegisterInfo *TRI = nullptr;
383 const RegisterClassInfo *RCI = nullptr;
384 const MachineRegisterInfo *MRI = nullptr;
385 const LiveIntervals *LIS = nullptr;
386
387 /// We currently only allow pressure tracking within a block.
388 const MachineBasicBlock *MBB = nullptr;
389
390 /// Track the max pressure within the region traversed so far.
391 RegisterPressure &P;
392
393 /// Run in two modes dependending on whether constructed with IntervalPressure
394 /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
395 bool RequireIntervals;
396
397 /// True if UntiedDefs will be populated.
398 bool TrackUntiedDefs = false;
399
400 /// True if lanemasks should be tracked.
401 bool TrackLaneMasks = false;
402
403 /// Register pressure corresponds to liveness before this instruction
404 /// iterator. It may point to the end of the block or a DebugValue rather than
405 /// an instruction.
406 MachineBasicBlock::const_iterator CurrPos;
407
408 /// Pressure map indexed by pressure set ID, not class ID.
409 std::vector<unsigned> CurrSetPressure;
410
411 /// Set of live registers.
412 LiveRegSet LiveRegs;
413
414 /// Set of vreg defs that start a live range.
415 SparseSet<Register, Register, VirtReg2IndexFunctor> UntiedDefs;
416 /// Live-through pressure.
417 std::vector<unsigned> LiveThruPressure;
418
419public:
420 RegPressureTracker(IntervalPressure &rp) : P(rp), RequireIntervals(true) {}
421 RegPressureTracker(RegionPressure &rp) : P(rp), RequireIntervals(false) {}
422
423 LLVM_ABI void reset();
424
425 LLVM_ABI void init(const MachineFunction *mf, const RegisterClassInfo *rci,
426 const LiveIntervals *lis, const MachineBasicBlock *mbb,
427 MachineBasicBlock::const_iterator pos, bool TrackLaneMasks,
428 bool TrackUntiedDefs);
429
430 /// Force liveness of virtual registers or physical register
431 /// units. Particularly useful to initialize the livein/out state of the
432 /// tracker before the first call to advance/recede.
433 LLVM_ABI void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
434
435 /// Get the MI position corresponding to this register pressure.
436 MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
437
438 // Reset the MI position corresponding to the register pressure. This allows
439 // schedulers to move instructions above the RegPressureTracker's
440 // CurrPos. Since the pressure is computed before CurrPos, the iterator
441 // position changes while pressure does not.
442 void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
443
444 /// Recede across the previous instruction.
445 LLVM_ABI void recede(SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
446
447 /// Recede across the previous instruction.
448 /// This "low-level" variant assumes that recedeSkipDebugValues() was
449 /// called previously and takes precomputed RegisterOperands for the
450 /// instruction.
451 LLVM_ABI void recede(const RegisterOperands &RegOpers,
452 SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
453
454 /// Recede until we find an instruction which is not a DebugValue.
455 LLVM_ABI void recedeSkipDebugValues();
456
457 /// Advance across the current instruction.
458 LLVM_ABI void advance();
459
460 /// Advance across the current instruction.
461 /// This is a "low-level" variant of advance() which takes precomputed
462 /// RegisterOperands of the instruction.
463 LLVM_ABI void advance(const RegisterOperands &RegOpers);
464
465 /// Finalize the region boundaries and recored live ins and live outs.
466 LLVM_ABI void closeRegion();
467
468 /// Initialize the LiveThru pressure set based on the untied defs found in
469 /// RPTracker.
470 LLVM_ABI void initLiveThru(const RegPressureTracker &RPTracker);
471
472 /// Copy an existing live thru pressure result.
473 void initLiveThru(ArrayRef<unsigned> PressureSet) {
474 LiveThruPressure.assign(first: PressureSet.begin(), last: PressureSet.end());
475 }
476
477 ArrayRef<unsigned> getLiveThru() const { return LiveThruPressure; }
478
479 /// Get the resulting register pressure over the traversed region.
480 /// This result is complete if closeRegion() was explicitly invoked.
481 RegisterPressure &getPressure() { return P; }
482 const RegisterPressure &getPressure() const { return P; }
483
484 /// Get the register set pressure at the current position, which may be less
485 /// than the pressure across the traversed region.
486 const std::vector<unsigned> &getRegSetPressureAtPos() const {
487 return CurrSetPressure;
488 }
489
490 LLVM_ABI bool isTopClosed() const;
491 LLVM_ABI bool isBottomClosed() const;
492
493 LLVM_ABI void closeTop();
494 LLVM_ABI void closeBottom();
495
496 /// Consider the pressure increase caused by traversing this instruction
497 /// bottom-up. Find the pressure set with the most change beyond its pressure
498 /// limit based on the tracker's current pressure, and record the number of
499 /// excess register units of that pressure set introduced by this instruction.
500 LLVM_ABI void
501 getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff,
502 RegPressureDelta &Delta,
503 ArrayRef<PressureChange> CriticalPSets,
504 ArrayRef<unsigned> MaxPressureLimit);
505
506 LLVM_ABI void
507 getUpwardPressureDelta(const MachineInstr *MI,
508 /*const*/ PressureDiff &PDiff, RegPressureDelta &Delta,
509 ArrayRef<PressureChange> CriticalPSets,
510 ArrayRef<unsigned> MaxPressureLimit) const;
511
512 /// Consider the pressure increase caused by traversing this instruction
513 /// top-down. Find the pressure set with the most change beyond its pressure
514 /// limit based on the tracker's current pressure, and record the number of
515 /// excess register units of that pressure set introduced by this instruction.
516 LLVM_ABI void
517 getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta,
518 ArrayRef<PressureChange> CriticalPSets,
519 ArrayRef<unsigned> MaxPressureLimit);
520
521 /// Find the pressure set with the most change beyond its pressure limit after
522 /// traversing this instruction either upward or downward depending on the
523 /// closed end of the current region.
524 void getMaxPressureDelta(const MachineInstr *MI,
525 RegPressureDelta &Delta,
526 ArrayRef<PressureChange> CriticalPSets,
527 ArrayRef<unsigned> MaxPressureLimit) {
528 if (isTopClosed())
529 return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,
530 MaxPressureLimit);
531
532 assert(isBottomClosed() && "Uninitialized pressure tracker");
533 return getMaxUpwardPressureDelta(MI, PDiff: nullptr, Delta, CriticalPSets,
534 MaxPressureLimit);
535 }
536
537 /// Get the pressure of each PSet after traversing this instruction bottom-up.
538 LLVM_ABI void getUpwardPressure(const MachineInstr *MI,
539 std::vector<unsigned> &PressureResult,
540 std::vector<unsigned> &MaxPressureResult);
541
542 /// Get the pressure of each PSet after traversing this instruction top-down.
543 LLVM_ABI void getDownwardPressure(const MachineInstr *MI,
544 std::vector<unsigned> &PressureResult,
545 std::vector<unsigned> &MaxPressureResult);
546
547 void getPressureAfterInst(const MachineInstr *MI,
548 std::vector<unsigned> &PressureResult,
549 std::vector<unsigned> &MaxPressureResult) {
550 if (isTopClosed())
551 return getUpwardPressure(MI, PressureResult, MaxPressureResult);
552
553 assert(isBottomClosed() && "Uninitialized pressure tracker");
554 return getDownwardPressure(MI, PressureResult, MaxPressureResult);
555 }
556
557 bool hasUntiedDef(Register VirtReg) const {
558 return UntiedDefs.count(Key: VirtReg);
559 }
560
561 LLVM_ABI void dump() const;
562
563 LLVM_ABI void increaseRegPressure(VirtRegOrUnit VRegOrUnit,
564 LaneBitmask PreviousMask,
565 LaneBitmask NewMask);
566 LLVM_ABI void decreaseRegPressure(VirtRegOrUnit VRegOrUnit,
567 LaneBitmask PreviousMask,
568 LaneBitmask NewMask);
569
570protected:
571 /// Add Reg to the live out set and increase max pressure.
572 LLVM_ABI void discoverLiveOut(VRegMaskOrUnit Pair);
573 /// Add Reg to the live in set and increase max pressure.
574 LLVM_ABI void discoverLiveIn(VRegMaskOrUnit Pair);
575
576 /// Get the SlotIndex for the first nondebug instruction including or
577 /// after the current position.
578 LLVM_ABI SlotIndex getCurrSlot() const;
579
580 LLVM_ABI void bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs);
581
582 LLVM_ABI void bumpUpwardPressure(const MachineInstr *MI);
583 LLVM_ABI void bumpDownwardPressure(const MachineInstr *MI);
584
585 LLVM_ABI void
586 discoverLiveInOrOut(VRegMaskOrUnit Pair,
587 SmallVectorImpl<VRegMaskOrUnit> &LiveInOrOut);
588
589 LLVM_ABI LaneBitmask getLastUsedLanes(VirtRegOrUnit VRegOrUnit,
590 SlotIndex Pos) const;
591 LLVM_ABI LaneBitmask getLiveLanesAt(VirtRegOrUnit VRegOrUnit,
592 SlotIndex Pos) const;
593 LLVM_ABI LaneBitmask getLiveThroughAt(VirtRegOrUnit VRegOrUnit,
594 SlotIndex Pos) const;
595};
596
597LLVM_ABI void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
598 const TargetRegisterInfo *TRI);
599
600} // end namespace llvm
601
602#endif // LLVM_CODEGEN_REGISTERPRESSURE_H
603