1//===- RegisterPressure.h - Dynamic Register Pressure -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the RegisterPressure class which can be used to track
10// MachineInstr level register pressure.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
15#define LLVM_CODEGEN_REGISTERPRESSURE_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/ADT/SparseSet.h"
20#include "llvm/CodeGen/MachineBasicBlock.h"
21#include "llvm/CodeGen/SlotIndexes.h"
22#include "llvm/CodeGen/TargetRegisterInfo.h"
23#include "llvm/MC/LaneBitmask.h"
24#include "llvm/Support/Compiler.h"
25#include <cassert>
26#include <cstdint>
27#include <cstdlib>
28#include <limits>
29#include <vector>
30
31namespace llvm {
32
33class LiveIntervals;
34class MachineFunction;
35class MachineInstr;
36class MachineRegisterInfo;
37class RegisterClassInfo;
38
39struct VRegMaskOrUnit {
40 VirtRegOrUnit VRegOrUnit;
41 LaneBitmask LaneMask;
42
43 VRegMaskOrUnit(VirtRegOrUnit VRegOrUnit, LaneBitmask LaneMask)
44 : VRegOrUnit(VRegOrUnit), LaneMask(LaneMask) {}
45};
46
47/// Base class for register pressure results.
48struct RegisterPressure {
49 /// Map of max reg pressure indexed by pressure set ID, not class ID.
50 std::vector<unsigned> MaxSetPressure;
51
52 /// List of live in virtual registers or physical register units.
53 SmallVector<VRegMaskOrUnit, 8> LiveInRegs;
54 SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
55
56 LLVM_ABI void dump(const TargetRegisterInfo *TRI) const;
57};
58
59/// RegisterPressure computed within a region of instructions delimited by
60/// TopIdx and BottomIdx. During pressure computation, the maximum pressure per
61/// register pressure set is increased. Once pressure within a region is fully
62/// computed, the live-in and live-out sets are recorded.
63///
64/// This is preferable to RegionPressure when LiveIntervals are available,
65/// because delimiting regions by SlotIndex is more robust and convenient than
66/// holding block iterators. The block contents can change without invalidating
67/// the pressure result.
68struct IntervalPressure : RegisterPressure {
69 /// Record the boundary of the region being tracked.
70 SlotIndex TopIdx;
71 SlotIndex BottomIdx;
72
73 LLVM_ABI void reset();
74
75 LLVM_ABI void openTop(SlotIndex NextTop);
76
77 LLVM_ABI void openBottom(SlotIndex PrevBottom);
78};
79
80/// RegisterPressure computed within a region of instructions delimited by
81/// TopPos and BottomPos. This is a less precise version of IntervalPressure for
82/// use when LiveIntervals are unavailable.
83struct RegionPressure : RegisterPressure {
84 /// Record the boundary of the region being tracked.
85 MachineBasicBlock::const_iterator TopPos;
86 MachineBasicBlock::const_iterator BottomPos;
87
88 LLVM_ABI void reset();
89
90 LLVM_ABI void openTop(MachineBasicBlock::const_iterator PrevTop);
91
92 LLVM_ABI void openBottom(MachineBasicBlock::const_iterator PrevBottom);
93};
94
95/// Capture a change in pressure for a single pressure set. UnitInc may be
96/// expressed in terms of upward or downward pressure depending on the client
97/// and will be dynamically adjusted for current liveness.
98///
99/// Pressure increments are tiny, typically 1-2 units, and this is only for
100/// heuristics, so we don't check UnitInc overflow. Instead, we may have a
101/// higher level assert that pressure is consistent within a region. We also
102/// effectively ignore dead defs which don't affect heuristics much.
103class PressureChange {
104 uint16_t PSetID = 0; // ID+1. 0=Invalid.
105 int16_t UnitInc = 0;
106
107public:
108 PressureChange() = default;
109 PressureChange(unsigned id): PSetID(id + 1) {
110 assert(id < std::numeric_limits<uint16_t>::max() && "PSetID overflow.");
111 }
112
113 bool isValid() const { return PSetID > 0; }
114
115 unsigned getPSet() const {
116 assert(isValid() && "invalid PressureChange");
117 return PSetID - 1;
118 }
119
120 // If PSetID is invalid, return UINT16_MAX to give it lowest priority.
121 unsigned getPSetOrMax() const {
122 return (PSetID - 1) & std::numeric_limits<uint16_t>::max();
123 }
124
125 int getUnitInc() const { return UnitInc; }
126
127 void setUnitInc(int Inc) { UnitInc = Inc; }
128
129 bool operator==(const PressureChange &RHS) const {
130 return PSetID == RHS.PSetID && UnitInc == RHS.UnitInc;
131 }
132
133 LLVM_ABI void dump() const;
134};
135
136/// List of PressureChanges in order of increasing, unique PSetID.
137///
138/// Use a small fixed number, because we can fit more PressureChanges in an
139/// empty SmallVector than ever need to be tracked per register class. If more
140/// PSets are affected, then we only track the most constrained.
141class PressureDiff {
142 // The initial design was for MaxPSets=4, but that requires PSet partitions,
143 // which are not yet implemented. (PSet partitions are equivalent PSets given
144 // the register classes actually in use within the scheduling region.)
145 enum { MaxPSets = 16 };
146
147 PressureChange PressureChanges[MaxPSets];
148
149 using iterator = PressureChange *;
150
151 iterator nonconst_begin() { return &PressureChanges[0]; }
152 iterator nonconst_end() { return &PressureChanges[MaxPSets]; }
153
154public:
155 using const_iterator = const PressureChange *;
156
157 const_iterator begin() const { return &PressureChanges[0]; }
158 const_iterator end() const { return &PressureChanges[MaxPSets]; }
159
160 LLVM_ABI void addPressureChange(VirtRegOrUnit VRegOrUnit, bool IsDec,
161 const MachineRegisterInfo *MRI);
162
163 LLVM_ABI void dump(const TargetRegisterInfo &TRI) const;
164};
165
166/// List of registers defined and used by a machine instruction.
167class RegisterOperands {
168public:
169 /// List of virtual registers and register units read by the instruction.
170 SmallVector<VRegMaskOrUnit, 8> Uses;
171 /// List of virtual registers and register units defined by the
172 /// instruction which are not dead.
173 SmallVector<VRegMaskOrUnit, 8> Defs;
174 /// List of virtual registers and register units defined by the
175 /// instruction but dead. Dead definitions should not necessarily be marked
176 /// with a dead flag. In this context a dead definition is just a definition
177 /// which doesn't define any register lane that remains live after the
178 /// defining instruction.
179 SmallVector<VRegMaskOrUnit, 8> DeadDefs;
180
181 /// Analyze the given instruction \p MI and fill in the Uses, Defs and
182 /// DeadDefs list based on the MachineOperand flags.
183 LLVM_ABI void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
184 const MachineRegisterInfo &MRI, bool TrackLaneMasks,
185 bool IgnoreDead);
186
187 /// Use liveness information to find dead defs at \p MI's dead slot not marked
188 /// with a dead flag and move them to the DeadDefs vector. This only considers
189 /// the merged live interval for defs, not the per-lane sub-ranges.
190 LLVM_ABI void detectDeadDefs(const MachineInstr &MI, LiveIntervals &LIS,
191 const MachineRegisterInfo &MRI);
192
193 /// Use liveness information to find out which uses/defs are partially
194 /// undefined/dead at \p Pos and adjust the VRegMaskOrUnits accordingly.
195 LLVM_ABI void adjustLaneLiveness(LiveIntervals &LIS,
196 const MachineRegisterInfo &MRI,
197 SlotIndex Pos);
198
199 /// Use liveness information to find out which uses/defs are partially
200 /// undefined/dead at the \p MI's position and adjust the VRegMaskOrUnits
201 /// accordingly. Missing read-undef and dead flags are added to \p MI.
202 LLVM_ABI void adjustLaneLiveness(LiveIntervals &LIS,
203 const MachineRegisterInfo &MRI,
204 MachineInstr &MI);
205
206 /// Clear potentially-stale read-undef flags on the defs of \p MI, then
207 /// recompute them from \p LIS. The clear must come first because
208 /// adjustLaneLiveness only adds flags. When \p OnlyRegs is non-empty, only
209 /// subregister defs of those virtual registers are cleared (and the
210 /// recompute is skipped when \p MI has none); otherwise all defs are
211 /// cleared. This is used after moving an already-scheduled instruction,
212 /// which can invalidate the flags set for its previous position.
213 LLVM_ABI static void restoreLivenessFlags(MachineInstr &MI,
214 const TargetRegisterInfo &TRI,
215 const MachineRegisterInfo &MRI,
216 LiveIntervals &LIS,
217 bool TrackLaneMasks = true,
218 ArrayRef<Register> OnlyRegs = {});
219
220private:
221 /// Adjusts the \p Def based on \p LiveAfterDef. The \p Def is moved from the
222 /// Defs vector to the DeadDefs vector when no defined lane remains live after
223 /// the def. Returns a pointer to the next definition to process in order in
224 /// the Defs vector.
225 VRegMaskOrUnit *adjustDef(VRegMaskOrUnit &Def, LaneBitmask LiveAfterDef);
226
227 /// Use liveness information at \p Pos to adjust the lanemask of all uses.
228 void adjustUses(LiveIntervals &LIS, const MachineRegisterInfo &MRI,
229 SlotIndex Pos);
230};
231
232/// Array of PressureDiffs.
233class PressureDiffs {
234 PressureDiff *PDiffArray = nullptr;
235 unsigned Size = 0;
236 unsigned Max = 0;
237
238public:
239 PressureDiffs() = default;
240 PressureDiffs &operator=(const PressureDiffs &other) = delete;
241 PressureDiffs(const PressureDiffs &other) = delete;
242 ~PressureDiffs() { free(ptr: PDiffArray); }
243
244 void clear() { Size = 0; }
245
246 LLVM_ABI void init(unsigned N);
247
248 PressureDiff &operator[](unsigned Idx) {
249 assert(Idx < Size && "PressureDiff index out of bounds");
250 return PDiffArray[Idx];
251 }
252 const PressureDiff &operator[](unsigned Idx) const {
253 return const_cast<PressureDiffs*>(this)->operator[](Idx);
254 }
255
256 /// Record pressure difference induced by the given operand list to
257 /// node with index \p Idx.
258 LLVM_ABI void addInstruction(unsigned Idx, const RegisterOperands &RegOpers,
259 const MachineRegisterInfo &MRI);
260};
261
262/// Store the effects of a change in pressure on things that MI scheduler cares
263/// about.
264///
265/// Excess records the value of the largest difference in register units beyond
266/// the target's pressure limits across the affected pressure sets, where
267/// largest is defined as the absolute value of the difference. Negative
268/// ExcessUnits indicates a reduction in pressure that had already exceeded the
269/// target's limits.
270///
271/// CriticalMax records the largest increase in the tracker's max pressure that
272/// exceeds the critical limit for some pressure set determined by the client.
273///
274/// CurrentMax records the largest increase in the tracker's max pressure that
275/// exceeds the current limit for some pressure set determined by the client.
276struct RegPressureDelta {
277 PressureChange Excess;
278 PressureChange CriticalMax;
279 PressureChange CurrentMax;
280
281 RegPressureDelta() = default;
282
283 bool operator==(const RegPressureDelta &RHS) const {
284 return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
285 && CurrentMax == RHS.CurrentMax;
286 }
287 bool operator!=(const RegPressureDelta &RHS) const {
288 return !operator==(RHS);
289 }
290 LLVM_ABI void dump() const;
291};
292
293/// A set of live virtual registers and physical register units.
294///
295/// This is a wrapper around a SparseSet which deals with mapping register unit
296/// and virtual register indexes to an index usable by the sparse set.
297class LiveRegSet {
298private:
299 struct IndexMaskPair {
300 unsigned Index;
301 LaneBitmask LaneMask;
302
303 IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
304 : Index(Index), LaneMask(LaneMask) {}
305
306 unsigned getSparseSetIndex() const {
307 return Index;
308 }
309 };
310
311 using RegSet = SparseSet<IndexMaskPair>;
312 RegSet Regs;
313 unsigned NumRegUnits = 0u;
314
315 unsigned getSparseIndexFromVirtRegOrUnit(VirtRegOrUnit VRegOrUnit) const {
316 if (VRegOrUnit.isVirtualReg())
317 return VRegOrUnit.asVirtualReg().virtRegIndex() + NumRegUnits;
318 assert(static_cast<unsigned>(VRegOrUnit.asMCRegUnit()) < NumRegUnits);
319 return static_cast<unsigned>(VRegOrUnit.asMCRegUnit());
320 }
321
322 VirtRegOrUnit getVirtRegOrUnitFromSparseIndex(unsigned SparseIndex) const {
323 if (SparseIndex >= NumRegUnits)
324 return VirtRegOrUnit(Register::index2VirtReg(Index: SparseIndex - NumRegUnits));
325 return VirtRegOrUnit(static_cast<MCRegUnit>(SparseIndex));
326 }
327
328public:
329 LLVM_ABI void clear();
330 LLVM_ABI void init(const MachineRegisterInfo &MRI);
331
332 LaneBitmask contains(VirtRegOrUnit VRegOrUnit) const {
333 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit);
334 RegSet::const_iterator I = Regs.find(Key: SparseIndex);
335 if (I == Regs.end())
336 return LaneBitmask::getNone();
337 return I->LaneMask;
338 }
339
340 /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
341 /// Returns the previously live lanes of \p Pair.Reg.
342 LaneBitmask insert(VRegMaskOrUnit Pair) {
343 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit: Pair.VRegOrUnit);
344 auto InsertRes = Regs.insert(Val: IndexMaskPair(SparseIndex, Pair.LaneMask));
345 if (!InsertRes.second) {
346 LaneBitmask PrevMask = InsertRes.first->LaneMask;
347 InsertRes.first->LaneMask |= Pair.LaneMask;
348 return PrevMask;
349 }
350 return LaneBitmask::getNone();
351 }
352
353 /// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
354 /// Returns the previously live lanes of \p Pair.Reg.
355 LaneBitmask erase(VRegMaskOrUnit Pair) {
356 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit: Pair.VRegOrUnit);
357 RegSet::iterator I = Regs.find(Key: SparseIndex);
358 if (I == Regs.end())
359 return LaneBitmask::getNone();
360 LaneBitmask PrevMask = I->LaneMask;
361 I->LaneMask &= ~Pair.LaneMask;
362 return PrevMask;
363 }
364
365 size_t size() const {
366 return Regs.size();
367 }
368
369 void appendTo(SmallVectorImpl<VRegMaskOrUnit> &To) const {
370 for (const IndexMaskPair &P : Regs) {
371 VirtRegOrUnit VRegOrUnit = getVirtRegOrUnitFromSparseIndex(SparseIndex: P.Index);
372 if (P.LaneMask.any())
373 To.emplace_back(Args&: VRegOrUnit, Args: P.LaneMask);
374 }
375 }
376};
377
378/// Track the current register pressure at some position in the instruction
379/// stream, and remember the high water mark within the region traversed. This
380/// does not automatically consider live-through ranges. The client may
381/// independently adjust for global liveness.
382///
383/// Each RegPressureTracker only works within a MachineBasicBlock. Pressure can
384/// be tracked across a larger region by storing a RegisterPressure result at
385/// each block boundary and explicitly adjusting pressure to account for block
386/// live-in and live-out register sets.
387///
388/// RegPressureTracker holds a reference to a RegisterPressure result that it
389/// computes incrementally. During downward tracking, P.BottomIdx or P.BottomPos
390/// is invalid until it reaches the end of the block or closeRegion() is
391/// explicitly called. Similarly, P.TopIdx is invalid during upward
392/// tracking. Changing direction has the side effect of closing region, and
393/// traversing past TopIdx or BottomIdx reopens it.
394class RegPressureTracker {
395 const MachineFunction *MF = nullptr;
396 const TargetRegisterInfo *TRI = nullptr;
397 const RegisterClassInfo *RCI = nullptr;
398 const MachineRegisterInfo *MRI = nullptr;
399 LiveIntervals *LIS = nullptr;
400
401 /// We currently only allow pressure tracking within a block.
402 const MachineBasicBlock *MBB = nullptr;
403
404 /// Track the max pressure within the region traversed so far.
405 RegisterPressure &P;
406
407 /// Run in two modes dependending on whether constructed with IntervalPressure
408 /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
409 bool RequireIntervals;
410
411 /// True if UntiedDefs will be populated.
412 bool TrackUntiedDefs = false;
413
414 /// True if lanemasks should be tracked.
415 bool TrackLaneMasks = false;
416
417 /// Register pressure corresponds to liveness before this instruction
418 /// iterator. It may point to the end of the block or a DebugValue rather than
419 /// an instruction.
420 MachineBasicBlock::const_iterator CurrPos;
421
422 /// Pressure map indexed by pressure set ID, not class ID.
423 std::vector<unsigned> CurrSetPressure;
424
425 /// Set of live registers.
426 LiveRegSet LiveRegs;
427
428 /// Set of vreg defs that start a live range.
429 SparseSet<Register, Register, VirtReg2IndexFunctor> UntiedDefs;
430 /// Live-through pressure.
431 std::vector<unsigned> LiveThruPressure;
432
433public:
434 RegPressureTracker(IntervalPressure &rp) : P(rp), RequireIntervals(true) {}
435 RegPressureTracker(RegionPressure &rp) : P(rp), RequireIntervals(false) {}
436
437 LLVM_ABI void reset();
438
439 LLVM_ABI void init(const MachineFunction *mf, const RegisterClassInfo *rci,
440 LiveIntervals *lis, const MachineBasicBlock *mbb,
441 MachineBasicBlock::const_iterator pos, bool TrackLaneMasks,
442 bool TrackUntiedDefs);
443
444 /// Force liveness of virtual registers or physical register
445 /// units. Particularly useful to initialize the livein/out state of the
446 /// tracker before the first call to advance/recede.
447 LLVM_ABI void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
448
449 /// Get the MI position corresponding to this register pressure.
450 MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
451
452 // Reset the MI position corresponding to the register pressure. This allows
453 // schedulers to move instructions above the RegPressureTracker's
454 // CurrPos. Since the pressure is computed before CurrPos, the iterator
455 // position changes while pressure does not.
456 void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
457
458 /// Recede across the previous instruction.
459 LLVM_ABI void recede(SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
460
461 /// Recede across the previous instruction.
462 /// This "low-level" variant assumes that recedeSkipDebugValues() was
463 /// called previously and takes precomputed RegisterOperands for the
464 /// instruction.
465 LLVM_ABI void recede(const RegisterOperands &RegOpers,
466 SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
467
468 /// Recede until we find an instruction which is not a DebugValue.
469 LLVM_ABI void recedeSkipDebugValues();
470
471 /// Advance across the current instruction.
472 LLVM_ABI void advance();
473
474 /// Advance across the current instruction.
475 /// This is a "low-level" variant of advance() which takes precomputed
476 /// RegisterOperands of the instruction.
477 LLVM_ABI void advance(const RegisterOperands &RegOpers);
478
479 /// Finalize the region boundaries and recored live ins and live outs.
480 LLVM_ABI void closeRegion();
481
482 /// Initialize the LiveThru pressure set based on the untied defs found in
483 /// RPTracker.
484 LLVM_ABI void initLiveThru(const RegPressureTracker &RPTracker);
485
486 /// Copy an existing live thru pressure result.
487 void initLiveThru(ArrayRef<unsigned> PressureSet) {
488 LiveThruPressure.assign(first: PressureSet.begin(), last: PressureSet.end());
489 }
490
491 ArrayRef<unsigned> getLiveThru() const { return LiveThruPressure; }
492
493 /// Get the resulting register pressure over the traversed region.
494 /// This result is complete if closeRegion() was explicitly invoked.
495 RegisterPressure &getPressure() { return P; }
496 const RegisterPressure &getPressure() const { return P; }
497
498 /// Get the register set pressure at the current position, which may be less
499 /// than the pressure across the traversed region.
500 const std::vector<unsigned> &getRegSetPressureAtPos() const {
501 return CurrSetPressure;
502 }
503
504 LLVM_ABI bool isTopClosed() const;
505 LLVM_ABI bool isBottomClosed() const;
506
507 LLVM_ABI void closeTop();
508 LLVM_ABI void closeBottom();
509
510 /// Consider the pressure increase caused by traversing this instruction
511 /// bottom-up. Find the pressure set with the most change beyond its pressure
512 /// limit based on the tracker's current pressure, and record the number of
513 /// excess register units of that pressure set introduced by this instruction.
514 LLVM_ABI void
515 getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff,
516 RegPressureDelta &Delta,
517 ArrayRef<PressureChange> CriticalPSets,
518 ArrayRef<unsigned> MaxPressureLimit);
519
520 LLVM_ABI void
521 getUpwardPressureDelta(const MachineInstr *MI,
522 /*const*/ PressureDiff &PDiff, RegPressureDelta &Delta,
523 ArrayRef<PressureChange> CriticalPSets,
524 ArrayRef<unsigned> MaxPressureLimit) const;
525
526 /// Consider the pressure increase caused by traversing this instruction
527 /// top-down. Find the pressure set with the most change beyond its pressure
528 /// limit based on the tracker's current pressure, and record the number of
529 /// excess register units of that pressure set introduced by this instruction.
530 LLVM_ABI void
531 getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta,
532 ArrayRef<PressureChange> CriticalPSets,
533 ArrayRef<unsigned> MaxPressureLimit);
534
535 /// Find the pressure set with the most change beyond its pressure limit after
536 /// traversing this instruction either upward or downward depending on the
537 /// closed end of the current region.
538 void getMaxPressureDelta(const MachineInstr *MI,
539 RegPressureDelta &Delta,
540 ArrayRef<PressureChange> CriticalPSets,
541 ArrayRef<unsigned> MaxPressureLimit) {
542 if (isTopClosed())
543 return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,
544 MaxPressureLimit);
545
546 assert(isBottomClosed() && "Uninitialized pressure tracker");
547 return getMaxUpwardPressureDelta(MI, PDiff: nullptr, Delta, CriticalPSets,
548 MaxPressureLimit);
549 }
550
551 /// Get the pressure of each PSet after traversing this instruction bottom-up.
552 LLVM_ABI void getUpwardPressure(const MachineInstr *MI,
553 std::vector<unsigned> &PressureResult,
554 std::vector<unsigned> &MaxPressureResult);
555
556 /// Get the pressure of each PSet after traversing this instruction top-down.
557 LLVM_ABI void getDownwardPressure(const MachineInstr *MI,
558 std::vector<unsigned> &PressureResult,
559 std::vector<unsigned> &MaxPressureResult);
560
561 void getPressureAfterInst(const MachineInstr *MI,
562 std::vector<unsigned> &PressureResult,
563 std::vector<unsigned> &MaxPressureResult) {
564 if (isTopClosed())
565 return getUpwardPressure(MI, PressureResult, MaxPressureResult);
566
567 assert(isBottomClosed() && "Uninitialized pressure tracker");
568 return getDownwardPressure(MI, PressureResult, MaxPressureResult);
569 }
570
571 bool hasUntiedDef(Register VirtReg) const {
572 return UntiedDefs.count(Key: VirtReg);
573 }
574
575 LLVM_ABI void dump() const;
576
577 LLVM_ABI void increaseRegPressure(VirtRegOrUnit VRegOrUnit,
578 LaneBitmask PreviousMask,
579 LaneBitmask NewMask);
580 LLVM_ABI void decreaseRegPressure(VirtRegOrUnit VRegOrUnit,
581 LaneBitmask PreviousMask,
582 LaneBitmask NewMask);
583
584protected:
585 /// Add Reg to the live out set and increase max pressure.
586 LLVM_ABI void discoverLiveOut(VRegMaskOrUnit Pair);
587 /// Add Reg to the live in set and increase max pressure.
588 LLVM_ABI void discoverLiveIn(VRegMaskOrUnit Pair);
589
590 /// Get the SlotIndex for the first nondebug instruction including or
591 /// after the current position.
592 LLVM_ABI SlotIndex getCurrSlot() const;
593
594 LLVM_ABI void bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs);
595
596 LLVM_ABI void bumpUpwardPressure(const MachineInstr *MI);
597 LLVM_ABI void bumpDownwardPressure(const MachineInstr *MI);
598
599 LLVM_ABI void
600 discoverLiveInOrOut(VRegMaskOrUnit Pair,
601 SmallVectorImpl<VRegMaskOrUnit> &LiveInOrOut);
602
603 LLVM_ABI LaneBitmask getLastUsedLanes(VirtRegOrUnit VRegOrUnit,
604 SlotIndex Pos) const;
605 LLVM_ABI LaneBitmask getLiveLanesAt(VirtRegOrUnit VRegOrUnit,
606 SlotIndex Pos) const;
607 LLVM_ABI LaneBitmask getLiveThroughAt(VirtRegOrUnit VRegOrUnit,
608 SlotIndex Pos) const;
609};
610
611LLVM_ABI void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
612 const TargetRegisterInfo *TRI);
613
614} // end namespace llvm
615
616#endif // LLVM_CODEGEN_REGISTERPRESSURE_H
617