1//===- RegisterPressure.h - Dynamic Register Pressure -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the RegisterPressure class which can be used to track
10// MachineInstr level register pressure.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
15#define LLVM_CODEGEN_REGISTERPRESSURE_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/ADT/SparseSet.h"
20#include "llvm/CodeGen/MachineBasicBlock.h"
21#include "llvm/CodeGen/SlotIndexes.h"
22#include "llvm/CodeGen/TargetRegisterInfo.h"
23#include "llvm/MC/LaneBitmask.h"
24#include "llvm/Support/Compiler.h"
25#include <cassert>
26#include <cstdint>
27#include <cstdlib>
28#include <limits>
29#include <vector>
30
31namespace llvm {
32
33class LiveIntervals;
34class MachineFunction;
35class MachineInstr;
36class MachineRegisterInfo;
37class RegisterClassInfo;
38
39struct VRegMaskOrUnit {
40 VirtRegOrUnit VRegOrUnit;
41 LaneBitmask LaneMask;
42
43 VRegMaskOrUnit(VirtRegOrUnit VRegOrUnit, LaneBitmask LaneMask)
44 : VRegOrUnit(VRegOrUnit), LaneMask(LaneMask) {}
45};
46
47/// Base class for register pressure results.
48struct RegisterPressure {
49 /// Map of max reg pressure indexed by pressure set ID, not class ID.
50 std::vector<unsigned> MaxSetPressure;
51
52 /// List of live in virtual registers or physical register units.
53 SmallVector<VRegMaskOrUnit, 8> LiveInRegs;
54 SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
55
56 LLVM_ABI void dump(const TargetRegisterInfo *TRI) const;
57};
58
59/// RegisterPressure computed within a region of instructions delimited by
60/// TopIdx and BottomIdx. During pressure computation, the maximum pressure per
61/// register pressure set is increased. Once pressure within a region is fully
62/// computed, the live-in and live-out sets are recorded.
63///
64/// This is preferable to RegionPressure when LiveIntervals are available,
65/// because delimiting regions by SlotIndex is more robust and convenient than
66/// holding block iterators. The block contents can change without invalidating
67/// the pressure result.
68struct IntervalPressure : RegisterPressure {
69 /// Record the boundary of the region being tracked.
70 SlotIndex TopIdx;
71 SlotIndex BottomIdx;
72
73 LLVM_ABI void reset();
74
75 LLVM_ABI void openTop(SlotIndex NextTop);
76
77 LLVM_ABI void openBottom(SlotIndex PrevBottom);
78};
79
80/// RegisterPressure computed within a region of instructions delimited by
81/// TopPos and BottomPos. This is a less precise version of IntervalPressure for
82/// use when LiveIntervals are unavailable.
83struct RegionPressure : RegisterPressure {
84 /// Record the boundary of the region being tracked.
85 MachineBasicBlock::const_iterator TopPos;
86 MachineBasicBlock::const_iterator BottomPos;
87
88 LLVM_ABI void reset();
89
90 LLVM_ABI void openTop(MachineBasicBlock::const_iterator PrevTop);
91
92 LLVM_ABI void openBottom(MachineBasicBlock::const_iterator PrevBottom);
93};
94
95/// Capture a change in pressure for a single pressure set. UnitInc may be
96/// expressed in terms of upward or downward pressure depending on the client
97/// and will be dynamically adjusted for current liveness.
98///
99/// Pressure increments are tiny, typically 1-2 units, and this is only for
100/// heuristics, so we don't check UnitInc overflow. Instead, we may have a
101/// higher level assert that pressure is consistent within a region. We also
102/// effectively ignore dead defs which don't affect heuristics much.
103class PressureChange {
104 uint16_t PSetID = 0; // ID+1. 0=Invalid.
105 int16_t UnitInc = 0;
106
107public:
108 PressureChange() = default;
109 PressureChange(unsigned id): PSetID(id + 1) {
110 assert(id < std::numeric_limits<uint16_t>::max() && "PSetID overflow.");
111 }
112
113 bool isValid() const { return PSetID > 0; }
114
115 unsigned getPSet() const {
116 assert(isValid() && "invalid PressureChange");
117 return PSetID - 1;
118 }
119
120 // If PSetID is invalid, return UINT16_MAX to give it lowest priority.
121 unsigned getPSetOrMax() const {
122 return (PSetID - 1) & std::numeric_limits<uint16_t>::max();
123 }
124
125 int getUnitInc() const { return UnitInc; }
126
127 void setUnitInc(int Inc) { UnitInc = Inc; }
128
129 bool operator==(const PressureChange &RHS) const {
130 return PSetID == RHS.PSetID && UnitInc == RHS.UnitInc;
131 }
132
133 LLVM_ABI void dump() const;
134};
135
136/// List of PressureChanges in order of increasing, unique PSetID.
137///
138/// Use a small fixed number, because we can fit more PressureChanges in an
139/// empty SmallVector than ever need to be tracked per register class. If more
140/// PSets are affected, then we only track the most constrained.
141class PressureDiff {
142 // The initial design was for MaxPSets=4, but that requires PSet partitions,
143 // which are not yet implemented. (PSet partitions are equivalent PSets given
144 // the register classes actually in use within the scheduling region.)
145 enum { MaxPSets = 16 };
146
147 PressureChange PressureChanges[MaxPSets];
148
149 using iterator = PressureChange *;
150
151 iterator nonconst_begin() { return &PressureChanges[0]; }
152 iterator nonconst_end() { return &PressureChanges[MaxPSets]; }
153
154public:
155 using const_iterator = const PressureChange *;
156
157 const_iterator begin() const { return &PressureChanges[0]; }
158 const_iterator end() const { return &PressureChanges[MaxPSets]; }
159
160 LLVM_ABI void addPressureChange(VirtRegOrUnit VRegOrUnit, bool IsDec,
161 const MachineRegisterInfo *MRI);
162
163 LLVM_ABI void dump(const TargetRegisterInfo &TRI) const;
164};
165
166/// List of registers defined and used by a machine instruction.
167class RegisterOperands {
168public:
169 /// List of virtual registers and register units read by the instruction.
170 SmallVector<VRegMaskOrUnit, 8> Uses;
171 /// List of virtual registers and register units defined by the
172 /// instruction which are not dead.
173 SmallVector<VRegMaskOrUnit, 8> Defs;
174 /// List of virtual registers and register units defined by the
175 /// instruction but dead.
176 SmallVector<VRegMaskOrUnit, 8> DeadDefs;
177
178 /// Analyze the given instruction \p MI and fill in the Uses, Defs and
179 /// DeadDefs list based on the MachineOperand flags.
180 LLVM_ABI void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
181 const MachineRegisterInfo &MRI, bool TrackLaneMasks,
182 bool IgnoreDead);
183
184 /// Use liveness information to find dead defs not marked with a dead flag
185 /// and move them to the DeadDefs vector.
186 LLVM_ABI void detectDeadDefs(const MachineInstr &MI,
187 const LiveIntervals &LIS);
188
189 /// Use liveness information to find out which uses/defs are partially
190 /// undefined/dead and adjust the VRegMaskOrUnits accordingly.
191 /// If \p AddFlagsMI is given then missing read-undef and dead flags will be
192 /// added to the instruction.
193 LLVM_ABI void adjustLaneLiveness(const LiveIntervals &LIS,
194 const MachineRegisterInfo &MRI,
195 SlotIndex Pos,
196 MachineInstr *AddFlagsMI = nullptr);
197};
198
199/// Array of PressureDiffs.
200class PressureDiffs {
201 PressureDiff *PDiffArray = nullptr;
202 unsigned Size = 0;
203 unsigned Max = 0;
204
205public:
206 PressureDiffs() = default;
207 PressureDiffs &operator=(const PressureDiffs &other) = delete;
208 PressureDiffs(const PressureDiffs &other) = delete;
209 ~PressureDiffs() { free(ptr: PDiffArray); }
210
211 void clear() { Size = 0; }
212
213 LLVM_ABI void init(unsigned N);
214
215 PressureDiff &operator[](unsigned Idx) {
216 assert(Idx < Size && "PressureDiff index out of bounds");
217 return PDiffArray[Idx];
218 }
219 const PressureDiff &operator[](unsigned Idx) const {
220 return const_cast<PressureDiffs*>(this)->operator[](Idx);
221 }
222
223 /// Record pressure difference induced by the given operand list to
224 /// node with index \p Idx.
225 LLVM_ABI void addInstruction(unsigned Idx, const RegisterOperands &RegOpers,
226 const MachineRegisterInfo &MRI);
227};
228
229/// Store the effects of a change in pressure on things that MI scheduler cares
230/// about.
231///
232/// Excess records the value of the largest difference in register units beyond
233/// the target's pressure limits across the affected pressure sets, where
234/// largest is defined as the absolute value of the difference. Negative
235/// ExcessUnits indicates a reduction in pressure that had already exceeded the
236/// target's limits.
237///
238/// CriticalMax records the largest increase in the tracker's max pressure that
239/// exceeds the critical limit for some pressure set determined by the client.
240///
241/// CurrentMax records the largest increase in the tracker's max pressure that
242/// exceeds the current limit for some pressure set determined by the client.
243struct RegPressureDelta {
244 PressureChange Excess;
245 PressureChange CriticalMax;
246 PressureChange CurrentMax;
247
248 RegPressureDelta() = default;
249
250 bool operator==(const RegPressureDelta &RHS) const {
251 return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
252 && CurrentMax == RHS.CurrentMax;
253 }
254 bool operator!=(const RegPressureDelta &RHS) const {
255 return !operator==(RHS);
256 }
257 LLVM_ABI void dump() const;
258};
259
260/// A set of live virtual registers and physical register units.
261///
262/// This is a wrapper around a SparseSet which deals with mapping register unit
263/// and virtual register indexes to an index usable by the sparse set.
264class LiveRegSet {
265private:
266 struct IndexMaskPair {
267 unsigned Index;
268 LaneBitmask LaneMask;
269
270 IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
271 : Index(Index), LaneMask(LaneMask) {}
272
273 unsigned getSparseSetIndex() const {
274 return Index;
275 }
276 };
277
278 using RegSet = SparseSet<IndexMaskPair>;
279 RegSet Regs;
280 unsigned NumRegUnits = 0u;
281
282 unsigned getSparseIndexFromVirtRegOrUnit(VirtRegOrUnit VRegOrUnit) const {
283 if (VRegOrUnit.isVirtualReg())
284 return VRegOrUnit.asVirtualReg().virtRegIndex() + NumRegUnits;
285 assert(static_cast<unsigned>(VRegOrUnit.asMCRegUnit()) < NumRegUnits);
286 return static_cast<unsigned>(VRegOrUnit.asMCRegUnit());
287 }
288
289 VirtRegOrUnit getVirtRegOrUnitFromSparseIndex(unsigned SparseIndex) const {
290 if (SparseIndex >= NumRegUnits)
291 return VirtRegOrUnit(Register::index2VirtReg(Index: SparseIndex - NumRegUnits));
292 return VirtRegOrUnit(static_cast<MCRegUnit>(SparseIndex));
293 }
294
295public:
296 LLVM_ABI void clear();
297 LLVM_ABI void init(const MachineRegisterInfo &MRI);
298
299 LaneBitmask contains(VirtRegOrUnit VRegOrUnit) const {
300 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit);
301 RegSet::const_iterator I = Regs.find(Key: SparseIndex);
302 if (I == Regs.end())
303 return LaneBitmask::getNone();
304 return I->LaneMask;
305 }
306
307 /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
308 /// Returns the previously live lanes of \p Pair.Reg.
309 LaneBitmask insert(VRegMaskOrUnit Pair) {
310 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit: Pair.VRegOrUnit);
311 auto InsertRes = Regs.insert(Val: IndexMaskPair(SparseIndex, Pair.LaneMask));
312 if (!InsertRes.second) {
313 LaneBitmask PrevMask = InsertRes.first->LaneMask;
314 InsertRes.first->LaneMask |= Pair.LaneMask;
315 return PrevMask;
316 }
317 return LaneBitmask::getNone();
318 }
319
320 /// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
321 /// Returns the previously live lanes of \p Pair.Reg.
322 LaneBitmask erase(VRegMaskOrUnit Pair) {
323 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit: Pair.VRegOrUnit);
324 RegSet::iterator I = Regs.find(Key: SparseIndex);
325 if (I == Regs.end())
326 return LaneBitmask::getNone();
327 LaneBitmask PrevMask = I->LaneMask;
328 I->LaneMask &= ~Pair.LaneMask;
329 return PrevMask;
330 }
331
332 size_t size() const {
333 return Regs.size();
334 }
335
336 void appendTo(SmallVectorImpl<VRegMaskOrUnit> &To) const {
337 for (const IndexMaskPair &P : Regs) {
338 VirtRegOrUnit VRegOrUnit = getVirtRegOrUnitFromSparseIndex(SparseIndex: P.Index);
339 if (P.LaneMask.any())
340 To.emplace_back(Args&: VRegOrUnit, Args: P.LaneMask);
341 }
342 }
343};
344
345/// Track the current register pressure at some position in the instruction
346/// stream, and remember the high water mark within the region traversed. This
347/// does not automatically consider live-through ranges. The client may
348/// independently adjust for global liveness.
349///
350/// Each RegPressureTracker only works within a MachineBasicBlock. Pressure can
351/// be tracked across a larger region by storing a RegisterPressure result at
352/// each block boundary and explicitly adjusting pressure to account for block
353/// live-in and live-out register sets.
354///
355/// RegPressureTracker holds a reference to a RegisterPressure result that it
356/// computes incrementally. During downward tracking, P.BottomIdx or P.BottomPos
357/// is invalid until it reaches the end of the block or closeRegion() is
358/// explicitly called. Similarly, P.TopIdx is invalid during upward
359/// tracking. Changing direction has the side effect of closing region, and
360/// traversing past TopIdx or BottomIdx reopens it.
361class RegPressureTracker {
362 const MachineFunction *MF = nullptr;
363 const TargetRegisterInfo *TRI = nullptr;
364 const RegisterClassInfo *RCI = nullptr;
365 const MachineRegisterInfo *MRI = nullptr;
366 const LiveIntervals *LIS = nullptr;
367
368 /// We currently only allow pressure tracking within a block.
369 const MachineBasicBlock *MBB = nullptr;
370
371 /// Track the max pressure within the region traversed so far.
372 RegisterPressure &P;
373
374 /// Run in two modes dependending on whether constructed with IntervalPressure
375 /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
376 bool RequireIntervals;
377
378 /// True if UntiedDefs will be populated.
379 bool TrackUntiedDefs = false;
380
381 /// True if lanemasks should be tracked.
382 bool TrackLaneMasks = false;
383
384 /// Register pressure corresponds to liveness before this instruction
385 /// iterator. It may point to the end of the block or a DebugValue rather than
386 /// an instruction.
387 MachineBasicBlock::const_iterator CurrPos;
388
389 /// Pressure map indexed by pressure set ID, not class ID.
390 std::vector<unsigned> CurrSetPressure;
391
392 /// Set of live registers.
393 LiveRegSet LiveRegs;
394
395 /// Set of vreg defs that start a live range.
396 SparseSet<Register, Register, VirtReg2IndexFunctor> UntiedDefs;
397 /// Live-through pressure.
398 std::vector<unsigned> LiveThruPressure;
399
400public:
401 RegPressureTracker(IntervalPressure &rp) : P(rp), RequireIntervals(true) {}
402 RegPressureTracker(RegionPressure &rp) : P(rp), RequireIntervals(false) {}
403
404 LLVM_ABI void reset();
405
406 LLVM_ABI void init(const MachineFunction *mf, const RegisterClassInfo *rci,
407 const LiveIntervals *lis, const MachineBasicBlock *mbb,
408 MachineBasicBlock::const_iterator pos, bool TrackLaneMasks,
409 bool TrackUntiedDefs);
410
411 /// Force liveness of virtual registers or physical register
412 /// units. Particularly useful to initialize the livein/out state of the
413 /// tracker before the first call to advance/recede.
414 LLVM_ABI void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
415
416 /// Get the MI position corresponding to this register pressure.
417 MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
418
419 // Reset the MI position corresponding to the register pressure. This allows
420 // schedulers to move instructions above the RegPressureTracker's
421 // CurrPos. Since the pressure is computed before CurrPos, the iterator
422 // position changes while pressure does not.
423 void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
424
425 /// Recede across the previous instruction.
426 LLVM_ABI void recede(SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
427
428 /// Recede across the previous instruction.
429 /// This "low-level" variant assumes that recedeSkipDebugValues() was
430 /// called previously and takes precomputed RegisterOperands for the
431 /// instruction.
432 LLVM_ABI void recede(const RegisterOperands &RegOpers,
433 SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
434
435 /// Recede until we find an instruction which is not a DebugValue.
436 LLVM_ABI void recedeSkipDebugValues();
437
438 /// Advance across the current instruction.
439 LLVM_ABI void advance();
440
441 /// Advance across the current instruction.
442 /// This is a "low-level" variant of advance() which takes precomputed
443 /// RegisterOperands of the instruction.
444 LLVM_ABI void advance(const RegisterOperands &RegOpers);
445
446 /// Finalize the region boundaries and recored live ins and live outs.
447 LLVM_ABI void closeRegion();
448
449 /// Initialize the LiveThru pressure set based on the untied defs found in
450 /// RPTracker.
451 LLVM_ABI void initLiveThru(const RegPressureTracker &RPTracker);
452
453 /// Copy an existing live thru pressure result.
454 void initLiveThru(ArrayRef<unsigned> PressureSet) {
455 LiveThruPressure.assign(first: PressureSet.begin(), last: PressureSet.end());
456 }
457
458 ArrayRef<unsigned> getLiveThru() const { return LiveThruPressure; }
459
460 /// Get the resulting register pressure over the traversed region.
461 /// This result is complete if closeRegion() was explicitly invoked.
462 RegisterPressure &getPressure() { return P; }
463 const RegisterPressure &getPressure() const { return P; }
464
465 /// Get the register set pressure at the current position, which may be less
466 /// than the pressure across the traversed region.
467 const std::vector<unsigned> &getRegSetPressureAtPos() const {
468 return CurrSetPressure;
469 }
470
471 LLVM_ABI bool isTopClosed() const;
472 LLVM_ABI bool isBottomClosed() const;
473
474 LLVM_ABI void closeTop();
475 LLVM_ABI void closeBottom();
476
477 /// Consider the pressure increase caused by traversing this instruction
478 /// bottom-up. Find the pressure set with the most change beyond its pressure
479 /// limit based on the tracker's current pressure, and record the number of
480 /// excess register units of that pressure set introduced by this instruction.
481 LLVM_ABI void
482 getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff,
483 RegPressureDelta &Delta,
484 ArrayRef<PressureChange> CriticalPSets,
485 ArrayRef<unsigned> MaxPressureLimit);
486
487 LLVM_ABI void
488 getUpwardPressureDelta(const MachineInstr *MI,
489 /*const*/ PressureDiff &PDiff, RegPressureDelta &Delta,
490 ArrayRef<PressureChange> CriticalPSets,
491 ArrayRef<unsigned> MaxPressureLimit) const;
492
493 /// Consider the pressure increase caused by traversing this instruction
494 /// top-down. Find the pressure set with the most change beyond its pressure
495 /// limit based on the tracker's current pressure, and record the number of
496 /// excess register units of that pressure set introduced by this instruction.
497 LLVM_ABI void
498 getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta,
499 ArrayRef<PressureChange> CriticalPSets,
500 ArrayRef<unsigned> MaxPressureLimit);
501
502 /// Find the pressure set with the most change beyond its pressure limit after
503 /// traversing this instruction either upward or downward depending on the
504 /// closed end of the current region.
505 void getMaxPressureDelta(const MachineInstr *MI,
506 RegPressureDelta &Delta,
507 ArrayRef<PressureChange> CriticalPSets,
508 ArrayRef<unsigned> MaxPressureLimit) {
509 if (isTopClosed())
510 return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,
511 MaxPressureLimit);
512
513 assert(isBottomClosed() && "Uninitialized pressure tracker");
514 return getMaxUpwardPressureDelta(MI, PDiff: nullptr, Delta, CriticalPSets,
515 MaxPressureLimit);
516 }
517
518 /// Get the pressure of each PSet after traversing this instruction bottom-up.
519 LLVM_ABI void getUpwardPressure(const MachineInstr *MI,
520 std::vector<unsigned> &PressureResult,
521 std::vector<unsigned> &MaxPressureResult);
522
523 /// Get the pressure of each PSet after traversing this instruction top-down.
524 LLVM_ABI void getDownwardPressure(const MachineInstr *MI,
525 std::vector<unsigned> &PressureResult,
526 std::vector<unsigned> &MaxPressureResult);
527
528 void getPressureAfterInst(const MachineInstr *MI,
529 std::vector<unsigned> &PressureResult,
530 std::vector<unsigned> &MaxPressureResult) {
531 if (isTopClosed())
532 return getUpwardPressure(MI, PressureResult, MaxPressureResult);
533
534 assert(isBottomClosed() && "Uninitialized pressure tracker");
535 return getDownwardPressure(MI, PressureResult, MaxPressureResult);
536 }
537
538 bool hasUntiedDef(Register VirtReg) const {
539 return UntiedDefs.count(Key: VirtReg);
540 }
541
542 LLVM_ABI void dump() const;
543
544 LLVM_ABI void increaseRegPressure(VirtRegOrUnit VRegOrUnit,
545 LaneBitmask PreviousMask,
546 LaneBitmask NewMask);
547 LLVM_ABI void decreaseRegPressure(VirtRegOrUnit VRegOrUnit,
548 LaneBitmask PreviousMask,
549 LaneBitmask NewMask);
550
551protected:
552 /// Add Reg to the live out set and increase max pressure.
553 LLVM_ABI void discoverLiveOut(VRegMaskOrUnit Pair);
554 /// Add Reg to the live in set and increase max pressure.
555 LLVM_ABI void discoverLiveIn(VRegMaskOrUnit Pair);
556
557 /// Get the SlotIndex for the first nondebug instruction including or
558 /// after the current position.
559 LLVM_ABI SlotIndex getCurrSlot() const;
560
561 LLVM_ABI void bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs);
562
563 LLVM_ABI void bumpUpwardPressure(const MachineInstr *MI);
564 LLVM_ABI void bumpDownwardPressure(const MachineInstr *MI);
565
566 LLVM_ABI void
567 discoverLiveInOrOut(VRegMaskOrUnit Pair,
568 SmallVectorImpl<VRegMaskOrUnit> &LiveInOrOut);
569
570 LLVM_ABI LaneBitmask getLastUsedLanes(VirtRegOrUnit VRegOrUnit,
571 SlotIndex Pos) const;
572 LLVM_ABI LaneBitmask getLiveLanesAt(VirtRegOrUnit VRegOrUnit,
573 SlotIndex Pos) const;
574 LLVM_ABI LaneBitmask getLiveThroughAt(VirtRegOrUnit VRegOrUnit,
575 SlotIndex Pos) const;
576};
577
578LLVM_ABI void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
579 const TargetRegisterInfo *TRI);
580
581} // end namespace llvm
582
583#endif // LLVM_CODEGEN_REGISTERPRESSURE_H
584