1//===- RegisterPressure.h - Dynamic Register Pressure -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the RegisterPressure class which can be used to track
10// MachineInstr level register pressure.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
15#define LLVM_CODEGEN_REGISTERPRESSURE_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/ADT/SparseSet.h"
20#include "llvm/CodeGen/MachineBasicBlock.h"
21#include "llvm/CodeGen/SlotIndexes.h"
22#include "llvm/CodeGen/TargetRegisterInfo.h"
23#include "llvm/MC/LaneBitmask.h"
24#include "llvm/Support/Compiler.h"
25#include <cassert>
26#include <cstdint>
27#include <cstdlib>
28#include <limits>
29#include <vector>
30
31namespace llvm {
32
33class LiveIntervals;
34class MachineFunction;
35class MachineInstr;
36class MachineRegisterInfo;
37class RegisterClassInfo;
38
39struct VRegMaskOrUnit {
40 VirtRegOrUnit VRegOrUnit;
41 LaneBitmask LaneMask;
42
43 VRegMaskOrUnit(VirtRegOrUnit VRegOrUnit, LaneBitmask LaneMask)
44 : VRegOrUnit(VRegOrUnit), LaneMask(LaneMask) {}
45};
46
47/// Base class for register pressure results.
48struct RegisterPressure {
49 /// Map of max reg pressure indexed by pressure set ID, not class ID.
50 std::vector<unsigned> MaxSetPressure;
51
52 /// List of live in virtual registers or physical register units.
53 SmallVector<VRegMaskOrUnit, 8> LiveInRegs;
54 SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
55
56 LLVM_ABI void dump(const TargetRegisterInfo *TRI) const;
57};
58
59/// RegisterPressure computed within a region of instructions delimited by
60/// TopIdx and BottomIdx. During pressure computation, the maximum pressure per
61/// register pressure set is increased. Once pressure within a region is fully
62/// computed, the live-in and live-out sets are recorded.
63///
64/// This is preferable to RegionPressure when LiveIntervals are available,
65/// because delimiting regions by SlotIndex is more robust and convenient than
66/// holding block iterators. The block contents can change without invalidating
67/// the pressure result.
68struct IntervalPressure : RegisterPressure {
69 /// Record the boundary of the region being tracked.
70 SlotIndex TopIdx;
71 SlotIndex BottomIdx;
72
73 LLVM_ABI void reset();
74
75 LLVM_ABI void openTop(SlotIndex NextTop);
76
77 LLVM_ABI void openBottom(SlotIndex PrevBottom);
78};
79
80/// RegisterPressure computed within a region of instructions delimited by
81/// TopPos and BottomPos. This is a less precise version of IntervalPressure for
82/// use when LiveIntervals are unavailable.
83struct RegionPressure : RegisterPressure {
84 /// Record the boundary of the region being tracked.
85 MachineBasicBlock::const_iterator TopPos;
86 MachineBasicBlock::const_iterator BottomPos;
87
88 LLVM_ABI void reset();
89
90 LLVM_ABI void openTop(MachineBasicBlock::const_iterator PrevTop);
91
92 LLVM_ABI void openBottom(MachineBasicBlock::const_iterator PrevBottom);
93};
94
95/// Capture a change in pressure for a single pressure set. UnitInc may be
96/// expressed in terms of upward or downward pressure depending on the client
97/// and will be dynamically adjusted for current liveness.
98///
99/// Pressure increments are tiny, typically 1-2 units, and this is only for
100/// heuristics, so we don't check UnitInc overflow. Instead, we may have a
101/// higher level assert that pressure is consistent within a region. We also
102/// effectively ignore dead defs which don't affect heuristics much.
103class PressureChange {
104 uint16_t PSetID = 0; // ID+1. 0=Invalid.
105 int16_t UnitInc = 0;
106
107public:
108 PressureChange() = default;
109 PressureChange(unsigned id): PSetID(id + 1) {
110 assert(id < std::numeric_limits<uint16_t>::max() && "PSetID overflow.");
111 }
112
113 bool isValid() const { return PSetID > 0; }
114
115 unsigned getPSet() const {
116 assert(isValid() && "invalid PressureChange");
117 return PSetID - 1;
118 }
119
120 // If PSetID is invalid, return UINT16_MAX to give it lowest priority.
121 unsigned getPSetOrMax() const {
122 return (PSetID - 1) & std::numeric_limits<uint16_t>::max();
123 }
124
125 int getUnitInc() const { return UnitInc; }
126
127 void setUnitInc(int Inc) { UnitInc = Inc; }
128
129 bool operator==(const PressureChange &RHS) const {
130 return PSetID == RHS.PSetID && UnitInc == RHS.UnitInc;
131 }
132
133 LLVM_ABI void dump() const;
134};
135
136/// List of PressureChanges in order of increasing, unique PSetID.
137///
138/// Use a small fixed number, because we can fit more PressureChanges in an
139/// empty SmallVector than ever need to be tracked per register class. If more
140/// PSets are affected, then we only track the most constrained.
141class PressureDiff {
142 // The initial design was for MaxPSets=4, but that requires PSet partitions,
143 // which are not yet implemented. (PSet partitions are equivalent PSets given
144 // the register classes actually in use within the scheduling region.)
145 enum { MaxPSets = 16 };
146
147 PressureChange PressureChanges[MaxPSets];
148
149 using iterator = PressureChange *;
150
151 iterator nonconst_begin() { return &PressureChanges[0]; }
152 iterator nonconst_end() { return &PressureChanges[MaxPSets]; }
153
154public:
155 using const_iterator = const PressureChange *;
156
157 const_iterator begin() const { return &PressureChanges[0]; }
158 const_iterator end() const { return &PressureChanges[MaxPSets]; }
159
160 LLVM_ABI void addPressureChange(VirtRegOrUnit VRegOrUnit, bool IsDec,
161 const MachineRegisterInfo *MRI);
162
163 LLVM_ABI void dump(const TargetRegisterInfo &TRI) const;
164};
165
166/// List of registers defined and used by a machine instruction.
167class RegisterOperands {
168public:
169 /// List of virtual registers and register units read by the instruction.
170 SmallVector<VRegMaskOrUnit, 8> Uses;
171 /// List of virtual registers and register units defined by the
172 /// instruction which are not dead.
173 SmallVector<VRegMaskOrUnit, 8> Defs;
174 /// List of virtual registers and register units defined by the
175 /// instruction but dead.
176 SmallVector<VRegMaskOrUnit, 8> DeadDefs;
177
178 /// Analyze the given instruction \p MI and fill in the Uses, Defs and
179 /// DeadDefs list based on the MachineOperand flags.
180 LLVM_ABI void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
181 const MachineRegisterInfo &MRI, bool TrackLaneMasks,
182 bool IgnoreDead);
183
184 /// Use liveness information to find dead defs not marked with a dead flag
185 /// and move them to the DeadDefs vector.
186 LLVM_ABI void detectDeadDefs(const MachineInstr &MI,
187 const LiveIntervals &LIS);
188
189 /// Use liveness information to find out which uses/defs are partially
190 /// undefined/dead at \p Pos and adjust the VRegMaskOrUnits accordingly.
191 LLVM_ABI void adjustLaneLiveness(const LiveIntervals &LIS,
192 const MachineRegisterInfo &MRI,
193 SlotIndex Pos);
194
195 /// Use liveness information to find out which uses/defs are partially
196 /// undefined/dead at the \p MI's position and adjust the VRegMaskOrUnits
197 /// accordingly. Missing read-undef and dead flags are added to \p MI.
198 LLVM_ABI void adjustLaneLiveness(const LiveIntervals &LIS,
199 const MachineRegisterInfo &MRI,
200 MachineInstr &MI);
201
202private:
203 /// Adjusts the \p Def based on \p LiveAfterDef. The \p Def is removed from
204 /// the Defs vector when no defined lane remains live after the def. Returns a
205 /// pointer to the next definition to process in order in the Defs vector.
206 VRegMaskOrUnit *adjustDef(VRegMaskOrUnit &Def, LaneBitmask LiveAfterDef);
207
208 /// Use liveness information at \p Pos to adjust the lanemask of all uses.
209 void adjustUses(const LiveIntervals &LIS, const MachineRegisterInfo &MRI,
210 SlotIndex Pos);
211};
212
213/// Array of PressureDiffs.
214class PressureDiffs {
215 PressureDiff *PDiffArray = nullptr;
216 unsigned Size = 0;
217 unsigned Max = 0;
218
219public:
220 PressureDiffs() = default;
221 PressureDiffs &operator=(const PressureDiffs &other) = delete;
222 PressureDiffs(const PressureDiffs &other) = delete;
223 ~PressureDiffs() { free(ptr: PDiffArray); }
224
225 void clear() { Size = 0; }
226
227 LLVM_ABI void init(unsigned N);
228
229 PressureDiff &operator[](unsigned Idx) {
230 assert(Idx < Size && "PressureDiff index out of bounds");
231 return PDiffArray[Idx];
232 }
233 const PressureDiff &operator[](unsigned Idx) const {
234 return const_cast<PressureDiffs*>(this)->operator[](Idx);
235 }
236
237 /// Record pressure difference induced by the given operand list to
238 /// node with index \p Idx.
239 LLVM_ABI void addInstruction(unsigned Idx, const RegisterOperands &RegOpers,
240 const MachineRegisterInfo &MRI);
241};
242
243/// Store the effects of a change in pressure on things that MI scheduler cares
244/// about.
245///
246/// Excess records the value of the largest difference in register units beyond
247/// the target's pressure limits across the affected pressure sets, where
248/// largest is defined as the absolute value of the difference. Negative
249/// ExcessUnits indicates a reduction in pressure that had already exceeded the
250/// target's limits.
251///
252/// CriticalMax records the largest increase in the tracker's max pressure that
253/// exceeds the critical limit for some pressure set determined by the client.
254///
255/// CurrentMax records the largest increase in the tracker's max pressure that
256/// exceeds the current limit for some pressure set determined by the client.
257struct RegPressureDelta {
258 PressureChange Excess;
259 PressureChange CriticalMax;
260 PressureChange CurrentMax;
261
262 RegPressureDelta() = default;
263
264 bool operator==(const RegPressureDelta &RHS) const {
265 return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
266 && CurrentMax == RHS.CurrentMax;
267 }
268 bool operator!=(const RegPressureDelta &RHS) const {
269 return !operator==(RHS);
270 }
271 LLVM_ABI void dump() const;
272};
273
274/// A set of live virtual registers and physical register units.
275///
276/// This is a wrapper around a SparseSet which deals with mapping register unit
277/// and virtual register indexes to an index usable by the sparse set.
278class LiveRegSet {
279private:
280 struct IndexMaskPair {
281 unsigned Index;
282 LaneBitmask LaneMask;
283
284 IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
285 : Index(Index), LaneMask(LaneMask) {}
286
287 unsigned getSparseSetIndex() const {
288 return Index;
289 }
290 };
291
292 using RegSet = SparseSet<IndexMaskPair>;
293 RegSet Regs;
294 unsigned NumRegUnits = 0u;
295
296 unsigned getSparseIndexFromVirtRegOrUnit(VirtRegOrUnit VRegOrUnit) const {
297 if (VRegOrUnit.isVirtualReg())
298 return VRegOrUnit.asVirtualReg().virtRegIndex() + NumRegUnits;
299 assert(static_cast<unsigned>(VRegOrUnit.asMCRegUnit()) < NumRegUnits);
300 return static_cast<unsigned>(VRegOrUnit.asMCRegUnit());
301 }
302
303 VirtRegOrUnit getVirtRegOrUnitFromSparseIndex(unsigned SparseIndex) const {
304 if (SparseIndex >= NumRegUnits)
305 return VirtRegOrUnit(Register::index2VirtReg(Index: SparseIndex - NumRegUnits));
306 return VirtRegOrUnit(static_cast<MCRegUnit>(SparseIndex));
307 }
308
309public:
310 LLVM_ABI void clear();
311 LLVM_ABI void init(const MachineRegisterInfo &MRI);
312
313 LaneBitmask contains(VirtRegOrUnit VRegOrUnit) const {
314 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit);
315 RegSet::const_iterator I = Regs.find(Key: SparseIndex);
316 if (I == Regs.end())
317 return LaneBitmask::getNone();
318 return I->LaneMask;
319 }
320
321 /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
322 /// Returns the previously live lanes of \p Pair.Reg.
323 LaneBitmask insert(VRegMaskOrUnit Pair) {
324 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit: Pair.VRegOrUnit);
325 auto InsertRes = Regs.insert(Val: IndexMaskPair(SparseIndex, Pair.LaneMask));
326 if (!InsertRes.second) {
327 LaneBitmask PrevMask = InsertRes.first->LaneMask;
328 InsertRes.first->LaneMask |= Pair.LaneMask;
329 return PrevMask;
330 }
331 return LaneBitmask::getNone();
332 }
333
334 /// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
335 /// Returns the previously live lanes of \p Pair.Reg.
336 LaneBitmask erase(VRegMaskOrUnit Pair) {
337 unsigned SparseIndex = getSparseIndexFromVirtRegOrUnit(VRegOrUnit: Pair.VRegOrUnit);
338 RegSet::iterator I = Regs.find(Key: SparseIndex);
339 if (I == Regs.end())
340 return LaneBitmask::getNone();
341 LaneBitmask PrevMask = I->LaneMask;
342 I->LaneMask &= ~Pair.LaneMask;
343 return PrevMask;
344 }
345
346 size_t size() const {
347 return Regs.size();
348 }
349
350 void appendTo(SmallVectorImpl<VRegMaskOrUnit> &To) const {
351 for (const IndexMaskPair &P : Regs) {
352 VirtRegOrUnit VRegOrUnit = getVirtRegOrUnitFromSparseIndex(SparseIndex: P.Index);
353 if (P.LaneMask.any())
354 To.emplace_back(Args&: VRegOrUnit, Args: P.LaneMask);
355 }
356 }
357};
358
359/// Track the current register pressure at some position in the instruction
360/// stream, and remember the high water mark within the region traversed. This
361/// does not automatically consider live-through ranges. The client may
362/// independently adjust for global liveness.
363///
364/// Each RegPressureTracker only works within a MachineBasicBlock. Pressure can
365/// be tracked across a larger region by storing a RegisterPressure result at
366/// each block boundary and explicitly adjusting pressure to account for block
367/// live-in and live-out register sets.
368///
369/// RegPressureTracker holds a reference to a RegisterPressure result that it
370/// computes incrementally. During downward tracking, P.BottomIdx or P.BottomPos
371/// is invalid until it reaches the end of the block or closeRegion() is
372/// explicitly called. Similarly, P.TopIdx is invalid during upward
373/// tracking. Changing direction has the side effect of closing region, and
374/// traversing past TopIdx or BottomIdx reopens it.
375class RegPressureTracker {
376 const MachineFunction *MF = nullptr;
377 const TargetRegisterInfo *TRI = nullptr;
378 const RegisterClassInfo *RCI = nullptr;
379 const MachineRegisterInfo *MRI = nullptr;
380 const LiveIntervals *LIS = nullptr;
381
382 /// We currently only allow pressure tracking within a block.
383 const MachineBasicBlock *MBB = nullptr;
384
385 /// Track the max pressure within the region traversed so far.
386 RegisterPressure &P;
387
388 /// Run in two modes dependending on whether constructed with IntervalPressure
389 /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
390 bool RequireIntervals;
391
392 /// True if UntiedDefs will be populated.
393 bool TrackUntiedDefs = false;
394
395 /// True if lanemasks should be tracked.
396 bool TrackLaneMasks = false;
397
398 /// Register pressure corresponds to liveness before this instruction
399 /// iterator. It may point to the end of the block or a DebugValue rather than
400 /// an instruction.
401 MachineBasicBlock::const_iterator CurrPos;
402
403 /// Pressure map indexed by pressure set ID, not class ID.
404 std::vector<unsigned> CurrSetPressure;
405
406 /// Set of live registers.
407 LiveRegSet LiveRegs;
408
409 /// Set of vreg defs that start a live range.
410 SparseSet<Register, Register, VirtReg2IndexFunctor> UntiedDefs;
411 /// Live-through pressure.
412 std::vector<unsigned> LiveThruPressure;
413
414public:
415 RegPressureTracker(IntervalPressure &rp) : P(rp), RequireIntervals(true) {}
416 RegPressureTracker(RegionPressure &rp) : P(rp), RequireIntervals(false) {}
417
418 LLVM_ABI void reset();
419
420 LLVM_ABI void init(const MachineFunction *mf, const RegisterClassInfo *rci,
421 const LiveIntervals *lis, const MachineBasicBlock *mbb,
422 MachineBasicBlock::const_iterator pos, bool TrackLaneMasks,
423 bool TrackUntiedDefs);
424
425 /// Force liveness of virtual registers or physical register
426 /// units. Particularly useful to initialize the livein/out state of the
427 /// tracker before the first call to advance/recede.
428 LLVM_ABI void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
429
430 /// Get the MI position corresponding to this register pressure.
431 MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
432
433 // Reset the MI position corresponding to the register pressure. This allows
434 // schedulers to move instructions above the RegPressureTracker's
435 // CurrPos. Since the pressure is computed before CurrPos, the iterator
436 // position changes while pressure does not.
437 void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
438
439 /// Recede across the previous instruction.
440 LLVM_ABI void recede(SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
441
442 /// Recede across the previous instruction.
443 /// This "low-level" variant assumes that recedeSkipDebugValues() was
444 /// called previously and takes precomputed RegisterOperands for the
445 /// instruction.
446 LLVM_ABI void recede(const RegisterOperands &RegOpers,
447 SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
448
449 /// Recede until we find an instruction which is not a DebugValue.
450 LLVM_ABI void recedeSkipDebugValues();
451
452 /// Advance across the current instruction.
453 LLVM_ABI void advance();
454
455 /// Advance across the current instruction.
456 /// This is a "low-level" variant of advance() which takes precomputed
457 /// RegisterOperands of the instruction.
458 LLVM_ABI void advance(const RegisterOperands &RegOpers);
459
460 /// Finalize the region boundaries and recored live ins and live outs.
461 LLVM_ABI void closeRegion();
462
463 /// Initialize the LiveThru pressure set based on the untied defs found in
464 /// RPTracker.
465 LLVM_ABI void initLiveThru(const RegPressureTracker &RPTracker);
466
467 /// Copy an existing live thru pressure result.
468 void initLiveThru(ArrayRef<unsigned> PressureSet) {
469 LiveThruPressure.assign(first: PressureSet.begin(), last: PressureSet.end());
470 }
471
472 ArrayRef<unsigned> getLiveThru() const { return LiveThruPressure; }
473
474 /// Get the resulting register pressure over the traversed region.
475 /// This result is complete if closeRegion() was explicitly invoked.
476 RegisterPressure &getPressure() { return P; }
477 const RegisterPressure &getPressure() const { return P; }
478
479 /// Get the register set pressure at the current position, which may be less
480 /// than the pressure across the traversed region.
481 const std::vector<unsigned> &getRegSetPressureAtPos() const {
482 return CurrSetPressure;
483 }
484
485 LLVM_ABI bool isTopClosed() const;
486 LLVM_ABI bool isBottomClosed() const;
487
488 LLVM_ABI void closeTop();
489 LLVM_ABI void closeBottom();
490
491 /// Consider the pressure increase caused by traversing this instruction
492 /// bottom-up. Find the pressure set with the most change beyond its pressure
493 /// limit based on the tracker's current pressure, and record the number of
494 /// excess register units of that pressure set introduced by this instruction.
495 LLVM_ABI void
496 getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff,
497 RegPressureDelta &Delta,
498 ArrayRef<PressureChange> CriticalPSets,
499 ArrayRef<unsigned> MaxPressureLimit);
500
501 LLVM_ABI void
502 getUpwardPressureDelta(const MachineInstr *MI,
503 /*const*/ PressureDiff &PDiff, RegPressureDelta &Delta,
504 ArrayRef<PressureChange> CriticalPSets,
505 ArrayRef<unsigned> MaxPressureLimit) const;
506
507 /// Consider the pressure increase caused by traversing this instruction
508 /// top-down. Find the pressure set with the most change beyond its pressure
509 /// limit based on the tracker's current pressure, and record the number of
510 /// excess register units of that pressure set introduced by this instruction.
511 LLVM_ABI void
512 getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta,
513 ArrayRef<PressureChange> CriticalPSets,
514 ArrayRef<unsigned> MaxPressureLimit);
515
516 /// Find the pressure set with the most change beyond its pressure limit after
517 /// traversing this instruction either upward or downward depending on the
518 /// closed end of the current region.
519 void getMaxPressureDelta(const MachineInstr *MI,
520 RegPressureDelta &Delta,
521 ArrayRef<PressureChange> CriticalPSets,
522 ArrayRef<unsigned> MaxPressureLimit) {
523 if (isTopClosed())
524 return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,
525 MaxPressureLimit);
526
527 assert(isBottomClosed() && "Uninitialized pressure tracker");
528 return getMaxUpwardPressureDelta(MI, PDiff: nullptr, Delta, CriticalPSets,
529 MaxPressureLimit);
530 }
531
532 /// Get the pressure of each PSet after traversing this instruction bottom-up.
533 LLVM_ABI void getUpwardPressure(const MachineInstr *MI,
534 std::vector<unsigned> &PressureResult,
535 std::vector<unsigned> &MaxPressureResult);
536
537 /// Get the pressure of each PSet after traversing this instruction top-down.
538 LLVM_ABI void getDownwardPressure(const MachineInstr *MI,
539 std::vector<unsigned> &PressureResult,
540 std::vector<unsigned> &MaxPressureResult);
541
542 void getPressureAfterInst(const MachineInstr *MI,
543 std::vector<unsigned> &PressureResult,
544 std::vector<unsigned> &MaxPressureResult) {
545 if (isTopClosed())
546 return getUpwardPressure(MI, PressureResult, MaxPressureResult);
547
548 assert(isBottomClosed() && "Uninitialized pressure tracker");
549 return getDownwardPressure(MI, PressureResult, MaxPressureResult);
550 }
551
552 bool hasUntiedDef(Register VirtReg) const {
553 return UntiedDefs.count(Key: VirtReg);
554 }
555
556 LLVM_ABI void dump() const;
557
558 LLVM_ABI void increaseRegPressure(VirtRegOrUnit VRegOrUnit,
559 LaneBitmask PreviousMask,
560 LaneBitmask NewMask);
561 LLVM_ABI void decreaseRegPressure(VirtRegOrUnit VRegOrUnit,
562 LaneBitmask PreviousMask,
563 LaneBitmask NewMask);
564
565protected:
566 /// Add Reg to the live out set and increase max pressure.
567 LLVM_ABI void discoverLiveOut(VRegMaskOrUnit Pair);
568 /// Add Reg to the live in set and increase max pressure.
569 LLVM_ABI void discoverLiveIn(VRegMaskOrUnit Pair);
570
571 /// Get the SlotIndex for the first nondebug instruction including or
572 /// after the current position.
573 LLVM_ABI SlotIndex getCurrSlot() const;
574
575 LLVM_ABI void bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs);
576
577 LLVM_ABI void bumpUpwardPressure(const MachineInstr *MI);
578 LLVM_ABI void bumpDownwardPressure(const MachineInstr *MI);
579
580 LLVM_ABI void
581 discoverLiveInOrOut(VRegMaskOrUnit Pair,
582 SmallVectorImpl<VRegMaskOrUnit> &LiveInOrOut);
583
584 LLVM_ABI LaneBitmask getLastUsedLanes(VirtRegOrUnit VRegOrUnit,
585 SlotIndex Pos) const;
586 LLVM_ABI LaneBitmask getLiveLanesAt(VirtRegOrUnit VRegOrUnit,
587 SlotIndex Pos) const;
588 LLVM_ABI LaneBitmask getLiveThroughAt(VirtRegOrUnit VRegOrUnit,
589 SlotIndex Pos) const;
590};
591
592LLVM_ABI void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
593 const TargetRegisterInfo *TRI);
594
595} // end namespace llvm
596
597#endif // LLVM_CODEGEN_REGISTERPRESSURE_H
598