1//===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// Target-Independent Code Generator Pass Configuration Options pass.
10///
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
14#define LLVM_CODEGEN_TARGETPASSCONFIG_H
15
16#include "llvm/Pass.h"
17#include "llvm/Support/CodeGen.h"
18#include "llvm/Support/Compiler.h"
19#include "llvm/Support/Error.h"
20#include <cassert>
21#include <string>
22
23namespace llvm {
24
25class TargetMachine;
26class PassConfigImpl;
27class CSEConfigBase;
28class PassInstrumentationCallbacks;
29
30// The old pass manager infrastructure is hidden in a legacy namespace now.
31namespace legacy {
32
33class PassManagerBase;
34
35} // end namespace legacy
36
37using legacy::PassManagerBase;
38
39/// Discriminated union of Pass ID types.
40///
41/// The PassConfig API prefers dealing with IDs because they are safer and more
42/// efficient. IDs decouple configuration from instantiation. This way, when a
43/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
44/// refer to a Pass pointer after adding it to a pass manager, which deletes
45/// redundant pass instances.
46///
47/// However, it is convient to directly instantiate target passes with
48/// non-default ctors. These often don't have a registered PassInfo. Rather than
49/// force all target passes to implement the pass registry boilerplate, allow
50/// the PassConfig API to handle either type.
51///
52/// AnalysisID is sadly char*, so PointerIntPair won't work.
53class IdentifyingPassPtr {
54 union {
55 AnalysisID ID;
56 Pass *P;
57 };
58 bool IsInstance = false;
59
60public:
61 IdentifyingPassPtr() : P(nullptr) {}
62 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
63 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
64
65 bool isValid() const { return P; }
66 bool isInstance() const { return IsInstance; }
67
68 AnalysisID getID() const {
69 assert(!IsInstance && "Not a Pass ID");
70 return ID;
71 }
72
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
75 return P;
76 }
77};
78
79
80/// Target-Independent Code Generator Pass Configuration Options.
81///
82/// This is an ImmutablePass solely for the purpose of exposing CodeGen options
83/// to the internals of other CodeGen passes.
84class LLVM_ABI TargetPassConfig : public ImmutablePass {
85private:
86 PassManagerBase *PM = nullptr;
87 AnalysisID StartBefore = nullptr;
88 AnalysisID StartAfter = nullptr;
89 AnalysisID StopBefore = nullptr;
90 AnalysisID StopAfter = nullptr;
91
92 unsigned StartBeforeInstanceNum = 0;
93 unsigned StartBeforeCount = 0;
94
95 unsigned StartAfterInstanceNum = 0;
96 unsigned StartAfterCount = 0;
97
98 unsigned StopBeforeInstanceNum = 0;
99 unsigned StopBeforeCount = 0;
100
101 unsigned StopAfterInstanceNum = 0;
102 unsigned StopAfterCount = 0;
103
104 bool Started = true;
105 bool Stopped = false;
106 bool AddingMachinePasses = false;
107 bool DebugifyIsSafe = true;
108
109 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
110 /// a portion of the normal code-gen pass sequence.
111 ///
112 /// If the StartAfter and StartBefore pass ID is zero, then compilation will
113 /// begin at the normal point; otherwise, clear the Started flag to indicate
114 /// that passes should not be added until the starting pass is seen. If the
115 /// Stop pass ID is zero, then compilation will continue to the end.
116 ///
117 /// This function expects that at least one of the StartAfter or the
118 /// StartBefore pass IDs is null.
119 void setStartStopPasses();
120
121protected:
122 TargetMachine *TM;
123 PassConfigImpl *Impl = nullptr; // Internal data structures
124 bool Initialized = false; // Flagged after all passes are configured.
125
126 // Target Pass Options
127 // Targets provide a default setting, user flags override.
128 bool DisableVerify = false;
129
130 /// Default setting for -enable-tail-merge on this target.
131 bool EnableTailMerge = true;
132
133 /// Enable sinking of instructions in MachineSink where a computation can be
134 /// folded into the addressing mode of a memory load/store instruction or
135 /// replace a copy.
136 bool EnableSinkAndFold = false;
137
138 /// Enable insertion of SSAMachineScheduler pass, this triggers early
139 /// computation of live intervals.
140 bool EnableSSAMachineScheduler = false;
141
142 /// Require processing of functions such that callees are generated before
143 /// callers.
144 bool RequireCodeGenSCCOrder = false;
145
146 /// Enable LoopTermFold immediately after LSR
147 bool EnableLoopTermFold = false;
148
149 /// Add the actual instruction selection passes. This does not include
150 /// preparation passes on IR.
151 bool addCoreISelPasses();
152
153public:
154 TargetPassConfig(TargetMachine &TM, PassManagerBase &PM);
155 // Dummy constructor.
156 TargetPassConfig();
157
158 ~TargetPassConfig() override;
159
160 static char ID;
161
162 /// Get the right type of TargetMachine for this target.
163 template<typename TMC> TMC &getTM() const {
164 return *static_cast<TMC*>(TM);
165 }
166
167 //
168 void setInitialized() { Initialized = true; }
169
170 CodeGenOptLevel getOptLevel() const;
171
172 /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
173 /// or `-stop-before` options is set.
174 static bool hasLimitedCodeGenPipeline();
175
176 /// Returns true if none of the `-stop-before` and `-stop-after` options is
177 /// set.
178 static bool willCompleteCodeGenPipeline();
179
180 /// If hasLimitedCodeGenPipeline is true, this method returns
181 /// a string with the name of the options that caused this
182 /// pipeline to be limited.
183 static std::string getLimitedCodeGenPipelineReason();
184
185 struct StartStopInfo {
186 bool StartAfter;
187 bool StopAfter;
188 unsigned StartInstanceNum;
189 unsigned StopInstanceNum;
190 StringRef StartPass;
191 StringRef StopPass;
192 };
193
194 /// Returns pass name in `-stop-before` or `-stop-after`
195 /// NOTE: New pass manager migration only
196 static Expected<StartStopInfo>
197 getStartStopInfo(PassInstrumentationCallbacks &PIC);
198
199 void setDisableVerify(bool Disable) { setOpt(Opt&: DisableVerify, Val: Disable); }
200
201 bool getEnableTailMerge() const { return EnableTailMerge; }
202 void setEnableTailMerge(bool Enable) { setOpt(Opt&: EnableTailMerge, Val: Enable); }
203
204 bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
205 void setEnableSinkAndFold(bool Enable) { setOpt(Opt&: EnableSinkAndFold, Val: Enable); }
206
207 bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
208 void setRequiresCodeGenSCCOrder(bool Enable = true) {
209 setOpt(Opt&: RequireCodeGenSCCOrder, Val: Enable);
210 }
211
212 bool getEnableSSAMachineScheduler() const {
213 return EnableSSAMachineScheduler;
214 }
215 void setEnableSSAMachineScheduler(bool Enable) {
216 setOpt(Opt&: EnableSSAMachineScheduler, Val: Enable);
217 }
218
219 /// Allow the target to override a specific pass without overriding the pass
220 /// pipeline. When passes are added to the standard pipeline at the
221 /// point where StandardID is expected, add TargetID in its place.
222 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
223
224 /// Insert InsertedPassID pass after TargetPassID pass.
225 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
226
227 /// Allow the target to enable a specific standard pass by default.
228 void enablePass(AnalysisID PassID) { substitutePass(StandardID: PassID, TargetID: PassID); }
229
230 /// Allow the target to disable a specific standard pass by default.
231 void disablePass(AnalysisID PassID) {
232 substitutePass(StandardID: PassID, TargetID: IdentifyingPassPtr());
233 }
234
235 /// Return the pass substituted for StandardID by the target.
236 /// If no substitution exists, return StandardID.
237 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
238
239 /// Return true if the pass has been substituted by the target or
240 /// overridden on the command line.
241 bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
242
243 /// Return true if the optimized regalloc pipeline is enabled.
244 bool getOptimizeRegAlloc() const;
245
246 /// Return true if the default global register allocator is in use and
247 /// has not be overriden on the command line with '-regalloc=...'
248 bool usingDefaultRegAlloc() const;
249
250 /// High level function that adds all passes necessary to go from llvm IR
251 /// representation to the MI representation.
252 /// Adds IR based lowering and target specific optimization passes and finally
253 /// the core instruction selection passes.
254 /// \returns true if an error occurred, false otherwise.
255 bool addISelPasses();
256
257 /// Add common target configurable passes that perform LLVM IR to IR
258 /// transforms following machine independent optimization.
259 virtual void addIRPasses();
260
261 /// Add passes to lower exception handling for the code generator.
262 void addPassesToHandleExceptions();
263
264 /// Add pass to prepare the LLVM IR for code generation. This should be done
265 /// before exception handling preparation passes.
266 virtual void addCodeGenPrepare();
267
268 /// Add common passes that perform LLVM IR to IR transforms in preparation for
269 /// instruction selection.
270 virtual void addISelPrepare();
271
272 /// addInstSelector - This method should install an instruction selector pass,
273 /// which converts from LLVM code to machine instructions.
274 virtual bool addInstSelector() {
275 return true;
276 }
277
278 /// This method should install an IR translator pass, which converts from
279 /// LLVM code to machine instructions with possibly generic opcodes.
280 virtual bool addIRTranslator() { return true; }
281
282 /// This method may be implemented by targets that want to run passes
283 /// immediately before legalization.
284 virtual void addPreLegalizeMachineIR() {}
285
286 /// This method should install a legalize pass, which converts the instruction
287 /// sequence into one that can be selected by the target.
288 virtual bool addLegalizeMachineIR() { return true; }
289
290 /// This method may be implemented by targets that want to run passes
291 /// immediately before the register bank selection.
292 virtual void addPreRegBankSelect() {}
293
294 /// This method should install a register bank selector pass, which
295 /// assigns register banks to virtual registers without a register
296 /// class or register banks.
297 virtual bool addRegBankSelect() { return true; }
298
299 /// This method may be implemented by targets that want to run passes
300 /// immediately before the (global) instruction selection.
301 virtual void addPreGlobalInstructionSelect() {}
302
303 /// This method should install a (global) instruction selector pass, which
304 /// converts possibly generic instructions to fully target-specific
305 /// instructions, thereby constraining all generic virtual registers to
306 /// register classes.
307 virtual bool addGlobalInstructionSelect() { return true; }
308
309 /// Add the complete, standard set of LLVM CodeGen passes.
310 /// Fully developed targets will not generally override this.
311 virtual void addMachinePasses();
312
313 /// printAndVerify - Add a pass to dump then verify the machine function, if
314 /// those steps are enabled.
315 void printAndVerify(const std::string &Banner);
316
317 /// Add a pass to print the machine function if printing is enabled.
318 void addPrintPass(const std::string &Banner);
319
320 /// Add a pass to perform basic verification of the machine function if
321 /// verification is enabled.
322 void addVerifyPass(const std::string &Banner);
323
324 /// Add a pass to add synthesized debug info to the MIR.
325 void addDebugifyPass();
326
327 /// Add a pass to remove debug info from the MIR.
328 void addStripDebugPass();
329
330 /// Add a pass to check synthesized debug info for MIR.
331 void addCheckDebugPass();
332
333 /// Add standard passes before a pass that's about to be added. For example,
334 /// the DebugifyMachineModulePass if it is enabled.
335 void addMachinePrePasses(bool AllowDebugify = true);
336
337 /// Add standard passes after a pass that has just been added. For example,
338 /// the MachineVerifier if it is enabled.
339 void addMachinePostPasses(const std::string &Banner);
340
341 /// Check whether or not GlobalISel should abort on error.
342 /// When this is disabled, GlobalISel will fall back on SDISel instead of
343 /// erroring out.
344 bool isGlobalISelAbortEnabled() const;
345
346 /// Check whether or not a diagnostic should be emitted when GlobalISel
347 /// uses the fallback path. In other words, it will emit a diagnostic
348 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
349 virtual bool reportDiagnosticWhenGlobalISelFallback() const;
350
351 /// Returns the CSEConfig object to use for the current optimization level.
352 virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const;
353
354protected:
355 // Helper to verify the analysis is really immutable.
356 void setOpt(bool &Opt, bool Val);
357
358 /// Return true if register allocator is specified by -regalloc=override.
359 bool isCustomizedRegAlloc();
360
361 /// Methods with trivial inline returns are convenient points in the common
362 /// codegen pass pipeline where targets may insert passes. Methods with
363 /// out-of-line standard implementations are major CodeGen stages called by
364 /// addMachinePasses. Some targets may override major stages when inserting
365 /// passes is insufficient, but maintaining overriden stages is more work.
366 ///
367
368 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
369 /// passes (which are run just before instruction selector).
370 virtual bool addPreISel() {
371 return true;
372 }
373
374 /// addMachineSSAOptimization - Add standard passes that optimize machine
375 /// instructions in SSA form.
376 virtual void addMachineSSAOptimization();
377
378 /// Add passes that optimize instruction level parallelism for out-of-order
379 /// targets. These passes are run while the machine code is still in SSA
380 /// form, so they can use MachineTraceMetrics to control their heuristics.
381 ///
382 /// All passes added here should preserve the MachineDominatorTree,
383 /// MachineLoopInfo, and MachineTraceMetrics analyses.
384 virtual bool addILPOpts() {
385 return false;
386 }
387
388 /// This method may be implemented by targets that want to run passes
389 /// immediately before register allocation.
390 virtual void addPreRegAlloc() { }
391
392 /// createTargetRegisterAllocator - Create the register allocator pass for
393 /// this target at the current optimization level.
394 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
395
396 /// addFastRegAlloc - Add the minimum set of target-independent passes that
397 /// are required for fast register allocation.
398 virtual void addFastRegAlloc();
399
400 /// addOptimizedRegAlloc - Add passes related to register allocation.
401 /// CodeGenTargetMachineImpl provides standard regalloc passes for most
402 /// targets.
403 virtual void addOptimizedRegAlloc();
404
405 /// addPreRewrite - Add passes to the optimized register allocation pipeline
406 /// after register allocation is complete, but before virtual registers are
407 /// rewritten to physical registers.
408 ///
409 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
410 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
411 /// When these passes run, VirtRegMap contains legal physreg assignments for
412 /// all virtual registers.
413 ///
414 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
415 /// be honored. This is also not generally used for the fast variant,
416 /// where the allocation and rewriting are done in one pass.
417 virtual bool addPreRewrite() {
418 return false;
419 }
420
421 /// addPostFastRegAllocRewrite - Add passes to the optimized register
422 /// allocation pipeline after fast register allocation is complete.
423 virtual bool addPostFastRegAllocRewrite() { return false; }
424
425 /// Add passes to be run immediately after virtual registers are rewritten
426 /// to physical registers.
427 virtual void addPostRewrite() { }
428
429 /// This method may be implemented by targets that want to run passes after
430 /// register allocation pass pipeline but before prolog-epilog insertion.
431 virtual void addPostRegAlloc() { }
432
433 /// Add passes that optimize machine instructions after register allocation.
434 virtual void addMachineLateOptimization();
435
436 /// This method may be implemented by targets that want to run passes after
437 /// prolog-epilog insertion and before the second instruction scheduling pass.
438 virtual void addPreSched2() { }
439
440 /// addGCPasses - Add late codegen passes that analyze code for garbage
441 /// collection. This should return true if GC info should be printed after
442 /// these passes.
443 virtual bool addGCPasses();
444
445 /// Add standard basic block placement passes.
446 virtual void addBlockPlacement();
447
448 /// This pass may be implemented by targets that want to run passes
449 /// immediately before machine code is emitted.
450 virtual void addPreEmitPass() { }
451
452 /// This pass may be implemented by targets that want to run passes
453 /// immediately after basic block sections are assigned.
454 virtual void addPostBBSections() {}
455
456 /// Targets may add passes immediately before machine code is emitted in this
457 /// callback. This is called even later than `addPreEmitPass`.
458 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
459 // position and remove the `2` suffix here as this callback is what
460 // `addPreEmitPass` *should* be but in reality isn't.
461 virtual void addPreEmitPass2() {}
462
463 /// Utilities for targets to add passes to the pass manager.
464 ///
465
466 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
467 /// Return the pass that was added, or zero if no pass was added.
468 AnalysisID addPass(AnalysisID PassID);
469
470 /// Add a pass to the PassManager if that pass is supposed to be run, as
471 /// determined by the StartAfter and StopAfter options. Takes ownership of the
472 /// pass.
473 void addPass(Pass *P);
474
475 /// addMachinePasses helper to create the target-selected or overriden
476 /// regalloc pass.
477 virtual FunctionPass *createRegAllocPass(bool Optimized);
478
479 /// Add core register allocator passes which do the actual register assignment
480 /// and rewriting. \returns true if any passes were added.
481 virtual bool addRegAssignAndRewriteFast();
482 virtual bool addRegAssignAndRewriteOptimized();
483};
484
485LLVM_ABI void registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
486 TargetMachine &);
487
488} // end namespace llvm
489
490#endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
491