1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the target independent instruction opcodes.
10//
11//===----------------------------------------------------------------------===//
12
13// NOTE: NO INCLUDE GUARD DESIRED!
14
15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value.
16///
17#ifndef HANDLE_TARGET_OPCODE
18#define HANDLE_TARGET_OPCODE(OPC, NUM)
19#endif
20
21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode.
22///
23#ifndef HANDLE_TARGET_OPCODE_MARKER
24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
25#endif
26
27/// Every instruction defined here must also appear in Target.td.
28///
29HANDLE_TARGET_OPCODE(PHI)
30HANDLE_TARGET_OPCODE(INLINEASM)
31HANDLE_TARGET_OPCODE(INLINEASM_BR)
32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION)
33HANDLE_TARGET_OPCODE(EH_LABEL)
34HANDLE_TARGET_OPCODE(GC_LABEL)
35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL)
36
37/// KILL - This instruction is a noop that is used only to adjust the
38/// liveness of registers. This can be useful when dealing with
39/// sub-registers.
40HANDLE_TARGET_OPCODE(KILL)
41
42/// EXTRACT_SUBREG - This instruction takes two operands: a register
43/// that has subregisters, and a subregister index. It returns the
44/// extracted subregister value. This is commonly used to implement
45/// truncation operations on target architectures which support it.
46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG)
47
48/// INSERT_SUBREG - This instruction takes three operands: a register that
49/// has subregisters, a register providing an insert value, and a
50/// subregister index. It returns the value of the first register with the
51/// value of the second register inserted. The first register is often
52/// defined by an IMPLICIT_DEF, because it is commonly used to implement
53/// anyext operations on target architectures which support it.
54HANDLE_TARGET_OPCODE(INSERT_SUBREG)
55
56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
57HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
58
59/// Explicit undef initialization used past IMPLICIT_DEF elimination in cases
60/// where an undef operand must be allocated to a different register than an
61/// early-clobber result operand.
62HANDLE_TARGET_OPCODE(INIT_UNDEF)
63
64/// SUBREG_TO_REG - Assert the value of bits in a super register.
65/// The result of this instruction is the value of the second operand inserted
66/// into the subregister specified by the third operand. All other bits are
67/// assumed to be equal to the bits in the immediate integer constant in the
68/// first operand. This instruction just communicates information; No code
69/// should be generated.
70/// This is typically used after an instruction where the write to a subregister
71/// implicitly cleared the bits in the super registers.
72HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
73
74/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
75/// register-to-register copy into a specific register class. This is only
76/// used between instruction selection and MachineInstr creation, before
77/// virtual registers have been created for all the instructions, and it's
78/// only needed in cases where the register classes implied by the
79/// instructions are insufficient. It is emitted as a COPY MachineInstr.
80HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS)
81
82/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
83HANDLE_TARGET_OPCODE(DBG_VALUE)
84
85/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic
86/// list of locations
87HANDLE_TARGET_OPCODE(DBG_VALUE_LIST)
88
89/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction
90/// that defines the value, rather than a virtual register.
91HANDLE_TARGET_OPCODE(DBG_INSTR_REF)
92
93/// DBG_PHI - remainder of a PHI, identifies a program point where values
94/// merge under control flow.
95HANDLE_TARGET_OPCODE(DBG_PHI)
96
97/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic
98HANDLE_TARGET_OPCODE(DBG_LABEL)
99
100/// REG_SEQUENCE - This variadic instruction is used to form a register that
101/// represents a consecutive sequence of sub-registers. It's used as a
102/// register coalescing / allocation aid and must be eliminated before code
103/// emission.
104// In SDNode form, the first operand encodes the register class created by
105// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
106// pair. Once it has been lowered to a MachineInstr, the regclass operand
107// is no longer present.
108/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
109/// After register coalescing references of v1024 should be replace with
110/// v1027:3, v1025 with v1027:4, etc.
111HANDLE_TARGET_OPCODE(REG_SEQUENCE)
112
113/// COPY - Target-independent register copy. This instruction can also be
114/// used to copy between subregisters of virtual registers.
115HANDLE_TARGET_OPCODE(COPY)
116
117/// COPY_LANEMASK - Target-independent partial register copy. The laneMask
118/// operand indicates which parts of the source register are copied to the
119/// destination. Other parts of the destination are undefined. It does not
120/// support copy between virtual registers having subregister indices.
121HANDLE_TARGET_OPCODE(COPY_LANEMASK)
122
123/// BUNDLE - This instruction represents an instruction bundle. Instructions
124/// which immediately follow a BUNDLE instruction which are marked with
125/// 'InsideBundle' flag are inside the bundle.
126HANDLE_TARGET_OPCODE(BUNDLE)
127
128/// Lifetime markers.
129HANDLE_TARGET_OPCODE(LIFETIME_START)
130HANDLE_TARGET_OPCODE(LIFETIME_END)
131
132/// Pseudo probe
133HANDLE_TARGET_OPCODE(PSEUDO_PROBE)
134
135/// Arithmetic fence.
136HANDLE_TARGET_OPCODE(ARITH_FENCE)
137
138/// A Stackmap instruction captures the location of live variables at its
139/// position in the instruction stream. It is followed by a shadow of bytes
140/// that must lie within the function and not contain another stackmap.
141HANDLE_TARGET_OPCODE(STACKMAP)
142
143/// FEntry all - This is a marker instruction which gets translated into a raw fentry call.
144HANDLE_TARGET_OPCODE(FENTRY_CALL)
145
146/// Patchable call instruction - this instruction represents a call to a
147/// constant address, followed by a series of NOPs. It is intended to
148/// support optimizations for dynamic languages (such as javascript) that
149/// rewrite calls to runtimes with more efficient code sequences.
150/// This also implies a stack map.
151HANDLE_TARGET_OPCODE(PATCHPOINT)
152
153/// This pseudo-instruction loads the stack guard value. Targets which need
154/// to prevent the stack guard value or address from being spilled to the
155/// stack should override TargetLowering::emitLoadStackGuardNode and
156/// additionally expand this pseudo after register allocation.
157HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD)
158
159/// These are used to support call sites that must have the stack adjusted
160/// before the call (e.g. to initialize an argument passed by value).
161/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details.
162HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP)
163HANDLE_TARGET_OPCODE(PREALLOCATED_ARG)
164
165/// Call instruction with associated vm state for deoptimization and list
166/// of live pointers for relocation by the garbage collector. It is
167/// intended to support garbage collection with fully precise relocating
168/// collectors and deoptimizations in either the callee or caller.
169HANDLE_TARGET_OPCODE(STATEPOINT)
170
171/// Instruction that records the offset of a local stack allocation passed to
172/// llvm.localescape. It has two arguments: the symbol for the label and the
173/// frame index of the local stack allocation.
174HANDLE_TARGET_OPCODE(LOCAL_ESCAPE)
175
176/// Wraps a machine instruction which can fault, bundled with associated
177/// information on how to handle such a fault.
178/// For example loading instruction that may page fault, bundled with associated
179/// information on how to handle such a page fault. It is intended to support
180/// "zero cost" null checks in managed languages by allowing LLVM to fold
181/// comparisons into existing memory operations.
182HANDLE_TARGET_OPCODE(FAULTING_OP)
183
184/// Precedes a machine instruction to add patchability constraints. An
185/// instruction after PATCHABLE_OP has to either have a minimum
186/// size or be preceded with a nop of that size. The first operand is
187/// an immediate denoting the minimum size of the following instruction.
188HANDLE_TARGET_OPCODE(PATCHABLE_OP)
189
190/// This is a marker instruction which gets translated into a nop sled, useful
191/// for inserting instrumentation instructions at runtime.
192HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER)
193
194/// Wraps a return instruction and its operands to enable adding nop sleds
195/// either before or after the return. The nop sleds are useful for inserting
196/// instrumentation instructions at runtime.
197/// The patch here replaces the return instruction.
198HANDLE_TARGET_OPCODE(PATCHABLE_RET)
199
200/// This is a marker instruction which gets translated into a nop sled, useful
201/// for inserting instrumentation instructions at runtime.
202/// The patch here prepends the return instruction.
203/// The same thing as in x86_64 is not possible for ARM because it has multiple
204/// return instructions. Furthermore, CPU allows parametrized and even
205/// conditional return instructions. In the current ARM implementation we are
206/// making use of the fact that currently LLVM doesn't seem to generate
207/// conditional return instructions.
208/// On ARM, the same instruction can be used for popping multiple registers
209/// from the stack and returning (it just pops pc register too), and LLVM
210/// generates it sometimes. So we can't insert the sled between this stack
211/// adjustment and the return without splitting the original instruction into 2
212/// instructions. So on ARM, rather than jumping into the exit trampoline, we
213/// call it, it does the tracing, preserves the stack and returns.
214HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT)
215
216/// Wraps a tail call instruction and its operands to enable adding nop sleds
217/// either before or after the tail exit. We use this as a disambiguation from
218/// PATCHABLE_RET which specifically only works for return instructions.
219HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL)
220
221/// Wraps a logging call and its arguments with nop sleds. At runtime, this can
222/// be patched to insert instrumentation instructions.
223HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL)
224
225/// Wraps a typed logging call and its argument with nop sleds. At runtime, this
226/// can be patched to insert instrumentation instructions.
227HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL)
228
229HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
230
231/// Represents a use of the operand but generates no code.
232HANDLE_TARGET_OPCODE(FAKE_USE)
233
234// This is a fence with the singlethread scope. It represents a compiler memory
235// barrier, but does not correspond to any generated instruction.
236HANDLE_TARGET_OPCODE(MEMBARRIER)
237
238// Provides information about what jump table the following indirect branch is
239// using.
240HANDLE_TARGET_OPCODE(JUMP_TABLE_DEBUG_INFO)
241
242// Issue a no-op relocation against a given symbol at the current location.
243HANDLE_TARGET_OPCODE(RELOC_NONE)
244
245HANDLE_TARGET_OPCODE(CONVERGENCECTRL_ENTRY)
246HANDLE_TARGET_OPCODE(CONVERGENCECTRL_ANCHOR)
247HANDLE_TARGET_OPCODE(CONVERGENCECTRL_LOOP)
248HANDLE_TARGET_OPCODE(CONVERGENCECTRL_GLUE)
249
250/// The following generic opcodes are not supposed to appear after ISel.
251/// This is something we might want to relax, but for now, this is convenient
252/// to produce diagnostics.
253
254/// Instructions which should not exist past instruction selection, but do not
255/// generate code. These instructions only act as optimization hints.
256HANDLE_TARGET_OPCODE(G_ASSERT_SEXT)
257HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT)
258HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN)
259HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START,
260 G_ASSERT_SEXT)
261HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END,
262 G_ASSERT_ALIGN)
263
264/// Generic ADD instruction. This is an integer add.
265HANDLE_TARGET_OPCODE(G_ADD)
266HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
267
268/// Generic SUB instruction. This is an integer sub.
269HANDLE_TARGET_OPCODE(G_SUB)
270
271// Generic multiply instruction.
272HANDLE_TARGET_OPCODE(G_MUL)
273
274// Generic signed division instruction.
275HANDLE_TARGET_OPCODE(G_SDIV)
276
277// Generic unsigned division instruction.
278HANDLE_TARGET_OPCODE(G_UDIV)
279
280// Generic signed remainder instruction.
281HANDLE_TARGET_OPCODE(G_SREM)
282
283// Generic unsigned remainder instruction.
284HANDLE_TARGET_OPCODE(G_UREM)
285
286// Generic signed divrem instruction.
287HANDLE_TARGET_OPCODE(G_SDIVREM)
288
289// Generic unsigned divrem instruction.
290HANDLE_TARGET_OPCODE(G_UDIVREM)
291
292/// Generic bitwise and instruction.
293HANDLE_TARGET_OPCODE(G_AND)
294
295/// Generic bitwise or instruction.
296HANDLE_TARGET_OPCODE(G_OR)
297
298/// Generic bitwise exclusive-or instruction.
299HANDLE_TARGET_OPCODE(G_XOR)
300
301/// Generic absolute difference signed instruction.
302HANDLE_TARGET_OPCODE(G_ABDS)
303
304/// Generic absolute difference unsigned instruction.
305HANDLE_TARGET_OPCODE(G_ABDU)
306
307/// Generic vector average with truncate unsigned instruction.
308HANDLE_TARGET_OPCODE(G_UAVGFLOOR)
309
310/// Generic vector average with round unsigned instruction.
311HANDLE_TARGET_OPCODE(G_UAVGCEIL)
312
313/// Generic vector average with truncate signed instruction.
314HANDLE_TARGET_OPCODE(G_SAVGFLOOR)
315
316/// Generic vector average with round signed instruction.
317HANDLE_TARGET_OPCODE(G_SAVGCEIL)
318
319HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
320
321/// Generic PHI instruction with types.
322HANDLE_TARGET_OPCODE(G_PHI)
323
324/// Generic instruction to materialize the address of an alloca or other
325/// stack-based object.
326HANDLE_TARGET_OPCODE(G_FRAME_INDEX)
327
328/// Generic reference to global value.
329HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE)
330
331/// Generic ptrauth-signed reference to global value.
332HANDLE_TARGET_OPCODE(G_PTRAUTH_GLOBAL_VALUE)
333
334/// Generic instruction to materialize the address of an object in the constant
335/// pool.
336HANDLE_TARGET_OPCODE(G_CONSTANT_POOL)
337
338/// Generic instruction to extract blocks of bits from the register given
339/// (typically a sub-register COPY after instruction selection).
340HANDLE_TARGET_OPCODE(G_EXTRACT)
341
342HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES)
343
344/// Generic instruction to insert blocks of bits from the registers given into
345/// the source.
346HANDLE_TARGET_OPCODE(G_INSERT)
347
348/// Generic instruction to paste a variable number of components together into a
349/// larger register.
350HANDLE_TARGET_OPCODE(G_MERGE_VALUES)
351
352/// Generic instruction to create a vector value from a number of scalar
353/// components.
354HANDLE_TARGET_OPCODE(G_BUILD_VECTOR)
355
356/// Generic instruction to create a vector value from a number of scalar
357/// components, which have types larger than the result vector elt type.
358HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC)
359
360/// Generic instruction to create a vector by concatenating multiple vectors.
361HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS)
362
363/// Generic pointer to int conversion.
364HANDLE_TARGET_OPCODE(G_PTRTOINT)
365
366/// Generic int to pointer conversion.
367HANDLE_TARGET_OPCODE(G_INTTOPTR)
368
369/// Generic bitcast. The source and destination types must be different, or a
370/// COPY is the relevant instruction.
371HANDLE_TARGET_OPCODE(G_BITCAST)
372
373/// Generic freeze.
374HANDLE_TARGET_OPCODE(G_FREEZE)
375
376/// Constant folding barrier.
377HANDLE_TARGET_OPCODE(G_CONSTANT_FOLD_BARRIER)
378
379// INTRINSIC fptrunc_round intrinsic.
380HANDLE_TARGET_OPCODE(G_INTRINSIC_FPTRUNC_ROUND)
381
382/// INTRINSIC trunc intrinsic.
383HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC)
384
385/// INTRINSIC round intrinsic.
386HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
387
388/// INTRINSIC round to integer intrinsic.
389HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT)
390
391/// INTRINSIC long round to integer intrinsic.
392HANDLE_TARGET_OPCODE(G_INTRINSIC_LLRINT)
393
394/// INTRINSIC roundeven intrinsic.
395HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN)
396
397/// INTRINSIC readcyclecounter
398HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER)
399
400/// INTRINSIC readsteadycounter
401HANDLE_TARGET_OPCODE(G_READSTEADYCOUNTER)
402
403/// Generic load (including anyext load)
404HANDLE_TARGET_OPCODE(G_LOAD)
405
406/// Generic signext load
407HANDLE_TARGET_OPCODE(G_SEXTLOAD)
408
409/// Generic zeroext load
410HANDLE_TARGET_OPCODE(G_ZEXTLOAD)
411
412/// Generic indexed load (including anyext load)
413HANDLE_TARGET_OPCODE(G_INDEXED_LOAD)
414
415/// Generic indexed signext load
416HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD)
417
418/// Generic indexed zeroext load
419HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD)
420
421/// Generic store.
422HANDLE_TARGET_OPCODE(G_STORE)
423
424/// Generic indexed store.
425HANDLE_TARGET_OPCODE(G_INDEXED_STORE)
426
427/// Generic atomic cmpxchg with internal success check.
428HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS)
429
430/// Generic atomic cmpxchg.
431HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG)
432
433/// Generic atomicrmw.
434HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG)
435HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD)
436HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB)
437HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND)
438HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND)
439HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR)
440HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR)
441HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX)
442HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN)
443HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX)
444HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN)
445HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD)
446HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB)
447HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX)
448HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN)
449HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAXIMUM)
450HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMINIMUM)
451HANDLE_TARGET_OPCODE(G_ATOMICRMW_UINC_WRAP)
452HANDLE_TARGET_OPCODE(G_ATOMICRMW_UDEC_WRAP)
453HANDLE_TARGET_OPCODE(G_ATOMICRMW_USUB_COND)
454HANDLE_TARGET_OPCODE(G_ATOMICRMW_USUB_SAT)
455
456// Marker for start of Generic AtomicRMW opcodes
457HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG)
458
459// Marker for end of Generic AtomicRMW opcodes
460HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_USUB_SAT)
461
462// Generic atomic fence
463HANDLE_TARGET_OPCODE(G_FENCE)
464
465/// Generic prefetch
466HANDLE_TARGET_OPCODE(G_PREFETCH)
467
468/// Generic conditional branch instruction.
469HANDLE_TARGET_OPCODE(G_BRCOND)
470
471/// Generic indirect branch instruction.
472HANDLE_TARGET_OPCODE(G_BRINDIRECT)
473
474/// Begin an invoke region marker.
475HANDLE_TARGET_OPCODE(G_INVOKE_REGION_START)
476
477/// Generic intrinsic use (without side effects).
478HANDLE_TARGET_OPCODE(G_INTRINSIC)
479
480/// Generic intrinsic use (with side effects).
481HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS)
482
483/// Generic intrinsic use (without side effects).
484HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT)
485
486/// Generic intrinsic use (with side effects).
487HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS)
488
489/// Generic extension allowing rubbish in high bits.
490HANDLE_TARGET_OPCODE(G_ANYEXT)
491
492/// Generic instruction to discard the high bits of a register. This differs
493/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate
494/// each element individually, G_EXTRACT will typically discard the high
495/// elements of the vector.
496HANDLE_TARGET_OPCODE(G_TRUNC)
497
498/// Generic instruction to truncate a signed operand to a signed result with saturation.
499HANDLE_TARGET_OPCODE(G_TRUNC_SSAT_S)
500
501/// Generic instruction to truncate a signed operand to an unsigned result with saturation.
502HANDLE_TARGET_OPCODE(G_TRUNC_SSAT_U)
503
504/// Generic instruction to truncate a unsigned operand to an unsigned result with saturation.
505HANDLE_TARGET_OPCODE(G_TRUNC_USAT_U)
506
507/// Generic integer constant.
508HANDLE_TARGET_OPCODE(G_CONSTANT)
509
510/// Generic floating constant.
511HANDLE_TARGET_OPCODE(G_FCONSTANT)
512
513/// Generic va_start instruction. Stores to its one pointer operand.
514HANDLE_TARGET_OPCODE(G_VASTART)
515
516/// Generic va_arg instruction. Stores to its one pointer operand.
517HANDLE_TARGET_OPCODE(G_VAARG)
518
519// Generic sign extend
520HANDLE_TARGET_OPCODE(G_SEXT)
521HANDLE_TARGET_OPCODE(G_SEXT_INREG)
522
523// Generic zero extend
524HANDLE_TARGET_OPCODE(G_ZEXT)
525
526// Generic left-shift
527HANDLE_TARGET_OPCODE(G_SHL)
528
529// Generic logical right-shift
530HANDLE_TARGET_OPCODE(G_LSHR)
531
532// Generic arithmetic right-shift
533HANDLE_TARGET_OPCODE(G_ASHR)
534
535// Generic funnel left shift
536HANDLE_TARGET_OPCODE(G_FSHL)
537
538// Generic funnel right shift
539HANDLE_TARGET_OPCODE(G_FSHR)
540
541// Generic right rotate
542HANDLE_TARGET_OPCODE(G_ROTR)
543
544// Generic left rotate
545HANDLE_TARGET_OPCODE(G_ROTL)
546
547/// Generic integer-base comparison, also applicable to vectors of integers.
548HANDLE_TARGET_OPCODE(G_ICMP)
549
550/// Generic floating-point comparison, also applicable to vectors.
551HANDLE_TARGET_OPCODE(G_FCMP)
552
553/// Generic signed 3-way comparison.
554HANDLE_TARGET_OPCODE(G_SCMP)
555
556/// Generic unsigned 3-way comparison.
557HANDLE_TARGET_OPCODE(G_UCMP)
558
559/// Generic select.
560HANDLE_TARGET_OPCODE(G_SELECT)
561
562/// Generic unsigned add instruction, consuming the normal operands and
563/// producing the result and a carry flag.
564HANDLE_TARGET_OPCODE(G_UADDO)
565
566/// Generic unsigned add instruction, consuming the normal operands plus a carry
567/// flag, and similarly producing the result and a carry flag.
568HANDLE_TARGET_OPCODE(G_UADDE)
569
570/// Generic unsigned sub instruction, consuming the normal operands and
571/// producing the result and a carry flag.
572HANDLE_TARGET_OPCODE(G_USUBO)
573
574/// Generic unsigned subtract instruction, consuming the normal operands plus a
575/// carry flag, and similarly producing the result and a carry flag.
576HANDLE_TARGET_OPCODE(G_USUBE)
577
578/// Generic signed add instruction, producing the result and a signed overflow
579/// flag.
580HANDLE_TARGET_OPCODE(G_SADDO)
581
582/// Generic signed add instruction, consuming the normal operands plus a carry
583/// flag, and similarly producing the result and a carry flag.
584HANDLE_TARGET_OPCODE(G_SADDE)
585
586/// Generic signed subtract instruction, producing the result and a signed
587/// overflow flag.
588HANDLE_TARGET_OPCODE(G_SSUBO)
589
590/// Generic signed sub instruction, consuming the normal operands plus a carry
591/// flag, and similarly producing the result and a carry flag.
592HANDLE_TARGET_OPCODE(G_SSUBE)
593
594/// Generic unsigned multiply instruction, producing the result and a signed
595/// overflow flag.
596HANDLE_TARGET_OPCODE(G_UMULO)
597
598/// Generic signed multiply instruction, producing the result and a signed
599/// overflow flag.
600HANDLE_TARGET_OPCODE(G_SMULO)
601
602// Multiply two numbers at twice the incoming bit width (unsigned) and return
603// the high half of the result.
604HANDLE_TARGET_OPCODE(G_UMULH)
605
606// Multiply two numbers at twice the incoming bit width (signed) and return
607// the high half of the result.
608HANDLE_TARGET_OPCODE(G_SMULH)
609
610/// Generic saturating unsigned addition.
611HANDLE_TARGET_OPCODE(G_UADDSAT)
612
613/// Generic saturating signed addition.
614HANDLE_TARGET_OPCODE(G_SADDSAT)
615
616/// Generic saturating unsigned subtraction.
617HANDLE_TARGET_OPCODE(G_USUBSAT)
618
619/// Generic saturating signed subtraction.
620HANDLE_TARGET_OPCODE(G_SSUBSAT)
621
622/// Generic saturating unsigned left shift.
623HANDLE_TARGET_OPCODE(G_USHLSAT)
624
625/// Generic saturating signed left shift.
626HANDLE_TARGET_OPCODE(G_SSHLSAT)
627
628// Perform signed fixed point multiplication
629HANDLE_TARGET_OPCODE(G_SMULFIX)
630
631// Perform unsigned fixed point multiplication
632HANDLE_TARGET_OPCODE(G_UMULFIX)
633
634// Perform signed, saturating fixed point multiplication
635HANDLE_TARGET_OPCODE(G_SMULFIXSAT)
636
637// Perform unsigned, saturating fixed point multiplication
638HANDLE_TARGET_OPCODE(G_UMULFIXSAT)
639
640// Perform signed fixed point division
641HANDLE_TARGET_OPCODE(G_SDIVFIX)
642
643// Perform unsigned fixed point division
644HANDLE_TARGET_OPCODE(G_UDIVFIX)
645
646// Perform signed, saturating fixed point division
647HANDLE_TARGET_OPCODE(G_SDIVFIXSAT)
648
649// Perform unsigned, saturating fixed point division
650HANDLE_TARGET_OPCODE(G_UDIVFIXSAT)
651
652/// Generic FP addition.
653HANDLE_TARGET_OPCODE(G_FADD)
654
655/// Generic FP subtraction.
656HANDLE_TARGET_OPCODE(G_FSUB)
657
658/// Generic FP multiplication.
659HANDLE_TARGET_OPCODE(G_FMUL)
660
661/// Generic FMA multiplication. Behaves like llvm fma intrinsic
662HANDLE_TARGET_OPCODE(G_FMA)
663
664/// Generic FP multiply and add. Behaves as separate fmul and fadd.
665HANDLE_TARGET_OPCODE(G_FMAD)
666
667/// Generic FP division.
668HANDLE_TARGET_OPCODE(G_FDIV)
669
670/// Generic FP remainder.
671HANDLE_TARGET_OPCODE(G_FREM)
672
673/// Generic FP modf
674HANDLE_TARGET_OPCODE(G_FMODF)
675
676/// Generic FP exponentiation.
677HANDLE_TARGET_OPCODE(G_FPOW)
678
679/// Generic FP exponentiation, with an integer exponent.
680HANDLE_TARGET_OPCODE(G_FPOWI)
681
682/// Generic base-e exponential of a value.
683HANDLE_TARGET_OPCODE(G_FEXP)
684
685/// Generic base-2 exponential of a value.
686HANDLE_TARGET_OPCODE(G_FEXP2)
687
688/// Generic base-10 exponential of a value.
689HANDLE_TARGET_OPCODE(G_FEXP10)
690
691/// Floating point base-e logarithm of a value.
692HANDLE_TARGET_OPCODE(G_FLOG)
693
694/// Floating point base-2 logarithm of a value.
695HANDLE_TARGET_OPCODE(G_FLOG2)
696
697/// Floating point base-10 logarithm of a value.
698HANDLE_TARGET_OPCODE(G_FLOG10)
699
700/// Floating point x * 2^n
701HANDLE_TARGET_OPCODE(G_FLDEXP)
702
703/// Floating point extract fraction and exponent.
704HANDLE_TARGET_OPCODE(G_FFREXP)
705
706/// Generic FP negation.
707HANDLE_TARGET_OPCODE(G_FNEG)
708
709/// Generic FP extension.
710HANDLE_TARGET_OPCODE(G_FPEXT)
711
712/// Generic float to signed-int conversion
713HANDLE_TARGET_OPCODE(G_FPTRUNC)
714
715/// Generic float to signed-int conversion
716HANDLE_TARGET_OPCODE(G_FPTOSI)
717
718/// Generic float to unsigned-int conversion
719HANDLE_TARGET_OPCODE(G_FPTOUI)
720
721/// Generic signed-int to float conversion
722HANDLE_TARGET_OPCODE(G_SITOFP)
723
724/// Generic unsigned-int to float conversion
725HANDLE_TARGET_OPCODE(G_UITOFP)
726
727/// Generic saturating float to signed-int conversion
728HANDLE_TARGET_OPCODE(G_FPTOSI_SAT)
729
730/// Generic saturating float to unsigned-int conversion
731HANDLE_TARGET_OPCODE(G_FPTOUI_SAT)
732
733/// Generic FP absolute value.
734HANDLE_TARGET_OPCODE(G_FABS)
735
736/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does
737/// not require that X and Y have the same type, just that they are both
738/// floating point. X and the result must have the same type. FCOPYSIGN(f32,
739/// f64) is allowed.
740HANDLE_TARGET_OPCODE(G_FCOPYSIGN)
741
742/// Generic test for floating-point class.
743HANDLE_TARGET_OPCODE(G_IS_FPCLASS)
744
745/// Generic FP canonicalize value.
746HANDLE_TARGET_OPCODE(G_FCANONICALIZE)
747
748/// FP min/max matching libm's fmin/fmax
749HANDLE_TARGET_OPCODE(G_FMINNUM)
750HANDLE_TARGET_OPCODE(G_FMAXNUM)
751
752/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics.
753HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE)
754HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE)
755
756/// FP min/max matching IEEE-754 2018 draft semantics.
757HANDLE_TARGET_OPCODE(G_FMINIMUM)
758HANDLE_TARGET_OPCODE(G_FMAXIMUM)
759HANDLE_TARGET_OPCODE(G_FMINIMUMNUM)
760HANDLE_TARGET_OPCODE(G_FMAXIMUMNUM)
761
762/// Access to FP environment.
763HANDLE_TARGET_OPCODE(G_GET_FPENV)
764HANDLE_TARGET_OPCODE(G_SET_FPENV)
765HANDLE_TARGET_OPCODE(G_RESET_FPENV)
766HANDLE_TARGET_OPCODE(G_GET_FPMODE)
767HANDLE_TARGET_OPCODE(G_SET_FPMODE)
768HANDLE_TARGET_OPCODE(G_RESET_FPMODE)
769
770HANDLE_TARGET_OPCODE(G_GET_ROUNDING)
771HANDLE_TARGET_OPCODE(G_SET_ROUNDING)
772
773/// Generic pointer offset
774HANDLE_TARGET_OPCODE(G_PTR_ADD)
775
776/// Clear the specified bits in a pointer.
777HANDLE_TARGET_OPCODE(G_PTRMASK)
778
779/// Generic signed integer minimum.
780HANDLE_TARGET_OPCODE(G_SMIN)
781
782/// Generic signed integer maximum.
783HANDLE_TARGET_OPCODE(G_SMAX)
784
785/// Generic unsigned integer maximum.
786HANDLE_TARGET_OPCODE(G_UMIN)
787
788/// Generic unsigned integer maximum.
789HANDLE_TARGET_OPCODE(G_UMAX)
790
791/// Generic integer absolute value.
792HANDLE_TARGET_OPCODE(G_ABS)
793
794HANDLE_TARGET_OPCODE(G_LROUND)
795HANDLE_TARGET_OPCODE(G_LLROUND)
796
797/// Generic BRANCH instruction. This is an unconditional branch.
798HANDLE_TARGET_OPCODE(G_BR)
799
800/// Generic branch to jump table entry.
801HANDLE_TARGET_OPCODE(G_BRJT)
802
803/// Generic vscale.
804HANDLE_TARGET_OPCODE(G_VSCALE)
805
806/// Generic insert subvector.
807HANDLE_TARGET_OPCODE(G_INSERT_SUBVECTOR)
808
809/// Generic extract subvector.
810HANDLE_TARGET_OPCODE(G_EXTRACT_SUBVECTOR)
811
812/// Generic insertelement.
813HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
814
815/// Generic extractelement.
816HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
817
818/// Generic shufflevector.
819HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
820
821/// Generic splatvector.
822HANDLE_TARGET_OPCODE(G_SPLAT_VECTOR)
823
824/// Generic stepvector.
825HANDLE_TARGET_OPCODE(G_STEP_VECTOR)
826
827/// Generic masked compress.
828HANDLE_TARGET_OPCODE(G_VECTOR_COMPRESS)
829
830/// Generic count trailing zeroes.
831HANDLE_TARGET_OPCODE(G_CTTZ)
832
833/// Same as above, undefined for zero inputs.
834HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF)
835
836/// Generic count leading zeroes.
837HANDLE_TARGET_OPCODE(G_CTLZ)
838
839/// Same as above, undefined for zero inputs.
840HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF)
841
842/// Generic count extra sign bits.
843HANDLE_TARGET_OPCODE(G_CTLS)
844
845/// Generic count bits.
846HANDLE_TARGET_OPCODE(G_CTPOP)
847
848/// Generic byte swap.
849HANDLE_TARGET_OPCODE(G_BSWAP)
850
851/// Generic bit reverse.
852HANDLE_TARGET_OPCODE(G_BITREVERSE)
853
854/// Floating point ceil.
855HANDLE_TARGET_OPCODE(G_FCEIL)
856
857/// Floating point cosine.
858HANDLE_TARGET_OPCODE(G_FCOS)
859
860/// Floating point sine.
861HANDLE_TARGET_OPCODE(G_FSIN)
862
863/// Floating point combined sine and cosine.
864HANDLE_TARGET_OPCODE(G_FSINCOS)
865
866/// Floating point tangent.
867HANDLE_TARGET_OPCODE(G_FTAN)
868
869/// Floating point arccosine.
870HANDLE_TARGET_OPCODE(G_FACOS)
871
872/// Floating point arcsine.
873HANDLE_TARGET_OPCODE(G_FASIN)
874
875/// Floating point arctangent.
876HANDLE_TARGET_OPCODE(G_FATAN)
877
878/// Floating point arctangent of y/x.
879HANDLE_TARGET_OPCODE(G_FATAN2)
880
881/// Floating point hyperbolic cosine.
882HANDLE_TARGET_OPCODE(G_FCOSH)
883
884/// Floating point hyperbolic sine.
885HANDLE_TARGET_OPCODE(G_FSINH)
886
887/// Floating point hyperbolic tangent.
888HANDLE_TARGET_OPCODE(G_FTANH)
889
890/// Floating point square root.
891HANDLE_TARGET_OPCODE(G_FSQRT)
892
893/// Floating point floor.
894HANDLE_TARGET_OPCODE(G_FFLOOR)
895
896/// Floating point round to next integer.
897HANDLE_TARGET_OPCODE(G_FRINT)
898
899/// Floating point round to nearest integer.
900HANDLE_TARGET_OPCODE(G_FNEARBYINT)
901
902/// Generic AddressSpaceCast.
903HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST)
904
905/// Generic block address
906HANDLE_TARGET_OPCODE(G_BLOCK_ADDR)
907
908/// Generic jump table address
909HANDLE_TARGET_OPCODE(G_JUMP_TABLE)
910
911/// Generic dynamic stack allocation.
912HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC)
913
914/// Generic stack pointer save.
915HANDLE_TARGET_OPCODE(G_STACKSAVE)
916
917/// Generic stack pointer restore.
918HANDLE_TARGET_OPCODE(G_STACKRESTORE)
919
920/// Strict floating point instructions.
921HANDLE_TARGET_OPCODE(G_STRICT_FADD)
922HANDLE_TARGET_OPCODE(G_STRICT_FSUB)
923HANDLE_TARGET_OPCODE(G_STRICT_FMUL)
924HANDLE_TARGET_OPCODE(G_STRICT_FDIV)
925HANDLE_TARGET_OPCODE(G_STRICT_FREM)
926HANDLE_TARGET_OPCODE(G_STRICT_FMA)
927HANDLE_TARGET_OPCODE(G_STRICT_FSQRT)
928HANDLE_TARGET_OPCODE(G_STRICT_FLDEXP)
929
930/// read_register intrinsic
931HANDLE_TARGET_OPCODE(G_READ_REGISTER)
932
933/// write_register intrinsic
934HANDLE_TARGET_OPCODE(G_WRITE_REGISTER)
935
936/// llvm.memcpy intrinsic
937HANDLE_TARGET_OPCODE(G_MEMCPY)
938
939/// llvm.memcpy.inline intrinsic
940HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE)
941
942/// llvm.memmove intrinsic
943HANDLE_TARGET_OPCODE(G_MEMMOVE)
944
945/// llvm.memset intrinsic
946HANDLE_TARGET_OPCODE(G_MEMSET)
947HANDLE_TARGET_OPCODE(G_BZERO)
948
949/// llvm.trap, llvm.debugtrap and llvm.ubsantrap intrinsics
950HANDLE_TARGET_OPCODE(G_TRAP)
951HANDLE_TARGET_OPCODE(G_DEBUGTRAP)
952HANDLE_TARGET_OPCODE(G_UBSANTRAP)
953
954/// Vector reductions
955HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD)
956HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL)
957HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD)
958HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL)
959HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX)
960HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN)
961HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAXIMUM)
962HANDLE_TARGET_OPCODE(G_VECREDUCE_FMINIMUM)
963HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD)
964HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL)
965HANDLE_TARGET_OPCODE(G_VECREDUCE_AND)
966HANDLE_TARGET_OPCODE(G_VECREDUCE_OR)
967HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR)
968HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX)
969HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN)
970HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX)
971HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN)
972
973HANDLE_TARGET_OPCODE(G_SBFX)
974HANDLE_TARGET_OPCODE(G_UBFX)
975
976/// Marker for the end of the generic opcode.
977/// This is used to check if an opcode is in the range of the
978/// generic opcodes.
979HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX)
980
981/// BUILTIN_OP_END - This must be the last enum value in this list.
982/// The target-specific post-isel opcode values start here.
983HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END)
984