1//===- llvm/CodeGen/DwarfExpression.h - Dwarf Compile Unit ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains support for writing dwarf compile unit.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_CODEGEN_ASMPRINTER_DWARFEXPRESSION_H
14#define LLVM_LIB_CODEGEN_ASMPRINTER_DWARFEXPRESSION_H
15
16#include "ByteStreamer.h"
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/IR/DebugInfoMetadata.h"
20#include <cassert>
21#include <cstdint>
22#include <optional>
23
24namespace llvm {
25
26class AsmPrinter;
27class APInt;
28class DwarfCompileUnit;
29class DIELoc;
30class TargetRegisterInfo;
31class MachineLocation;
32
33/// Base class containing the logic for constructing DWARF expressions
34/// independently of whether they are emitted into a DIE or into a .debug_loc
35/// entry.
36///
37/// Some DWARF operations, e.g. DW_OP_entry_value, need to calculate the size
38/// of a succeeding DWARF block before the latter is emitted to the output.
39/// To handle such cases, data can conditionally be emitted to a temporary
40/// buffer, which can later on be committed to the main output. The size of the
41/// temporary buffer is queryable, allowing for the size of the data to be
42/// emitted before the data is committed.
43class DwarfExpression {
44protected:
45 /// Holds information about all subregisters comprising a register location.
46 struct Register {
47 int64_t DwarfRegNo;
48 unsigned SubRegSize;
49 const char *Comment;
50
51 /// Create a full register, no extra DW_OP_piece operators necessary.
52 static Register createRegister(int64_t RegNo, const char *Comment) {
53 return {.DwarfRegNo: RegNo, .SubRegSize: 0, .Comment: Comment};
54 }
55
56 /// Create a subregister that needs a DW_OP_piece operator with SizeInBits.
57 static Register createSubRegister(int64_t RegNo, unsigned SizeInBits,
58 const char *Comment) {
59 return {.DwarfRegNo: RegNo, .SubRegSize: SizeInBits, .Comment: Comment};
60 }
61
62 bool isSubRegister() const { return SubRegSize; }
63 };
64
65 /// Whether we are currently emitting an entry value operation.
66 bool IsEmittingEntryValue = false;
67
68 DwarfCompileUnit &CU;
69
70 /// The register location, if any.
71 SmallVector<Register, 2> DwarfRegs;
72
73 /// Current Fragment Offset in Bits.
74 uint64_t OffsetInBits = 0;
75
76 /// Sometimes we need to add a DW_OP_bit_piece to describe a subregister.
77 unsigned SubRegisterSizeInBits : 16;
78 unsigned SubRegisterOffsetInBits : 16;
79
80 /// The kind of location description being produced.
81 enum { Unknown = 0, Register, Memory, Implicit };
82
83 /// Additional location flags which may be combined with any location kind.
84 /// Currently, entry values are not supported for the Memory location kind.
85 enum { EntryValue = 1 << 0, Indirect = 1 << 1, CallSiteParamValue = 1 << 2 };
86
87 unsigned LocationKind : 3;
88 unsigned SavedLocationKind : 3;
89 unsigned LocationFlags : 3;
90 unsigned DwarfVersion : 4;
91
92public:
93 /// Set the location (\p Loc) and \ref DIExpression (\p DIExpr) to describe.
94 void setLocation(const MachineLocation &Loc, const DIExpression *DIExpr);
95
96 bool isUnknownLocation() const { return LocationKind == Unknown; }
97
98 bool isMemoryLocation() const { return LocationKind == Memory; }
99
100 bool isRegisterLocation() const { return LocationKind == Register; }
101
102 bool isImplicitLocation() const { return LocationKind == Implicit; }
103
104 bool isEntryValue() const { return LocationFlags & EntryValue; }
105
106 bool isIndirect() const { return LocationFlags & Indirect; }
107
108 bool isParameterValue() { return LocationFlags & CallSiteParamValue; }
109
110 std::optional<uint8_t> TagOffset;
111
112protected:
113 /// Push a DW_OP_piece / DW_OP_bit_piece for emitting later, if one is needed
114 /// to represent a subregister.
115 void setSubRegisterPiece(unsigned SizeInBits, unsigned OffsetInBits) {
116 assert(SizeInBits < 65536 && OffsetInBits < 65536);
117 SubRegisterSizeInBits = SizeInBits;
118 SubRegisterOffsetInBits = OffsetInBits;
119 }
120
121 /// Add masking operations to stencil out a subregister.
122 void maskSubRegister();
123
124 /// Output a dwarf operand and an optional assembler comment.
125 virtual void emitOp(uint8_t Op, const char *Comment = nullptr) = 0;
126
127 /// Emit a raw signed value.
128 virtual void emitSigned(int64_t Value) = 0;
129
130 /// Emit a raw unsigned value.
131 virtual void emitUnsigned(uint64_t Value) = 0;
132
133 virtual void emitData1(uint8_t Value) = 0;
134
135 virtual void emitBaseTypeRef(uint64_t Idx) = 0;
136
137 /// Start emitting data to the temporary buffer. The data stored in the
138 /// temporary buffer can be committed to the main output using
139 /// commitTemporaryBuffer().
140 virtual void enableTemporaryBuffer() = 0;
141
142 /// Disable emission to the temporary buffer. This does not commit data
143 /// in the temporary buffer to the main output.
144 virtual void disableTemporaryBuffer() = 0;
145
146 /// Return the emitted size, in number of bytes, for the data stored in the
147 /// temporary buffer.
148 virtual unsigned getTemporaryBufferSize() = 0;
149
150 /// Commit the data stored in the temporary buffer to the main output.
151 virtual void commitTemporaryBuffer() = 0;
152
153 /// Emit a normalized unsigned constant.
154 void emitConstu(uint64_t Value);
155
156 /// Return whether the given machine register is the frame register in the
157 /// current function.
158 virtual bool isFrameRegister(const TargetRegisterInfo &TRI,
159 llvm::Register MachineReg) = 0;
160
161 /// Emit a DW_OP_reg operation. Note that this is only legal inside a DWARF
162 /// register location description.
163 void addReg(int64_t DwarfReg, const char *Comment = nullptr);
164
165 /// Emit a DW_OP_breg operation.
166 void addBReg(int64_t DwarfReg, int64_t Offset);
167
168 /// Emit DW_OP_fbreg <Offset>.
169 void addFBReg(int64_t Offset);
170
171 /// Emit a partial DWARF register operation.
172 ///
173 /// \param MachineReg The register number.
174 /// \param MaxSize If the register must be composed from
175 /// sub-registers this is an upper bound
176 /// for how many bits the emitted DW_OP_piece
177 /// may cover.
178 ///
179 /// If size and offset is zero an operation for the entire register is
180 /// emitted: Some targets do not provide a DWARF register number for every
181 /// register. If this is the case, this function will attempt to emit a DWARF
182 /// register by emitting a fragment of a super-register or by piecing together
183 /// multiple subregisters that alias the register.
184 ///
185 /// \return false if no DWARF register exists for MachineReg.
186 bool addMachineReg(const TargetRegisterInfo &TRI, llvm::Register MachineReg,
187 unsigned MaxSize = ~1U);
188
189 /// Emit a DW_OP_piece or DW_OP_bit_piece operation for a variable fragment.
190 /// \param OffsetInBits This is an optional offset into the location that
191 /// is at the top of the DWARF stack.
192 void addOpPiece(unsigned SizeInBits, unsigned OffsetInBits = 0);
193
194 /// Emit a shift-right dwarf operation.
195 void addShr(unsigned ShiftBy);
196
197 /// Emit a bitwise and dwarf operation.
198 void addAnd(unsigned Mask);
199
200 /// Emit a DW_OP_stack_value, if supported.
201 ///
202 /// The proper way to describe a constant value is DW_OP_constu <const>,
203 /// DW_OP_stack_value. Unfortunately, DW_OP_stack_value was not available
204 /// until DWARF 4, so we will continue to generate DW_OP_constu <const> for
205 /// DWARF 2 and DWARF 3. Technically, this is incorrect since DW_OP_const
206 /// <const> actually describes a value at a constant address, not a constant
207 /// value. However, in the past there was no better way to describe a
208 /// constant value, so the producers and consumers started to rely on
209 /// heuristics to disambiguate the value vs. location status of the
210 /// expression. See PR21176 for more details.
211 void addStackValue();
212
213 /// Finalize an entry value by emitting its size operand, and committing the
214 /// DWARF block which has been emitted to the temporary buffer.
215 void finalizeEntryValue();
216
217 /// Cancel the emission of an entry value.
218 void cancelEntryValue();
219
220 ~DwarfExpression() = default;
221
222public:
223 DwarfExpression(unsigned DwarfVersion, DwarfCompileUnit &CU)
224 : CU(CU), SubRegisterSizeInBits(0), SubRegisterOffsetInBits(0),
225 LocationKind(Unknown), SavedLocationKind(Unknown),
226 LocationFlags(Unknown), DwarfVersion(DwarfVersion) {}
227
228 /// This needs to be called last to commit any pending changes.
229 void finalize();
230
231 /// Emit a boolean constant.
232 void addBooleanConstant(int64_t Value);
233
234 /// Emit a signed constant.
235 void addSignedConstant(int64_t Value);
236
237 /// Emit an unsigned constant.
238 void addUnsignedConstant(uint64_t Value);
239
240 /// Emit an unsigned constant.
241 void addUnsignedConstant(const APInt &Value);
242
243 /// Emit an implicit value.
244 void addImplicitValue(const APInt &Value, const AsmPrinter &AP);
245
246 /// Emit an floating point constant.
247 void addConstantFP(const APFloat &Value, const AsmPrinter &AP);
248
249 /// Lock this down to become a memory location description.
250 void setMemoryLocationKind() {
251 assert(isUnknownLocation());
252 LocationKind = Memory;
253 }
254
255 /// Lock this down to become an entry value location.
256 void setEntryValueFlags(const MachineLocation &Loc);
257
258 /// Lock this down to become a call site parameter location.
259 void setCallSiteParamValueFlag() { LocationFlags |= CallSiteParamValue; }
260
261 /// Emit a machine register location. As an optimization this may also consume
262 /// the prefix of a DwarfExpression if a more efficient representation for
263 /// combining the register location and the first operation exists.
264 ///
265 /// \param FragmentOffsetInBits If this is one fragment out of a
266 /// fragmented
267 /// location, this is the offset of the
268 /// fragment inside the entire variable.
269 /// \return false if no DWARF register exists
270 /// for MachineReg.
271 bool addMachineRegExpression(const TargetRegisterInfo &TRI,
272 DIExpressionCursor &Expr,
273 llvm::Register MachineReg,
274 unsigned FragmentOffsetInBits = 0);
275
276 /// Begin emission of an entry value dwarf operation. The entry value's
277 /// first operand is the size of the DWARF block (its second operand),
278 /// which needs to be calculated at time of emission, so we don't emit
279 /// any operands here.
280 void beginEntryValueExpression(DIExpressionCursor &ExprCursor);
281
282 /// Return the index of a base type with the given properties and
283 /// create one if necessary.
284 unsigned getOrCreateBaseType(unsigned BitSize, dwarf::TypeKind Encoding);
285
286 /// Emit all remaining operations in the DIExpressionCursor. The
287 /// cursor must not contain any DW_OP_LLVM_arg operations.
288 void addExpression(DIExpressionCursor &&Expr);
289
290 /// Emit all remaining operations in the DIExpressionCursor.
291 /// DW_OP_LLVM_arg operations are resolved by calling (\p InsertArg).
292 //
293 /// \return false if any call to (\p InsertArg) returns false.
294 bool addExpression(
295 DIExpressionCursor &&Expr,
296 llvm::function_ref<bool(unsigned, DIExpressionCursor &)> InsertArg);
297
298 /// If applicable, emit an empty DW_OP_piece / DW_OP_bit_piece to advance to
299 /// the fragment described by \c Expr.
300 void addFragmentOffset(const DIExpression *Expr);
301
302 void emitLegacySExt(unsigned FromBits);
303 void emitLegacyZExt(unsigned FromBits);
304
305 /// Emit location information expressed via WebAssembly location + offset
306 /// The Index is an identifier for locals, globals or operand stack.
307 void addWasmLocation(unsigned Index, uint64_t Offset);
308};
309
310/// DwarfExpression implementation for .debug_loc entries.
311class DebugLocDwarfExpression final : public DwarfExpression {
312
313 struct TempBuffer {
314 SmallString<32> Bytes;
315 std::vector<std::string> Comments;
316 BufferByteStreamer BS;
317
318 TempBuffer(bool GenerateComments) : BS(Bytes, Comments, GenerateComments) {}
319 };
320
321 std::unique_ptr<TempBuffer> TmpBuf;
322 BufferByteStreamer &OutBS;
323 bool IsBuffering = false;
324
325 /// Return the byte streamer that currently is being emitted to.
326 ByteStreamer &getActiveStreamer() { return IsBuffering ? TmpBuf->BS : OutBS; }
327
328 void emitOp(uint8_t Op, const char *Comment = nullptr) override;
329 void emitSigned(int64_t Value) override;
330 void emitUnsigned(uint64_t Value) override;
331 void emitData1(uint8_t Value) override;
332 void emitBaseTypeRef(uint64_t Idx) override;
333
334 void enableTemporaryBuffer() override;
335 void disableTemporaryBuffer() override;
336 unsigned getTemporaryBufferSize() override;
337 void commitTemporaryBuffer() override;
338
339 bool isFrameRegister(const TargetRegisterInfo &TRI,
340 llvm::Register MachineReg) override;
341
342public:
343 DebugLocDwarfExpression(unsigned DwarfVersion, BufferByteStreamer &BS,
344 DwarfCompileUnit &CU)
345 : DwarfExpression(DwarfVersion, CU), OutBS(BS) {}
346};
347
348/// DwarfExpression implementation for singular DW_AT_location.
349class DIEDwarfExpression final : public DwarfExpression {
350 const AsmPrinter &AP;
351 DIELoc &OutDIE;
352 DIELoc TmpDIE;
353 bool IsBuffering = false;
354
355 /// Return the DIE that currently is being emitted to.
356 DIELoc &getActiveDIE() { return IsBuffering ? TmpDIE : OutDIE; }
357
358 void emitOp(uint8_t Op, const char *Comment = nullptr) override;
359 void emitSigned(int64_t Value) override;
360 void emitUnsigned(uint64_t Value) override;
361 void emitData1(uint8_t Value) override;
362 void emitBaseTypeRef(uint64_t Idx) override;
363
364 void enableTemporaryBuffer() override;
365 void disableTemporaryBuffer() override;
366 unsigned getTemporaryBufferSize() override;
367 void commitTemporaryBuffer() override;
368
369 bool isFrameRegister(const TargetRegisterInfo &TRI,
370 llvm::Register MachineReg) override;
371
372public:
373 DIEDwarfExpression(const AsmPrinter &AP, DwarfCompileUnit &CU, DIELoc &DIE);
374
375 DIELoc *finalize() {
376 DwarfExpression::finalize();
377 return &OutDIE;
378 }
379};
380
381} // end namespace llvm
382
383#endif // LLVM_LIB_CODEGEN_ASMPRINTER_DWARFEXPRESSION_H
384