1//===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/CodeGen/MachineCycleAnalysis.h"
10#include "llvm/ADT/GenericCycleImpl.h"
11#include "llvm/CodeGen/MachineRegisterInfo.h"
12#include "llvm/CodeGen/MachineSSAContext.h"
13#include "llvm/CodeGen/TargetInstrInfo.h"
14#include "llvm/CodeGen/TargetSubtargetInfo.h"
15#include "llvm/InitializePasses.h"
16
17using namespace llvm;
18
19template class llvm::GenericCycleInfo<llvm::MachineSSAContext>;
20
21char MachineCycleInfoWrapperPass::ID = 0;
22
23MachineCycleInfoWrapperPass::MachineCycleInfoWrapperPass()
24 : MachineFunctionPass(ID) {}
25
26INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles",
27 "Machine Cycle Info Analysis", true, true)
28INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles",
29 "Machine Cycle Info Analysis", true, true)
30
31void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
32 AU.setPreservesAll();
33 MachineFunctionPass::getAnalysisUsage(AU);
34}
35
36bool MachineCycleInfoWrapperPass::runOnMachineFunction(MachineFunction &Func) {
37 CI.clear();
38
39 F = &Func;
40 CI.compute(F&: Func);
41 return false;
42}
43
44void MachineCycleInfoWrapperPass::print(raw_ostream &OS, const Module *) const {
45 OS << "MachineCycleInfo for function: " << F->getName() << "\n";
46 CI.print(Out&: OS);
47}
48
49void MachineCycleInfoWrapperPass::releaseMemory() {
50 CI.clear();
51 F = nullptr;
52}
53
54AnalysisKey MachineCycleAnalysis::Key;
55
56MachineCycleInfo
57MachineCycleAnalysis::run(MachineFunction &MF,
58 MachineFunctionAnalysisManager &MFAM) {
59 MachineCycleInfo MCI;
60 MCI.compute(F&: MF);
61 return MCI;
62}
63
64bool MachineCycleAnalysis::invalidate(
65 MachineFunction &, const PreservedAnalyses &PA,
66 MachineFunctionAnalysisManager::Invalidator &) {
67 // Check whether the analysis, all analyses on functions, or the function's
68 // CFG have been preserved.
69 auto PAC = PA.getChecker<MachineCycleAnalysis>();
70 return !(PAC.preserved() ||
71 PAC.preservedSet<AllAnalysesOn<MachineFunction>>() ||
72 PAC.preservedSet<CFGAnalyses>());
73}
74
75namespace {
76class MachineCycleInfoPrinterLegacy : public MachineFunctionPass {
77public:
78 static char ID;
79
80 MachineCycleInfoPrinterLegacy();
81
82 bool runOnMachineFunction(MachineFunction &F) override;
83 void getAnalysisUsage(AnalysisUsage &AU) const override;
84};
85} // namespace
86
87char MachineCycleInfoPrinterLegacy::ID = 0;
88
89MachineCycleInfoPrinterLegacy::MachineCycleInfoPrinterLegacy()
90 : MachineFunctionPass(ID) {}
91
92INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterLegacy, "print-machine-cycles",
93 "Print Machine Cycle Info Analysis", true, true)
94INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
95INITIALIZE_PASS_END(MachineCycleInfoPrinterLegacy, "print-machine-cycles",
96 "Print Machine Cycle Info Analysis", true, true)
97
98void MachineCycleInfoPrinterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
99 AU.setPreservesAll();
100 AU.addRequired<MachineCycleInfoWrapperPass>();
101 MachineFunctionPass::getAnalysisUsage(AU);
102}
103
104bool MachineCycleInfoPrinterLegacy::runOnMachineFunction(MachineFunction &F) {
105 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>();
106 CI.print(OS&: errs());
107 return false;
108}
109
110PreservedAnalyses
111MachineCycleInfoPrinterPass::run(MachineFunction &MF,
112 MachineFunctionAnalysisManager &MFAM) {
113 auto &MCI = MFAM.getResult<MachineCycleAnalysis>(IR&: MF);
114 MCI.print(Out&: OS);
115 return PreservedAnalyses::all();
116}
117
118bool llvm::isCycleInvariant(const MachineCycleInfo &CI, CycleRef Cycle,
119 MachineInstr &I) {
120 MachineFunction *MF = I.getParent()->getParent();
121 MachineRegisterInfo *MRI = &MF->getRegInfo();
122 const TargetSubtargetInfo &ST = MF->getSubtarget();
123 const TargetRegisterInfo *TRI = ST.getRegisterInfo();
124 const TargetInstrInfo *TII = ST.getInstrInfo();
125
126 // The instruction is cycle invariant if all of its operands are.
127 for (const MachineOperand &MO : I.operands()) {
128 if (!MO.isReg())
129 continue;
130
131 Register Reg = MO.getReg();
132 if (Reg == 0)
133 continue;
134
135 // An instruction that uses or defines a physical register can't e.g. be
136 // hoisted, so mark this as not invariant.
137 if (Reg.isPhysical()) {
138 if (MO.isUse()) {
139 // If the physreg has no defs anywhere, it's just an ambient register
140 // and we can freely move its uses. Alternatively, if it's allocatable,
141 // it could get allocated to something with a def during allocation.
142 // However, if the physreg is known to always be caller saved/restored
143 // then this use is safe to hoist.
144 if (!MRI->isConstantPhysReg(PhysReg: Reg) &&
145 !(TRI->isCallerPreservedPhysReg(PhysReg: Reg.asMCReg(), MF: *I.getMF())) &&
146 !TII->isIgnorableUse(MO))
147 return false;
148 // Otherwise it's safe to move.
149 continue;
150 } else if (!MO.isDead()) {
151 // A def that isn't dead can't be moved.
152 return false;
153 } else if (any_of(Range: CI.getEntries(C: Cycle),
154 P: [&](const MachineBasicBlock *Block) {
155 return Block->isLiveIn(Reg);
156 })) {
157 // If the reg is live into any header of the cycle we can't hoist an
158 // instruction which would clobber it.
159 return false;
160 }
161 }
162
163 if (!MO.isUse())
164 continue;
165
166 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!");
167
168 // If the cycle contains the definition of an operand, then the instruction
169 // isn't cycle invariant.
170 if (CI.contains(C: Cycle, Block: MRI->getVRegDef(Reg)->getParent()))
171 return false;
172 }
173
174 // If we got this far, the instruction is cycle invariant!
175 return true;
176}
177