1//===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/CodeGen/MachineCycleAnalysis.h"
10#include "llvm/ADT/GenericCycleImpl.h"
11#include "llvm/CodeGen/MachineRegisterInfo.h"
12#include "llvm/CodeGen/MachineSSAContext.h"
13#include "llvm/CodeGen/TargetInstrInfo.h"
14#include "llvm/CodeGen/TargetSubtargetInfo.h"
15#include "llvm/InitializePasses.h"
16
17using namespace llvm;
18
19template class llvm::GenericCycleInfo<llvm::MachineSSAContext>;
20template class llvm::GenericCycle<llvm::MachineSSAContext>;
21
22char MachineCycleInfoWrapperPass::ID = 0;
23
24MachineCycleInfoWrapperPass::MachineCycleInfoWrapperPass()
25 : MachineFunctionPass(ID) {}
26
27INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles",
28 "Machine Cycle Info Analysis", true, true)
29INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles",
30 "Machine Cycle Info Analysis", true, true)
31
32void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
33 AU.setPreservesAll();
34 MachineFunctionPass::getAnalysisUsage(AU);
35}
36
37bool MachineCycleInfoWrapperPass::runOnMachineFunction(MachineFunction &Func) {
38 CI.clear();
39
40 F = &Func;
41 CI.compute(F&: Func);
42 return false;
43}
44
45void MachineCycleInfoWrapperPass::print(raw_ostream &OS, const Module *) const {
46 OS << "MachineCycleInfo for function: " << F->getName() << "\n";
47 CI.print(Out&: OS);
48}
49
50void MachineCycleInfoWrapperPass::releaseMemory() {
51 CI.clear();
52 F = nullptr;
53}
54
55AnalysisKey MachineCycleAnalysis::Key;
56
57MachineCycleInfo
58MachineCycleAnalysis::run(MachineFunction &MF,
59 MachineFunctionAnalysisManager &MFAM) {
60 MachineCycleInfo MCI;
61 MCI.compute(F&: MF);
62 return MCI;
63}
64
65namespace {
66class MachineCycleInfoPrinterLegacy : public MachineFunctionPass {
67public:
68 static char ID;
69
70 MachineCycleInfoPrinterLegacy();
71
72 bool runOnMachineFunction(MachineFunction &F) override;
73 void getAnalysisUsage(AnalysisUsage &AU) const override;
74};
75} // namespace
76
77char MachineCycleInfoPrinterLegacy::ID = 0;
78
79MachineCycleInfoPrinterLegacy::MachineCycleInfoPrinterLegacy()
80 : MachineFunctionPass(ID) {}
81
82INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterLegacy, "print-machine-cycles",
83 "Print Machine Cycle Info Analysis", true, true)
84INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
85INITIALIZE_PASS_END(MachineCycleInfoPrinterLegacy, "print-machine-cycles",
86 "Print Machine Cycle Info Analysis", true, true)
87
88void MachineCycleInfoPrinterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
89 AU.setPreservesAll();
90 AU.addRequired<MachineCycleInfoWrapperPass>();
91 MachineFunctionPass::getAnalysisUsage(AU);
92}
93
94bool MachineCycleInfoPrinterLegacy::runOnMachineFunction(MachineFunction &F) {
95 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>();
96 CI.print(OS&: errs());
97 return false;
98}
99
100PreservedAnalyses
101MachineCycleInfoPrinterPass::run(MachineFunction &MF,
102 MachineFunctionAnalysisManager &MFAM) {
103 auto &MCI = MFAM.getResult<MachineCycleAnalysis>(IR&: MF);
104 MCI.print(Out&: OS);
105 return PreservedAnalyses::all();
106}
107
108bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) {
109 MachineFunction *MF = I.getParent()->getParent();
110 MachineRegisterInfo *MRI = &MF->getRegInfo();
111 const TargetSubtargetInfo &ST = MF->getSubtarget();
112 const TargetRegisterInfo *TRI = ST.getRegisterInfo();
113 const TargetInstrInfo *TII = ST.getInstrInfo();
114
115 // The instruction is cycle invariant if all of its operands are.
116 for (const MachineOperand &MO : I.operands()) {
117 if (!MO.isReg())
118 continue;
119
120 Register Reg = MO.getReg();
121 if (Reg == 0)
122 continue;
123
124 // An instruction that uses or defines a physical register can't e.g. be
125 // hoisted, so mark this as not invariant.
126 if (Reg.isPhysical()) {
127 if (MO.isUse()) {
128 // If the physreg has no defs anywhere, it's just an ambient register
129 // and we can freely move its uses. Alternatively, if it's allocatable,
130 // it could get allocated to something with a def during allocation.
131 // However, if the physreg is known to always be caller saved/restored
132 // then this use is safe to hoist.
133 if (!MRI->isConstantPhysReg(PhysReg: Reg) &&
134 !(TRI->isCallerPreservedPhysReg(PhysReg: Reg.asMCReg(), MF: *I.getMF())) &&
135 !TII->isIgnorableUse(MO))
136 return false;
137 // Otherwise it's safe to move.
138 continue;
139 } else if (!MO.isDead()) {
140 // A def that isn't dead can't be moved.
141 return false;
142 } else if (any_of(Range: Cycle->getEntries(),
143 P: [&](const MachineBasicBlock *Block) {
144 return Block->isLiveIn(Reg);
145 })) {
146 // If the reg is live into any header of the cycle we can't hoist an
147 // instruction which would clobber it.
148 return false;
149 }
150 }
151
152 if (!MO.isUse())
153 continue;
154
155 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!");
156
157 // If the cycle contains the definition of an operand, then the instruction
158 // isn't cycle invariant.
159 if (Cycle->contains(Block: MRI->getVRegDef(Reg)->getParent()))
160 return false;
161 }
162
163 // If we got this far, the instruction is cycle invariant!
164 return true;
165}
166