1//===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/CodeGen/MachineCycleAnalysis.h"
10#include "llvm/ADT/GenericCycleImpl.h"
11#include "llvm/CodeGen/MachineRegisterInfo.h"
12#include "llvm/CodeGen/MachineSSAContext.h"
13#include "llvm/CodeGen/TargetInstrInfo.h"
14#include "llvm/CodeGen/TargetSubtargetInfo.h"
15#include "llvm/InitializePasses.h"
16
17using namespace llvm;
18
19template class LLVM_ABI_FOR_TEST
20 llvm::GenericCycleInfo<llvm::MachineSSAContext>;
21
22char MachineCycleInfoWrapperPass::ID = 0;
23
24MachineCycleInfoWrapperPass::MachineCycleInfoWrapperPass()
25 : MachineFunctionPass(ID) {}
26
27INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles",
28 "Machine Cycle Info Analysis", true, true)
29INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles",
30 "Machine Cycle Info Analysis", true, true)
31
32void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
33 AU.setPreservesAll();
34 MachineFunctionPass::getAnalysisUsage(AU);
35}
36
37bool MachineCycleInfoWrapperPass::runOnMachineFunction(MachineFunction &Func) {
38 CI.clear();
39
40 F = &Func;
41 CI.compute(F&: Func);
42 return false;
43}
44
45void MachineCycleInfoWrapperPass::print(raw_ostream &OS, const Module *) const {
46 OS << "MachineCycleInfo for function: " << F->getName() << "\n";
47 CI.print(Out&: OS);
48}
49
50void MachineCycleInfoWrapperPass::releaseMemory() {
51 CI.clear();
52 F = nullptr;
53}
54
55AnalysisKey MachineCycleAnalysis::Key;
56
57MachineCycleInfo
58MachineCycleAnalysis::run(MachineFunction &MF,
59 MachineFunctionAnalysisManager &MFAM) {
60 MachineCycleInfo MCI;
61 MCI.compute(F&: MF);
62 return MCI;
63}
64
65bool MachineCycleAnalysis::invalidate(
66 MachineFunction &, const PreservedAnalyses &PA,
67 MachineFunctionAnalysisManager::Invalidator &) {
68 // Check whether the analysis, all analyses on functions, or the function's
69 // CFG have been preserved.
70 auto PAC = PA.getChecker<MachineCycleAnalysis>();
71 return !(PAC.preserved() ||
72 PAC.preservedSet<AllAnalysesOn<MachineFunction>>() ||
73 PAC.preservedSet<CFGAnalyses>());
74}
75
76namespace {
77class MachineCycleInfoPrinterLegacy : public MachineFunctionPass {
78public:
79 static char ID;
80
81 MachineCycleInfoPrinterLegacy();
82
83 bool runOnMachineFunction(MachineFunction &F) override;
84 void getAnalysisUsage(AnalysisUsage &AU) const override;
85};
86} // namespace
87
88char MachineCycleInfoPrinterLegacy::ID = 0;
89
90MachineCycleInfoPrinterLegacy::MachineCycleInfoPrinterLegacy()
91 : MachineFunctionPass(ID) {}
92
93INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterLegacy, "print-machine-cycles",
94 "Print Machine Cycle Info Analysis", true, true)
95INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
96INITIALIZE_PASS_END(MachineCycleInfoPrinterLegacy, "print-machine-cycles",
97 "Print Machine Cycle Info Analysis", true, true)
98
99void MachineCycleInfoPrinterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
100 AU.setPreservesAll();
101 AU.addRequired<MachineCycleInfoWrapperPass>();
102 MachineFunctionPass::getAnalysisUsage(AU);
103}
104
105bool MachineCycleInfoPrinterLegacy::runOnMachineFunction(MachineFunction &F) {
106 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>();
107 CI.print(OS&: errs());
108 return false;
109}
110
111PreservedAnalyses
112MachineCycleInfoPrinterPass::run(MachineFunction &MF,
113 MachineFunctionAnalysisManager &MFAM) {
114 auto &MCI = MFAM.getResult<MachineCycleAnalysis>(IR&: MF);
115 MCI.print(Out&: OS);
116 return PreservedAnalyses::all();
117}
118
119bool llvm::isCycleInvariant(const MachineCycleInfo &CI, CycleRef Cycle,
120 MachineInstr &I) {
121 MachineFunction *MF = I.getParent()->getParent();
122 MachineRegisterInfo *MRI = &MF->getRegInfo();
123 const TargetSubtargetInfo &ST = MF->getSubtarget();
124 const TargetRegisterInfo *TRI = ST.getRegisterInfo();
125 const TargetInstrInfo *TII = ST.getInstrInfo();
126
127 // The instruction is cycle invariant if all of its operands are.
128 for (const MachineOperand &MO : I.operands()) {
129 if (!MO.isReg())
130 continue;
131
132 Register Reg = MO.getReg();
133 if (Reg == 0)
134 continue;
135
136 // An instruction that uses or defines a physical register can't e.g. be
137 // hoisted, so mark this as not invariant.
138 if (Reg.isPhysical()) {
139 if (MO.isUse()) {
140 // If the physreg has no defs anywhere, it's just an ambient register
141 // and we can freely move its uses. Alternatively, if it's allocatable,
142 // it could get allocated to something with a def during allocation.
143 // However, if the physreg is known to always be caller saved/restored
144 // then this use is safe to hoist.
145 if (!MRI->isConstantPhysReg(PhysReg: Reg) &&
146 !(TRI->isCallerPreservedPhysReg(PhysReg: Reg.asMCReg(), MF: *I.getMF())) &&
147 !TII->isIgnorableUse(MI: I, OpIdx: I.getOperandNo(I: &MO)))
148 return false;
149 // Otherwise it's safe to move.
150 continue;
151 } else if (!MO.isDead()) {
152 // A def that isn't dead can't be moved.
153 return false;
154 } else if (any_of(Range: CI.getEntries(C: Cycle),
155 P: [&](const MachineBasicBlock *Block) {
156 return Block->isLiveIn(Reg);
157 })) {
158 // If the reg is live into any header of the cycle we can't hoist an
159 // instruction which would clobber it.
160 return false;
161 }
162 }
163
164 if (!MO.isUse())
165 continue;
166
167 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!");
168
169 // If the cycle contains the definition of an operand, then the instruction
170 // isn't cycle invariant.
171 if (CI.contains(C: Cycle, Block: MRI->getDefBlock(Reg)))
172 return false;
173 }
174
175 // If we got this far, the instruction is cycle invariant!
176 return true;
177}
178