1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Methods common to all machine operands.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineOperand.h"
14#include "llvm/ADT/StableHashing.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/Analysis/Loads.h"
17#include "llvm/CodeGen/MIRFormatter.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineJumpTableInfo.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/CodeGen/PseudoSourceValueManager.h"
22#include "llvm/CodeGen/TargetInstrInfo.h"
23#include "llvm/CodeGen/TargetRegisterInfo.h"
24#include "llvm/Config/llvm-config.h"
25#include "llvm/IR/Constants.h"
26#include "llvm/IR/IRPrintingPasses.h"
27#include "llvm/IR/Instructions.h"
28#include "llvm/IR/ModuleSlotTracker.h"
29#include "llvm/MC/MCDwarf.h"
30#include "llvm/Target/TargetMachine.h"
31#include <optional>
32
33using namespace llvm;
34
35static cl::opt<int>
36 PrintRegMaskNumRegs("print-regmask-num-regs",
37 cl::desc("Number of registers to limit to when "
38 "printing regmask operands in IR dumps. "
39 "unlimited = -1"),
40 cl::init(Val: 32), cl::Hidden);
41
42static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
43 if (const MachineInstr *MI = MO.getParent())
44 if (const MachineBasicBlock *MBB = MI->getParent())
45 if (const MachineFunction *MF = MBB->getParent())
46 return MF;
47 return nullptr;
48}
49
50static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
51 return const_cast<MachineFunction *>(
52 getMFIfAvailable(MO: const_cast<const MachineOperand &>(MO)));
53}
54
55unsigned MachineOperand::getOperandNo() const {
56 assert(getParent() && "Operand does not belong to any instruction!");
57 return getParent()->getOperandNo(I: this);
58}
59
60void MachineOperand::setReg(Register Reg) {
61 if (getReg() == Reg)
62 return; // No change.
63
64 // Clear the IsRenamable bit to keep it conservatively correct.
65 IsRenamable = false;
66
67 // Otherwise, we have to change the register. If this operand is embedded
68 // into a machine function, we need to update the old and new register's
69 // use/def lists.
70 if (MachineFunction *MF = getMFIfAvailable(MO&: *this)) {
71 MachineRegisterInfo &MRI = MF->getRegInfo();
72 MRI.removeRegOperandFromUseList(MO: this);
73 SmallContents.RegNo = Reg.id();
74 MRI.addRegOperandToUseList(MO: this);
75 return;
76 }
77
78 // Otherwise, just change the register, no problem. :)
79 SmallContents.RegNo = Reg.id();
80}
81
82void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
83 const TargetRegisterInfo &TRI) {
84 assert(Reg.isVirtual());
85 if (SubIdx && getSubReg())
86 SubIdx = TRI.composeSubRegIndices(a: SubIdx, b: getSubReg());
87 setReg(Reg);
88 if (SubIdx)
89 setSubReg(SubIdx);
90}
91
92void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
93 assert(Reg.isPhysical());
94 if (getSubReg()) {
95 Reg = TRI.getSubReg(Reg, Idx: getSubReg());
96 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
97 // That won't happen in legal code.
98 setSubReg(0);
99 if (isDef())
100 setIsUndef(false);
101 }
102 setReg(Reg);
103}
104
105/// Change a def to a use, or a use to a def.
106void MachineOperand::setIsDef(bool Val) {
107 assert(isReg() && "Wrong MachineOperand accessor");
108 assert((!Val || !isDebug()) && "Marking a debug operation as def");
109 if (IsDef == Val)
110 return;
111 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
112 // MRI may keep uses and defs in different list positions.
113 if (MachineFunction *MF = getMFIfAvailable(MO&: *this)) {
114 MachineRegisterInfo &MRI = MF->getRegInfo();
115 MRI.removeRegOperandFromUseList(MO: this);
116 IsDef = Val;
117 MRI.addRegOperandToUseList(MO: this);
118 return;
119 }
120 IsDef = Val;
121}
122
123bool MachineOperand::isRenamable() const {
124 assert(isReg() && "Wrong MachineOperand accessor");
125 assert(getReg().isPhysical() &&
126 "isRenamable should only be checked on physical registers");
127 if (!IsRenamable)
128 return false;
129
130 const MachineInstr *MI = getParent();
131 if (!MI)
132 return true;
133
134 if (isDef())
135 return !MI->hasExtraDefRegAllocReq(Type: MachineInstr::IgnoreBundle);
136
137 assert(isUse() && "Reg is not def or use");
138 return !MI->hasExtraSrcRegAllocReq(Type: MachineInstr::IgnoreBundle);
139}
140
141void MachineOperand::setIsRenamable(bool Val) {
142 assert(isReg() && "Wrong MachineOperand accessor");
143 assert(getReg().isPhysical() &&
144 "setIsRenamable should only be called on physical registers");
145 IsRenamable = Val;
146}
147
148// If this operand is currently a register operand, and if this is in a
149// function, deregister the operand from the register's use/def list.
150void MachineOperand::removeRegFromUses() {
151 if (!isReg() || !isOnRegUseList())
152 return;
153
154 if (MachineFunction *MF = getMFIfAvailable(MO&: *this))
155 MF->getRegInfo().removeRegOperandFromUseList(MO: this);
156}
157
158/// ChangeToImmediate - Replace this operand with a new immediate operand of
159/// the specified value. If an operand is known to be an immediate already,
160/// the setImm method should be used.
161void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
162 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
163
164 removeRegFromUses();
165
166 OpKind = MO_Immediate;
167 Contents.ImmVal = ImmVal;
168 setTargetFlags(TargetFlags);
169}
170
171void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,
172 unsigned TargetFlags) {
173 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
174
175 removeRegFromUses();
176
177 OpKind = MO_FPImmediate;
178 Contents.CFP = FPImm;
179 setTargetFlags(TargetFlags);
180}
181
182void MachineOperand::ChangeToES(const char *SymName,
183 unsigned TargetFlags) {
184 assert((!isReg() || !isTied()) &&
185 "Cannot change a tied operand into an external symbol");
186
187 removeRegFromUses();
188
189 OpKind = MO_ExternalSymbol;
190 Contents.OffsetedInfo.Val.SymbolName = SymName;
191 setOffset(0); // Offset is always 0.
192 setTargetFlags(TargetFlags);
193}
194
195void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
196 unsigned TargetFlags) {
197 assert((!isReg() || !isTied()) &&
198 "Cannot change a tied operand into a global address");
199
200 removeRegFromUses();
201
202 OpKind = MO_GlobalAddress;
203 Contents.OffsetedInfo.Val.GV = GV;
204 setOffset(Offset);
205 setTargetFlags(TargetFlags);
206}
207
208void MachineOperand::ChangeToBA(const BlockAddress *BA, int64_t Offset,
209 unsigned TargetFlags) {
210 assert((!isReg() || !isTied()) &&
211 "Cannot change a tied operand into a block address");
212
213 removeRegFromUses();
214
215 OpKind = MO_BlockAddress;
216 Contents.OffsetedInfo.Val.BA = BA;
217 setOffset(Offset);
218 setTargetFlags(TargetFlags);
219}
220
221void MachineOperand::ChangeToCPI(unsigned Idx, int Offset,
222 unsigned TargetFlags) {
223 assert((!isReg() || !isTied()) &&
224 "Cannot change a tied operand into a constant pool index");
225
226 removeRegFromUses();
227
228 OpKind = MO_ConstantPoolIndex;
229 setIndex(Idx);
230 setOffset(Offset);
231 setTargetFlags(TargetFlags);
232}
233
234void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
235 assert((!isReg() || !isTied()) &&
236 "Cannot change a tied operand into an MCSymbol");
237
238 removeRegFromUses();
239
240 OpKind = MO_MCSymbol;
241 Contents.Sym = Sym;
242 setTargetFlags(TargetFlags);
243}
244
245void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
246 assert((!isReg() || !isTied()) &&
247 "Cannot change a tied operand into a FrameIndex");
248
249 removeRegFromUses();
250
251 OpKind = MO_FrameIndex;
252 setIndex(Idx);
253 setTargetFlags(TargetFlags);
254}
255
256void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
257 unsigned TargetFlags) {
258 assert((!isReg() || !isTied()) &&
259 "Cannot change a tied operand into a FrameIndex");
260
261 removeRegFromUses();
262
263 OpKind = MO_TargetIndex;
264 setIndex(Idx);
265 setOffset(Offset);
266 setTargetFlags(TargetFlags);
267}
268
269void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
270 unsigned TargetFlags) {
271 assert((!isReg() || !isTied()) &&
272 "Cannot change a tied operand into a DbgInstrRef");
273
274 removeRegFromUses();
275
276 OpKind = MO_DbgInstrRef;
277 setInstrRefInstrIndex(InstrIdx);
278 setInstrRefOpIndex(OpIdx);
279 setTargetFlags(TargetFlags);
280}
281
282/// ChangeToRegister - Replace this operand with a new register operand of
283/// the specified value. If an operand is known to be an register already,
284/// the setReg method should be used.
285void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
286 bool isKill, bool isDead, bool isUndef,
287 bool isDebug) {
288 MachineRegisterInfo *RegInfo = nullptr;
289 if (MachineFunction *MF = getMFIfAvailable(MO&: *this))
290 RegInfo = &MF->getRegInfo();
291 // If this operand is already a register operand, remove it from the
292 // register's use/def lists.
293 bool WasReg = isReg();
294 if (RegInfo && WasReg)
295 RegInfo->removeRegOperandFromUseList(MO: this);
296
297 // Ensure debug instructions set debug flag on register uses.
298 const MachineInstr *MI = getParent();
299 if (!isDef && MI && MI->isDebugInstr())
300 isDebug = true;
301
302 // Change this to a register and set the reg#.
303 assert(!(isDead && !isDef) && "Dead flag on non-def");
304 assert(!(isKill && isDef) && "Kill flag on def");
305 OpKind = MO_Register;
306 SmallContents.RegNo = Reg.id();
307 SubReg_TargetFlags = 0;
308 IsDef = isDef;
309 IsImp = isImp;
310 IsDeadOrKill = isKill | isDead;
311 IsRenamable = false;
312 IsUndef = isUndef;
313 IsInternalRead = false;
314 IsEarlyClobber = false;
315 IsDebug = isDebug;
316 // Ensure isOnRegUseList() returns false.
317 Contents.Reg.Prev = nullptr;
318 // Preserve the tie when the operand was already a register.
319 if (!WasReg)
320 TiedTo = 0;
321
322 // If this operand is embedded in a function, add the operand to the
323 // register's use/def list.
324 if (RegInfo)
325 RegInfo->addRegOperandToUseList(MO: this);
326}
327
328/// isIdenticalTo - Return true if this operand is identical to the specified
329/// operand. Note that this should stay in sync with the hash_value overload
330/// below.
331bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
332 if (getType() != Other.getType() ||
333 getTargetFlags() != Other.getTargetFlags())
334 return false;
335
336 switch (getType()) {
337 case MachineOperand::MO_Register:
338 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
339 getSubReg() == Other.getSubReg();
340 case MachineOperand::MO_Immediate:
341 return getImm() == Other.getImm();
342 case MachineOperand::MO_CImmediate:
343 return getCImm() == Other.getCImm();
344 case MachineOperand::MO_FPImmediate:
345 return getFPImm() == Other.getFPImm();
346 case MachineOperand::MO_MachineBasicBlock:
347 return getMBB() == Other.getMBB();
348 case MachineOperand::MO_FrameIndex:
349 return getIndex() == Other.getIndex();
350 case MachineOperand::MO_ConstantPoolIndex:
351 case MachineOperand::MO_TargetIndex:
352 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
353 case MachineOperand::MO_JumpTableIndex:
354 return getIndex() == Other.getIndex();
355 case MachineOperand::MO_GlobalAddress:
356 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
357 case MachineOperand::MO_ExternalSymbol:
358 return strcmp(s1: getSymbolName(), s2: Other.getSymbolName()) == 0 &&
359 getOffset() == Other.getOffset();
360 case MachineOperand::MO_BlockAddress:
361 return getBlockAddress() == Other.getBlockAddress() &&
362 getOffset() == Other.getOffset();
363 case MachineOperand::MO_RegisterMask:
364 case MachineOperand::MO_RegisterLiveOut: {
365 // Shallow compare of the two RegMasks
366 const uint32_t *RegMask = isRegMask() ? getRegMask() : getRegLiveOut();
367 const uint32_t *OtherRegMask =
368 isRegMask() ? Other.getRegMask() : Other.getRegLiveOut();
369 if (RegMask == OtherRegMask)
370 return true;
371
372 if (const MachineFunction *MF = getMFIfAvailable(MO: *this)) {
373 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
374 unsigned RegMaskSize = MachineOperand::getRegMaskSize(NumRegs: TRI->getNumRegs());
375 // Deep compare of the two RegMasks
376 return std::equal(first1: RegMask, last1: RegMask + RegMaskSize, first2: OtherRegMask);
377 }
378 // We don't know the size of the RegMask, so we can't deep compare the two
379 // reg masks.
380 return false;
381 }
382 case MachineOperand::MO_MCSymbol:
383 return getMCSymbol() == Other.getMCSymbol();
384 case MachineOperand::MO_DbgInstrRef:
385 return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
386 getInstrRefOpIndex() == Other.getInstrRefOpIndex();
387 case MachineOperand::MO_CFIIndex:
388 return getCFIIndex() == Other.getCFIIndex();
389 case MachineOperand::MO_Metadata:
390 return getMetadata() == Other.getMetadata();
391 case MachineOperand::MO_IntrinsicID:
392 return getIntrinsicID() == Other.getIntrinsicID();
393 case MachineOperand::MO_Predicate:
394 return getPredicate() == Other.getPredicate();
395 case MachineOperand::MO_ShuffleMask:
396 return getShuffleMask() == Other.getShuffleMask();
397 case MachineOperand::MO_LaneMask:
398 return getLaneMask() == Other.getLaneMask();
399 }
400 llvm_unreachable("Invalid machine operand type");
401}
402
403// Note: this must stay exactly in sync with isIdenticalTo above.
404hash_code llvm::hash_value(const MachineOperand &MO) {
405 switch (MO.getType()) {
406 case MachineOperand::MO_Register:
407 // Register operands don't have target flags.
408 return hash_combine(args: MO.getType(), args: MO.getReg().id(), args: MO.getSubReg(),
409 args: MO.isDef());
410 case MachineOperand::MO_Immediate:
411 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getImm());
412 case MachineOperand::MO_CImmediate:
413 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getCImm());
414 case MachineOperand::MO_FPImmediate:
415 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getFPImm());
416 case MachineOperand::MO_MachineBasicBlock:
417 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getMBB());
418 case MachineOperand::MO_FrameIndex:
419 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getIndex());
420 case MachineOperand::MO_ConstantPoolIndex:
421 case MachineOperand::MO_TargetIndex:
422 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getIndex(),
423 args: MO.getOffset());
424 case MachineOperand::MO_JumpTableIndex:
425 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getIndex());
426 case MachineOperand::MO_ExternalSymbol:
427 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getOffset(),
428 args: StringRef(MO.getSymbolName()));
429 case MachineOperand::MO_GlobalAddress:
430 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getGlobal(),
431 args: MO.getOffset());
432 case MachineOperand::MO_BlockAddress:
433 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getBlockAddress(),
434 args: MO.getOffset());
435 case MachineOperand::MO_RegisterMask:
436 case MachineOperand::MO_RegisterLiveOut: {
437 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
438 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
439 unsigned RegMaskSize = MachineOperand::getRegMaskSize(NumRegs: TRI->getNumRegs());
440 const uint32_t *RegMask =
441 MO.isRegMask() ? MO.getRegMask() : MO.getRegLiveOut();
442 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
443 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(),
444 args: stable_hash_combine(Buffer: RegMaskHashes));
445 }
446
447 assert(0 && "MachineOperand not associated with any MachineFunction");
448 return hash_combine(args: MO.getType(), args: MO.getTargetFlags());
449 }
450 case MachineOperand::MO_Metadata:
451 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getMetadata());
452 case MachineOperand::MO_MCSymbol:
453 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getMCSymbol());
454 case MachineOperand::MO_DbgInstrRef:
455 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(),
456 args: MO.getInstrRefInstrIndex(), args: MO.getInstrRefOpIndex());
457 case MachineOperand::MO_CFIIndex:
458 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getCFIIndex());
459 case MachineOperand::MO_IntrinsicID:
460 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getIntrinsicID());
461 case MachineOperand::MO_Predicate:
462 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getPredicate());
463 case MachineOperand::MO_ShuffleMask:
464 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(), args: MO.getShuffleMask());
465 case MachineOperand::MO_LaneMask:
466 return hash_combine(args: MO.getType(), args: MO.getTargetFlags(),
467 args: MO.getLaneMask().getAsInteger());
468 }
469 llvm_unreachable("Invalid machine operand type");
470}
471
472// Try to crawl up to the machine function and get TRI from it.
473static void tryToGetTargetInfo(const MachineOperand &MO,
474 const TargetRegisterInfo *&TRI) {
475 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
476 TRI = MF->getSubtarget().getRegisterInfo();
477 }
478}
479
480static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
481 const auto *TII = MF.getSubtarget().getInstrInfo();
482 assert(TII && "expected instruction info");
483 auto Indices = TII->getSerializableTargetIndices();
484 auto Found = find_if(Range&: Indices, P: [&](const std::pair<int, const char *> &I) {
485 return I.first == Index;
486 });
487 if (Found != Indices.end())
488 return Found->second;
489 return nullptr;
490}
491
492const char *MachineOperand::getTargetIndexName() const {
493 const MachineFunction *MF = getMFIfAvailable(MO: *this);
494 return MF ? ::getTargetIndexName(MF: *MF, Index: this->getIndex()) : nullptr;
495}
496
497static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
498 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
499 for (const auto &I : Flags) {
500 if (I.first == TF) {
501 return I.second;
502 }
503 }
504 return nullptr;
505}
506
507static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
508 const TargetRegisterInfo *TRI) {
509 if (!TRI) {
510 OS << "%dwarfreg." << DwarfReg;
511 return;
512 }
513
514 if (std::optional<MCRegister> Reg = TRI->getLLVMRegNum(RegNum: DwarfReg, isEH: true))
515 OS << printReg(Reg: *Reg, TRI);
516 else
517 OS << "<badreg>";
518}
519
520static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
521 ModuleSlotTracker &MST) {
522 OS << "%ir-block.";
523 if (BB.hasName()) {
524 printLLVMNameWithoutPrefix(OS, Name: BB.getName());
525 return;
526 }
527 std::optional<int> Slot;
528 if (const Function *F = BB.getParent()) {
529 if (F == MST.getCurrentFunction()) {
530 Slot = MST.getLocalSlot(V: &BB);
531 } else if (const Module *M = F->getParent()) {
532 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
533 CustomMST.incorporateFunction(F: *F);
534 Slot = CustomMST.getLocalSlot(V: &BB);
535 }
536 }
537 if (Slot)
538 MachineOperand::printIRSlotNumber(OS, Slot: *Slot);
539 else
540 OS << "<unknown>";
541}
542
543static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
544 SyncScope::ID SSID,
545 SmallVectorImpl<StringRef> &SSNs) {
546 switch (SSID) {
547 case SyncScope::System:
548 break;
549 default:
550 if (SSNs.empty())
551 Context.getSyncScopeNames(SSNs);
552
553 OS << "syncscope(\"";
554 printEscapedString(Name: SSNs[SSID], Out&: OS);
555 OS << "\") ";
556 break;
557 }
558}
559
560static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
561 unsigned TMMOFlag) {
562 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
563 for (const auto &I : Flags) {
564 if (I.first == TMMOFlag) {
565 return I.second;
566 }
567 }
568 return nullptr;
569}
570
571static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
572 const MachineFrameInfo *MFI) {
573 StringRef Name;
574 if (MFI) {
575 IsFixed = MFI->isFixedObjectIndex(ObjectIdx: FrameIndex);
576 if (const AllocaInst *Alloca = MFI->getObjectAllocation(ObjectIdx: FrameIndex))
577 if (Alloca->hasName())
578 Name = Alloca->getName();
579 if (IsFixed)
580 FrameIndex -= MFI->getObjectIndexBegin();
581 }
582 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
583}
584
585void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
586 const TargetRegisterInfo *TRI) {
587 OS << "%subreg.";
588 if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
589 OS << TRI->getSubRegIndexName(SubIdx: Index);
590 else
591 OS << Index;
592}
593
594void MachineOperand::printTargetFlags(raw_ostream &OS,
595 const MachineOperand &Op) {
596 if (!Op.getTargetFlags())
597 return;
598 const MachineFunction *MF = getMFIfAvailable(MO: Op);
599 if (!MF)
600 return;
601
602 const auto *TII = MF->getSubtarget().getInstrInfo();
603 assert(TII && "expected instruction info");
604 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
605 OS << "target-flags(";
606 const bool HasDirectFlags = Flags.first;
607 const bool HasBitmaskFlags = Flags.second;
608 if (!HasDirectFlags && !HasBitmaskFlags) {
609 OS << "<unknown>) ";
610 return;
611 }
612 if (HasDirectFlags) {
613 if (const auto *Name = getTargetFlagName(TII, TF: Flags.first))
614 OS << Name;
615 else
616 OS << "<unknown target flag>";
617 }
618 if (!HasBitmaskFlags) {
619 OS << ") ";
620 return;
621 }
622 bool IsCommaNeeded = HasDirectFlags;
623 unsigned BitMask = Flags.second;
624 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
625 for (const auto &Mask : BitMasks) {
626 // Check if the flag's bitmask has the bits of the current mask set.
627 if ((BitMask & Mask.first) == Mask.first) {
628 if (IsCommaNeeded)
629 OS << ", ";
630 IsCommaNeeded = true;
631 OS << Mask.second;
632 // Clear the bits which were serialized from the flag's bitmask.
633 BitMask &= ~(Mask.first);
634 }
635 }
636 if (BitMask) {
637 // When the resulting flag's bitmask isn't zero, we know that we didn't
638 // serialize all of the bit flags.
639 if (IsCommaNeeded)
640 OS << ", ";
641 OS << "<unknown bitmask target flag>";
642 }
643 OS << ") ";
644}
645
646void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
647 OS << "<mcsymbol " << Sym << ">";
648}
649
650void MachineOperand::printStackObjectReference(raw_ostream &OS,
651 unsigned FrameIndex,
652 bool IsFixed, StringRef Name) {
653 if (IsFixed) {
654 OS << "%fixed-stack." << FrameIndex;
655 return;
656 }
657
658 OS << "%stack." << FrameIndex;
659 if (!Name.empty())
660 OS << '.' << Name;
661}
662
663void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
664 if (Offset == 0)
665 return;
666 if (Offset < 0) {
667 OS << " - " << -Offset;
668 return;
669 }
670 OS << " + " << Offset;
671}
672
673void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
674 if (Slot == -1)
675 OS << "<badref>";
676 else
677 OS << Slot;
678}
679
680static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
681 const TargetRegisterInfo *TRI) {
682 switch (CFI.getOperation()) {
683 case MCCFIInstruction::OpSameValue:
684 OS << "same_value ";
685 if (MCSymbol *Label = CFI.getLabel())
686 MachineOperand::printSymbol(OS, Sym&: *Label);
687 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
688 break;
689 case MCCFIInstruction::OpRememberState:
690 OS << "remember_state ";
691 if (MCSymbol *Label = CFI.getLabel())
692 MachineOperand::printSymbol(OS, Sym&: *Label);
693 break;
694 case MCCFIInstruction::OpRestoreState:
695 OS << "restore_state ";
696 if (MCSymbol *Label = CFI.getLabel())
697 MachineOperand::printSymbol(OS, Sym&: *Label);
698 break;
699 case MCCFIInstruction::OpOffset:
700 OS << "offset ";
701 if (MCSymbol *Label = CFI.getLabel())
702 MachineOperand::printSymbol(OS, Sym&: *Label);
703 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
704 OS << ", " << CFI.getOffset();
705 break;
706 case MCCFIInstruction::OpDefCfaRegister:
707 OS << "def_cfa_register ";
708 if (MCSymbol *Label = CFI.getLabel())
709 MachineOperand::printSymbol(OS, Sym&: *Label);
710 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
711 break;
712 case MCCFIInstruction::OpDefCfaOffset:
713 OS << "def_cfa_offset ";
714 if (MCSymbol *Label = CFI.getLabel())
715 MachineOperand::printSymbol(OS, Sym&: *Label);
716 OS << CFI.getOffset();
717 break;
718 case MCCFIInstruction::OpDefCfa:
719 OS << "def_cfa ";
720 if (MCSymbol *Label = CFI.getLabel())
721 MachineOperand::printSymbol(OS, Sym&: *Label);
722 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
723 OS << ", " << CFI.getOffset();
724 break;
725 case MCCFIInstruction::OpLLVMDefAspaceCfa:
726 OS << "llvm_def_aspace_cfa ";
727 if (MCSymbol *Label = CFI.getLabel())
728 MachineOperand::printSymbol(OS, Sym&: *Label);
729 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
730 OS << ", " << CFI.getOffset();
731 OS << ", " << CFI.getAddressSpace();
732 break;
733 case MCCFIInstruction::OpRelOffset:
734 OS << "rel_offset ";
735 if (MCSymbol *Label = CFI.getLabel())
736 MachineOperand::printSymbol(OS, Sym&: *Label);
737 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
738 OS << ", " << CFI.getOffset();
739 break;
740 case MCCFIInstruction::OpAdjustCfaOffset:
741 OS << "adjust_cfa_offset ";
742 if (MCSymbol *Label = CFI.getLabel())
743 MachineOperand::printSymbol(OS, Sym&: *Label);
744 OS << CFI.getOffset();
745 break;
746 case MCCFIInstruction::OpRestore:
747 OS << "restore ";
748 if (MCSymbol *Label = CFI.getLabel())
749 MachineOperand::printSymbol(OS, Sym&: *Label);
750 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
751 break;
752 case MCCFIInstruction::OpEscape: {
753 OS << "escape ";
754 if (MCSymbol *Label = CFI.getLabel())
755 MachineOperand::printSymbol(OS, Sym&: *Label);
756 if (!CFI.getValues().empty()) {
757 size_t e = CFI.getValues().size() - 1;
758 for (size_t i = 0; i < e; ++i)
759 OS << format(Fmt: "0x%02x", Vals: uint8_t(CFI.getValues()[i])) << ", ";
760 OS << format(Fmt: "0x%02x", Vals: uint8_t(CFI.getValues()[e]));
761 }
762 break;
763 }
764 case MCCFIInstruction::OpUndefined:
765 OS << "undefined ";
766 if (MCSymbol *Label = CFI.getLabel())
767 MachineOperand::printSymbol(OS, Sym&: *Label);
768 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
769 break;
770 case MCCFIInstruction::OpRegister:
771 OS << "register ";
772 if (MCSymbol *Label = CFI.getLabel())
773 MachineOperand::printSymbol(OS, Sym&: *Label);
774 printCFIRegister(DwarfReg: CFI.getRegister(), OS, TRI);
775 OS << ", ";
776 printCFIRegister(DwarfReg: CFI.getRegister2(), OS, TRI);
777 break;
778 case MCCFIInstruction::OpWindowSave:
779 OS << "window_save ";
780 if (MCSymbol *Label = CFI.getLabel())
781 MachineOperand::printSymbol(OS, Sym&: *Label);
782 break;
783 case MCCFIInstruction::OpNegateRAState:
784 OS << "negate_ra_sign_state ";
785 if (MCSymbol *Label = CFI.getLabel())
786 MachineOperand::printSymbol(OS, Sym&: *Label);
787 break;
788 case MCCFIInstruction::OpNegateRAStateWithPC:
789 OS << "negate_ra_sign_state_with_pc ";
790 if (MCSymbol *Label = CFI.getLabel())
791 MachineOperand::printSymbol(OS, Sym&: *Label);
792 break;
793 case MCCFIInstruction::OpLLVMSetRAState: {
794 OS << "llvm_set_ra_state ";
795 if (MCSymbol *Label = CFI.getLabel())
796 MachineOperand::printSymbol(OS, Sym&: *Label);
797 OS << CFI.getRASignState() << ", ";
798 if (MCSymbol *PACSym = CFI.getRASignSymbol())
799 MachineOperand::printSymbol(OS, Sym&: *PACSym);
800 else
801 OS << CFI.getRASignOffset();
802 break;
803 }
804 case MCCFIInstruction::OpLLVMRegisterPair: {
805 const auto &Fields =
806 CFI.getExtraFields<MCCFIInstruction::RegisterPairFields>();
807
808 OS << "llvm_register_pair ";
809 if (MCSymbol *Label = CFI.getLabel())
810 MachineOperand::printSymbol(OS, Sym&: *Label);
811 printCFIRegister(DwarfReg: Fields.Register, OS, TRI);
812 OS << ", ";
813 printCFIRegister(DwarfReg: Fields.Reg1, OS, TRI);
814 OS << ", " << Fields.Reg1SizeInBits << ", ";
815 printCFIRegister(DwarfReg: Fields.Reg2, OS, TRI);
816 OS << ", " << Fields.Reg2SizeInBits;
817 break;
818 }
819 case MCCFIInstruction::OpLLVMVectorRegisters: {
820 const auto &Fields =
821 CFI.getExtraFields<MCCFIInstruction::VectorRegistersFields>();
822
823 OS << "llvm_vector_registers ";
824 if (MCSymbol *Label = CFI.getLabel())
825 MachineOperand::printSymbol(OS, Sym&: *Label);
826 printCFIRegister(DwarfReg: Fields.Register, OS, TRI);
827 for (auto [Reg, Lane, Size] : Fields.VectorRegisters) {
828 OS << ", ";
829 printCFIRegister(DwarfReg: Reg, OS, TRI);
830 OS << ", " << Lane << ", " << Size;
831 }
832 break;
833 }
834 case MCCFIInstruction::OpLLVMVectorOffset: {
835 const auto &Fields =
836 CFI.getExtraFields<MCCFIInstruction::VectorOffsetFields>();
837
838 OS << "llvm_vector_offset ";
839 if (MCSymbol *Label = CFI.getLabel())
840 MachineOperand::printSymbol(OS, Sym&: *Label);
841 printCFIRegister(DwarfReg: Fields.Register, OS, TRI);
842 OS << ", " << Fields.RegisterSizeInBits << ", ";
843 printCFIRegister(DwarfReg: Fields.MaskRegister, OS, TRI);
844 OS << ", " << Fields.MaskRegisterSizeInBits << ", " << Fields.Offset;
845 break;
846 }
847 case MCCFIInstruction::OpLLVMVectorRegisterMask: {
848 const auto &Fields =
849 CFI.getExtraFields<MCCFIInstruction::VectorRegisterMaskFields>();
850
851 OS << "llvm_vector_register_mask ";
852 if (MCSymbol *Label = CFI.getLabel())
853 MachineOperand::printSymbol(OS, Sym&: *Label);
854 printCFIRegister(DwarfReg: Fields.Register, OS, TRI);
855 OS << ", ";
856 printCFIRegister(DwarfReg: Fields.SpillRegister, OS, TRI);
857 OS << ", " << Fields.SpillRegisterLaneSizeInBits << ", ";
858 printCFIRegister(DwarfReg: Fields.MaskRegister, OS, TRI);
859 OS << ", " << Fields.MaskRegisterSizeInBits;
860 break;
861 }
862 default:
863 // TODO: Print the other CFI Operations.
864 OS << "<unserializable cfi directive>";
865 break;
866 }
867}
868
869void MachineOperand::print(raw_ostream &OS,
870 const TargetRegisterInfo *TRI) const {
871 print(os&: OS, TypeToPrint: LLT{}, TRI);
872}
873
874void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
875 const TargetRegisterInfo *TRI) const {
876 tryToGetTargetInfo(MO: *this, TRI);
877 ModuleSlotTracker DummyMST(nullptr);
878 print(os&: OS, MST&: DummyMST, TypeToPrint, OpIdx: std::nullopt, /*PrintDef=*/false,
879 /*IsStandalone=*/true,
880 /*ShouldPrintRegisterTies=*/true,
881 /*TiedOperandIdx=*/0, TRI);
882}
883
884void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
885 LLT TypeToPrint, std::optional<unsigned> OpIdx,
886 bool PrintDef, bool IsStandalone,
887 bool ShouldPrintRegisterTies,
888 unsigned TiedOperandIdx,
889 const TargetRegisterInfo *TRI) const {
890 printTargetFlags(OS, Op: *this);
891 switch (getType()) {
892 case MachineOperand::MO_Register: {
893 Register Reg = getReg();
894 if (isImplicit())
895 OS << (isDef() ? "implicit-def " : "implicit ");
896 else if (PrintDef && isDef())
897 // Print the 'def' flag only when the operand is defined after '='.
898 OS << "def ";
899 if (isInternalRead())
900 OS << "internal ";
901 if (isDead())
902 OS << "dead ";
903 if (isKill())
904 OS << "killed ";
905 if (isUndef())
906 OS << "undef ";
907 if (isEarlyClobber())
908 OS << "early-clobber ";
909 if (getReg().isPhysical() && isRenamable())
910 OS << "renamable ";
911 // isDebug() is exactly true for register operands of a DBG_VALUE. So we
912 // simply infer it when parsing and do not need to print it.
913
914 const MachineRegisterInfo *MRI = nullptr;
915 if (Reg.isVirtual()) {
916 if (const MachineFunction *MF = getMFIfAvailable(MO: *this)) {
917 MRI = &MF->getRegInfo();
918 }
919 }
920
921 OS << printReg(Reg, TRI, SubIdx: 0, MRI);
922 // Print the sub register.
923 if (unsigned SubReg = getSubReg()) {
924 if (TRI)
925 OS << '.' << TRI->getSubRegIndexName(SubIdx: SubReg);
926 else
927 OS << ".subreg" << SubReg;
928 }
929 // Print the register class / bank.
930 if (Reg.isVirtual()) {
931 if (const MachineFunction *MF = getMFIfAvailable(MO: *this)) {
932 const MachineRegisterInfo &MRI = MF->getRegInfo();
933 if (IsStandalone || !PrintDef || MRI.def_empty(RegNo: Reg)) {
934 OS << ':';
935 OS << printRegClassOrBank(Reg, RegInfo: MRI, TRI);
936 }
937 }
938 }
939 // Print ties.
940 if (ShouldPrintRegisterTies && isTied() && !isDef())
941 OS << "(tied-def " << TiedOperandIdx << ")";
942 // Print types.
943 if (TypeToPrint.isValid())
944 OS << '(' << TypeToPrint << ')';
945 break;
946 }
947 case MachineOperand::MO_Immediate: {
948 const MIRFormatter *Formatter = nullptr;
949 if (const MachineFunction *MF = getMFIfAvailable(MO: *this)) {
950 const auto *TII = MF->getSubtarget().getInstrInfo();
951 assert(TII && "expected instruction info");
952 Formatter = TII->getMIRFormatter();
953 }
954 if (Formatter)
955 Formatter->printImm(OS, MI: *getParent(), OpIdx, Imm: getImm());
956 else
957 OS << getImm();
958 break;
959 }
960 case MachineOperand::MO_CImmediate:
961 getCImm()->printAsOperand(O&: OS, /*PrintType=*/true, MST);
962 break;
963 case MachineOperand::MO_FPImmediate:
964 getFPImm()->printAsOperand(O&: OS, /*PrintType=*/true, MST);
965 break;
966 case MachineOperand::MO_MachineBasicBlock:
967 OS << printMBBReference(MBB: *getMBB());
968 break;
969 case MachineOperand::MO_FrameIndex: {
970 int FrameIndex = getIndex();
971 bool IsFixed = false;
972 const MachineFrameInfo *MFI = nullptr;
973 if (const MachineFunction *MF = getMFIfAvailable(MO: *this))
974 MFI = &MF->getFrameInfo();
975 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
976 break;
977 }
978 case MachineOperand::MO_ConstantPoolIndex:
979 OS << "%const." << getIndex();
980 printOperandOffset(OS, Offset: getOffset());
981 break;
982 case MachineOperand::MO_TargetIndex: {
983 OS << "target-index(";
984 const char *Name = "<unknown>";
985 if (const MachineFunction *MF = getMFIfAvailable(MO: *this))
986 if (const auto *TargetIndexName = ::getTargetIndexName(MF: *MF, Index: getIndex()))
987 Name = TargetIndexName;
988 OS << Name << ')';
989 printOperandOffset(OS, Offset: getOffset());
990 break;
991 }
992 case MachineOperand::MO_JumpTableIndex:
993 OS << printJumpTableEntryReference(Idx: getIndex());
994 break;
995 case MachineOperand::MO_GlobalAddress:
996 if (auto *GV = getGlobal())
997 GV->printAsOperand(O&: OS, /*PrintType=*/false, MST);
998 else // Invalid, but may appear in debugging scenarios.
999 OS << "globaladdress(null)";
1000
1001 printOperandOffset(OS, Offset: getOffset());
1002 break;
1003 case MachineOperand::MO_ExternalSymbol: {
1004 StringRef Name = getSymbolName();
1005 OS << '&';
1006 if (Name.empty()) {
1007 OS << "\"\"";
1008 } else {
1009 printLLVMNameWithoutPrefix(OS, Name);
1010 }
1011 printOperandOffset(OS, Offset: getOffset());
1012 break;
1013 }
1014 case MachineOperand::MO_BlockAddress: {
1015 OS << "blockaddress(";
1016 getBlockAddress()->getFunction()->printAsOperand(O&: OS, /*PrintType=*/false,
1017 MST);
1018 OS << ", ";
1019 printIRBlockReference(OS, BB: *getBlockAddress()->getBasicBlock(), MST);
1020 OS << ')';
1021 MachineOperand::printOperandOffset(OS, Offset: getOffset());
1022 break;
1023 }
1024 case MachineOperand::MO_RegisterMask: {
1025 OS << "<regmask";
1026 if (TRI) {
1027 unsigned NumRegsInMask = 0;
1028 unsigned NumRegsEmitted = 0;
1029 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
1030 unsigned MaskWord = i / 32;
1031 unsigned MaskBit = i % 32;
1032 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
1033 if (PrintRegMaskNumRegs < 0 ||
1034 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
1035 OS << " " << printReg(Reg: i, TRI);
1036 NumRegsEmitted++;
1037 }
1038 NumRegsInMask++;
1039 }
1040 }
1041 if (NumRegsEmitted != NumRegsInMask)
1042 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
1043 } else {
1044 OS << " ...";
1045 }
1046 OS << ">";
1047 break;
1048 }
1049 case MachineOperand::MO_RegisterLiveOut: {
1050 const uint32_t *RegMask = getRegLiveOut();
1051 OS << "liveout(";
1052 if (!TRI) {
1053 OS << "<unknown>";
1054 } else {
1055 bool IsCommaNeeded = false;
1056 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
1057 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
1058 if (IsCommaNeeded)
1059 OS << ", ";
1060 OS << printReg(Reg, TRI);
1061 IsCommaNeeded = true;
1062 }
1063 }
1064 }
1065 OS << ")";
1066 break;
1067 }
1068 case MachineOperand::MO_Metadata:
1069 getMetadata()->printAsOperand(OS, MST);
1070 break;
1071 case MachineOperand::MO_MCSymbol:
1072 printSymbol(OS, Sym&: *getMCSymbol());
1073 break;
1074 case MachineOperand::MO_DbgInstrRef: {
1075 OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
1076 << getInstrRefOpIndex() << ')';
1077 break;
1078 }
1079 case MachineOperand::MO_CFIIndex: {
1080 if (const MachineFunction *MF = getMFIfAvailable(MO: *this))
1081 printCFI(OS, CFI: MF->getFrameInstructions()[getCFIIndex()], TRI);
1082 else
1083 OS << "<cfi directive>";
1084 break;
1085 }
1086 case MachineOperand::MO_IntrinsicID: {
1087 Intrinsic::ID ID = getIntrinsicID();
1088 if (ID < Intrinsic::num_intrinsics)
1089 OS << "intrinsic(@" << Intrinsic::getBaseName(id: ID) << ')';
1090 else
1091 OS << "intrinsic(" << ID << ')';
1092 break;
1093 }
1094 case MachineOperand::MO_Predicate: {
1095 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
1096 OS << (CmpInst::isIntPredicate(P: Pred) ? "int" : "float") << "pred(" << Pred
1097 << ')';
1098 break;
1099 }
1100 case MachineOperand::MO_ShuffleMask: {
1101 OS << "shufflemask(";
1102 ArrayRef<int> Mask = getShuffleMask();
1103 StringRef Separator;
1104 for (int Elt : Mask) {
1105 if (Elt == -1)
1106 OS << Separator << "undef";
1107 else
1108 OS << Separator << Elt;
1109 Separator = ", ";
1110 }
1111
1112 OS << ')';
1113 break;
1114 }
1115 case MachineOperand::MO_LaneMask: {
1116 OS << "lanemask(";
1117 LaneBitmask LaneMask = getLaneMask();
1118 OS << "0x" << PrintLaneMask(LaneMask);
1119 OS << ')';
1120 break;
1121 }
1122 }
1123}
1124
1125#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1126LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
1127#endif
1128
1129//===----------------------------------------------------------------------===//
1130// MachineMemOperand Implementation
1131//===----------------------------------------------------------------------===//
1132
1133/// getAddrSpace - Return the LLVM IR address space number that this pointer
1134/// points into.
1135unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
1136
1137/// isDereferenceable - Return true if V is always dereferenceable for
1138/// Offset + Size byte.
1139bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
1140 const DataLayout &DL) const {
1141 if (!isa<const Value *>(Val: V))
1142 return false;
1143
1144 const Value *BasePtr = cast<const Value *>(Val: V);
1145 if (BasePtr == nullptr)
1146 return false;
1147
1148 return isDereferenceablePointer(
1149 V: BasePtr, Size: APInt(DL.getPointerSizeInBits(), Offset + Size),
1150 Q: SimplifyQuery(DL, dyn_cast<Instruction>(Val: BasePtr)));
1151}
1152
1153/// getConstantPool - Return a MachinePointerInfo record that refers to the
1154/// constant pool.
1155MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
1156 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
1157}
1158
1159/// getFixedStack - Return a MachinePointerInfo record that refers to the
1160/// the specified FrameIndex.
1161MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
1162 int FI, int64_t Offset) {
1163 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
1164}
1165
1166MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1167 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1168}
1169
1170MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1171 return MachinePointerInfo(MF.getPSVManager().getGOT());
1172}
1173
1174MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1175 int64_t Offset, uint8_t ID) {
1176 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1177}
1178
1179MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1180 return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1181}
1182
1183MachineMemOperand::MachineMemOperand(MachinePointerInfo PtrInfo, Flags F,
1184 LLT Type, Align A,
1185 const MMOMetadata &Metadata,
1186 SyncScope::ID SSID,
1187 AtomicOrdering Ordering,
1188 AtomicOrdering FailureOrdering)
1189 : PtrInfo(PtrInfo), MemoryType(Type), FlagVals(F), BaseAlign(A),
1190 AAInfo(Metadata.AAInfo), Ranges(Metadata.Ranges),
1191 MemCacheHint(Metadata.MemCacheHint) {
1192 assert((PtrInfo.V.isNull() || isa<const PseudoSourceValue *>(PtrInfo.V) ||
1193 isa<PointerType>(cast<const Value *>(PtrInfo.V)->getType())) &&
1194 "invalid pointer value");
1195 assert((isLoad() || isStore()) && "Not a load/store!");
1196
1197 AtomicInfo.SSID = static_cast<unsigned>(SSID);
1198 assert(getSyncScopeID() == SSID && "Value truncated");
1199 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1200 assert(getSuccessOrdering() == Ordering && "Value truncated");
1201 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1202 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1203}
1204
1205MachineMemOperand::MachineMemOperand(MachinePointerInfo PtrInfo, Flags F,
1206 LocationSize TS, Align BaseAlignment,
1207 const MMOMetadata &Metadata,
1208 SyncScope::ID SSID,
1209 AtomicOrdering Ordering,
1210 AtomicOrdering FailureOrdering)
1211 : MachineMemOperand(
1212 PtrInfo, F,
1213 !TS.isPrecise() ? LLT()
1214 : TS.isScalable()
1215 ? LLT::scalable_vector(MinNumElements: 1, ScalarSizeInBits: 8 * TS.getValue().getKnownMinValue())
1216 : LLT::scalar(SizeInBits: 8 * TS.getValue().getKnownMinValue()),
1217 BaseAlignment, Metadata, SSID, Ordering, FailureOrdering) {}
1218
1219void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1220 // The Value and Offset may differ due to CSE. But the flags and size
1221 // should be the same.
1222 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1223 assert((!MMO->getSize().hasValue() || !getSize().hasValue() ||
1224 MMO->getSize() == getSize()) &&
1225 "Size mismatch!");
1226 if (MMO->getBaseAlign() >= getBaseAlign()) {
1227 // Update the alignment value.
1228 BaseAlign = MMO->getBaseAlign();
1229 // Also update the base and offset, because the new alignment may
1230 // not be applicable with the old ones.
1231 PtrInfo = MMO->PtrInfo;
1232 }
1233}
1234
1235/// getAlign - Return the minimum known alignment in bytes of the
1236/// actual memory reference.
1237Align MachineMemOperand::getAlign() const {
1238 return commonAlignment(A: getBaseAlign(), Offset: getOffset());
1239}
1240
1241void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1242 SmallVectorImpl<StringRef> &SSNs,
1243 const LLVMContext &Context,
1244 const MachineFrameInfo *MFI,
1245 const TargetInstrInfo *TII) const {
1246 OS << '(';
1247 if (isVolatile())
1248 OS << "volatile ";
1249 if (isNonTemporal())
1250 OS << "non-temporal ";
1251 if (isDereferenceable())
1252 OS << "dereferenceable ";
1253 if (isInvariant())
1254 OS << "invariant ";
1255 if (TII) {
1256 if (getFlags() & MachineMemOperand::MOTargetFlag1)
1257 OS << '"' << getTargetMMOFlagName(TII: *TII, TMMOFlag: MachineMemOperand::MOTargetFlag1)
1258 << "\" ";
1259 if (getFlags() & MachineMemOperand::MOTargetFlag2)
1260 OS << '"' << getTargetMMOFlagName(TII: *TII, TMMOFlag: MachineMemOperand::MOTargetFlag2)
1261 << "\" ";
1262 if (getFlags() & MachineMemOperand::MOTargetFlag3)
1263 OS << '"' << getTargetMMOFlagName(TII: *TII, TMMOFlag: MachineMemOperand::MOTargetFlag3)
1264 << "\" ";
1265 if (getFlags() & MachineMemOperand::MOTargetFlag4)
1266 OS << '"' << getTargetMMOFlagName(TII: *TII, TMMOFlag: MachineMemOperand::MOTargetFlag4)
1267 << "\" ";
1268 } else {
1269 if (getFlags() & MachineMemOperand::MOTargetFlag1)
1270 OS << "\"MOTargetFlag1\" ";
1271 if (getFlags() & MachineMemOperand::MOTargetFlag2)
1272 OS << "\"MOTargetFlag2\" ";
1273 if (getFlags() & MachineMemOperand::MOTargetFlag3)
1274 OS << "\"MOTargetFlag3\" ";
1275 if (getFlags() & MachineMemOperand::MOTargetFlag4)
1276 OS << "\"MOTargetFlag4\" ";
1277 }
1278
1279 assert((isLoad() || isStore()) &&
1280 "machine memory operand must be a load or store (or both)");
1281 if (isLoad())
1282 OS << "load ";
1283 if (isStore())
1284 OS << "store ";
1285
1286 printSyncScope(OS, Context, SSID: getSyncScopeID(), SSNs);
1287
1288 if (getSuccessOrdering() != AtomicOrdering::NotAtomic)
1289 OS << toIRString(ao: getSuccessOrdering()) << ' ';
1290 if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1291 OS << toIRString(ao: getFailureOrdering()) << ' ';
1292
1293 if (getMemoryType().isValid())
1294 OS << '(' << getMemoryType() << ')';
1295 else
1296 OS << "unknown-size";
1297
1298 if (const Value *Val = getValue()) {
1299 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1300 MIRFormatter::printIRValue(OS, V: *Val, MST);
1301 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1302 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1303 assert(PVal && "Expected a pseudo source value");
1304 switch (PVal->kind()) {
1305 case PseudoSourceValue::Stack:
1306 OS << "stack";
1307 break;
1308 case PseudoSourceValue::GOT:
1309 OS << "got";
1310 break;
1311 case PseudoSourceValue::JumpTable:
1312 OS << "jump-table";
1313 break;
1314 case PseudoSourceValue::ConstantPool:
1315 OS << "constant-pool";
1316 break;
1317 case PseudoSourceValue::FixedStack: {
1318 int FrameIndex = cast<FixedStackPseudoSourceValue>(Val: PVal)->getFrameIndex();
1319 bool IsFixed = true;
1320 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1321 break;
1322 }
1323 case PseudoSourceValue::GlobalValueCallEntry:
1324 OS << "call-entry ";
1325 cast<GlobalValuePseudoSourceValue>(Val: PVal)->getValue()->printAsOperand(
1326 O&: OS, /*PrintType=*/false, MST);
1327 break;
1328 case PseudoSourceValue::ExternalSymbolCallEntry:
1329 OS << "call-entry &";
1330 printLLVMNameWithoutPrefix(
1331 OS, Name: cast<ExternalSymbolPseudoSourceValue>(Val: PVal)->getSymbol());
1332 break;
1333 default: {
1334 // FIXME: This is not necessarily the correct MIR serialization format for
1335 // a custom pseudo source value, but at least it allows
1336 // MIR printing to work on a target with custom pseudo source
1337 // values.
1338 OS << "custom \"";
1339 if (TII) {
1340 const MIRFormatter *Formatter = TII->getMIRFormatter();
1341 Formatter->printCustomPseudoSourceValue(OS, MST, PSV: *PVal);
1342 } else {
1343 PVal->printCustom(O&: OS);
1344 }
1345 OS << '\"';
1346 break;
1347 }
1348 }
1349 } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1350 OS << ((isLoad() && isStore()) ? " on "
1351 : isLoad() ? " from "
1352 : " into ")
1353 << "unknown-address";
1354 }
1355 MachineOperand::printOperandOffset(OS, Offset: getOffset());
1356 if (!getSize().hasValue() ||
1357 (!getSize().isZero() &&
1358 getAlign() != getSize().getValue().getKnownMinValue()))
1359 OS << ", align " << getAlign().value();
1360 if (getAlign() != getBaseAlign())
1361 OS << ", basealign " << getBaseAlign().value();
1362 auto AAInfo = getAAInfo();
1363 if (AAInfo.TBAA) {
1364 OS << ", !tbaa ";
1365 AAInfo.TBAA->printAsOperand(OS, MST);
1366 }
1367 if (AAInfo.Scope) {
1368 OS << ", !alias.scope ";
1369 AAInfo.Scope->printAsOperand(OS, MST);
1370 }
1371 if (AAInfo.NoAlias) {
1372 OS << ", !noalias ";
1373 AAInfo.NoAlias->printAsOperand(OS, MST);
1374 }
1375 if (AAInfo.NoAliasAddrSpace) {
1376 OS << ", !noalias.addrspace ";
1377 AAInfo.NoAliasAddrSpace->printAsOperand(OS, MST);
1378 }
1379 if (getRanges()) {
1380 OS << ", !range ";
1381 getRanges()->printAsOperand(OS, MST);
1382 }
1383 if (getMemCacheHint()) {
1384 OS << ", !mem.cache_hint ";
1385 getMemCacheHint()->printAsOperand(OS, MST);
1386 }
1387 // FIXME: Implement addrspace printing/parsing in MIR.
1388 // For now, print this even though parsing it is not available in MIR.
1389 if (unsigned AS = getAddrSpace())
1390 OS << ", addrspace " << AS;
1391
1392 OS << ')';
1393}
1394