1//===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This pass is required to take advantage of the interprocedural register
10/// allocation infrastructure.
11///
12/// This pass is simple MachineFunction pass which collects register usage
13/// details by iterating through each physical registers and checking
14/// MRI::isPhysRegUsed() then creates a RegMask based on this details.
15/// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
16///
17//===----------------------------------------------------------------------===//
18
19#include "llvm/CodeGen/RegUsageInfoCollector.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/CodeGen/MachineFunctionPass.h"
22#include "llvm/CodeGen/MachineOperand.h"
23#include "llvm/CodeGen/MachinePassManager.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/Passes.h"
26#include "llvm/CodeGen/RegisterUsageInfo.h"
27#include "llvm/CodeGen/TargetFrameLowering.h"
28#include "llvm/IR/Function.h"
29#include "llvm/InitializePasses.h"
30#include "llvm/Support/Debug.h"
31#include "llvm/Support/raw_ostream.h"
32
33using namespace llvm;
34
35#define DEBUG_TYPE "ip-regalloc"
36
37STATISTIC(NumCSROpt,
38 "Number of functions optimized for callee saved registers");
39
40namespace {
41
42class RegUsageInfoCollector {
43 PhysicalRegisterUsageInfo &PRUI;
44
45public:
46 RegUsageInfoCollector(PhysicalRegisterUsageInfo &PRUI) : PRUI(PRUI) {}
47 bool run(MachineFunction &MF);
48
49 // Call getCalleeSaves and then also set the bits for subregs and
50 // fully saved superregs.
51 static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
52};
53
54class RegUsageInfoCollectorLegacy : public MachineFunctionPass {
55public:
56 static char ID;
57 RegUsageInfoCollectorLegacy() : MachineFunctionPass(ID) {}
58
59 StringRef getPassName() const override {
60 return "Register Usage Information Collector Pass";
61 }
62
63 void getAnalysisUsage(AnalysisUsage &AU) const override {
64 AU.addRequired<PhysicalRegisterUsageInfoWrapperLegacy>();
65 AU.setPreservesAll();
66 MachineFunctionPass::getAnalysisUsage(AU);
67 }
68
69 bool runOnMachineFunction(MachineFunction &MF) override;
70};
71} // end of anonymous namespace
72
73char RegUsageInfoCollectorLegacy::ID = 0;
74
75INITIALIZE_PASS_BEGIN(RegUsageInfoCollectorLegacy, "RegUsageInfoCollector",
76 "Register Usage Information Collector", false, false)
77INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfoWrapperLegacy)
78INITIALIZE_PASS_END(RegUsageInfoCollectorLegacy, "RegUsageInfoCollector",
79 "Register Usage Information Collector", false, false)
80
81FunctionPass *llvm::createRegUsageInfoCollector() {
82 return new RegUsageInfoCollectorLegacy();
83}
84
85// TODO: Move to hook somwehere?
86
87// Return true if it is useful to track the used registers for IPRA / no CSR
88// optimizations. This is not useful for entry points, and computing the
89// register usage information is expensive.
90static bool isCallableFunction(const MachineFunction &MF) {
91 switch (MF.getFunction().getCallingConv()) {
92 case CallingConv::AMDGPU_VS:
93 case CallingConv::AMDGPU_GS:
94 case CallingConv::AMDGPU_PS:
95 case CallingConv::AMDGPU_CS:
96 case CallingConv::AMDGPU_HS:
97 case CallingConv::AMDGPU_ES:
98 case CallingConv::AMDGPU_LS:
99 case CallingConv::AMDGPU_KERNEL:
100 return false;
101 default:
102 return true;
103 }
104}
105
106PreservedAnalyses
107RegUsageInfoCollectorPass::run(MachineFunction &MF,
108 MachineFunctionAnalysisManager &MFAM) {
109 Module &MFA = *MF.getFunction().getParent();
110 auto *PRUI = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(IR&: MF)
111 .getCachedResult<PhysicalRegisterUsageAnalysis>(IR&: MFA);
112 assert(PRUI && "PhysicalRegisterUsageAnalysis not available");
113 RegUsageInfoCollector(*PRUI).run(MF);
114 return PreservedAnalyses::all();
115}
116
117bool RegUsageInfoCollectorLegacy::runOnMachineFunction(MachineFunction &MF) {
118 PhysicalRegisterUsageInfo &PRUI =
119 getAnalysis<PhysicalRegisterUsageInfoWrapperLegacy>().getPRUI();
120 return RegUsageInfoCollector(PRUI).run(MF);
121}
122
123bool RegUsageInfoCollector::run(MachineFunction &MF) {
124 MachineRegisterInfo *MRI = &MF.getRegInfo();
125 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
126 const TargetMachine &TM = MF.getTarget();
127
128 LLVM_DEBUG(
129 dbgs()
130 << " -------------------- Register Usage Information Collector Pass"
131 << " -------------------- \nFunction Name : " << MF.getName() << '\n');
132
133 // Analyzing the register usage may be expensive on some targets.
134 if (!isCallableFunction(MF)) {
135 LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n");
136 return false;
137 }
138
139 // If there are no callers, there's no point in computing more precise
140 // register usage here.
141 if (MF.getFunction().use_empty()) {
142 LLVM_DEBUG(dbgs() << "Not analyzing function with no callers\n");
143 return false;
144 }
145
146 std::vector<uint32_t> RegMask;
147
148 // Compute the size of the bit vector to represent all the registers.
149 // The bit vector is broken into 32-bit chunks, thus takes the ceil of
150 // the number of registers divided by 32 for the size.
151 unsigned RegMaskSize = MachineOperand::getRegMaskSize(NumRegs: TRI->getNumRegs());
152 RegMask.resize(new_size: RegMaskSize, x: ~((uint32_t)0));
153
154 const Function &F = MF.getFunction();
155
156 PRUI.setTargetMachine(TM);
157
158 LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
159
160 BitVector SavedRegs;
161 computeCalleeSavedRegs(SavedRegs, MF);
162
163 const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
164 auto SetRegAsDefined = [&RegMask](MCRegister Reg) {
165 RegMask[Reg.id() / 32] &= ~(1u << Reg.id() % 32);
166 };
167
168 // Don't include $noreg in any regmasks.
169 SetRegAsDefined(MCRegister());
170
171 // Some targets can clobber registers "inside" a call, typically in
172 // linker-generated code.
173 for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(MF: &MF))
174 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
175 SetRegAsDefined(*AI);
176
177 // Scan all the physical registers. When a register is defined in the current
178 // function set it and all the aliasing registers as defined in the regmask.
179 // FIXME: Rewrite to use regunits.
180 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
181 // Don't count registers that are saved and restored.
182 if (SavedRegs.test(Idx: PReg))
183 continue;
184 // If a register is defined by an instruction mark it as defined together
185 // with all it's unsaved aliases.
186 if (!MRI->def_empty(RegNo: PReg)) {
187 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
188 if (!SavedRegs.test(Idx: (*AI).id()))
189 SetRegAsDefined(*AI);
190 continue;
191 }
192 // If a register is in the UsedPhysRegsMask set then mark it as defined.
193 // All clobbered aliases will also be in the set, so we can skip setting
194 // as defined all the aliases here.
195 if (UsedPhysRegsMask.test(Idx: PReg))
196 SetRegAsDefined(PReg);
197 }
198
199 if (TargetFrameLowering::isSafeForNoCSROpt(F) &&
200 MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) {
201 ++NumCSROpt;
202 LLVM_DEBUG(dbgs() << MF.getName()
203 << " function optimized for not having CSR.\n");
204 }
205
206 LLVM_DEBUG(
207 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
208 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
209 dbgs() << printReg(PReg, TRI) << " ";
210 }
211
212 dbgs() << " \n----------------------------------------\n";
213 );
214
215 PRUI.storeUpdateRegUsageInfo(FP: F, RegMask);
216
217 return false;
218}
219
220void RegUsageInfoCollector::
221computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
222 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
223 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
224
225 // Target will return the set of registers that it saves/restores as needed.
226 SavedRegs.clear();
227 TFI.getCalleeSaves(MF, SavedRegs);
228 if (SavedRegs.none())
229 return;
230
231 // Insert subregs.
232 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(MF: &MF);
233 for (unsigned i = 0; CSRegs[i]; ++i) {
234 MCPhysReg Reg = CSRegs[i];
235 if (SavedRegs.test(Idx: Reg)) {
236 // Save subregisters
237 for (MCPhysReg SR : TRI.subregs(Reg))
238 SavedRegs.set(SR);
239 }
240 }
241}
242