1//===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RegisterClassInfo class which provides dynamic
10// information about target register classes. Callee-saved vs. caller-saved and
11// reserved registers depend on calling conventions and other dynamic
12// information, so some things cannot be determined statically.
13//
14//===----------------------------------------------------------------------===//
15
16#include "llvm/CodeGen/RegisterClassInfo.h"
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetRegisterInfo.h"
23#include "llvm/CodeGen/TargetSubtargetInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/raw_ostream.h"
28#include <algorithm>
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "regalloc"
35
36static cl::opt<unsigned>
37StressRA("stress-regalloc", cl::Hidden, cl::init(Val: 0), cl::value_desc("N"),
38 cl::desc("Limit all regclasses to N registers"));
39
40RegisterClassInfo::RegisterClassInfo() = default;
41
42void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf,
43 bool Rev) {
44 bool Update = false;
45 MF = &mf;
46
47 auto &STI = MF->getSubtarget();
48
49 // Allocate new array the first time we see a new target.
50 if (STI.getRegisterInfo() != TRI || Reverse != Rev) {
51 Reverse = Rev;
52 TRI = STI.getRegisterInfo();
53 RegClass.reset(p: new RCInfo[TRI->getNumRegClasses()]);
54 Update = true;
55 }
56
57 // Test if CSRs have changed from the previous function.
58 const MachineRegisterInfo &MRI = MF->getRegInfo();
59 const MCPhysReg *CSR = MRI.getCalleeSavedRegs();
60 bool CSRChanged = true;
61 if (!Update) {
62 CSRChanged = false;
63 size_t LastSize = LastCalleeSavedRegs.size();
64 for (unsigned I = 0;; ++I) {
65 if (CSR[I] == 0) {
66 CSRChanged = I != LastSize;
67 break;
68 }
69 if (I >= LastSize) {
70 CSRChanged = true;
71 break;
72 }
73 if (CSR[I] != LastCalleeSavedRegs[I]) {
74 CSRChanged = true;
75 break;
76 }
77 }
78 }
79
80 // Get the callee saved registers.
81 if (CSRChanged) {
82 LastCalleeSavedRegs.clear();
83 // Build a CSRAlias map. Every CSR alias saves the last
84 // overlapping CSR.
85 CalleeSavedAliases.assign(NumElts: TRI->getNumRegUnits(), Elt: 0);
86 for (const MCPhysReg *I = CSR; *I; ++I) {
87 for (MCRegUnit U : TRI->regunits(Reg: *I))
88 CalleeSavedAliases[static_cast<unsigned>(U)] = *I;
89 LastCalleeSavedRegs.push_back(Elt: *I);
90 }
91
92 Update = true;
93 }
94
95 // Even if CSR list is same, we could have had a different allocation order
96 // if ignoreCSRForAllocationOrder is evaluated differently.
97 BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
98 for (const MCPhysReg *I = CSR; *I; ++I)
99 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
100 CSRHintsForAllocOrder[(*AI).id()] =
101 STI.ignoreCSRForAllocationOrder(MF: mf, PhysReg: *AI);
102 if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
103 Update = true;
104 IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
105 }
106
107 RegCosts = TRI->getRegisterCosts(MF: *MF);
108
109 // Different reserved registers?
110 const BitVector &RR = MF->getRegInfo().getReservedRegs();
111 if (RR != Reserved) {
112 Update = true;
113 Reserved = RR;
114 }
115
116 // Invalidate cached information from previous function.
117 if (Update) {
118 unsigned NumPSets = TRI->getNumRegPressureSets();
119 PSetLimits.reset(p: new unsigned[NumPSets]);
120 std::fill(first: &PSetLimits[0], last: &PSetLimits[NumPSets], value: 0);
121 ++Tag;
122 }
123}
124
125/// compute - Compute the preferred allocation order for RC with reserved
126/// registers filtered out. Volatile registers come first followed by CSR
127/// aliases ordered according to the CSR order specified by the target.
128void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
129 assert(RC && "no register class given");
130 RCInfo &RCI = RegClass[RC->getID()];
131 auto &STI = MF->getSubtarget();
132
133 // Raw register count, including all reserved regs.
134 unsigned NumRegs = RC->getNumRegs();
135
136 if (!RCI.Order)
137 RCI.Order.reset(p: new MCPhysReg[NumRegs]);
138
139 unsigned N = 0;
140 SmallVector<MCPhysReg, 16> CSRAlias;
141 uint8_t MinCost = uint8_t(~0u);
142 uint8_t LastCost = uint8_t(~0u);
143 unsigned LastCostChange = 0;
144
145 // FIXME: Once targets reserve registers instead of removing them from the
146 // allocation order, we can simply use begin/end here.
147 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(MF: *MF, Rev: Reverse);
148 for (unsigned PhysReg : reverse_conditionally(C&: RawOrder, ShouldReverse: Reverse)) {
149 // Remove reserved registers from the allocation order.
150 if (Reserved.test(Idx: PhysReg))
151 continue;
152 uint8_t Cost = RegCosts[PhysReg];
153 MinCost = std::min(a: MinCost, b: Cost);
154
155 if (getLastCalleeSavedAlias(PhysReg) &&
156 !STI.ignoreCSRForAllocationOrder(MF: *MF, PhysReg))
157 // PhysReg aliases a CSR, save it for later.
158 CSRAlias.push_back(Elt: PhysReg);
159 else {
160 if (Cost != LastCost)
161 LastCostChange = N;
162 RCI.Order[N++] = PhysReg;
163 LastCost = Cost;
164 }
165 }
166 RCI.NumRegs = N + CSRAlias.size();
167 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
168
169 // CSR aliases go after the volatile registers, preserve the target's order.
170 for (unsigned PhysReg : CSRAlias) {
171 uint8_t Cost = RegCosts[PhysReg];
172 if (Cost != LastCost)
173 LastCostChange = N;
174 RCI.Order[N++] = PhysReg;
175 LastCost = Cost;
176 }
177
178 // Register allocator stress test. Clip register class to N registers.
179 if (StressRA && RCI.NumRegs > StressRA)
180 RCI.NumRegs = StressRA;
181
182 // Check if RC is a proper sub-class.
183 if (const TargetRegisterClass *Super =
184 TRI->getLargestLegalSuperClass(RC, *MF))
185 if (Super != RC && getNumAllocatableRegs(RC: Super) > RCI.NumRegs)
186 RCI.ProperSubClass = true;
187
188 RCI.MinCost = MinCost;
189 RCI.LastCostChange = LastCostChange;
190
191 LLVM_DEBUG({
192 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
193 for (unsigned I = 0; I != RCI.NumRegs; ++I)
194 dbgs() << ' ' << printReg(RCI.Order[I], TRI);
195 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
196 });
197
198 // RCI is now up-to-date.
199 RCI.Tag = Tag;
200}
201
202/// This is not accurate because two overlapping register sets may have some
203/// nonoverlapping reserved registers. However, computing the allocation order
204/// for all register classes would be too expensive.
205unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
206 const TargetRegisterClass *RC = nullptr;
207 unsigned NumRCUnits = 0;
208 for (const TargetRegisterClass *C : TRI->regclasses()) {
209 const int *PSetID = TRI->getRegClassPressureSets(RC: C);
210 for (; *PSetID != -1; ++PSetID) {
211 if ((unsigned)*PSetID == Idx)
212 break;
213 }
214 if (*PSetID == -1)
215 continue;
216
217 // Found a register class that counts against this pressure set.
218 // For efficiency, only compute the set order for the largest set.
219 unsigned NUnits = TRI->getRegClassWeight(RC: C).WeightLimit;
220 if (!RC || NUnits > NumRCUnits) {
221 RC = C;
222 NumRCUnits = NUnits;
223 }
224 }
225 assert(RC && "Failed to find register class");
226 compute(RC);
227 unsigned NAllocatableRegs = getNumAllocatableRegs(RC);
228 unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(MF: *MF, Idx);
229 // If all the regs are reserved, return raw RegPressureSetLimit.
230 // One example is VRSAVERC in PowerPC.
231 // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit
232 // return non-zero value.
233 if (NAllocatableRegs == 0)
234 return RegPressureSetLimit;
235 unsigned NReserved = RC->getNumRegs() - NAllocatableRegs;
236 return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved;
237}
238