1//===- RegisterUsageInfo.cpp - Register Usage Information Storage ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This pass is required to take advantage of the interprocedural register
10/// allocation infrastructure.
11///
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/RegisterUsageInfo.h"
15#include "CodeGenOptions.h"
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/CodeGen/MachineOperand.h"
18#include "llvm/CodeGen/TargetRegisterInfo.h"
19#include "llvm/CodeGen/TargetSubtargetInfo.h"
20#include "llvm/IR/Analysis.h"
21#include "llvm/IR/Function.h"
22#include "llvm/IR/Module.h"
23#include "llvm/IR/PassManager.h"
24#include "llvm/InitializePasses.h"
25#include "llvm/Pass.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/Target/TargetMachine.h"
28#include <cstdint>
29#include <utility>
30#include <vector>
31
32using namespace llvm;
33
34INITIALIZE_PASS(PhysicalRegisterUsageInfoWrapperLegacy, "reg-usage-info",
35 "Register Usage Information Storage", false, true)
36
37char PhysicalRegisterUsageInfoWrapperLegacy::ID = 0;
38
39void PhysicalRegisterUsageInfo::setTargetMachine(const TargetMachine &TM) {
40 this->TM = &TM;
41}
42
43bool PhysicalRegisterUsageInfo::doInitialization(Module &M) {
44 RegMasks.reserve(NumEntries: M.size());
45 return false;
46}
47
48bool PhysicalRegisterUsageInfo::doFinalization(Module &M) {
49 if (CodeGenOptions::Global.print_regusage)
50 print(OS&: errs());
51
52 RegMasks.shrink_and_clear();
53 return false;
54}
55
56void PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo(
57 const Function &FP, ArrayRef<uint32_t> RegMask) {
58 RegMasks[&FP] = RegMask;
59}
60
61ArrayRef<uint32_t>
62PhysicalRegisterUsageInfo::getRegUsageInfo(const Function &FP) {
63 auto It = RegMasks.find(Val: &FP);
64 if (It != RegMasks.end())
65 return ArrayRef<uint32_t>(It->second);
66 return ArrayRef<uint32_t>();
67}
68
69void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
70 using FuncPtrRegMaskPair = decltype(RegMasks)::value_type;
71
72 // Create a vector of pointer to RegMasks entries
73 SmallVector<const FuncPtrRegMaskPair *, 64> FPRMPairVector(
74 llvm::make_pointer_range(Range: RegMasks));
75
76 // sort the vector to print analysis in alphabatic order of function name.
77 llvm::sort(
78 C&: FPRMPairVector,
79 Comp: [](const FuncPtrRegMaskPair *A, const FuncPtrRegMaskPair *B) -> bool {
80 return A->first->getName() < B->first->getName();
81 });
82
83 for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) {
84 OS << FPRMPair->first->getName() << " "
85 << "Clobbered Registers: ";
86 const TargetRegisterInfo *TRI
87 = TM->getSubtarget<TargetSubtargetInfo>(F: *(FPRMPair->first))
88 .getRegisterInfo();
89
90 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
91 if (MachineOperand::clobbersPhysReg(RegMask: &(FPRMPair->second[0]), PhysReg: PReg))
92 OS << printReg(Reg: PReg, TRI) << " ";
93 }
94 OS << "\n";
95 }
96}
97
98bool PhysicalRegisterUsageInfo::invalidate(
99 Module &M, const PreservedAnalyses &PA,
100 ModuleAnalysisManager::Invalidator &) {
101 auto PAC = PA.getChecker<PhysicalRegisterUsageAnalysis>();
102 return !PAC.preservedWhenStateless();
103}
104
105AnalysisKey PhysicalRegisterUsageAnalysis::Key;
106PhysicalRegisterUsageInfo
107PhysicalRegisterUsageAnalysis::run(Module &M, ModuleAnalysisManager &) {
108 PhysicalRegisterUsageInfo PRUI;
109 PRUI.doInitialization(M);
110 return PRUI;
111}
112
113PreservedAnalyses
114PhysicalRegisterUsageInfoPrinterPass::run(Module &M,
115 ModuleAnalysisManager &AM) {
116 auto *PRUI = &AM.getResult<PhysicalRegisterUsageAnalysis>(IR&: M);
117 PRUI->print(OS, M: &M);
118 return PreservedAnalyses::all();
119}
120