1//===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SelectionDAG::Legalize method.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/APFloat.h"
14#include "llvm/ADT/APInt.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/FloatingPointMode.h"
17#include "llvm/ADT/SetVector.h"
18#include "llvm/ADT/SmallPtrSet.h"
19#include "llvm/ADT/SmallSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/StringRef.h"
22#include "llvm/Analysis/ConstantFolding.h"
23#include "llvm/Analysis/TargetLibraryInfo.h"
24#include "llvm/CodeGen/ISDOpcodes.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineJumpTableInfo.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/RuntimeLibcallUtil.h"
30#include "llvm/CodeGen/SelectionDAG.h"
31#include "llvm/CodeGen/SelectionDAGNodes.h"
32#include "llvm/CodeGen/TargetFrameLowering.h"
33#include "llvm/CodeGen/TargetLowering.h"
34#include "llvm/CodeGen/TargetSubtargetInfo.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/CodeGenTypes/MachineValueType.h"
37#include "llvm/IR/CallingConv.h"
38#include "llvm/IR/Constants.h"
39#include "llvm/IR/DataLayout.h"
40#include "llvm/IR/DerivedTypes.h"
41#include "llvm/IR/Function.h"
42#include "llvm/IR/Metadata.h"
43#include "llvm/IR/Type.h"
44#include "llvm/Support/Casting.h"
45#include "llvm/Support/Compiler.h"
46#include "llvm/Support/Debug.h"
47#include "llvm/Support/ErrorHandling.h"
48#include "llvm/Support/MathExtras.h"
49#include "llvm/Support/raw_ostream.h"
50#include "llvm/Target/TargetMachine.h"
51#include "llvm/Target/TargetOptions.h"
52#include <cassert>
53#include <cstdint>
54#include <tuple>
55#include <utility>
56
57using namespace llvm;
58
59#define DEBUG_TYPE "legalizedag"
60
61namespace {
62
63/// Keeps track of state when getting the sign of a floating-point value as an
64/// integer.
65struct FloatSignAsInt {
66 EVT FloatVT;
67 SDValue Chain;
68 SDValue FloatPtr;
69 SDValue IntPtr;
70 MachinePointerInfo IntPointerInfo;
71 MachinePointerInfo FloatPointerInfo;
72 SDValue IntValue;
73 APInt SignMask;
74 uint8_t SignBit;
75};
76
77//===----------------------------------------------------------------------===//
78/// This takes an arbitrary SelectionDAG as input and
79/// hacks on it until the target machine can handle it. This involves
80/// eliminating value sizes the machine cannot handle (promoting small sizes to
81/// large sizes or splitting up large values into small values) as well as
82/// eliminating operations the machine cannot handle.
83///
84/// This code also does a small amount of optimization and recognition of idioms
85/// as part of its processing. For example, if a target does not support a
86/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
87/// will attempt merge setcc and brc instructions into brcc's.
88class SelectionDAGLegalize {
89 const TargetMachine &TM;
90 const TargetLowering &TLI;
91 SelectionDAG &DAG;
92
93 /// The set of nodes which have already been legalized. We hold a
94 /// reference to it in order to update as necessary on node deletion.
95 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
96
97 /// A set of all the nodes updated during legalization.
98 SmallSetVector<SDNode *, 16> *UpdatedNodes;
99
100 EVT getSetCCResultType(EVT VT) const {
101 return TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT);
102 }
103
104 // Libcall insertion helpers.
105
106public:
107 SelectionDAGLegalize(SelectionDAG &DAG,
108 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
109 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
110 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
111 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
112
113 /// Legalizes the given operation.
114 void LegalizeOp(SDNode *Node);
115
116private:
117 SDValue OptimizeFloatStore(StoreSDNode *ST);
118
119 void LegalizeLoadOps(SDNode *Node);
120 void LegalizeStoreOps(SDNode *Node);
121
122 SDValue ExpandINSERT_VECTOR_ELT(SDValue Op);
123
124 /// Return a vector shuffle operation which
125 /// performs the same shuffe in terms of order or result bytes, but on a type
126 /// whose vector element type is narrower than the original shuffle type.
127 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
128 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
129 SDValue N1, SDValue N2,
130 ArrayRef<int> Mask) const;
131
132 std::pair<SDValue, SDValue> ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
133 TargetLowering::ArgListTy &&Args,
134 bool IsSigned, EVT RetVT);
135 std::pair<SDValue, SDValue> ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
136
137 void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall LC,
138 SmallVectorImpl<SDValue> &Results);
139 void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
140 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
141 RTLIB::Libcall Call_F128,
142 RTLIB::Libcall Call_PPCF128,
143 SmallVectorImpl<SDValue> &Results);
144
145 void
146 ExpandFastFPLibCall(SDNode *Node, bool IsFast,
147 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_F32,
148 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_F64,
149 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_F80,
150 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_F128,
151 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_PPCF128,
152 SmallVectorImpl<SDValue> &Results);
153
154 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I8,
155 RTLIB::Libcall Call_I16, RTLIB::Libcall Call_I32,
156 RTLIB::Libcall Call_I64, RTLIB::Libcall Call_I128);
157 void ExpandArgFPLibCall(SDNode *Node,
158 RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
159 RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
160 RTLIB::Libcall Call_PPCF128,
161 SmallVectorImpl<SDValue> &Results);
162 SDValue ExpandBitCountingLibCall(SDNode *Node, RTLIB::Libcall CallI32,
163 RTLIB::Libcall CallI64,
164 RTLIB::Libcall CallI128);
165 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
166
167 SDValue ExpandSincosStretLibCall(SDNode *Node) const;
168
169 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
170 const SDLoc &dl);
171 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
172 const SDLoc &dl, SDValue ChainIn);
173 SDValue ExpandBUILD_VECTOR(SDNode *Node);
174 SDValue ExpandSPLAT_VECTOR(SDNode *Node);
175 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
176 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
177 SmallVectorImpl<SDValue> &Results);
178 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
179 SDValue Value) const;
180 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
181 SDValue NewIntValue) const;
182 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
183 SDValue ExpandFABS(SDNode *Node) const;
184 SDValue ExpandFNEG(SDNode *Node) const;
185 SDValue expandLdexp(SDNode *Node) const;
186 SDValue expandFrexp(SDNode *Node) const;
187 SDValue expandModf(SDNode *Node) const;
188
189 SDValue ExpandLegalINT_TO_FP(SDNode *Node, SDValue &Chain);
190 void PromoteLegalINT_TO_FP(SDNode *N, const SDLoc &dl,
191 SmallVectorImpl<SDValue> &Results);
192 void PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
193 SmallVectorImpl<SDValue> &Results);
194 SDValue PromoteLegalFP_TO_INT_SAT(SDNode *Node, const SDLoc &dl);
195
196 /// Implements vector reduce operation promotion.
197 ///
198 /// All vector operands are promoted to a vector type with larger element
199 /// type, and the start value is promoted to a larger scalar type. Then the
200 /// result is truncated back to the original scalar type.
201 SDValue PromoteReduction(SDNode *Node);
202
203 SDValue ExpandPARITY(SDValue Op, const SDLoc &dl);
204
205 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
206 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
207 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
208 SDValue ExpandConcatVectors(SDNode *Node);
209
210 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
211 SDValue ExpandConstant(ConstantSDNode *CP);
212
213 // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
214 bool ExpandNode(SDNode *Node);
215 void ConvertNodeToLibcall(SDNode *Node);
216 void PromoteNode(SDNode *Node);
217
218public:
219 // Node replacement helpers
220
221 void ReplacedNode(SDNode *N) {
222 LegalizedNodes.erase(Ptr: N);
223 if (UpdatedNodes)
224 UpdatedNodes->insert(X: N);
225 }
226
227 void ReplaceNode(SDNode *Old, SDNode *New) {
228 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
229 dbgs() << " with: "; New->dump(&DAG));
230
231 assert(Old->getNumValues() == New->getNumValues() &&
232 "Replacing one node with another that produces a different number "
233 "of values!");
234 DAG.ReplaceAllUsesWith(From: Old, To: New);
235 if (UpdatedNodes)
236 UpdatedNodes->insert(X: New);
237 ReplacedNode(N: Old);
238 }
239
240 void ReplaceNode(SDValue Old, SDValue New) {
241 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
242 dbgs() << " with: "; New->dump(&DAG));
243
244 DAG.ReplaceAllUsesWith(From: Old, To: New);
245 if (UpdatedNodes)
246 UpdatedNodes->insert(X: New.getNode());
247 ReplacedNode(N: Old.getNode());
248 }
249
250 void ReplaceNode(SDNode *Old, const SDValue *New) {
251 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
252
253 DAG.ReplaceAllUsesWith(From: Old, To: New);
254 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
255 LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
256 New[i]->dump(&DAG));
257 if (UpdatedNodes)
258 UpdatedNodes->insert(X: New[i].getNode());
259 }
260 ReplacedNode(N: Old);
261 }
262
263 void ReplaceNodeWithValue(SDValue Old, SDValue New) {
264 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
265 dbgs() << " with: "; New->dump(&DAG));
266
267 DAG.ReplaceAllUsesOfValueWith(From: Old, To: New);
268 if (UpdatedNodes)
269 UpdatedNodes->insert(X: New.getNode());
270 ReplacedNode(N: Old.getNode());
271 }
272};
273
274} // end anonymous namespace
275
276// Helper function that generates an MMO that considers the alignment of the
277// stack, and the size of the stack object
278static MachineMemOperand *getStackAlignedMMO(SDValue StackPtr,
279 MachineFunction &MF,
280 bool isObjectScalable) {
281 auto &MFI = MF.getFrameInfo();
282 int FI = cast<FrameIndexSDNode>(Val&: StackPtr)->getIndex();
283 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
284 LocationSize ObjectSize = isObjectScalable
285 ? LocationSize::beforeOrAfterPointer()
286 : LocationSize::precise(Value: MFI.getObjectSize(ObjectIdx: FI));
287 return MF.getMachineMemOperand(PtrInfo, F: MachineMemOperand::MOStore,
288 Size: ObjectSize, BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
289}
290
291/// Return a vector shuffle operation which
292/// performs the same shuffle in terms of order or result bytes, but on a type
293/// whose vector element type is narrower than the original shuffle type.
294/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
295SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
296 EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
297 ArrayRef<int> Mask) const {
298 unsigned NumMaskElts = VT.getVectorNumElements();
299 unsigned NumDestElts = NVT.getVectorNumElements();
300 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
301
302 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
303
304 if (NumEltsGrowth == 1)
305 return DAG.getVectorShuffle(VT: NVT, dl, N1, N2, Mask);
306
307 SmallVector<int, 8> NewMask;
308 for (unsigned i = 0; i != NumMaskElts; ++i) {
309 int Idx = Mask[i];
310 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
311 if (Idx < 0)
312 NewMask.push_back(Elt: -1);
313 else
314 NewMask.push_back(Elt: Idx * NumEltsGrowth + j);
315 }
316 }
317 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
318 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
319 return DAG.getVectorShuffle(VT: NVT, dl, N1, N2, Mask: NewMask);
320}
321
322/// Expands the ConstantFP node to an integer constant or
323/// a load from the constant pool.
324SDValue
325SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
326 bool Extend = false;
327 SDLoc dl(CFP);
328
329 // If a FP immediate is precise when represented as a float and if the
330 // target can do an extending load from float to double, we put it into
331 // the constant pool as a float, even if it's is statically typed as a
332 // double. This shrinks FP constants and canonicalizes them for targets where
333 // an FP extending load is the same cost as a normal load (such as on the x87
334 // fp stack or PPC FP unit).
335 EVT VT = CFP->getValueType(ResNo: 0);
336 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
337 if (!UseCP) {
338 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
339 return DAG.getConstant(Val: LLVMC->getValueAPF().bitcastToAPInt(), DL: dl,
340 VT: (VT == MVT::f64) ? MVT::i64 : MVT::i32);
341 }
342
343 APFloat APF = CFP->getValueAPF();
344 EVT OrigVT = VT;
345 EVT SVT = VT;
346
347 // We don't want to shrink SNaNs. Converting the SNaN back to its real type
348 // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
349 if (!APF.isSignaling()) {
350 while (SVT != MVT::f32 && SVT != MVT::f16 && SVT != MVT::bf16) {
351 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
352 if (ConstantFPSDNode::isValueValidForType(VT: SVT, Val: APF) &&
353 // Only do this if the target has a native EXTLOAD instruction from
354 // smaller type.
355 TLI.isLoadLegal(
356 ValVT: OrigVT, MemVT: SVT,
357 Alignment: Align(DAG.getDataLayout().getPrefTypeAlign(
358 Ty: SVT.getTypeForEVT(Context&: *DAG.getContext()))),
359 AddrSpace: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction())
360 .getAddrSpace(),
361 ExtType: ISD::EXTLOAD, Atomic: false) &&
362 TLI.ShouldShrinkFPConstant(OrigVT)) {
363 Type *SType = SVT.getTypeForEVT(Context&: *DAG.getContext());
364 LLVMC = cast<ConstantFP>(Val: ConstantFoldCastOperand(
365 Opcode: Instruction::FPTrunc, C: LLVMC, DestTy: SType, DL: DAG.getDataLayout()));
366 VT = SVT;
367 Extend = true;
368 }
369 }
370 }
371
372 SDValue CPIdx =
373 DAG.getConstantPool(C: LLVMC, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
374 Align Alignment = cast<ConstantPoolSDNode>(Val&: CPIdx)->getAlign();
375 if (Extend) {
376 SDValue Result = DAG.getExtLoad(
377 ExtType: ISD::EXTLOAD, dl, VT: OrigVT, Chain: DAG.getEntryNode(), Ptr: CPIdx,
378 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()), MemVT: VT,
379 Alignment);
380 return Result;
381 }
382 SDValue Result = DAG.getLoad(
383 VT: OrigVT, dl, Chain: DAG.getEntryNode(), Ptr: CPIdx,
384 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()), Alignment);
385 return Result;
386}
387
388/// Expands the Constant node to a load from the constant pool.
389SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
390 SDLoc dl(CP);
391 EVT VT = CP->getValueType(ResNo: 0);
392 SDValue CPIdx = DAG.getConstantPool(C: CP->getConstantIntValue(),
393 VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
394 Align Alignment = cast<ConstantPoolSDNode>(Val&: CPIdx)->getAlign();
395 SDValue Result = DAG.getLoad(
396 VT, dl, Chain: DAG.getEntryNode(), Ptr: CPIdx,
397 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()), Alignment);
398 return Result;
399}
400
401SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Op) {
402 SDValue Vec = Op.getOperand(i: 0);
403 SDValue Val = Op.getOperand(i: 1);
404 SDValue Idx = Op.getOperand(i: 2);
405 SDLoc dl(Op);
406
407 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Val&: Idx)) {
408 // SCALAR_TO_VECTOR requires that the type of the value being inserted
409 // match the element type of the vector being created, except for
410 // integers in which case the inserted value can be over width.
411 EVT EltVT = Vec.getValueType().getVectorElementType();
412 if (Val.getValueType() == EltVT ||
413 (EltVT.isInteger() && Val.getValueType().bitsGE(VT: EltVT))) {
414 SDValue ScVec = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl,
415 VT: Vec.getValueType(), Operand: Val);
416
417 unsigned NumElts = Vec.getValueType().getVectorNumElements();
418 // We generate a shuffle of InVec and ScVec, so the shuffle mask
419 // should be 0,1,2,3,4,5... with the appropriate element replaced with
420 // elt 0 of the RHS.
421 SmallVector<int, 8> ShufOps;
422 for (unsigned i = 0; i != NumElts; ++i)
423 ShufOps.push_back(Elt: i != InsertPos->getZExtValue() ? i : NumElts);
424
425 return DAG.getVectorShuffle(VT: Vec.getValueType(), dl, N1: Vec, N2: ScVec, Mask: ShufOps);
426 }
427 }
428 return ExpandInsertToVectorThroughStack(Op);
429}
430
431SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
432 if (!ISD::isNormalStore(N: ST))
433 return SDValue();
434
435 LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
436 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
437 // FIXME: move this to the DAG Combiner! Note that we can't regress due
438 // to phase ordering between legalized code and the dag combiner. This
439 // probably means that we need to integrate dag combiner and legalizer
440 // together.
441 // We generally can't do this one for long doubles.
442 SDValue Chain = ST->getChain();
443 SDValue Ptr = ST->getBasePtr();
444 SDValue Value = ST->getValue();
445 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
446 AAMDNodes AAInfo = ST->getAAInfo();
447 SDLoc dl(ST);
448
449 // Don't optimise TargetConstantFP
450 if (Value.getOpcode() == ISD::TargetConstantFP)
451 return SDValue();
452
453 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Val&: Value)) {
454 if (CFP->getValueType(ResNo: 0) == MVT::f32 &&
455 TLI.isTypeLegal(VT: MVT::i32)) {
456 SDValue Con = DAG.getConstant(Val: CFP->getValueAPF().
457 bitcastToAPInt().zextOrTrunc(width: 32),
458 DL: SDLoc(CFP), VT: MVT::i32);
459 return DAG.getStore(Chain, dl, Val: Con, Ptr, PtrInfo: ST->getPointerInfo(),
460 Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
461 }
462
463 if (CFP->getValueType(ResNo: 0) == MVT::f64 &&
464 !TLI.isFPImmLegal(CFP->getValueAPF(), MVT::f64)) {
465 // If this target supports 64-bit registers, do a single 64-bit store.
466 if (TLI.isTypeLegal(VT: MVT::i64)) {
467 SDValue Con = DAG.getConstant(Val: CFP->getValueAPF().bitcastToAPInt().
468 zextOrTrunc(width: 64), DL: SDLoc(CFP), VT: MVT::i64);
469 return DAG.getStore(Chain, dl, Val: Con, Ptr, PtrInfo: ST->getPointerInfo(),
470 Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
471 }
472
473 if (TLI.isTypeLegal(VT: MVT::i32) && !ST->isVolatile()) {
474 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
475 // stores. If the target supports neither 32- nor 64-bits, this
476 // xform is certainly not worth it.
477 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
478 SDValue Lo = DAG.getConstant(Val: IntVal.trunc(width: 32), DL: dl, VT: MVT::i32);
479 SDValue Hi = DAG.getConstant(Val: IntVal.lshr(shiftAmt: 32).trunc(width: 32), DL: dl, VT: MVT::i32);
480 if (DAG.getDataLayout().isBigEndian())
481 std::swap(a&: Lo, b&: Hi);
482
483 Lo = DAG.getStore(Chain, dl, Val: Lo, Ptr, PtrInfo: ST->getPointerInfo(),
484 Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
485 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: 4), DL: dl);
486 Hi = DAG.getStore(Chain, dl, Val: Hi, Ptr,
487 PtrInfo: ST->getPointerInfo().getWithOffset(O: 4),
488 Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
489
490 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
491 }
492 }
493 }
494 return SDValue();
495}
496
497void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
498 StoreSDNode *ST = cast<StoreSDNode>(Val: Node);
499 SDValue Chain = ST->getChain();
500 SDValue Ptr = ST->getBasePtr();
501 SDLoc dl(Node);
502
503 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
504 AAMDNodes AAInfo = ST->getAAInfo();
505
506 if (!ST->isTruncatingStore()) {
507 LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
508 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
509 ReplaceNode(Old: ST, New: OptStore);
510 return;
511 }
512
513 SDValue Value = ST->getValue();
514 MVT VT = Value.getSimpleValueType();
515 switch (TLI.getOperationAction(Op: ISD::STORE, VT)) {
516 default: llvm_unreachable("This action is not supported yet!");
517 case TargetLowering::Legal: {
518 // If this is an unaligned store and the target doesn't support it,
519 // expand it.
520 EVT MemVT = ST->getMemoryVT();
521 const DataLayout &DL = DAG.getDataLayout();
522 if (!TLI.allowsMemoryAccessForAlignment(Context&: *DAG.getContext(), DL, VT: MemVT,
523 MMO: *ST->getMemOperand())) {
524 LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
525 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
526 ReplaceNode(Old: SDValue(ST, 0), New: Result);
527 } else
528 LLVM_DEBUG(dbgs() << "Legal store\n");
529 break;
530 }
531 case TargetLowering::Custom: {
532 LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
533 SDValue Res = TLI.LowerOperation(Op: SDValue(Node, 0), DAG);
534 if (Res && Res != SDValue(Node, 0))
535 ReplaceNode(Old: SDValue(Node, 0), New: Res);
536 return;
537 }
538 case TargetLowering::Promote: {
539 MVT NVT = TLI.getTypeToPromoteTo(Op: ISD::STORE, VT);
540 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
541 "Can only promote stores to same size type");
542 Value = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NVT, Operand: Value);
543 SDValue Result = DAG.getStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(),
544 Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
545 ReplaceNode(Old: SDValue(Node, 0), New: Result);
546 break;
547 }
548 }
549 return;
550 }
551
552 LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
553 SDValue Value = ST->getValue();
554 EVT StVT = ST->getMemoryVT();
555 TypeSize StWidth = StVT.getSizeInBits();
556 TypeSize StSize = StVT.getStoreSizeInBits();
557 auto &DL = DAG.getDataLayout();
558
559 if (StWidth != StSize) {
560 // Promote to a byte-sized store with upper bits zero if not
561 // storing an integral number of bytes. For example, promote
562 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
563 EVT NVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StSize.getFixedValue());
564 Value = DAG.getZeroExtendInReg(Op: Value, DL: dl, VT: StVT);
565 SDValue Result =
566 DAG.getTruncStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(), SVT: NVT,
567 Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
568 ReplaceNode(Old: SDValue(Node, 0), New: Result);
569 } else if (!StVT.isVector() && !isPowerOf2_64(Value: StWidth.getFixedValue())) {
570 // If not storing a power-of-2 number of bits, expand as two stores.
571 assert(!StVT.isVector() && "Unsupported truncstore!");
572 unsigned StWidthBits = StWidth.getFixedValue();
573 unsigned LogStWidth = Log2_32(Value: StWidthBits);
574 assert(LogStWidth < 32);
575 unsigned RoundWidth = 1 << LogStWidth;
576 assert(RoundWidth < StWidthBits);
577 unsigned ExtraWidth = StWidthBits - RoundWidth;
578 assert(ExtraWidth < RoundWidth);
579 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
580 "Store size not an integral number of bytes!");
581 EVT RoundVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RoundWidth);
582 EVT ExtraVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExtraWidth);
583 SDValue Lo, Hi;
584 unsigned IncrementSize;
585
586 if (DL.isLittleEndian()) {
587 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
588 // Store the bottom RoundWidth bits.
589 Lo = DAG.getTruncStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(),
590 SVT: RoundVT, Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
591
592 // Store the remaining ExtraWidth bits.
593 IncrementSize = RoundWidth / 8;
594 Ptr =
595 DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
596 Hi = DAG.getNode(
597 Opcode: ISD::SRL, DL: dl, VT: Value.getValueType(), N1: Value,
598 N2: DAG.getShiftAmountConstant(Val: RoundWidth, VT: Value.getValueType(), DL: dl));
599 Hi = DAG.getTruncStore(Chain, dl, Val: Hi, Ptr,
600 PtrInfo: ST->getPointerInfo().getWithOffset(O: IncrementSize),
601 SVT: ExtraVT, Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
602 } else {
603 // Big endian - avoid unaligned stores.
604 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
605 // Store the top RoundWidth bits.
606 Hi = DAG.getNode(
607 Opcode: ISD::SRL, DL: dl, VT: Value.getValueType(), N1: Value,
608 N2: DAG.getShiftAmountConstant(Val: ExtraWidth, VT: Value.getValueType(), DL: dl));
609 Hi = DAG.getTruncStore(Chain, dl, Val: Hi, Ptr, PtrInfo: ST->getPointerInfo(), SVT: RoundVT,
610 Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
611
612 // Store the remaining ExtraWidth bits.
613 IncrementSize = RoundWidth / 8;
614 Ptr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: Ptr.getValueType(), N1: Ptr,
615 N2: DAG.getConstant(Val: IncrementSize, DL: dl,
616 VT: Ptr.getValueType()));
617 Lo = DAG.getTruncStore(Chain, dl, Val: Value, Ptr,
618 PtrInfo: ST->getPointerInfo().getWithOffset(O: IncrementSize),
619 SVT: ExtraVT, Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
620 }
621
622 // The order of the stores doesn't matter.
623 SDValue Result = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
624 ReplaceNode(Old: SDValue(Node, 0), New: Result);
625 } else {
626 switch (TLI.getTruncStoreAction(ValVT: ST->getValue().getValueType(), MemVT: StVT,
627 Alignment: ST->getAlign(), AddrSpace: ST->getAddressSpace())) {
628 default:
629 llvm_unreachable("This action is not supported yet!");
630 case TargetLowering::Legal: {
631 EVT MemVT = ST->getMemoryVT();
632 // If this is an unaligned store and the target doesn't support it,
633 // expand it.
634 if (!TLI.allowsMemoryAccessForAlignment(Context&: *DAG.getContext(), DL, VT: MemVT,
635 MMO: *ST->getMemOperand())) {
636 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
637 ReplaceNode(Old: SDValue(ST, 0), New: Result);
638 }
639 break;
640 }
641 case TargetLowering::Custom: {
642 SDValue Res = TLI.LowerOperation(Op: SDValue(Node, 0), DAG);
643 if (Res && Res != SDValue(Node, 0))
644 ReplaceNode(Old: SDValue(Node, 0), New: Res);
645 return;
646 }
647 case TargetLowering::Expand:
648 assert(!StVT.isVector() &&
649 "Vector Stores are handled in LegalizeVectorOps");
650
651 SDValue Result;
652
653 // TRUNCSTORE:i16 i32 -> STORE i16
654 if (TLI.isTypeLegal(VT: StVT)) {
655 Value = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: StVT, Operand: Value);
656 Result = DAG.getStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(),
657 Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
658 } else {
659 // The in-memory type isn't legal. Truncate to the type it would promote
660 // to, and then do a truncstore.
661 Value = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl,
662 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: StVT),
663 Operand: Value);
664 Result = DAG.getTruncStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(),
665 SVT: StVT, Alignment: ST->getBaseAlign(), MMOFlags, AAInfo);
666 }
667
668 ReplaceNode(Old: SDValue(Node, 0), New: Result);
669 break;
670 }
671 }
672}
673
674void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
675 LoadSDNode *LD = cast<LoadSDNode>(Val: Node);
676 SDValue Chain = LD->getChain(); // The chain.
677 SDValue Ptr = LD->getBasePtr(); // The base pointer.
678 SDValue Value; // The value returned by the load op.
679 SDLoc dl(Node);
680
681 ISD::LoadExtType ExtType = LD->getExtensionType();
682 if (ExtType == ISD::NON_EXTLOAD) {
683 LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
684 MVT VT = Node->getSimpleValueType(ResNo: 0);
685 SDValue RVal = SDValue(Node, 0);
686 SDValue RChain = SDValue(Node, 1);
687
688 switch (TLI.getOperationAction(Op: Node->getOpcode(), VT)) {
689 default: llvm_unreachable("This action is not supported yet!");
690 case TargetLowering::Legal: {
691 EVT MemVT = LD->getMemoryVT();
692 const DataLayout &DL = DAG.getDataLayout();
693 // If this is an unaligned load and the target doesn't support it,
694 // expand it.
695 if (!TLI.allowsMemoryAccessForAlignment(Context&: *DAG.getContext(), DL, VT: MemVT,
696 MMO: *LD->getMemOperand())) {
697 std::tie(args&: RVal, args&: RChain) = TLI.expandUnalignedLoad(LD, DAG);
698 }
699 break;
700 }
701 case TargetLowering::Custom:
702 if (SDValue Res = TLI.LowerOperation(Op: RVal, DAG)) {
703 RVal = Res;
704 RChain = Res.getValue(R: 1);
705 }
706 break;
707
708 case TargetLowering::Promote: {
709 MVT NVT = TLI.getTypeToPromoteTo(Op: Node->getOpcode(), VT);
710 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
711 "Can only promote loads to same size type");
712
713 // If the range metadata type does not match the legalized memory
714 // operation type, remove the range metadata.
715 if (const MDNode *MD = LD->getRanges()) {
716 ConstantInt *Lower = mdconst::extract<ConstantInt>(MD: MD->getOperand(I: 0));
717 if (Lower->getBitWidth() != NVT.getScalarSizeInBits() ||
718 !NVT.isInteger())
719 LD->getMemOperand()->clearRanges();
720 }
721 SDValue Res = DAG.getLoad(VT: NVT, dl, Chain, Ptr, MMO: LD->getMemOperand());
722 RVal = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Res);
723 RChain = Res.getValue(R: 1);
724 break;
725 }
726 }
727 if (RChain.getNode() != Node) {
728 assert(RVal.getNode() != Node && "Load must be completely replaced");
729 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 0), To: RVal);
730 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 1), To: RChain);
731 if (UpdatedNodes) {
732 UpdatedNodes->insert(X: RVal.getNode());
733 UpdatedNodes->insert(X: RChain.getNode());
734 }
735 ReplacedNode(N: Node);
736 }
737 return;
738 }
739
740 LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
741 EVT SrcVT = LD->getMemoryVT();
742 TypeSize SrcWidth = SrcVT.getSizeInBits();
743 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
744 AAMDNodes AAInfo = LD->getAAInfo();
745
746 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
747 // Some targets pretend to have an i1 loading operation, and actually
748 // load an i8. This trick is correct for ZEXTLOAD because the top 7
749 // bits are guaranteed to be zero; it helps the optimizers understand
750 // that these bits are zero. It is also useful for EXTLOAD, since it
751 // tells the optimizers that those bits are undefined. It would be
752 // nice to have an effective generic way of getting these benefits...
753 // Until such a way is found, don't insist on promoting i1 here.
754 (SrcVT != MVT::i1 ||
755 TLI.getLoadAction(ValVT: Node->getValueType(ResNo: 0), MemVT: MVT::i1, Alignment: LD->getAlign(),
756 AddrSpace: LD->getAddressSpace(), ExtType,
757 Atomic: false) == TargetLowering::Promote)) {
758 // Promote to a byte-sized load if not loading an integral number of
759 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
760 unsigned NewWidth = SrcVT.getStoreSizeInBits();
761 EVT NVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NewWidth);
762 SDValue Ch;
763
764 // The extra bits are guaranteed to be zero, since we stored them that
765 // way. A zext load from NVT thus automatically gives zext from SrcVT.
766
767 ISD::LoadExtType NewExtType =
768 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
769
770 SDValue Result = DAG.getExtLoad(ExtType: NewExtType, dl, VT: Node->getValueType(ResNo: 0),
771 Chain, Ptr, PtrInfo: LD->getPointerInfo(), MemVT: NVT,
772 Alignment: LD->getBaseAlign(), MMOFlags, AAInfo);
773
774 Ch = Result.getValue(R: 1); // The chain.
775
776 if (ExtType == ISD::SEXTLOAD)
777 // Having the top bits zero doesn't help when sign extending.
778 Result = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl,
779 VT: Result.getValueType(),
780 N1: Result, N2: DAG.getValueType(SrcVT));
781 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
782 // All the top bits are guaranteed to be zero - inform the optimizers.
783 Result = DAG.getNode(Opcode: ISD::AssertZext, DL: dl,
784 VT: Result.getValueType(), N1: Result,
785 N2: DAG.getValueType(SrcVT));
786
787 Value = Result;
788 Chain = Ch;
789 } else if (!isPowerOf2_64(Value: SrcWidth.getKnownMinValue())) {
790 // If not loading a power-of-2 number of bits, expand as two loads.
791 assert(!SrcVT.isVector() && "Unsupported extload!");
792 unsigned SrcWidthBits = SrcWidth.getFixedValue();
793 unsigned LogSrcWidth = Log2_32(Value: SrcWidthBits);
794 assert(LogSrcWidth < 32);
795 unsigned RoundWidth = 1 << LogSrcWidth;
796 assert(RoundWidth < SrcWidthBits);
797 unsigned ExtraWidth = SrcWidthBits - RoundWidth;
798 assert(ExtraWidth < RoundWidth);
799 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
800 "Load size not an integral number of bytes!");
801 EVT RoundVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RoundWidth);
802 EVT ExtraVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExtraWidth);
803 SDValue Lo, Hi, Ch;
804 unsigned IncrementSize;
805 auto &DL = DAG.getDataLayout();
806
807 if (DL.isLittleEndian()) {
808 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
809 // Load the bottom RoundWidth bits.
810 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: Node->getValueType(ResNo: 0), Chain, Ptr,
811 PtrInfo: LD->getPointerInfo(), MemVT: RoundVT, Alignment: LD->getBaseAlign(),
812 MMOFlags, AAInfo);
813
814 // Load the remaining ExtraWidth bits.
815 IncrementSize = RoundWidth / 8;
816 Ptr =
817 DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
818 Hi = DAG.getExtLoad(ExtType, dl, VT: Node->getValueType(ResNo: 0), Chain, Ptr,
819 PtrInfo: LD->getPointerInfo().getWithOffset(O: IncrementSize),
820 MemVT: ExtraVT, Alignment: LD->getBaseAlign(), MMOFlags, AAInfo);
821
822 // Build a factor node to remember that this load is independent of
823 // the other one.
824 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
825 N2: Hi.getValue(R: 1));
826
827 // Move the top bits to the right place.
828 Hi = DAG.getNode(
829 Opcode: ISD::SHL, DL: dl, VT: Hi.getValueType(), N1: Hi,
830 N2: DAG.getShiftAmountConstant(Val: RoundWidth, VT: Hi.getValueType(), DL: dl));
831
832 // Join the hi and lo parts.
833 Value = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Lo, N2: Hi);
834 } else {
835 // Big endian - avoid unaligned loads.
836 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
837 // Load the top RoundWidth bits.
838 Hi = DAG.getExtLoad(ExtType, dl, VT: Node->getValueType(ResNo: 0), Chain, Ptr,
839 PtrInfo: LD->getPointerInfo(), MemVT: RoundVT, Alignment: LD->getBaseAlign(),
840 MMOFlags, AAInfo);
841
842 // Load the remaining ExtraWidth bits.
843 IncrementSize = RoundWidth / 8;
844 Ptr =
845 DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
846 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: Node->getValueType(ResNo: 0), Chain, Ptr,
847 PtrInfo: LD->getPointerInfo().getWithOffset(O: IncrementSize),
848 MemVT: ExtraVT, Alignment: LD->getBaseAlign(), MMOFlags, AAInfo);
849
850 // Build a factor node to remember that this load is independent of
851 // the other one.
852 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
853 N2: Hi.getValue(R: 1));
854
855 // Move the top bits to the right place.
856 Hi = DAG.getNode(
857 Opcode: ISD::SHL, DL: dl, VT: Hi.getValueType(), N1: Hi,
858 N2: DAG.getShiftAmountConstant(Val: ExtraWidth, VT: Hi.getValueType(), DL: dl));
859
860 // Join the hi and lo parts.
861 Value = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Lo, N2: Hi);
862 }
863
864 Chain = Ch;
865 } else {
866 bool isCustom = false;
867 switch (TLI.getLoadAction(ValVT: Node->getValueType(ResNo: 0), MemVT: SrcVT.getSimpleVT(),
868 Alignment: LD->getAlign(), AddrSpace: LD->getAddressSpace(), ExtType,
869 Atomic: false)) {
870 default:
871 llvm_unreachable("This action is not supported yet!");
872 case TargetLowering::Custom:
873 isCustom = true;
874 [[fallthrough]];
875 case TargetLowering::Legal:
876 Value = SDValue(Node, 0);
877 Chain = SDValue(Node, 1);
878
879 if (isCustom) {
880 if (SDValue Res = TLI.LowerOperation(Op: SDValue(Node, 0), DAG)) {
881 Value = Res;
882 Chain = Res.getValue(R: 1);
883 }
884 } else {
885 // If this is an unaligned load and the target doesn't support it,
886 // expand it.
887 EVT MemVT = LD->getMemoryVT();
888 const DataLayout &DL = DAG.getDataLayout();
889 if (!TLI.allowsMemoryAccess(Context&: *DAG.getContext(), DL, VT: MemVT,
890 MMO: *LD->getMemOperand())) {
891 std::tie(args&: Value, args&: Chain) = TLI.expandUnalignedLoad(LD, DAG);
892 }
893 }
894 break;
895
896 case TargetLowering::Expand: {
897 EVT DestVT = Node->getValueType(ResNo: 0);
898 if (!TLI.isLoadLegal(ValVT: DestVT, MemVT: SrcVT, Alignment: LD->getAlign(), AddrSpace: LD->getAddressSpace(),
899 ExtType: ISD::EXTLOAD, Atomic: false)) {
900 // If the source type is not legal, see if there is a legal extload to
901 // an intermediate type that we can then extend further.
902 EVT LoadVT = TLI.getRegisterType(VT: SrcVT.getSimpleVT());
903 if ((LoadVT.isFloatingPoint() == SrcVT.isFloatingPoint()) &&
904 (TLI.isTypeLegal(VT: SrcVT) || // Same as SrcVT == LoadVT?
905 TLI.isLoadLegal(ValVT: LoadVT, MemVT: SrcVT, Alignment: LD->getAlign(),
906 AddrSpace: LD->getAddressSpace(), ExtType, Atomic: false))) {
907 // If we are loading a legal type, this is a non-extload followed by a
908 // full extend.
909 ISD::LoadExtType MidExtType =
910 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
911
912 SDValue Load = DAG.getExtLoad(ExtType: MidExtType, dl, VT: LoadVT, Chain, Ptr,
913 MemVT: SrcVT, MMO: LD->getMemOperand());
914 unsigned ExtendOp =
915 ISD::getExtForLoadExtType(IsFP: SrcVT.isFloatingPoint(), ExtType);
916 Value = DAG.getNode(Opcode: ExtendOp, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Load);
917 Chain = Load.getValue(R: 1);
918 break;
919 }
920
921 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
922 // normal undefined upper bits behavior to allow using an in-reg extend
923 // with the illegal FP type, so load as an integer and do the
924 // from-integer conversion.
925 EVT SVT = SrcVT.getScalarType();
926 if (SVT == MVT::f16 || SVT == MVT::bf16) {
927 EVT ISrcVT = SrcVT.changeTypeToInteger();
928 EVT IDestVT = DestVT.changeTypeToInteger();
929 EVT ILoadVT = TLI.getRegisterType(VT: IDestVT.getSimpleVT());
930
931 SDValue Result = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: ILoadVT, Chain,
932 Ptr, MemVT: ISrcVT, MMO: LD->getMemOperand());
933 Value =
934 DAG.getNode(Opcode: SVT == MVT::f16 ? ISD::FP16_TO_FP : ISD::BF16_TO_FP,
935 DL: dl, VT: DestVT, Operand: Result);
936 Chain = Result.getValue(R: 1);
937 break;
938 }
939 }
940
941 assert(!SrcVT.isVector() &&
942 "Vector Loads are handled in LegalizeVectorOps");
943
944 // FIXME: This does not work for vectors on most targets. Sign-
945 // and zero-extend operations are currently folded into extending
946 // loads, whether they are legal or not, and then we end up here
947 // without any support for legalizing them.
948 assert(ExtType != ISD::EXTLOAD &&
949 "EXTLOAD should always be supported!");
950 // Turn the unsupported load into an EXTLOAD followed by an
951 // explicit zero/sign extend inreg.
952 SDValue Result = DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl,
953 VT: Node->getValueType(ResNo: 0),
954 Chain, Ptr, MemVT: SrcVT,
955 MMO: LD->getMemOperand());
956 SDValue ValRes;
957 if (ExtType == ISD::SEXTLOAD)
958 ValRes = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl,
959 VT: Result.getValueType(),
960 N1: Result, N2: DAG.getValueType(SrcVT));
961 else
962 ValRes = DAG.getZeroExtendInReg(Op: Result, DL: dl, VT: SrcVT);
963 Value = ValRes;
964 Chain = Result.getValue(R: 1);
965 break;
966 }
967 }
968 }
969
970 // Since loads produce two values, make sure to remember that we legalized
971 // both of them.
972 if (Chain.getNode() != Node) {
973 assert(Value.getNode() != Node && "Load must be completely replaced");
974 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 0), To: Value);
975 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 1), To: Chain);
976 if (UpdatedNodes) {
977 UpdatedNodes->insert(X: Value.getNode());
978 UpdatedNodes->insert(X: Chain.getNode());
979 }
980 ReplacedNode(N: Node);
981 }
982}
983
984/// Return a legal replacement for the given operation, with all legal operands.
985void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
986 LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
987
988 // Allow illegal target nodes and illegal registers.
989 if (Node->getOpcode() == ISD::TargetConstant ||
990 Node->getOpcode() == ISD::Register)
991 return;
992
993#ifndef NDEBUG
994 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
995 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
996 TargetLowering::TypeLegal &&
997 "Unexpected illegal type!");
998
999 for (const SDValue &Op : Node->op_values())
1000 assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
1001 TargetLowering::TypeLegal ||
1002 Op.getOpcode() == ISD::TargetConstant ||
1003 Op.getOpcode() == ISD::Register) &&
1004 "Unexpected illegal type!");
1005#endif
1006
1007 // Figure out the correct action; the way to query this varies by opcode
1008 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1009 bool SimpleFinishLegalizing = true;
1010 switch (Node->getOpcode()) {
1011 case ISD::POISON: {
1012 // TODO: Currently, POISON is being lowered to UNDEF here. However, there is
1013 // an open concern that this transformation may not be ideal, as targets
1014 // should ideally handle POISON directly. Changing this behavior would
1015 // require adding support for POISON in TableGen, which is a large change.
1016 // Additionally, many existing test cases rely on the current behavior
1017 // (e.g., llvm/test/CodeGen/PowerPC/vec_shuffle.ll). A broader discussion
1018 // and incremental changes might be needed to properly support POISON
1019 // without breaking existing targets and tests.
1020 SDValue UndefNode = DAG.getUNDEF(VT: Node->getValueType(ResNo: 0));
1021 ReplaceNode(Old: Node, New: UndefNode.getNode());
1022 return;
1023 }
1024 case ISD::INTRINSIC_W_CHAIN:
1025 case ISD::INTRINSIC_WO_CHAIN:
1026 case ISD::INTRINSIC_VOID:
1027 case ISD::STACKSAVE:
1028 case ISD::STACKADDRESS:
1029 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: MVT::Other);
1030 break;
1031 case ISD::GET_DYNAMIC_AREA_OFFSET:
1032 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1033 VT: Node->getValueType(ResNo: 0));
1034 break;
1035 case ISD::VAARG:
1036 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1037 VT: Node->getValueType(ResNo: 0));
1038 if (Action != TargetLowering::Promote)
1039 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: MVT::Other);
1040 break;
1041 case ISD::SET_FPENV:
1042 case ISD::SET_FPMODE:
1043 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1044 VT: Node->getOperand(Num: 1).getValueType());
1045 break;
1046 case ISD::FP_TO_FP16:
1047 case ISD::FP_TO_BF16:
1048 case ISD::SINT_TO_FP:
1049 case ISD::UINT_TO_FP:
1050 case ISD::EXTRACT_VECTOR_ELT:
1051 case ISD::LROUND:
1052 case ISD::LLROUND:
1053 case ISD::LRINT:
1054 case ISD::LLRINT:
1055 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1056 VT: Node->getOperand(Num: 0).getValueType());
1057 break;
1058 case ISD::STRICT_FP_TO_FP16:
1059 case ISD::STRICT_FP_TO_BF16:
1060 case ISD::STRICT_SINT_TO_FP:
1061 case ISD::STRICT_UINT_TO_FP:
1062 case ISD::STRICT_LRINT:
1063 case ISD::STRICT_LLRINT:
1064 case ISD::STRICT_LROUND:
1065 case ISD::STRICT_LLROUND:
1066 // These pseudo-ops are the same as the other STRICT_ ops except
1067 // they are registered with setOperationAction() using the input type
1068 // instead of the output type.
1069 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1070 VT: Node->getOperand(Num: 1).getValueType());
1071 break;
1072 case ISD::SIGN_EXTEND_INREG: {
1073 EVT InnerType = cast<VTSDNode>(Val: Node->getOperand(Num: 1))->getVT();
1074 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: InnerType);
1075 break;
1076 }
1077 case ISD::ATOMIC_STORE:
1078 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1079 VT: Node->getOperand(Num: 1).getValueType());
1080 break;
1081 case ISD::SELECT_CC:
1082 case ISD::STRICT_FSETCC:
1083 case ISD::STRICT_FSETCCS:
1084 case ISD::SETCC:
1085 case ISD::SETCCCARRY:
1086 case ISD::VP_SETCC:
1087 case ISD::BR_CC: {
1088 unsigned Opc = Node->getOpcode();
1089 unsigned CCOperand = Opc == ISD::SELECT_CC ? 4
1090 : Opc == ISD::STRICT_FSETCC ? 3
1091 : Opc == ISD::STRICT_FSETCCS ? 3
1092 : Opc == ISD::SETCCCARRY ? 3
1093 : (Opc == ISD::SETCC || Opc == ISD::VP_SETCC) ? 2
1094 : 1;
1095 unsigned CompareOperand = Opc == ISD::BR_CC ? 2
1096 : Opc == ISD::STRICT_FSETCC ? 1
1097 : Opc == ISD::STRICT_FSETCCS ? 1
1098 : 0;
1099 MVT OpVT = Node->getOperand(Num: CompareOperand).getSimpleValueType();
1100 ISD::CondCode CCCode =
1101 cast<CondCodeSDNode>(Val: Node->getOperand(Num: CCOperand))->get();
1102 Action = TLI.getCondCodeAction(CC: CCCode, VT: OpVT);
1103 if (Action == TargetLowering::Legal) {
1104 if (Node->getOpcode() == ISD::SELECT_CC)
1105 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1106 VT: Node->getValueType(ResNo: 0));
1107 else
1108 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: OpVT);
1109 }
1110 break;
1111 }
1112 case ISD::LOAD:
1113 case ISD::STORE:
1114 // FIXME: Model these properly. LOAD and STORE are complicated, and
1115 // STORE expects the unlegalized operand in some cases.
1116 SimpleFinishLegalizing = false;
1117 break;
1118 case ISD::CALLSEQ_START:
1119 case ISD::CALLSEQ_END:
1120 // FIXME: This shouldn't be necessary. These nodes have special properties
1121 // dealing with the recursive nature of legalization. Removing this
1122 // special case should be done as part of making LegalizeDAG non-recursive.
1123 SimpleFinishLegalizing = false;
1124 break;
1125 case ISD::EXTRACT_ELEMENT:
1126 case ISD::GET_ROUNDING:
1127 case ISD::MERGE_VALUES:
1128 case ISD::EH_RETURN:
1129 case ISD::FRAME_TO_ARGS_OFFSET:
1130 case ISD::EH_DWARF_CFA:
1131 case ISD::EH_SJLJ_SETJMP:
1132 case ISD::EH_SJLJ_LONGJMP:
1133 case ISD::EH_SJLJ_SETUP_DISPATCH:
1134 // These operations lie about being legal: when they claim to be legal,
1135 // they should actually be expanded.
1136 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1137 if (Action == TargetLowering::Legal)
1138 Action = TargetLowering::Expand;
1139 break;
1140 case ISD::INIT_TRAMPOLINE:
1141 case ISD::ADJUST_TRAMPOLINE:
1142 case ISD::FRAMEADDR:
1143 case ISD::RETURNADDR:
1144 case ISD::ADDROFRETURNADDR:
1145 case ISD::SPONENTRY:
1146 // These operations lie about being legal: when they claim to be legal,
1147 // they should actually be custom-lowered.
1148 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1149 if (Action == TargetLowering::Legal)
1150 Action = TargetLowering::Custom;
1151 break;
1152 case ISD::CLEAR_CACHE:
1153 // This operation is typically going to be LibCall unless the target wants
1154 // something differrent.
1155 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1156 break;
1157 case ISD::READCYCLECOUNTER:
1158 case ISD::READSTEADYCOUNTER:
1159 // READCYCLECOUNTER and READSTEADYCOUNTER return a i64, even if type
1160 // legalization might have expanded that to several smaller types.
1161 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: MVT::i64);
1162 break;
1163 case ISD::READ_REGISTER:
1164 case ISD::WRITE_REGISTER:
1165 // Named register is legal in the DAG, but blocked by register name
1166 // selection if not implemented by target (to chose the correct register)
1167 // They'll be converted to Copy(To/From)Reg.
1168 Action = TargetLowering::Legal;
1169 break;
1170 case ISD::UBSANTRAP:
1171 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1172 if (Action == TargetLowering::Expand) {
1173 // replace ISD::UBSANTRAP with ISD::TRAP
1174 SDValue NewVal;
1175 NewVal = DAG.getNode(Opcode: ISD::TRAP, DL: SDLoc(Node), VTList: Node->getVTList(),
1176 N: Node->getOperand(Num: 0));
1177 ReplaceNode(Old: Node, New: NewVal.getNode());
1178 LegalizeOp(Node: NewVal.getNode());
1179 return;
1180 }
1181 break;
1182 case ISD::DEBUGTRAP:
1183 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1184 if (Action == TargetLowering::Expand) {
1185 // replace ISD::DEBUGTRAP with ISD::TRAP
1186 SDValue NewVal;
1187 NewVal = DAG.getNode(Opcode: ISD::TRAP, DL: SDLoc(Node), VTList: Node->getVTList(),
1188 N: Node->getOperand(Num: 0));
1189 ReplaceNode(Old: Node, New: NewVal.getNode());
1190 LegalizeOp(Node: NewVal.getNode());
1191 return;
1192 }
1193 break;
1194 case ISD::SADDSAT:
1195 case ISD::UADDSAT:
1196 case ISD::SSUBSAT:
1197 case ISD::USUBSAT:
1198 case ISD::SSHLSAT:
1199 case ISD::USHLSAT:
1200 case ISD::SCMP:
1201 case ISD::UCMP:
1202 case ISD::FP_TO_SINT_SAT:
1203 case ISD::FP_TO_UINT_SAT:
1204 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1205 break;
1206 case ISD::SMULFIX:
1207 case ISD::SMULFIXSAT:
1208 case ISD::UMULFIX:
1209 case ISD::UMULFIXSAT:
1210 case ISD::SDIVFIX:
1211 case ISD::SDIVFIXSAT:
1212 case ISD::UDIVFIX:
1213 case ISD::UDIVFIXSAT: {
1214 unsigned Scale = Node->getConstantOperandVal(Num: 2);
1215 Action = TLI.getFixedPointOperationAction(Op: Node->getOpcode(),
1216 VT: Node->getValueType(ResNo: 0), Scale);
1217 break;
1218 }
1219 case ISD::MSCATTER:
1220 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1221 VT: cast<MaskedScatterSDNode>(Val: Node)->getValue().getValueType());
1222 break;
1223 case ISD::MSTORE:
1224 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1225 VT: cast<MaskedStoreSDNode>(Val: Node)->getValue().getValueType());
1226 break;
1227 case ISD::VP_SCATTER:
1228 Action = TLI.getOperationAction(
1229 Op: Node->getOpcode(),
1230 VT: cast<VPScatterSDNode>(Val: Node)->getValue().getValueType());
1231 break;
1232 case ISD::VP_STORE:
1233 Action = TLI.getOperationAction(
1234 Op: Node->getOpcode(),
1235 VT: cast<VPStoreSDNode>(Val: Node)->getValue().getValueType());
1236 break;
1237 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
1238 Action = TLI.getOperationAction(
1239 Op: Node->getOpcode(),
1240 VT: cast<VPStridedStoreSDNode>(Val: Node)->getValue().getValueType());
1241 break;
1242 case ISD::VECREDUCE_FADD:
1243 case ISD::VECREDUCE_FMUL:
1244 case ISD::VECREDUCE_ADD:
1245 case ISD::VECREDUCE_MUL:
1246 case ISD::VECREDUCE_AND:
1247 case ISD::VECREDUCE_OR:
1248 case ISD::VECREDUCE_XOR:
1249 case ISD::VECREDUCE_SMAX:
1250 case ISD::VECREDUCE_SMIN:
1251 case ISD::VECREDUCE_UMAX:
1252 case ISD::VECREDUCE_UMIN:
1253 case ISD::VECREDUCE_FMAX:
1254 case ISD::VECREDUCE_FMIN:
1255 case ISD::VECREDUCE_FMAXIMUM:
1256 case ISD::VECREDUCE_FMINIMUM:
1257 case ISD::IS_FPCLASS:
1258 Action = TLI.getOperationAction(
1259 Op: Node->getOpcode(), VT: Node->getOperand(Num: 0).getValueType());
1260 break;
1261 case ISD::VECREDUCE_SEQ_FADD:
1262 case ISD::VECREDUCE_SEQ_FMUL:
1263 case ISD::VP_REDUCE_FADD:
1264 case ISD::VP_REDUCE_FMUL:
1265 case ISD::VP_REDUCE_ADD:
1266 case ISD::VP_REDUCE_MUL:
1267 case ISD::VP_REDUCE_AND:
1268 case ISD::VP_REDUCE_OR:
1269 case ISD::VP_REDUCE_XOR:
1270 case ISD::VP_REDUCE_SMAX:
1271 case ISD::VP_REDUCE_SMIN:
1272 case ISD::VP_REDUCE_UMAX:
1273 case ISD::VP_REDUCE_UMIN:
1274 case ISD::VP_REDUCE_FMAX:
1275 case ISD::VP_REDUCE_FMIN:
1276 case ISD::VP_REDUCE_FMAXIMUM:
1277 case ISD::VP_REDUCE_FMINIMUM:
1278 case ISD::VP_REDUCE_SEQ_FADD:
1279 case ISD::VP_REDUCE_SEQ_FMUL:
1280 Action = TLI.getOperationAction(
1281 Op: Node->getOpcode(), VT: Node->getOperand(Num: 1).getValueType());
1282 break;
1283 case ISD::CTTZ_ELTS:
1284 case ISD::CTTZ_ELTS_ZERO_POISON:
1285 case ISD::VP_CTTZ_ELTS:
1286 case ISD::VP_CTTZ_ELTS_ZERO_POISON:
1287 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1288 VT: Node->getOperand(Num: 0).getValueType());
1289 break;
1290 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
1291 Action = TLI.getOperationAction(
1292 Op: Node->getOpcode(),
1293 VT: cast<MaskedHistogramSDNode>(Val: Node)->getIndex().getValueType());
1294 break;
1295 default:
1296 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1297 Action = TLI.getCustomOperationAction(Op&: *Node);
1298 } else {
1299 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1300 }
1301 break;
1302 }
1303
1304 if (SimpleFinishLegalizing) {
1305 SDNode *NewNode = Node;
1306 switch (Node->getOpcode()) {
1307 default: break;
1308 case ISD::SHL:
1309 case ISD::SRL:
1310 case ISD::SRA:
1311 case ISD::ROTL:
1312 case ISD::ROTR:
1313 case ISD::SSHLSAT:
1314 case ISD::USHLSAT: {
1315 // Legalizing shifts/rotates requires adjusting the shift amount
1316 // to the appropriate width.
1317 SDValue Op0 = Node->getOperand(Num: 0);
1318 SDValue Op1 = Node->getOperand(Num: 1);
1319 if (!Op1.getValueType().isVector()) {
1320 SDValue SAO = DAG.getShiftAmountOperand(LHSTy: Op0.getValueType(), Op: Op1);
1321 // The getShiftAmountOperand() may create a new operand node or
1322 // return the existing one. If new operand is created we need
1323 // to update the parent node.
1324 // Do not try to legalize SAO here! It will be automatically legalized
1325 // in the next round.
1326 if (SAO != Op1)
1327 NewNode = DAG.UpdateNodeOperands(N: Node, Op1: Op0, Op2: SAO);
1328 }
1329 break;
1330 }
1331 case ISD::FSHL:
1332 case ISD::FSHR:
1333 case ISD::SRL_PARTS:
1334 case ISD::SRA_PARTS:
1335 case ISD::SHL_PARTS: {
1336 // Legalizing shifts/rotates requires adjusting the shift amount
1337 // to the appropriate width.
1338 SDValue Op0 = Node->getOperand(Num: 0);
1339 SDValue Op1 = Node->getOperand(Num: 1);
1340 SDValue Op2 = Node->getOperand(Num: 2);
1341 if (!Op2.getValueType().isVector()) {
1342 SDValue SAO = DAG.getShiftAmountOperand(LHSTy: Op0.getValueType(), Op: Op2);
1343 // The getShiftAmountOperand() may create a new operand node or
1344 // return the existing one. If new operand is created we need
1345 // to update the parent node.
1346 if (SAO != Op2)
1347 NewNode = DAG.UpdateNodeOperands(N: Node, Op1: Op0, Op2: Op1, Op3: SAO);
1348 }
1349 break;
1350 }
1351 }
1352
1353 if (NewNode != Node) {
1354 ReplaceNode(Old: Node, New: NewNode);
1355 Node = NewNode;
1356 }
1357 switch (Action) {
1358 case TargetLowering::Legal:
1359 LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1360 return;
1361 case TargetLowering::Custom:
1362 LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1363 // FIXME: The handling for custom lowering with multiple results is
1364 // a complete mess.
1365 if (SDValue Res = TLI.LowerOperation(Op: SDValue(Node, 0), DAG)) {
1366 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1367 return;
1368
1369 if (Node->getNumValues() == 1) {
1370 // Verify the new types match the original. Glue is waived because
1371 // ISD::ADDC can be legalized by replacing Glue with an integer type.
1372 assert((Res.getValueType() == Node->getValueType(0) ||
1373 Node->getValueType(0) == MVT::Glue) &&
1374 "Type mismatch for custom legalized operation");
1375 LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1376 // We can just directly replace this node with the lowered value.
1377 ReplaceNode(Old: SDValue(Node, 0), New: Res);
1378 return;
1379 }
1380
1381 SmallVector<SDValue, 8> ResultVals;
1382 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1383 // Verify the new types match the original. Glue is waived because
1384 // ISD::ADDC can be legalized by replacing Glue with an integer type.
1385 assert((Res->getValueType(i) == Node->getValueType(i) ||
1386 Node->getValueType(i) == MVT::Glue) &&
1387 "Type mismatch for custom legalized operation");
1388 ResultVals.push_back(Elt: Res.getValue(R: i));
1389 }
1390 LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1391 ReplaceNode(Old: Node, New: ResultVals.data());
1392 return;
1393 }
1394 LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1395 [[fallthrough]];
1396 case TargetLowering::Expand:
1397 if (ExpandNode(Node))
1398 return;
1399 [[fallthrough]];
1400 case TargetLowering::LibCall:
1401 ConvertNodeToLibcall(Node);
1402 return;
1403 case TargetLowering::Promote:
1404 PromoteNode(Node);
1405 return;
1406 }
1407 }
1408
1409 switch (Node->getOpcode()) {
1410 default:
1411#ifndef NDEBUG
1412 dbgs() << "NODE: ";
1413 Node->dump( &DAG);
1414 dbgs() << "\n";
1415#endif
1416 llvm_unreachable("Do not know how to legalize this operator!");
1417
1418 case ISD::CALLSEQ_START:
1419 case ISD::CALLSEQ_END:
1420 break;
1421 case ISD::LOAD:
1422 return LegalizeLoadOps(Node);
1423 case ISD::STORE:
1424 return LegalizeStoreOps(Node);
1425 }
1426}
1427
1428SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1429 SDValue Vec = Op.getOperand(i: 0);
1430 SDValue Idx = Op.getOperand(i: 1);
1431 SDLoc dl(Op);
1432
1433 // Before we generate a new store to a temporary stack slot, see if there is
1434 // already one that we can use. There often is because when we scalarize
1435 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1436 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1437 // the vector. If all are expanded here, we don't want one store per vector
1438 // element.
1439
1440 // Caches for hasPredecessorHelper
1441 SmallPtrSet<const SDNode *, 32> Visited;
1442 SmallVector<const SDNode *, 16> Worklist;
1443 Visited.insert(Ptr: Op.getNode());
1444 Worklist.push_back(Elt: Idx.getNode());
1445 SDValue StackPtr, Ch;
1446 for (SDNode *User : Vec.getNode()->users()) {
1447 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: User)) {
1448 if (ST->isIndexed() || ST->isTruncatingStore() ||
1449 ST->getValue() != Vec)
1450 continue;
1451
1452 // Make sure that nothing else could have stored into the destination of
1453 // this store.
1454 if (!ST->getChain().reachesChainWithoutSideEffects(Dest: DAG.getEntryNode()))
1455 continue;
1456
1457 // If the index is dependent on the store we will introduce a cycle when
1458 // creating the load (the load uses the index, and by replacing the chain
1459 // we will make the index dependent on the load). Also, the store might be
1460 // dependent on the extractelement and introduce a cycle when creating
1461 // the load.
1462 if (SDNode::hasPredecessorHelper(N: ST, Visited, Worklist) ||
1463 ST->hasPredecessor(N: Op.getNode()))
1464 continue;
1465
1466 StackPtr = ST->getBasePtr();
1467 Ch = SDValue(ST, 0);
1468 break;
1469 }
1470 }
1471
1472 EVT VecVT = Vec.getValueType();
1473
1474 if (!Ch.getNode()) {
1475 // Store the value to a temporary stack slot, then LOAD the returned part.
1476 StackPtr = DAG.CreateStackTemporary(VT: VecVT);
1477 MachineMemOperand *StoreMMO = getStackAlignedMMO(
1478 StackPtr, MF&: DAG.getMachineFunction(), isObjectScalable: VecVT.isScalableVector());
1479 Ch = DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: Vec, Ptr: StackPtr, MMO: StoreMMO);
1480 }
1481
1482 SDValue NewLoad;
1483 Align ElementAlignment =
1484 std::min(a: cast<StoreSDNode>(Val&: Ch)->getAlign(),
1485 b: DAG.getDataLayout().getPrefTypeAlign(
1486 Ty: Op.getValueType().getTypeForEVT(Context&: *DAG.getContext())));
1487
1488 if (Op.getValueType().isVector()) {
1489 StackPtr = TLI.getVectorSubVecPointer(DAG, VecPtr: StackPtr, VecVT,
1490 SubVecVT: Op.getValueType(), Index: Idx);
1491 NewLoad = DAG.getLoad(VT: Op.getValueType(), dl, Chain: Ch, Ptr: StackPtr,
1492 PtrInfo: MachinePointerInfo(), Alignment: ElementAlignment);
1493 } else {
1494 StackPtr = TLI.getVectorElementPointer(DAG, VecPtr: StackPtr, VecVT, Index: Idx);
1495 NewLoad = DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl, VT: Op.getValueType(), Chain: Ch, Ptr: StackPtr,
1496 PtrInfo: MachinePointerInfo(), MemVT: VecVT.getVectorElementType(),
1497 Alignment: ElementAlignment);
1498 }
1499
1500 // Replace the chain going out of the store, by the one out of the load.
1501 DAG.ReplaceAllUsesOfValueWith(From: Ch, To: SDValue(NewLoad.getNode(), 1));
1502
1503 // We introduced a cycle though, so update the loads operands, making sure
1504 // to use the original store's chain as an incoming chain.
1505 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->ops());
1506 NewLoadOperands[0] = Ch;
1507 NewLoad =
1508 SDValue(DAG.UpdateNodeOperands(N: NewLoad.getNode(), Ops: NewLoadOperands), 0);
1509 return NewLoad;
1510}
1511
1512SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1513 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1514
1515 SDValue Vec = Op.getOperand(i: 0);
1516 SDValue Part = Op.getOperand(i: 1);
1517 SDValue Idx = Op.getOperand(i: 2);
1518 SDLoc dl(Op);
1519
1520 // Store the value to a temporary stack slot, then LOAD the returned part.
1521 EVT VecVT = Vec.getValueType();
1522 EVT PartVT = Part.getValueType();
1523 SDValue StackPtr = DAG.CreateStackTemporary(VT: VecVT);
1524 int FI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
1525 MachinePointerInfo PtrInfo =
1526 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI);
1527
1528 // First store the whole vector.
1529 Align BaseVecAlignment =
1530 DAG.getMachineFunction().getFrameInfo().getObjectAlign(ObjectIdx: FI);
1531 SDValue Ch = DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: Vec, Ptr: StackPtr, PtrInfo,
1532 Alignment: BaseVecAlignment);
1533
1534 // Freeze the index so we don't poison the clamping code we're about to emit.
1535 Idx = DAG.getFreeze(V: Idx);
1536
1537 Type *PartTy = PartVT.getTypeForEVT(Context&: *DAG.getContext());
1538 Align PartAlignment = DAG.getDataLayout().getPrefTypeAlign(Ty: PartTy);
1539
1540 // Then store the inserted part.
1541 if (PartVT.isVector()) {
1542 SDValue SubStackPtr =
1543 TLI.getVectorSubVecPointer(DAG, VecPtr: StackPtr, VecVT, SubVecVT: PartVT, Index: Idx);
1544
1545 // Store the subvector.
1546 Ch = DAG.getStore(
1547 Chain: Ch, dl, Val: Part, Ptr: SubStackPtr,
1548 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
1549 Alignment: PartAlignment);
1550 } else {
1551 SDValue SubStackPtr =
1552 TLI.getVectorElementPointer(DAG, VecPtr: StackPtr, VecVT, Index: Idx);
1553
1554 // Store the scalar value.
1555 Ch = DAG.getTruncStore(
1556 Chain: Ch, dl, Val: Part, Ptr: SubStackPtr,
1557 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
1558 SVT: VecVT.getVectorElementType(), Alignment: PartAlignment);
1559 }
1560
1561 assert(cast<StoreSDNode>(Ch)->getAlign() == PartAlignment &&
1562 "ElementAlignment does not match!");
1563
1564 // Finally, load the updated vector.
1565 return DAG.getLoad(VT: Op.getValueType(), dl, Chain: Ch, Ptr: StackPtr, PtrInfo,
1566 Alignment: BaseVecAlignment);
1567}
1568
1569SDValue SelectionDAGLegalize::ExpandConcatVectors(SDNode *Node) {
1570 assert(Node->getOpcode() == ISD::CONCAT_VECTORS && "Unexpected opcode!");
1571 SDLoc DL(Node);
1572 SmallVector<SDValue, 16> Ops;
1573 unsigned NumOperands = Node->getNumOperands();
1574 MVT VectorIdxType = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
1575 EVT VectorValueType = Node->getOperand(Num: 0).getValueType();
1576 unsigned NumSubElem = VectorValueType.getVectorNumElements();
1577 EVT ElementValueType = TLI.getTypeToTransformTo(
1578 Context&: *DAG.getContext(), VT: VectorValueType.getVectorElementType());
1579 for (unsigned I = 0; I < NumOperands; ++I) {
1580 SDValue SubOp = Node->getOperand(Num: I);
1581 for (unsigned Idx = 0; Idx < NumSubElem; ++Idx) {
1582 Ops.push_back(Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: ElementValueType,
1583 N1: SubOp,
1584 N2: DAG.getConstant(Val: Idx, DL, VT: VectorIdxType)));
1585 }
1586 }
1587 return DAG.getBuildVector(VT: Node->getValueType(ResNo: 0), DL, Ops);
1588}
1589
1590SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1591 assert((Node->getOpcode() == ISD::BUILD_VECTOR ||
1592 Node->getOpcode() == ISD::CONCAT_VECTORS) &&
1593 "Unexpected opcode!");
1594
1595 // We can't handle this case efficiently. Allocate a sufficiently
1596 // aligned object on the stack, store each operand into it, then load
1597 // the result as a vector.
1598 // Create the stack frame object.
1599 EVT VT = Node->getValueType(ResNo: 0);
1600 EVT MemVT = isa<BuildVectorSDNode>(Val: Node) ? VT.getVectorElementType()
1601 : Node->getOperand(Num: 0).getValueType();
1602 SDLoc dl(Node);
1603 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1604 int FI = cast<FrameIndexSDNode>(Val: FIPtr.getNode())->getIndex();
1605 MachinePointerInfo PtrInfo =
1606 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI);
1607
1608 // Emit a store of each element to the stack slot.
1609 SmallVector<SDValue, 8> Stores;
1610 unsigned TypeByteSize = MemVT.getSizeInBits() / 8;
1611 assert(TypeByteSize > 0 && "Vector element type too small for stack store!");
1612
1613 // If the destination vector element type of a BUILD_VECTOR is narrower than
1614 // the source element type, only store the bits necessary.
1615 bool Truncate = isa<BuildVectorSDNode>(Val: Node) &&
1616 MemVT.bitsLT(VT: Node->getOperand(Num: 0).getValueType());
1617
1618 // Store (in the right endianness) the elements to memory.
1619 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1620 // Ignore undef elements.
1621 if (Node->getOperand(Num: i).isUndef()) continue;
1622
1623 unsigned Offset = TypeByteSize*i;
1624
1625 SDValue Idx =
1626 DAG.getMemBasePlusOffset(Base: FIPtr, Offset: TypeSize::getFixed(ExactSize: Offset), DL: dl);
1627
1628 if (Truncate)
1629 Stores.push_back(Elt: DAG.getTruncStore(Chain: DAG.getEntryNode(), dl,
1630 Val: Node->getOperand(Num: i), Ptr: Idx,
1631 PtrInfo: PtrInfo.getWithOffset(O: Offset), SVT: MemVT));
1632 else
1633 Stores.push_back(Elt: DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: Node->getOperand(Num: i),
1634 Ptr: Idx, PtrInfo: PtrInfo.getWithOffset(O: Offset)));
1635 }
1636
1637 SDValue StoreChain;
1638 if (!Stores.empty()) // Not all undef elements?
1639 StoreChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: Stores);
1640 else
1641 StoreChain = DAG.getEntryNode();
1642
1643 // Result is a load from the stack slot.
1644 return DAG.getLoad(VT, dl, Chain: StoreChain, Ptr: FIPtr, PtrInfo);
1645}
1646
1647/// Bitcast a floating-point value to an integer value. Only bitcast the part
1648/// containing the sign bit if the target has no integer value capable of
1649/// holding all bits of the floating-point value.
1650void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1651 const SDLoc &DL,
1652 SDValue Value) const {
1653 EVT FloatVT = Value.getValueType();
1654 unsigned NumBits = FloatVT.getScalarSizeInBits();
1655 State.FloatVT = FloatVT;
1656 EVT IVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumBits);
1657 // Convert to an integer of the same size.
1658 if (TLI.isTypeLegal(VT: IVT)) {
1659 State.IntValue = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: IVT, Operand: Value);
1660 State.SignMask = APInt::getSignMask(BitWidth: NumBits);
1661 State.SignBit = NumBits - 1;
1662 return;
1663 }
1664
1665 auto &DataLayout = DAG.getDataLayout();
1666 // Store the float to memory, then load the sign part out as an integer.
1667 MVT LoadTy = TLI.getRegisterType(VT: MVT::i8);
1668 // First create a temporary that is aligned for both the load and store.
1669 SDValue StackPtr = DAG.CreateStackTemporary(VT1: FloatVT, VT2: LoadTy);
1670 int FI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
1671 // Then store the float to it.
1672 State.FloatPtr = StackPtr;
1673 MachineFunction &MF = DAG.getMachineFunction();
1674 State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1675 State.Chain = DAG.getStore(Chain: DAG.getEntryNode(), dl: DL, Val: Value, Ptr: State.FloatPtr,
1676 PtrInfo: State.FloatPointerInfo);
1677
1678 SDValue IntPtr;
1679 if (DataLayout.isBigEndian()) {
1680 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1681 // Load out a legal integer with the same sign bit as the float.
1682 IntPtr = StackPtr;
1683 State.IntPointerInfo = State.FloatPointerInfo;
1684 } else {
1685 // Advance the pointer so that the loaded byte will contain the sign bit.
1686 unsigned ByteOffset = (NumBits / 8) - 1;
1687 IntPtr =
1688 DAG.getMemBasePlusOffset(Base: StackPtr, Offset: TypeSize::getFixed(ExactSize: ByteOffset), DL);
1689 State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1690 Offset: ByteOffset);
1691 }
1692
1693 State.IntPtr = IntPtr;
1694 State.IntValue = DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl: DL, VT: LoadTy, Chain: State.Chain, Ptr: IntPtr,
1695 PtrInfo: State.IntPointerInfo, MemVT: MVT::i8);
1696 State.SignMask = APInt::getOneBitSet(numBits: LoadTy.getScalarSizeInBits(), BitNo: 7);
1697 State.SignBit = 7;
1698}
1699
1700/// Replace the integer value produced by getSignAsIntValue() with a new value
1701/// and cast the result back to a floating-point type.
1702SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1703 const SDLoc &DL,
1704 SDValue NewIntValue) const {
1705 if (!State.Chain)
1706 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: State.FloatVT, Operand: NewIntValue);
1707
1708 // Override the part containing the sign bit in the value stored on the stack.
1709 SDValue Chain = DAG.getTruncStore(Chain: State.Chain, dl: DL, Val: NewIntValue, Ptr: State.IntPtr,
1710 PtrInfo: State.IntPointerInfo, SVT: MVT::i8);
1711 return DAG.getLoad(VT: State.FloatVT, dl: DL, Chain, Ptr: State.FloatPtr,
1712 PtrInfo: State.FloatPointerInfo);
1713}
1714
1715SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1716 SDLoc DL(Node);
1717 SDValue Mag = Node->getOperand(Num: 0);
1718 SDValue Sign = Node->getOperand(Num: 1);
1719
1720 // Get sign bit into an integer value.
1721 FloatSignAsInt SignAsInt;
1722 getSignAsIntValue(State&: SignAsInt, DL, Value: Sign);
1723
1724 EVT IntVT = SignAsInt.IntValue.getValueType();
1725 SDValue SignMask = DAG.getConstant(Val: SignAsInt.SignMask, DL, VT: IntVT);
1726 SDValue SignBit = DAG.getNode(Opcode: ISD::AND, DL, VT: IntVT, N1: SignAsInt.IntValue,
1727 N2: SignMask);
1728
1729 // If FABS is legal transform
1730 // FCOPYSIGN(x, y) => SignBit(y) ? -FABS(x) : FABS(x)
1731 EVT FloatVT = Mag.getValueType();
1732 if (TLI.isOperationLegalOrCustom(Op: ISD::FABS, VT: FloatVT) &&
1733 TLI.isOperationLegalOrCustom(Op: ISD::FNEG, VT: FloatVT)) {
1734 SDValue AbsValue = DAG.getNode(Opcode: ISD::FABS, DL, VT: FloatVT, Operand: Mag);
1735 SDValue NegValue = DAG.getNode(Opcode: ISD::FNEG, DL, VT: FloatVT, Operand: AbsValue);
1736 SDValue Cond = DAG.getSetCC(DL, VT: getSetCCResultType(VT: IntVT), LHS: SignBit,
1737 RHS: DAG.getConstant(Val: 0, DL, VT: IntVT), Cond: ISD::SETNE);
1738 return DAG.getSelect(DL, VT: FloatVT, Cond, LHS: NegValue, RHS: AbsValue);
1739 }
1740
1741 // Transform Mag value to integer, and clear the sign bit.
1742 FloatSignAsInt MagAsInt;
1743 getSignAsIntValue(State&: MagAsInt, DL, Value: Mag);
1744 EVT MagVT = MagAsInt.IntValue.getValueType();
1745 SDValue ClearSignMask = DAG.getConstant(Val: ~MagAsInt.SignMask, DL, VT: MagVT);
1746 SDValue ClearedSign = DAG.getNode(Opcode: ISD::AND, DL, VT: MagVT, N1: MagAsInt.IntValue,
1747 N2: ClearSignMask);
1748
1749 // Get the signbit at the right position for MagAsInt.
1750 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1751 EVT ShiftVT = IntVT;
1752 if (SignBit.getScalarValueSizeInBits() <
1753 ClearedSign.getScalarValueSizeInBits()) {
1754 SignBit = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MagVT, Operand: SignBit);
1755 ShiftVT = MagVT;
1756 }
1757 if (ShiftAmount > 0) {
1758 SDValue ShiftCnst = DAG.getConstant(Val: ShiftAmount, DL, VT: ShiftVT);
1759 SignBit = DAG.getNode(Opcode: ISD::SRL, DL, VT: ShiftVT, N1: SignBit, N2: ShiftCnst);
1760 } else if (ShiftAmount < 0) {
1761 SDValue ShiftCnst = DAG.getConstant(Val: -ShiftAmount, DL, VT: ShiftVT);
1762 SignBit = DAG.getNode(Opcode: ISD::SHL, DL, VT: ShiftVT, N1: SignBit, N2: ShiftCnst);
1763 }
1764 if (SignBit.getScalarValueSizeInBits() >
1765 ClearedSign.getScalarValueSizeInBits()) {
1766 SignBit = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MagVT, Operand: SignBit);
1767 }
1768
1769 // Store the part with the modified sign and convert back to float.
1770 SDValue CopiedSign = DAG.getNode(Opcode: ISD::OR, DL, VT: MagVT, N1: ClearedSign, N2: SignBit,
1771 Flags: SDNodeFlags::Disjoint);
1772
1773 return modifySignAsInt(State: MagAsInt, DL, NewIntValue: CopiedSign);
1774}
1775
1776SDValue SelectionDAGLegalize::ExpandFNEG(SDNode *Node) const {
1777 // Get the sign bit as an integer.
1778 SDLoc DL(Node);
1779 FloatSignAsInt SignAsInt;
1780 getSignAsIntValue(State&: SignAsInt, DL, Value: Node->getOperand(Num: 0));
1781 EVT IntVT = SignAsInt.IntValue.getValueType();
1782
1783 // Flip the sign.
1784 SDValue SignMask = DAG.getConstant(Val: SignAsInt.SignMask, DL, VT: IntVT);
1785 SDValue SignFlip =
1786 DAG.getNode(Opcode: ISD::XOR, DL, VT: IntVT, N1: SignAsInt.IntValue, N2: SignMask);
1787
1788 // Convert back to float.
1789 return modifySignAsInt(State: SignAsInt, DL, NewIntValue: SignFlip);
1790}
1791
1792SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1793 SDLoc DL(Node);
1794 SDValue Value = Node->getOperand(Num: 0);
1795
1796 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1797 EVT FloatVT = Value.getValueType();
1798 if (TLI.isOperationLegalOrCustom(Op: ISD::FCOPYSIGN, VT: FloatVT)) {
1799 SDValue Zero = DAG.getConstantFP(Val: 0.0, DL, VT: FloatVT);
1800 return DAG.getNode(Opcode: ISD::FCOPYSIGN, DL, VT: FloatVT, N1: Value, N2: Zero);
1801 }
1802
1803 // Transform value to integer, clear the sign bit and transform back.
1804 FloatSignAsInt ValueAsInt;
1805 getSignAsIntValue(State&: ValueAsInt, DL, Value);
1806 EVT IntVT = ValueAsInt.IntValue.getValueType();
1807 SDValue ClearSignMask = DAG.getConstant(Val: ~ValueAsInt.SignMask, DL, VT: IntVT);
1808 SDValue ClearedSign = DAG.getNode(Opcode: ISD::AND, DL, VT: IntVT, N1: ValueAsInt.IntValue,
1809 N2: ClearSignMask);
1810 return modifySignAsInt(State: ValueAsInt, DL, NewIntValue: ClearedSign);
1811}
1812
1813void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1814 SmallVectorImpl<SDValue> &Results) {
1815 Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
1816 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1817 " not tell us which reg is the stack pointer!");
1818 SDLoc dl(Node);
1819 EVT VT = Node->getValueType(ResNo: 0);
1820 SDValue Tmp1 = SDValue(Node, 0);
1821 SDValue Tmp2 = SDValue(Node, 1);
1822 SDValue Tmp3 = Node->getOperand(Num: 2);
1823 SDValue Chain = Tmp1.getOperand(i: 0);
1824
1825 // Chain the dynamic stack allocation so that it doesn't modify the stack
1826 // pointer when other instructions are using the stack.
1827 Chain = DAG.getCALLSEQ_START(Chain, InSize: 0, OutSize: 0, DL: dl);
1828
1829 SDValue Size = Tmp2.getOperand(i: 1);
1830 SDValue SP = DAG.getCopyFromReg(Chain, dl, Reg: SPReg, VT);
1831 Chain = SP.getValue(R: 1);
1832 Align Alignment = cast<ConstantSDNode>(Val&: Tmp3)->getAlignValue();
1833 const TargetFrameLowering *TFL = DAG.getSubtarget().getFrameLowering();
1834 unsigned Opc =
1835 TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp ?
1836 ISD::ADD : ISD::SUB;
1837
1838 Align StackAlign = TFL->getStackAlign();
1839 Tmp1 = DAG.getNode(Opcode: Opc, DL: dl, VT, N1: SP, N2: Size); // Value
1840 if (Alignment > StackAlign)
1841 Tmp1 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Tmp1,
1842 N2: DAG.getSignedConstant(Val: -Alignment.value(), DL: dl, VT));
1843 Chain = DAG.getCopyToReg(Chain, dl, Reg: SPReg, N: Tmp1); // Output chain
1844
1845 Tmp2 = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: SDValue(), DL: dl);
1846
1847 Results.push_back(Elt: Tmp1);
1848 Results.push_back(Elt: Tmp2);
1849}
1850
1851/// Emit a store/load combination to the stack. This stores
1852/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1853/// a load from the stack slot to DestVT, extending it if needed.
1854/// The resultant code need not be legal.
1855SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1856 EVT DestVT, const SDLoc &dl) {
1857 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, ChainIn: DAG.getEntryNode());
1858}
1859
1860SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1861 EVT DestVT, const SDLoc &dl,
1862 SDValue Chain) {
1863 EVT SrcVT = SrcOp.getValueType();
1864 Type *DestType = DestVT.getTypeForEVT(Context&: *DAG.getContext());
1865 Align DestAlign = DAG.getDataLayout().getPrefTypeAlign(Ty: DestType);
1866
1867 // Don't convert with stack if the load/store is expensive.
1868 if ((SrcVT.bitsGT(VT: SlotVT) && !TLI.isTruncStoreLegalOrCustom(
1869 ValVT: SrcOp.getValueType(), MemVT: SlotVT, Alignment: DestAlign,
1870 AddrSpace: DAG.getDataLayout().getAllocaAddrSpace())) ||
1871 (SlotVT.bitsLT(VT: DestVT) &&
1872 !TLI.isLoadLegalOrCustom(ValVT: DestVT, MemVT: SlotVT, Alignment: DestAlign,
1873 AddrSpace: DAG.getDataLayout().getAllocaAddrSpace(),
1874 ExtType: ISD::EXTLOAD, Atomic: false)))
1875 return SDValue();
1876
1877 // Create the stack frame object.
1878 Align SrcAlign = DAG.getDataLayout().getPrefTypeAlign(
1879 Ty: SrcOp.getValueType().getTypeForEVT(Context&: *DAG.getContext()));
1880 SDValue FIPtr = DAG.CreateStackTemporary(Bytes: SlotVT.getStoreSize(), Alignment: SrcAlign);
1881
1882 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(Val&: FIPtr);
1883 int SPFI = StackPtrFI->getIndex();
1884 MachinePointerInfo PtrInfo =
1885 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
1886
1887 // Emit a store to the stack slot. Use a truncstore if the input value is
1888 // later than DestVT.
1889 SDValue Store;
1890
1891 if (SrcVT.bitsGT(VT: SlotVT))
1892 Store = DAG.getTruncStore(Chain, dl, Val: SrcOp, Ptr: FIPtr, PtrInfo,
1893 SVT: SlotVT, Alignment: SrcAlign);
1894 else {
1895 assert(SrcVT.bitsEq(SlotVT) && "Invalid store");
1896 Store = DAG.getStore(Chain, dl, Val: SrcOp, Ptr: FIPtr, PtrInfo, Alignment: SrcAlign);
1897 }
1898
1899 // Result is a load from the stack slot.
1900 if (SlotVT.bitsEq(VT: DestVT))
1901 return DAG.getLoad(VT: DestVT, dl, Chain: Store, Ptr: FIPtr, PtrInfo, Alignment: DestAlign);
1902
1903 assert(SlotVT.bitsLT(DestVT) && "Unknown extension!");
1904 return DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl, VT: DestVT, Chain: Store, Ptr: FIPtr, PtrInfo, MemVT: SlotVT,
1905 Alignment: DestAlign);
1906}
1907
1908SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1909 SDLoc dl(Node);
1910 // Create a vector sized/aligned stack slot, store the value to element #0,
1911 // then load the whole vector back out.
1912 SDValue StackPtr = DAG.CreateStackTemporary(VT: Node->getValueType(ResNo: 0));
1913
1914 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(Val&: StackPtr);
1915 int SPFI = StackPtrFI->getIndex();
1916
1917 SDValue Ch = DAG.getTruncStore(
1918 Chain: DAG.getEntryNode(), dl, Val: Node->getOperand(Num: 0), Ptr: StackPtr,
1919 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI),
1920 SVT: Node->getValueType(ResNo: 0).getVectorElementType());
1921 return DAG.getLoad(
1922 VT: Node->getValueType(ResNo: 0), dl, Chain: Ch, Ptr: StackPtr,
1923 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI));
1924}
1925
1926static bool
1927ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1928 const TargetLowering &TLI, SDValue &Res) {
1929 unsigned NumElems = Node->getNumOperands();
1930 SDLoc dl(Node);
1931 EVT VT = Node->getValueType(ResNo: 0);
1932
1933 // Try to group the scalars into pairs, shuffle the pairs together, then
1934 // shuffle the pairs of pairs together, etc. until the vector has
1935 // been built. This will work only if all of the necessary shuffle masks
1936 // are legal.
1937
1938 // We do this in two phases; first to check the legality of the shuffles,
1939 // and next, assuming that all shuffles are legal, to create the new nodes.
1940 for (int Phase = 0; Phase < 2; ++Phase) {
1941 SmallVector<std::pair<SDValue, SmallVector<int, 16>>, 16> IntermedVals,
1942 NewIntermedVals;
1943 for (unsigned i = 0; i < NumElems; ++i) {
1944 SDValue V = Node->getOperand(Num: i);
1945 if (V.isUndef())
1946 continue;
1947
1948 SDValue Vec;
1949 if (Phase)
1950 Vec = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT, Operand: V);
1951 IntermedVals.push_back(Elt: std::make_pair(x&: Vec, y: SmallVector<int, 16>(1, i)));
1952 }
1953
1954 while (IntermedVals.size() > 2) {
1955 NewIntermedVals.clear();
1956 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1957 // This vector and the next vector are shuffled together (simply to
1958 // append the one to the other).
1959 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1960
1961 SmallVector<int, 16> FinalIndices;
1962 FinalIndices.reserve(N: IntermedVals[i].second.size() +
1963 IntermedVals[i+1].second.size());
1964
1965 int k = 0;
1966 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1967 ++j, ++k) {
1968 ShuffleVec[k] = j;
1969 FinalIndices.push_back(Elt: IntermedVals[i].second[j]);
1970 }
1971 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1972 ++j, ++k) {
1973 ShuffleVec[k] = NumElems + j;
1974 FinalIndices.push_back(Elt: IntermedVals[i+1].second[j]);
1975 }
1976
1977 SDValue Shuffle;
1978 if (Phase)
1979 Shuffle = DAG.getVectorShuffle(VT, dl, N1: IntermedVals[i].first,
1980 N2: IntermedVals[i+1].first,
1981 Mask: ShuffleVec);
1982 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1983 return false;
1984 NewIntermedVals.push_back(
1985 Elt: std::make_pair(x&: Shuffle, y: std::move(FinalIndices)));
1986 }
1987
1988 // If we had an odd number of defined values, then append the last
1989 // element to the array of new vectors.
1990 if ((IntermedVals.size() & 1) != 0)
1991 NewIntermedVals.push_back(Elt: IntermedVals.back());
1992
1993 IntermedVals.swap(RHS&: NewIntermedVals);
1994 }
1995
1996 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1997 "Invalid number of intermediate vectors");
1998 SDValue Vec1 = IntermedVals[0].first;
1999 SDValue Vec2;
2000 if (IntermedVals.size() > 1)
2001 Vec2 = IntermedVals[1].first;
2002 else if (Phase)
2003 Vec2 = DAG.getPOISON(VT);
2004
2005 SmallVector<int, 16> ShuffleVec(NumElems, -1);
2006 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
2007 ShuffleVec[IntermedVals[0].second[i]] = i;
2008 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
2009 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
2010
2011 if (Phase)
2012 Res = DAG.getVectorShuffle(VT, dl, N1: Vec1, N2: Vec2, Mask: ShuffleVec);
2013 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
2014 return false;
2015 }
2016
2017 return true;
2018}
2019
2020/// Expand a BUILD_VECTOR node on targets that don't
2021/// support the operation, but do support the resultant vector type.
2022SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
2023 unsigned NumElems = Node->getNumOperands();
2024 SDValue Value1, Value2;
2025 SDLoc dl(Node);
2026 EVT VT = Node->getValueType(ResNo: 0);
2027 EVT OpVT = Node->getOperand(Num: 0).getValueType();
2028 EVT EltVT = VT.getVectorElementType();
2029
2030 // If the only non-undef value is the low element, turn this into a
2031 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
2032 bool isOnlyLowElement = true;
2033 bool MoreThanTwoValues = false;
2034 bool isConstant = true;
2035 for (unsigned i = 0; i < NumElems; ++i) {
2036 SDValue V = Node->getOperand(Num: i);
2037 if (V.isUndef())
2038 continue;
2039 if (i > 0)
2040 isOnlyLowElement = false;
2041 if (!isa<ConstantFPSDNode>(Val: V) && !isa<ConstantSDNode>(Val: V))
2042 isConstant = false;
2043
2044 if (!Value1.getNode()) {
2045 Value1 = V;
2046 } else if (!Value2.getNode()) {
2047 if (V != Value1)
2048 Value2 = V;
2049 } else if (V != Value1 && V != Value2) {
2050 MoreThanTwoValues = true;
2051 }
2052 }
2053
2054 if (!Value1.getNode())
2055 return DAG.getUNDEF(VT);
2056
2057 if (isOnlyLowElement)
2058 return DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT, Operand: Node->getOperand(Num: 0));
2059
2060 // If all elements are constants, create a load from the constant pool.
2061 if (isConstant) {
2062 SmallVector<Constant*, 16> CV;
2063 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2064 if (ConstantFPSDNode *V =
2065 dyn_cast<ConstantFPSDNode>(Val: Node->getOperand(Num: i))) {
2066 CV.push_back(Elt: const_cast<ConstantFP *>(V->getConstantFPValue()));
2067 } else if (ConstantSDNode *V =
2068 dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: i))) {
2069 if (OpVT==EltVT)
2070 CV.push_back(Elt: const_cast<ConstantInt *>(V->getConstantIntValue()));
2071 else {
2072 // If OpVT and EltVT don't match, EltVT is not legal and the
2073 // element values have been promoted/truncated earlier. Undo this;
2074 // we don't want a v16i8 to become a v16i32 for example.
2075 const ConstantInt *CI = V->getConstantIntValue();
2076 CV.push_back(Elt: ConstantInt::get(Ty: EltVT.getTypeForEVT(Context&: *DAG.getContext()),
2077 V: CI->getZExtValue(), /*IsSigned=*/false,
2078 /*ImplicitTrunc=*/true));
2079 }
2080 } else {
2081 assert(Node->getOperand(i).isUndef());
2082 Type *OpNTy = EltVT.getTypeForEVT(Context&: *DAG.getContext());
2083 CV.push_back(Elt: UndefValue::get(T: OpNTy));
2084 }
2085 }
2086 Constant *CP = ConstantVector::get(V: CV);
2087 SDValue CPIdx =
2088 DAG.getConstantPool(C: CP, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
2089 Align Alignment = cast<ConstantPoolSDNode>(Val&: CPIdx)->getAlign();
2090 return DAG.getLoad(
2091 VT, dl, Chain: DAG.getEntryNode(), Ptr: CPIdx,
2092 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()),
2093 Alignment);
2094 }
2095
2096 SmallSet<SDValue, 16> DefinedValues;
2097 for (unsigned i = 0; i < NumElems; ++i) {
2098 if (Node->getOperand(Num: i).isUndef())
2099 continue;
2100 DefinedValues.insert(V: Node->getOperand(Num: i));
2101 }
2102
2103 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues: DefinedValues.size())) {
2104 if (!MoreThanTwoValues) {
2105 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2106 for (unsigned i = 0; i < NumElems; ++i) {
2107 SDValue V = Node->getOperand(Num: i);
2108 if (V.isUndef())
2109 continue;
2110 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2111 }
2112 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(ResNo: 0))) {
2113 // Get the splatted value into the low element of a vector register.
2114 SDValue Vec1 = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT, Operand: Value1);
2115 SDValue Vec2;
2116 if (Value2.getNode())
2117 Vec2 = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT, Operand: Value2);
2118 else
2119 Vec2 = DAG.getPOISON(VT);
2120
2121 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2122 return DAG.getVectorShuffle(VT, dl, N1: Vec1, N2: Vec2, Mask: ShuffleVec);
2123 }
2124 } else {
2125 SDValue Res;
2126 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2127 return Res;
2128 }
2129 }
2130
2131 // Otherwise, we can't handle this case efficiently.
2132 return ExpandVectorBuildThroughStack(Node);
2133}
2134
2135SDValue SelectionDAGLegalize::ExpandSPLAT_VECTOR(SDNode *Node) {
2136 SDLoc DL(Node);
2137 EVT VT = Node->getValueType(ResNo: 0);
2138 SDValue SplatVal = Node->getOperand(Num: 0);
2139
2140 return DAG.getSplatBuildVector(VT, DL, Op: SplatVal);
2141}
2142
2143// Expand a node into a call to a libcall, returning the value as the first
2144// result and the chain as the second. If the result value does not fit into a
2145// register, return the lo part and set the hi part to the by-reg argument in
2146// the first. If it does fit into a single register, return the result and
2147// leave the Hi part unset.
2148std::pair<SDValue, SDValue>
2149SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2150 TargetLowering::ArgListTy &&Args,
2151 bool IsSigned, EVT RetVT) {
2152 EVT CodePtrTy = TLI.getPointerTy(DL: DAG.getDataLayout());
2153 SDValue Callee;
2154 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
2155 if (LCImpl != RTLIB::Unsupported)
2156 Callee = DAG.getExternalSymbol(LCImpl, VT: CodePtrTy);
2157 else {
2158 Callee = DAG.getPOISON(VT: CodePtrTy);
2159 DAG.getContext()->emitError(ErrorStr: Twine("no libcall available for ") +
2160 Node->getOperationName(G: &DAG));
2161 }
2162
2163 Type *RetTy = RetVT.getTypeForEVT(Context&: *DAG.getContext());
2164
2165 // By default, the input chain to this libcall is the entry node of the
2166 // function. If the libcall is going to be emitted as a tail call then
2167 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2168 // node which is being folded has a non-entry input chain.
2169 SDValue InChain = DAG.getEntryNode();
2170
2171 // isTailCall may be true since the callee does not reference caller stack
2172 // frame. Check if it's in the right position and that the return types match.
2173 SDValue TCChain = InChain;
2174 const Function &F = DAG.getMachineFunction().getFunction();
2175 bool isTailCall =
2176 TLI.isInTailCallPosition(DAG, Node, Chain&: TCChain) &&
2177 (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2178 if (isTailCall)
2179 InChain = TCChain;
2180
2181 TargetLowering::CallLoweringInfo CLI(DAG);
2182 bool signExtend = TLI.shouldSignExtendTypeInLibCall(Ty: RetTy, IsSigned);
2183 CLI.setDebugLoc(SDLoc(Node))
2184 .setChain(InChain)
2185 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
2186 Target: Callee, ArgsList: std::move(Args))
2187 .setTailCall(isTailCall)
2188 .setSExtResult(signExtend)
2189 .setZExtResult(!signExtend)
2190 .setIsPostTypeLegalization(true);
2191
2192 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2193
2194 if (!CallInfo.second.getNode()) {
2195 LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump(&DAG));
2196 // It's a tailcall, return the chain (which is the DAG root).
2197 return {DAG.getRoot(), DAG.getRoot()};
2198 }
2199
2200 LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump(&DAG));
2201 return CallInfo;
2202}
2203
2204std::pair<SDValue, SDValue> SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2205 bool isSigned) {
2206 TargetLowering::ArgListTy Args;
2207 for (const SDValue &Op : Node->op_values()) {
2208 EVT ArgVT = Op.getValueType();
2209 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2210 TargetLowering::ArgListEntry Entry(Op, ArgTy);
2211 Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(Ty: ArgTy, IsSigned: isSigned);
2212 Entry.IsZExt = !Entry.IsSExt;
2213 Args.push_back(x: Entry);
2214 }
2215
2216 return ExpandLibCall(LC, Node, Args: std::move(Args), IsSigned: isSigned,
2217 RetVT: Node->getValueType(ResNo: 0));
2218}
2219
2220void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2221 RTLIB::Libcall LC,
2222 SmallVectorImpl<SDValue> &Results) {
2223 if (LC == RTLIB::UNKNOWN_LIBCALL)
2224 llvm_unreachable("Can't create an unknown libcall!");
2225
2226 if (Node->isStrictFPOpcode()) {
2227 EVT RetVT = Node->getValueType(ResNo: 0);
2228 SmallVector<SDValue, 4> Ops(drop_begin(RangeOrContainer: Node->ops()));
2229 TargetLowering::MakeLibCallOptions CallOptions;
2230 CallOptions.IsPostTypeLegalization = true;
2231 // FIXME: This doesn't support tail calls.
2232 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2233 Ops, CallOptions,
2234 dl: SDLoc(Node),
2235 Chain: Node->getOperand(Num: 0));
2236 Results.push_back(Elt: Tmp.first);
2237 Results.push_back(Elt: Tmp.second);
2238 } else {
2239 bool IsSignedArgument = Node->getOpcode() == ISD::FLDEXP;
2240 SDValue Tmp = ExpandLibCall(LC, Node, isSigned: IsSignedArgument).first;
2241 Results.push_back(Elt: Tmp);
2242 }
2243}
2244
2245/// Expand the node to a libcall based on the result type.
2246void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2247 RTLIB::Libcall Call_F32,
2248 RTLIB::Libcall Call_F64,
2249 RTLIB::Libcall Call_F80,
2250 RTLIB::Libcall Call_F128,
2251 RTLIB::Libcall Call_PPCF128,
2252 SmallVectorImpl<SDValue> &Results) {
2253 RTLIB::Libcall LC = RTLIB::getFPLibCall(VT: Node->getSimpleValueType(ResNo: 0),
2254 Call_F32, Call_F64, Call_F80,
2255 Call_F128, Call_PPCF128);
2256 ExpandFPLibCall(Node, LC, Results);
2257}
2258
2259void SelectionDAGLegalize::ExpandFastFPLibCall(
2260 SDNode *Node, bool IsFast,
2261 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_F32,
2262 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_F64,
2263 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_F80,
2264 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_F128,
2265 std::pair<RTLIB::Libcall, RTLIB::Libcall> Call_PPCF128,
2266 SmallVectorImpl<SDValue> &Results) {
2267
2268 EVT VT = Node->getSimpleValueType(ResNo: 0);
2269
2270 RTLIB::Libcall LC;
2271
2272 // FIXME: Probably should define fast to respect nan/inf and only be
2273 // approximate functions.
2274
2275 if (IsFast) {
2276 LC = RTLIB::getFPLibCall(VT, Call_F32: Call_F32.first, Call_F64: Call_F64.first, Call_F80: Call_F80.first,
2277 Call_F128: Call_F128.first, Call_PPCF128: Call_PPCF128.first);
2278 }
2279
2280 if (!IsFast || DAG.getLibcalls().getLibcallImpl(Call: LC) == RTLIB::Unsupported) {
2281 // Fall back if we don't have a fast implementation.
2282 LC = RTLIB::getFPLibCall(VT, Call_F32: Call_F32.second, Call_F64: Call_F64.second,
2283 Call_F80: Call_F80.second, Call_F128: Call_F128.second,
2284 Call_PPCF128: Call_PPCF128.second);
2285 }
2286
2287 ExpandFPLibCall(Node, LC, Results);
2288}
2289
2290SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2291 RTLIB::Libcall Call_I8,
2292 RTLIB::Libcall Call_I16,
2293 RTLIB::Libcall Call_I32,
2294 RTLIB::Libcall Call_I64,
2295 RTLIB::Libcall Call_I128) {
2296 RTLIB::Libcall LC;
2297 switch (Node->getSimpleValueType(ResNo: 0).SimpleTy) {
2298 default: llvm_unreachable("Unexpected request for libcall!");
2299 case MVT::i8: LC = Call_I8; break;
2300 case MVT::i16: LC = Call_I16; break;
2301 case MVT::i32: LC = Call_I32; break;
2302 case MVT::i64: LC = Call_I64; break;
2303 case MVT::i128: LC = Call_I128; break;
2304 }
2305 return ExpandLibCall(LC, Node, isSigned).first;
2306}
2307
2308/// Expand the node to a libcall based on first argument type (for instance
2309/// lround and its variant).
2310void SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
2311 RTLIB::Libcall Call_F32,
2312 RTLIB::Libcall Call_F64,
2313 RTLIB::Libcall Call_F80,
2314 RTLIB::Libcall Call_F128,
2315 RTLIB::Libcall Call_PPCF128,
2316 SmallVectorImpl<SDValue> &Results) {
2317 EVT InVT = Node->getOperand(Num: Node->isStrictFPOpcode() ? 1 : 0).getValueType();
2318 RTLIB::Libcall LC = RTLIB::getFPLibCall(VT: InVT.getSimpleVT(),
2319 Call_F32, Call_F64, Call_F80,
2320 Call_F128, Call_PPCF128);
2321 ExpandFPLibCall(Node, LC, Results);
2322}
2323
2324SDValue SelectionDAGLegalize::ExpandBitCountingLibCall(
2325 SDNode *Node, RTLIB::Libcall CallI32, RTLIB::Libcall CallI64,
2326 RTLIB::Libcall CallI128) {
2327 RTLIB::Libcall LC;
2328 switch (Node->getSimpleValueType(ResNo: 0).SimpleTy) {
2329 default:
2330 llvm_unreachable("Unexpected request for libcall!");
2331 case MVT::i32:
2332 LC = CallI32;
2333 break;
2334 case MVT::i64:
2335 LC = CallI64;
2336 break;
2337 case MVT::i128:
2338 LC = CallI128;
2339 break;
2340 }
2341
2342 // Bit-counting libcalls have one unsigned argument and return `int`.
2343 // Note that `int` may be illegal on this target; ExpandLibCall will
2344 // take care of promoting it to a legal type.
2345 SDValue Op = Node->getOperand(Num: 0);
2346 EVT IntVT =
2347 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
2348
2349 EVT ArgVT = Op.getValueType();
2350 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2351 TargetLowering::ArgListEntry Arg(Op, ArgTy);
2352 Arg.IsSExt = TLI.shouldSignExtendTypeInLibCall(Ty: ArgTy, /*IsSigned=*/false);
2353 Arg.IsZExt = !Arg.IsSExt;
2354
2355 SDValue Res = ExpandLibCall(LC, Node, Args: TargetLowering::ArgListTy{Arg},
2356 /*IsSigned=*/true, RetVT: IntVT)
2357 .first;
2358
2359 // If ExpandLibCall created a tail call, the result was already
2360 // of the correct type. Otherwise, we need to sign extend it.
2361 if (Res.getValueType() != MVT::Other)
2362 Res = DAG.getSExtOrTrunc(Op: Res, DL: SDLoc(Node), VT: Node->getValueType(ResNo: 0));
2363 return Res;
2364}
2365
2366/// Issue libcalls to __{u}divmod to compute div / rem pairs.
2367void
2368SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2369 SmallVectorImpl<SDValue> &Results) {
2370 unsigned Opcode = Node->getOpcode();
2371 bool isSigned = Opcode == ISD::SDIVREM;
2372
2373 RTLIB::Libcall LC;
2374 switch (Node->getSimpleValueType(ResNo: 0).SimpleTy) {
2375 default: llvm_unreachable("Unexpected request for libcall!");
2376 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2377 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2378 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2379 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2380 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2381 }
2382
2383 // The input chain to this libcall is the entry node of the function.
2384 // Legalizing the call will automatically add the previous call to the
2385 // dependence.
2386 SDValue InChain = DAG.getEntryNode();
2387
2388 EVT RetVT = Node->getValueType(ResNo: 0);
2389 Type *RetTy = RetVT.getTypeForEVT(Context&: *DAG.getContext());
2390
2391 TargetLowering::ArgListTy Args;
2392 for (const SDValue &Op : Node->op_values()) {
2393 EVT ArgVT = Op.getValueType();
2394 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2395 TargetLowering::ArgListEntry Entry(Op, ArgTy);
2396 Entry.IsSExt = isSigned;
2397 Entry.IsZExt = !isSigned;
2398 Args.push_back(x: Entry);
2399 }
2400
2401 // Also pass the return address of the remainder.
2402 SDValue FIPtr = DAG.CreateStackTemporary(VT: RetVT);
2403 TargetLowering::ArgListEntry Entry(
2404 FIPtr, PointerType::getUnqual(C&: RetTy->getContext()));
2405 Entry.IsSExt = isSigned;
2406 Entry.IsZExt = !isSigned;
2407 Args.push_back(x: Entry);
2408
2409 RTLIB::LibcallImpl LibcallImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
2410 if (LibcallImpl == RTLIB::Unsupported) {
2411 DAG.getContext()->emitError(ErrorStr: Twine("no libcall available for ") +
2412 Node->getOperationName(G: &DAG));
2413 SDValue Poison = DAG.getPOISON(VT: RetVT);
2414 Results.push_back(Elt: Poison);
2415 Results.push_back(Elt: Poison);
2416 return;
2417 }
2418
2419 SDValue Callee =
2420 DAG.getExternalSymbol(LCImpl: LibcallImpl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
2421
2422 SDLoc dl(Node);
2423 TargetLowering::CallLoweringInfo CLI(DAG);
2424 CLI.setDebugLoc(dl)
2425 .setChain(InChain)
2426 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LibcallImpl),
2427 ResultType: RetTy, Target: Callee, ArgsList: std::move(Args))
2428 .setSExtResult(isSigned)
2429 .setZExtResult(!isSigned);
2430
2431 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2432
2433 // Remainder is loaded back from the stack frame.
2434 int FI = cast<FrameIndexSDNode>(Val&: FIPtr)->getIndex();
2435 MachinePointerInfo PtrInfo =
2436 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI);
2437
2438 SDValue Rem = DAG.getLoad(VT: RetVT, dl, Chain: CallInfo.second, Ptr: FIPtr, PtrInfo);
2439 Results.push_back(Elt: CallInfo.first);
2440 Results.push_back(Elt: Rem);
2441}
2442
2443/// Return true if sincos or __sincos_stret libcall is available.
2444static bool isSinCosLibcallAvailable(SDNode *Node,
2445 const LibcallLoweringInfo &Libcalls) {
2446 MVT::SimpleValueType VT = Node->getSimpleValueType(ResNo: 0).SimpleTy;
2447 return Libcalls.getLibcallImpl(Call: RTLIB::getSINCOS(RetVT: VT)) != RTLIB::Unsupported ||
2448 Libcalls.getLibcallImpl(Call: RTLIB::getSINCOS_STRET(RetVT: VT)) !=
2449 RTLIB::Unsupported;
2450}
2451
2452/// Only issue sincos libcall if both sin and cos are needed.
2453static bool useSinCos(SDNode *Node) {
2454 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2455 ? ISD::FCOS : ISD::FSIN;
2456
2457 SDValue Op0 = Node->getOperand(Num: 0);
2458 for (const SDNode *User : Op0.getNode()->users()) {
2459 if (User == Node)
2460 continue;
2461 // The other user might have been turned into sincos already.
2462 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2463 return true;
2464 }
2465 return false;
2466}
2467
2468SDValue SelectionDAGLegalize::ExpandSincosStretLibCall(SDNode *Node) const {
2469 // For iOS, we want to call an alternative entry point: __sincos_stret,
2470 // which returns the values in two S / D registers.
2471 SDLoc dl(Node);
2472 SDValue Arg = Node->getOperand(Num: 0);
2473 EVT ArgVT = Arg.getValueType();
2474 RTLIB::Libcall LC = RTLIB::getSINCOS_STRET(RetVT: ArgVT);
2475 RTLIB::LibcallImpl SincosStret = DAG.getLibcalls().getLibcallImpl(Call: LC);
2476 if (SincosStret == RTLIB::Unsupported)
2477 return SDValue();
2478
2479 /// There are 3 different ABI cases to handle:
2480 /// - Direct return of separate fields in registers
2481 /// - Single return as vector elements
2482 /// - sret struct
2483
2484 const RTLIB::RuntimeLibcallsInfo &CallsInfo = TLI.getRuntimeLibcallsInfo();
2485
2486 const DataLayout &DL = DAG.getDataLayout();
2487
2488 auto [FuncTy, FuncAttrs] = CallsInfo.getFunctionTy(
2489 Ctx&: *DAG.getContext(), TT: TM.getTargetTriple(), DL, LibcallImpl: SincosStret);
2490
2491 Type *SincosStretRetTy = FuncTy->getReturnType();
2492 CallingConv::ID CallConv = CallsInfo.getLibcallImplCallingConv(Call: SincosStret);
2493
2494 SDValue Callee =
2495 DAG.getExternalSymbol(LCImpl: SincosStret, VT: TLI.getProgramPointerTy(DL));
2496
2497 TargetLowering::ArgListTy Args;
2498 SDValue SRet;
2499
2500 int FrameIdx;
2501 if (FuncTy->getParamType(i: 0)->isPointerTy()) {
2502 // Uses sret
2503 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2504
2505 AttributeSet PtrAttrs = FuncAttrs.getParamAttrs(ArgNo: 0);
2506 Type *StructTy = PtrAttrs.getStructRetType();
2507 const uint64_t ByteSize = DL.getTypeAllocSize(Ty: StructTy);
2508 const Align StackAlign = DL.getPrefTypeAlign(Ty: StructTy);
2509
2510 FrameIdx = MFI.CreateStackObject(Size: ByteSize, Alignment: StackAlign, isSpillSlot: false);
2511 SRet = DAG.getFrameIndex(FI: FrameIdx, VT: TLI.getFrameIndexTy(DL));
2512
2513 TargetLowering::ArgListEntry Entry(SRet, FuncTy->getParamType(i: 0));
2514 Entry.IsSRet = true;
2515 Entry.IndirectType = StructTy;
2516 Entry.Alignment = StackAlign;
2517
2518 Args.push_back(x: Entry);
2519 Args.emplace_back(args&: Arg, args: FuncTy->getParamType(i: 1));
2520 } else {
2521 Args.emplace_back(args&: Arg, args: FuncTy->getParamType(i: 0));
2522 }
2523
2524 TargetLowering::CallLoweringInfo CLI(DAG);
2525 CLI.setDebugLoc(dl)
2526 .setChain(DAG.getEntryNode())
2527 .setLibCallee(CC: CallConv, ResultType: SincosStretRetTy, Target: Callee, ArgsList: std::move(Args))
2528 .setIsPostTypeLegalization();
2529
2530 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2531
2532 if (SRet) {
2533 MachinePointerInfo PtrInfo =
2534 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: FrameIdx);
2535 SDValue LoadSin = DAG.getLoad(VT: ArgVT, dl, Chain: CallResult.second, Ptr: SRet, PtrInfo);
2536
2537 TypeSize StoreSize = ArgVT.getStoreSize();
2538
2539 // Address of cos field.
2540 SDValue Add = DAG.getObjectPtrOffset(SL: dl, Ptr: SRet, Offset: StoreSize);
2541 SDValue LoadCos = DAG.getLoad(VT: ArgVT, dl, Chain: LoadSin.getValue(R: 1), Ptr: Add,
2542 PtrInfo: PtrInfo.getWithOffset(O: StoreSize));
2543
2544 SDVTList Tys = DAG.getVTList(VT1: ArgVT, VT2: ArgVT);
2545 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: dl, VTList: Tys, N1: LoadSin.getValue(R: 0),
2546 N2: LoadCos.getValue(R: 0));
2547 }
2548
2549 if (!CallResult.first.getValueType().isVector())
2550 return CallResult.first;
2551
2552 SDValue SinVal =
2553 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: ArgVT, N1: CallResult.first,
2554 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
2555 SDValue CosVal =
2556 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: ArgVT, N1: CallResult.first,
2557 N2: DAG.getVectorIdxConstant(Val: 1, DL: dl));
2558 SDVTList Tys = DAG.getVTList(VT1: ArgVT, VT2: ArgVT);
2559 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: dl, VTList: Tys, N1: SinVal, N2: CosVal);
2560}
2561
2562SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
2563 SDLoc dl(Node);
2564 EVT VT = Node->getValueType(ResNo: 0);
2565 SDValue X = Node->getOperand(Num: 0);
2566 SDValue N = Node->getOperand(Num: 1);
2567 EVT ExpVT = N.getValueType();
2568 EVT AsIntVT = VT.changeTypeToInteger();
2569 if (AsIntVT == EVT()) // TODO: How to handle f80?
2570 return SDValue();
2571
2572 if (Node->getOpcode() == ISD::STRICT_FLDEXP) // TODO
2573 return SDValue();
2574
2575 SDNodeFlags NSW;
2576 NSW.setNoSignedWrap(true);
2577 SDNodeFlags NUW_NSW;
2578 NUW_NSW.setNoUnsignedWrap(true);
2579 NUW_NSW.setNoSignedWrap(true);
2580
2581 EVT SetCCVT =
2582 TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT: ExpVT);
2583 const fltSemantics &FltSem = VT.getFltSemantics();
2584
2585 const APFloat::ExponentType MaxExpVal = APFloat::semanticsMaxExponent(FltSem);
2586 const APFloat::ExponentType MinExpVal = APFloat::semanticsMinExponent(FltSem);
2587 const int Precision = APFloat::semanticsPrecision(FltSem);
2588
2589 const SDValue MaxExp = DAG.getSignedConstant(Val: MaxExpVal, DL: dl, VT: ExpVT);
2590 const SDValue MinExp = DAG.getSignedConstant(Val: MinExpVal, DL: dl, VT: ExpVT);
2591
2592 const SDValue DoubleMaxExp = DAG.getSignedConstant(Val: 2 * MaxExpVal, DL: dl, VT: ExpVT);
2593
2594 const APFloat One(FltSem, "1.0");
2595 APFloat ScaleUpK = scalbn(X: One, Exp: MaxExpVal, RM: APFloat::rmNearestTiesToEven);
2596
2597 // Offset by precision to avoid denormal range.
2598 APFloat ScaleDownK =
2599 scalbn(X: One, Exp: MinExpVal + Precision, RM: APFloat::rmNearestTiesToEven);
2600
2601 // TODO: Should really introduce control flow and use a block for the >
2602 // MaxExp, < MinExp cases
2603
2604 // First, handle exponents Exp > MaxExp and scale down.
2605 SDValue NGtMaxExp = DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: N, RHS: MaxExp, Cond: ISD::SETGT);
2606
2607 SDValue DecN0 = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ExpVT, N1: N, N2: MaxExp, Flags: NSW);
2608 SDValue ClampMaxVal = DAG.getConstant(Val: 3 * MaxExpVal, DL: dl, VT: ExpVT);
2609 SDValue ClampN_Big = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT: ExpVT, N1: N, N2: ClampMaxVal);
2610 SDValue DecN1 =
2611 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ExpVT, N1: ClampN_Big, N2: DoubleMaxExp, Flags: NSW);
2612
2613 SDValue ScaleUpTwice =
2614 DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: N, RHS: DoubleMaxExp, Cond: ISD::SETUGT);
2615
2616 const SDValue ScaleUpVal = DAG.getConstantFP(Val: ScaleUpK, DL: dl, VT);
2617 SDValue ScaleUp0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: X, N2: ScaleUpVal);
2618 SDValue ScaleUp1 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: ScaleUp0, N2: ScaleUpVal);
2619
2620 SDValue SelectN_Big =
2621 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: ScaleUpTwice, N2: DecN1, N3: DecN0);
2622 SDValue SelectX_Big =
2623 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT, N1: ScaleUpTwice, N2: ScaleUp1, N3: ScaleUp0);
2624
2625 // Now handle exponents Exp < MinExp
2626 SDValue NLtMinExp = DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: N, RHS: MinExp, Cond: ISD::SETLT);
2627
2628 SDValue Increment0 = DAG.getConstant(Val: -(MinExpVal + Precision), DL: dl, VT: ExpVT);
2629 SDValue Increment1 = DAG.getConstant(Val: -2 * (MinExpVal + Precision), DL: dl, VT: ExpVT);
2630
2631 SDValue IncN0 = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: N, N2: Increment0, Flags: NUW_NSW);
2632
2633 SDValue ClampMinVal =
2634 DAG.getSignedConstant(Val: 3 * MinExpVal + 2 * Precision, DL: dl, VT: ExpVT);
2635 SDValue ClampN_Small = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT: ExpVT, N1: N, N2: ClampMinVal);
2636 SDValue IncN1 =
2637 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: ClampN_Small, N2: Increment1, Flags: NSW);
2638
2639 const SDValue ScaleDownVal = DAG.getConstantFP(Val: ScaleDownK, DL: dl, VT);
2640 SDValue ScaleDown0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: X, N2: ScaleDownVal);
2641 SDValue ScaleDown1 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: ScaleDown0, N2: ScaleDownVal);
2642
2643 SDValue ScaleDownTwice = DAG.getSetCC(
2644 DL: dl, VT: SetCCVT, LHS: N,
2645 RHS: DAG.getSignedConstant(Val: 2 * MinExpVal + Precision, DL: dl, VT: ExpVT), Cond: ISD::SETULT);
2646
2647 SDValue SelectN_Small =
2648 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: ScaleDownTwice, N2: IncN1, N3: IncN0);
2649 SDValue SelectX_Small =
2650 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT, N1: ScaleDownTwice, N2: ScaleDown1, N3: ScaleDown0);
2651
2652 // Now combine the two out of range exponent handling cases with the base
2653 // case.
2654 SDValue NewX = DAG.getNode(
2655 Opcode: ISD::SELECT, DL: dl, VT, N1: NGtMaxExp, N2: SelectX_Big,
2656 N3: DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT, N1: NLtMinExp, N2: SelectX_Small, N3: X));
2657
2658 SDValue NewN = DAG.getNode(
2659 Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: NGtMaxExp, N2: SelectN_Big,
2660 N3: DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: NLtMinExp, N2: SelectN_Small, N3: N));
2661
2662 SDValue BiasedN = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: NewN, N2: MaxExp, Flags: NSW);
2663
2664 SDValue ExponentShiftAmt =
2665 DAG.getShiftAmountConstant(Val: Precision - 1, VT: ExpVT, DL: dl);
2666 SDValue CastExpToValTy = DAG.getZExtOrTrunc(Op: BiasedN, DL: dl, VT: AsIntVT);
2667
2668 SDValue AsInt = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: AsIntVT, N1: CastExpToValTy,
2669 N2: ExponentShiftAmt, Flags: NUW_NSW);
2670 SDValue AsFP = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: AsInt);
2671 return DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: NewX, N2: AsFP);
2672}
2673
2674SDValue SelectionDAGLegalize::expandFrexp(SDNode *Node) const {
2675 SDLoc dl(Node);
2676 SDValue Val = Node->getOperand(Num: 0);
2677 EVT VT = Val.getValueType();
2678 EVT ExpVT = Node->getValueType(ResNo: 1);
2679 EVT AsIntVT = VT.changeTypeToInteger();
2680 if (AsIntVT == EVT()) // TODO: How to handle f80?
2681 return SDValue();
2682
2683 const fltSemantics &FltSem = VT.getFltSemantics();
2684 const APFloat::ExponentType MinExpVal = APFloat::semanticsMinExponent(FltSem);
2685 const unsigned Precision = APFloat::semanticsPrecision(FltSem);
2686 const unsigned BitSize = VT.getScalarSizeInBits();
2687
2688 // TODO: Could introduce control flow and skip over the denormal handling.
2689
2690 // scale_up = fmul value, scalbn(1.0, precision + 1)
2691 // extracted_exp = (bitcast value to uint) >> precision - 1
2692 // biased_exp = extracted_exp + min_exp
2693 // extracted_fract = (bitcast value to uint) & (fract_mask | sign_mask)
2694 //
2695 // is_denormal = val < smallest_normalized
2696 // computed_fract = is_denormal ? scale_up : extracted_fract
2697 // computed_exp = is_denormal ? biased_exp + (-precision - 1) : biased_exp
2698 //
2699 // result_0 = (!isfinite(val) || iszero(val)) ? val : computed_fract
2700 // result_1 = (!isfinite(val) || iszero(val)) ? 0 : computed_exp
2701
2702 SDValue NegSmallestNormalizedInt = DAG.getConstant(
2703 Val: APFloat::getSmallestNormalized(Sem: FltSem, Negative: true).bitcastToAPInt(), DL: dl,
2704 VT: AsIntVT);
2705
2706 SDValue SmallestNormalizedInt = DAG.getConstant(
2707 Val: APFloat::getSmallestNormalized(Sem: FltSem, Negative: false).bitcastToAPInt(), DL: dl,
2708 VT: AsIntVT);
2709
2710 // Masks out the exponent bits.
2711 SDValue ExpMask =
2712 DAG.getConstant(Val: APFloat::getInf(Sem: FltSem).bitcastToAPInt(), DL: dl, VT: AsIntVT);
2713
2714 // Mask out the exponent part of the value.
2715 //
2716 // e.g, for f32 FractSignMaskVal = 0x807fffff
2717 APInt FractSignMaskVal = APInt::getBitsSet(numBits: BitSize, loBit: 0, hiBit: Precision - 1);
2718 FractSignMaskVal.setBit(BitSize - 1); // Set the sign bit
2719
2720 APInt SignMaskVal = APInt::getSignedMaxValue(numBits: BitSize);
2721 SDValue SignMask = DAG.getConstant(Val: SignMaskVal, DL: dl, VT: AsIntVT);
2722
2723 SDValue FractSignMask = DAG.getConstant(Val: FractSignMaskVal, DL: dl, VT: AsIntVT);
2724
2725 const APFloat One(FltSem, "1.0");
2726 // Scale a possible denormal input.
2727 // e.g., for f64, 0x1p+54
2728 APFloat ScaleUpKVal =
2729 scalbn(X: One, Exp: Precision + 1, RM: APFloat::rmNearestTiesToEven);
2730
2731 SDValue ScaleUpK = DAG.getConstantFP(Val: ScaleUpKVal, DL: dl, VT);
2732 SDValue ScaleUp = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: Val, N2: ScaleUpK);
2733
2734 EVT SetCCVT =
2735 TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT);
2736
2737 SDValue AsInt = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: AsIntVT, Operand: Val);
2738
2739 SDValue Abs = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AsIntVT, N1: AsInt, N2: SignMask);
2740
2741 SDValue AddNegSmallestNormal =
2742 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: AsIntVT, N1: Abs, N2: NegSmallestNormalizedInt);
2743 SDValue DenormOrZero = DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: AddNegSmallestNormal,
2744 RHS: NegSmallestNormalizedInt, Cond: ISD::SETULE);
2745
2746 SDValue IsDenormal =
2747 DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: Abs, RHS: SmallestNormalizedInt, Cond: ISD::SETULT);
2748
2749 SDValue MinExp = DAG.getSignedConstant(Val: MinExpVal, DL: dl, VT: ExpVT);
2750 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: ExpVT);
2751
2752 SDValue ScaledAsInt = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: AsIntVT, Operand: ScaleUp);
2753 SDValue ScaledSelect =
2754 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: AsIntVT, N1: IsDenormal, N2: ScaledAsInt, N3: AsInt);
2755
2756 SDValue ExpMaskScaled =
2757 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AsIntVT, N1: ScaledAsInt, N2: ExpMask);
2758
2759 SDValue ScaledValue =
2760 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: AsIntVT, N1: IsDenormal, N2: ExpMaskScaled, N3: Abs);
2761
2762 // Extract the exponent bits.
2763 SDValue ExponentShiftAmt =
2764 DAG.getShiftAmountConstant(Val: Precision - 1, VT: AsIntVT, DL: dl);
2765 SDValue ShiftedExp =
2766 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: AsIntVT, N1: ScaledValue, N2: ExponentShiftAmt);
2767 SDValue Exp = DAG.getSExtOrTrunc(Op: ShiftedExp, DL: dl, VT: ExpVT);
2768
2769 SDValue NormalBiasedExp = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: Exp, N2: MinExp);
2770 SDValue DenormalOffset = DAG.getConstant(Val: -Precision - 1, DL: dl, VT: ExpVT);
2771 SDValue DenormalExpBias =
2772 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: IsDenormal, N2: DenormalOffset, N3: Zero);
2773
2774 SDValue MaskedFractAsInt =
2775 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AsIntVT, N1: ScaledSelect, N2: FractSignMask);
2776 const APFloat Half(FltSem, "0.5");
2777 SDValue FPHalf = DAG.getConstant(Val: Half.bitcastToAPInt(), DL: dl, VT: AsIntVT);
2778 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: AsIntVT, N1: MaskedFractAsInt, N2: FPHalf);
2779 SDValue MaskedFract = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Or);
2780
2781 SDValue ComputedExp =
2782 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: NormalBiasedExp, N2: DenormalExpBias);
2783
2784 SDValue Result0 =
2785 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT, N1: DenormOrZero, N2: Val, N3: MaskedFract);
2786
2787 SDValue Result1 =
2788 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: DenormOrZero, N2: Zero, N3: ComputedExp);
2789
2790 return DAG.getMergeValues(Ops: {Result0, Result1}, dl);
2791}
2792
2793SDValue SelectionDAGLegalize::expandModf(SDNode *Node) const {
2794 SDLoc dl(Node);
2795 SDValue Val = Node->getOperand(Num: 0);
2796 EVT VT = Val.getValueType();
2797 SDNodeFlags Flags = Node->getFlags();
2798
2799 SDValue IntPart = DAG.getNode(Opcode: ISD::FTRUNC, DL: dl, VT, Operand: Val, Flags);
2800 SDValue FracPart = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT, N1: Val, N2: IntPart, Flags);
2801
2802 SDValue FracToUse;
2803 if (Flags.hasNoInfs()) {
2804 FracToUse = FracPart;
2805 } else {
2806 SDValue Abs = DAG.getNode(Opcode: ISD::FABS, DL: dl, VT, Operand: Val, Flags);
2807 SDValue Inf =
2808 DAG.getConstantFP(Val: APFloat::getInf(Sem: VT.getFltSemantics()), DL: dl, VT);
2809 EVT SetCCVT =
2810 TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT);
2811 SDValue IsInf = DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: Abs, RHS: Inf, Cond: ISD::SETOEQ);
2812 SDValue Zero = DAG.getConstantFP(Val: 0.0, DL: dl, VT);
2813 FracToUse = DAG.getSelect(DL: dl, VT, Cond: IsInf, LHS: Zero, RHS: FracPart);
2814 }
2815
2816 SDValue ResultFrac =
2817 DAG.getNode(Opcode: ISD::FCOPYSIGN, DL: dl, VT, N1: FracToUse, N2: Val, Flags);
2818 return DAG.getMergeValues(Ops: {ResultFrac, IntPart}, dl);
2819}
2820
2821/// This function is responsible for legalizing a
2822/// INT_TO_FP operation of the specified operand when the target requests that
2823/// we expand it. At this point, we know that the result and operand types are
2824/// legal for the target.
2825SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node,
2826 SDValue &Chain) {
2827 bool isSigned = (Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
2828 Node->getOpcode() == ISD::SINT_TO_FP);
2829 EVT DestVT = Node->getValueType(ResNo: 0);
2830 SDLoc dl(Node);
2831 unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0;
2832 SDValue Op0 = Node->getOperand(Num: OpNo);
2833 EVT SrcVT = Op0.getValueType();
2834
2835 // TODO: Should any fast-math-flags be set for the created nodes?
2836 LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2837 if (SrcVT == MVT::i32 && TLI.isTypeLegal(VT: MVT::f64) &&
2838 (DestVT.bitsLE(VT: MVT::f64) ||
2839 TLI.isOperationLegal(Op: Node->isStrictFPOpcode() ? ISD::STRICT_FP_EXTEND
2840 : ISD::FP_EXTEND,
2841 VT: DestVT))) {
2842 LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2843 "expansion\n");
2844
2845 // Get the stack frame index of a 8 byte buffer.
2846 SDValue StackSlot = DAG.CreateStackTemporary(VT: MVT::f64);
2847
2848 SDValue Lo = Op0;
2849 // if signed map to unsigned space
2850 if (isSigned) {
2851 // Invert sign bit (signed to unsigned mapping).
2852 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: MVT::i32, N1: Lo,
2853 N2: DAG.getConstant(Val: 0x80000000u, DL: dl, VT: MVT::i32));
2854 }
2855 // Initial hi portion of constructed double.
2856 SDValue Hi = DAG.getConstant(Val: 0x43300000u, DL: dl, VT: MVT::i32);
2857
2858 // If this a big endian target, swap the lo and high data.
2859 if (DAG.getDataLayout().isBigEndian())
2860 std::swap(a&: Lo, b&: Hi);
2861
2862 SDValue MemChain = DAG.getEntryNode();
2863
2864 // Store the lo of the constructed double.
2865 SDValue Store1 = DAG.getStore(Chain: MemChain, dl, Val: Lo, Ptr: StackSlot,
2866 PtrInfo: MachinePointerInfo());
2867 // Store the hi of the constructed double.
2868 SDValue HiPtr =
2869 DAG.getMemBasePlusOffset(Base: StackSlot, Offset: TypeSize::getFixed(ExactSize: 4), DL: dl);
2870 SDValue Store2 =
2871 DAG.getStore(Chain: MemChain, dl, Val: Hi, Ptr: HiPtr, PtrInfo: MachinePointerInfo());
2872 MemChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Store1, N2: Store2);
2873
2874 // load the constructed double
2875 SDValue Load =
2876 DAG.getLoad(VT: MVT::f64, dl, Chain: MemChain, Ptr: StackSlot, PtrInfo: MachinePointerInfo());
2877 // FP constant to bias correct the final result
2878 SDValue Bias = DAG.getConstantFP(
2879 Val: isSigned ? llvm::bit_cast<double>(from: 0x4330000080000000ULL)
2880 : llvm::bit_cast<double>(from: 0x4330000000000000ULL),
2881 DL: dl, VT: MVT::f64);
2882 // Subtract the bias and get the final result.
2883 SDValue Sub;
2884 SDValue Result;
2885 if (Node->isStrictFPOpcode()) {
2886 Sub = DAG.getNode(Opcode: ISD::STRICT_FSUB, DL: dl, ResultTys: {MVT::f64, MVT::Other},
2887 Ops: {Node->getOperand(Num: 0), Load, Bias});
2888 Chain = Sub.getValue(R: 1);
2889 if (DestVT != Sub.getValueType()) {
2890 std::pair<SDValue, SDValue> ResultPair;
2891 ResultPair =
2892 DAG.getStrictFPExtendOrRound(Op: Sub, Chain, DL: dl, VT: DestVT);
2893 Result = ResultPair.first;
2894 Chain = ResultPair.second;
2895 }
2896 else
2897 Result = Sub;
2898 } else {
2899 Sub = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f64, N1: Load, N2: Bias);
2900 Result = DAG.getFPExtendOrRound(Op: Sub, DL: dl, VT: DestVT);
2901 }
2902 return Result;
2903 }
2904
2905 if (isSigned)
2906 return SDValue();
2907
2908 // TODO: Generalize this for use with other types.
2909 if (((SrcVT == MVT::i32 || SrcVT == MVT::i64) && DestVT == MVT::f32) ||
2910 (SrcVT == MVT::i64 && DestVT == MVT::f64)) {
2911 LLVM_DEBUG(dbgs() << "Converting unsigned i32/i64 to f32/f64\n");
2912 // For unsigned conversions, convert them to signed conversions using the
2913 // algorithm from the x86_64 __floatundisf in compiler_rt. That method
2914 // should be valid for i32->f32 as well.
2915
2916 // More generally this transform should be valid if there are 3 more bits
2917 // in the integer type than the significand. Rounding uses the first bit
2918 // after the width of the significand and the OR of all bits after that. So
2919 // we need to be able to OR the shifted out bit into one of the bits that
2920 // participate in the OR.
2921
2922 // TODO: This really should be implemented using a branch rather than a
2923 // select. We happen to get lucky and machinesink does the right
2924 // thing most of the time. This would be a good candidate for a
2925 // pseudo-op, or, even better, for whole-function isel.
2926 EVT SetCCVT = getSetCCResultType(VT: SrcVT);
2927
2928 SDValue SignBitTest = DAG.getSetCC(
2929 DL: dl, VT: SetCCVT, LHS: Op0, RHS: DAG.getConstant(Val: 0, DL: dl, VT: SrcVT), Cond: ISD::SETLT);
2930
2931 SDValue ShiftConst = DAG.getShiftAmountConstant(Val: 1, VT: SrcVT, DL: dl);
2932 SDValue Shr = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: SrcVT, N1: Op0, N2: ShiftConst);
2933 SDValue AndConst = DAG.getConstant(Val: 1, DL: dl, VT: SrcVT);
2934 SDValue And = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: SrcVT, N1: Op0, N2: AndConst);
2935 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: SrcVT, N1: And, N2: Shr);
2936
2937 SDValue Slow, Fast;
2938 if (Node->isStrictFPOpcode()) {
2939 // In strict mode, we must avoid spurious exceptions, and therefore
2940 // must make sure to only emit a single STRICT_SINT_TO_FP.
2941 SDValue InCvt = DAG.getSelect(DL: dl, VT: SrcVT, Cond: SignBitTest, LHS: Or, RHS: Op0);
2942 // The STRICT_SINT_TO_FP inherits the exception mode from the
2943 // incoming STRICT_UINT_TO_FP node; the STRICT_FADD node can
2944 // never raise any exception.
2945 SDNodeFlags Flags;
2946 Flags.setNoFPExcept(Node->getFlags().hasNoFPExcept());
2947 Fast = DAG.getNode(Opcode: ISD::STRICT_SINT_TO_FP, DL: dl, ResultTys: {DestVT, MVT::Other},
2948 Ops: {Node->getOperand(Num: 0), InCvt}, Flags);
2949 Flags.setNoFPExcept(true);
2950 Slow = DAG.getNode(Opcode: ISD::STRICT_FADD, DL: dl, ResultTys: {DestVT, MVT::Other},
2951 Ops: {Fast.getValue(R: 1), Fast, Fast}, Flags);
2952 Chain = Slow.getValue(R: 1);
2953 } else {
2954 SDValue SignCvt = DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: DestVT, Operand: Or);
2955 Slow = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: DestVT, N1: SignCvt, N2: SignCvt);
2956 Fast = DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: DestVT, Operand: Op0);
2957 }
2958
2959 return DAG.getSelect(DL: dl, VT: DestVT, Cond: SignBitTest, LHS: Slow, RHS: Fast);
2960 }
2961
2962 // Don't expand it if there isn't cheap fadd.
2963 if (!TLI.isOperationLegalOrCustom(
2964 Op: Node->isStrictFPOpcode() ? ISD::STRICT_FADD : ISD::FADD, VT: DestVT))
2965 return SDValue();
2966
2967 // The following optimization is valid only if every value in SrcVT (when
2968 // treated as signed) is representable in DestVT. Check that the mantissa
2969 // size of DestVT is >= than the number of bits in SrcVT -1.
2970 assert(APFloat::semanticsPrecision(DestVT.getFltSemantics()) >=
2971 SrcVT.getSizeInBits() - 1 &&
2972 "Cannot perform lossless SINT_TO_FP!");
2973
2974 SDValue Tmp1;
2975 if (Node->isStrictFPOpcode()) {
2976 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_SINT_TO_FP, DL: dl, ResultTys: { DestVT, MVT::Other },
2977 Ops: { Node->getOperand(Num: 0), Op0 });
2978 } else
2979 Tmp1 = DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: DestVT, Operand: Op0);
2980
2981 SDValue SignSet = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: SrcVT), LHS: Op0,
2982 RHS: DAG.getConstant(Val: 0, DL: dl, VT: SrcVT), Cond: ISD::SETLT);
2983 SDValue Zero = DAG.getIntPtrConstant(Val: 0, DL: dl),
2984 Four = DAG.getIntPtrConstant(Val: 4, DL: dl);
2985 SDValue CstOffset = DAG.getSelect(DL: dl, VT: Zero.getValueType(),
2986 Cond: SignSet, LHS: Four, RHS: Zero);
2987
2988 // If the sign bit of the integer is set, the large number will be treated
2989 // as a negative number. To counteract this, the dynamic code adds an
2990 // offset depending on the data type.
2991 uint64_t FF;
2992 switch (SrcVT.getSimpleVT().SimpleTy) {
2993 default:
2994 return SDValue();
2995 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2996 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2997 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2998 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2999 }
3000 if (DAG.getDataLayout().isLittleEndian())
3001 FF <<= 32;
3002 Constant *FudgeFactor = ConstantInt::get(
3003 Ty: Type::getInt64Ty(C&: *DAG.getContext()), V: FF);
3004
3005 SDValue CPIdx =
3006 DAG.getConstantPool(C: FudgeFactor, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
3007 Align Alignment = cast<ConstantPoolSDNode>(Val&: CPIdx)->getAlign();
3008 CPIdx = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: CPIdx.getValueType(), N1: CPIdx, N2: CstOffset);
3009 Alignment = commonAlignment(A: Alignment, Offset: 4);
3010 SDValue FudgeInReg;
3011 if (DestVT == MVT::f32)
3012 FudgeInReg = DAG.getLoad(
3013 VT: MVT::f32, dl, Chain: DAG.getEntryNode(), Ptr: CPIdx,
3014 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()),
3015 Alignment);
3016 else {
3017 SDValue Load = DAG.getExtLoad(
3018 ExtType: ISD::EXTLOAD, dl, VT: DestVT, Chain: DAG.getEntryNode(), Ptr: CPIdx,
3019 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()), MemVT: MVT::f32,
3020 Alignment);
3021 HandleSDNode Handle(Load);
3022 LegalizeOp(Node: Load.getNode());
3023 FudgeInReg = Handle.getValue();
3024 }
3025
3026 if (Node->isStrictFPOpcode()) {
3027 SDValue Result = DAG.getNode(Opcode: ISD::STRICT_FADD, DL: dl, ResultTys: { DestVT, MVT::Other },
3028 Ops: { Tmp1.getValue(R: 1), Tmp1, FudgeInReg });
3029 Chain = Result.getValue(R: 1);
3030 return Result;
3031 }
3032
3033 return DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: DestVT, N1: Tmp1, N2: FudgeInReg);
3034}
3035
3036/// This function is responsible for legalizing a
3037/// *INT_TO_FP operation of the specified operand when the target requests that
3038/// we promote it. At this point, we know that the result and operand types are
3039/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3040/// operation that takes a larger input.
3041void SelectionDAGLegalize::PromoteLegalINT_TO_FP(
3042 SDNode *N, const SDLoc &dl, SmallVectorImpl<SDValue> &Results) {
3043 bool IsStrict = N->isStrictFPOpcode();
3044 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
3045 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
3046 EVT DestVT = N->getValueType(ResNo: 0);
3047 SDValue LegalOp = N->getOperand(Num: IsStrict ? 1 : 0);
3048 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP;
3049 unsigned SIntOp = IsStrict ? ISD::STRICT_SINT_TO_FP : ISD::SINT_TO_FP;
3050
3051 // First step, figure out the appropriate *INT_TO_FP operation to use.
3052 EVT NewInTy = LegalOp.getValueType();
3053
3054 unsigned OpToUse = 0;
3055
3056 // Scan for the appropriate larger type to use.
3057 while (true) {
3058 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
3059 assert(NewInTy.isInteger() && "Ran out of possibilities!");
3060
3061 // If the target supports SINT_TO_FP of this type, use it.
3062 if (TLI.isOperationLegalOrCustom(Op: SIntOp, VT: NewInTy)) {
3063 OpToUse = SIntOp;
3064 break;
3065 }
3066 if (IsSigned)
3067 continue;
3068
3069 // If the target supports UINT_TO_FP of this type, use it.
3070 if (TLI.isOperationLegalOrCustom(Op: UIntOp, VT: NewInTy)) {
3071 OpToUse = UIntOp;
3072 break;
3073 }
3074
3075 // Otherwise, try a larger type.
3076 }
3077
3078 // Okay, we found the operation and type to use. Zero extend our input to the
3079 // desired type then run the operation on it.
3080 if (IsStrict) {
3081 SDValue Res =
3082 DAG.getNode(Opcode: OpToUse, DL: dl, ResultTys: {DestVT, MVT::Other},
3083 Ops: {N->getOperand(Num: 0),
3084 DAG.getNode(Opcode: IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
3085 DL: dl, VT: NewInTy, Operand: LegalOp)});
3086 Results.push_back(Elt: Res);
3087 Results.push_back(Elt: Res.getValue(R: 1));
3088 return;
3089 }
3090
3091 Results.push_back(
3092 Elt: DAG.getNode(Opcode: OpToUse, DL: dl, VT: DestVT,
3093 Operand: DAG.getNode(Opcode: IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
3094 DL: dl, VT: NewInTy, Operand: LegalOp)));
3095}
3096
3097/// This function is responsible for legalizing a
3098/// FP_TO_*INT operation of the specified operand when the target requests that
3099/// we promote it. At this point, we know that the result and operand types are
3100/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
3101/// operation that returns a larger result.
3102void SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
3103 SmallVectorImpl<SDValue> &Results) {
3104 bool IsStrict = N->isStrictFPOpcode();
3105 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
3106 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
3107 EVT DestVT = N->getValueType(ResNo: 0);
3108 SDValue LegalOp = N->getOperand(Num: IsStrict ? 1 : 0);
3109 // First step, figure out the appropriate FP_TO*INT operation to use.
3110 EVT NewOutTy = DestVT;
3111
3112 unsigned OpToUse = 0;
3113
3114 // Scan for the appropriate larger type to use.
3115 while (true) {
3116 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
3117 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
3118
3119 // A larger signed type can hold all unsigned values of the requested type,
3120 // so using FP_TO_SINT is valid
3121 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT;
3122 if (TLI.isOperationLegalOrCustom(Op: OpToUse, VT: NewOutTy))
3123 break;
3124
3125 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
3126 OpToUse = IsStrict ? ISD::STRICT_FP_TO_UINT : ISD::FP_TO_UINT;
3127 if (!IsSigned && TLI.isOperationLegalOrCustom(Op: OpToUse, VT: NewOutTy))
3128 break;
3129
3130 // Otherwise, try a larger type.
3131 }
3132
3133 // Okay, we found the operation and type to use.
3134 SDValue Operation;
3135 if (IsStrict) {
3136 SDVTList VTs = DAG.getVTList(VT1: NewOutTy, VT2: MVT::Other);
3137 Operation = DAG.getNode(Opcode: OpToUse, DL: dl, VTList: VTs, N1: N->getOperand(Num: 0), N2: LegalOp);
3138 } else
3139 Operation = DAG.getNode(Opcode: OpToUse, DL: dl, VT: NewOutTy, Operand: LegalOp);
3140
3141 // Truncate the result of the extended FP_TO_*INT operation to the desired
3142 // size.
3143 SDValue Trunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: DestVT, Operand: Operation);
3144 Results.push_back(Elt: Trunc);
3145 if (IsStrict)
3146 Results.push_back(Elt: Operation.getValue(R: 1));
3147}
3148
3149/// Promote FP_TO_*INT_SAT operation to a larger result type. At this point
3150/// the result and operand types are legal and there must be a legal
3151/// FP_TO_*INT_SAT operation for a larger result type.
3152SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT_SAT(SDNode *Node,
3153 const SDLoc &dl) {
3154 unsigned Opcode = Node->getOpcode();
3155
3156 // Scan for the appropriate larger type to use.
3157 EVT NewOutTy = Node->getValueType(ResNo: 0);
3158 while (true) {
3159 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy + 1);
3160 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
3161
3162 if (TLI.isOperationLegalOrCustom(Op: Opcode, VT: NewOutTy))
3163 break;
3164 }
3165
3166 // Saturation width is determined by second operand, so we don't have to
3167 // perform any fixup and can directly truncate the result.
3168 SDValue Result = DAG.getNode(Opcode, DL: dl, VT: NewOutTy, N1: Node->getOperand(Num: 0),
3169 N2: Node->getOperand(Num: 1));
3170 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Result);
3171}
3172
3173/// Open code the operations for PARITY of the specified operation.
3174SDValue SelectionDAGLegalize::ExpandPARITY(SDValue Op, const SDLoc &dl) {
3175 EVT VT = Op.getValueType();
3176 EVT ShVT = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
3177 unsigned Sz = VT.getScalarSizeInBits();
3178
3179 // If CTPOP is legal, use it. Otherwise use shifts and xor.
3180 SDValue Result;
3181 if (TLI.isOperationLegalOrPromote(Op: ISD::CTPOP, VT)) {
3182 Result = DAG.getNode(Opcode: ISD::CTPOP, DL: dl, VT, Operand: Op);
3183 } else {
3184 Result = Op;
3185 for (unsigned i = Log2_32_Ceil(Value: Sz); i != 0;) {
3186 SDValue Shift = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT, N1: Result,
3187 N2: DAG.getConstant(Val: 1ULL << (--i), DL: dl, VT: ShVT));
3188 Result = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: Result, N2: Shift);
3189 }
3190 }
3191
3192 return DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Result, N2: DAG.getConstant(Val: 1, DL: dl, VT));
3193}
3194
3195SDValue SelectionDAGLegalize::PromoteReduction(SDNode *Node) {
3196 bool IsVPOpcode = ISD::isVPOpcode(Opcode: Node->getOpcode());
3197 MVT VecVT = IsVPOpcode ? Node->getOperand(Num: 1).getSimpleValueType()
3198 : Node->getOperand(Num: 0).getSimpleValueType();
3199 MVT NewVecVT = TLI.getTypeToPromoteTo(Op: Node->getOpcode(), VT: VecVT);
3200 MVT ScalarVT = Node->getSimpleValueType(ResNo: 0);
3201 MVT NewScalarVT = NewVecVT.getVectorElementType();
3202
3203 SDLoc DL(Node);
3204 SmallVector<SDValue, 4> Operands(Node->getNumOperands());
3205
3206 // FIXME: Support integer.
3207 assert(Node->getOperand(0).getValueType().isFloatingPoint() &&
3208 "Only FP promotion is supported");
3209
3210 for (unsigned j = 0; j != Node->getNumOperands(); ++j)
3211 if (Node->getOperand(Num: j).getValueType().isVector() &&
3212 !(IsVPOpcode &&
3213 ISD::getVPMaskIdx(Opcode: Node->getOpcode()) == j)) { // Skip mask operand.
3214 // promote the vector operand.
3215 // FIXME: Support integer.
3216 assert(Node->getOperand(j).getValueType().isFloatingPoint() &&
3217 "Only FP promotion is supported");
3218 Operands[j] =
3219 DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: NewVecVT, Operand: Node->getOperand(Num: j));
3220 } else if (Node->getOperand(Num: j).getValueType().isFloatingPoint()) {
3221 // promote the initial value.
3222 Operands[j] =
3223 DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: NewScalarVT, Operand: Node->getOperand(Num: j));
3224 } else {
3225 Operands[j] = Node->getOperand(Num: j); // Skip VL operand.
3226 }
3227
3228 SDValue Res = DAG.getNode(Opcode: Node->getOpcode(), DL, VT: NewScalarVT, Ops: Operands,
3229 Flags: Node->getFlags());
3230
3231 assert(ScalarVT.isFloatingPoint() && "Only FP promotion is supported");
3232 return DAG.getNode(Opcode: ISD::FP_ROUND, DL, VT: ScalarVT, N1: Res,
3233 N2: DAG.getIntPtrConstant(Val: 0, DL, /*isTarget=*/true));
3234}
3235
3236bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
3237 LLVM_DEBUG(dbgs() << "Trying to expand node\n");
3238 SmallVector<SDValue, 8> Results;
3239 SDLoc dl(Node);
3240 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3241 bool NeedInvert;
3242 switch (Node->getOpcode()) {
3243 case ISD::ABS:
3244 case ISD::ABS_MIN_POISON:
3245 if ((Tmp1 = TLI.expandABS(N: Node, DAG)))
3246 Results.push_back(Elt: Tmp1);
3247 break;
3248 case ISD::ABDS:
3249 case ISD::ABDU:
3250 if ((Tmp1 = TLI.expandABD(N: Node, DAG)))
3251 Results.push_back(Elt: Tmp1);
3252 break;
3253 case ISD::AVGCEILS:
3254 case ISD::AVGCEILU:
3255 case ISD::AVGFLOORS:
3256 case ISD::AVGFLOORU:
3257 if ((Tmp1 = TLI.expandAVG(N: Node, DAG)))
3258 Results.push_back(Elt: Tmp1);
3259 break;
3260 case ISD::CTPOP:
3261 if ((Tmp1 = TLI.expandCTPOP(N: Node, DAG)))
3262 Results.push_back(Elt: Tmp1);
3263 break;
3264 case ISD::CTLZ:
3265 case ISD::CTLZ_ZERO_POISON:
3266 if ((Tmp1 = TLI.expandCTLZ(N: Node, DAG)))
3267 Results.push_back(Elt: Tmp1);
3268 break;
3269 case ISD::CTLS:
3270 if ((Tmp1 = TLI.expandCTLS(N: Node, DAG)))
3271 Results.push_back(Elt: Tmp1);
3272 break;
3273 case ISD::CTTZ:
3274 case ISD::CTTZ_ZERO_POISON:
3275 if ((Tmp1 = TLI.expandCTTZ(N: Node, DAG)))
3276 Results.push_back(Elt: Tmp1);
3277 break;
3278 case ISD::BITREVERSE:
3279 if ((Tmp1 = TLI.expandBITREVERSE(N: Node, DAG)))
3280 Results.push_back(Elt: Tmp1);
3281 break;
3282 case ISD::BSWAP:
3283 if ((Tmp1 = TLI.expandBSWAP(N: Node, DAG)))
3284 Results.push_back(Elt: Tmp1);
3285 break;
3286 case ISD::PARITY:
3287 Results.push_back(Elt: ExpandPARITY(Op: Node->getOperand(Num: 0), dl));
3288 break;
3289 case ISD::FRAMEADDR:
3290 case ISD::RETURNADDR:
3291 case ISD::FRAME_TO_ARGS_OFFSET:
3292 Results.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT: Node->getValueType(ResNo: 0)));
3293 break;
3294 case ISD::EH_DWARF_CFA: {
3295 SDValue CfaArg = DAG.getSExtOrTrunc(Op: Node->getOperand(Num: 0), DL: dl,
3296 VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
3297 SDValue Offset = DAG.getNode(Opcode: ISD::ADD, DL: dl,
3298 VT: CfaArg.getValueType(),
3299 N1: DAG.getNode(Opcode: ISD::FRAME_TO_ARGS_OFFSET, DL: dl,
3300 VT: CfaArg.getValueType()),
3301 N2: CfaArg);
3302 SDValue FA = DAG.getNode(
3303 Opcode: ISD::FRAMEADDR, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()),
3304 Operand: DAG.getConstant(Val: 0, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
3305 Results.push_back(Elt: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: FA.getValueType(),
3306 N1: FA, N2: Offset));
3307 break;
3308 }
3309 case ISD::GET_ROUNDING:
3310 Results.push_back(Elt: DAG.getConstant(Val: 1, DL: dl, VT: Node->getValueType(ResNo: 0)));
3311 Results.push_back(Elt: Node->getOperand(Num: 0));
3312 break;
3313 case ISD::EH_RETURN:
3314 case ISD::EH_LABEL:
3315 case ISD::PREFETCH:
3316 case ISD::VAEND:
3317 case ISD::EH_SJLJ_LONGJMP:
3318 // If the target didn't expand these, there's nothing to do, so just
3319 // preserve the chain and be done.
3320 Results.push_back(Elt: Node->getOperand(Num: 0));
3321 break;
3322 case ISD::READCYCLECOUNTER:
3323 case ISD::READSTEADYCOUNTER:
3324 // If the target didn't expand this, just return 'zero' and preserve the
3325 // chain.
3326 Results.append(NumInputs: Node->getNumValues() - 1,
3327 Elt: DAG.getConstant(Val: 0, DL: dl, VT: Node->getValueType(ResNo: 0)));
3328 Results.push_back(Elt: Node->getOperand(Num: 0));
3329 break;
3330 case ISD::EH_SJLJ_SETJMP:
3331 // If the target didn't expand this, just return 'zero' and preserve the
3332 // chain.
3333 Results.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
3334 Results.push_back(Elt: Node->getOperand(Num: 0));
3335 break;
3336 case ISD::ATOMIC_LOAD: {
3337 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3338 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: Node->getValueType(ResNo: 0));
3339 SDVTList VTs = DAG.getVTList(VT1: Node->getValueType(ResNo: 0), VT2: MVT::Other);
3340 SDValue Swap = DAG.getAtomicCmpSwap(
3341 Opcode: ISD::ATOMIC_CMP_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: Node)->getMemoryVT(), VTs,
3342 Chain: Node->getOperand(Num: 0), Ptr: Node->getOperand(Num: 1), Cmp: Zero, Swp: Zero,
3343 MMO: cast<AtomicSDNode>(Val: Node)->getMemOperand());
3344 Results.push_back(Elt: Swap.getValue(R: 0));
3345 Results.push_back(Elt: Swap.getValue(R: 1));
3346 break;
3347 }
3348 case ISD::ATOMIC_STORE: {
3349 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3350 SDValue Swap = DAG.getAtomic(
3351 Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: Node)->getMemoryVT(),
3352 Chain: Node->getOperand(Num: 0), Ptr: Node->getOperand(Num: 2), Val: Node->getOperand(Num: 1),
3353 MMO: cast<AtomicSDNode>(Val: Node)->getMemOperand());
3354 Results.push_back(Elt: Swap.getValue(R: 1));
3355 break;
3356 }
3357 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3358 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3359 // splits out the success value as a comparison. Expanding the resulting
3360 // ATOMIC_CMP_SWAP will produce a libcall.
3361 SDVTList VTs = DAG.getVTList(VT1: Node->getValueType(ResNo: 0), VT2: MVT::Other);
3362 SDValue Res = DAG.getAtomicCmpSwap(
3363 Opcode: ISD::ATOMIC_CMP_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: Node)->getMemoryVT(), VTs,
3364 Chain: Node->getOperand(Num: 0), Ptr: Node->getOperand(Num: 1), Cmp: Node->getOperand(Num: 2),
3365 Swp: Node->getOperand(Num: 3), MMO: cast<MemSDNode>(Val: Node)->getMemOperand());
3366
3367 SDValue ExtRes = Res;
3368 SDValue LHS = Res;
3369 SDValue RHS = Node->getOperand(Num: 1);
3370
3371 EVT AtomicType = cast<AtomicSDNode>(Val: Node)->getMemoryVT();
3372 EVT OuterType = Node->getValueType(ResNo: 0);
3373 switch (TLI.getExtendForAtomicOps()) {
3374 case ISD::SIGN_EXTEND:
3375 LHS = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: OuterType, N1: Res,
3376 N2: DAG.getValueType(AtomicType));
3377 RHS = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: OuterType,
3378 N1: Node->getOperand(Num: 2), N2: DAG.getValueType(AtomicType));
3379 ExtRes = LHS;
3380 break;
3381 case ISD::ZERO_EXTEND:
3382 LHS = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: OuterType, N1: Res,
3383 N2: DAG.getValueType(AtomicType));
3384 RHS = DAG.getZeroExtendInReg(Op: Node->getOperand(Num: 2), DL: dl, VT: AtomicType);
3385 ExtRes = LHS;
3386 break;
3387 case ISD::ANY_EXTEND:
3388 LHS = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: AtomicType);
3389 RHS = DAG.getZeroExtendInReg(Op: Node->getOperand(Num: 2), DL: dl, VT: AtomicType);
3390 break;
3391 default:
3392 llvm_unreachable("Invalid atomic op extension");
3393 }
3394
3395 SDValue Success =
3396 DAG.getSetCC(DL: dl, VT: Node->getValueType(ResNo: 1), LHS, RHS, Cond: ISD::SETEQ);
3397
3398 Results.push_back(Elt: ExtRes.getValue(R: 0));
3399 Results.push_back(Elt: Success);
3400 Results.push_back(Elt: Res.getValue(R: 1));
3401 break;
3402 }
3403 case ISD::ATOMIC_LOAD_SUB: {
3404 SDLoc DL(Node);
3405 EVT VT = Node->getValueType(ResNo: 0);
3406 SDValue RHS = Node->getOperand(Num: 2);
3407 AtomicSDNode *AN = cast<AtomicSDNode>(Val: Node);
3408 if (RHS->getOpcode() == ISD::SIGN_EXTEND_INREG &&
3409 cast<VTSDNode>(Val: RHS->getOperand(Num: 1))->getVT() == AN->getMemoryVT())
3410 RHS = RHS->getOperand(Num: 0);
3411 SDValue NewRHS =
3412 DAG.getNode(Opcode: ISD::SUB, DL, VT, N1: DAG.getConstant(Val: 0, DL, VT), N2: RHS);
3413 SDValue Res = DAG.getAtomic(Opcode: ISD::ATOMIC_LOAD_ADD, dl: DL, MemVT: AN->getMemoryVT(),
3414 Chain: Node->getOperand(Num: 0), Ptr: Node->getOperand(Num: 1),
3415 Val: NewRHS, MMO: AN->getMemOperand());
3416 Results.push_back(Elt: Res);
3417 Results.push_back(Elt: Res.getValue(R: 1));
3418 break;
3419 }
3420 case ISD::DYNAMIC_STACKALLOC:
3421 ExpandDYNAMIC_STACKALLOC(Node, Results);
3422 break;
3423 case ISD::MERGE_VALUES:
3424 for (unsigned i = 0; i < Node->getNumValues(); i++)
3425 Results.push_back(Elt: Node->getOperand(Num: i));
3426 break;
3427 case ISD::POISON:
3428 case ISD::UNDEF: {
3429 EVT VT = Node->getValueType(ResNo: 0);
3430 if (VT.isInteger())
3431 Results.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT));
3432 else {
3433 assert(VT.isFloatingPoint() && "Unknown value type!");
3434 Results.push_back(Elt: DAG.getConstantFP(Val: 0, DL: dl, VT));
3435 }
3436 break;
3437 }
3438 case ISD::STRICT_FP_ROUND:
3439 // When strict mode is enforced we can't do expansion because it
3440 // does not honor the "strict" properties. Only libcall is allowed.
3441 if (TLI.isStrictFPEnabled())
3442 break;
3443 // We might as well mutate to FP_ROUND when FP_ROUND operation is legal
3444 // since this operation is more efficient than stack operation.
3445 if (TLI.getStrictFPOperationAction(Op: Node->getOpcode(),
3446 VT: Node->getValueType(ResNo: 0))
3447 == TargetLowering::Legal)
3448 break;
3449 // We fall back to use stack operation when the FP_ROUND operation
3450 // isn't available.
3451 if ((Tmp1 = EmitStackConvert(SrcOp: Node->getOperand(Num: 1), SlotVT: Node->getValueType(ResNo: 0),
3452 DestVT: Node->getValueType(ResNo: 0), dl,
3453 Chain: Node->getOperand(Num: 0)))) {
3454 ReplaceNode(Old: Node, New: Tmp1.getNode());
3455 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_ROUND node\n");
3456 return true;
3457 }
3458 break;
3459 case ISD::FP_ROUND: {
3460 if ((Tmp1 = TLI.expandFP_ROUND(Node, DAG))) {
3461 Results.push_back(Elt: Tmp1);
3462 break;
3463 }
3464
3465 [[fallthrough]];
3466 }
3467 case ISD::BITCAST:
3468 if ((Tmp1 = EmitStackConvert(SrcOp: Node->getOperand(Num: 0), SlotVT: Node->getValueType(ResNo: 0),
3469 DestVT: Node->getValueType(ResNo: 0), dl)))
3470 Results.push_back(Elt: Tmp1);
3471 break;
3472 case ISD::STRICT_FP_EXTEND:
3473 // When strict mode is enforced we can't do expansion because it
3474 // does not honor the "strict" properties. Only libcall is allowed.
3475 if (TLI.isStrictFPEnabled())
3476 break;
3477 // We might as well mutate to FP_EXTEND when FP_EXTEND operation is legal
3478 // since this operation is more efficient than stack operation.
3479 if (TLI.getStrictFPOperationAction(Op: Node->getOpcode(),
3480 VT: Node->getValueType(ResNo: 0))
3481 == TargetLowering::Legal)
3482 break;
3483 // We fall back to use stack operation when the FP_EXTEND operation
3484 // isn't available.
3485 if ((Tmp1 = EmitStackConvert(
3486 SrcOp: Node->getOperand(Num: 1), SlotVT: Node->getOperand(Num: 1).getValueType(),
3487 DestVT: Node->getValueType(ResNo: 0), dl, Chain: Node->getOperand(Num: 0)))) {
3488 ReplaceNode(Old: Node, New: Tmp1.getNode());
3489 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_EXTEND node\n");
3490 return true;
3491 }
3492 break;
3493 case ISD::FP_EXTEND: {
3494 SDValue Op = Node->getOperand(Num: 0);
3495 EVT SrcVT = Op.getValueType();
3496 EVT DstVT = Node->getValueType(ResNo: 0);
3497 if (SrcVT.getScalarType() == MVT::bf16) {
3498 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BF16_TO_FP, DL: SDLoc(Node), VT: DstVT, Operand: Op));
3499 break;
3500 }
3501
3502 if ((Tmp1 = EmitStackConvert(SrcOp: Op, SlotVT: SrcVT, DestVT: DstVT, dl)))
3503 Results.push_back(Elt: Tmp1);
3504 break;
3505 }
3506 case ISD::BF16_TO_FP: {
3507 // Always expand bf16 to f32 casts, they lower to ext + shift.
3508 //
3509 // Note that the operand of this code can be bf16 or an integer type in case
3510 // bf16 is not supported on the target and was softened.
3511 SDValue Op = Node->getOperand(Num: 0);
3512 if (Op.getValueType() == MVT::bf16) {
3513 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: MVT::i32,
3514 Operand: DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i16, Operand: Op));
3515 } else {
3516 Op = DAG.getAnyExtOrTrunc(Op, DL: dl, VT: MVT::i32);
3517 }
3518 Op = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: MVT::i32, N1: Op,
3519 N2: DAG.getShiftAmountConstant(Val: 16, VT: MVT::i32, DL: dl));
3520 Op = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: Op);
3521 // Add fp_extend in case the output is bigger than f32.
3522 if (Node->getValueType(ResNo: 0) != MVT::f32)
3523 Op = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Op);
3524 Results.push_back(Elt: Op);
3525 break;
3526 }
3527 case ISD::FP_TO_BF16: {
3528 SDValue Op = Node->getOperand(Num: 0);
3529 if (Op.getValueType() != MVT::f32)
3530 Op = DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: MVT::f32, N1: Op,
3531 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true));
3532 // Certain SNaNs will turn into infinities if we do a simple shift right.
3533 if (!DAG.isKnownNeverSNaN(Op)) {
3534 Op = DAG.getNode(Opcode: ISD::FCANONICALIZE, DL: dl, VT: MVT::f32, Operand: Op, Flags: Node->getFlags());
3535 }
3536 Op = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: MVT::i32,
3537 N1: DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Op),
3538 N2: DAG.getShiftAmountConstant(Val: 16, VT: MVT::i32, DL: dl));
3539 // The result of this node can be bf16 or an integer type in case bf16 is
3540 // not supported on the target and was softened to i16 for storage.
3541 if (Node->getValueType(ResNo: 0) == MVT::bf16) {
3542 Op = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::bf16,
3543 Operand: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: MVT::i16, Operand: Op));
3544 } else {
3545 Op = DAG.getAnyExtOrTrunc(Op, DL: dl, VT: Node->getValueType(ResNo: 0));
3546 }
3547 Results.push_back(Elt: Op);
3548 break;
3549 }
3550 case ISD::CONVERT_FROM_ARBITRARY_FP: {
3551 // Expand conversion from arbitrary FP format stored in an integer to a
3552 // native IEEE float type using integer bit manipulation.
3553 //
3554 // TODO: currently only conversions from FP4, FP6 and FP8 formats from OCP
3555 // specification are expanded. Remaining arbitrary FP types: Float8E4M3,
3556 // Float8E3M4, Float8E5M2FNUZ, Float8E4M3FNUZ, Float8E4M3B11FNUZ,
3557 // Float8E8M0FNU.
3558 EVT DstVT = Node->getValueType(ResNo: 0);
3559 if (SDValue Expanded = TLI.expandCONVERT_FROM_ARBITRARY_FP(Node, DAG))
3560 Results.push_back(Elt: Expanded);
3561 else
3562 Results.push_back(Elt: DAG.getPOISON(VT: DstVT));
3563 break;
3564 }
3565 case ISD::CONVERT_TO_ARBITRARY_FP: {
3566 // Expand conversion from a native IEEE float type to an arbitrary FP
3567 // format, returning the result as an integer using bit manipulation.
3568 //
3569 // TODO: currently only conversions to FP4, FP6 and FP8 formats from OCP
3570 // specification are expanded. Remaining arbitrary FP types: Float8E4M3,
3571 // Float8E3M4, Float8E5M2FNUZ, Float8E4M3FNUZ, Float8E4M3B11FNUZ,
3572 // Float8E8M0FNU.
3573 EVT ResVT = Node->getValueType(ResNo: 0);
3574 if (SDValue Expanded = TLI.expandCONVERT_TO_ARBITRARY_FP(Node, DAG))
3575 Results.push_back(Elt: Expanded);
3576 else
3577 Results.push_back(Elt: DAG.getPOISON(VT: ResVT));
3578 break;
3579 }
3580 case ISD::FCANONICALIZE: {
3581 SDValue Mul = TLI.expandFCANONICALIZE(Node, DAG);
3582 Results.push_back(Elt: Mul);
3583 break;
3584 }
3585 case ISD::SIGN_EXTEND_INREG: {
3586 EVT ExtraVT = cast<VTSDNode>(Val: Node->getOperand(Num: 1))->getVT();
3587 EVT VT = Node->getValueType(ResNo: 0);
3588
3589 // An in-register sign-extend of a boolean is a negation:
3590 // 'true' (1) sign-extended is -1.
3591 // 'false' (0) sign-extended is 0.
3592 // However, we must mask the high bits of the source operand because the
3593 // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
3594
3595 // TODO: Do this for vectors too?
3596 if (ExtraVT.isScalarInteger() && ExtraVT.getSizeInBits() == 1) {
3597 SDValue One = DAG.getConstant(Val: 1, DL: dl, VT);
3598 SDValue And = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Node->getOperand(Num: 0), N2: One);
3599 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
3600 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: Zero, N2: And);
3601 Results.push_back(Elt: Neg);
3602 break;
3603 }
3604
3605 // NOTE: we could fall back on load/store here too for targets without
3606 // SRA. However, it is doubtful that any exist.
3607 unsigned BitsDiff = VT.getScalarSizeInBits() -
3608 ExtraVT.getScalarSizeInBits();
3609 SDValue ShiftCst = DAG.getShiftAmountConstant(Val: BitsDiff, VT, DL: dl);
3610 Tmp1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT, N1: Node->getOperand(Num: 0), N2: ShiftCst);
3611 Tmp1 = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT, N1: Tmp1, N2: ShiftCst);
3612 Results.push_back(Elt: Tmp1);
3613 break;
3614 }
3615 case ISD::UINT_TO_FP:
3616 case ISD::STRICT_UINT_TO_FP:
3617 if (TLI.expandUINT_TO_FP(N: Node, Result&: Tmp1, Chain&: Tmp2, DAG)) {
3618 Results.push_back(Elt: Tmp1);
3619 if (Node->isStrictFPOpcode())
3620 Results.push_back(Elt: Tmp2);
3621 break;
3622 }
3623 [[fallthrough]];
3624 case ISD::SINT_TO_FP:
3625 case ISD::STRICT_SINT_TO_FP:
3626 if ((Tmp1 = ExpandLegalINT_TO_FP(Node, Chain&: Tmp2))) {
3627 Results.push_back(Elt: Tmp1);
3628 if (Node->isStrictFPOpcode())
3629 Results.push_back(Elt: Tmp2);
3630 }
3631 break;
3632 case ISD::FP_TO_SINT:
3633 if (TLI.expandFP_TO_SINT(N: Node, Result&: Tmp1, DAG))
3634 Results.push_back(Elt: Tmp1);
3635 break;
3636 case ISD::STRICT_FP_TO_SINT:
3637 if (TLI.expandFP_TO_SINT(N: Node, Result&: Tmp1, DAG)) {
3638 ReplaceNode(Old: Node, New: Tmp1.getNode());
3639 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_SINT node\n");
3640 return true;
3641 }
3642 break;
3643 case ISD::FP_TO_UINT:
3644 if (TLI.expandFP_TO_UINT(N: Node, Result&: Tmp1, Chain&: Tmp2, DAG))
3645 Results.push_back(Elt: Tmp1);
3646 break;
3647 case ISD::STRICT_FP_TO_UINT:
3648 if (TLI.expandFP_TO_UINT(N: Node, Result&: Tmp1, Chain&: Tmp2, DAG)) {
3649 // Relink the chain.
3650 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node,1), To: Tmp2);
3651 // Replace the new UINT result.
3652 ReplaceNodeWithValue(Old: SDValue(Node, 0), New: Tmp1);
3653 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_UINT node\n");
3654 return true;
3655 }
3656 break;
3657 case ISD::FP_TO_SINT_SAT:
3658 case ISD::FP_TO_UINT_SAT:
3659 Results.push_back(Elt: TLI.expandFP_TO_INT_SAT(N: Node, DAG));
3660 break;
3661 case ISD::LROUND:
3662 case ISD::LLROUND: {
3663 SDValue Arg = Node->getOperand(Num: 0);
3664 EVT ArgVT = Arg.getValueType();
3665 EVT ResVT = Node->getValueType(ResNo: 0);
3666 SDLoc dl(Node);
3667 SDValue RoundNode = DAG.getNode(Opcode: ISD::FROUND, DL: dl, VT: ArgVT, Operand: Arg);
3668 Results.push_back(Elt: DAG.getNode(Opcode: ISD::FP_TO_SINT, DL: dl, VT: ResVT, Operand: RoundNode));
3669 break;
3670 }
3671 case ISD::VAARG:
3672 Results.push_back(Elt: DAG.expandVAArg(Node));
3673 Results.push_back(Elt: Results[0].getValue(R: 1));
3674 break;
3675 case ISD::VACOPY:
3676 Results.push_back(Elt: DAG.expandVACopy(Node));
3677 break;
3678 case ISD::EXTRACT_VECTOR_ELT:
3679 if (Node->getOperand(Num: 0).getValueType().getVectorElementCount().isScalar())
3680 // This must be an access of the only element. Return it.
3681 Tmp1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: Node->getValueType(ResNo: 0),
3682 Operand: Node->getOperand(Num: 0));
3683 else
3684 Tmp1 = ExpandExtractFromVectorThroughStack(Op: SDValue(Node, 0));
3685 Results.push_back(Elt: Tmp1);
3686 break;
3687 case ISD::EXTRACT_SUBVECTOR:
3688 Results.push_back(Elt: ExpandExtractFromVectorThroughStack(Op: SDValue(Node, 0)));
3689 break;
3690 case ISD::INSERT_SUBVECTOR:
3691 Results.push_back(Elt: ExpandInsertToVectorThroughStack(Op: SDValue(Node, 0)));
3692 break;
3693 case ISD::CONCAT_VECTORS:
3694 if (EVT VectorValueType = Node->getOperand(Num: 0).getValueType();
3695 VectorValueType.isScalableVector() ||
3696 TLI.isOperationExpand(Op: ISD::EXTRACT_VECTOR_ELT, VT: VectorValueType))
3697 Results.push_back(Elt: ExpandVectorBuildThroughStack(Node));
3698 else
3699 Results.push_back(Elt: ExpandConcatVectors(Node));
3700 break;
3701 case ISD::SCALAR_TO_VECTOR:
3702 Results.push_back(Elt: ExpandSCALAR_TO_VECTOR(Node));
3703 break;
3704 case ISD::INSERT_VECTOR_ELT:
3705 Results.push_back(Elt: ExpandINSERT_VECTOR_ELT(Op: SDValue(Node, 0)));
3706 break;
3707 case ISD::VECTOR_SHUFFLE: {
3708 SmallVector<int, 32> NewMask;
3709 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Val: Node)->getMask();
3710
3711 EVT VT = Node->getValueType(ResNo: 0);
3712 EVT EltVT = VT.getVectorElementType();
3713 SDValue Op0 = Node->getOperand(Num: 0);
3714 SDValue Op1 = Node->getOperand(Num: 1);
3715 if (!TLI.isTypeLegal(VT: EltVT)) {
3716 EVT NewEltVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: EltVT);
3717
3718 // BUILD_VECTOR operands are allowed to be wider than the element type.
3719 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3720 // it.
3721 if (NewEltVT.bitsLT(VT: EltVT)) {
3722 // Convert shuffle node.
3723 // If original node was v4i64 and the new EltVT is i32,
3724 // cast operands to v8i32 and re-build the mask.
3725
3726 // Calculate new VT, the size of the new VT should be equal to original.
3727 EVT NewVT =
3728 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NewEltVT,
3729 NumElements: VT.getSizeInBits() / NewEltVT.getSizeInBits());
3730 assert(NewVT.bitsEq(VT));
3731
3732 // cast operands to new VT
3733 Op0 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NewVT, Operand: Op0);
3734 Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NewVT, Operand: Op1);
3735
3736 // Convert the shuffle mask
3737 unsigned int factor =
3738 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3739
3740 // EltVT gets smaller
3741 assert(factor > 0);
3742
3743 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3744 if (Mask[i] < 0) {
3745 for (unsigned fi = 0; fi < factor; ++fi)
3746 NewMask.push_back(Elt: Mask[i]);
3747 }
3748 else {
3749 for (unsigned fi = 0; fi < factor; ++fi)
3750 NewMask.push_back(Elt: Mask[i]*factor+fi);
3751 }
3752 }
3753 Mask = NewMask;
3754 VT = NewVT;
3755 }
3756 EltVT = NewEltVT;
3757 }
3758 unsigned NumElems = VT.getVectorNumElements();
3759 SmallVector<SDValue, 16> Ops;
3760 for (unsigned i = 0; i != NumElems; ++i) {
3761 if (Mask[i] < 0) {
3762 Ops.push_back(Elt: DAG.getUNDEF(VT: EltVT));
3763 continue;
3764 }
3765 unsigned Idx = Mask[i];
3766 if (Idx < NumElems)
3767 Ops.push_back(Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: EltVT, N1: Op0,
3768 N2: DAG.getVectorIdxConstant(Val: Idx, DL: dl)));
3769 else
3770 Ops.push_back(
3771 Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: EltVT, N1: Op1,
3772 N2: DAG.getVectorIdxConstant(Val: Idx - NumElems, DL: dl)));
3773 }
3774
3775 Tmp1 = DAG.getBuildVector(VT, DL: dl, Ops);
3776 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3777 Tmp1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Tmp1);
3778 Results.push_back(Elt: Tmp1);
3779 break;
3780 }
3781 case ISD::VECTOR_SPLICE_LEFT:
3782 case ISD::VECTOR_SPLICE_RIGHT: {
3783 Results.push_back(Elt: TLI.expandVectorSplice(Node, DAG));
3784 break;
3785 }
3786 case ISD::VECTOR_DEINTERLEAVE: {
3787 unsigned Factor = Node->getNumOperands();
3788 if (Factor <= 2 || Factor % 2 != 0)
3789 break;
3790 SmallVector<SDValue, 8> Ops(Node->ops());
3791 EVT VecVT = Node->getValueType(ResNo: 0);
3792 SmallVector<EVT> HalfVTs(Factor / 2, VecVT);
3793 // Deinterleave at Factor/2 so each result contains two factors interleaved:
3794 // a0b0 c0d0 a1b1 c1d1 -> [a0c0 b0d0] [a1c1 b1d1]
3795 SDValue L = DAG.getNode(Opcode: ISD::VECTOR_DEINTERLEAVE, DL: dl, ResultTys: HalfVTs,
3796 Ops: ArrayRef(Ops).take_front(N: Factor / 2));
3797 SDValue R = DAG.getNode(Opcode: ISD::VECTOR_DEINTERLEAVE, DL: dl, ResultTys: HalfVTs,
3798 Ops: ArrayRef(Ops).take_back(N: Factor / 2));
3799 Results.resize(N: Factor);
3800 // Deinterleave the 2 factors out:
3801 // [a0c0 a1c1] [b0d0 b1d1] -> a0a1 b0b1 c0c1 d0d1
3802 for (unsigned I = 0; I < Factor / 2; I++) {
3803 SDValue Deinterleave =
3804 DAG.getNode(Opcode: ISD::VECTOR_DEINTERLEAVE, DL: dl, ResultTys: {VecVT, VecVT},
3805 Ops: {L.getValue(R: I), R.getValue(R: I)});
3806 Results[I] = Deinterleave.getValue(R: 0);
3807 Results[I + Factor / 2] = Deinterleave.getValue(R: 1);
3808 }
3809 break;
3810 }
3811 case ISD::VECTOR_INTERLEAVE: {
3812 unsigned Factor = Node->getNumOperands();
3813 if (Factor <= 2 || Factor % 2 != 0)
3814 break;
3815 EVT VecVT = Node->getValueType(ResNo: 0);
3816 SmallVector<EVT> HalfVTs(Factor / 2, VecVT);
3817 SmallVector<SDValue, 8> LOps, ROps;
3818 // Interleave so we have 2 factors per result:
3819 // a0a1 b0b1 c0c1 d0d1 -> [a0c0 b0d0] [a1c1 b1d1]
3820 for (unsigned I = 0; I < Factor / 2; I++) {
3821 SDValue Interleave =
3822 DAG.getNode(Opcode: ISD::VECTOR_INTERLEAVE, DL: dl, ResultTys: {VecVT, VecVT},
3823 Ops: {Node->getOperand(Num: I), Node->getOperand(Num: I + Factor / 2)});
3824 LOps.push_back(Elt: Interleave.getValue(R: 0));
3825 ROps.push_back(Elt: Interleave.getValue(R: 1));
3826 }
3827 // Interleave at Factor/2:
3828 // [a0c0 b0d0] [a1c1 b1d1] -> a0b0 c0d0 a1b1 c1d1
3829 SDValue L = DAG.getNode(Opcode: ISD::VECTOR_INTERLEAVE, DL: dl, ResultTys: HalfVTs, Ops: LOps);
3830 SDValue R = DAG.getNode(Opcode: ISD::VECTOR_INTERLEAVE, DL: dl, ResultTys: HalfVTs, Ops: ROps);
3831 for (unsigned I = 0; I < Factor / 2; I++)
3832 Results.push_back(Elt: L.getValue(R: I));
3833 for (unsigned I = 0; I < Factor / 2; I++)
3834 Results.push_back(Elt: R.getValue(R: I));
3835 break;
3836 }
3837 case ISD::EXTRACT_ELEMENT: {
3838 EVT OpTy = Node->getOperand(Num: 0).getValueType();
3839 if (Node->getConstantOperandVal(Num: 1)) {
3840 // 1 -> Hi
3841 Tmp1 = DAG.getNode(
3842 Opcode: ISD::SRL, DL: dl, VT: OpTy, N1: Node->getOperand(Num: 0),
3843 N2: DAG.getShiftAmountConstant(Val: OpTy.getSizeInBits() / 2, VT: OpTy, DL: dl));
3844 Tmp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Tmp1);
3845 } else {
3846 // 0 -> Lo
3847 Tmp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: Node->getValueType(ResNo: 0),
3848 Operand: Node->getOperand(Num: 0));
3849 }
3850 Results.push_back(Elt: Tmp1);
3851 break;
3852 }
3853 case ISD::STACKADDRESS:
3854 case ISD::STACKSAVE:
3855 // Expand to CopyFromReg if the target set
3856 // StackPointerRegisterToSaveRestore.
3857 if (Register SP = TLI.getStackPointerRegisterToSaveRestore()) {
3858 Results.push_back(Elt: DAG.getCopyFromReg(Chain: Node->getOperand(Num: 0), dl, Reg: SP,
3859 VT: Node->getValueType(ResNo: 0)));
3860 Results.push_back(Elt: Results[0].getValue(R: 1));
3861 } else {
3862 Results.push_back(Elt: DAG.getUNDEF(VT: Node->getValueType(ResNo: 0)));
3863 Results.push_back(Elt: Node->getOperand(Num: 0));
3864
3865 StringRef IntrinsicName = Node->getOpcode() == ISD::STACKADDRESS
3866 ? "llvm.stackaddress"
3867 : "llvm.stacksave";
3868 DAG.getContext()->diagnose(DI: DiagnosticInfoLegalizationFailure(
3869 Twine(IntrinsicName) + " is not supported on this target.",
3870 DAG.getMachineFunction().getFunction(), dl.getDebugLoc()));
3871 }
3872 break;
3873 case ISD::STACKRESTORE:
3874 // Expand to CopyToReg if the target set
3875 // StackPointerRegisterToSaveRestore.
3876 if (Register SP = TLI.getStackPointerRegisterToSaveRestore()) {
3877 Results.push_back(Elt: DAG.getCopyToReg(Chain: Node->getOperand(Num: 0), dl, Reg: SP,
3878 N: Node->getOperand(Num: 1)));
3879 } else {
3880 Results.push_back(Elt: Node->getOperand(Num: 0));
3881 }
3882 break;
3883 case ISD::GET_DYNAMIC_AREA_OFFSET:
3884 Results.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT: Node->getValueType(ResNo: 0)));
3885 Results.push_back(Elt: Results[0].getValue(R: 0));
3886 break;
3887 case ISD::FCOPYSIGN:
3888 Results.push_back(Elt: ExpandFCOPYSIGN(Node));
3889 break;
3890 case ISD::FNEG:
3891 Results.push_back(Elt: ExpandFNEG(Node));
3892 break;
3893 case ISD::FABS:
3894 Results.push_back(Elt: ExpandFABS(Node));
3895 break;
3896 case ISD::IS_FPCLASS: {
3897 auto Test = static_cast<FPClassTest>(Node->getConstantOperandVal(Num: 1));
3898 if (SDValue Expanded =
3899 TLI.expandIS_FPCLASS(ResultVT: Node->getValueType(ResNo: 0), Op: Node->getOperand(Num: 0),
3900 Test, Flags: Node->getFlags(), DL: SDLoc(Node), DAG))
3901 Results.push_back(Elt: Expanded);
3902 break;
3903 }
3904 case ISD::SMIN:
3905 case ISD::SMAX:
3906 case ISD::UMIN:
3907 case ISD::UMAX: {
3908 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3909 ISD::CondCode Pred;
3910 switch (Node->getOpcode()) {
3911 default: llvm_unreachable("How did we get here?");
3912 case ISD::SMAX: Pred = ISD::SETGT; break;
3913 case ISD::SMIN: Pred = ISD::SETLT; break;
3914 case ISD::UMAX: Pred = ISD::SETUGT; break;
3915 case ISD::UMIN: Pred = ISD::SETULT; break;
3916 }
3917 Tmp1 = Node->getOperand(Num: 0);
3918 Tmp2 = Node->getOperand(Num: 1);
3919 Tmp1 = DAG.getSelectCC(DL: dl, LHS: Tmp1, RHS: Tmp2, True: Tmp1, False: Tmp2, Cond: Pred);
3920 Results.push_back(Elt: Tmp1);
3921 break;
3922 }
3923 case ISD::FMINNUM:
3924 case ISD::FMAXNUM: {
3925 if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(N: Node, DAG))
3926 Results.push_back(Elt: Expanded);
3927 break;
3928 }
3929 case ISD::FMINIMUM:
3930 case ISD::FMAXIMUM: {
3931 if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(N: Node, DAG))
3932 Results.push_back(Elt: Expanded);
3933 break;
3934 }
3935 case ISD::FMINIMUMNUM:
3936 case ISD::FMAXIMUMNUM: {
3937 Results.push_back(Elt: TLI.expandFMINIMUMNUM_FMAXIMUMNUM(N: Node, DAG));
3938 break;
3939 }
3940 case ISD::FSIN:
3941 case ISD::FCOS: {
3942 EVT VT = Node->getValueType(ResNo: 0);
3943 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3944 // fcos which share the same operand and both are used.
3945 if ((TLI.isOperationLegal(Op: ISD::FSINCOS, VT) ||
3946 isSinCosLibcallAvailable(Node, Libcalls: DAG.getLibcalls())) &&
3947 useSinCos(Node)) {
3948 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: VT);
3949 Tmp1 = DAG.getNode(Opcode: ISD::FSINCOS, DL: dl, VTList: VTs, N: Node->getOperand(Num: 0));
3950 if (Node->getOpcode() == ISD::FCOS)
3951 Tmp1 = Tmp1.getValue(R: 1);
3952 Results.push_back(Elt: Tmp1);
3953 }
3954 break;
3955 }
3956 case ISD::FLDEXP:
3957 case ISD::STRICT_FLDEXP: {
3958 EVT VT = Node->getValueType(ResNo: 0);
3959 RTLIB::Libcall LC = RTLIB::getLDEXP(RetVT: VT);
3960 // Use the LibCall instead, it is very likely faster
3961 // FIXME: Use separate LibCall action.
3962 if (DAG.getLibcalls().getLibcallImpl(Call: LC) != RTLIB::Unsupported)
3963 break;
3964
3965 if (SDValue Expanded = expandLdexp(Node)) {
3966 Results.push_back(Elt: Expanded);
3967 if (Node->getOpcode() == ISD::STRICT_FLDEXP)
3968 Results.push_back(Elt: Expanded.getValue(R: 1));
3969 }
3970
3971 break;
3972 }
3973 case ISD::FFREXP: {
3974 RTLIB::Libcall LC = RTLIB::getFREXP(RetVT: Node->getValueType(ResNo: 0));
3975 // Use the LibCall instead, it is very likely faster
3976 // FIXME: Use separate LibCall action.
3977 if (DAG.getLibcalls().getLibcallImpl(Call: LC) != RTLIB::Unsupported)
3978 break;
3979
3980 if (SDValue Expanded = expandFrexp(Node)) {
3981 Results.push_back(Elt: Expanded);
3982 Results.push_back(Elt: Expanded.getValue(R: 1));
3983 }
3984 break;
3985 }
3986 case ISD::FMODF: {
3987 RTLIB::Libcall LC = RTLIB::getMODF(VT: Node->getValueType(ResNo: 0));
3988 // Use the LibCall instead, it is very likely faster
3989 // FIXME: Use separate LibCall action.
3990 if (DAG.getLibcalls().getLibcallImpl(Call: LC) != RTLIB::Unsupported)
3991 break;
3992
3993 if (SDValue Expanded = expandModf(Node)) {
3994 Results.push_back(Elt: Expanded);
3995 Results.push_back(Elt: Expanded.getValue(R: 1));
3996 }
3997 break;
3998 }
3999 case ISD::FSINCOS: {
4000 if (isSinCosLibcallAvailable(Node, Libcalls: DAG.getLibcalls()))
4001 break;
4002 EVT VT = Node->getValueType(ResNo: 0);
4003 SDValue Op = Node->getOperand(Num: 0);
4004 SDNodeFlags Flags = Node->getFlags();
4005 Tmp1 = DAG.getNode(Opcode: ISD::FSIN, DL: dl, VT, Operand: Op, Flags);
4006 Tmp2 = DAG.getNode(Opcode: ISD::FCOS, DL: dl, VT, Operand: Op, Flags);
4007 Results.append(IL: {Tmp1, Tmp2});
4008 break;
4009 }
4010 case ISD::FMAD:
4011 llvm_unreachable("Illegal fmad should never be formed");
4012
4013 case ISD::FP16_TO_FP:
4014 if (Node->getValueType(ResNo: 0) != MVT::f32) {
4015 // We can extend to types bigger than f32 in two steps without changing
4016 // the result. Since "f16 -> f32" is much more commonly available, give
4017 // CodeGen the option of emitting that before resorting to a libcall.
4018 SDValue Res =
4019 DAG.getNode(Opcode: ISD::FP16_TO_FP, DL: dl, VT: MVT::f32, Operand: Node->getOperand(Num: 0));
4020 Results.push_back(
4021 Elt: DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Res));
4022 }
4023 break;
4024 case ISD::STRICT_BF16_TO_FP:
4025 case ISD::STRICT_FP16_TO_FP:
4026 if (Node->getValueType(ResNo: 0) != MVT::f32) {
4027 // We can extend to types bigger than f32 in two steps without changing
4028 // the result. Since "f16 -> f32" is much more commonly available, give
4029 // CodeGen the option of emitting that before resorting to a libcall.
4030 SDValue Res = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {MVT::f32, MVT::Other},
4031 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
4032 Res = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl,
4033 ResultTys: {Node->getValueType(ResNo: 0), MVT::Other},
4034 Ops: {Res.getValue(R: 1), Res});
4035 Results.push_back(Elt: Res);
4036 Results.push_back(Elt: Res.getValue(R: 1));
4037 }
4038 break;
4039 case ISD::FP_TO_FP16:
4040 LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
4041 if (Node->getFlags().hasApproximateFuncs() && !TLI.useSoftFloat()) {
4042 SDValue Op = Node->getOperand(Num: 0);
4043 MVT SVT = Op.getSimpleValueType();
4044 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
4045 TLI.isOperationLegalOrCustom(Op: ISD::FP_TO_FP16, VT: MVT::f32)) {
4046 // Under fastmath, we can expand this node into a fround followed by
4047 // a float-half conversion.
4048 SDValue FloatVal =
4049 DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: MVT::f32, N1: Op,
4050 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true));
4051 Results.push_back(
4052 Elt: DAG.getNode(Opcode: ISD::FP_TO_FP16, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: FloatVal));
4053 }
4054 }
4055 break;
4056 case ISD::ConstantFP: {
4057 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Val: Node);
4058 // Check to see if this FP immediate is already legal.
4059 // If this is a legal constant, turn it into a TargetConstantFP node.
4060 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(ResNo: 0),
4061 ForCodeSize: DAG.shouldOptForSize()))
4062 Results.push_back(Elt: ExpandConstantFP(CFP, UseCP: true));
4063 break;
4064 }
4065 case ISD::Constant: {
4066 ConstantSDNode *CP = cast<ConstantSDNode>(Val: Node);
4067 Results.push_back(Elt: ExpandConstant(CP));
4068 break;
4069 }
4070 case ISD::FSUB: {
4071 EVT VT = Node->getValueType(ResNo: 0);
4072 if (TLI.isOperationLegalOrCustom(Op: ISD::FADD, VT) &&
4073 TLI.isOperationLegalOrCustom(Op: ISD::FNEG, VT)) {
4074 const SDNodeFlags Flags = Node->getFlags();
4075 Tmp1 = DAG.getNode(Opcode: ISD::FNEG, DL: dl, VT, Operand: Node->getOperand(Num: 1));
4076 Tmp1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT, N1: Node->getOperand(Num: 0), N2: Tmp1, Flags);
4077 Results.push_back(Elt: Tmp1);
4078 }
4079 break;
4080 }
4081 case ISD::SUB: {
4082 EVT VT = Node->getValueType(ResNo: 0);
4083 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
4084 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
4085 "Don't know how to expand this subtraction!");
4086 Tmp1 = DAG.getNOT(DL: dl, Val: Node->getOperand(Num: 1), VT);
4087 Tmp1 = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Tmp1, N2: DAG.getConstant(Val: 1, DL: dl, VT));
4088 Results.push_back(Elt: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Node->getOperand(Num: 0), N2: Tmp1));
4089 break;
4090 }
4091 case ISD::UREM:
4092 case ISD::SREM:
4093 if (TLI.expandREM(Node, Result&: Tmp1, DAG))
4094 Results.push_back(Elt: Tmp1);
4095 break;
4096 case ISD::UDIV:
4097 case ISD::SDIV: {
4098 bool isSigned = Node->getOpcode() == ISD::SDIV;
4099 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
4100 EVT VT = Node->getValueType(ResNo: 0);
4101 if (TLI.isOperationLegalOrCustom(Op: DivRemOpc, VT)) {
4102 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: VT);
4103 Tmp1 = DAG.getNode(Opcode: DivRemOpc, DL: dl, VTList: VTs, N1: Node->getOperand(Num: 0),
4104 N2: Node->getOperand(Num: 1));
4105 Results.push_back(Elt: Tmp1);
4106 }
4107 break;
4108 }
4109 case ISD::MULHU:
4110 case ISD::MULHS: {
4111 unsigned ExpandOpcode =
4112 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
4113 EVT VT = Node->getValueType(ResNo: 0);
4114 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: VT);
4115
4116 Tmp1 = DAG.getNode(Opcode: ExpandOpcode, DL: dl, VTList: VTs, N1: Node->getOperand(Num: 0),
4117 N2: Node->getOperand(Num: 1));
4118 Results.push_back(Elt: Tmp1.getValue(R: 1));
4119 break;
4120 }
4121 case ISD::UMUL_LOHI:
4122 case ISD::SMUL_LOHI: {
4123 SDValue LHS = Node->getOperand(Num: 0);
4124 SDValue RHS = Node->getOperand(Num: 1);
4125 EVT VT = LHS.getValueType();
4126 unsigned MULHOpcode =
4127 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
4128
4129 if (TLI.isOperationLegalOrCustom(Op: MULHOpcode, VT)) {
4130 Results.push_back(Elt: DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS));
4131 Results.push_back(Elt: DAG.getNode(Opcode: MULHOpcode, DL: dl, VT, N1: LHS, N2: RHS));
4132 break;
4133 }
4134
4135 SmallVector<SDValue, 4> Halves;
4136 EVT HalfType = VT.getHalfSizedIntegerVT(Context&: *DAG.getContext());
4137 assert(TLI.isTypeLegal(HalfType));
4138 if (TLI.expandMUL_LOHI(Opcode: Node->getOpcode(), VT, dl, LHS, RHS, Result&: Halves,
4139 HiLoVT: HalfType, DAG,
4140 Kind: TargetLowering::MulExpansionKind::Always)) {
4141 for (unsigned i = 0; i < 2; ++i) {
4142 SDValue Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: Halves[2 * i]);
4143 SDValue Hi = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Halves[2 * i + 1]);
4144 SDValue Shift =
4145 DAG.getShiftAmountConstant(Val: HalfType.getScalarSizeInBits(), VT, DL: dl);
4146 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT, N1: Hi, N2: Shift);
4147 Results.push_back(Elt: DAG.getNode(Opcode: ISD::OR, DL: dl, VT, N1: Lo, N2: Hi));
4148 }
4149 break;
4150 }
4151 break;
4152 }
4153 case ISD::MUL: {
4154 EVT VT = Node->getValueType(ResNo: 0);
4155 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: VT);
4156 // See if multiply or divide can be lowered using two-result operations.
4157 // We just need the low half of the multiply; try both the signed
4158 // and unsigned forms. If the target supports both SMUL_LOHI and
4159 // UMUL_LOHI, form a preference by checking which forms of plain
4160 // MULH it supports.
4161 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(Op: ISD::SMUL_LOHI, VT);
4162 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(Op: ISD::UMUL_LOHI, VT);
4163 bool HasMULHS = TLI.isOperationLegalOrCustom(Op: ISD::MULHS, VT);
4164 bool HasMULHU = TLI.isOperationLegalOrCustom(Op: ISD::MULHU, VT);
4165 unsigned OpToUse = 0;
4166 if (HasSMUL_LOHI && !HasMULHS) {
4167 OpToUse = ISD::SMUL_LOHI;
4168 } else if (HasUMUL_LOHI && !HasMULHU) {
4169 OpToUse = ISD::UMUL_LOHI;
4170 } else if (HasSMUL_LOHI) {
4171 OpToUse = ISD::SMUL_LOHI;
4172 } else if (HasUMUL_LOHI) {
4173 OpToUse = ISD::UMUL_LOHI;
4174 }
4175 if (OpToUse) {
4176 Results.push_back(Elt: DAG.getNode(Opcode: OpToUse, DL: dl, VTList: VTs, N1: Node->getOperand(Num: 0),
4177 N2: Node->getOperand(Num: 1)));
4178 break;
4179 }
4180
4181 SDValue Lo, Hi;
4182 EVT HalfType = VT.getHalfSizedIntegerVT(Context&: *DAG.getContext());
4183 if (TLI.isOperationLegalOrCustom(Op: ISD::ZERO_EXTEND, VT) &&
4184 TLI.isOperationLegalOrCustom(Op: ISD::ANY_EXTEND, VT) &&
4185 TLI.isOperationLegalOrCustom(Op: ISD::SHL, VT) &&
4186 TLI.isOperationLegalOrCustom(Op: ISD::OR, VT) &&
4187 TLI.expandMUL(N: Node, Lo, Hi, HiLoVT: HalfType, DAG,
4188 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom)) {
4189 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: Lo);
4190 Hi = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Hi);
4191 SDValue Shift =
4192 DAG.getShiftAmountConstant(Val: HalfType.getSizeInBits(), VT, DL: dl);
4193 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT, N1: Hi, N2: Shift);
4194 Results.push_back(Elt: DAG.getNode(Opcode: ISD::OR, DL: dl, VT, N1: Lo, N2: Hi));
4195 }
4196 break;
4197 }
4198 case ISD::FSHL:
4199 case ISD::FSHR:
4200 if (SDValue Expanded = TLI.expandFunnelShift(N: Node, DAG))
4201 Results.push_back(Elt: Expanded);
4202 break;
4203 case ISD::ROTL:
4204 case ISD::ROTR:
4205 if (SDValue Expanded = TLI.expandROT(N: Node, AllowVectorOps: true /*AllowVectorOps*/, DAG))
4206 Results.push_back(Elt: Expanded);
4207 break;
4208 case ISD::CLMUL:
4209 case ISD::CLMULR:
4210 case ISD::CLMULH:
4211 if (SDValue Expanded = TLI.expandCLMUL(N: Node, DAG))
4212 Results.push_back(Elt: Expanded);
4213 break;
4214 case ISD::PEXT:
4215 Results.push_back(Elt: TLI.expandPEXT(N: Node, DAG));
4216 break;
4217 case ISD::PDEP:
4218 Results.push_back(Elt: TLI.expandPDEP(N: Node, DAG));
4219 break;
4220 case ISD::SADDSAT:
4221 case ISD::UADDSAT:
4222 case ISD::SSUBSAT:
4223 case ISD::USUBSAT:
4224 Results.push_back(Elt: TLI.expandAddSubSat(Node, DAG));
4225 break;
4226 case ISD::SCMP:
4227 case ISD::UCMP:
4228 Results.push_back(Elt: TLI.expandCMP(Node, DAG));
4229 break;
4230 case ISD::SSHLSAT:
4231 case ISD::USHLSAT:
4232 Results.push_back(Elt: TLI.expandShlSat(Node, DAG));
4233 break;
4234 case ISD::SMULFIX:
4235 case ISD::SMULFIXSAT:
4236 case ISD::UMULFIX:
4237 case ISD::UMULFIXSAT:
4238 Results.push_back(Elt: TLI.expandFixedPointMul(Node, DAG));
4239 break;
4240 case ISD::SDIVFIX:
4241 case ISD::SDIVFIXSAT:
4242 case ISD::UDIVFIX:
4243 case ISD::UDIVFIXSAT:
4244 if (SDValue V = TLI.expandFixedPointDiv(Opcode: Node->getOpcode(), dl: SDLoc(Node),
4245 LHS: Node->getOperand(Num: 0),
4246 RHS: Node->getOperand(Num: 1),
4247 Scale: Node->getConstantOperandVal(Num: 2),
4248 DAG)) {
4249 Results.push_back(Elt: V);
4250 break;
4251 }
4252 // FIXME: We might want to retry here with a wider type if we fail, if that
4253 // type is legal.
4254 // FIXME: Technically, so long as we only have sdivfixes where BW+Scale is
4255 // <= 128 (which is the case for all of the default Embedded-C types),
4256 // we will only get here with types and scales that we could always expand
4257 // if we were allowed to generate libcalls to division functions of illegal
4258 // type. But we cannot do that.
4259 llvm_unreachable("Cannot expand DIVFIX!");
4260 case ISD::UADDO_CARRY:
4261 case ISD::USUBO_CARRY: {
4262 SDValue LHS = Node->getOperand(Num: 0);
4263 SDValue RHS = Node->getOperand(Num: 1);
4264 SDValue Carry = Node->getOperand(Num: 2);
4265
4266 bool IsAdd = Node->getOpcode() == ISD::UADDO_CARRY;
4267
4268 // Initial add of the 2 operands.
4269 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
4270 EVT VT = LHS.getValueType();
4271 SDValue Sum = DAG.getNode(Opcode: Op, DL: dl, VT, N1: LHS, N2: RHS);
4272
4273 // Initial check for overflow.
4274 EVT CarryType = Node->getValueType(ResNo: 1);
4275 EVT SetCCType = getSetCCResultType(VT: Node->getValueType(ResNo: 0));
4276 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
4277 SDValue Overflow = DAG.getSetCC(DL: dl, VT: SetCCType, LHS: Sum, RHS: LHS, Cond: CC);
4278
4279 // Add of the sum and the carry.
4280 SDValue One = DAG.getConstant(Val: 1, DL: dl, VT);
4281 SDValue CarryExt =
4282 DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: DAG.getZExtOrTrunc(Op: Carry, DL: dl, VT), N2: One);
4283 SDValue Sum2 = DAG.getNode(Opcode: Op, DL: dl, VT, N1: Sum, N2: CarryExt);
4284
4285 // Second check for overflow. If we are adding, we can only overflow if the
4286 // initial sum is all 1s ang the carry is set, resulting in a new sum of 0.
4287 // If we are subtracting, we can only overflow if the initial sum is 0 and
4288 // the carry is set, resulting in a new sum of all 1s.
4289 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
4290 SDValue Overflow2 =
4291 IsAdd ? DAG.getSetCC(DL: dl, VT: SetCCType, LHS: Sum2, RHS: Zero, Cond: ISD::SETEQ)
4292 : DAG.getSetCC(DL: dl, VT: SetCCType, LHS: Sum, RHS: Zero, Cond: ISD::SETEQ);
4293 Overflow2 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: SetCCType, N1: Overflow2,
4294 N2: DAG.getZExtOrTrunc(Op: Carry, DL: dl, VT: SetCCType));
4295
4296 SDValue ResultCarry =
4297 DAG.getNode(Opcode: ISD::OR, DL: dl, VT: SetCCType, N1: Overflow, N2: Overflow2);
4298
4299 Results.push_back(Elt: Sum2);
4300 Results.push_back(Elt: DAG.getBoolExtOrTrunc(Op: ResultCarry, SL: dl, VT: CarryType, OpVT: VT));
4301 break;
4302 }
4303 case ISD::SADDO:
4304 case ISD::SSUBO: {
4305 SDValue Result, Overflow;
4306 TLI.expandSADDSUBO(Node, Result, Overflow, DAG);
4307 Results.push_back(Elt: Result);
4308 Results.push_back(Elt: Overflow);
4309 break;
4310 }
4311 case ISD::UADDO:
4312 case ISD::USUBO: {
4313 SDValue Result, Overflow;
4314 TLI.expandUADDSUBO(Node, Result, Overflow, DAG);
4315 Results.push_back(Elt: Result);
4316 Results.push_back(Elt: Overflow);
4317 break;
4318 }
4319 case ISD::UMULO:
4320 case ISD::SMULO: {
4321 SDValue Result, Overflow;
4322 if (TLI.expandMULO(Node, Result, Overflow, DAG)) {
4323 Results.push_back(Elt: Result);
4324 Results.push_back(Elt: Overflow);
4325 }
4326 break;
4327 }
4328 case ISD::BUILD_PAIR: {
4329 EVT PairTy = Node->getValueType(ResNo: 0);
4330 Tmp1 = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: PairTy, Operand: Node->getOperand(Num: 0));
4331 Tmp2 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: PairTy, Operand: Node->getOperand(Num: 1));
4332 Tmp2 = DAG.getNode(
4333 Opcode: ISD::SHL, DL: dl, VT: PairTy, N1: Tmp2,
4334 N2: DAG.getShiftAmountConstant(Val: PairTy.getSizeInBits() / 2, VT: PairTy, DL: dl));
4335 Results.push_back(Elt: DAG.getNode(Opcode: ISD::OR, DL: dl, VT: PairTy, N1: Tmp1, N2: Tmp2));
4336 break;
4337 }
4338 case ISD::SELECT:
4339 Tmp1 = Node->getOperand(Num: 0);
4340 Tmp2 = Node->getOperand(Num: 1);
4341 Tmp3 = Node->getOperand(Num: 2);
4342 if (Tmp1.getOpcode() == ISD::SETCC) {
4343 Tmp1 = DAG.getSelectCC(
4344 DL: dl, LHS: Tmp1.getOperand(i: 0), RHS: Tmp1.getOperand(i: 1), True: Tmp2, False: Tmp3,
4345 Cond: cast<CondCodeSDNode>(Val: Tmp1.getOperand(i: 2))->get(), Flags: Node->getFlags());
4346 } else {
4347 Tmp1 =
4348 DAG.getSelectCC(DL: dl, LHS: Tmp1, RHS: DAG.getConstant(Val: 0, DL: dl, VT: Tmp1.getValueType()),
4349 True: Tmp2, False: Tmp3, Cond: ISD::SETNE, Flags: Node->getFlags());
4350 }
4351 Results.push_back(Elt: Tmp1);
4352 break;
4353 case ISD::BR_JT: {
4354 SDValue Chain = Node->getOperand(Num: 0);
4355 SDValue Table = Node->getOperand(Num: 1);
4356 SDValue Index = Node->getOperand(Num: 2);
4357 int JTI = cast<JumpTableSDNode>(Val: Table.getNode())->getIndex();
4358
4359 const DataLayout &TD = DAG.getDataLayout();
4360 EVT PTy = TLI.getPointerTy(DL: TD);
4361
4362 unsigned EntrySize =
4363 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
4364
4365 // For power-of-two jumptable entry sizes convert multiplication to a shift.
4366 // This transformation needs to be done here since otherwise the MIPS
4367 // backend will end up emitting a three instruction multiply sequence
4368 // instead of a single shift and MSP430 will call a runtime function.
4369 if (llvm::isPowerOf2_32(Value: EntrySize))
4370 Index = DAG.getNode(
4371 Opcode: ISD::SHL, DL: dl, VT: Index.getValueType(), N1: Index,
4372 N2: DAG.getConstant(Val: llvm::Log2_32(Value: EntrySize), DL: dl, VT: Index.getValueType()));
4373 else
4374 Index = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: Index.getValueType(), N1: Index,
4375 N2: DAG.getConstant(Val: EntrySize, DL: dl, VT: Index.getValueType()));
4376 SDValue Addr = DAG.getMemBasePlusOffset(Base: Table, Offset: Index, DL: dl);
4377
4378 EVT MemVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: EntrySize * 8);
4379 SDValue LD = DAG.getExtLoad(
4380 ExtType: ISD::SEXTLOAD, dl, VT: PTy, Chain, Ptr: Addr,
4381 PtrInfo: MachinePointerInfo::getJumpTable(MF&: DAG.getMachineFunction()), MemVT);
4382 Addr = LD;
4383 if (TLI.isJumpTableRelative()) {
4384 // For PIC, the sequence is:
4385 // BRIND(RelocBase + load(Jumptable + index))
4386 // RelocBase can be JumpTable, GOT or some sort of global base.
4387 Addr = DAG.getMemBasePlusOffset(Base: TLI.getPICJumpTableRelocBase(Table, DAG),
4388 Offset: Addr, DL: dl);
4389 }
4390
4391 Tmp1 = TLI.expandIndirectJTBranch(dl, Value: LD.getValue(R: 1), Addr, JTI, DAG);
4392 Results.push_back(Elt: Tmp1);
4393 break;
4394 }
4395 case ISD::BRCOND:
4396 // Expand brcond's setcc into its constituent parts and create a BR_CC
4397 // Node.
4398 Tmp1 = Node->getOperand(Num: 0);
4399 Tmp2 = Node->getOperand(Num: 1);
4400 if (Tmp2.getOpcode() == ISD::SETCC &&
4401 TLI.isOperationLegalOrCustom(Op: ISD::BR_CC,
4402 VT: Tmp2.getOperand(i: 0).getValueType())) {
4403 Tmp1 = DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: MVT::Other, N1: Tmp1, N2: Tmp2.getOperand(i: 2),
4404 N3: Tmp2.getOperand(i: 0), N4: Tmp2.getOperand(i: 1),
4405 N5: Node->getOperand(Num: 2));
4406 } else {
4407 // We test only the i1 bit. Skip the AND if UNDEF or another AND.
4408 if (Tmp2.isUndef() ||
4409 (Tmp2.getOpcode() == ISD::AND && isOneConstant(V: Tmp2.getOperand(i: 1))))
4410 Tmp3 = Tmp2;
4411 else
4412 Tmp3 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: Tmp2.getValueType(), N1: Tmp2,
4413 N2: DAG.getConstant(Val: 1, DL: dl, VT: Tmp2.getValueType()));
4414 Tmp1 = DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: MVT::Other, N1: Tmp1,
4415 N2: DAG.getCondCode(Cond: ISD::SETNE), N3: Tmp3,
4416 N4: DAG.getConstant(Val: 0, DL: dl, VT: Tmp3.getValueType()),
4417 N5: Node->getOperand(Num: 2));
4418 }
4419 Results.push_back(Elt: Tmp1);
4420 break;
4421 case ISD::SETCC:
4422 case ISD::VP_SETCC:
4423 case ISD::STRICT_FSETCC:
4424 case ISD::STRICT_FSETCCS: {
4425 bool IsVP = Node->getOpcode() == ISD::VP_SETCC;
4426 bool IsStrict = Node->getOpcode() == ISD::STRICT_FSETCC ||
4427 Node->getOpcode() == ISD::STRICT_FSETCCS;
4428 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS;
4429 SDValue Chain = IsStrict ? Node->getOperand(Num: 0) : SDValue();
4430 unsigned Offset = IsStrict ? 1 : 0;
4431 Tmp1 = Node->getOperand(Num: 0 + Offset);
4432 Tmp2 = Node->getOperand(Num: 1 + Offset);
4433 Tmp3 = Node->getOperand(Num: 2 + Offset);
4434 SDValue Mask, EVL;
4435 if (IsVP) {
4436 Mask = Node->getOperand(Num: 3 + Offset);
4437 EVL = Node->getOperand(Num: 4 + Offset);
4438 }
4439 bool Legalized = TLI.LegalizeSetCCCondCode(
4440 DAG, VT: Node->getValueType(ResNo: 0), LHS&: Tmp1, RHS&: Tmp2, CC&: Tmp3, Mask, EVL, NeedInvert, dl,
4441 Chain, IsSignaling);
4442
4443 if (Legalized) {
4444 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
4445 // condition code, create a new SETCC node.
4446 if (Tmp3.getNode()) {
4447 if (IsStrict) {
4448 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VTList: Node->getVTList(),
4449 Ops: {Chain, Tmp1, Tmp2, Tmp3}, Flags: Node->getFlags());
4450 Chain = Tmp1.getValue(R: 1);
4451 } else if (IsVP) {
4452 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: Node->getValueType(ResNo: 0),
4453 Ops: {Tmp1, Tmp2, Tmp3, Mask, EVL}, Flags: Node->getFlags());
4454 } else {
4455 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
4456 N2: Tmp2, N3: Tmp3, Flags: Node->getFlags());
4457 }
4458 }
4459
4460 // If we expanded the SETCC by inverting the condition code, then wrap
4461 // the existing SETCC in a NOT to restore the intended condition.
4462 if (NeedInvert) {
4463 if (!IsVP)
4464 Tmp1 = DAG.getLogicalNOT(DL: dl, Val: Tmp1, VT: Tmp1->getValueType(ResNo: 0));
4465 else
4466 Tmp1 =
4467 DAG.getVPLogicalNOT(DL: dl, Val: Tmp1, Mask, EVL, VT: Tmp1->getValueType(ResNo: 0));
4468 }
4469
4470 Results.push_back(Elt: Tmp1);
4471 if (IsStrict)
4472 Results.push_back(Elt: Chain);
4473
4474 break;
4475 }
4476
4477 // FIXME: It seems Legalized is false iff CCCode is Legal. I don't
4478 // understand if this code is useful for strict nodes.
4479 assert(!IsStrict && "Don't know how to expand for strict nodes.");
4480
4481 // Otherwise, SETCC for the given comparison type must be completely
4482 // illegal; expand it into a SELECT_CC.
4483 // FIXME: This drops the mask/evl for VP_SETCC.
4484 EVT VT = Node->getValueType(ResNo: 0);
4485 EVT Tmp1VT = Tmp1.getValueType();
4486 Tmp1 = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT, N1: Tmp1, N2: Tmp2,
4487 N3: DAG.getBoolConstant(V: true, DL: dl, VT, OpVT: Tmp1VT),
4488 N4: DAG.getBoolConstant(V: false, DL: dl, VT, OpVT: Tmp1VT), N5: Tmp3,
4489 Flags: Node->getFlags());
4490 Results.push_back(Elt: Tmp1);
4491 break;
4492 }
4493 case ISD::SELECT_CC: {
4494 // TODO: need to add STRICT_SELECT_CC and STRICT_SELECT_CCS
4495 Tmp1 = Node->getOperand(Num: 0); // LHS
4496 Tmp2 = Node->getOperand(Num: 1); // RHS
4497 Tmp3 = Node->getOperand(Num: 2); // True
4498 Tmp4 = Node->getOperand(Num: 3); // False
4499 EVT VT = Node->getValueType(ResNo: 0);
4500 SDValue Chain;
4501 SDValue CC = Node->getOperand(Num: 4);
4502 ISD::CondCode CCOp = cast<CondCodeSDNode>(Val&: CC)->get();
4503
4504 if (TLI.isCondCodeLegalOrCustom(CC: CCOp, VT: Tmp1.getSimpleValueType())) {
4505 // If the condition code is legal, then we need to expand this
4506 // node using SETCC and SELECT.
4507 EVT CmpVT = Tmp1.getValueType();
4508 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
4509 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
4510 "expanded.");
4511 EVT CCVT = getSetCCResultType(VT: CmpVT);
4512 SDValue Cond = DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: CCVT, N1: Tmp1, N2: Tmp2, N3: CC, Flags: Node->getFlags());
4513 Results.push_back(
4514 Elt: DAG.getSelect(DL: dl, VT, Cond, LHS: Tmp3, RHS: Tmp4, Flags: Node->getFlags()));
4515 break;
4516 }
4517
4518 // SELECT_CC is legal, so the condition code must not be.
4519 bool Legalized = false;
4520 // Try to legalize by inverting the condition. This is for targets that
4521 // might support an ordered version of a condition, but not the unordered
4522 // version (or vice versa).
4523 ISD::CondCode InvCC = ISD::getSetCCInverse(Operation: CCOp, Type: Tmp1.getValueType());
4524 if (TLI.isCondCodeLegalOrCustom(CC: InvCC, VT: Tmp1.getSimpleValueType())) {
4525 // Use the new condition code and swap true and false
4526 Legalized = true;
4527 Tmp1 =
4528 DAG.getSelectCC(DL: dl, LHS: Tmp1, RHS: Tmp2, True: Tmp4, False: Tmp3, Cond: InvCC, Flags: Node->getFlags());
4529 } else {
4530 // If The inverse is not legal, then try to swap the arguments using
4531 // the inverse condition code.
4532 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(Operation: InvCC);
4533 if (TLI.isCondCodeLegalOrCustom(CC: SwapInvCC, VT: Tmp1.getSimpleValueType())) {
4534 // The swapped inverse condition is legal, so swap true and false,
4535 // lhs and rhs.
4536 Legalized = true;
4537 Tmp1 = DAG.getSelectCC(DL: dl, LHS: Tmp2, RHS: Tmp1, True: Tmp4, False: Tmp3, Cond: SwapInvCC,
4538 Flags: Node->getFlags());
4539 }
4540 }
4541
4542 if (!Legalized) {
4543 Legalized = TLI.LegalizeSetCCCondCode(
4544 DAG, VT: getSetCCResultType(VT: Tmp1.getValueType()), LHS&: Tmp1, RHS&: Tmp2, CC,
4545 /*Mask*/ SDValue(), /*EVL*/ SDValue(), NeedInvert, dl, Chain);
4546
4547 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
4548
4549 // If we expanded the SETCC by inverting the condition code, then swap
4550 // the True/False operands to match.
4551 if (NeedInvert)
4552 std::swap(a&: Tmp3, b&: Tmp4);
4553
4554 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
4555 // condition code, create a new SELECT_CC node.
4556 if (CC.getNode()) {
4557 Tmp1 = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
4558 N2: Tmp2, N3: Tmp3, N4: Tmp4, N5: CC, Flags: Node->getFlags());
4559 } else {
4560 Tmp2 = DAG.getConstant(Val: 0, DL: dl, VT: Tmp1.getValueType());
4561 CC = DAG.getCondCode(Cond: ISD::SETNE);
4562 Tmp1 = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
4563 N2: Tmp2, N3: Tmp3, N4: Tmp4, N5: CC, Flags: Node->getFlags());
4564 }
4565 }
4566 Results.push_back(Elt: Tmp1);
4567 break;
4568 }
4569 case ISD::BR_CC: {
4570 // TODO: need to add STRICT_BR_CC and STRICT_BR_CCS
4571 SDValue Chain;
4572 Tmp1 = Node->getOperand(Num: 0); // Chain
4573 Tmp2 = Node->getOperand(Num: 2); // LHS
4574 Tmp3 = Node->getOperand(Num: 3); // RHS
4575 Tmp4 = Node->getOperand(Num: 1); // CC
4576
4577 bool Legalized = TLI.LegalizeSetCCCondCode(
4578 DAG, VT: getSetCCResultType(VT: Tmp2.getValueType()), LHS&: Tmp2, RHS&: Tmp3, CC&: Tmp4,
4579 /*Mask*/ SDValue(), /*EVL*/ SDValue(), NeedInvert, dl, Chain);
4580 (void)Legalized;
4581 assert(Legalized && "Can't legalize BR_CC with legal condition!");
4582
4583 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4584 // node.
4585 if (Tmp4.getNode()) {
4586 assert(!NeedInvert && "Don't know how to invert BR_CC!");
4587
4588 Tmp1 = DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
4589 N2: Tmp4, N3: Tmp2, N4: Tmp3, N5: Node->getOperand(Num: 4));
4590 } else {
4591 Tmp3 = DAG.getConstant(Val: 0, DL: dl, VT: Tmp2.getValueType());
4592 Tmp4 = DAG.getCondCode(Cond: NeedInvert ? ISD::SETEQ : ISD::SETNE);
4593 Tmp1 = DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1, N2: Tmp4,
4594 N3: Tmp2, N4: Tmp3, N5: Node->getOperand(Num: 4));
4595 }
4596 Results.push_back(Elt: Tmp1);
4597 break;
4598 }
4599 case ISD::BUILD_VECTOR:
4600 Results.push_back(Elt: ExpandBUILD_VECTOR(Node));
4601 break;
4602 case ISD::SPLAT_VECTOR:
4603 Results.push_back(Elt: ExpandSPLAT_VECTOR(Node));
4604 break;
4605 case ISD::SRA:
4606 case ISD::SRL:
4607 case ISD::SHL: {
4608 // Scalarize vector SRA/SRL/SHL.
4609 EVT VT = Node->getValueType(ResNo: 0);
4610 assert(VT.isVector() && "Unable to legalize non-vector shift");
4611 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4612 unsigned NumElem = VT.getVectorNumElements();
4613
4614 SmallVector<SDValue, 8> Scalars;
4615 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4616 SDValue Ex =
4617 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: VT.getScalarType(),
4618 N1: Node->getOperand(Num: 0), N2: DAG.getVectorIdxConstant(Val: Idx, DL: dl));
4619 SDValue Sh =
4620 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: VT.getScalarType(),
4621 N1: Node->getOperand(Num: 1), N2: DAG.getVectorIdxConstant(Val: Idx, DL: dl));
4622 Scalars.push_back(Elt: DAG.getNode(Opcode: Node->getOpcode(), DL: dl,
4623 VT: VT.getScalarType(), N1: Ex, N2: Sh));
4624 }
4625
4626 SDValue Result = DAG.getBuildVector(VT: Node->getValueType(ResNo: 0), DL: dl, Ops: Scalars);
4627 Results.push_back(Elt: Result);
4628 break;
4629 }
4630 case ISD::VECREDUCE_FADD:
4631 case ISD::VECREDUCE_FMUL:
4632 case ISD::VECREDUCE_ADD:
4633 case ISD::VECREDUCE_MUL:
4634 case ISD::VECREDUCE_AND:
4635 case ISD::VECREDUCE_OR:
4636 case ISD::VECREDUCE_XOR:
4637 case ISD::VECREDUCE_SMAX:
4638 case ISD::VECREDUCE_SMIN:
4639 case ISD::VECREDUCE_UMAX:
4640 case ISD::VECREDUCE_UMIN:
4641 case ISD::VECREDUCE_FMAX:
4642 case ISD::VECREDUCE_FMIN:
4643 case ISD::VECREDUCE_FMAXIMUM:
4644 case ISD::VECREDUCE_FMINIMUM:
4645 Results.push_back(Elt: TLI.expandVecReduce(Node, DAG));
4646 break;
4647 case ISD::VP_CTTZ_ELTS:
4648 case ISD::VP_CTTZ_ELTS_ZERO_POISON:
4649 Results.push_back(Elt: TLI.expandVPCTTZElements(N: Node, DAG));
4650 break;
4651 case ISD::CLEAR_CACHE:
4652 // The default expansion of llvm.clear_cache is simply a no-op for those
4653 // targets where it is not needed.
4654 Results.push_back(Elt: Node->getOperand(Num: 0));
4655 break;
4656 case ISD::LRINT:
4657 case ISD::LLRINT: {
4658 SDValue Arg = Node->getOperand(Num: 0);
4659 EVT ArgVT = Arg.getValueType();
4660 EVT ResVT = Node->getValueType(ResNo: 0);
4661 SDLoc DL(Node);
4662 SDValue RoundNode = DAG.getNode(Opcode: ISD::FRINT, DL, VT: ArgVT, Operand: Arg);
4663 SDValue ConvertNode = DAG.getNode(Opcode: ISD::FP_TO_SINT, DL, VT: ResVT, Operand: RoundNode);
4664 // Non-deterministic results are equivalent to freeze poison.
4665 Results.push_back(Elt: DAG.getFreeze(V: ConvertNode));
4666 break;
4667 }
4668 case ISD::ADDRSPACECAST:
4669 Results.push_back(Elt: DAG.UnrollVectorOp(N: Node));
4670 break;
4671 case ISD::GLOBAL_OFFSET_TABLE:
4672 case ISD::GlobalAddress:
4673 case ISD::GlobalTLSAddress:
4674 case ISD::ExternalSymbol:
4675 case ISD::ConstantPool:
4676 case ISD::JumpTable:
4677 case ISD::INTRINSIC_W_CHAIN:
4678 case ISD::INTRINSIC_WO_CHAIN:
4679 case ISD::INTRINSIC_VOID:
4680 // FIXME: Custom lowering for these operations shouldn't return null!
4681 // Return true so that we don't call ConvertNodeToLibcall which also won't
4682 // do anything.
4683 return true;
4684 }
4685
4686 if (!TLI.isStrictFPEnabled() && Results.empty() && Node->isStrictFPOpcode()) {
4687 // FIXME: We were asked to expand a strict floating-point operation,
4688 // but there is currently no expansion implemented that would preserve
4689 // the "strict" properties. For now, we just fall back to the non-strict
4690 // version if that is legal on the target. The actual mutation of the
4691 // operation will happen in SelectionDAGISel::DoInstructionSelection.
4692 switch (Node->getOpcode()) {
4693 default:
4694 if (TLI.getStrictFPOperationAction(Op: Node->getOpcode(),
4695 VT: Node->getValueType(ResNo: 0))
4696 == TargetLowering::Legal)
4697 return true;
4698 break;
4699 case ISD::STRICT_FSUB: {
4700 if (TLI.getStrictFPOperationAction(
4701 Op: ISD::STRICT_FSUB, VT: Node->getValueType(ResNo: 0)) == TargetLowering::Legal)
4702 return true;
4703 if (TLI.getStrictFPOperationAction(
4704 Op: ISD::STRICT_FADD, VT: Node->getValueType(ResNo: 0)) != TargetLowering::Legal)
4705 break;
4706
4707 EVT VT = Node->getValueType(ResNo: 0);
4708 const SDNodeFlags Flags = Node->getFlags();
4709 SDValue Neg = DAG.getNode(Opcode: ISD::FNEG, DL: dl, VT, Operand: Node->getOperand(Num: 2), Flags);
4710 SDValue Fadd = DAG.getNode(Opcode: ISD::STRICT_FADD, DL: dl, VTList: Node->getVTList(),
4711 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1), Neg},
4712 Flags);
4713
4714 Results.push_back(Elt: Fadd);
4715 Results.push_back(Elt: Fadd.getValue(R: 1));
4716 break;
4717 }
4718 case ISD::STRICT_SINT_TO_FP:
4719 case ISD::STRICT_UINT_TO_FP:
4720 case ISD::STRICT_LRINT:
4721 case ISD::STRICT_LLRINT:
4722 case ISD::STRICT_LROUND:
4723 case ISD::STRICT_LLROUND:
4724 // These are registered by the operand type instead of the value
4725 // type. Reflect that here.
4726 if (TLI.getStrictFPOperationAction(Op: Node->getOpcode(),
4727 VT: Node->getOperand(Num: 1).getValueType())
4728 == TargetLowering::Legal)
4729 return true;
4730 break;
4731 }
4732 }
4733
4734 // Replace the original node with the legalized result.
4735 if (Results.empty()) {
4736 LLVM_DEBUG(dbgs() << "Cannot expand node\n");
4737 return false;
4738 }
4739
4740 LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
4741 ReplaceNode(Old: Node, New: Results.data());
4742 return true;
4743}
4744
4745/// Return if we can use the FAST_* variant of a math libcall for the node.
4746/// FIXME: This is just guessing, we probably should have unique specific sets
4747/// flags required per libcall.
4748static bool canUseFastMathLibcall(const SDNode *Node) {
4749 // FIXME: Probably should define fast to respect nan/inf and only be
4750 // approximate functions.
4751
4752 SDNodeFlags Flags = Node->getFlags();
4753 return Flags.hasApproximateFuncs() && Flags.hasNoNaNs() &&
4754 Flags.hasNoInfs() && Flags.hasNoSignedZeros();
4755}
4756
4757void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
4758 LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
4759 SmallVector<SDValue, 8> Results;
4760 SDLoc dl(Node);
4761 TargetLowering::MakeLibCallOptions CallOptions;
4762 CallOptions.IsPostTypeLegalization = true;
4763 // FIXME: Check flags on the node to see if we can use a finite call.
4764 unsigned Opc = Node->getOpcode();
4765 switch (Opc) {
4766 case ISD::ATOMIC_FENCE: {
4767 // If the target didn't lower this, lower it to '__sync_synchronize()' call
4768 // FIXME: handle "fence singlethread" more efficiently.
4769 TargetLowering::ArgListTy Args;
4770
4771 TargetLowering::CallLoweringInfo CLI(DAG);
4772 CLI.setDebugLoc(dl)
4773 .setChain(Node->getOperand(Num: 0))
4774 .setLibCallee(
4775 CC: CallingConv::C, ResultType: Type::getVoidTy(C&: *DAG.getContext()),
4776 Target: DAG.getExternalSymbol(Sym: "__sync_synchronize",
4777 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
4778 ArgsList: std::move(Args));
4779
4780 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4781
4782 Results.push_back(Elt: CallResult.second);
4783 break;
4784 }
4785 // By default, atomic intrinsics are marked Legal and lowered. Targets
4786 // which don't support them directly, however, may want libcalls, in which
4787 // case they mark them Expand, and we get here.
4788 case ISD::ATOMIC_SWAP:
4789 case ISD::ATOMIC_LOAD_ADD:
4790 case ISD::ATOMIC_LOAD_SUB:
4791 case ISD::ATOMIC_LOAD_AND:
4792 case ISD::ATOMIC_LOAD_CLR:
4793 case ISD::ATOMIC_LOAD_OR:
4794 case ISD::ATOMIC_LOAD_XOR:
4795 case ISD::ATOMIC_LOAD_NAND:
4796 case ISD::ATOMIC_LOAD_MIN:
4797 case ISD::ATOMIC_LOAD_MAX:
4798 case ISD::ATOMIC_LOAD_UMIN:
4799 case ISD::ATOMIC_LOAD_UMAX:
4800 case ISD::ATOMIC_CMP_SWAP: {
4801 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
4802 AtomicOrdering Order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
4803 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order, VT);
4804 EVT RetVT = Node->getValueType(ResNo: 0);
4805 SmallVector<SDValue, 4> Ops;
4806 if (DAG.getLibcalls().getLibcallImpl(Call: LC) != RTLIB::Unsupported) {
4807 // If outline atomic available, prepare its arguments and expand.
4808 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
4809 Ops.push_back(Elt: Node->getOperand(Num: 1));
4810
4811 } else {
4812 LC = RTLIB::getSYNC(Opc, VT);
4813 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
4814 "Unexpected atomic op or value type!");
4815 // Arguments for expansion to sync libcall
4816 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
4817 }
4818 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
4819 Ops, CallOptions,
4820 dl: SDLoc(Node),
4821 Chain: Node->getOperand(Num: 0));
4822 Results.push_back(Elt: Tmp.first);
4823 Results.push_back(Elt: Tmp.second);
4824 break;
4825 }
4826 case ISD::TRAP: {
4827 // If this operation is not supported, lower it to 'abort()' call
4828 TargetLowering::ArgListTy Args;
4829 TargetLowering::CallLoweringInfo CLI(DAG);
4830 CLI.setDebugLoc(dl)
4831 .setChain(Node->getOperand(Num: 0))
4832 .setLibCallee(CC: CallingConv::C, ResultType: Type::getVoidTy(C&: *DAG.getContext()),
4833 Target: DAG.getExternalSymbol(
4834 Sym: "abort", VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
4835 ArgsList: std::move(Args));
4836 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4837
4838 Results.push_back(Elt: CallResult.second);
4839 break;
4840 }
4841 case ISD::CLEAR_CACHE: {
4842 SDValue InputChain = Node->getOperand(Num: 0);
4843 SDValue StartVal = Node->getOperand(Num: 1);
4844 SDValue EndVal = Node->getOperand(Num: 2);
4845 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
4846 DAG, LC: RTLIB::CLEAR_CACHE, RetVT: MVT::isVoid, Ops: {StartVal, EndVal}, CallOptions,
4847 dl: SDLoc(Node), Chain: InputChain);
4848 Results.push_back(Elt: Tmp.second);
4849 break;
4850 }
4851 case ISD::FMINNUM:
4852 case ISD::STRICT_FMINNUM:
4853 ExpandFPLibCall(Node, Call_F32: RTLIB::FMIN_F32, Call_F64: RTLIB::FMIN_F64,
4854 Call_F80: RTLIB::FMIN_F80, Call_F128: RTLIB::FMIN_F128,
4855 Call_PPCF128: RTLIB::FMIN_PPCF128, Results);
4856 break;
4857 // FIXME: We do not have libcalls for FMAXIMUM and FMINIMUM. So, we cannot use
4858 // libcall legalization for these nodes, but there is no default expasion for
4859 // these nodes either (see PR63267 for example).
4860 case ISD::FMAXNUM:
4861 case ISD::STRICT_FMAXNUM:
4862 ExpandFPLibCall(Node, Call_F32: RTLIB::FMAX_F32, Call_F64: RTLIB::FMAX_F64,
4863 Call_F80: RTLIB::FMAX_F80, Call_F128: RTLIB::FMAX_F128,
4864 Call_PPCF128: RTLIB::FMAX_PPCF128, Results);
4865 break;
4866 case ISD::FMINIMUMNUM:
4867 ExpandFPLibCall(Node, Call_F32: RTLIB::FMINIMUM_NUM_F32, Call_F64: RTLIB::FMINIMUM_NUM_F64,
4868 Call_F80: RTLIB::FMINIMUM_NUM_F80, Call_F128: RTLIB::FMINIMUM_NUM_F128,
4869 Call_PPCF128: RTLIB::FMINIMUM_NUM_PPCF128, Results);
4870 break;
4871 case ISD::FMAXIMUMNUM:
4872 ExpandFPLibCall(Node, Call_F32: RTLIB::FMAXIMUM_NUM_F32, Call_F64: RTLIB::FMAXIMUM_NUM_F64,
4873 Call_F80: RTLIB::FMAXIMUM_NUM_F80, Call_F128: RTLIB::FMAXIMUM_NUM_F128,
4874 Call_PPCF128: RTLIB::FMAXIMUM_NUM_PPCF128, Results);
4875 break;
4876 case ISD::FSQRT:
4877 case ISD::STRICT_FSQRT: {
4878 // FIXME: Probably should define fast to respect nan/inf and only be
4879 // approximate functions.
4880 ExpandFastFPLibCall(Node, IsFast: canUseFastMathLibcall(Node),
4881 Call_F32: {RTLIB::FAST_SQRT_F32, RTLIB::SQRT_F32},
4882 Call_F64: {RTLIB::FAST_SQRT_F64, RTLIB::SQRT_F64},
4883 Call_F80: {RTLIB::FAST_SQRT_F80, RTLIB::SQRT_F80},
4884 Call_F128: {RTLIB::FAST_SQRT_F128, RTLIB::SQRT_F128},
4885 Call_PPCF128: {RTLIB::FAST_SQRT_PPCF128, RTLIB::SQRT_PPCF128},
4886 Results);
4887 break;
4888 }
4889 case ISD::FCBRT:
4890 ExpandFPLibCall(Node, Call_F32: RTLIB::CBRT_F32, Call_F64: RTLIB::CBRT_F64,
4891 Call_F80: RTLIB::CBRT_F80, Call_F128: RTLIB::CBRT_F128,
4892 Call_PPCF128: RTLIB::CBRT_PPCF128, Results);
4893 break;
4894 case ISD::FSIN:
4895 case ISD::STRICT_FSIN:
4896 ExpandFPLibCall(Node, Call_F32: RTLIB::SIN_F32, Call_F64: RTLIB::SIN_F64,
4897 Call_F80: RTLIB::SIN_F80, Call_F128: RTLIB::SIN_F128,
4898 Call_PPCF128: RTLIB::SIN_PPCF128, Results);
4899 break;
4900 case ISD::FCOS:
4901 case ISD::STRICT_FCOS:
4902 ExpandFPLibCall(Node, Call_F32: RTLIB::COS_F32, Call_F64: RTLIB::COS_F64,
4903 Call_F80: RTLIB::COS_F80, Call_F128: RTLIB::COS_F128,
4904 Call_PPCF128: RTLIB::COS_PPCF128, Results);
4905 break;
4906 case ISD::FTAN:
4907 case ISD::STRICT_FTAN:
4908 ExpandFPLibCall(Node, Call_F32: RTLIB::TAN_F32, Call_F64: RTLIB::TAN_F64, Call_F80: RTLIB::TAN_F80,
4909 Call_F128: RTLIB::TAN_F128, Call_PPCF128: RTLIB::TAN_PPCF128, Results);
4910 break;
4911 case ISD::FASIN:
4912 case ISD::STRICT_FASIN:
4913 ExpandFPLibCall(Node, Call_F32: RTLIB::ASIN_F32, Call_F64: RTLIB::ASIN_F64, Call_F80: RTLIB::ASIN_F80,
4914 Call_F128: RTLIB::ASIN_F128, Call_PPCF128: RTLIB::ASIN_PPCF128, Results);
4915 break;
4916 case ISD::FACOS:
4917 case ISD::STRICT_FACOS:
4918 ExpandFPLibCall(Node, Call_F32: RTLIB::ACOS_F32, Call_F64: RTLIB::ACOS_F64, Call_F80: RTLIB::ACOS_F80,
4919 Call_F128: RTLIB::ACOS_F128, Call_PPCF128: RTLIB::ACOS_PPCF128, Results);
4920 break;
4921 case ISD::FATAN:
4922 case ISD::STRICT_FATAN:
4923 ExpandFPLibCall(Node, Call_F32: RTLIB::ATAN_F32, Call_F64: RTLIB::ATAN_F64, Call_F80: RTLIB::ATAN_F80,
4924 Call_F128: RTLIB::ATAN_F128, Call_PPCF128: RTLIB::ATAN_PPCF128, Results);
4925 break;
4926 case ISD::FATAN2:
4927 case ISD::STRICT_FATAN2:
4928 ExpandFPLibCall(Node, Call_F32: RTLIB::ATAN2_F32, Call_F64: RTLIB::ATAN2_F64, Call_F80: RTLIB::ATAN2_F80,
4929 Call_F128: RTLIB::ATAN2_F128, Call_PPCF128: RTLIB::ATAN2_PPCF128, Results);
4930 break;
4931 case ISD::FSINH:
4932 case ISD::STRICT_FSINH:
4933 ExpandFPLibCall(Node, Call_F32: RTLIB::SINH_F32, Call_F64: RTLIB::SINH_F64, Call_F80: RTLIB::SINH_F80,
4934 Call_F128: RTLIB::SINH_F128, Call_PPCF128: RTLIB::SINH_PPCF128, Results);
4935 break;
4936 case ISD::FCOSH:
4937 case ISD::STRICT_FCOSH:
4938 ExpandFPLibCall(Node, Call_F32: RTLIB::COSH_F32, Call_F64: RTLIB::COSH_F64, Call_F80: RTLIB::COSH_F80,
4939 Call_F128: RTLIB::COSH_F128, Call_PPCF128: RTLIB::COSH_PPCF128, Results);
4940 break;
4941 case ISD::FTANH:
4942 case ISD::STRICT_FTANH:
4943 ExpandFPLibCall(Node, Call_F32: RTLIB::TANH_F32, Call_F64: RTLIB::TANH_F64, Call_F80: RTLIB::TANH_F80,
4944 Call_F128: RTLIB::TANH_F128, Call_PPCF128: RTLIB::TANH_PPCF128, Results);
4945 break;
4946 case ISD::FSINCOS:
4947 case ISD::FSINCOSPI: {
4948 EVT VT = Node->getValueType(ResNo: 0);
4949
4950 if (Node->getOpcode() == ISD::FSINCOS) {
4951 RTLIB::Libcall SincosStret = RTLIB::getSINCOS_STRET(RetVT: VT);
4952 if (SincosStret != RTLIB::UNKNOWN_LIBCALL) {
4953 if (SDValue Expanded = ExpandSincosStretLibCall(Node)) {
4954 Results.push_back(Elt: Expanded);
4955 Results.push_back(Elt: Expanded.getValue(R: 1));
4956 break;
4957 }
4958 }
4959 }
4960
4961 RTLIB::Libcall LC = Node->getOpcode() == ISD::FSINCOS
4962 ? RTLIB::getSINCOS(RetVT: VT)
4963 : RTLIB::getSINCOSPI(RetVT: VT);
4964 bool Expanded = TLI.expandMultipleResultFPLibCall(DAG, LC, Node, Results);
4965 if (!Expanded) {
4966 DAG.getContext()->emitError(ErrorStr: Twine("no libcall available for ") +
4967 Node->getOperationName(G: &DAG));
4968 SDValue Poison = DAG.getPOISON(VT);
4969 Results.push_back(Elt: Poison);
4970 Results.push_back(Elt: Poison);
4971 }
4972
4973 break;
4974 }
4975 case ISD::FLOG:
4976 case ISD::STRICT_FLOG:
4977 ExpandFPLibCall(Node, Call_F32: RTLIB::LOG_F32, Call_F64: RTLIB::LOG_F64, Call_F80: RTLIB::LOG_F80,
4978 Call_F128: RTLIB::LOG_F128, Call_PPCF128: RTLIB::LOG_PPCF128, Results);
4979 break;
4980 case ISD::FLOG2:
4981 case ISD::STRICT_FLOG2:
4982 ExpandFPLibCall(Node, Call_F32: RTLIB::LOG2_F32, Call_F64: RTLIB::LOG2_F64, Call_F80: RTLIB::LOG2_F80,
4983 Call_F128: RTLIB::LOG2_F128, Call_PPCF128: RTLIB::LOG2_PPCF128, Results);
4984 break;
4985 case ISD::FLOG10:
4986 case ISD::STRICT_FLOG10:
4987 ExpandFPLibCall(Node, Call_F32: RTLIB::LOG10_F32, Call_F64: RTLIB::LOG10_F64, Call_F80: RTLIB::LOG10_F80,
4988 Call_F128: RTLIB::LOG10_F128, Call_PPCF128: RTLIB::LOG10_PPCF128, Results);
4989 break;
4990 case ISD::FEXP:
4991 case ISD::STRICT_FEXP:
4992 ExpandFPLibCall(Node, Call_F32: RTLIB::EXP_F32, Call_F64: RTLIB::EXP_F64, Call_F80: RTLIB::EXP_F80,
4993 Call_F128: RTLIB::EXP_F128, Call_PPCF128: RTLIB::EXP_PPCF128, Results);
4994 break;
4995 case ISD::FEXP2:
4996 case ISD::STRICT_FEXP2:
4997 ExpandFPLibCall(Node, Call_F32: RTLIB::EXP2_F32, Call_F64: RTLIB::EXP2_F64, Call_F80: RTLIB::EXP2_F80,
4998 Call_F128: RTLIB::EXP2_F128, Call_PPCF128: RTLIB::EXP2_PPCF128, Results);
4999 break;
5000 case ISD::FEXP10:
5001 ExpandFPLibCall(Node, Call_F32: RTLIB::EXP10_F32, Call_F64: RTLIB::EXP10_F64, Call_F80: RTLIB::EXP10_F80,
5002 Call_F128: RTLIB::EXP10_F128, Call_PPCF128: RTLIB::EXP10_PPCF128, Results);
5003 break;
5004 case ISD::FTRUNC:
5005 case ISD::STRICT_FTRUNC:
5006 ExpandFPLibCall(Node, Call_F32: RTLIB::TRUNC_F32, Call_F64: RTLIB::TRUNC_F64,
5007 Call_F80: RTLIB::TRUNC_F80, Call_F128: RTLIB::TRUNC_F128,
5008 Call_PPCF128: RTLIB::TRUNC_PPCF128, Results);
5009 break;
5010 case ISD::FFLOOR:
5011 case ISD::STRICT_FFLOOR:
5012 ExpandFPLibCall(Node, Call_F32: RTLIB::FLOOR_F32, Call_F64: RTLIB::FLOOR_F64,
5013 Call_F80: RTLIB::FLOOR_F80, Call_F128: RTLIB::FLOOR_F128,
5014 Call_PPCF128: RTLIB::FLOOR_PPCF128, Results);
5015 break;
5016 case ISD::FCEIL:
5017 case ISD::STRICT_FCEIL:
5018 ExpandFPLibCall(Node, Call_F32: RTLIB::CEIL_F32, Call_F64: RTLIB::CEIL_F64,
5019 Call_F80: RTLIB::CEIL_F80, Call_F128: RTLIB::CEIL_F128,
5020 Call_PPCF128: RTLIB::CEIL_PPCF128, Results);
5021 break;
5022 case ISD::FRINT:
5023 case ISD::STRICT_FRINT:
5024 ExpandFPLibCall(Node, Call_F32: RTLIB::RINT_F32, Call_F64: RTLIB::RINT_F64,
5025 Call_F80: RTLIB::RINT_F80, Call_F128: RTLIB::RINT_F128,
5026 Call_PPCF128: RTLIB::RINT_PPCF128, Results);
5027 break;
5028 case ISD::FNEARBYINT:
5029 case ISD::STRICT_FNEARBYINT:
5030 ExpandFPLibCall(Node, Call_F32: RTLIB::NEARBYINT_F32,
5031 Call_F64: RTLIB::NEARBYINT_F64,
5032 Call_F80: RTLIB::NEARBYINT_F80,
5033 Call_F128: RTLIB::NEARBYINT_F128,
5034 Call_PPCF128: RTLIB::NEARBYINT_PPCF128, Results);
5035 break;
5036 case ISD::FROUND:
5037 case ISD::STRICT_FROUND:
5038 ExpandFPLibCall(Node, Call_F32: RTLIB::ROUND_F32,
5039 Call_F64: RTLIB::ROUND_F64,
5040 Call_F80: RTLIB::ROUND_F80,
5041 Call_F128: RTLIB::ROUND_F128,
5042 Call_PPCF128: RTLIB::ROUND_PPCF128, Results);
5043 break;
5044 case ISD::FROUNDEVEN:
5045 case ISD::STRICT_FROUNDEVEN:
5046 ExpandFPLibCall(Node, Call_F32: RTLIB::ROUNDEVEN_F32,
5047 Call_F64: RTLIB::ROUNDEVEN_F64,
5048 Call_F80: RTLIB::ROUNDEVEN_F80,
5049 Call_F128: RTLIB::ROUNDEVEN_F128,
5050 Call_PPCF128: RTLIB::ROUNDEVEN_PPCF128, Results);
5051 break;
5052 case ISD::FLDEXP:
5053 case ISD::STRICT_FLDEXP:
5054 ExpandFPLibCall(Node, Call_F32: RTLIB::LDEXP_F32, Call_F64: RTLIB::LDEXP_F64, Call_F80: RTLIB::LDEXP_F80,
5055 Call_F128: RTLIB::LDEXP_F128, Call_PPCF128: RTLIB::LDEXP_PPCF128, Results);
5056 break;
5057 case ISD::FMODF:
5058 case ISD::FFREXP: {
5059 EVT VT = Node->getValueType(ResNo: 0);
5060 RTLIB::Libcall LC = Node->getOpcode() == ISD::FMODF ? RTLIB::getMODF(VT)
5061 : RTLIB::getFREXP(RetVT: VT);
5062 bool Expanded = TLI.expandMultipleResultFPLibCall(DAG, LC, Node, Results,
5063 /*CallRetResNo=*/0);
5064 if (!Expanded)
5065 llvm_unreachable("Expected scalar FFREXP/FMODF to expand to libcall!");
5066 break;
5067 }
5068 case ISD::FPOWI:
5069 case ISD::STRICT_FPOWI: {
5070 RTLIB::Libcall LC = RTLIB::getPOWI(RetVT: Node->getSimpleValueType(ResNo: 0));
5071 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fpowi.");
5072 if (DAG.getLibcalls().getLibcallImpl(Call: LC) == RTLIB::Unsupported) {
5073 // Some targets don't have a powi libcall; use pow instead.
5074 if (Node->isStrictFPOpcode()) {
5075 SDValue Exponent =
5076 DAG.getNode(Opcode: ISD::STRICT_SINT_TO_FP, DL: SDLoc(Node),
5077 ResultTys: {Node->getValueType(ResNo: 0), Node->getValueType(ResNo: 1)},
5078 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 2)});
5079 SDValue FPOW =
5080 DAG.getNode(Opcode: ISD::STRICT_FPOW, DL: SDLoc(Node),
5081 ResultTys: {Node->getValueType(ResNo: 0), Node->getValueType(ResNo: 1)},
5082 Ops: {Exponent.getValue(R: 1), Node->getOperand(Num: 1), Exponent});
5083 Results.push_back(Elt: FPOW);
5084 Results.push_back(Elt: FPOW.getValue(R: 1));
5085 } else {
5086 SDValue Exponent =
5087 DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: SDLoc(Node), VT: Node->getValueType(ResNo: 0),
5088 Operand: Node->getOperand(Num: 1));
5089 Results.push_back(Elt: DAG.getNode(Opcode: ISD::FPOW, DL: SDLoc(Node),
5090 VT: Node->getValueType(ResNo: 0),
5091 N1: Node->getOperand(Num: 0), N2: Exponent));
5092 }
5093 break;
5094 }
5095 unsigned Offset = Node->isStrictFPOpcode() ? 1 : 0;
5096 bool ExponentHasSizeOfInt =
5097 DAG.getLibInfo().getIntSize() ==
5098 Node->getOperand(Num: 1 + Offset).getValueType().getSizeInBits();
5099 if (!ExponentHasSizeOfInt) {
5100 // If the exponent does not match with sizeof(int) a libcall to
5101 // RTLIB::POWI would use the wrong type for the argument.
5102 DAG.getContext()->emitError(ErrorStr: "POWI exponent does not match sizeof(int)");
5103 Results.push_back(Elt: DAG.getPOISON(VT: Node->getValueType(ResNo: 0)));
5104 break;
5105 }
5106 ExpandFPLibCall(Node, LC, Results);
5107 break;
5108 }
5109 case ISD::FPOW:
5110 case ISD::STRICT_FPOW:
5111 ExpandFPLibCall(Node, Call_F32: RTLIB::POW_F32, Call_F64: RTLIB::POW_F64, Call_F80: RTLIB::POW_F80,
5112 Call_F128: RTLIB::POW_F128, Call_PPCF128: RTLIB::POW_PPCF128, Results);
5113 break;
5114 case ISD::LROUND:
5115 case ISD::STRICT_LROUND:
5116 ExpandArgFPLibCall(Node, Call_F32: RTLIB::LROUND_F32,
5117 Call_F64: RTLIB::LROUND_F64, Call_F80: RTLIB::LROUND_F80,
5118 Call_F128: RTLIB::LROUND_F128,
5119 Call_PPCF128: RTLIB::LROUND_PPCF128, Results);
5120 break;
5121 case ISD::LLROUND:
5122 case ISD::STRICT_LLROUND:
5123 ExpandArgFPLibCall(Node, Call_F32: RTLIB::LLROUND_F32,
5124 Call_F64: RTLIB::LLROUND_F64, Call_F80: RTLIB::LLROUND_F80,
5125 Call_F128: RTLIB::LLROUND_F128,
5126 Call_PPCF128: RTLIB::LLROUND_PPCF128, Results);
5127 break;
5128 case ISD::LRINT:
5129 case ISD::STRICT_LRINT:
5130 ExpandArgFPLibCall(Node, Call_F32: RTLIB::LRINT_F32,
5131 Call_F64: RTLIB::LRINT_F64, Call_F80: RTLIB::LRINT_F80,
5132 Call_F128: RTLIB::LRINT_F128,
5133 Call_PPCF128: RTLIB::LRINT_PPCF128, Results);
5134 break;
5135 case ISD::LLRINT:
5136 case ISD::STRICT_LLRINT:
5137 ExpandArgFPLibCall(Node, Call_F32: RTLIB::LLRINT_F32,
5138 Call_F64: RTLIB::LLRINT_F64, Call_F80: RTLIB::LLRINT_F80,
5139 Call_F128: RTLIB::LLRINT_F128,
5140 Call_PPCF128: RTLIB::LLRINT_PPCF128, Results);
5141 break;
5142 case ISD::FDIV:
5143 case ISD::STRICT_FDIV: {
5144 ExpandFastFPLibCall(Node, IsFast: canUseFastMathLibcall(Node),
5145 Call_F32: {RTLIB::FAST_DIV_F32, RTLIB::DIV_F32},
5146 Call_F64: {RTLIB::FAST_DIV_F64, RTLIB::DIV_F64},
5147 Call_F80: {RTLIB::FAST_DIV_F80, RTLIB::DIV_F80},
5148 Call_F128: {RTLIB::FAST_DIV_F128, RTLIB::DIV_F128},
5149 Call_PPCF128: {RTLIB::FAST_DIV_PPCF128, RTLIB::DIV_PPCF128}, Results);
5150 break;
5151 }
5152 case ISD::FREM:
5153 case ISD::STRICT_FREM:
5154 ExpandFPLibCall(Node, Call_F32: RTLIB::REM_F32, Call_F64: RTLIB::REM_F64,
5155 Call_F80: RTLIB::REM_F80, Call_F128: RTLIB::REM_F128,
5156 Call_PPCF128: RTLIB::REM_PPCF128, Results);
5157 break;
5158 case ISD::FMA:
5159 case ISD::STRICT_FMA:
5160 ExpandFPLibCall(Node, Call_F32: RTLIB::FMA_F32, Call_F64: RTLIB::FMA_F64,
5161 Call_F80: RTLIB::FMA_F80, Call_F128: RTLIB::FMA_F128,
5162 Call_PPCF128: RTLIB::FMA_PPCF128, Results);
5163 break;
5164 case ISD::FADD:
5165 case ISD::STRICT_FADD: {
5166 ExpandFastFPLibCall(Node, IsFast: canUseFastMathLibcall(Node),
5167 Call_F32: {RTLIB::FAST_ADD_F32, RTLIB::ADD_F32},
5168 Call_F64: {RTLIB::FAST_ADD_F64, RTLIB::ADD_F64},
5169 Call_F80: {RTLIB::FAST_ADD_F80, RTLIB::ADD_F80},
5170 Call_F128: {RTLIB::FAST_ADD_F128, RTLIB::ADD_F128},
5171 Call_PPCF128: {RTLIB::FAST_ADD_PPCF128, RTLIB::ADD_PPCF128}, Results);
5172 break;
5173 }
5174 case ISD::FMUL:
5175 case ISD::STRICT_FMUL: {
5176 ExpandFastFPLibCall(Node, IsFast: canUseFastMathLibcall(Node),
5177 Call_F32: {RTLIB::FAST_MUL_F32, RTLIB::MUL_F32},
5178 Call_F64: {RTLIB::FAST_MUL_F64, RTLIB::MUL_F64},
5179 Call_F80: {RTLIB::FAST_MUL_F80, RTLIB::MUL_F80},
5180 Call_F128: {RTLIB::FAST_MUL_F128, RTLIB::MUL_F128},
5181 Call_PPCF128: {RTLIB::FAST_MUL_PPCF128, RTLIB::MUL_PPCF128}, Results);
5182 break;
5183 }
5184 case ISD::FP16_TO_FP:
5185 if (Node->getValueType(ResNo: 0) == MVT::f32) {
5186 Results.push_back(Elt: ExpandLibCall(LC: RTLIB::FPEXT_F16_F32, Node, isSigned: false).first);
5187 }
5188 break;
5189 case ISD::STRICT_BF16_TO_FP:
5190 if (Node->getValueType(ResNo: 0) == MVT::f32) {
5191 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
5192 DAG, LC: RTLIB::FPEXT_BF16_F32, RetVT: MVT::f32, Ops: Node->getOperand(Num: 1),
5193 CallOptions, dl: SDLoc(Node), Chain: Node->getOperand(Num: 0));
5194 Results.push_back(Elt: Tmp.first);
5195 Results.push_back(Elt: Tmp.second);
5196 }
5197 break;
5198 case ISD::STRICT_FP16_TO_FP: {
5199 if (Node->getValueType(ResNo: 0) == MVT::f32) {
5200 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
5201 DAG, LC: RTLIB::FPEXT_F16_F32, RetVT: MVT::f32, Ops: Node->getOperand(Num: 1), CallOptions,
5202 dl: SDLoc(Node), Chain: Node->getOperand(Num: 0));
5203 Results.push_back(Elt: Tmp.first);
5204 Results.push_back(Elt: Tmp.second);
5205 }
5206 break;
5207 }
5208 case ISD::FP_TO_FP16: {
5209 RTLIB::Libcall LC =
5210 RTLIB::getFPROUND(OpVT: Node->getOperand(Num: 0).getValueType(), RetVT: MVT::f16);
5211 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
5212 Results.push_back(Elt: ExpandLibCall(LC, Node, isSigned: false).first);
5213 break;
5214 }
5215 case ISD::FP_TO_BF16: {
5216 RTLIB::Libcall LC =
5217 RTLIB::getFPROUND(OpVT: Node->getOperand(Num: 0).getValueType(), RetVT: MVT::bf16);
5218 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_bf16");
5219 Results.push_back(Elt: ExpandLibCall(LC, Node, isSigned: false).first);
5220 break;
5221 }
5222 case ISD::STRICT_SINT_TO_FP:
5223 case ISD::STRICT_UINT_TO_FP:
5224 case ISD::SINT_TO_FP:
5225 case ISD::UINT_TO_FP: {
5226 // TODO - Common the code with DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP
5227 bool IsStrict = Node->isStrictFPOpcode();
5228 bool Signed = Node->getOpcode() == ISD::SINT_TO_FP ||
5229 Node->getOpcode() == ISD::STRICT_SINT_TO_FP;
5230 EVT SVT = Node->getOperand(Num: IsStrict ? 1 : 0).getValueType();
5231 EVT RVT = Node->getValueType(ResNo: 0);
5232 EVT NVT = EVT();
5233 SDLoc dl(Node);
5234
5235 // Even if the input is legal, no libcall may exactly match, eg. we don't
5236 // have i1 -> fp conversions. So, it needs to be promoted to a larger type,
5237 // eg: i13 -> fp. Then, look for an appropriate libcall.
5238 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5239 for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
5240 t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
5241 ++t) {
5242 NVT = (MVT::SimpleValueType)t;
5243 // The source needs to big enough to hold the operand.
5244 if (NVT.bitsGE(VT: SVT))
5245 LC = Signed ? RTLIB::getSINTTOFP(OpVT: NVT, RetVT: RVT)
5246 : RTLIB::getUINTTOFP(OpVT: NVT, RetVT: RVT);
5247 }
5248 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
5249
5250 SDValue Chain = IsStrict ? Node->getOperand(Num: 0) : SDValue();
5251 // Sign/zero extend the argument if the libcall takes a larger type.
5252 SDValue Op = DAG.getNode(Opcode: Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL: dl,
5253 VT: NVT, Operand: Node->getOperand(Num: IsStrict ? 1 : 0));
5254 CallOptions.setIsSigned(Signed);
5255 std::pair<SDValue, SDValue> Tmp =
5256 TLI.makeLibCall(DAG, LC, RetVT: RVT, Ops: Op, CallOptions, dl, Chain);
5257 Results.push_back(Elt: Tmp.first);
5258 if (IsStrict)
5259 Results.push_back(Elt: Tmp.second);
5260 break;
5261 }
5262 case ISD::FP_TO_SINT:
5263 case ISD::FP_TO_UINT:
5264 case ISD::STRICT_FP_TO_SINT:
5265 case ISD::STRICT_FP_TO_UINT: {
5266 // TODO - Common the code with DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT.
5267 bool IsStrict = Node->isStrictFPOpcode();
5268 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT ||
5269 Node->getOpcode() == ISD::STRICT_FP_TO_SINT;
5270
5271 SDValue Op = Node->getOperand(Num: IsStrict ? 1 : 0);
5272 EVT SVT = Op.getValueType();
5273 EVT RVT = Node->getValueType(ResNo: 0);
5274 EVT NVT = EVT();
5275 SDLoc dl(Node);
5276
5277 // Even if the result is legal, no libcall may exactly match, eg. we don't
5278 // have fp -> i1 conversions. So, it needs to be promoted to a larger type,
5279 // eg: fp -> i32. Then, look for an appropriate libcall.
5280 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5281 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
5282 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
5283 ++IntVT) {
5284 NVT = (MVT::SimpleValueType)IntVT;
5285 // The type needs to big enough to hold the result.
5286 if (NVT.bitsGE(VT: RVT))
5287 LC = Signed ? RTLIB::getFPTOSINT(OpVT: SVT, RetVT: NVT)
5288 : RTLIB::getFPTOUINT(OpVT: SVT, RetVT: NVT);
5289 }
5290 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
5291
5292 SDValue Chain = IsStrict ? Node->getOperand(Num: 0) : SDValue();
5293 std::pair<SDValue, SDValue> Tmp =
5294 TLI.makeLibCall(DAG, LC, RetVT: NVT, Ops: Op, CallOptions, dl, Chain);
5295
5296 // Truncate the result if the libcall returns a larger type.
5297 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RVT, Operand: Tmp.first));
5298 if (IsStrict)
5299 Results.push_back(Elt: Tmp.second);
5300 break;
5301 }
5302
5303 case ISD::FP_ROUND:
5304 case ISD::STRICT_FP_ROUND: {
5305 // X = FP_ROUND(Y, TRUNC)
5306 // TRUNC is a flag, which is always an integer that is zero or one.
5307 // If TRUNC is 0, this is a normal rounding, if it is 1, this FP_ROUND
5308 // is known to not change the value of Y.
5309 // We can only expand it into libcall if the TRUNC is 0.
5310 bool IsStrict = Node->isStrictFPOpcode();
5311 SDValue Op = Node->getOperand(Num: IsStrict ? 1 : 0);
5312 SDValue Chain = IsStrict ? Node->getOperand(Num: 0) : SDValue();
5313 EVT VT = Node->getValueType(ResNo: 0);
5314 assert(cast<ConstantSDNode>(Node->getOperand(IsStrict ? 2 : 1))->isZero() &&
5315 "Unable to expand as libcall if it is not normal rounding");
5316
5317 RTLIB::Libcall LC = RTLIB::getFPROUND(OpVT: Op.getValueType(), RetVT: VT);
5318 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
5319
5320 std::pair<SDValue, SDValue> Tmp =
5321 TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op, CallOptions, dl: SDLoc(Node), Chain);
5322 Results.push_back(Elt: Tmp.first);
5323 if (IsStrict)
5324 Results.push_back(Elt: Tmp.second);
5325 break;
5326 }
5327 case ISD::FP_EXTEND: {
5328 Results.push_back(
5329 Elt: ExpandLibCall(LC: RTLIB::getFPEXT(OpVT: Node->getOperand(Num: 0).getValueType(),
5330 RetVT: Node->getValueType(ResNo: 0)),
5331 Node, isSigned: false).first);
5332 break;
5333 }
5334 case ISD::STRICT_FP_EXTEND:
5335 case ISD::STRICT_FP_TO_FP16:
5336 case ISD::STRICT_FP_TO_BF16: {
5337 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5338 if (Node->getOpcode() == ISD::STRICT_FP_TO_FP16)
5339 LC = RTLIB::getFPROUND(OpVT: Node->getOperand(Num: 1).getValueType(), RetVT: MVT::f16);
5340 else if (Node->getOpcode() == ISD::STRICT_FP_TO_BF16)
5341 LC = RTLIB::getFPROUND(OpVT: Node->getOperand(Num: 1).getValueType(), RetVT: MVT::bf16);
5342 else
5343 LC = RTLIB::getFPEXT(OpVT: Node->getOperand(Num: 1).getValueType(),
5344 RetVT: Node->getValueType(ResNo: 0));
5345
5346 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
5347
5348 std::pair<SDValue, SDValue> Tmp =
5349 TLI.makeLibCall(DAG, LC, RetVT: Node->getValueType(ResNo: 0), Ops: Node->getOperand(Num: 1),
5350 CallOptions, dl: SDLoc(Node), Chain: Node->getOperand(Num: 0));
5351 Results.push_back(Elt: Tmp.first);
5352 Results.push_back(Elt: Tmp.second);
5353 break;
5354 }
5355 case ISD::FSUB:
5356 case ISD::STRICT_FSUB: {
5357 ExpandFastFPLibCall(Node, IsFast: canUseFastMathLibcall(Node),
5358 Call_F32: {RTLIB::FAST_SUB_F32, RTLIB::SUB_F32},
5359 Call_F64: {RTLIB::FAST_SUB_F64, RTLIB::SUB_F64},
5360 Call_F80: {RTLIB::FAST_SUB_F80, RTLIB::SUB_F80},
5361 Call_F128: {RTLIB::FAST_SUB_F128, RTLIB::SUB_F128},
5362 Call_PPCF128: {RTLIB::FAST_SUB_PPCF128, RTLIB::SUB_PPCF128}, Results);
5363 break;
5364 }
5365 case ISD::SREM:
5366 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: true,
5367 Call_I8: RTLIB::SREM_I8,
5368 Call_I16: RTLIB::SREM_I16, Call_I32: RTLIB::SREM_I32,
5369 Call_I64: RTLIB::SREM_I64, Call_I128: RTLIB::SREM_I128));
5370 break;
5371 case ISD::UREM:
5372 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: false,
5373 Call_I8: RTLIB::UREM_I8,
5374 Call_I16: RTLIB::UREM_I16, Call_I32: RTLIB::UREM_I32,
5375 Call_I64: RTLIB::UREM_I64, Call_I128: RTLIB::UREM_I128));
5376 break;
5377 case ISD::SDIV:
5378 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: true,
5379 Call_I8: RTLIB::SDIV_I8,
5380 Call_I16: RTLIB::SDIV_I16, Call_I32: RTLIB::SDIV_I32,
5381 Call_I64: RTLIB::SDIV_I64, Call_I128: RTLIB::SDIV_I128));
5382 break;
5383 case ISD::UDIV:
5384 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: false,
5385 Call_I8: RTLIB::UDIV_I8,
5386 Call_I16: RTLIB::UDIV_I16, Call_I32: RTLIB::UDIV_I32,
5387 Call_I64: RTLIB::UDIV_I64, Call_I128: RTLIB::UDIV_I128));
5388 break;
5389 case ISD::SDIVREM:
5390 case ISD::UDIVREM:
5391 // Expand into divrem libcall
5392 ExpandDivRemLibCall(Node, Results);
5393 break;
5394 case ISD::MUL:
5395 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: false,
5396 Call_I8: RTLIB::MUL_I8,
5397 Call_I16: RTLIB::MUL_I16, Call_I32: RTLIB::MUL_I32,
5398 Call_I64: RTLIB::MUL_I64, Call_I128: RTLIB::MUL_I128));
5399 break;
5400 case ISD::CTLZ_ZERO_POISON:
5401 Results.push_back(Elt: ExpandBitCountingLibCall(
5402 Node, CallI32: RTLIB::CTLZ_I32, CallI64: RTLIB::CTLZ_I64, CallI128: RTLIB::CTLZ_I128));
5403 break;
5404 case ISD::CTPOP:
5405 Results.push_back(Elt: ExpandBitCountingLibCall(
5406 Node, CallI32: RTLIB::CTPOP_I32, CallI64: RTLIB::CTPOP_I64, CallI128: RTLIB::CTPOP_I128));
5407 break;
5408 case ISD::RESET_FPENV: {
5409 // It is legalized to call 'fesetenv(FE_DFL_ENV)'. On most targets
5410 // FE_DFL_ENV is defined as '((const fenv_t *) -1)' in glibc.
5411 EVT PtrTy = TLI.getPointerTy(DL: DAG.getDataLayout());
5412 SDValue Ptr = DAG.getAllOnesConstant(DL: dl, VT: PtrTy);
5413 SDValue Chain = Node->getOperand(Num: 0);
5414 Results.push_back(
5415 Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FESETENV, Ptr, InChain: Chain, DLoc: dl));
5416 break;
5417 }
5418 case ISD::GET_FPENV_MEM: {
5419 SDValue Chain = Node->getOperand(Num: 0);
5420 SDValue EnvPtr = Node->getOperand(Num: 1);
5421 Results.push_back(
5422 Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FEGETENV, Ptr: EnvPtr, InChain: Chain, DLoc: dl));
5423 break;
5424 }
5425 case ISD::SET_FPENV_MEM: {
5426 SDValue Chain = Node->getOperand(Num: 0);
5427 SDValue EnvPtr = Node->getOperand(Num: 1);
5428 Results.push_back(
5429 Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FESETENV, Ptr: EnvPtr, InChain: Chain, DLoc: dl));
5430 break;
5431 }
5432 case ISD::GET_FPMODE: {
5433 // Call fegetmode, which saves control modes into a stack slot. Then load
5434 // the value to return from the stack.
5435 EVT ModeVT = Node->getValueType(ResNo: 0);
5436 SDValue StackPtr = DAG.CreateStackTemporary(VT: ModeVT);
5437 int SPFI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
5438 SDValue Chain = DAG.makeStateFunctionCall(LibFunc: RTLIB::FEGETMODE, Ptr: StackPtr,
5439 InChain: Node->getOperand(Num: 0), DLoc: dl);
5440 SDValue LdInst = DAG.getLoad(
5441 VT: ModeVT, dl, Chain, Ptr: StackPtr,
5442 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI));
5443 Results.push_back(Elt: LdInst);
5444 Results.push_back(Elt: LdInst.getValue(R: 1));
5445 break;
5446 }
5447 case ISD::SET_FPMODE: {
5448 // Move control modes to stack slot and then call fesetmode with the pointer
5449 // to the slot as argument.
5450 SDValue Mode = Node->getOperand(Num: 1);
5451 EVT ModeVT = Mode.getValueType();
5452 SDValue StackPtr = DAG.CreateStackTemporary(VT: ModeVT);
5453 int SPFI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
5454 SDValue StInst = DAG.getStore(
5455 Chain: Node->getOperand(Num: 0), dl, Val: Mode, Ptr: StackPtr,
5456 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI));
5457 Results.push_back(
5458 Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FESETMODE, Ptr: StackPtr, InChain: StInst, DLoc: dl));
5459 break;
5460 }
5461 case ISD::RESET_FPMODE: {
5462 // It is legalized to a call 'fesetmode(FE_DFL_MODE)'. On most targets
5463 // FE_DFL_MODE is defined as '((const femode_t *) -1)' in glibc. If not, the
5464 // target must provide custom lowering.
5465 const DataLayout &DL = DAG.getDataLayout();
5466 EVT PtrTy = TLI.getPointerTy(DL);
5467 SDValue Mode = DAG.getAllOnesConstant(DL: dl, VT: PtrTy);
5468 Results.push_back(Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FESETMODE, Ptr: Mode,
5469 InChain: Node->getOperand(Num: 0), DLoc: dl));
5470 break;
5471 }
5472 }
5473
5474 // Replace the original node with the legalized result.
5475 if (!Results.empty()) {
5476 LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
5477 ReplaceNode(Old: Node, New: Results.data());
5478 } else
5479 LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
5480}
5481
5482// Determine the vector type to use in place of an original scalar element when
5483// promoting equally sized vectors.
5484static MVT getPromotedVectorElementType(const TargetLowering &TLI,
5485 MVT EltVT, MVT NewEltVT) {
5486 unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
5487 MVT MidVT = OldEltsPerNewElt == 1
5488 ? NewEltVT
5489 : MVT::getVectorVT(VT: NewEltVT, NumElements: OldEltsPerNewElt);
5490 assert(TLI.isTypeLegal(MidVT) && "unexpected");
5491 return MidVT;
5492}
5493
5494void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
5495 LLVM_DEBUG(dbgs() << "Trying to promote node\n");
5496 SmallVector<SDValue, 8> Results;
5497 MVT OVT = Node->getSimpleValueType(ResNo: 0);
5498 if (Node->getOpcode() == ISD::UINT_TO_FP ||
5499 Node->getOpcode() == ISD::SINT_TO_FP ||
5500 Node->getOpcode() == ISD::SETCC ||
5501 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
5502 Node->getOpcode() == ISD::INSERT_VECTOR_ELT ||
5503 Node->getOpcode() == ISD::VECREDUCE_FMAX ||
5504 Node->getOpcode() == ISD::VECREDUCE_FMIN ||
5505 Node->getOpcode() == ISD::VECREDUCE_FMAXIMUM ||
5506 Node->getOpcode() == ISD::VECREDUCE_FMINIMUM) {
5507 OVT = Node->getOperand(Num: 0).getSimpleValueType();
5508 }
5509 if (Node->getOpcode() == ISD::ATOMIC_STORE ||
5510 Node->getOpcode() == ISD::STRICT_UINT_TO_FP ||
5511 Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
5512 Node->getOpcode() == ISD::STRICT_FSETCC ||
5513 Node->getOpcode() == ISD::STRICT_FSETCCS ||
5514 Node->getOpcode() == ISD::STRICT_LRINT ||
5515 Node->getOpcode() == ISD::STRICT_LLRINT ||
5516 Node->getOpcode() == ISD::STRICT_LROUND ||
5517 Node->getOpcode() == ISD::STRICT_LLROUND ||
5518 Node->getOpcode() == ISD::VP_REDUCE_FADD ||
5519 Node->getOpcode() == ISD::VP_REDUCE_FMUL ||
5520 Node->getOpcode() == ISD::VP_REDUCE_FMAX ||
5521 Node->getOpcode() == ISD::VP_REDUCE_FMIN ||
5522 Node->getOpcode() == ISD::VP_REDUCE_FMAXIMUM ||
5523 Node->getOpcode() == ISD::VP_REDUCE_FMINIMUM ||
5524 Node->getOpcode() == ISD::VP_REDUCE_SEQ_FADD)
5525 OVT = Node->getOperand(Num: 1).getSimpleValueType();
5526 if (Node->getOpcode() == ISD::BR_CC ||
5527 Node->getOpcode() == ISD::SELECT_CC)
5528 OVT = Node->getOperand(Num: 2).getSimpleValueType();
5529 // Preserve fast math flags
5530 SDNodeFlags FastMathFlags = Node->getFlags() & SDNodeFlags::FastMathFlags;
5531 SelectionDAG::FlagInserter FlagsInserter(DAG, FastMathFlags);
5532 MVT NVT = TLI.getTypeToPromoteTo(Op: Node->getOpcode(), VT: OVT);
5533 SDLoc dl(Node);
5534 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
5535 switch (Node->getOpcode()) {
5536 case ISD::CTTZ:
5537 case ISD::CTTZ_ZERO_POISON:
5538 case ISD::CTLZ:
5539 case ISD::CTPOP: {
5540 // Zero extend the argument unless its cttz, then use any_extend.
5541 if (Node->getOpcode() == ISD::CTTZ ||
5542 Node->getOpcode() == ISD::CTTZ_ZERO_POISON)
5543 Tmp1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5544 else
5545 Tmp1 = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5546
5547 unsigned NewOpc = Node->getOpcode();
5548 if (NewOpc == ISD::CTTZ) {
5549 // The count is the same in the promoted type except if the original
5550 // value was zero. This can be handled by setting the bit just off
5551 // the top of the original type.
5552 auto TopBit = APInt::getOneBitSet(numBits: NVT.getSizeInBits(),
5553 BitNo: OVT.getSizeInBits());
5554 Tmp1 = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Tmp1,
5555 N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
5556 NewOpc = ISD::CTTZ_ZERO_POISON;
5557 }
5558 // Perform the larger operation. For CTPOP and CTTZ_ZERO_POISON, this is
5559 // already the correct result.
5560 Tmp1 = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Tmp1);
5561 if (NewOpc == ISD::CTLZ) {
5562 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
5563 Tmp1 = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Tmp1,
5564 N2: DAG.getConstant(Val: NVT.getSizeInBits() -
5565 OVT.getSizeInBits(), DL: dl, VT: NVT));
5566 }
5567 Results.push_back(
5568 Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1, Flags: SDNodeFlags::NoWrap));
5569 break;
5570 }
5571 case ISD::CTLZ_ZERO_POISON: {
5572 // We know that the argument is unlikely to be zero, hence we can take a
5573 // different approach as compared to ISD::CTLZ
5574
5575 // Any Extend the argument
5576 auto AnyExtendedNode =
5577 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5578
5579 // Tmp1 = Tmp1 << (sizeinbits(NVT) - sizeinbits(Old VT))
5580 auto ShiftConstant = DAG.getShiftAmountConstant(
5581 Val: NVT.getSizeInBits() - OVT.getSizeInBits(), VT: NVT, DL: dl);
5582 auto LeftShiftResult =
5583 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: AnyExtendedNode, N2: ShiftConstant);
5584
5585 // Perform the larger operation
5586 auto CTLZResult = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: LeftShiftResult);
5587 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: CTLZResult));
5588 break;
5589 }
5590 case ISD::PEXT: {
5591 Tmp1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5592 Tmp2 = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5593 Tmp1 = DAG.getNode(Opcode: ISD::PEXT, DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5594 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1));
5595 break;
5596 }
5597 case ISD::PDEP: {
5598 Tmp1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5599 Tmp2 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5600 Tmp1 = DAG.getNode(Opcode: ISD::PDEP, DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5601 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1));
5602 break;
5603 }
5604 case ISD::BITREVERSE:
5605 case ISD::BSWAP: {
5606 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
5607 Tmp1 = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5608 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: Tmp1);
5609 Tmp1 = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Tmp1,
5610 N2: DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl));
5611
5612 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1));
5613 break;
5614 }
5615 case ISD::FP_TO_UINT:
5616 case ISD::STRICT_FP_TO_UINT:
5617 case ISD::FP_TO_SINT:
5618 case ISD::STRICT_FP_TO_SINT:
5619 PromoteLegalFP_TO_INT(N: Node, dl, Results);
5620 break;
5621 case ISD::FP_TO_UINT_SAT:
5622 case ISD::FP_TO_SINT_SAT:
5623 Results.push_back(Elt: PromoteLegalFP_TO_INT_SAT(Node, dl));
5624 break;
5625 case ISD::UINT_TO_FP:
5626 case ISD::STRICT_UINT_TO_FP:
5627 case ISD::SINT_TO_FP:
5628 case ISD::STRICT_SINT_TO_FP:
5629 PromoteLegalINT_TO_FP(N: Node, dl, Results);
5630 break;
5631 case ISD::VAARG: {
5632 SDValue Chain = Node->getOperand(Num: 0); // Get the chain.
5633 SDValue Ptr = Node->getOperand(Num: 1); // Get the pointer.
5634
5635 unsigned TruncOp;
5636 if (OVT.isVector()) {
5637 TruncOp = ISD::BITCAST;
5638 } else {
5639 assert(OVT.isInteger()
5640 && "VAARG promotion is supported only for vectors or integer types");
5641 TruncOp = ISD::TRUNCATE;
5642 }
5643
5644 // Perform the larger operation, then convert back
5645 Tmp1 = DAG.getVAArg(VT: NVT, dl, Chain, Ptr, SV: Node->getOperand(Num: 2),
5646 Align: Node->getConstantOperandVal(Num: 3));
5647 Chain = Tmp1.getValue(R: 1);
5648
5649 Tmp2 = DAG.getNode(Opcode: TruncOp, DL: dl, VT: OVT, Operand: Tmp1);
5650
5651 // Modified the chain result - switch anything that used the old chain to
5652 // use the new one.
5653 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 0), To: Tmp2);
5654 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 1), To: Chain);
5655 if (UpdatedNodes) {
5656 UpdatedNodes->insert(X: Tmp2.getNode());
5657 UpdatedNodes->insert(X: Chain.getNode());
5658 }
5659 ReplacedNode(N: Node);
5660 break;
5661 }
5662 case ISD::MUL:
5663 case ISD::SDIV:
5664 case ISD::SREM:
5665 case ISD::UDIV:
5666 case ISD::UREM:
5667 case ISD::SMIN:
5668 case ISD::SMAX:
5669 case ISD::UMIN:
5670 case ISD::UMAX:
5671 case ISD::AND:
5672 case ISD::OR:
5673 case ISD::XOR: {
5674 unsigned ExtOp, TruncOp;
5675 if (OVT.isVector()) {
5676 ExtOp = ISD::BITCAST;
5677 TruncOp = ISD::BITCAST;
5678 } else {
5679 assert(OVT.isInteger() && "Cannot promote logic operation");
5680
5681 switch (Node->getOpcode()) {
5682 default:
5683 ExtOp = ISD::ANY_EXTEND;
5684 break;
5685 case ISD::SDIV:
5686 case ISD::SREM:
5687 case ISD::SMIN:
5688 case ISD::SMAX:
5689 ExtOp = ISD::SIGN_EXTEND;
5690 break;
5691 case ISD::UDIV:
5692 case ISD::UREM:
5693 ExtOp = ISD::ZERO_EXTEND;
5694 break;
5695 case ISD::UMIN:
5696 case ISD::UMAX:
5697 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT))
5698 ExtOp = ISD::SIGN_EXTEND;
5699 else
5700 ExtOp = ISD::ZERO_EXTEND;
5701 break;
5702 }
5703 TruncOp = ISD::TRUNCATE;
5704 }
5705 // Promote each of the values to the new type.
5706 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5707 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5708 // Perform the larger operation, then convert back
5709 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5710 Results.push_back(Elt: DAG.getNode(Opcode: TruncOp, DL: dl, VT: OVT, Operand: Tmp1));
5711 break;
5712 }
5713 case ISD::UMUL_LOHI:
5714 case ISD::SMUL_LOHI: {
5715 // Promote to a multiply in a wider integer type.
5716 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
5717 : ISD::SIGN_EXTEND;
5718 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5719 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5720 Tmp1 = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5721
5722 unsigned OriginalSize = OVT.getScalarSizeInBits();
5723 Tmp2 = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Tmp1,
5724 N2: DAG.getShiftAmountConstant(Val: OriginalSize, VT: NVT, DL: dl));
5725 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1));
5726 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp2));
5727 break;
5728 }
5729 case ISD::SELECT: {
5730 unsigned ExtOp, TruncOp;
5731 if (Node->getValueType(ResNo: 0).isVector() ||
5732 Node->getValueType(ResNo: 0).getSizeInBits() == NVT.getSizeInBits()) {
5733 ExtOp = ISD::BITCAST;
5734 TruncOp = ISD::BITCAST;
5735 } else if (Node->getValueType(ResNo: 0).isInteger()) {
5736 ExtOp = ISD::ANY_EXTEND;
5737 TruncOp = ISD::TRUNCATE;
5738 } else {
5739 ExtOp = ISD::FP_EXTEND;
5740 TruncOp = ISD::FP_ROUND;
5741 }
5742 Tmp1 = Node->getOperand(Num: 0);
5743 // Promote each of the values to the new type.
5744 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5745 Tmp3 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 2));
5746 // Perform the larger operation, then round down.
5747 Tmp1 = DAG.getSelect(DL: dl, VT: NVT, Cond: Tmp1, LHS: Tmp2, RHS: Tmp3);
5748 if (TruncOp != ISD::FP_ROUND)
5749 Tmp1 = DAG.getNode(Opcode: TruncOp, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Tmp1);
5750 else
5751 Tmp1 = DAG.getNode(Opcode: TruncOp, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
5752 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true));
5753 Results.push_back(Elt: Tmp1);
5754 break;
5755 }
5756 case ISD::VECTOR_SHUFFLE: {
5757 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Val: Node)->getMask();
5758
5759 // Cast the two input vectors.
5760 Tmp1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5761 Tmp2 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5762
5763 // Convert the shuffle mask to the right # elements.
5764 Tmp1 = ShuffleWithNarrowerEltType(NVT, VT: OVT, dl, N1: Tmp1, N2: Tmp2, Mask);
5765 Tmp1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: OVT, Operand: Tmp1);
5766 Results.push_back(Elt: Tmp1);
5767 break;
5768 }
5769 case ISD::VECTOR_SPLICE_LEFT:
5770 case ISD::VECTOR_SPLICE_RIGHT: {
5771 Tmp1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5772 Tmp2 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5773 Tmp3 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2,
5774 N3: Node->getOperand(Num: 2));
5775 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp3));
5776 break;
5777 }
5778 case ISD::SELECT_CC: {
5779 SDValue Cond = Node->getOperand(Num: 4);
5780 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val&: Cond)->get();
5781 // Type of the comparison operands.
5782 MVT CVT = Node->getSimpleValueType(ResNo: 0);
5783 assert(CVT == OVT && "not handled");
5784
5785 unsigned ExtOp = ISD::FP_EXTEND;
5786 if (NVT.isInteger()) {
5787 ExtOp = isSignedIntSetCC(Code: CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5788 }
5789
5790 // Promote the comparison operands, if needed.
5791 if (TLI.isCondCodeLegal(CC: CCCode, VT: CVT)) {
5792 Tmp1 = Node->getOperand(Num: 0);
5793 Tmp2 = Node->getOperand(Num: 1);
5794 } else {
5795 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5796 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5797 }
5798 // Cast the true/false operands.
5799 Tmp3 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 2));
5800 Tmp4 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 3));
5801
5802 Tmp1 = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: NVT, Ops: {Tmp1, Tmp2, Tmp3, Tmp4, Cond},
5803 Flags: Node->getFlags());
5804
5805 // Cast the result back to the original type.
5806 if (ExtOp != ISD::FP_EXTEND)
5807 Tmp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1);
5808 else
5809 Tmp1 = DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp1,
5810 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true));
5811
5812 Results.push_back(Elt: Tmp1);
5813 break;
5814 }
5815 case ISD::SETCC:
5816 case ISD::STRICT_FSETCC:
5817 case ISD::STRICT_FSETCCS: {
5818 unsigned ExtOp = ISD::FP_EXTEND;
5819 if (NVT.isInteger()) {
5820 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: Node->getOperand(Num: 2))->get();
5821 if (isSignedIntSetCC(Code: CCCode) ||
5822 TLI.isSExtCheaperThanZExt(FromTy: Node->getOperand(Num: 0).getValueType(), ToTy: NVT))
5823 ExtOp = ISD::SIGN_EXTEND;
5824 else
5825 ExtOp = ISD::ZERO_EXTEND;
5826 }
5827 if (Node->isStrictFPOpcode()) {
5828 SDValue InChain = Node->getOperand(Num: 0);
5829 std::tie(args&: Tmp1, args: std::ignore) =
5830 DAG.getStrictFPExtendOrRound(Op: Node->getOperand(Num: 1), Chain: InChain, DL: dl, VT: NVT);
5831 std::tie(args&: Tmp2, args: std::ignore) =
5832 DAG.getStrictFPExtendOrRound(Op: Node->getOperand(Num: 2), Chain: InChain, DL: dl, VT: NVT);
5833 SmallVector<SDValue, 2> TmpChains = {Tmp1.getValue(R: 1), Tmp2.getValue(R: 1)};
5834 SDValue OutChain = DAG.getTokenFactor(DL: dl, Vals&: TmpChains);
5835 SDVTList VTs = DAG.getVTList(VT1: Node->getValueType(ResNo: 0), VT2: MVT::Other);
5836 Results.push_back(Elt: DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VTList: VTs,
5837 Ops: {OutChain, Tmp1, Tmp2, Node->getOperand(Num: 3)},
5838 Flags: Node->getFlags()));
5839 Results.push_back(Elt: Results.back().getValue(R: 1));
5840 break;
5841 }
5842 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5843 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5844 Results.push_back(Elt: DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
5845 N2: Tmp2, N3: Node->getOperand(Num: 2), Flags: Node->getFlags()));
5846 break;
5847 }
5848 case ISD::BR_CC: {
5849 unsigned ExtOp = ISD::FP_EXTEND;
5850 if (NVT.isInteger()) {
5851 ISD::CondCode CCCode =
5852 cast<CondCodeSDNode>(Val: Node->getOperand(Num: 1))->get();
5853 ExtOp = isSignedIntSetCC(Code: CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5854 }
5855 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 2));
5856 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 3));
5857 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: Node->getValueType(ResNo: 0),
5858 N1: Node->getOperand(Num: 0), N2: Node->getOperand(Num: 1),
5859 N3: Tmp1, N4: Tmp2, N5: Node->getOperand(Num: 4)));
5860 break;
5861 }
5862 case ISD::FADD:
5863 case ISD::FSUB:
5864 case ISD::FMUL:
5865 case ISD::FDIV:
5866 case ISD::FREM:
5867 case ISD::FMINNUM:
5868 case ISD::FMAXNUM:
5869 case ISD::FMINIMUM:
5870 case ISD::FMAXIMUM:
5871 case ISD::FMINIMUMNUM:
5872 case ISD::FMAXIMUMNUM:
5873 case ISD::FPOW:
5874 case ISD::FATAN2:
5875 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5876 Tmp2 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5877 Tmp3 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5878 Results.push_back(
5879 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp3,
5880 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
5881 break;
5882
5883 case ISD::STRICT_FMINIMUM:
5884 case ISD::STRICT_FMAXIMUM: {
5885 SDValue InChain = Node->getOperand(Num: 0);
5886 SDVTList VTs = DAG.getVTList(VT1: NVT, VT2: MVT::Other);
5887 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, VTList: VTs, N1: InChain,
5888 N2: Node->getOperand(Num: 1));
5889 Tmp2 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, VTList: VTs, N1: InChain,
5890 N2: Node->getOperand(Num: 2));
5891 SmallVector<SDValue, 4> Ops = {InChain, Tmp1, Tmp2};
5892 Tmp3 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VTList: VTs, Ops, Flags: Node->getFlags());
5893 Tmp4 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, VTList: DAG.getVTList(VT1: OVT, VT2: MVT::Other),
5894 N1: InChain, N2: Tmp3,
5895 N3: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true));
5896 Results.push_back(Elt: Tmp4);
5897 Results.push_back(Elt: Tmp4.getValue(R: 1));
5898 break;
5899 }
5900
5901 case ISD::STRICT_FADD:
5902 case ISD::STRICT_FSUB:
5903 case ISD::STRICT_FMUL:
5904 case ISD::STRICT_FDIV:
5905 case ISD::STRICT_FMINNUM:
5906 case ISD::STRICT_FMAXNUM:
5907 case ISD::STRICT_FREM:
5908 case ISD::STRICT_FPOW:
5909 case ISD::STRICT_FATAN2:
5910 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5911 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
5912 Tmp2 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5913 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 2)});
5914 Tmp3 = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Tmp1.getValue(R: 1),
5915 N2: Tmp2.getValue(R: 1));
5916 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
5917 Ops: {Tmp3, Tmp1, Tmp2});
5918 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
5919 Ops: {Tmp1.getValue(R: 1), Tmp1,
5920 DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)});
5921 Results.push_back(Elt: Tmp1);
5922 Results.push_back(Elt: Tmp1.getValue(R: 1));
5923 break;
5924 case ISD::FMA:
5925 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5926 Tmp2 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5927 Tmp3 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 2));
5928 Results.push_back(
5929 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT,
5930 N1: DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2, N3: Tmp3),
5931 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
5932 break;
5933 case ISD::STRICT_FMA:
5934 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5935 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
5936 Tmp2 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5937 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 2)});
5938 Tmp3 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5939 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 3)});
5940 Tmp4 = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Tmp1.getValue(R: 1),
5941 N2: Tmp2.getValue(R: 1), N3: Tmp3.getValue(R: 1));
5942 Tmp4 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
5943 Ops: {Tmp4, Tmp1, Tmp2, Tmp3});
5944 Tmp4 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
5945 Ops: {Tmp4.getValue(R: 1), Tmp4,
5946 DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)});
5947 Results.push_back(Elt: Tmp4);
5948 Results.push_back(Elt: Tmp4.getValue(R: 1));
5949 break;
5950 case ISD::FCOPYSIGN:
5951 case ISD::FLDEXP:
5952 case ISD::FPOWI: {
5953 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5954 Tmp2 = Node->getOperand(Num: 1);
5955 Tmp3 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5956
5957 // fcopysign doesn't change anything but the sign bit, so
5958 // (fp_round (fcopysign (fpext a), b))
5959 // is as precise as
5960 // (fp_round (fpext a))
5961 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
5962 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
5963 Results.push_back(
5964 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp3,
5965 N2: DAG.getIntPtrConstant(Val: isTrunc, DL: dl, /*isTarget=*/true)));
5966 break;
5967 }
5968 case ISD::STRICT_FLDEXP: {
5969 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5970 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
5971 Tmp2 = Node->getOperand(Num: 2);
5972 Tmp3 = DAG.getNode(Opcode: ISD::STRICT_FLDEXP, DL: dl, ResultTys: {NVT, MVT::Other},
5973 Ops: {Tmp1.getValue(R: 1), Tmp1, Tmp2});
5974 Tmp4 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
5975 Ops: {Tmp3.getValue(R: 1), Tmp3,
5976 DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)});
5977 Results.push_back(Elt: Tmp4);
5978 Results.push_back(Elt: Tmp4.getValue(R: 1));
5979 break;
5980 }
5981 case ISD::STRICT_FPOWI:
5982 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5983 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
5984 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
5985 Ops: {Tmp1.getValue(R: 1), Tmp1, Node->getOperand(Num: 2)});
5986 Tmp3 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
5987 Ops: {Tmp2.getValue(R: 1), Tmp2,
5988 DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)});
5989 Results.push_back(Elt: Tmp3);
5990 Results.push_back(Elt: Tmp3.getValue(R: 1));
5991 break;
5992 case ISD::FFREXP: {
5993 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5994 Tmp2 = DAG.getNode(Opcode: ISD::FFREXP, DL: dl, ResultTys: {NVT, Node->getValueType(ResNo: 1)}, Ops: Tmp1);
5995
5996 Results.push_back(
5997 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp2,
5998 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
5999
6000 Results.push_back(Elt: Tmp2.getValue(R: 1));
6001 break;
6002 }
6003 case ISD::FMODF:
6004 case ISD::FSINCOS:
6005 case ISD::FSINCOSPI: {
6006 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
6007 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: NVT, VT2: NVT), N: Tmp1);
6008 Tmp3 = DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true);
6009 for (unsigned ResNum = 0; ResNum < Node->getNumValues(); ResNum++)
6010 Results.push_back(
6011 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp2.getValue(R: ResNum), N2: Tmp3));
6012 break;
6013 }
6014 case ISD::FFLOOR:
6015 case ISD::FCEIL:
6016 case ISD::FRINT:
6017 case ISD::FNEARBYINT:
6018 case ISD::FROUND:
6019 case ISD::FROUNDEVEN:
6020 case ISD::FTRUNC:
6021 case ISD::FNEG:
6022 case ISD::FSQRT:
6023 case ISD::FSIN:
6024 case ISD::FCOS:
6025 case ISD::FTAN:
6026 case ISD::FASIN:
6027 case ISD::FACOS:
6028 case ISD::FATAN:
6029 case ISD::FSINH:
6030 case ISD::FCOSH:
6031 case ISD::FTANH:
6032 case ISD::FLOG:
6033 case ISD::FLOG2:
6034 case ISD::FLOG10:
6035 case ISD::FABS:
6036 case ISD::FEXP:
6037 case ISD::FEXP2:
6038 case ISD::FEXP10:
6039 case ISD::FCANONICALIZE:
6040 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
6041 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: Tmp1);
6042 Results.push_back(
6043 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp2,
6044 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
6045 break;
6046 case ISD::STRICT_FFLOOR:
6047 case ISD::STRICT_FCEIL:
6048 case ISD::STRICT_FRINT:
6049 case ISD::STRICT_FNEARBYINT:
6050 case ISD::STRICT_FROUND:
6051 case ISD::STRICT_FROUNDEVEN:
6052 case ISD::STRICT_FTRUNC:
6053 case ISD::STRICT_FSQRT:
6054 case ISD::STRICT_FSIN:
6055 case ISD::STRICT_FCOS:
6056 case ISD::STRICT_FTAN:
6057 case ISD::STRICT_FASIN:
6058 case ISD::STRICT_FACOS:
6059 case ISD::STRICT_FATAN:
6060 case ISD::STRICT_FSINH:
6061 case ISD::STRICT_FCOSH:
6062 case ISD::STRICT_FTANH:
6063 case ISD::STRICT_FLOG:
6064 case ISD::STRICT_FLOG2:
6065 case ISD::STRICT_FLOG10:
6066 case ISD::STRICT_FEXP:
6067 case ISD::STRICT_FEXP2:
6068 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
6069 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
6070 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
6071 Ops: {Tmp1.getValue(R: 1), Tmp1});
6072 Tmp3 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
6073 Ops: {Tmp2.getValue(R: 1), Tmp2,
6074 DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)});
6075 Results.push_back(Elt: Tmp3);
6076 Results.push_back(Elt: Tmp3.getValue(R: 1));
6077 break;
6078 case ISD::LLROUND:
6079 case ISD::LROUND:
6080 case ISD::LRINT:
6081 case ISD::LLRINT:
6082 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
6083 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Tmp1);
6084 Results.push_back(Elt: Tmp2);
6085 break;
6086 case ISD::STRICT_LLROUND:
6087 case ISD::STRICT_LROUND:
6088 case ISD::STRICT_LRINT:
6089 case ISD::STRICT_LLRINT:
6090 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
6091 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
6092 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
6093 Ops: {Tmp1.getValue(R: 1), Tmp1});
6094 Results.push_back(Elt: Tmp2);
6095 Results.push_back(Elt: Tmp2.getValue(R: 1));
6096 break;
6097 case ISD::BUILD_VECTOR: {
6098 MVT EltVT = OVT.getVectorElementType();
6099 MVT NewEltVT = NVT.getVectorElementType();
6100
6101 // Handle bitcasts to a different vector type with the same total bit size
6102 //
6103 // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
6104 // =>
6105 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
6106
6107 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
6108 "Invalid promote type for build_vector");
6109 assert(NewEltVT.bitsLE(EltVT) && "not handled");
6110
6111 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
6112
6113 SmallVector<SDValue, 8> NewOps;
6114 for (const SDValue &Op : Node->op_values())
6115 NewOps.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(Op), VT: MidVT, Operand: Op));
6116
6117 SDLoc SL(Node);
6118 SDValue Concat =
6119 DAG.getNode(Opcode: MidVT == NewEltVT ? ISD::BUILD_VECTOR : ISD::CONCAT_VECTORS,
6120 DL: SL, VT: NVT, Ops: NewOps);
6121 SDValue CvtVec = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: Concat);
6122 Results.push_back(Elt: CvtVec);
6123 break;
6124 }
6125 case ISD::EXTRACT_VECTOR_ELT: {
6126 MVT EltVT = OVT.getVectorElementType();
6127 MVT NewEltVT = NVT.getVectorElementType();
6128
6129 // Handle bitcasts to a different vector type with the same total bit size.
6130 //
6131 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
6132 // =>
6133 // v4i32:castx = bitcast x:v2i64
6134 //
6135 // i64 = bitcast
6136 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
6137 // (i32 (extract_vector_elt castx, (2 * y + 1)))
6138 //
6139
6140 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
6141 "Invalid promote type for extract_vector_elt");
6142 assert(NewEltVT.bitsLT(EltVT) && "not handled");
6143
6144 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
6145 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
6146
6147 SDValue Idx = Node->getOperand(Num: 1);
6148 EVT IdxVT = Idx.getValueType();
6149 SDLoc SL(Node);
6150 SDValue Factor = DAG.getConstant(Val: NewEltsPerOldElt, DL: SL, VT: IdxVT);
6151 SDValue NewBaseIdx = DAG.getNode(Opcode: ISD::MUL, DL: SL, VT: IdxVT, N1: Idx, N2: Factor);
6152
6153 SDValue CastVec = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: NVT, Operand: Node->getOperand(Num: 0));
6154
6155 SmallVector<SDValue, 8> NewOps;
6156 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
6157 SDValue IdxOffset = DAG.getConstant(Val: I, DL: SL, VT: IdxVT);
6158 SDValue TmpIdx = DAG.getNode(Opcode: ISD::ADD, DL: SL, VT: IdxVT, N1: NewBaseIdx, N2: IdxOffset);
6159
6160 SDValue Elt = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SL, VT: NewEltVT,
6161 N1: CastVec, N2: TmpIdx);
6162 NewOps.push_back(Elt);
6163 }
6164
6165 SDValue NewVec = DAG.getBuildVector(VT: MidVT, DL: SL, Ops: NewOps);
6166 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: EltVT, Operand: NewVec));
6167 break;
6168 }
6169 case ISD::INSERT_VECTOR_ELT: {
6170 MVT EltVT = OVT.getVectorElementType();
6171 MVT NewEltVT = NVT.getVectorElementType();
6172
6173 // Handle bitcasts to a different vector type with the same total bit size
6174 //
6175 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
6176 // =>
6177 // v4i32:castx = bitcast x:v2i64
6178 // v2i32:casty = bitcast y:i64
6179 //
6180 // v2i64 = bitcast
6181 // (v4i32 insert_vector_elt
6182 // (v4i32 insert_vector_elt v4i32:castx,
6183 // (extract_vector_elt casty, 0), 2 * z),
6184 // (extract_vector_elt casty, 1), (2 * z + 1))
6185
6186 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
6187 "Invalid promote type for insert_vector_elt");
6188 assert(NewEltVT.bitsLT(EltVT) && "not handled");
6189
6190 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
6191 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
6192
6193 SDValue Val = Node->getOperand(Num: 1);
6194 SDValue Idx = Node->getOperand(Num: 2);
6195 EVT IdxVT = Idx.getValueType();
6196 SDLoc SL(Node);
6197
6198 SDValue Factor = DAG.getConstant(Val: NewEltsPerOldElt, DL: SDLoc(), VT: IdxVT);
6199 SDValue NewBaseIdx = DAG.getNode(Opcode: ISD::MUL, DL: SL, VT: IdxVT, N1: Idx, N2: Factor);
6200
6201 SDValue CastVec = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: NVT, Operand: Node->getOperand(Num: 0));
6202 SDValue CastVal = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: MidVT, Operand: Val);
6203
6204 SDValue NewVec = CastVec;
6205 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
6206 SDValue IdxOffset = DAG.getConstant(Val: I, DL: SL, VT: IdxVT);
6207 SDValue InEltIdx = DAG.getNode(Opcode: ISD::ADD, DL: SL, VT: IdxVT, N1: NewBaseIdx, N2: IdxOffset);
6208
6209 SDValue Elt = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SL, VT: NewEltVT,
6210 N1: CastVal, N2: IdxOffset);
6211
6212 NewVec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: SL, VT: NVT,
6213 N1: NewVec, N2: Elt, N3: InEltIdx);
6214 }
6215
6216 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: NewVec));
6217 break;
6218 }
6219 case ISD::SCALAR_TO_VECTOR: {
6220 MVT EltVT = OVT.getVectorElementType();
6221 MVT NewEltVT = NVT.getVectorElementType();
6222
6223 // Handle bitcasts to different vector type with the same total bit size.
6224 //
6225 // e.g. v2i64 = scalar_to_vector x:i64
6226 // =>
6227 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
6228 //
6229
6230 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
6231 SDValue Val = Node->getOperand(Num: 0);
6232 SDLoc SL(Node);
6233
6234 SDValue CastVal = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: MidVT, Operand: Val);
6235 SDValue Undef = DAG.getUNDEF(VT: MidVT);
6236
6237 SmallVector<SDValue, 8> NewElts;
6238 NewElts.push_back(Elt: CastVal);
6239 for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
6240 NewElts.push_back(Elt: Undef);
6241
6242 SDValue Concat = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: SL, VT: NVT, Ops: NewElts);
6243 SDValue CvtVec = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: Concat);
6244 Results.push_back(Elt: CvtVec);
6245 break;
6246 }
6247 case ISD::ATOMIC_SWAP:
6248 case ISD::ATOMIC_STORE: {
6249 AtomicSDNode *AM = cast<AtomicSDNode>(Val: Node);
6250 SDLoc SL(Node);
6251 SDValue CastVal = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: NVT, Operand: AM->getVal());
6252 assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
6253 "unexpected promotion type");
6254 assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
6255 "unexpected atomic_swap with illegal type");
6256
6257 SDValue Op0 = AM->getBasePtr();
6258 SDValue Op1 = CastVal;
6259
6260 // ATOMIC_STORE uses a swapped operand order from every other AtomicSDNode,
6261 // but really it should merge with ISD::STORE.
6262 if (AM->getOpcode() == ISD::ATOMIC_STORE)
6263 std::swap(a&: Op0, b&: Op1);
6264
6265 SDValue NewAtomic = DAG.getAtomic(Opcode: AM->getOpcode(), dl: SL, MemVT: NVT, Chain: AM->getChain(),
6266 Ptr: Op0, Val: Op1, MMO: AM->getMemOperand());
6267
6268 if (AM->getOpcode() != ISD::ATOMIC_STORE) {
6269 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: NewAtomic));
6270 Results.push_back(Elt: NewAtomic.getValue(R: 1));
6271 } else
6272 Results.push_back(Elt: NewAtomic);
6273 break;
6274 }
6275 case ISD::ATOMIC_LOAD: {
6276 AtomicSDNode *AM = cast<AtomicSDNode>(Val: Node);
6277 SDLoc SL(Node);
6278 assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
6279 "unexpected promotion type");
6280 assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
6281 "unexpected atomic_load with illegal type");
6282
6283 SDValue NewAtomic =
6284 DAG.getAtomic(Opcode: ISD::ATOMIC_LOAD, dl: SL, MemVT: NVT, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
6285 Ops: {AM->getChain(), AM->getBasePtr()}, MMO: AM->getMemOperand());
6286 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: NewAtomic));
6287 Results.push_back(Elt: NewAtomic.getValue(R: 1));
6288 break;
6289 }
6290 case ISD::SPLAT_VECTOR: {
6291 SDValue Scalar = Node->getOperand(Num: 0);
6292 MVT ScalarType = Scalar.getSimpleValueType();
6293 MVT NewScalarType = NVT.getVectorElementType();
6294 if (ScalarType.isInteger()) {
6295 Tmp1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NewScalarType, Operand: Scalar);
6296 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: Tmp1);
6297 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp2));
6298 break;
6299 }
6300 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NewScalarType, Operand: Scalar);
6301 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: Tmp1);
6302 Results.push_back(
6303 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp2,
6304 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
6305 break;
6306 }
6307 case ISD::VECREDUCE_FMAX:
6308 case ISD::VECREDUCE_FMIN:
6309 case ISD::VECREDUCE_FMAXIMUM:
6310 case ISD::VECREDUCE_FMINIMUM:
6311 case ISD::VP_REDUCE_FMAX:
6312 case ISD::VP_REDUCE_FMIN:
6313 case ISD::VP_REDUCE_FMAXIMUM:
6314 case ISD::VP_REDUCE_FMINIMUM:
6315 Results.push_back(Elt: PromoteReduction(Node));
6316 break;
6317 }
6318
6319 // Replace the original node with the legalized result.
6320 if (!Results.empty()) {
6321 LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
6322 ReplaceNode(Old: Node, New: Results.data());
6323 } else
6324 LLVM_DEBUG(dbgs() << "Could not promote node\n");
6325}
6326
6327/// This is the entry point for the file.
6328void SelectionDAG::Legalize() {
6329 AssignTopologicalOrder();
6330
6331 SmallPtrSet<SDNode *, 16> LegalizedNodes;
6332 // Use a delete listener to remove nodes which were deleted during
6333 // legalization from LegalizeNodes. This is needed to handle the situation
6334 // where a new node is allocated by the object pool to the same address of a
6335 // previously deleted node.
6336 DAGNodeDeletedListener DeleteListener(
6337 *this,
6338 [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(Ptr: N); });
6339
6340 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
6341
6342 // Visit all the nodes. We start in topological order, so that we see
6343 // nodes with their original operands intact. Legalization can produce
6344 // new nodes which may themselves need to be legalized. Iterate until all
6345 // nodes have been legalized.
6346 while (true) {
6347 bool AnyLegalized = false;
6348 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
6349 --NI;
6350
6351 SDNode *N = &*NI;
6352 if (N->use_empty() && N != getRoot().getNode()) {
6353 ++NI;
6354 DeleteNode(N);
6355 continue;
6356 }
6357
6358 if (LegalizedNodes.insert(Ptr: N).second) {
6359 AnyLegalized = true;
6360 Legalizer.LegalizeOp(Node: N);
6361
6362 if (N->use_empty() && N != getRoot().getNode()) {
6363 ++NI;
6364 DeleteNode(N);
6365 }
6366 }
6367 }
6368 if (!AnyLegalized)
6369 break;
6370
6371 }
6372
6373 // Remove dead nodes now.
6374 RemoveDeadNodes();
6375}
6376
6377bool SelectionDAG::LegalizeOp(SDNode *N,
6378 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
6379 SmallPtrSet<SDNode *, 16> LegalizedNodes;
6380 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
6381
6382 // Directly insert the node in question, and legalize it. This will recurse
6383 // as needed through operands.
6384 LegalizedNodes.insert(Ptr: N);
6385 Legalizer.LegalizeOp(Node: N);
6386
6387 return LegalizedNodes.count(Ptr: N);
6388}
6389