1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetLowering.h"
24#include "llvm/IR/DerivedTypes.h"
25#include "llvm/IR/DiagnosticInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/KnownBits.h"
28#include "llvm/Support/raw_ostream.h"
29#include <algorithm>
30using namespace llvm;
31
32#define DEBUG_TYPE "legalize-types"
33
34//===----------------------------------------------------------------------===//
35// Integer Result Promotion
36//===----------------------------------------------------------------------===//
37
38/// PromoteIntegerResult - This method is called when a result of a node is
39/// found to be in need of promotion to a larger type. At this point, the node
40/// may also have invalid operands or may have other results that need
41/// expansion, we just know that (at least) one result needs promotion.
42void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
43 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG));
44 SDValue Res = SDValue();
45
46 // See if the target wants to custom expand this node.
47 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true)) {
48 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
49 return;
50 }
51
52 switch (N->getOpcode()) {
53 default:
54#ifndef NDEBUG
55 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
56 N->dump(&DAG); dbgs() << "\n";
57#endif
58 report_fatal_error(reason: "Do not know how to promote this operator!");
59 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
60 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
61 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
62 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
63 case ISD::VP_BITREVERSE:
64 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
65 case ISD::VP_BSWAP:
66 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
67 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
68 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
69 case ISD::VP_CTLZ_ZERO_UNDEF:
70 case ISD::VP_CTLZ:
71 case ISD::CTLZ_ZERO_UNDEF:
72 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
73 case ISD::CTLS: Res = PromoteIntRes_CTLS(N); break;
74 case ISD::PARITY:
75 case ISD::VP_CTPOP:
76 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
77 case ISD::VP_CTTZ_ZERO_UNDEF:
78 case ISD::VP_CTTZ:
79 case ISD::CTTZ_ZERO_UNDEF:
80 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
81 case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
82 case ISD::VP_CTTZ_ELTS:
83 Res = PromoteIntRes_VP_CttzElements(N);
84 break;
85 case ISD::EXTRACT_VECTOR_ELT:
86 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
87 case ISD::LOAD: Res = PromoteIntRes_LOAD(N: cast<LoadSDNode>(Val: N)); break;
88 case ISD::VP_LOAD:
89 Res = PromoteIntRes_VP_LOAD(N: cast<VPLoadSDNode>(Val: N));
90 break;
91 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(N: cast<MaskedLoadSDNode>(Val: N));
92 break;
93 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(N: cast<MaskedGatherSDNode>(Val: N));
94 break;
95 case ISD::VECTOR_COMPRESS:
96 Res = PromoteIntRes_VECTOR_COMPRESS(N);
97 break;
98 case ISD::SELECT:
99 case ISD::VSELECT:
100 case ISD::VP_SELECT:
101 case ISD::VP_MERGE:
102 Res = PromoteIntRes_Select(N);
103 break;
104 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
105 case ISD::STRICT_FSETCC:
106 case ISD::STRICT_FSETCCS:
107 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
108 case ISD::SMIN:
109 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
110 case ISD::UMIN:
111 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
112
113 case ISD::SHL:
114 case ISD::VP_SHL: Res = PromoteIntRes_SHL(N); break;
115 case ISD::SIGN_EXTEND_INREG:
116 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
117 case ISD::SRA:
118 case ISD::VP_SRA: Res = PromoteIntRes_SRA(N); break;
119 case ISD::SRL:
120 case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
121 case ISD::VP_TRUNCATE:
122 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
123 case ISD::POISON:
124 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
125 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
126 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
127
128 case ISD::EXTRACT_SUBVECTOR:
129 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
130 case ISD::INSERT_SUBVECTOR:
131 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
132 case ISD::VECTOR_REVERSE:
133 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
134 case ISD::VECTOR_SHUFFLE:
135 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
136 case ISD::VECTOR_SPLICE_LEFT:
137 case ISD::VECTOR_SPLICE_RIGHT:
138 Res = PromoteIntRes_VECTOR_SPLICE(N);
139 break;
140 case ISD::VECTOR_INTERLEAVE:
141 case ISD::VECTOR_DEINTERLEAVE:
142 Res = PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(N);
143 return;
144 case ISD::INSERT_VECTOR_ELT:
145 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
146 case ISD::BUILD_VECTOR:
147 Res = PromoteIntRes_BUILD_VECTOR(N);
148 break;
149 case ISD::SPLAT_VECTOR:
150 case ISD::SCALAR_TO_VECTOR:
151 Res = PromoteIntRes_ScalarOp(N);
152 break;
153 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
154 case ISD::CONCAT_VECTORS:
155 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
156
157 case ISD::ANY_EXTEND_VECTOR_INREG:
158 case ISD::SIGN_EXTEND_VECTOR_INREG:
159 case ISD::ZERO_EXTEND_VECTOR_INREG:
160 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
161
162 case ISD::VECTOR_FIND_LAST_ACTIVE:
163 Res = PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(N);
164 break;
165
166 case ISD::GET_ACTIVE_LANE_MASK:
167 Res = PromoteIntRes_GET_ACTIVE_LANE_MASK(N);
168 break;
169
170 case ISD::PARTIAL_REDUCE_UMLA:
171 case ISD::PARTIAL_REDUCE_SMLA:
172 case ISD::PARTIAL_REDUCE_SUMLA:
173 Res = PromoteIntRes_PARTIAL_REDUCE_MLA(N);
174 break;
175
176 case ISD::SIGN_EXTEND:
177 case ISD::VP_SIGN_EXTEND:
178 case ISD::ZERO_EXTEND:
179 case ISD::VP_ZERO_EXTEND:
180 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
181
182 case ISD::VP_FP_TO_SINT:
183 case ISD::VP_FP_TO_UINT:
184 case ISD::STRICT_FP_TO_SINT:
185 case ISD::STRICT_FP_TO_UINT:
186 case ISD::FP_TO_SINT:
187 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
188
189 case ISD::FP_TO_SINT_SAT:
190 case ISD::FP_TO_UINT_SAT:
191 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
192
193 case ISD::FP_TO_BF16:
194 case ISD::FP_TO_FP16:
195 Res = PromoteIntRes_FP_TO_FP16_BF16(N);
196 break;
197 case ISD::STRICT_FP_TO_BF16:
198 case ISD::STRICT_FP_TO_FP16:
199 Res = PromoteIntRes_STRICT_FP_TO_FP16_BF16(N);
200 break;
201 case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break;
202
203 case ISD::AND:
204 case ISD::OR:
205 case ISD::XOR:
206 case ISD::ADD:
207 case ISD::SUB:
208 case ISD::MUL:
209 case ISD::VP_AND:
210 case ISD::VP_OR:
211 case ISD::VP_XOR:
212 case ISD::VP_ADD:
213 case ISD::VP_SUB:
214 case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
215
216 case ISD::ABDS:
217 case ISD::AVGCEILS:
218 case ISD::AVGFLOORS:
219 case ISD::VP_SMIN:
220 case ISD::VP_SMAX:
221 case ISD::SDIV:
222 case ISD::SREM:
223 case ISD::VP_SDIV:
224 case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
225
226 case ISD::ABDU:
227 case ISD::AVGCEILU:
228 case ISD::AVGFLOORU:
229 case ISD::VP_UMIN:
230 case ISD::VP_UMAX:
231 case ISD::UDIV:
232 case ISD::UREM:
233 case ISD::VP_UDIV:
234 case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
235
236 case ISD::SADDO:
237 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
238 case ISD::UADDO:
239 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
240 case ISD::SMULO:
241 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
242
243 case ISD::ADDE:
244 case ISD::SUBE:
245 case ISD::UADDO_CARRY:
246 case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break;
247
248 case ISD::SADDO_CARRY:
249 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
250
251 case ISD::SADDSAT:
252 case ISD::UADDSAT:
253 case ISD::SSUBSAT:
254 case ISD::USUBSAT:
255 case ISD::SSHLSAT:
256 case ISD::USHLSAT:
257 Res = PromoteIntRes_ADDSUBSHLSAT<EmptyMatchContext>(N);
258 break;
259 case ISD::VP_SADDSAT:
260 case ISD::VP_UADDSAT:
261 case ISD::VP_SSUBSAT:
262 case ISD::VP_USUBSAT:
263 Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
264 break;
265
266 case ISD::SCMP:
267 case ISD::UCMP:
268 Res = PromoteIntRes_CMP(N);
269 break;
270
271 case ISD::SMULFIX:
272 case ISD::SMULFIXSAT:
273 case ISD::UMULFIX:
274 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
275
276 case ISD::SDIVFIX:
277 case ISD::SDIVFIXSAT:
278 case ISD::UDIVFIX:
279 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
280
281 case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
282
283 case ISD::ATOMIC_LOAD:
284 Res = PromoteIntRes_Atomic0(N: cast<AtomicSDNode>(Val: N)); break;
285
286 case ISD::ATOMIC_LOAD_ADD:
287 case ISD::ATOMIC_LOAD_SUB:
288 case ISD::ATOMIC_LOAD_AND:
289 case ISD::ATOMIC_LOAD_CLR:
290 case ISD::ATOMIC_LOAD_OR:
291 case ISD::ATOMIC_LOAD_XOR:
292 case ISD::ATOMIC_LOAD_NAND:
293 case ISD::ATOMIC_LOAD_MIN:
294 case ISD::ATOMIC_LOAD_MAX:
295 case ISD::ATOMIC_LOAD_UMIN:
296 case ISD::ATOMIC_LOAD_UMAX:
297 case ISD::ATOMIC_SWAP:
298 Res = PromoteIntRes_Atomic1(N: cast<AtomicSDNode>(Val: N)); break;
299
300 case ISD::ATOMIC_CMP_SWAP:
301 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
302 Res = PromoteIntRes_AtomicCmpSwap(N: cast<AtomicSDNode>(Val: N), ResNo);
303 break;
304
305 case ISD::VECREDUCE_ADD:
306 case ISD::VECREDUCE_MUL:
307 case ISD::VECREDUCE_AND:
308 case ISD::VECREDUCE_OR:
309 case ISD::VECREDUCE_XOR:
310 case ISD::VECREDUCE_SMAX:
311 case ISD::VECREDUCE_SMIN:
312 case ISD::VECREDUCE_UMAX:
313 case ISD::VECREDUCE_UMIN:
314 Res = PromoteIntRes_VECREDUCE(N);
315 break;
316
317 case ISD::VP_REDUCE_ADD:
318 case ISD::VP_REDUCE_MUL:
319 case ISD::VP_REDUCE_AND:
320 case ISD::VP_REDUCE_OR:
321 case ISD::VP_REDUCE_XOR:
322 case ISD::VP_REDUCE_SMAX:
323 case ISD::VP_REDUCE_SMIN:
324 case ISD::VP_REDUCE_UMAX:
325 case ISD::VP_REDUCE_UMIN:
326 Res = PromoteIntRes_VP_REDUCE(N);
327 break;
328
329 case ISD::LOOP_DEPENDENCE_WAR_MASK:
330 case ISD::LOOP_DEPENDENCE_RAW_MASK:
331 Res = PromoteIntRes_LOOP_DEPENDENCE_MASK(N);
332 break;
333
334 case ISD::FREEZE:
335 Res = PromoteIntRes_FREEZE(N);
336 break;
337
338 case ISD::ROTL:
339 case ISD::ROTR:
340 Res = PromoteIntRes_Rotate(N);
341 break;
342
343 case ISD::FSHL:
344 case ISD::FSHR:
345 Res = PromoteIntRes_FunnelShift(N);
346 break;
347
348 case ISD::VP_FSHL:
349 case ISD::VP_FSHR:
350 Res = PromoteIntRes_VPFunnelShift(N);
351 break;
352
353 case ISD::CLMUL:
354 case ISD::CLMULH:
355 case ISD::CLMULR:
356 Res = PromoteIntRes_CLMUL(N);
357 break;
358
359 case ISD::IS_FPCLASS:
360 Res = PromoteIntRes_IS_FPCLASS(N);
361 break;
362 case ISD::FFREXP:
363 Res = PromoteIntRes_FFREXP(N);
364 break;
365
366 case ISD::LRINT:
367 case ISD::LLRINT:
368 Res = PromoteIntRes_XRINT(N);
369 break;
370
371 case ISD::PATCHPOINT:
372 Res = PromoteIntRes_PATCHPOINT(N);
373 break;
374 case ISD::READ_REGISTER:
375 Res = PromoteIntRes_READ_REGISTER(N);
376 break;
377 }
378
379 // If the result is null then the sub-method took care of registering it.
380 if (Res.getNode())
381 SetPromotedInteger(Op: SDValue(N, ResNo), Result: Res);
382}
383
384SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
385 unsigned ResNo) {
386 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
387 return GetPromotedInteger(Op);
388}
389
390SDValue DAGTypeLegalizer::PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
391 EVT VT = N->getValueType(ResNo: 0);
392 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
393 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: NewVT, Ops: N->ops());
394}
395
396SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
397 // Sign-extend the new bits, and continue the assertion.
398 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
399 return DAG.getNode(Opcode: ISD::AssertSext, DL: SDLoc(N),
400 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
401}
402
403SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
404 // Zero the new bits, and continue the assertion.
405 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
406 return DAG.getNode(Opcode: ISD::AssertZext, DL: SDLoc(N),
407 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
408}
409
410SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
411 EVT ResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
412 ISD::LoadExtType ExtType = N->getExtensionType();
413 if (ExtType == ISD::NON_EXTLOAD) {
414 switch (TLI.getExtendForAtomicOps()) {
415 case ISD::SIGN_EXTEND:
416 ExtType = ISD::SEXTLOAD;
417 break;
418 case ISD::ZERO_EXTEND:
419 ExtType = ISD::ZEXTLOAD;
420 break;
421 case ISD::ANY_EXTEND:
422 ExtType = ISD::EXTLOAD;
423 break;
424 default:
425 llvm_unreachable("Invalid atomic op extension");
426 }
427 }
428
429 SDValue Res =
430 DAG.getAtomicLoad(ExtType, dl: SDLoc(N), MemVT: N->getMemoryVT(), VT: ResVT,
431 Chain: N->getChain(), Ptr: N->getBasePtr(), MMO: N->getMemOperand());
432
433 // Legalize the chain result - switch anything that used the old chain to
434 // use the new one.
435 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
436 return Res;
437}
438
439SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
440 SDValue Op2 = N->getOperand(Num: 2);
441 switch (TLI.getExtendForAtomicRMWArg(Op: N->getOpcode())) {
442 case ISD::SIGN_EXTEND:
443 Op2 = SExtPromotedInteger(Op: Op2);
444 break;
445 case ISD::ZERO_EXTEND:
446 Op2 = ZExtPromotedInteger(Op: Op2);
447 break;
448 case ISD::ANY_EXTEND:
449 Op2 = GetPromotedInteger(Op: Op2);
450 break;
451 default:
452 llvm_unreachable("Invalid atomic op extension");
453 }
454 SDValue Res = DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N),
455 MemVT: N->getMemoryVT(),
456 Chain: N->getChain(), Ptr: N->getBasePtr(),
457 Val: Op2, MMO: N->getMemOperand());
458 // Legalize the chain result - switch anything that used the old chain to
459 // use the new one.
460 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
461 return Res;
462}
463
464SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
465 unsigned ResNo) {
466 if (ResNo == 1) {
467 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
468 EVT SVT = getSetCCResultType(VT: N->getOperand(Num: 2).getValueType());
469 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
470
471 // Only use the result of getSetCCResultType if it is legal,
472 // otherwise just use the promoted result type (NVT).
473 if (!TLI.isTypeLegal(VT: SVT))
474 SVT = NVT;
475
476 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: SVT, VT3: MVT::Other);
477 SDValue Res = DAG.getAtomicCmpSwap(
478 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs,
479 Chain: N->getChain(), Ptr: N->getBasePtr(), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
480 MMO: N->getMemOperand());
481 ReplaceValueWith(From: SDValue(N, 0), To: Res.getValue(R: 0));
482 ReplaceValueWith(From: SDValue(N, 2), To: Res.getValue(R: 2));
483 return DAG.getSExtOrTrunc(Op: Res.getValue(R: 1), DL: SDLoc(N), VT: NVT);
484 }
485
486 // Op2 is used for the comparison and thus must be extended according to the
487 // target's atomic operations. Op3 is merely stored and so can be left alone.
488 SDValue Op2 = N->getOperand(Num: 2);
489 SDValue Op3 = GetPromotedInteger(Op: N->getOperand(Num: 3));
490 switch (TLI.getExtendForAtomicCmpSwapArg()) {
491 case ISD::SIGN_EXTEND:
492 Op2 = SExtPromotedInteger(Op: Op2);
493 break;
494 case ISD::ZERO_EXTEND:
495 Op2 = ZExtPromotedInteger(Op: Op2);
496 break;
497 case ISD::ANY_EXTEND:
498 Op2 = GetPromotedInteger(Op: Op2);
499 break;
500 default:
501 llvm_unreachable("Invalid atomic op extension");
502 }
503
504 SDVTList VTs =
505 DAG.getVTList(VT1: Op2.getValueType(), VT2: N->getValueType(ResNo: 1), VT3: MVT::Other);
506 SDValue Res = DAG.getAtomicCmpSwap(
507 Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs, Chain: N->getChain(),
508 Ptr: N->getBasePtr(), Cmp: Op2, Swp: Op3, MMO: N->getMemOperand());
509 // Update the use to N with the newly created Res.
510 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
511 ReplaceValueWith(From: SDValue(N, i), To: Res.getValue(R: i));
512 return Res;
513}
514
515SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
516 SDValue InOp = N->getOperand(Num: 0);
517 EVT InVT = InOp.getValueType();
518 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
519 EVT OutVT = N->getValueType(ResNo: 0);
520 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
521 SDLoc dl(N);
522
523 switch (getTypeAction(VT: InVT)) {
524 case TargetLowering::TypeLegal:
525 break;
526 case TargetLowering::TypePromoteInteger:
527 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector() && !NInVT.isVector())
528 // The input promotes to the same size. Convert the promoted value.
529 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetPromotedInteger(Op: InOp));
530 break;
531 case TargetLowering::TypeSoftenFloat:
532 // Promote the integer operand by hand.
533 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftenedFloat(Op: InOp));
534 case TargetLowering::TypeSoftPromoteHalf:
535 // Promote the integer operand by hand.
536 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftPromotedHalf(Op: InOp));
537 case TargetLowering::TypeExpandInteger:
538 case TargetLowering::TypeExpandFloat:
539 break;
540 case TargetLowering::TypeScalarizeVector:
541 // Convert the element to an integer and promote it by hand.
542 if (!NOutVT.isVector())
543 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
544 Operand: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)));
545 break;
546 case TargetLowering::TypeScalarizeScalableVector:
547 report_fatal_error(reason: "Scalarization of scalable vectors is not supported.");
548 case TargetLowering::TypeSplitVector: {
549 if (!NOutVT.isVector()) {
550 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
551 // pieces of the input into integers and reassemble in the final type.
552 SDValue Lo, Hi;
553 GetSplitVector(Op: N->getOperand(Num: 0), Lo, Hi);
554 Lo = BitConvertToInteger(Op: Lo);
555 Hi = BitConvertToInteger(Op: Hi);
556
557 if (DAG.getDataLayout().isBigEndian())
558 std::swap(a&: Lo, b&: Hi);
559
560 InOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
561 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
562 BitWidth: NOutVT.getSizeInBits()),
563 Operand: JoinIntegers(Lo, Hi));
564 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: InOp);
565 }
566 break;
567 }
568 case TargetLowering::TypeWidenVector:
569 // The input is widened to the same size. Convert to the widened value.
570 // Make sure that the outgoing value is not a vector, because this would
571 // make us bitcast between two vectors which are legalized in different ways.
572 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector()) {
573 SDValue Res =
574 DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetWidenedVector(Op: InOp));
575
576 // For big endian targets we need to shift the casted value or the
577 // interesting bits will end up at the wrong place.
578 if (DAG.getDataLayout().isBigEndian()) {
579 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
580 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
581 Res = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NOutVT, N1: Res,
582 N2: DAG.getShiftAmountConstant(Val: ShiftAmt, VT: NOutVT, DL: dl));
583 }
584 return Res;
585 }
586 // If the output type is also a vector and widening it to the same size
587 // as the widened input type would be a legal type, we can widen the bitcast
588 // and handle the promotion after.
589 if (NOutVT.isVector()) {
590 TypeSize WidenInSize = NInVT.getSizeInBits();
591 TypeSize OutSize = OutVT.getSizeInBits();
592 if (WidenInSize.hasKnownScalarFactor(RHS: OutSize)) {
593 unsigned Scale = WidenInSize.getKnownScalarFactor(RHS: OutSize);
594 EVT WideOutVT =
595 EVT::getVectorVT(Context&: *DAG.getContext(), VT: OutVT.getVectorElementType(),
596 EC: OutVT.getVectorElementCount() * Scale);
597 if (isTypeLegal(VT: WideOutVT)) {
598 InOp = DAG.getBitcast(VT: WideOutVT, V: GetWidenedVector(Op: InOp));
599 InOp = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: InOp,
600 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
601 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: InOp);
602 }
603 }
604 }
605 }
606
607 // TODO: Handle big endian
608 if (!NOutVT.isVector() && InOp.getValueType().isVector() &&
609 DAG.getDataLayout().isLittleEndian()) {
610 // Pad the vector operand with undef and cast to a wider integer.
611 EVT EltVT = InOp.getValueType().getVectorElementType();
612 TypeSize EltSize = EltVT.getSizeInBits();
613 TypeSize OutSize = NOutVT.getSizeInBits();
614
615 if (OutSize.hasKnownScalarFactor(RHS: EltSize)) {
616 unsigned NumEltsWithPadding = OutSize.getKnownScalarFactor(RHS: EltSize);
617 EVT WideVecVT =
618 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
619
620 if (isTypeLegal(VT: WideVecVT)) {
621 SDValue Inserted = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: WideVecVT,
622 N1: DAG.getUNDEF(VT: WideVecVT), N2: InOp,
623 N3: DAG.getVectorIdxConstant(Val: 0, DL: dl));
624
625 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Inserted);
626 }
627 }
628 }
629
630 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
631 Operand: CreateStackStoreLoad(Op: InOp, DestVT: OutVT));
632}
633
634SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
635 SDValue V = GetPromotedInteger(Op: N->getOperand(Num: 0));
636 return DAG.getNode(Opcode: ISD::FREEZE, DL: SDLoc(N),
637 VT: V.getValueType(), Operand: V);
638}
639
640SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
641 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
642 EVT OVT = N->getValueType(ResNo: 0);
643 EVT NVT = Op.getValueType();
644 SDLoc dl(N);
645
646 // If the larger BSWAP isn't supported by the target, try to expand now.
647 // If we expand later we'll end up with more operations since we lost the
648 // original type. We only do this for scalars since we have a shuffle
649 // based lowering for vectors in LegalizeVectorOps.
650 if (!OVT.isVector() &&
651 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BSWAP, VT: NVT)) {
652 if (SDValue Res = TLI.expandBSWAP(N, DAG))
653 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
654 }
655
656 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
657 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
658 if (N->getOpcode() == ISD::BSWAP)
659 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: NVT, Operand: Op),
660 N2: ShAmt);
661 SDValue Mask = N->getOperand(Num: 1);
662 SDValue EVL = N->getOperand(Num: 2);
663 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
664 N1: DAG.getNode(Opcode: ISD::VP_BSWAP, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL), N2: ShAmt,
665 N3: Mask, N4: EVL);
666}
667
668SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
669 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
670 EVT OVT = N->getValueType(ResNo: 0);
671 EVT NVT = Op.getValueType();
672 SDLoc dl(N);
673
674 // If the larger BITREVERSE isn't supported by the target, try to expand now.
675 // If we expand later we'll end up with more operations since we lost the
676 // original type. We only do this for scalars since we have a shuffle
677 // based lowering for vectors in LegalizeVectorOps.
678 if (!OVT.isVector() && OVT.isSimple() &&
679 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BITREVERSE, VT: NVT)) {
680 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
681 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
682 }
683
684 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
685 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
686 if (N->getOpcode() == ISD::BITREVERSE)
687 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT,
688 N1: DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: NVT, Operand: Op), N2: ShAmt);
689 SDValue Mask = N->getOperand(Num: 1);
690 SDValue EVL = N->getOperand(Num: 2);
691 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
692 N1: DAG.getNode(Opcode: ISD::VP_BITREVERSE, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
693 N2: ShAmt, N3: Mask, N4: EVL);
694}
695
696SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
697 // The pair element type may be legal, or may not promote to the same type as
698 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
699 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N),
700 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
701 VT: N->getValueType(ResNo: 0)), Operand: JoinIntegers(Lo: N->getOperand(Num: 0),
702 Hi: N->getOperand(Num: 1)));
703}
704
705SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
706 EVT VT = N->getValueType(ResNo: 0);
707 // FIXME there is no actual debug info here
708 SDLoc dl(N);
709 // Zero extend things like i1, sign extend everything else. It shouldn't
710 // matter in theory which one we pick, but this tends to give better code?
711 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
712 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl,
713 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT),
714 Operand: SDValue(N, 0));
715 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
716 return Result;
717}
718
719SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
720 EVT OVT = N->getValueType(ResNo: 0);
721 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
722 SDLoc dl(N);
723
724 // If the larger CTLZ isn't supported by the target, try to expand now.
725 // If we expand later we'll end up with more operations since we lost the
726 // original type.
727 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
728 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ, VT: NVT) &&
729 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ_ZERO_UNDEF, VT: NVT)) {
730 if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
731 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
732 return Result;
733 }
734 }
735
736 unsigned CtlzOpcode = N->getOpcode();
737 if (CtlzOpcode == ISD::CTLZ || CtlzOpcode == ISD::VP_CTLZ) {
738 // Subtract off the extra leading bits in the bigger type.
739 SDValue ExtractLeadingBits = DAG.getConstant(
740 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
741 // Zero extend to the promoted type and do the count there.
742 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
743
744 if (!N->isVPOpcode())
745 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT,
746 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Op),
747 N2: ExtractLeadingBits);
748 SDValue Mask = N->getOperand(Num: 1);
749 SDValue EVL = N->getOperand(Num: 2);
750 return DAG.getNode(Opcode: ISD::VP_SUB, DL: dl, VT: NVT,
751 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
752 N2: ExtractLeadingBits, N3: Mask, N4: EVL);
753 }
754 if (CtlzOpcode == ISD::CTLZ_ZERO_UNDEF ||
755 CtlzOpcode == ISD::VP_CTLZ_ZERO_UNDEF) {
756 // Any Extend the argument
757 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
758 // Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
759 unsigned SHLAmount = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
760 auto ShiftConst =
761 DAG.getShiftAmountConstant(Val: SHLAmount, VT: Op.getValueType(), DL: dl);
762 if (!N->isVPOpcode()) {
763 Op = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst);
764 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, Operand: Op);
765 }
766
767 SDValue Mask = N->getOperand(Num: 1);
768 SDValue EVL = N->getOperand(Num: 2);
769 Op = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst, N3: Mask, N4: EVL);
770 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL);
771 }
772 llvm_unreachable("Invalid CTLZ Opcode");
773}
774
775SDValue DAGTypeLegalizer::PromoteIntRes_CTLS(SDNode *N) {
776 EVT OVT = N->getValueType(ResNo: 0);
777 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
778 SDLoc dl(N);
779
780 SDValue ExtractLeadingBits = DAG.getConstant(
781 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
782
783 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
784 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Op),
785 N2: ExtractLeadingBits);
786}
787
788SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
789 EVT OVT = N->getValueType(ResNo: 0);
790 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
791
792 // If the larger CTPOP isn't supported by the target, try to expand now.
793 // If we expand later we'll end up with more operations since we lost the
794 // original type.
795 // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
796 // TargetLowering.
797 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
798 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTPOP, VT: NVT)) {
799 if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
800 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Result);
801 return Result;
802 }
803 }
804
805 // Zero extend to the promoted type and do the count or parity there.
806 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
807 if (!N->isVPOpcode())
808 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), Operand: Op);
809
810 SDValue Mask = N->getOperand(Num: 1);
811 SDValue EVL = N->getOperand(Num: 2);
812 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), N1: Op, N2: Mask,
813 N3: EVL);
814}
815
816SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
817 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
818 EVT OVT = N->getValueType(ResNo: 0);
819 EVT NVT = Op.getValueType();
820 SDLoc dl(N);
821
822 // If the larger CTTZ isn't supported by the target, try to expand now.
823 // If we expand later we'll end up with more operations since we lost the
824 // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
825 // larger type.
826 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
827 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ, VT: NVT) &&
828 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ_ZERO_UNDEF, VT: NVT) &&
829 !TLI.isOperationLegal(Op: ISD::CTPOP, VT: NVT) &&
830 !TLI.isOperationLegal(Op: ISD::CTLZ, VT: NVT)) {
831 if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
832 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
833 return Result;
834 }
835 }
836
837 unsigned NewOpc = N->getOpcode();
838 if (NewOpc == ISD::CTTZ || NewOpc == ISD::VP_CTTZ) {
839 // The count is the same in the promoted type except if the original
840 // value was zero. This can be handled by setting the bit just off
841 // the top of the original type.
842 auto TopBit = APInt::getOneBitSet(numBits: NVT.getScalarSizeInBits(),
843 BitNo: OVT.getScalarSizeInBits());
844 if (NewOpc == ISD::CTTZ) {
845 Op = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
846 NewOpc = ISD::CTTZ_ZERO_UNDEF;
847 } else {
848 Op =
849 DAG.getNode(Opcode: ISD::VP_OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT),
850 N3: N->getOperand(Num: 1), N4: N->getOperand(Num: 2));
851 NewOpc = ISD::VP_CTTZ_ZERO_UNDEF;
852 }
853 }
854 if (!N->isVPOpcode())
855 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Op);
856 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, N1: Op, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
857}
858
859SDValue DAGTypeLegalizer::PromoteIntRes_VP_CttzElements(SDNode *N) {
860 SDLoc DL(N);
861 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
862 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NewVT, Ops: N->ops());
863}
864
865SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
866 SDLoc dl(N);
867 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
868
869 SDValue Op0 = N->getOperand(Num: 0);
870 SDValue Op1 = N->getOperand(Num: 1);
871
872 // If the input also needs to be promoted, do that first so we can get a
873 // get a good idea for the output type.
874 if (TLI.getTypeAction(Context&: *DAG.getContext(), VT: Op0.getValueType())
875 == TargetLowering::TypePromoteInteger) {
876 SDValue In = GetPromotedInteger(Op: Op0);
877
878 // If the new type is larger than NVT, use it. We probably won't need to
879 // promote it again.
880 EVT SVT = In.getValueType().getScalarType();
881 if (SVT.bitsGE(VT: NVT)) {
882 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SVT, N1: In, N2: Op1);
883 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NVT);
884 }
885 }
886
887 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NVT, N1: Op0, N2: Op1);
888}
889
890SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
891 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
892 unsigned NewOpc =
893 TLI.getPreferredFPToIntOpcode(Op: N->getOpcode(), FromVT: N->getValueType(ResNo: 0), ToVT: NVT);
894 SDLoc dl(N);
895
896 SDValue Res;
897 if (N->isStrictFPOpcode()) {
898 Res = DAG.getNode(Opcode: NewOpc, DL: dl, ResultTys: {NVT, MVT::Other},
899 Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1)});
900 // Legalize the chain result - switch anything that used the old chain to
901 // use the new one.
902 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
903 } else if (NewOpc == ISD::VP_FP_TO_SINT || NewOpc == ISD::VP_FP_TO_UINT) {
904 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1),
905 N->getOperand(Num: 2)});
906 } else {
907 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
908 }
909
910 // Assert that the converted value fits in the original type. If it doesn't
911 // (eg: because the value being converted is too big), then the result of the
912 // original operation was undefined anyway, so the assert is still correct.
913 //
914 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
915 // before legalization: fp-to-uint16, 65534. -> 0xfffe
916 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
917 return DAG.getNode(Opcode: (N->getOpcode() == ISD::FP_TO_UINT ||
918 N->getOpcode() == ISD::STRICT_FP_TO_UINT ||
919 N->getOpcode() == ISD::VP_FP_TO_UINT)
920 ? ISD::AssertZext
921 : ISD::AssertSext,
922 DL: dl, VT: NVT, N1: Res,
923 N2: DAG.getValueType(N->getValueType(ResNo: 0).getScalarType()));
924}
925
926SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
927 // Promote the result type, while keeping the original width in Op1.
928 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
929 SDLoc dl(N);
930 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
931 N2: N->getOperand(Num: 1));
932}
933
934SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16_BF16(SDNode *N) {
935 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
936 SDLoc dl(N);
937
938 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
939}
940
941SDValue DAGTypeLegalizer::PromoteIntRes_STRICT_FP_TO_FP16_BF16(SDNode *N) {
942 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
943 SDLoc dl(N);
944
945 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
946 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
947 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
948 return Res;
949}
950
951SDValue DAGTypeLegalizer::PromoteIntRes_XRINT(SDNode *N) {
952 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
953 SDLoc dl(N);
954 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
955}
956
957SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) {
958 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
959 SDLoc dl(N);
960
961 SDValue Res =
962 DAG.getNode(Opcode: N->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
963
964 // Legalize the chain result - switch anything that used the old chain to
965 // use the new one.
966 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
967 return Res;
968}
969
970SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
971 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
972 SDLoc dl(N);
973
974 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
975 == TargetLowering::TypePromoteInteger) {
976 SDValue Res = GetPromotedInteger(Op: N->getOperand(Num: 0));
977 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
978
979 // If the result and operand types are the same after promotion, simplify
980 // to an in-register extension. Unless this is a VP_*_EXTEND.
981 if (NVT == Res.getValueType() && N->getNumOperands() == 1) {
982 // The high bits are not guaranteed to be anything. Insert an extend.
983 if (N->getOpcode() == ISD::SIGN_EXTEND)
984 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
985 N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
986 if (N->getOpcode() == ISD::ZERO_EXTEND)
987 return DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: N->getOperand(Num: 0).getValueType());
988 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
989 return Res;
990 }
991 }
992
993 // Otherwise, just extend the original operand all the way to the larger type.
994 if (N->getNumOperands() != 1) {
995 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
996 assert(N->isVPOpcode() && "Expected VP opcode");
997 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
998 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
999 }
1000 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
1001}
1002
1003SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
1004 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1005 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1006 ISD::LoadExtType ExtType =
1007 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
1008 SDLoc dl(N);
1009 SDValue Res = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
1010 MemVT: N->getMemoryVT(), MMO: N->getMemOperand());
1011
1012 // Legalize the chain result - switch anything that used the old chain to
1013 // use the new one.
1014 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1015 return Res;
1016}
1017
1018SDValue DAGTypeLegalizer::PromoteIntRes_VP_LOAD(VPLoadSDNode *N) {
1019 assert(!N->isIndexed() && "Indexed vp_load during type legalization!");
1020 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1021 ISD::LoadExtType ExtType = (N->getExtensionType() == ISD::NON_EXTLOAD)
1022 ? ISD::EXTLOAD
1023 : N->getExtensionType();
1024 SDLoc dl(N);
1025 SDValue Res =
1026 DAG.getExtLoadVP(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
1027 Mask: N->getMask(), EVL: N->getVectorLength(), MemVT: N->getMemoryVT(),
1028 MMO: N->getMemOperand(), IsExpanding: N->isExpandingLoad());
1029 // Legalize the chain result - switch anything that used the old chain to
1030 // use the new one.
1031 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1032 return Res;
1033}
1034
1035SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
1036 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1037 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1038
1039 ISD::LoadExtType ExtType = N->getExtensionType();
1040 if (ExtType == ISD::NON_EXTLOAD)
1041 ExtType = ISD::EXTLOAD;
1042
1043 SDLoc dl(N);
1044 SDValue Res = DAG.getMaskedLoad(VT: NVT, dl, Chain: N->getChain(), Base: N->getBasePtr(),
1045 Offset: N->getOffset(), Mask: N->getMask(), Src0: ExtPassThru,
1046 MemVT: N->getMemoryVT(), MMO: N->getMemOperand(),
1047 AM: N->getAddressingMode(), ExtType,
1048 IsExpanding: N->isExpandingLoad());
1049 // Legalize the chain result - switch anything that used the old chain to
1050 // use the new one.
1051 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1052 return Res;
1053}
1054
1055SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
1056 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1057 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1058 assert(NVT == ExtPassThru.getValueType() &&
1059 "Gather result type and the passThru argument type should be the same");
1060
1061 ISD::LoadExtType ExtType = N->getExtensionType();
1062 if (ExtType == ISD::NON_EXTLOAD)
1063 ExtType = ISD::EXTLOAD;
1064
1065 SDLoc dl(N);
1066 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
1067 N->getIndex(), N->getScale() };
1068 SDValue Res = DAG.getMaskedGather(VTs: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
1069 MemVT: N->getMemoryVT(), dl, Ops,
1070 MMO: N->getMemOperand(), IndexType: N->getIndexType(),
1071 ExtTy: ExtType);
1072 // Legalize the chain result - switch anything that used the old chain to
1073 // use the new one.
1074 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1075 return Res;
1076}
1077
1078SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_COMPRESS(SDNode *N) {
1079 SDValue Vec = GetPromotedInteger(Op: N->getOperand(Num: 0));
1080 SDValue Passthru = GetPromotedInteger(Op: N->getOperand(Num: 2));
1081 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT: Vec.getValueType(), N1: Vec,
1082 N2: N->getOperand(Num: 1), N3: Passthru);
1083}
1084
1085/// Promote the overflow flag of an overflowing arithmetic node.
1086SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
1087 // Change the return type of the boolean result while obeying
1088 // getSetCCResultType.
1089 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1090 EVT VT = N->getValueType(ResNo: 0);
1091 EVT SVT = getSetCCResultType(VT);
1092 SDValue Ops[3] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
1093 unsigned NumOps = N->getNumOperands();
1094 assert(NumOps <= 3 && "Too many operands");
1095 if (NumOps == 3)
1096 Ops[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: VT);
1097
1098 SDLoc dl(N);
1099 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: SVT),
1100 Ops: ArrayRef(Ops, NumOps));
1101
1102 // Modified the sum result - switch anything that used the old sum to use
1103 // the new one.
1104 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1105
1106 // Convert to the expected type.
1107 return DAG.getBoolExtOrTrunc(Op: Res.getValue(R: 1), SL: dl, VT: NVT, OpVT: VT);
1108}
1109
1110template <class MatchContextClass>
1111SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
1112 // If the promoted type is legal, we can convert this to:
1113 // 1. ANY_EXTEND iN to iM
1114 // 2. SHL by M-N
1115 // 3. [US][ADD|SUB|SHL]SAT
1116 // 4. L/ASHR by M-N
1117 // Else it is more efficient to convert this to a min and a max
1118 // operation in the higher precision arithmetic.
1119 SDLoc dl(N);
1120 SDValue Op1 = N->getOperand(Num: 0);
1121 SDValue Op2 = N->getOperand(Num: 1);
1122 MatchContextClass matcher(DAG, TLI, N);
1123
1124 unsigned Opcode = matcher.getRootBaseOpcode();
1125 unsigned OldBits = Op1.getScalarValueSizeInBits();
1126
1127 // USUBSAT can always be promoted as long as we have zero/sign-extended the
1128 // args.
1129 if (Opcode == ISD::USUBSAT) {
1130 SExtOrZExtPromotedOperands(LHS&: Op1, RHS&: Op2);
1131 return matcher.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
1132 }
1133
1134 if (Opcode == ISD::UADDSAT) {
1135 EVT OVT = Op1.getValueType();
1136 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1137 // We can promote if we use sign-extend. Do this if the target prefers.
1138 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT)) {
1139 Op1 = SExtPromotedInteger(Op: Op1);
1140 Op2 = SExtPromotedInteger(Op: Op2);
1141 return matcher.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2);
1142 }
1143
1144 Op1 = ZExtPromotedInteger(Op: Op1);
1145 Op2 = ZExtPromotedInteger(Op: Op2);
1146 unsigned NewBits = NVT.getScalarSizeInBits();
1147 APInt MaxVal = APInt::getLowBitsSet(numBits: NewBits, loBitsSet: OldBits);
1148 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: NVT);
1149 SDValue Add = matcher.getNode(ISD::ADD, dl, NVT, Op1, Op2);
1150 return matcher.getNode(ISD::UMIN, dl, NVT, Add, SatMax);
1151 }
1152
1153 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
1154
1155 // FIXME: We need vp-aware PromotedInteger functions.
1156 if (IsShift) {
1157 Op1 = GetPromotedInteger(Op: Op1);
1158 if (getTypeAction(VT: Op2.getValueType()) == TargetLowering::TypePromoteInteger)
1159 Op2 = ZExtPromotedInteger(Op: Op2);
1160 } else {
1161 Op1 = SExtPromotedInteger(Op: Op1);
1162 Op2 = SExtPromotedInteger(Op: Op2);
1163 }
1164 EVT PromotedType = Op1.getValueType();
1165 unsigned NewBits = PromotedType.getScalarSizeInBits();
1166
1167 // Shift cannot use a min/max expansion, we can't detect overflow if all of
1168 // the bits have been shifted out.
1169 if (IsShift || matcher.isOperationLegal(Opcode, PromotedType)) {
1170 unsigned ShiftOp;
1171 switch (Opcode) {
1172 case ISD::SADDSAT:
1173 case ISD::SSUBSAT:
1174 case ISD::SSHLSAT:
1175 ShiftOp = ISD::SRA;
1176 break;
1177 case ISD::USHLSAT:
1178 ShiftOp = ISD::SRL;
1179 break;
1180 default:
1181 llvm_unreachable("Expected opcode to be signed or unsigned saturation "
1182 "addition, subtraction or left shift");
1183 }
1184
1185 unsigned SHLAmount = NewBits - OldBits;
1186 SDValue ShiftAmount =
1187 DAG.getShiftAmountConstant(Val: SHLAmount, VT: PromotedType, DL: dl);
1188 Op1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1, N2: ShiftAmount);
1189 if (!IsShift)
1190 Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
1191
1192 SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
1193 return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
1194 }
1195
1196 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
1197 APInt MinVal = APInt::getSignedMinValue(numBits: OldBits).sext(width: NewBits);
1198 APInt MaxVal = APInt::getSignedMaxValue(numBits: OldBits).sext(width: NewBits);
1199 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT: PromotedType);
1200 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: PromotedType);
1201 SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
1202 Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
1203 Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
1204 return Result;
1205}
1206
1207SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
1208 // Can just promote the operands then continue with operation.
1209 SDLoc dl(N);
1210 SDValue Op1Promoted, Op2Promoted;
1211 bool Signed =
1212 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
1213 bool Saturating =
1214 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
1215 if (Signed) {
1216 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1217 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1218 } else {
1219 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1220 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1221 }
1222 EVT OldType = N->getOperand(Num: 0).getValueType();
1223 EVT PromotedType = Op1Promoted.getValueType();
1224 unsigned DiffSize =
1225 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
1226
1227 if (Saturating) {
1228 // Promoting the operand and result values changes the saturation width,
1229 // which is extends the values that we clamp to on saturation. This could be
1230 // resolved by shifting one of the operands the same amount, which would
1231 // also shift the result we compare against, then shifting back.
1232 Op1Promoted =
1233 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1234 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1235 SDValue Result = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1236 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1237 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1238 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result,
1239 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1240 }
1241 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted, N2: Op2Promoted,
1242 N3: N->getOperand(Num: 2));
1243}
1244
1245static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
1246 unsigned SatW, bool Signed,
1247 const TargetLowering &TLI,
1248 SelectionDAG &DAG) {
1249 EVT VT = V.getValueType();
1250 unsigned VTW = VT.getScalarSizeInBits();
1251
1252 if (!Signed) {
1253 // Saturate to the unsigned maximum by getting the minimum of V and the
1254 // maximum.
1255 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT, N1: V,
1256 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW),
1257 DL: dl, VT));
1258 }
1259
1260 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
1261 // signed minimum of it and V.
1262 V = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT, N1: V,
1263 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW - 1),
1264 DL: dl, VT));
1265 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
1266 // signed maximum of it and V.
1267 V = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT, N1: V,
1268 N2: DAG.getConstant(Val: APInt::getHighBitsSet(numBits: VTW, hiBitsSet: VTW - SatW + 1),
1269 DL: dl, VT));
1270 return V;
1271}
1272
1273static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
1274 unsigned Scale, const TargetLowering &TLI,
1275 SelectionDAG &DAG, unsigned SatW = 0) {
1276 EVT VT = LHS.getValueType();
1277 unsigned VTSize = VT.getScalarSizeInBits();
1278 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1279 N->getOpcode() == ISD::SDIVFIXSAT;
1280 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1281 N->getOpcode() == ISD::UDIVFIXSAT;
1282
1283 SDLoc dl(N);
1284 // Widen the types by a factor of two. This is guaranteed to expand, since it
1285 // will always have enough high bits in the LHS to shift into.
1286 EVT WideVT = VT.changeElementType(
1287 Context&: *DAG.getContext(), EltVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: VTSize * 2));
1288 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL: dl, VT: WideVT);
1289 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL: dl, VT: WideVT);
1290 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS, RHS, Scale,
1291 DAG);
1292 assert(Res && "Expanding DIVFIX with wide type failed?");
1293 if (Saturating) {
1294 // If the caller has told us to saturate at something less, use that width
1295 // instead of the type before doubling. However, it cannot be more than
1296 // what we just widened!
1297 assert(SatW <= VTSize &&
1298 "Tried to saturate to more than the original type?");
1299 Res = SaturateWidenedDIVFIX(V: Res, dl, SatW: SatW == 0 ? VTSize : SatW, Signed,
1300 TLI, DAG);
1301 }
1302 return DAG.getZExtOrTrunc(Op: Res, DL: dl, VT);
1303}
1304
1305SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1306 SDLoc dl(N);
1307 SDValue Op1Promoted, Op2Promoted;
1308 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1309 N->getOpcode() == ISD::SDIVFIXSAT;
1310 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1311 N->getOpcode() == ISD::UDIVFIXSAT;
1312 if (Signed) {
1313 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1314 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1315 } else {
1316 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1317 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1318 }
1319 EVT PromotedType = Op1Promoted.getValueType();
1320 unsigned Scale = N->getConstantOperandVal(Num: 2);
1321
1322 // If the type is already legal and the operation is legal in that type, we
1323 // should not early expand.
1324 if (TLI.isTypeLegal(VT: PromotedType)) {
1325 TargetLowering::LegalizeAction Action =
1326 TLI.getFixedPointOperationAction(Op: N->getOpcode(), VT: PromotedType, Scale);
1327 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1328 unsigned Diff = PromotedType.getScalarSizeInBits() -
1329 N->getValueType(ResNo: 0).getScalarSizeInBits();
1330 if (Saturating)
1331 Op1Promoted =
1332 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1333 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1334 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1335 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1336 if (Saturating)
1337 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL: dl, VT: PromotedType, N1: Res,
1338 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1339 return Res;
1340 }
1341 }
1342
1343 // See if we can perform the division in this type without expanding.
1344 if (SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: Op1Promoted,
1345 RHS: Op2Promoted, Scale, DAG)) {
1346 if (Saturating)
1347 Res = SaturateWidenedDIVFIX(V: Res, dl,
1348 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits(),
1349 Signed, TLI, DAG);
1350 return Res;
1351 }
1352 // If we cannot, expand it to twice the type width. If we are saturating, give
1353 // it the original width as a saturating width so we don't need to emit
1354 // two saturations.
1355 return earlyExpandDIVFIX(N, LHS: Op1Promoted, RHS: Op2Promoted, Scale, TLI, DAG,
1356 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits());
1357}
1358
1359SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1360 if (ResNo == 1)
1361 return PromoteIntRes_Overflow(N);
1362
1363 // The operation overflowed iff the result in the larger type is not the
1364 // sign extension of its truncation to the original type.
1365 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1366 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1367 EVT OVT = N->getOperand(Num: 0).getValueType();
1368 EVT NVT = LHS.getValueType();
1369 SDLoc dl(N);
1370
1371 // Do the arithmetic in the larger type.
1372 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1373 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1374
1375 // Calculate the overflow flag: sign extend the arithmetic result from
1376 // the original type.
1377 SDValue Ofl = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1378 N2: DAG.getValueType(OVT));
1379 // Overflowed if and only if this is not equal to Res.
1380 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1381
1382 // Use the calculated overflow everywhere.
1383 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1384
1385 return Res;
1386}
1387
1388SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
1389 EVT PromotedResultTy =
1390 TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1391 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: PromotedResultTy,
1392 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
1393}
1394
1395SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1396 SDValue Mask = N->getOperand(Num: 0);
1397
1398 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1399 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1400
1401 unsigned Opcode = N->getOpcode();
1402 if (Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE)
1403 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS,
1404 N4: N->getOperand(Num: 3));
1405 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS);
1406}
1407
1408SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1409 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1410 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 3));
1411 return DAG.getNode(Opcode: ISD::SELECT_CC, DL: SDLoc(N),
1412 VT: LHS.getValueType(), N1: N->getOperand(Num: 0),
1413 N2: N->getOperand(Num: 1), N3: LHS, N4: RHS, N5: N->getOperand(Num: 4));
1414}
1415
1416SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1417 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1418 EVT InVT = N->getOperand(Num: OpNo).getValueType();
1419 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1420
1421 EVT SVT = getSetCCResultType(VT: InVT);
1422
1423 // If we got back a type that needs to be promoted, this likely means the
1424 // the input type also needs to be promoted. So get the promoted type for
1425 // the input and try the query again.
1426 if (getTypeAction(VT: SVT) == TargetLowering::TypePromoteInteger) {
1427 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
1428 InVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
1429 SVT = getSetCCResultType(VT: InVT);
1430 } else {
1431 // Input type isn't promoted, just use the default promoted type.
1432 SVT = NVT;
1433 }
1434 }
1435
1436 SDLoc dl(N);
1437 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1438 "Vector compare must return a vector result!");
1439
1440 // Get the SETCC result using the canonical SETCC type.
1441 SDValue SetCC;
1442 if (N->isStrictFPOpcode()) {
1443 SDVTList VTs = DAG.getVTList(VTs: {SVT, MVT::Other});
1444 SDValue Opers[] = {N->getOperand(Num: 0), N->getOperand(Num: 1),
1445 N->getOperand(Num: 2), N->getOperand(Num: 3)};
1446 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: VTs, Ops: Opers, Flags: N->getFlags());
1447 // Legalize the chain result - switch anything that used the old chain to
1448 // use the new one.
1449 ReplaceValueWith(From: SDValue(N, 1), To: SetCC.getValue(R: 1));
1450 } else
1451 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: SVT, N1: N->getOperand(Num: 0),
1452 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), Flags: N->getFlags());
1453
1454 // Convert to the expected type.
1455 return DAG.getSExtOrTrunc(Op: SetCC, DL: dl, VT: NVT);
1456}
1457
1458SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
1459 SDLoc DL(N);
1460 SDValue Arg = N->getOperand(Num: 0);
1461 SDValue Test = N->getOperand(Num: 1);
1462 EVT NResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1463 return DAG.getNode(Opcode: ISD::IS_FPCLASS, DL, VT: NResVT, N1: Arg, N2: Test);
1464}
1465
1466SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
1467 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1468 EVT VT = N->getValueType(ResNo: 0);
1469
1470 SDLoc dl(N);
1471 SDValue Res =
1472 DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: NVT), N: N->getOperand(Num: 0));
1473
1474 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1475 return Res.getValue(R: 1);
1476}
1477
1478SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1479 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1480 SDValue RHS = N->getOperand(Num: 1);
1481 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1482 RHS = ZExtPromotedInteger(Op: RHS);
1483 if (N->getOpcode() != ISD::VP_SHL)
1484 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1485
1486 SDValue Mask = N->getOperand(Num: 2);
1487 SDValue EVL = N->getOperand(Num: 3);
1488 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1489 N3: Mask, N4: EVL);
1490}
1491
1492SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1493 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
1494 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: SDLoc(N),
1495 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
1496}
1497
1498SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1499 // The input may have strange things in the top bits of the registers, but
1500 // these operations don't care. They may have weird bits going out, but
1501 // that too is okay if they are integer operations.
1502 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1503 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1504 if (N->getNumOperands() == 2)
1505 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1506 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1507 assert(N->isVPOpcode() && "Expected VP opcode");
1508 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1509 N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
1510}
1511
1512SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1513 // Sign extend the input.
1514 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1515 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1516 if (N->getNumOperands() == 2)
1517 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1518 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1519 assert(N->isVPOpcode() && "Expected VP opcode");
1520 SDValue Mask = N->getOperand(Num: 2);
1521 SDValue EVL = N->getOperand(Num: 3);
1522 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1523 N3: Mask, N4: EVL);
1524}
1525
1526SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1527 // Zero extend the input.
1528 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1529 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1530 if (N->getNumOperands() == 2)
1531 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1532 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1533 assert(N->isVPOpcode() && "Expected VP opcode");
1534 // Zero extend the input.
1535 SDValue Mask = N->getOperand(Num: 2);
1536 SDValue EVL = N->getOperand(Num: 3);
1537 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1538 N3: Mask, N4: EVL);
1539}
1540
1541SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1542 SDValue LHS = N->getOperand(Num: 0);
1543 SDValue RHS = N->getOperand(Num: 1);
1544
1545 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1546 // whatever is best for the target and the promoted operands.
1547 SExtOrZExtPromotedOperands(LHS, RHS);
1548
1549 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N),
1550 VT: LHS.getValueType(), N1: LHS, N2: RHS);
1551}
1552
1553SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1554 // The input value must be properly sign extended.
1555 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1556 SDValue RHS = N->getOperand(Num: 1);
1557 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1558 RHS = ZExtPromotedInteger(Op: RHS);
1559 if (N->getOpcode() != ISD::VP_SRA)
1560 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1561
1562 SDValue Mask = N->getOperand(Num: 2);
1563 SDValue EVL = N->getOperand(Num: 3);
1564 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1565 N3: Mask, N4: EVL);
1566}
1567
1568SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1569 SDValue RHS = N->getOperand(Num: 1);
1570 // The input value must be properly zero extended.
1571 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1572 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1573 RHS = ZExtPromotedInteger(Op: RHS);
1574 if (N->getOpcode() != ISD::VP_SRL)
1575 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1576
1577 SDValue Mask = N->getOperand(Num: 2);
1578 SDValue EVL = N->getOperand(Num: 3);
1579 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1580 N3: Mask, N4: EVL);
1581}
1582
1583SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1584 // Lower the rotate to shifts and ORs which can be promoted.
1585 SDValue Res = TLI.expandROT(N, AllowVectorOps: true /*AllowVectorOps*/, DAG);
1586 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1587 return SDValue();
1588}
1589
1590SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1591 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1592 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1593 SDValue Amt = N->getOperand(Num: 2);
1594 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1595 Amt = ZExtPromotedInteger(Op: Amt);
1596 EVT AmtVT = Amt.getValueType();
1597
1598 SDLoc DL(N);
1599 EVT OldVT = N->getOperand(Num: 0).getValueType();
1600 EVT VT = Lo.getValueType();
1601 unsigned Opcode = N->getOpcode();
1602 bool IsFSHR = Opcode == ISD::FSHR;
1603 unsigned OldBits = OldVT.getScalarSizeInBits();
1604 unsigned NewBits = VT.getScalarSizeInBits();
1605
1606 // Amount has to be interpreted modulo the old bit width.
1607 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1608 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1609
1610 // If the promoted type is twice the size (or more), then we use the
1611 // traditional funnel 'double' shift codegen. This isn't necessary if the
1612 // shift amount is constant.
1613 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1614 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1615 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1616 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1617 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1618 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: HiShift);
1619 Lo = DAG.getZeroExtendInReg(Op: Lo, DL, VT: OldVT);
1620 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1621 Res = DAG.getNode(Opcode: IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1622 if (!IsFSHR)
1623 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1624 return Res;
1625 }
1626
1627 // Shift Lo up to occupy the upper bits of the promoted type.
1628 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Lo,
1629 N2: DAG.getShiftAmountConstant(Val: NewBits - OldBits, VT, DL));
1630
1631 // Increase Amount to shift the result into the lower bits of the promoted
1632 // type.
1633 if (IsFSHR)
1634 Amt = DAG.getNode(Opcode: ISD::ADD, DL, VT: AmtVT, N1: Amt,
1635 N2: DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT));
1636
1637 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt);
1638}
1639
1640// A vp version of PromoteIntRes_FunnelShift.
1641SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
1642 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1643 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1644 SDValue Amt = N->getOperand(Num: 2);
1645 SDValue Mask = N->getOperand(Num: 3);
1646 SDValue EVL = N->getOperand(Num: 4);
1647 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1648 Amt = ZExtPromotedInteger(Op: Amt);
1649 EVT AmtVT = Amt.getValueType();
1650
1651 SDLoc DL(N);
1652 EVT OldVT = N->getOperand(Num: 0).getValueType();
1653 EVT VT = Lo.getValueType();
1654 unsigned Opcode = N->getOpcode();
1655 bool IsFSHR = Opcode == ISD::VP_FSHR;
1656 unsigned OldBits = OldVT.getScalarSizeInBits();
1657 unsigned NewBits = VT.getScalarSizeInBits();
1658
1659 // Amount has to be interpreted modulo the old bit width.
1660 Amt = DAG.getNode(Opcode: ISD::VP_UREM, DL, VT: AmtVT, N1: Amt,
1661 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT), N3: Mask, N4: EVL);
1662
1663 // If the promoted type is twice the size (or more), then we use the
1664 // traditional funnel 'double' shift codegen. This isn't necessary if the
1665 // shift amount is constant.
1666 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1667 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1668 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1669 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1670 SDValue HiShift = DAG.getConstant(Val: OldBits, DL, VT);
1671 Hi = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Hi, N2: HiShift, N3: Mask, N4: EVL);
1672 Lo = DAG.getVPZeroExtendInReg(Op: Lo, Mask, EVL, DL, VT: OldVT);
1673 SDValue Res = DAG.getNode(Opcode: ISD::VP_OR, DL, VT, N1: Hi, N2: Lo, N3: Mask, N4: EVL);
1674 Res = DAG.getNode(Opcode: IsFSHR ? ISD::VP_SRL : ISD::VP_SHL, DL, VT, N1: Res, N2: Amt,
1675 N3: Mask, N4: EVL);
1676 if (!IsFSHR)
1677 Res = DAG.getNode(Opcode: ISD::VP_SRL, DL, VT, N1: Res, N2: HiShift, N3: Mask, N4: EVL);
1678 return Res;
1679 }
1680
1681 // Shift Lo up to occupy the upper bits of the promoted type.
1682 SDValue ShiftOffset = DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT);
1683 Lo = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Lo, N2: ShiftOffset, N3: Mask, N4: EVL);
1684
1685 // Increase Amount to shift the result into the lower bits of the promoted
1686 // type.
1687 if (IsFSHR)
1688 Amt = DAG.getNode(Opcode: ISD::VP_ADD, DL, VT: AmtVT, N1: Amt, N2: ShiftOffset, N3: Mask, N4: EVL);
1689
1690 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt, N4: Mask, N5: EVL);
1691}
1692
1693SDValue DAGTypeLegalizer::PromoteIntRes_CLMUL(SDNode *N) {
1694 unsigned Opcode = N->getOpcode();
1695
1696 SDLoc DL(N);
1697 EVT OldVT = N->getOperand(Num: 0).getValueType();
1698 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1699
1700 if (Opcode == ISD::CLMUL) {
1701 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CLMUL, VT)) {
1702 if (SDValue Res = TLI.expandCLMUL(N, DAG))
1703 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1704 }
1705 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1706 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1707 return DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1708 }
1709
1710 SDValue X = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1711 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1712
1713 unsigned OldBits = OldVT.getScalarSizeInBits();
1714 unsigned NewBits = VT.getScalarSizeInBits();
1715 if (NewBits < 2 * OldBits) {
1716 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1717 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1718 SDValue Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1719 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1720 SDValue Clmulh = DAG.getNode(Opcode: ISD::CLMULH, DL, VT, N1: X, N2: Y);
1721 ShAmt = Opcode == ISD::CLMULH ? NewBits - OldBits : NewBits - OldBits + 1;
1722 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Clmulh,
1723 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1724 return DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Lo, N2: Hi);
1725 }
1726
1727 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1728 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1729 return DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1730 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1731}
1732
1733SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1734 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1735 SDValue Res;
1736 SDValue InOp = N->getOperand(Num: 0);
1737 SDLoc dl(N);
1738
1739 switch (getTypeAction(VT: InOp.getValueType())) {
1740 default: llvm_unreachable("Unknown type action!");
1741 case TargetLowering::TypeLegal:
1742 case TargetLowering::TypeExpandInteger:
1743 Res = InOp;
1744 break;
1745 case TargetLowering::TypePromoteInteger:
1746 Res = GetPromotedInteger(Op: InOp);
1747 break;
1748 case TargetLowering::TypeSplitVector: {
1749 EVT InVT = InOp.getValueType();
1750 assert(InVT.isVector() && "Cannot split scalar types");
1751 ElementCount NumElts = InVT.getVectorElementCount();
1752 assert(NumElts == NVT.getVectorElementCount() &&
1753 "Dst and Src must have the same number of elements");
1754 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1755 "Promoted vector type must be a power of two");
1756
1757 SDValue EOp1, EOp2;
1758 GetSplitVector(Op: InOp, Lo&: EOp1, Hi&: EOp2);
1759
1760 EVT HalfNVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getScalarType(),
1761 EC: NumElts.divideCoefficientBy(RHS: 2));
1762 if (N->getOpcode() == ISD::TRUNCATE) {
1763 EOp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp1);
1764 EOp2 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp2);
1765 } else {
1766 assert(N->getOpcode() == ISD::VP_TRUNCATE &&
1767 "Expected VP_TRUNCATE opcode");
1768 SDValue MaskLo, MaskHi, EVLLo, EVLHi;
1769 std::tie(args&: MaskLo, args&: MaskHi) = SplitMask(Mask: N->getOperand(Num: 1));
1770 std::tie(args&: EVLLo, args&: EVLHi) =
1771 DAG.SplitEVL(N: N->getOperand(Num: 2), VecVT: N->getValueType(ResNo: 0), DL: dl);
1772 EOp1 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp1, N2: MaskLo, N3: EVLLo);
1773 EOp2 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp2, N2: MaskHi, N3: EVLHi);
1774 }
1775 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl, VT: NVT, N1: EOp1, N2: EOp2);
1776 }
1777 // TODO: VP_TRUNCATE need to handle when TypeWidenVector access to some
1778 // targets.
1779 case TargetLowering::TypeWidenVector: {
1780 SDValue WideInOp = GetWidenedVector(Op: InOp);
1781
1782 // Truncate widened InOp.
1783 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1784 EVT TruncVT = EVT::getVectorVT(Context&: *DAG.getContext(),
1785 VT: N->getValueType(ResNo: 0).getScalarType(), NumElements: NumElem);
1786 SDValue WideTrunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: TruncVT, Operand: WideInOp);
1787
1788 // Zero extend so that the elements are of same type as those of NVT
1789 EVT ExtVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getVectorElementType(),
1790 NumElements: NumElem);
1791 SDValue WideExt = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: ExtVT, Operand: WideTrunc);
1792
1793 // Extract the low NVT subvector.
1794 SDValue ZeroIdx = DAG.getVectorIdxConstant(Val: 0, DL: dl);
1795 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NVT, N1: WideExt, N2: ZeroIdx);
1796 }
1797 }
1798
1799 // Truncate to NVT instead of VT
1800 if (N->getOpcode() == ISD::VP_TRUNCATE)
1801 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: NVT, N1: Res, N2: N->getOperand(Num: 1),
1802 N3: N->getOperand(Num: 2));
1803 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Res);
1804}
1805
1806SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1807 if (ResNo == 1)
1808 return PromoteIntRes_Overflow(N);
1809
1810 // The operation overflowed iff the result in the larger type is not the
1811 // zero extension of its truncation to the original type.
1812 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1813 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1814 EVT OVT = N->getOperand(Num: 0).getValueType();
1815 EVT NVT = LHS.getValueType();
1816 SDLoc dl(N);
1817
1818 // Do the arithmetic in the larger type.
1819 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1820 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1821
1822 // Calculate the overflow flag: zero extend the arithmetic result from
1823 // the original type.
1824 SDValue Ofl = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: OVT);
1825 // Overflowed if and only if this is not equal to Res.
1826 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1827
1828 // Use the calculated overflow everywhere.
1829 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1830
1831 return Res;
1832}
1833
1834// Handle promotion for the ADDE/SUBE/UADDO_CARRY/USUBO_CARRY nodes. Notice that
1835// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1836// the UADDO_CARRY/USUBO_CARRY nodes in that the third operand is carry Boolean.
1837SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO_CARRY(SDNode *N,
1838 unsigned ResNo) {
1839 if (ResNo == 1)
1840 return PromoteIntRes_Overflow(N);
1841
1842 // We need to sign-extend the operands so the carry value computed by the
1843 // wide operation will be equivalent to the carry value computed by the
1844 // narrow operation.
1845 // An UADDO_CARRY can generate carry only if any of the operands has its
1846 // most significant bit set. Sign extension propagates the most significant
1847 // bit into the higher bits which means the extra bit that the narrow
1848 // addition would need (i.e. the carry) will be propagated through the higher
1849 // bits of the wide addition.
1850 // A USUBO_CARRY can generate borrow only if LHS < RHS and this property will
1851 // be preserved by sign extension.
1852 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1853 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1854
1855 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(ResNo: 1)};
1856
1857 // Do the arithmetic in the wide type.
1858 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VTList: DAG.getVTList(VTs: ValueVTs),
1859 N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
1860
1861 // Update the users of the original carry/borrow value.
1862 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1863
1864 return SDValue(Res.getNode(), 0);
1865}
1866
1867SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1868 unsigned ResNo) {
1869 assert(ResNo == 1 && "Don't know how to promote other results yet.");
1870 return PromoteIntRes_Overflow(N);
1871}
1872
1873SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1874 EVT OVT = N->getValueType(ResNo: 0);
1875 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1876
1877 // If a larger ABS or SMAX isn't supported by the target, try to expand now.
1878 // If we expand later we'll end up sign extending more than just the sra input
1879 // in sra+xor+sub expansion.
1880 if (!OVT.isVector() &&
1881 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS, VT: NVT) &&
1882 !TLI.isOperationLegal(Op: ISD::SMAX, VT: NVT)) {
1883 if (SDValue Res = TLI.expandABS(N, DAG))
1884 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Res);
1885 }
1886
1887 SDValue Op0 = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1888 return DAG.getNode(Opcode: ISD::ABS, DL: SDLoc(N), VT: Op0.getValueType(), Operand: Op0);
1889}
1890
1891SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1892 // Promote the overflow bit trivially.
1893 if (ResNo == 1)
1894 return PromoteIntRes_Overflow(N);
1895
1896 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
1897 SDLoc DL(N);
1898 EVT SmallVT = LHS.getValueType();
1899
1900 // To determine if the result overflowed in a larger type, we extend the
1901 // input to the larger type, do the multiply (checking if it overflows),
1902 // then also check the high bits of the result to see if overflow happened
1903 // there.
1904 if (N->getOpcode() == ISD::SMULO) {
1905 LHS = SExtPromotedInteger(Op: LHS);
1906 RHS = SExtPromotedInteger(Op: RHS);
1907 } else {
1908 LHS = ZExtPromotedInteger(Op: LHS);
1909 RHS = ZExtPromotedInteger(Op: RHS);
1910 }
1911 SDVTList VTs = DAG.getVTList(VT1: LHS.getValueType(), VT2: N->getValueType(ResNo: 1));
1912 SDValue Mul = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N1: LHS, N2: RHS);
1913
1914 // Overflow occurred if it occurred in the larger type, or if the high part
1915 // of the result does not zero/sign-extend the low part. Check this second
1916 // possibility first.
1917 SDValue Overflow;
1918 if (N->getOpcode() == ISD::UMULO) {
1919 // Unsigned overflow occurred if the high part is non-zero.
1920 unsigned Shift = SmallVT.getScalarSizeInBits();
1921 SDValue Hi =
1922 DAG.getNode(Opcode: ISD::SRL, DL, VT: Mul.getValueType(), N1: Mul,
1923 N2: DAG.getShiftAmountConstant(Val: Shift, VT: Mul.getValueType(), DL));
1924 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: Hi,
1925 RHS: DAG.getConstant(Val: 0, DL, VT: Hi.getValueType()),
1926 Cond: ISD::SETNE);
1927 } else {
1928 // Signed overflow occurred if the high part does not sign extend the low.
1929 SDValue SExt = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: Mul.getValueType(),
1930 N1: Mul, N2: DAG.getValueType(SmallVT));
1931 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: SExt, RHS: Mul, Cond: ISD::SETNE);
1932 }
1933
1934 // The only other way for overflow to occur is if the multiplication in the
1935 // larger type itself overflowed.
1936 Overflow = DAG.getNode(Opcode: ISD::OR, DL, VT: N->getValueType(ResNo: 1), N1: Overflow,
1937 N2: SDValue(Mul.getNode(), 1));
1938
1939 // Use the calculated overflow everywhere.
1940 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
1941 return Mul;
1942}
1943
1944SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1945 return DAG.getUNDEF(VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
1946 VT: N->getValueType(ResNo: 0)));
1947}
1948
1949SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1950 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1951
1952 const APInt &MulImm = N->getConstantOperandAPInt(Num: 0);
1953 return DAG.getVScale(DL: SDLoc(N), VT, MulImm: MulImm.sext(width: VT.getSizeInBits()));
1954}
1955
1956SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1957 SDValue Chain = N->getOperand(Num: 0); // Get the chain.
1958 SDValue Ptr = N->getOperand(Num: 1); // Get the pointer.
1959 EVT VT = N->getValueType(ResNo: 0);
1960 SDLoc dl(N);
1961
1962 MVT RegVT = TLI.getRegisterType(Context&: *DAG.getContext(), VT);
1963 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
1964 // The argument is passed as NumRegs registers of type RegVT.
1965
1966 SmallVector<SDValue, 8> Parts(NumRegs);
1967 for (unsigned i = 0; i < NumRegs; ++i) {
1968 Parts[i] = DAG.getVAArg(VT: RegVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2),
1969 Align: N->getConstantOperandVal(Num: 3));
1970 Chain = Parts[i].getValue(R: 1);
1971 }
1972
1973 // Handle endianness of the load.
1974 if (DAG.getDataLayout().isBigEndian())
1975 std::reverse(first: Parts.begin(), last: Parts.end());
1976
1977 // Assemble the parts in the promoted type.
1978 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1979 SDValue Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[0]);
1980 for (unsigned i = 1; i < NumRegs; ++i) {
1981 SDValue Part = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[i]);
1982 // Shift it to the right position and "or" it in.
1983 Part = DAG.getNode(
1984 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Part,
1985 N2: DAG.getShiftAmountConstant(Val: i * RegVT.getSizeInBits(), VT: NVT, DL: dl));
1986 Res = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Res, N2: Part);
1987 }
1988
1989 // Modified the chain result - switch anything that used the old chain to
1990 // use the new one.
1991 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
1992
1993 return Res;
1994}
1995
1996//===----------------------------------------------------------------------===//
1997// Integer Operand Promotion
1998//===----------------------------------------------------------------------===//
1999
2000/// PromoteIntegerOperand - This method is called when the specified operand of
2001/// the specified node is found to need promotion. At this point, all of the
2002/// result types of the node are known to be legal, but other operands of the
2003/// node may need promotion or expansion as well as the specified one.
2004bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
2005 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG));
2006 SDValue Res = SDValue();
2007 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false)) {
2008 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
2009 return false;
2010 }
2011
2012 switch (N->getOpcode()) {
2013 default:
2014 #ifndef NDEBUG
2015 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
2016 N->dump(&DAG); dbgs() << "\n";
2017 #endif
2018 report_fatal_error(reason: "Do not know how to promote this operator's operand!");
2019
2020 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
2021 case ISD::ANY_EXTEND_VECTOR_INREG:
2022 Res = PromoteIntOp_ANY_EXTEND_VECTOR_INREG(N);
2023 break;
2024 case ISD::ATOMIC_STORE:
2025 Res = PromoteIntOp_ATOMIC_STORE(N: cast<AtomicSDNode>(Val: N));
2026 break;
2027 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
2028 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
2029 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
2030 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
2031 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
2032 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
2033 case ISD::COND_LOOP:
2034 Res = PromoteIntOp_COND_LOOP(N, OpNo);
2035 break;
2036 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
2037 case ISD::FAKE_USE:
2038 Res = PromoteIntOp_FAKE_USE(N);
2039 break;
2040 case ISD::INSERT_VECTOR_ELT:
2041 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
2042 break;
2043 case ISD::SPLAT_VECTOR:
2044 case ISD::SCALAR_TO_VECTOR:
2045 Res = PromoteIntOp_ScalarOp(N);
2046 break;
2047 case ISD::VSELECT:
2048 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
2049 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
2050 case ISD::VP_SETCC:
2051 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
2052 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
2053 case ISD::VP_SIGN_EXTEND: Res = PromoteIntOp_VP_SIGN_EXTEND(N); break;
2054 case ISD::VP_SINT_TO_FP:
2055 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
2056 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
2057 case ISD::STORE: Res = PromoteIntOp_STORE(N: cast<StoreSDNode>(Val: N),
2058 OpNo); break;
2059 case ISD::VP_STORE:
2060 Res = PromoteIntOp_VP_STORE(N: cast<VPStoreSDNode>(Val: N), OpNo);
2061 break;
2062 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(N: cast<MaskedStoreSDNode>(Val: N),
2063 OpNo); break;
2064 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(N: cast<MaskedLoadSDNode>(Val: N),
2065 OpNo); break;
2066 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(N: cast<MaskedGatherSDNode>(Val: N),
2067 OpNo); break;
2068 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(N: cast<MaskedScatterSDNode>(Val: N),
2069 OpNo); break;
2070 case ISD::VECTOR_COMPRESS:
2071 Res = PromoteIntOp_VECTOR_COMPRESS(N, OpNo);
2072 break;
2073 case ISD::VP_TRUNCATE:
2074 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
2075 case ISD::BF16_TO_FP:
2076 case ISD::FP16_TO_FP:
2077 case ISD::VP_UINT_TO_FP:
2078 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
2079 case ISD::STRICT_FP16_TO_FP:
2080 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
2081 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
2082 case ISD::VP_ZERO_EXTEND: Res = PromoteIntOp_VP_ZERO_EXTEND(N); break;
2083 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
2084 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
2085
2086 case ISD::SHL:
2087 case ISD::SRA:
2088 case ISD::SRL:
2089 case ISD::ROTL:
2090 case ISD::ROTR:
2091 case ISD::SSHLSAT:
2092 case ISD::USHLSAT:
2093 Res = PromoteIntOp_Shift(N);
2094 break;
2095
2096 case ISD::SCMP:
2097 case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
2098
2099 case ISD::FSHL:
2100 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
2101
2102 case ISD::FRAMEADDR:
2103 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
2104
2105 case ISD::SMULFIX:
2106 case ISD::SMULFIXSAT:
2107 case ISD::UMULFIX:
2108 case ISD::UMULFIXSAT:
2109 case ISD::SDIVFIX:
2110 case ISD::SDIVFIXSAT:
2111 case ISD::UDIVFIX:
2112 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
2113 case ISD::FPOWI:
2114 case ISD::STRICT_FPOWI:
2115 case ISD::FLDEXP:
2116 case ISD::STRICT_FLDEXP: Res = PromoteIntOp_ExpOp(N); break;
2117 case ISD::VECREDUCE_ADD:
2118 case ISD::VECREDUCE_MUL:
2119 case ISD::VECREDUCE_AND:
2120 case ISD::VECREDUCE_OR:
2121 case ISD::VECREDUCE_XOR:
2122 case ISD::VECREDUCE_SMAX:
2123 case ISD::VECREDUCE_SMIN:
2124 case ISD::VECREDUCE_UMAX:
2125 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
2126 case ISD::VP_REDUCE_ADD:
2127 case ISD::VP_REDUCE_MUL:
2128 case ISD::VP_REDUCE_AND:
2129 case ISD::VP_REDUCE_OR:
2130 case ISD::VP_REDUCE_XOR:
2131 case ISD::VP_REDUCE_SMAX:
2132 case ISD::VP_REDUCE_SMIN:
2133 case ISD::VP_REDUCE_UMAX:
2134 case ISD::VP_REDUCE_UMIN:
2135 Res = PromoteIntOp_VP_REDUCE(N, OpNo);
2136 break;
2137
2138 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
2139 case ISD::STACKMAP:
2140 Res = PromoteIntOp_STACKMAP(N, OpNo);
2141 break;
2142 case ISD::PATCHPOINT:
2143 Res = PromoteIntOp_PATCHPOINT(N, OpNo);
2144 break;
2145 case ISD::WRITE_REGISTER:
2146 Res = PromoteIntOp_WRITE_REGISTER(N, OpNo);
2147 break;
2148 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
2149 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
2150 Res = PromoteIntOp_VP_STRIDED(N, OpNo);
2151 break;
2152 case ISD::EXPERIMENTAL_VP_SPLICE:
2153 Res = PromoteIntOp_VP_SPLICE(N, OpNo);
2154 break;
2155 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
2156 Res = PromoteIntOp_VECTOR_HISTOGRAM(N, OpNo);
2157 break;
2158 case ISD::VECTOR_FIND_LAST_ACTIVE:
2159 Res = PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(N, OpNo);
2160 break;
2161 case ISD::GET_ACTIVE_LANE_MASK:
2162 Res = PromoteIntOp_GET_ACTIVE_LANE_MASK(N);
2163 break;
2164 case ISD::PARTIAL_REDUCE_UMLA:
2165 case ISD::PARTIAL_REDUCE_SMLA:
2166 case ISD::PARTIAL_REDUCE_SUMLA:
2167 Res = PromoteIntOp_PARTIAL_REDUCE_MLA(N);
2168 break;
2169 }
2170
2171 // If the result is null, the sub-method took care of registering results etc.
2172 if (!Res.getNode()) return false;
2173
2174 // If the result is N, the sub-method updated N in place. Tell the legalizer
2175 // core about this.
2176 if (Res.getNode() == N)
2177 return true;
2178
2179 const bool IsStrictFp = N->isStrictFPOpcode();
2180 assert(Res.getValueType() == N->getValueType(0) &&
2181 N->getNumValues() == (IsStrictFp ? 2 : 1) &&
2182 "Invalid operand expansion");
2183 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
2184 Res.dump());
2185
2186 ReplaceValueWith(From: SDValue(N, 0), To: Res);
2187 if (IsStrictFp)
2188 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res.getNode(), 1));
2189
2190 return false;
2191}
2192
2193// These operands can be either sign extended or zero extended as long as we
2194// treat them the same. If an extension is free, choose that. Otherwise, follow
2195// target preference.
2196void DAGTypeLegalizer::SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS) {
2197 SDValue OpL = GetPromotedInteger(Op: LHS);
2198 SDValue OpR = GetPromotedInteger(Op: RHS);
2199
2200 if (TLI.isSExtCheaperThanZExt(FromTy: LHS.getValueType(), ToTy: OpL.getValueType())) {
2201 // The target would prefer to promote the comparison operand with sign
2202 // extension. Honor that unless the promoted values are already zero
2203 // extended.
2204 unsigned OpLEffectiveBits =
2205 DAG.computeKnownBits(Op: OpL).countMaxActiveBits();
2206 unsigned OpREffectiveBits =
2207 DAG.computeKnownBits(Op: OpR).countMaxActiveBits();
2208 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2209 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2210 LHS = OpL;
2211 RHS = OpR;
2212 return;
2213 }
2214
2215 // The promoted values aren't zero extended, use a sext_inreg.
2216 LHS = SExtPromotedInteger(Op: LHS);
2217 RHS = SExtPromotedInteger(Op: RHS);
2218 return;
2219 }
2220
2221 // Prefer to promote the comparison operand with zero extension.
2222
2223 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
2224 // than the width of LHS/RHS, we can avoid/ inserting a zext_inreg operation
2225 // that we might not be able to remove.
2226 unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpL);
2227 unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpR);
2228 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2229 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2230 LHS = OpL;
2231 RHS = OpR;
2232 return;
2233 }
2234
2235 // Otherwise, use zext_inreg.
2236 LHS = ZExtPromotedInteger(Op: LHS);
2237 RHS = ZExtPromotedInteger(Op: RHS);
2238}
2239
2240/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
2241/// shared among BR_CC, SELECT_CC, and SETCC handlers.
2242void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
2243 ISD::CondCode CCCode) {
2244 // We have to insert explicit sign or zero extends. Note that we could
2245 // insert sign extends for ALL conditions. For those operations where either
2246 // zero or sign extension would be valid, we ask the target which extension
2247 // it would prefer.
2248
2249 // Signed comparisons always require sign extension.
2250 if (ISD::isSignedIntSetCC(Code: CCCode)) {
2251 LHS = SExtPromotedInteger(Op: LHS);
2252 RHS = SExtPromotedInteger(Op: RHS);
2253 return;
2254 }
2255
2256 assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
2257 "Unknown integer comparison!");
2258
2259 SExtOrZExtPromotedOperands(LHS, RHS);
2260}
2261
2262SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
2263 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2264 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2265}
2266
2267SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND_VECTOR_INREG(SDNode *N) {
2268 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2269 EVT ResVT = N->getValueType(ResNo: 0);
2270 EVT OpVT = Op.getValueType();
2271 EVT NewVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: OpVT.getScalarType(),
2272 NumElements: ResVT.getVectorNumElements());
2273 Op = DAG.getExtractSubvector(DL: SDLoc(Op), VT: NewVT, Vec: Op, Idx: 0);
2274 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: ResVT, Operand: Op);
2275}
2276
2277SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
2278 SDValue Op1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
2279 return DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(),
2280 Chain: N->getChain(), Ptr: Op1, Val: N->getBasePtr(), MMO: N->getMemOperand());
2281}
2282
2283SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
2284 EVT OutVT = N->getValueType(ResNo: 0);
2285 SDValue InOp = N->getOperand(Num: 0);
2286 EVT InVT = InOp.getValueType();
2287 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
2288 SDLoc dl(N);
2289
2290 switch (getTypeAction(VT: InVT)) {
2291 case TargetLowering::TypePromoteInteger: {
2292 // TODO: Handle big endian & vector input type.
2293 if (OutVT.isVector() && !InVT.isVector() &&
2294 DAG.getDataLayout().isLittleEndian()) {
2295 EVT EltVT = OutVT.getVectorElementType();
2296 TypeSize EltSize = EltVT.getSizeInBits();
2297 TypeSize NInSize = NInVT.getSizeInBits();
2298
2299 if (NInSize.hasKnownScalarFactor(RHS: EltSize)) {
2300 unsigned NumEltsWithPadding = NInSize.getKnownScalarFactor(RHS: EltSize);
2301 EVT WideVecVT =
2302 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
2303
2304 if (isTypeLegal(VT: WideVecVT)) {
2305 SDValue Promoted = GetPromotedInteger(Op: InOp);
2306 SDValue Cast = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: WideVecVT, Operand: Promoted);
2307 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Cast,
2308 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
2309 }
2310 }
2311 }
2312
2313 break;
2314 }
2315 default:
2316 break;
2317 }
2318
2319 // This should only occur in unusual situations like bitcasting to an
2320 // x86_fp80, so just turn it into a store+load
2321 return CreateStackStoreLoad(Op: InOp, DestVT: OutVT);
2322}
2323
2324SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
2325 assert(OpNo == 2 && "Don't know how to promote this operand!");
2326
2327 SDValue LHS = N->getOperand(Num: 2);
2328 SDValue RHS = N->getOperand(Num: 3);
2329 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get());
2330
2331 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
2332 // legal types.
2333 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2334 Op2: N->getOperand(Num: 1), Op3: LHS, Op4: RHS, Op5: N->getOperand(Num: 4)),
2335 0);
2336}
2337
2338SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
2339 assert(OpNo == 1 && "only know how to promote condition");
2340
2341 // Promote all the way up to the canonical SetCC type.
2342 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2343
2344 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
2345 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond,
2346 Op3: N->getOperand(Num: 2)), 0);
2347}
2348
2349SDValue DAGTypeLegalizer::PromoteIntOp_COND_LOOP(SDNode *N, unsigned OpNo) {
2350 assert(OpNo == 1 && "only know how to promote condition");
2351
2352 // Promote all the way up to the canonical SetCC type.
2353 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2354
2355 // The chain (Op#0) is always a legal type.
2356 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond), 0);
2357}
2358
2359SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
2360 // Since the result type is legal, the operands must promote to it.
2361 EVT OVT = N->getOperand(Num: 0).getValueType();
2362 SDValue Lo = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2363 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 1));
2364 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
2365 SDLoc dl(N);
2366
2367 Hi = DAG.getNode(
2368 Opcode: ISD::SHL, DL: dl, VT: N->getValueType(ResNo: 0), N1: Hi,
2369 N2: DAG.getShiftAmountConstant(Val: OVT.getSizeInBits(), VT: N->getValueType(ResNo: 0), DL: dl));
2370 return DAG.getNode(Opcode: ISD::OR, DL: dl, VT: N->getValueType(ResNo: 0), N1: Lo, N2: Hi);
2371}
2372
2373SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
2374 // The vector type is legal but the element type is not. This implies
2375 // that the vector is a power-of-two in length and that the element
2376 // type does not have a strange size (eg: it is not i1).
2377 EVT VecVT = N->getValueType(ResNo: 0);
2378 unsigned NumElts = VecVT.getVectorNumElements();
2379 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
2380 "Legal vector of one illegal element?");
2381
2382 // Promote the inserted value. The type does not need to match the
2383 // vector element type. Check that any extra bits introduced will be
2384 // truncated away.
2385 assert(N->getOperand(0).getValueSizeInBits() >=
2386 N->getValueType(0).getScalarSizeInBits() &&
2387 "Type of inserted value narrower than vector element type!");
2388
2389 SmallVector<SDValue, 16> NewOps;
2390 for (unsigned i = 0; i < NumElts; ++i)
2391 NewOps.push_back(Elt: GetPromotedInteger(Op: N->getOperand(Num: i)));
2392
2393 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2394}
2395
2396SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
2397 unsigned OpNo) {
2398 if (OpNo == 1) {
2399 // Promote the inserted value. This is valid because the type does not
2400 // have to match the vector element type.
2401
2402 // Check that any extra bits introduced will be truncated away.
2403 assert(N->getOperand(1).getValueSizeInBits() >=
2404 N->getValueType(0).getScalarSizeInBits() &&
2405 "Type of inserted value narrower than vector element type!");
2406 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2407 Op2: GetPromotedInteger(Op: N->getOperand(Num: 1)),
2408 Op3: N->getOperand(Num: 2)),
2409 0);
2410 }
2411
2412 assert(OpNo == 2 && "Different operand and result vector types?");
2413
2414 // Promote the index.
2415 SDValue Idx = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 2), DL: SDLoc(N),
2416 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
2417 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2418 Op2: N->getOperand(Num: 1), Op3: Idx), 0);
2419}
2420
2421SDValue DAGTypeLegalizer::PromoteIntOp_ScalarOp(SDNode *N) {
2422 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2423
2424 // Integer SPLAT_VECTOR/SCALAR_TO_VECTOR operands are implicitly truncated,
2425 // so just promote the operand in place.
2426 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2427}
2428
2429SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
2430 assert(OpNo == 0 && "Only know how to promote the condition!");
2431 SDValue Cond = N->getOperand(Num: 0);
2432 EVT OpTy = N->getOperand(Num: 1).getValueType();
2433
2434 if (N->getOpcode() == ISD::VSELECT)
2435 if (SDValue Res = WidenVSELECTMask(N))
2436 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
2437 N1: Res, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2438
2439 // Promote all the way up to the canonical SetCC type.
2440 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
2441 Cond = PromoteTargetBoolean(Bool: Cond, ValVT: OpVT);
2442
2443 return SDValue(DAG.UpdateNodeOperands(N, Op1: Cond, Op2: N->getOperand(Num: 1),
2444 Op3: N->getOperand(Num: 2)), 0);
2445}
2446
2447SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
2448 assert(OpNo == 0 && "Don't know how to promote this operand!");
2449
2450 SDValue LHS = N->getOperand(Num: 0);
2451 SDValue RHS = N->getOperand(Num: 1);
2452 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get());
2453
2454 // The CC (#4) and the possible return values (#2 and #3) have legal types.
2455 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2456 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)), 0);
2457}
2458
2459SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
2460 assert(OpNo == 0 && "Don't know how to promote this operand!");
2461
2462 SDValue LHS = N->getOperand(Num: 0);
2463 SDValue RHS = N->getOperand(Num: 1);
2464 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get());
2465
2466 // The CC (#2) is always legal.
2467 if (N->getOpcode() == ISD::SETCC)
2468 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2)), 0);
2469
2470 assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
2471
2472 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2473 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)),
2474 0);
2475}
2476
2477SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
2478 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2479 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2480}
2481
2482SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
2483 SDValue LHS = N->getOperand(Num: 0);
2484 SDValue RHS = N->getOperand(Num: 1);
2485
2486 if (N->getOpcode() == ISD::SCMP) {
2487 LHS = SExtPromotedInteger(Op: LHS);
2488 RHS = SExtPromotedInteger(Op: RHS);
2489 } else {
2490 SExtOrZExtPromotedOperands(LHS, RHS);
2491 }
2492
2493 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS), 0);
2494}
2495
2496SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
2497 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
2498 Op3: ZExtPromotedInteger(Op: N->getOperand(Num: 2))), 0);
2499}
2500
2501SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
2502 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2503 SDLoc dl(N);
2504 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Op);
2505 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Op.getValueType(),
2506 N1: Op, N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
2507}
2508
2509SDValue DAGTypeLegalizer::PromoteIntOp_VP_SIGN_EXTEND(SDNode *N) {
2510 SDLoc dl(N);
2511 EVT VT = N->getValueType(ResNo: 0);
2512 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2513 // FIXME: There is no VP_ANY_EXTEND yet.
2514 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2515 N3: N->getOperand(Num: 2));
2516 unsigned Diff =
2517 VT.getScalarSizeInBits() - N->getOperand(Num: 0).getScalarValueSizeInBits();
2518 SDValue ShAmt = DAG.getShiftAmountConstant(Val: Diff, VT, DL: dl);
2519 // FIXME: There is no VP_SIGN_EXTEND_INREG so use a pair of shifts.
2520 SDValue Shl = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT, N1: Op, N2: ShAmt, N3: N->getOperand(Num: 1),
2521 N4: N->getOperand(Num: 2));
2522 return DAG.getNode(Opcode: ISD::VP_SRA, DL: dl, VT, N1: Shl, N2: ShAmt, N3: N->getOperand(Num: 1),
2523 N4: N->getOperand(Num: 2));
2524}
2525
2526SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
2527 if (N->getOpcode() == ISD::VP_SINT_TO_FP)
2528 return SDValue(DAG.UpdateNodeOperands(N,
2529 Op1: SExtPromotedInteger(Op: N->getOperand(Num: 0)),
2530 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2531 0);
2532 return SDValue(DAG.UpdateNodeOperands(N,
2533 Op: SExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2534}
2535
2536SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
2537 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2538 Op2: SExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2539}
2540
2541SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
2542 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2543 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
2544 SDLoc dl(N);
2545
2546 SDValue Val = GetPromotedInteger(Op: N->getValue()); // Get promoted value.
2547
2548 // Truncate the value and store the result.
2549 return DAG.getTruncStore(Chain: Ch, dl, Val, Ptr,
2550 SVT: N->getMemoryVT(), MMO: N->getMemOperand());
2551}
2552
2553SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
2554 unsigned OpNo) {
2555
2556 assert(OpNo == 1 && "Unexpected operand for promotion");
2557 assert(!N->isIndexed() && "expecting unindexed vp_store!");
2558
2559 SDValue DataOp = GetPromotedInteger(Op: N->getValue());
2560 return DAG.getTruncStoreVP(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Ptr: N->getBasePtr(),
2561 Mask: N->getMask(), EVL: N->getVectorLength(),
2562 SVT: N->getMemoryVT(), MMO: N->getMemOperand(),
2563 IsCompressing: N->isCompressingStore());
2564}
2565
2566SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
2567 unsigned OpNo) {
2568 SDValue DataOp = N->getValue();
2569 SDValue Mask = N->getMask();
2570
2571 if (OpNo == 4) {
2572 // The Mask. Update in place.
2573 EVT DataVT = DataOp.getValueType();
2574 Mask = PromoteTargetBoolean(Bool: Mask, ValVT: DataVT);
2575 SmallVector<SDValue, 4> NewOps(N->ops());
2576 NewOps[4] = Mask;
2577 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2578 }
2579
2580 assert(OpNo == 1 && "Unexpected operand for promotion");
2581 DataOp = GetPromotedInteger(Op: DataOp);
2582
2583 return DAG.getMaskedStore(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Base: N->getBasePtr(),
2584 Offset: N->getOffset(), Mask, MemVT: N->getMemoryVT(),
2585 MMO: N->getMemOperand(), AM: N->getAddressingMode(),
2586 /*IsTruncating*/ true, IsCompressing: N->isCompressingStore());
2587}
2588
2589SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
2590 unsigned OpNo) {
2591 assert(OpNo == 3 && "Only know how to promote the mask!");
2592 EVT DataVT = N->getValueType(ResNo: 0);
2593 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2594 SmallVector<SDValue, 4> NewOps(N->ops());
2595 NewOps[OpNo] = Mask;
2596 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2597 if (Res == N)
2598 return SDValue(Res, 0);
2599
2600 // Update triggered CSE, do our own replacement since caller can't.
2601 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2602 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2603 return SDValue();
2604}
2605
2606SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
2607 unsigned OpNo) {
2608 SmallVector<SDValue, 5> NewOps(N->ops());
2609
2610 if (OpNo == 2) {
2611 // The Mask
2612 EVT DataVT = N->getValueType(ResNo: 0);
2613 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2614 } else if (OpNo == 4) {
2615 // The Index
2616 if (N->isIndexSigned())
2617 // Need to sign extend the index since the bits will likely be used.
2618 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2619 else
2620 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2621 } else
2622 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2623
2624 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2625 if (Res == N)
2626 return SDValue(Res, 0);
2627
2628 // Update triggered CSE, do our own replacement since caller can't.
2629 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2630 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2631 return SDValue();
2632}
2633
2634SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2635 unsigned OpNo) {
2636 bool TruncateStore = N->isTruncatingStore();
2637 SmallVector<SDValue, 5> NewOps(N->ops());
2638
2639 if (OpNo == 2) {
2640 // The Mask
2641 EVT DataVT = N->getValue().getValueType();
2642 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2643 } else if (OpNo == 4) {
2644 // The Index
2645 if (N->isIndexSigned())
2646 // Need to sign extend the index since the bits will likely be used.
2647 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2648 else
2649 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2650 } else {
2651 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2652 TruncateStore = true;
2653 }
2654
2655 return DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: N->getMemoryVT(),
2656 dl: SDLoc(N), Ops: NewOps, MMO: N->getMemOperand(),
2657 IndexType: N->getIndexType(), IsTruncating: TruncateStore);
2658}
2659
2660SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_COMPRESS(SDNode *N,
2661 unsigned OpNo) {
2662 assert(OpNo == 1 && "Can only promote VECTOR_COMPRESS mask.");
2663 SDValue Vec = N->getOperand(Num: 0);
2664 EVT VT = Vec.getValueType();
2665 SDValue Passthru = N->getOperand(Num: 2);
2666 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: VT);
2667 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT, N1: Vec, N2: Mask, N3: Passthru);
2668}
2669
2670SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2671 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2672 if (N->getOpcode() == ISD::VP_TRUNCATE)
2673 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Op,
2674 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2675 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2676}
2677
2678SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2679 if (N->getOpcode() == ISD::VP_UINT_TO_FP)
2680 return SDValue(DAG.UpdateNodeOperands(N,
2681 Op1: ZExtPromotedInteger(Op: N->getOperand(Num: 0)),
2682 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2683 0);
2684 return SDValue(DAG.UpdateNodeOperands(N,
2685 Op: ZExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2686}
2687
2688SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2689 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2690 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2691}
2692
2693SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2694 SDLoc dl(N);
2695 SDValue Src = N->getOperand(Num: 0);
2696 SDValue Op = GetPromotedInteger(Op: Src);
2697 EVT VT = N->getValueType(ResNo: 0);
2698
2699 // If this zext has the nneg flag and the target prefers sext, see if the
2700 // promoted input is already sign extended.
2701 // TODO: Should we have some way to set nneg on ISD::AND instead?
2702 if (N->getFlags().hasNonNeg() && Op.getValueType() == VT &&
2703 TLI.isSExtCheaperThanZExt(FromTy: Src.getValueType(), ToTy: VT)) {
2704 unsigned OpEffectiveBits = DAG.ComputeMaxSignificantBits(Op);
2705 if (OpEffectiveBits <= Src.getScalarValueSizeInBits())
2706 return Op;
2707 }
2708
2709 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Op);
2710 return DAG.getZeroExtendInReg(Op, DL: dl, VT: Src.getValueType());
2711}
2712
2713SDValue DAGTypeLegalizer::PromoteIntOp_VP_ZERO_EXTEND(SDNode *N) {
2714 SDLoc dl(N);
2715 EVT VT = N->getValueType(ResNo: 0);
2716 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2717 // FIXME: There is no VP_ANY_EXTEND yet.
2718 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2719 N3: N->getOperand(Num: 2));
2720 return DAG.getVPZeroExtendInReg(Op, Mask: N->getOperand(Num: 1), EVL: N->getOperand(Num: 2), DL: dl,
2721 VT: N->getOperand(Num: 0).getValueType());
2722}
2723
2724SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2725 SDValue Op2 = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2726 return SDValue(
2727 DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1), Op3: Op2), 0);
2728}
2729
2730SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2731 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2732 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2733 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2734}
2735
2736SDValue DAGTypeLegalizer::PromoteIntOp_ExpOp(SDNode *N) {
2737 bool IsStrict = N->isStrictFPOpcode();
2738 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
2739
2740 bool IsPowI =
2741 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI;
2742 unsigned OpOffset = IsStrict ? 1 : 0;
2743
2744 // The integer operand is the last operand in FPOWI (or FLDEXP) (so the result
2745 // and floating point operand is already type legalized).
2746 RTLIB::Libcall LC = IsPowI ? RTLIB::getPOWI(RetVT: N->getValueType(ResNo: 0))
2747 : RTLIB::getLDEXP(RetVT: N->getValueType(ResNo: 0));
2748
2749 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
2750 if (LCImpl == RTLIB::Unsupported) {
2751 // Scalarize vector FPOWI instead of promoting the type. This allows the
2752 // scalar FPOWIs to be visited and converted to libcalls before promoting
2753 // the type.
2754 // FIXME: This should be done in LegalizeVectorOps/LegalizeDAG, but call
2755 // lowering needs the unpromoted EVT.
2756 if (IsPowI && N->getValueType(ResNo: 0).isVector())
2757 return DAG.UnrollVectorOp(N);
2758 SmallVector<SDValue, 3> NewOps(N->ops());
2759 NewOps[1 + OpOffset] = SExtPromotedInteger(Op: N->getOperand(Num: 1 + OpOffset));
2760 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2761 }
2762
2763 // We can't just promote the exponent type in FPOWI, since we want to lower
2764 // the node to a libcall and we if we promote to a type larger than
2765 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2766 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2767 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2768
2769 // The exponent should fit in a sizeof(int) type for the libcall to be valid.
2770 assert(DAG.getLibInfo().getIntSize() ==
2771 N->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&
2772 "POWI exponent should match with sizeof(int) when doing the libcall.");
2773 TargetLowering::MakeLibCallOptions CallOptions;
2774 CallOptions.setIsSigned(true);
2775 SDValue Ops[2] = {N->getOperand(Num: 0 + OpOffset), N->getOperand(Num: 1 + OpOffset)};
2776 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2777 DAG, LibcallImpl: LCImpl, RetVT: N->getValueType(ResNo: 0), Ops, CallOptions, dl: SDLoc(N), Chain);
2778 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
2779 if (IsStrict)
2780 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
2781 return SDValue();
2782}
2783
2784static unsigned getExtendForIntVecReduction(SDNode *N) {
2785 switch (N->getOpcode()) {
2786 default:
2787 llvm_unreachable("Expected integer vector reduction");
2788 case ISD::VECREDUCE_ADD:
2789 case ISD::VECREDUCE_MUL:
2790 case ISD::VECREDUCE_AND:
2791 case ISD::VECREDUCE_OR:
2792 case ISD::VECREDUCE_XOR:
2793 case ISD::VP_REDUCE_ADD:
2794 case ISD::VP_REDUCE_MUL:
2795 case ISD::VP_REDUCE_AND:
2796 case ISD::VP_REDUCE_OR:
2797 case ISD::VP_REDUCE_XOR:
2798 return ISD::ANY_EXTEND;
2799 case ISD::VECREDUCE_SMAX:
2800 case ISD::VECREDUCE_SMIN:
2801 case ISD::VP_REDUCE_SMAX:
2802 case ISD::VP_REDUCE_SMIN:
2803 return ISD::SIGN_EXTEND;
2804 case ISD::VECREDUCE_UMAX:
2805 case ISD::VECREDUCE_UMIN:
2806 case ISD::VP_REDUCE_UMAX:
2807 case ISD::VP_REDUCE_UMIN:
2808 return ISD::ZERO_EXTEND;
2809 }
2810}
2811
2812SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2813 switch (getExtendForIntVecReduction(N)) {
2814 default:
2815 llvm_unreachable("Impossible extension kind for integer reduction");
2816 case ISD::ANY_EXTEND:
2817 return GetPromotedInteger(Op: V);
2818 case ISD::SIGN_EXTEND:
2819 return SExtPromotedInteger(Op: V);
2820 case ISD::ZERO_EXTEND:
2821 return ZExtPromotedInteger(Op: V);
2822 }
2823}
2824
2825SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2826 SDLoc dl(N);
2827 SDValue Op = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
2828
2829 EVT OrigEltVT = N->getOperand(Num: 0).getValueType().getVectorElementType();
2830 EVT InVT = Op.getValueType();
2831 EVT EltVT = InVT.getVectorElementType();
2832 EVT ResVT = N->getValueType(ResNo: 0);
2833 unsigned Opcode = N->getOpcode();
2834
2835 // An i1 vecreduce_xor is equivalent to vecreduce_add, use that instead if
2836 // vecreduce_xor is not legal
2837 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 &&
2838 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_XOR, VT: InVT) &&
2839 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_ADD, VT: InVT))
2840 Opcode = ISD::VECREDUCE_ADD;
2841
2842 // An i1 vecreduce_or is equivalent to vecreduce_umax, use that instead if
2843 // vecreduce_or is not legal
2844 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 &&
2845 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_OR, VT: InVT) &&
2846 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMAX, VT: InVT)) {
2847 Opcode = ISD::VECREDUCE_UMAX;
2848 // Can't use promoteTargetBoolean here because we still need
2849 // to either sign_ext or zero_ext in the undefined case.
2850 switch (TLI.getBooleanContents(Type: InVT)) {
2851 case TargetLoweringBase::UndefinedBooleanContent:
2852 case TargetLoweringBase::ZeroOrOneBooleanContent:
2853 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2854 break;
2855 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2856 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2857 break;
2858 }
2859 }
2860
2861 // An i1 vecreduce_and is equivalent to vecreduce_umin, use that instead if
2862 // vecreduce_and is not legal
2863 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 &&
2864 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_AND, VT: InVT) &&
2865 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMIN, VT: InVT)) {
2866 Opcode = ISD::VECREDUCE_UMIN;
2867 // Can't use promoteTargetBoolean here because we still need
2868 // to either sign_ext or zero_ext in the undefined case.
2869 switch (TLI.getBooleanContents(Type: InVT)) {
2870 case TargetLoweringBase::UndefinedBooleanContent:
2871 case TargetLoweringBase::ZeroOrOneBooleanContent:
2872 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2873 break;
2874 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2875 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2876 break;
2877 }
2878 }
2879
2880 if (ResVT.bitsGE(VT: EltVT))
2881 return DAG.getNode(Opcode, DL: SDLoc(N), VT: ResVT, Operand: Op);
2882
2883 // Result size must be >= element size. If this is not the case after
2884 // promotion, also promote the result type and then truncate.
2885 SDValue Reduce = DAG.getNode(Opcode, DL: dl, VT: EltVT, Operand: Op);
2886 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: ResVT, Operand: Reduce);
2887}
2888
2889SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
2890 SDLoc DL(N);
2891 SDValue Op = N->getOperand(Num: OpNo);
2892 SmallVector<SDValue, 4> NewOps(N->ops());
2893
2894 if (OpNo == 2) { // Mask
2895 // Update in place.
2896 NewOps[2] = PromoteTargetBoolean(Bool: Op, ValVT: N->getOperand(Num: 1).getValueType());
2897 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2898 }
2899
2900 assert(OpNo == 1 && "Unexpected operand for promotion");
2901
2902 Op = PromoteIntOpVectorReduction(N, V: Op);
2903
2904 NewOps[OpNo] = Op;
2905
2906 EVT VT = N->getValueType(ResNo: 0);
2907 EVT EltVT = Op.getValueType().getScalarType();
2908
2909 if (VT.bitsGE(VT: EltVT))
2910 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT, Ops: NewOps);
2911
2912 // Result size must be >= element/start-value size. If this is not the case
2913 // after promotion, also promote both the start value and result type and
2914 // then truncate.
2915 NewOps[0] =
2916 DAG.getNode(Opcode: getExtendForIntVecReduction(N), DL, VT: EltVT, Operand: N->getOperand(Num: 0));
2917 SDValue Reduce = DAG.getNode(Opcode: N->getOpcode(), DL, VT: EltVT, Ops: NewOps);
2918 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT, Operand: Reduce);
2919}
2920
2921SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2922 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2923 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Op), 0);
2924}
2925
2926SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
2927 assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
2928 SmallVector<SDValue> NewOps(N->ops());
2929 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
2930 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2931}
2932
2933SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
2934 assert(OpNo >= 7);
2935 SmallVector<SDValue> NewOps(N->ops());
2936 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
2937 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2938}
2939
2940SDValue DAGTypeLegalizer::PromoteIntOp_WRITE_REGISTER(SDNode *N,
2941 unsigned OpNo) {
2942 const Function &Fn = DAG.getMachineFunction().getFunction();
2943 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
2944 "cannot use llvm.write_register with illegal type", Fn,
2945 N->getDebugLoc()));
2946 return N->getOperand(Num: 0);
2947}
2948
2949SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
2950 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
2951 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
2952
2953 SmallVector<SDValue, 8> NewOps(N->ops());
2954 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2955
2956 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2957}
2958
2959SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
2960 SmallVector<SDValue, 6> NewOps(N->ops());
2961
2962 if (OpNo == 2) { // Offset operand
2963 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2964 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2965 }
2966
2967 assert((OpNo == 4 || OpNo == 5) && "Unexpected operand for promotion");
2968
2969 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2970 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2971}
2972
2973SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_HISTOGRAM(SDNode *N,
2974 unsigned OpNo) {
2975 assert(OpNo == 1 && "Unexpected operand for promotion");
2976 SmallVector<SDValue, 7> NewOps(N->ops());
2977 NewOps[1] = GetPromotedInteger(Op: N->getOperand(Num: 1));
2978 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2979}
2980
2981SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(SDNode *N,
2982 unsigned OpNo) {
2983 SmallVector<SDValue, 1> NewOps(N->ops());
2984 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2985 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2986}
2987
2988SDValue DAGTypeLegalizer::PromoteIntOp_GET_ACTIVE_LANE_MASK(SDNode *N) {
2989 SmallVector<SDValue, 1> NewOps(N->ops());
2990 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2991 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2992 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2993}
2994
2995SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
2996 SmallVector<SDValue, 1> NewOps(N->ops());
2997 switch (N->getOpcode()) {
2998 case ISD::PARTIAL_REDUCE_SMLA:
2999 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3000 NewOps[2] = SExtPromotedInteger(Op: N->getOperand(Num: 2));
3001 break;
3002 case ISD::PARTIAL_REDUCE_UMLA:
3003 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3004 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3005 break;
3006 case ISD::PARTIAL_REDUCE_SUMLA:
3007 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3008 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3009 break;
3010 default:
3011 llvm_unreachable("unexpected opcode");
3012 }
3013 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3014}
3015
3016//===----------------------------------------------------------------------===//
3017// Integer Result Expansion
3018//===----------------------------------------------------------------------===//
3019
3020/// ExpandIntegerResult - This method is called when the specified result of the
3021/// specified node is found to need expansion. At this point, the node may also
3022/// have invalid operands or may have other results that need promotion, we just
3023/// know that (at least) one result needs expansion.
3024void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
3025 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG));
3026 SDValue Lo, Hi;
3027 Lo = Hi = SDValue();
3028
3029 // See if the target wants to custom expand this node.
3030 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true))
3031 return;
3032
3033 switch (N->getOpcode()) {
3034 default:
3035#ifndef NDEBUG
3036 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
3037 N->dump(&DAG); dbgs() << "\n";
3038#endif
3039 report_fatal_error(reason: "Do not know how to expand the result of this "
3040 "operator!");
3041
3042 case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
3043 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
3044 case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
3045 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
3046 case ISD::POISON:
3047 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
3048 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
3049 case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;
3050
3051 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
3052 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
3053 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
3054 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
3055 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
3056
3057 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
3058 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
3059 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
3060 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
3061 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
3062 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
3063 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
3064 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
3065 case ISD::ABDS:
3066 case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
3067 case ISD::CTLZ_ZERO_UNDEF:
3068 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
3069 case ISD::CTLS: ExpandIntRes_CTLS(N, Lo, Hi); break;
3070 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
3071 case ISD::CTTZ_ZERO_UNDEF:
3072 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
3073 case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
3074 case ISD::STRICT_FP_TO_SINT:
3075 case ISD::FP_TO_SINT:
3076 case ISD::STRICT_FP_TO_UINT:
3077 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_XINT(N, Lo, Hi); break;
3078 case ISD::FP_TO_SINT_SAT:
3079 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
3080 case ISD::STRICT_LROUND:
3081 case ISD::STRICT_LRINT:
3082 case ISD::LROUND:
3083 case ISD::LRINT:
3084 case ISD::STRICT_LLROUND:
3085 case ISD::STRICT_LLRINT:
3086 case ISD::LLROUND:
3087 case ISD::LLRINT: ExpandIntRes_XROUND_XRINT(N, Lo, Hi); break;
3088 case ISD::LOAD: ExpandIntRes_LOAD(N: cast<LoadSDNode>(Val: N), Lo, Hi); break;
3089 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
3090 case ISD::READCYCLECOUNTER:
3091 case ISD::READSTEADYCOUNTER: ExpandIntRes_READCOUNTER(N, Lo, Hi); break;
3092 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
3093 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
3094 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
3095 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
3096 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
3097 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
3098 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
3099 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
3100 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
3101
3102 case ISD::ATOMIC_LOAD_ADD:
3103 case ISD::ATOMIC_LOAD_SUB:
3104 case ISD::ATOMIC_LOAD_AND:
3105 case ISD::ATOMIC_LOAD_CLR:
3106 case ISD::ATOMIC_LOAD_OR:
3107 case ISD::ATOMIC_LOAD_XOR:
3108 case ISD::ATOMIC_LOAD_NAND:
3109 case ISD::ATOMIC_LOAD_MIN:
3110 case ISD::ATOMIC_LOAD_MAX:
3111 case ISD::ATOMIC_LOAD_UMIN:
3112 case ISD::ATOMIC_LOAD_UMAX:
3113 case ISD::ATOMIC_SWAP:
3114 case ISD::ATOMIC_CMP_SWAP: {
3115 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node: N);
3116 SplitInteger(Op: Tmp.first, Lo, Hi);
3117 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
3118 break;
3119 }
3120 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3121 AtomicSDNode *AN = cast<AtomicSDNode>(Val: N);
3122 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: MVT::Other);
3123 SDValue Tmp = DAG.getAtomicCmpSwap(
3124 Opcode: ISD::ATOMIC_CMP_SWAP, dl: SDLoc(N), MemVT: AN->getMemoryVT(), VTs,
3125 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 1), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
3126 MMO: AN->getMemOperand());
3127
3128 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
3129 // success simply by comparing the loaded value against the ingoing
3130 // comparison.
3131 SDValue Success = DAG.getSetCC(DL: SDLoc(N), VT: N->getValueType(ResNo: 1), LHS: Tmp,
3132 RHS: N->getOperand(Num: 2), Cond: ISD::SETEQ);
3133
3134 SplitInteger(Op: Tmp, Lo, Hi);
3135 ReplaceValueWith(From: SDValue(N, 1), To: Success);
3136 ReplaceValueWith(From: SDValue(N, 2), To: Tmp.getValue(R: 1));
3137 break;
3138 }
3139
3140 case ISD::AND:
3141 case ISD::OR:
3142 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
3143
3144 case ISD::UMAX:
3145 case ISD::SMAX:
3146 case ISD::UMIN:
3147 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
3148
3149 case ISD::SCMP:
3150 case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
3151
3152 case ISD::ADD:
3153 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
3154
3155 case ISD::ADDC:
3156 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
3157
3158 case ISD::ADDE:
3159 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
3160
3161 case ISD::UADDO_CARRY:
3162 case ISD::USUBO_CARRY: ExpandIntRes_UADDSUBO_CARRY(N, Lo, Hi); break;
3163
3164 case ISD::SADDO_CARRY:
3165 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
3166
3167 case ISD::SHL:
3168 case ISD::SRA:
3169 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
3170
3171 case ISD::SADDO:
3172 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
3173 case ISD::UADDO:
3174 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
3175 case ISD::UMULO:
3176 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3177
3178 case ISD::SADDSAT:
3179 case ISD::UADDSAT:
3180 case ISD::SSUBSAT:
3181 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
3182
3183 case ISD::SSHLSAT:
3184 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
3185
3186 case ISD::AVGCEILS:
3187 case ISD::AVGCEILU:
3188 case ISD::AVGFLOORS:
3189 case ISD::AVGFLOORU: ExpandIntRes_AVG(N, Lo, Hi); break;
3190
3191 case ISD::SMULFIX:
3192 case ISD::SMULFIXSAT:
3193 case ISD::UMULFIX:
3194 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
3195
3196 case ISD::SDIVFIX:
3197 case ISD::SDIVFIXSAT:
3198 case ISD::UDIVFIX:
3199 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
3200
3201 case ISD::VECREDUCE_ADD:
3202 case ISD::VECREDUCE_MUL:
3203 case ISD::VECREDUCE_AND:
3204 case ISD::VECREDUCE_OR:
3205 case ISD::VECREDUCE_XOR:
3206 case ISD::VECREDUCE_SMAX:
3207 case ISD::VECREDUCE_SMIN:
3208 case ISD::VECREDUCE_UMAX:
3209 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
3210
3211 case ISD::ROTL:
3212 case ISD::ROTR:
3213 ExpandIntRes_Rotate(N, Lo, Hi);
3214 break;
3215
3216 case ISD::FSHL:
3217 case ISD::FSHR:
3218 ExpandIntRes_FunnelShift(N, Lo, Hi);
3219 break;
3220
3221 case ISD::CLMUL:
3222 case ISD::CLMULR:
3223 case ISD::CLMULH:
3224 ExpandIntRes_CLMUL(N, Lo, Hi);
3225 break;
3226
3227 case ISD::VSCALE:
3228 ExpandIntRes_VSCALE(N, Lo, Hi);
3229 break;
3230
3231 case ISD::READ_REGISTER:
3232 ExpandIntRes_READ_REGISTER(N, Lo, Hi);
3233 break;
3234 }
3235
3236 // If Lo/Hi is null, the sub-method took care of registering results etc.
3237 if (Lo.getNode())
3238 SetExpandedInteger(Op: SDValue(N, ResNo), Lo, Hi);
3239}
3240
3241/// Lower an atomic node to the appropriate builtin call.
3242std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
3243 unsigned Opc = Node->getOpcode();
3244 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
3245 AtomicOrdering order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
3246 // Lower to outline atomic libcall if outline atomics enabled,
3247 // or to sync libcall otherwise
3248 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order: order, VT);
3249 EVT RetVT = Node->getValueType(ResNo: 0);
3250 TargetLowering::MakeLibCallOptions CallOptions;
3251 SmallVector<SDValue, 4> Ops;
3252
3253 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3254 if (LCImpl != RTLIB::Unsupported) {
3255 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
3256 Ops.push_back(Elt: Node->getOperand(Num: 1));
3257 } else {
3258 LC = RTLIB::getSYNC(Opc, VT);
3259 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3260 "Unexpected atomic op or value type!");
3261 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
3262 LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3263 }
3264 return TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT, Ops, CallOptions, dl: SDLoc(Node),
3265 Chain: Node->getOperand(Num: 0));
3266}
3267
3268/// N is a shift by a value that needs to be expanded,
3269/// and the shift amount is a constant 'Amt'. Expand the operation.
3270void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
3271 SDValue &Lo, SDValue &Hi) {
3272 SDLoc DL(N);
3273 // Expand the incoming operand to be shifted, so that we have its parts
3274 SDValue InL, InH;
3275 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3276
3277 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
3278 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
3279 if (!Amt) {
3280 Lo = InL;
3281 Hi = InH;
3282 return;
3283 }
3284
3285 EVT NVT = InL.getValueType();
3286 unsigned VTBits = N->getValueType(ResNo: 0).getSizeInBits();
3287 unsigned NVTBits = NVT.getSizeInBits();
3288
3289 if (N->getOpcode() == ISD::SHL) {
3290 if (Amt.uge(RHS: VTBits)) {
3291 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3292 } else if (Amt.ugt(RHS: NVTBits)) {
3293 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3294 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3295 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3296 } else if (Amt == NVTBits) {
3297 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3298 Hi = InL;
3299 } else {
3300 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3301 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3302 Hi = DAG.getNode(
3303 Opcode: ISD::OR, DL, VT: NVT,
3304 N1: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3305 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3306 N2: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3307 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3308 }
3309 return;
3310 }
3311
3312 if (N->getOpcode() == ISD::SRL) {
3313 if (Amt.uge(RHS: VTBits)) {
3314 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3315 } else if (Amt.ugt(RHS: NVTBits)) {
3316 Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3317 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3318 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3319 } else if (Amt == NVTBits) {
3320 Lo = InH;
3321 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3322 } else {
3323 Lo = DAG.getNode(
3324 Opcode: ISD::OR, DL, VT: NVT,
3325 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3326 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3327 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3328 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3329 Hi = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3330 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3331 }
3332 return;
3333 }
3334
3335 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3336 if (Amt.uge(RHS: VTBits)) {
3337 Hi = Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3338 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3339 } else if (Amt.ugt(RHS: NVTBits)) {
3340 Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3341 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3342 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3343 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3344 } else if (Amt == NVTBits) {
3345 Lo = InH;
3346 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3347 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3348 } else {
3349 Lo = DAG.getNode(
3350 Opcode: ISD::OR, DL, VT: NVT,
3351 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3352 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3353 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3354 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3355 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3356 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3357 }
3358}
3359
3360/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
3361/// this shift based on knowledge of the high bit of the shift amount. If we
3362/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
3363/// shift amount.
3364bool DAGTypeLegalizer::
3365ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3366 unsigned Opc = N->getOpcode();
3367 SDValue In = N->getOperand(Num: 0);
3368 SDValue Amt = N->getOperand(Num: 1);
3369 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3370 EVT ShTy = Amt.getValueType();
3371 unsigned ShBits = ShTy.getScalarSizeInBits();
3372 unsigned NVTBits = NVT.getScalarSizeInBits();
3373 assert(isPowerOf2_32(NVTBits) &&
3374 "Expanded integer type size not a power of two!");
3375 SDLoc dl(N);
3376
3377 APInt HighBitMask = APInt::getHighBitsSet(numBits: ShBits, hiBitsSet: ShBits - Log2_32(Value: NVTBits));
3378 KnownBits Known = DAG.computeKnownBits(Op: Amt);
3379
3380 // If we don't know anything about the high bits, exit.
3381 if (((Known.Zero | Known.One) & HighBitMask) == 0)
3382 return false;
3383
3384 // Get the incoming operand to be shifted.
3385 SDValue InL, InH;
3386 GetExpandedInteger(Op: In, Lo&: InL, Hi&: InH);
3387
3388 // If we know that any of the high bits of the shift amount are one, then we
3389 // can do this as a couple of simple shifts.
3390 if (Known.One.intersects(RHS: HighBitMask)) {
3391 // Mask out the high bit, which we know is set.
3392 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShTy, N1: Amt,
3393 N2: DAG.getConstant(Val: ~HighBitMask, DL: dl, VT: ShTy));
3394
3395 switch (Opc) {
3396 default: llvm_unreachable("Unknown shift");
3397 case ISD::SHL:
3398 Lo = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Low part is zero.
3399 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt); // High part from Lo part.
3400 return true;
3401 case ISD::SRL:
3402 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3403 Lo = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3404 return true;
3405 case ISD::SRA:
3406 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign extend high part.
3407 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3408 Lo = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3409 return true;
3410 }
3411 }
3412
3413 // If we know that all of the high bits of the shift amount are zero, then we
3414 // can do this as a couple of simple shifts.
3415 if (HighBitMask.isSubsetOf(RHS: Known.Zero)) {
3416 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
3417 // shift if x is zero. We can use XOR here because x is known to be smaller
3418 // than 32.
3419 SDValue Amt2 = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: ShTy, N1: Amt,
3420 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3421
3422 unsigned Op1, Op2;
3423 switch (Opc) {
3424 default: llvm_unreachable("Unknown shift");
3425 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
3426 case ISD::SRL:
3427 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
3428 }
3429
3430 // When shifting right the arithmetic for Lo and Hi is swapped.
3431 if (Opc != ISD::SHL)
3432 std::swap(a&: InL, b&: InH);
3433
3434 // Use a little trick to get the bits that move from Lo to Hi. First
3435 // shift by one bit.
3436 SDValue Sh1 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: InL, N2: DAG.getConstant(Val: 1, DL: dl, VT: ShTy));
3437 // Then compute the remaining shift with amount-1.
3438 SDValue Sh2 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: Sh1, N2: Amt2);
3439
3440 Lo = DAG.getNode(Opcode: Opc, DL: dl, VT: NVT, N1: InL, N2: Amt);
3441 Hi = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: Op1, DL: dl, VT: NVT, N1: InH, N2: Amt),N2: Sh2);
3442
3443 if (Opc != ISD::SHL)
3444 std::swap(a&: Hi, b&: Lo);
3445 return true;
3446 }
3447
3448 return false;
3449}
3450
3451/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
3452/// of any size.
3453bool DAGTypeLegalizer::
3454ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3455 SDValue Amt = N->getOperand(Num: 1);
3456 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3457 EVT ShTy = Amt.getValueType();
3458 unsigned NVTBits = NVT.getSizeInBits();
3459 assert(isPowerOf2_32(NVTBits) &&
3460 "Expanded integer type size not a power of two!");
3461 SDLoc dl(N);
3462
3463 // Get the incoming operand to be shifted.
3464 SDValue InL, InH;
3465 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3466
3467 SDValue NVBitsNode = DAG.getConstant(Val: NVTBits, DL: dl, VT: ShTy);
3468 SDValue AmtExcess = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: Amt, N2: NVBitsNode);
3469 SDValue AmtLack = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: NVBitsNode, N2: Amt);
3470 SDValue isShort = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3471 LHS: Amt, RHS: NVBitsNode, Cond: ISD::SETULT);
3472 SDValue isZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3473 LHS: Amt, RHS: DAG.getConstant(Val: 0, DL: dl, VT: ShTy),
3474 Cond: ISD::SETEQ);
3475
3476 SDValue LoS, HiS, LoL, HiL;
3477 switch (N->getOpcode()) {
3478 default: llvm_unreachable("Unknown shift");
3479 case ISD::SHL:
3480 // Short: ShAmt < NVTBits
3481 LoS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt);
3482 HiS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3483 N1: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: Amt),
3484 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: AmtLack));
3485
3486 // Long: ShAmt >= NVTBits
3487 LoL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Lo part is zero.
3488 HiL = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: AmtExcess); // Hi from Lo part.
3489
3490 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL);
3491 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InH,
3492 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL));
3493 return true;
3494 case ISD::SRL:
3495 // Short: ShAmt < NVTBits
3496 HiS = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt);
3497 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3498 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3499 // FIXME: If Amt is zero, the following shift generates an undefined result
3500 // on some architectures.
3501 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3502
3503 // Long: ShAmt >= NVTBits
3504 HiL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3505 LoL = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3506
3507 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3508 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3509 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3510 return true;
3511 case ISD::SRA:
3512 // Short: ShAmt < NVTBits
3513 HiS = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt);
3514 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3515 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3516 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3517
3518 // Long: ShAmt >= NVTBits
3519 HiL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign of Hi part.
3520 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3521 LoL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3522
3523 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3524 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3525 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3526 return true;
3527 }
3528}
3529
3530static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
3531
3532 switch (Op) {
3533 default: llvm_unreachable("invalid min/max opcode");
3534 case ISD::SMAX:
3535 return std::make_pair(x: ISD::SETGT, y: ISD::UMAX);
3536 case ISD::UMAX:
3537 return std::make_pair(x: ISD::SETUGT, y: ISD::UMAX);
3538 case ISD::SMIN:
3539 return std::make_pair(x: ISD::SETLT, y: ISD::UMIN);
3540 case ISD::UMIN:
3541 return std::make_pair(x: ISD::SETULT, y: ISD::UMIN);
3542 }
3543}
3544
3545void DAGTypeLegalizer::ExpandIntRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
3546 SDLoc DL(N);
3547
3548 SDValue LHS = N->getOperand(Num: 0);
3549 SDValue RHS = N->getOperand(Num: 1);
3550 EVT NewVT = getSetCCResultType(VT: LHS.getValueType());
3551
3552 // Taking the same approach as ScalarizeVecRes_SETCC
3553 SDValue Res = DAG.getNode(Opcode: ISD::SETCC, DL, VT: NewVT, N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
3554
3555 Res = DAG.getBoolExtOrTrunc(Op: Res, SL: DL, VT: N->getValueType(ResNo: 0), OpVT: NewVT);
3556 SplitInteger(Op: Res, Lo, Hi);
3557}
3558
3559void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
3560 SDValue &Lo, SDValue &Hi) {
3561 SDLoc DL(N);
3562
3563 SDValue LHS = N->getOperand(Num: 0);
3564 SDValue RHS = N->getOperand(Num: 1);
3565
3566 // If the upper halves are all sign bits, then we can perform the MINMAX on
3567 // the lower half and sign-extend the result to the upper half.
3568 unsigned NumBits = N->getValueType(ResNo: 0).getScalarSizeInBits();
3569 unsigned NumHalfBits = NumBits / 2;
3570 if (DAG.ComputeNumSignBits(Op: LHS) > NumHalfBits &&
3571 DAG.ComputeNumSignBits(Op: RHS) > NumHalfBits) {
3572 SDValue LHSL, LHSH, RHSL, RHSH;
3573 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3574 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3575 EVT NVT = LHSL.getValueType();
3576
3577 Lo = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: LHSL, N2: RHSL);
3578 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: Lo,
3579 N2: DAG.getShiftAmountConstant(Val: NumHalfBits - 1, VT: NVT, DL));
3580 return;
3581 }
3582
3583 // The Lo of smin(X, -1) is LHSL if X is negative. Otherwise it's -1.
3584 // The Lo of smax(X, 0) is 0 if X is negative. Otherwise it's LHSL.
3585 if ((N->getOpcode() == ISD::SMAX && isNullConstant(V: RHS)) ||
3586 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(V: RHS))) {
3587 SDValue LHSL, LHSH, RHSL, RHSH;
3588 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3589 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3590 EVT NVT = LHSL.getValueType();
3591 EVT CCT = getSetCCResultType(VT: NVT);
3592
3593 SDValue HiNeg =
3594 DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: DAG.getConstant(Val: 0, DL, VT: NVT), Cond: ISD::SETLT);
3595 if (N->getOpcode() == ISD::SMIN) {
3596 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: LHSL, RHS: DAG.getAllOnesConstant(DL, VT: NVT));
3597 } else {
3598 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: DAG.getConstant(Val: 0, DL, VT: NVT), RHS: LHSL);
3599 }
3600 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3601 return;
3602 }
3603
3604 const APInt *RHSVal = nullptr;
3605 if (auto *RHSConst = dyn_cast<ConstantSDNode>(Val&: RHS))
3606 RHSVal = &RHSConst->getAPIntValue();
3607
3608 // The high half of MIN/MAX is always just the the MIN/MAX of the
3609 // high halves of the operands. Expand this way if it appears profitable.
3610 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) &&
3611 (RHSVal->countLeadingOnes() >= NumHalfBits ||
3612 RHSVal->countLeadingZeros() >= NumHalfBits)) {
3613 SDValue LHSL, LHSH, RHSL, RHSH;
3614 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3615 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3616 EVT NVT = LHSL.getValueType();
3617 EVT CCT = getSetCCResultType(VT: NVT);
3618
3619 ISD::NodeType LoOpc;
3620 ISD::CondCode CondC;
3621 std::tie(args&: CondC, args&: LoOpc) = getExpandedMinMaxOps(Op: N->getOpcode());
3622
3623 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3624 // We need to know whether to select Lo part that corresponds to 'winning'
3625 // Hi part or if Hi parts are equal.
3626 SDValue IsHiLeft = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: CondC);
3627 SDValue IsHiEq = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: ISD::SETEQ);
3628
3629 // Lo part corresponding to the 'winning' Hi part
3630 SDValue LoCmp = DAG.getSelect(DL, VT: NVT, Cond: IsHiLeft, LHS: LHSL, RHS: RHSL);
3631
3632 // Recursed Lo part if Hi parts are equal, this uses unsigned version
3633 SDValue LoMinMax = DAG.getNode(Opcode: LoOpc, DL, VT: NVT, Ops: {LHSL, RHSL});
3634
3635 Lo = DAG.getSelect(DL, VT: NVT, Cond: IsHiEq, LHS: LoMinMax, RHS: LoCmp);
3636 return;
3637 }
3638
3639 // Expand to "a < b ? a : b" etc. Prefer ge/le if that simplifies
3640 // the compare.
3641 ISD::CondCode Pred;
3642 switch (N->getOpcode()) {
3643 default: llvm_unreachable("How did we get here?");
3644 case ISD::SMAX:
3645 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3646 Pred = ISD::SETGE;
3647 else
3648 Pred = ISD::SETGT;
3649 break;
3650 case ISD::SMIN:
3651 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3652 Pred = ISD::SETLE;
3653 else
3654 Pred = ISD::SETLT;
3655 break;
3656 case ISD::UMAX:
3657 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3658 Pred = ISD::SETUGE;
3659 else
3660 Pred = ISD::SETUGT;
3661 break;
3662 case ISD::UMIN:
3663 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3664 Pred = ISD::SETULE;
3665 else
3666 Pred = ISD::SETULT;
3667 break;
3668 }
3669 EVT VT = N->getValueType(ResNo: 0);
3670 EVT CCT = getSetCCResultType(VT);
3671 SDValue Cond = DAG.getSetCC(DL, VT: CCT, LHS, RHS, Cond: Pred);
3672 SDValue Result = DAG.getSelect(DL, VT, Cond, LHS, RHS);
3673 SplitInteger(Op: Result, Lo, Hi);
3674}
3675
3676void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
3677 SDValue ExpandedCMP = TLI.expandCMP(Node: N, DAG);
3678 SplitInteger(Op: ExpandedCMP, Lo, Hi);
3679}
3680
3681void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
3682 SDValue &Lo, SDValue &Hi) {
3683 SDLoc dl(N);
3684 // Expand the subcomponents.
3685 SDValue LHSL, LHSH, RHSL, RHSH;
3686 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3687 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3688
3689 EVT NVT = LHSL.getValueType();
3690 SDValue LoOps[2] = { LHSL, RHSL };
3691 SDValue HiOps[3] = { LHSH, RHSH };
3692
3693 bool HasOpCarry = TLI.isOperationLegalOrCustom(
3694 Op: N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
3695 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3696 if (HasOpCarry) {
3697 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
3698 if (N->getOpcode() == ISD::ADD) {
3699 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3700 HiOps[2] = Lo.getValue(R: 1);
3701 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3702 ? DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3703 : DAG.getNode(Opcode: ISD::UADDO_CARRY, DL: dl, VTList, Ops: HiOps);
3704 } else {
3705 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3706 HiOps[2] = Lo.getValue(R: 1);
3707 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3708 ? DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3709 : DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, Ops: HiOps);
3710 }
3711 return;
3712 }
3713
3714 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
3715 // them. TODO: Teach operation legalization how to expand unsupported
3716 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
3717 // a carry of type MVT::Glue, but there doesn't seem to be any way to
3718 // generate a value of this type in the expanded code sequence.
3719 bool hasCarry =
3720 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3721 ISD::ADDC : ISD::SUBC,
3722 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3723
3724 if (hasCarry) {
3725 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: MVT::Glue);
3726 if (N->getOpcode() == ISD::ADD) {
3727 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3728 HiOps[2] = Lo.getValue(R: 1);
3729 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3730 } else {
3731 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3732 HiOps[2] = Lo.getValue(R: 1);
3733 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3734 }
3735 return;
3736 }
3737
3738 bool hasOVF =
3739 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3740 ISD::UADDO : ISD::USUBO,
3741 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3742 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(Type: NVT);
3743
3744 if (hasOVF) {
3745 EVT OvfVT = getSetCCResultType(VT: NVT);
3746 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: OvfVT);
3747 int RevOpc;
3748 if (N->getOpcode() == ISD::ADD) {
3749 RevOpc = ISD::SUB;
3750 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3751 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3752 } else {
3753 RevOpc = ISD::ADD;
3754 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3755 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3756 }
3757 SDValue OVF = Lo.getValue(R: 1);
3758
3759 switch (BoolType) {
3760 case TargetLoweringBase::UndefinedBooleanContent:
3761 OVF = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: OvfVT, N1: DAG.getConstant(Val: 1, DL: dl, VT: OvfVT), N2: OVF);
3762 [[fallthrough]];
3763 case TargetLoweringBase::ZeroOrOneBooleanContent:
3764 OVF = DAG.getZExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3765 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Hi, N2: OVF);
3766 break;
3767 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3768 OVF = DAG.getSExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3769 Hi = DAG.getNode(Opcode: RevOpc, DL: dl, VT: NVT, N1: Hi, N2: OVF);
3770 }
3771 return;
3772 }
3773
3774 if (N->getOpcode() == ISD::ADD) {
3775 Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: LoOps);
3776 SDValue Cmp;
3777 // Special case: X+1 has a carry out if X+1==0. This may reduce the live
3778 // range of X. We assume comparing with 0 is cheap.
3779 if (isOneConstant(V: LoOps[1]))
3780 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
3781 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3782 else if (isAllOnesConstant(V: LoOps[1])) {
3783 if (isAllOnesConstant(V: HiOps[1]))
3784 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3785 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3786 else
3787 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3788 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
3789 } else
3790 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo, RHS: LoOps[0],
3791 Cond: ISD::SETULT);
3792
3793 SDValue Carry;
3794 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3795 Carry = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3796 else
3797 Carry = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3798 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3799
3800 if (isAllOnesConstant(V: LoOps[1]) && isAllOnesConstant(V: HiOps[1])) {
3801 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: HiOps[0], N2: Carry);
3802 } else {
3803 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3804 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Hi, N2: Carry);
3805 }
3806 } else {
3807 Lo = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: LoOps);
3808 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3809 SDValue Cmp =
3810 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LoOps[0].getValueType()),
3811 LHS: LoOps[0], RHS: LoOps[1], Cond: ISD::SETULT);
3812
3813 SDValue Borrow;
3814 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3815 Borrow = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3816 else
3817 Borrow = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3818 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3819
3820 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Hi, N2: Borrow);
3821 }
3822}
3823
3824void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
3825 SDValue &Lo, SDValue &Hi) {
3826 // Expand the subcomponents.
3827 SDValue LHSL, LHSH, RHSL, RHSH;
3828 SDLoc dl(N);
3829 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3830 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3831 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3832 SDValue LoOps[2] = { LHSL, RHSL };
3833 SDValue HiOps[3] = { LHSH, RHSH };
3834
3835 if (N->getOpcode() == ISD::ADDC) {
3836 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3837 HiOps[2] = Lo.getValue(R: 1);
3838 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3839 } else {
3840 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3841 HiOps[2] = Lo.getValue(R: 1);
3842 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3843 }
3844
3845 // Legalized the flag result - switch anything that used the old flag to
3846 // use the new one.
3847 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3848}
3849
3850void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
3851 SDValue &Lo, SDValue &Hi) {
3852 // Expand the subcomponents.
3853 SDValue LHSL, LHSH, RHSL, RHSH;
3854 SDLoc dl(N);
3855 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3856 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3857 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3858 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3859 SDValue HiOps[3] = { LHSH, RHSH };
3860
3861 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3862 HiOps[2] = Lo.getValue(R: 1);
3863 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
3864
3865 // Legalized the flag result - switch anything that used the old flag to
3866 // use the new one.
3867 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3868}
3869
3870void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
3871 SDValue &Lo, SDValue &Hi) {
3872 SDValue LHS = N->getOperand(Num: 0);
3873 SDValue RHS = N->getOperand(Num: 1);
3874 SDLoc dl(N);
3875
3876 SDValue Ovf;
3877
3878 unsigned CarryOp, NoCarryOp;
3879 ISD::CondCode Cond;
3880 switch(N->getOpcode()) {
3881 case ISD::UADDO:
3882 CarryOp = ISD::UADDO_CARRY;
3883 NoCarryOp = ISD::ADD;
3884 Cond = ISD::SETULT;
3885 break;
3886 case ISD::USUBO:
3887 CarryOp = ISD::USUBO_CARRY;
3888 NoCarryOp = ISD::SUB;
3889 Cond = ISD::SETUGT;
3890 break;
3891 default:
3892 llvm_unreachable("Node has unexpected Opcode");
3893 }
3894
3895 bool HasCarryOp = TLI.isOperationLegalOrCustom(
3896 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
3897
3898 if (HasCarryOp) {
3899 // Expand the subcomponents.
3900 SDValue LHSL, LHSH, RHSL, RHSH;
3901 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3902 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3903 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3904 SDValue LoOps[2] = { LHSL, RHSL };
3905 SDValue HiOps[3] = { LHSH, RHSH };
3906
3907 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3908 HiOps[2] = Lo.getValue(R: 1);
3909 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: HiOps);
3910
3911 Ovf = Hi.getValue(R: 1);
3912 } else {
3913 // Expand the result by simply replacing it with the equivalent
3914 // non-overflow-checking operation.
3915 SDValue Sum = DAG.getNode(Opcode: NoCarryOp, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS);
3916 SplitInteger(Op: Sum, Lo, Hi);
3917
3918 if (N->getOpcode() == ISD::UADDO && isOneConstant(V: RHS)) {
3919 // Special case: uaddo X, 1 overflowed if X+1 == 0. We can detect this
3920 // with (Lo | Hi) == 0.
3921 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Lo.getValueType(), N1: Lo, N2: Hi);
3922 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Or,
3923 RHS: DAG.getConstant(Val: 0, DL: dl, VT: Lo.getValueType()), Cond: ISD::SETEQ);
3924 } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(V: RHS)) {
3925 // Special case: uaddo X, -1 overflows if X == 0.
3926 Ovf =
3927 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS,
3928 RHS: DAG.getConstant(Val: 0, DL: dl, VT: LHS.getValueType()), Cond: ISD::SETNE);
3929 } else {
3930 // Calculate the overflow: addition overflows iff a + b < a, and
3931 // subtraction overflows iff a - b > a.
3932 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Sum, RHS: LHS, Cond);
3933 }
3934 }
3935
3936 // Legalized the flag result - switch anything that used the old flag to
3937 // use the new one.
3938 ReplaceValueWith(From: SDValue(N, 1), To: Ovf);
3939}
3940
3941void DAGTypeLegalizer::ExpandIntRes_UADDSUBO_CARRY(SDNode *N, SDValue &Lo,
3942 SDValue &Hi) {
3943 // Expand the subcomponents.
3944 SDValue LHSL, LHSH, RHSL, RHSH;
3945 SDLoc dl(N);
3946 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3947 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3948 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3949 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3950 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
3951
3952 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3953 HiOps[2] = Lo.getValue(R: 1);
3954 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
3955
3956 // Legalized the flag result - switch anything that used the old flag to
3957 // use the new one.
3958 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3959}
3960
3961void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
3962 SDValue &Lo, SDValue &Hi) {
3963 // Expand the subcomponents.
3964 SDValue LHSL, LHSH, RHSL, RHSH;
3965 SDLoc dl(N);
3966 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3967 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3968 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3969
3970 // We need to use an unsigned carry op for the lo part.
3971 unsigned CarryOp =
3972 N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
3973 Lo = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSL, RHSL, N->getOperand(Num: 2) });
3974 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
3975
3976 // Legalized the flag result - switch anything that used the old flag to
3977 // use the new one.
3978 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3979}
3980
3981void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
3982 SDValue &Lo, SDValue &Hi) {
3983 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3984 SDLoc dl(N);
3985 SDValue Op = N->getOperand(Num: 0);
3986 if (Op.getValueType().bitsLE(VT: NVT)) {
3987 // The low part is any extension of the input (which degenerates to a copy).
3988 Lo = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Op);
3989 Hi = DAG.getUNDEF(VT: NVT); // The high part is undefined.
3990 } else {
3991 // For example, extension of an i48 to an i64. The operand type necessarily
3992 // promotes to the result type, so will end up being expanded too.
3993 assert(getTypeAction(Op.getValueType()) ==
3994 TargetLowering::TypePromoteInteger &&
3995 "Only know how to promote this result!");
3996 SDValue Res = GetPromotedInteger(Op);
3997 assert(Res.getValueType() == N->getValueType(0) &&
3998 "Operand over promoted?");
3999 // Split the promoted operand. This will simplify when it is expanded.
4000 SplitInteger(Op: Res, Lo, Hi);
4001 }
4002}
4003
4004void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
4005 SDValue &Lo, SDValue &Hi) {
4006 SDLoc dl(N);
4007 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4008 EVT NVT = Lo.getValueType();
4009 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4010 unsigned NVTBits = NVT.getSizeInBits();
4011 unsigned EVTBits = EVT.getSizeInBits();
4012
4013 if (NVTBits < EVTBits) {
4014 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Hi,
4015 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4016 BitWidth: EVTBits - NVTBits)));
4017 } else {
4018 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4019 // The high part replicates the sign bit of Lo, make it explicit.
4020 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4021 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL: dl));
4022 }
4023}
4024
4025void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
4026 SDValue &Lo, SDValue &Hi) {
4027 SDLoc dl(N);
4028 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4029 EVT NVT = Lo.getValueType();
4030 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4031 unsigned NVTBits = NVT.getSizeInBits();
4032 unsigned EVTBits = EVT.getSizeInBits();
4033
4034 if (NVTBits < EVTBits) {
4035 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Hi,
4036 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4037 BitWidth: EVTBits - NVTBits)));
4038 } else {
4039 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4040 // The high part must be zero, make it explicit.
4041 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4042 }
4043}
4044
4045void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
4046 SDValue &Lo, SDValue &Hi) {
4047 SDLoc dl(N);
4048 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4049 Lo = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4050 Hi = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4051}
4052
4053void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
4054 SDValue &Lo, SDValue &Hi) {
4055 SDLoc dl(N);
4056 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4057 Lo = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4058 Hi = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4059}
4060
4061void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
4062 SDValue &Hi) {
4063 SDLoc dl(N);
4064 // parity(HiLo) -> parity(Lo^Hi)
4065 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4066 EVT NVT = Lo.getValueType();
4067 Lo =
4068 DAG.getNode(Opcode: ISD::PARITY, DL: dl, VT: NVT, Operand: DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Hi));
4069 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4070}
4071
4072void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
4073 SDValue &Lo, SDValue &Hi) {
4074 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4075 unsigned NBitWidth = NVT.getSizeInBits();
4076 auto Constant = cast<ConstantSDNode>(Val: N);
4077 const APInt &Cst = Constant->getAPIntValue();
4078 bool IsTarget = Constant->isTargetOpcode();
4079 bool IsOpaque = Constant->isOpaque();
4080 SDLoc dl(N);
4081 Lo = DAG.getConstant(Val: Cst.trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget, isOpaque: IsOpaque);
4082 Hi = DAG.getConstant(Val: Cst.lshr(shiftAmt: NBitWidth).trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget,
4083 isOpaque: IsOpaque);
4084}
4085
4086void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4087 SDLoc dl(N);
4088
4089 SDValue N0 = N->getOperand(Num: 0);
4090 GetExpandedInteger(Op: N0, Lo, Hi);
4091 EVT NVT = Lo.getValueType();
4092
4093 // If the upper half is all sign bits, then we can perform the ABS on the
4094 // lower half and zero-extend.
4095 if (DAG.ComputeNumSignBits(Op: N0) > NVT.getScalarSizeInBits()) {
4096 Lo = DAG.getNode(Opcode: ISD::ABS, DL: dl, VT: NVT, Operand: Lo);
4097 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4098 return;
4099 }
4100
4101 // If we have USUBO_CARRY, use the expanded form of the sra+xor+sub sequence
4102 // we use in LegalizeDAG. The SUB part of the expansion is based on
4103 // ExpandIntRes_ADDSUB which also uses USUBO_CARRY/USUBO after checking that
4104 // USUBO_CARRY is LegalOrCustom. Each of the pieces here can be further
4105 // expanded if needed. Shift expansion has a special case for filling with
4106 // sign bits so that we will only end up with one SRA.
4107 bool HasSubCarry = TLI.isOperationLegalOrCustom(
4108 Op: ISD::USUBO_CARRY, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
4109 if (HasSubCarry) {
4110 SDValue Sign = DAG.getNode(
4111 Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Hi,
4112 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - 1, VT: NVT, DL: dl));
4113 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
4114 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Sign);
4115 Hi = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Hi, N2: Sign);
4116 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: Lo, N2: Sign);
4117 Hi = DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: Hi, N2: Sign, N3: Lo.getValue(R: 1));
4118 return;
4119 }
4120
4121 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
4122 EVT VT = N->getValueType(ResNo: 0);
4123 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT,
4124 N1: DAG.getConstant(Val: 0, DL: dl, VT), N2: N0);
4125 SDValue NegLo, NegHi;
4126 SplitInteger(Op: Neg, Lo&: NegLo, Hi&: NegHi);
4127
4128 SDValue HiIsNeg = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4129 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETLT);
4130 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegLo, RHS: Lo);
4131 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegHi, RHS: Hi);
4132}
4133
4134void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
4135 SDValue &Lo, SDValue &Hi) {
4136 SDLoc dl(N);
4137 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
4138 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4139 EVT NVT = Lo.getValueType();
4140
4141 SDValue HiNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4142 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4143
4144 SDValue LoLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Lo);
4145 SDValue HiLZ = DAG.getNode(Opcode: ISD::CTLZ_ZERO_UNDEF, DL: dl, VT: NVT, Operand: Hi);
4146
4147 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiNotZero, LHS: HiLZ,
4148 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoLZ,
4149 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4150 VT: NVT)));
4151 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4152}
4153
4154void DAGTypeLegalizer::ExpandIntRes_CTLS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4155 SDLoc dl(N);
4156 // ctls(HiLo) -> if (IsAllSignBits = (ctls(Hi) == BW-1)) then
4157 // BW-1 + clz(IsNegative = (Hi < 0) ? ~Lo : Lo)
4158 // else ctls(Hi)
4159 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4160 EVT NVT = Lo.getValueType();
4161 unsigned NVTBits = NVT.getScalarSizeInBits();
4162
4163 SDValue Constant0 = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4164 SDValue ConstantBWM1 = DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: NVT);
4165
4166 SDValue HiCTLS = DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Hi);
4167 SDValue IsAllSignBits = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: HiCTLS,
4168 RHS: ConstantBWM1, Cond: ISD::SETEQ);
4169 SDValue IsNegative =
4170 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi, RHS: Constant0, Cond: ISD::SETLT);
4171 SDValue AdjustedLo =
4172 DAG.getSelect(DL: dl, VT: NVT, Cond: IsNegative, LHS: DAG.getNOT(DL: dl, Val: Lo, VT: NVT), RHS: Lo);
4173 SDValue LoCLZ = DAG.getNode(Opcode: ISD::CTLZ, DL: dl, VT: NVT, Operand: AdjustedLo);
4174 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: IsAllSignBits,
4175 LHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoCLZ, N2: ConstantBWM1),
4176 RHS: HiCTLS);
4177 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4178}
4179
4180void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
4181 SDValue Result = TLI.expandABD(N, DAG);
4182 SplitInteger(Op: Result, Lo, Hi);
4183}
4184
4185void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
4186 SDValue Op = N->getOperand(Num: 0);
4187 EVT VT = N->getValueType(ResNo: 0);
4188 SDLoc DL(N);
4189
4190 if (TLI.getOperationAction(Op: ISD::CTPOP, VT) == TargetLoweringBase::LibCall) {
4191 RTLIB::Libcall LC = RTLIB::getCTPOP(VT);
4192 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
4193 "LibCall explicitly requested, but not available");
4194
4195 if (RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
4196 TargetLowering::MakeLibCallOptions CallOptions;
4197 EVT IntVT =
4198 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
4199 SDValue Res =
4200 TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: IntVT, Ops: Op, CallOptions, dl: DL).first;
4201 SplitInteger(Op: DAG.getSExtOrTrunc(Op: Res, DL, VT), Lo, Hi);
4202 return;
4203 }
4204
4205 // If the function is not available, fall back on the expansion.
4206 }
4207
4208 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
4209 GetExpandedInteger(Op, Lo, Hi);
4210 EVT NVT = Lo.getValueType();
4211 Lo = DAG.getNode(Opcode: ISD::ADD, DL, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Lo),
4212 N2: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Hi));
4213 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
4214}
4215
4216void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
4217 SDValue &Lo, SDValue &Hi) {
4218 SDLoc dl(N);
4219 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
4220 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4221 EVT NVT = Lo.getValueType();
4222
4223 SDValue LoNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
4224 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4225
4226 SDValue LoLZ = DAG.getNode(Opcode: ISD::CTTZ_ZERO_UNDEF, DL: dl, VT: NVT, Operand: Lo);
4227 SDValue HiLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Hi);
4228
4229 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: LoNotZero, LHS: LoLZ,
4230 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: HiLZ,
4231 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4232 VT: NVT)));
4233 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4234}
4235
4236void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo,
4237 SDValue &Hi) {
4238 SDLoc dl(N);
4239 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4240 unsigned NBitWidth = NVT.getSizeInBits();
4241
4242 Lo = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
4243 SDValue Chain = Lo.getValue(R: 1);
4244 // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING
4245 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4246 N2: DAG.getShiftAmountConstant(Val: NBitWidth - 1, VT: NVT, DL: dl));
4247
4248 // Legalize the chain result - switch anything that used the old chain to
4249 // use the new one.
4250 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
4251}
4252
4253// Helper for producing an FP_EXTEND/STRICT_FP_EXTEND of Op.
4254static SDValue fpExtendHelper(SDValue Op, SDValue &Chain, bool IsStrict, EVT VT,
4255 SDLoc DL, SelectionDAG &DAG) {
4256 if (IsStrict) {
4257 Op = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL, ResultTys: {VT, MVT::Other}, Ops: {Chain, Op});
4258 Chain = Op.getValue(R: 1);
4259 return Op;
4260 }
4261 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT, Operand: Op);
4262}
4263
4264void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
4265 SDValue &Hi) {
4266 SDLoc dl(N);
4267 EVT VT = N->getValueType(ResNo: 0);
4268
4269 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
4270 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
4271 bool IsStrict = N->isStrictFPOpcode();
4272 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4273 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4274
4275 // If the input is bf16 or needs to be soft promoted, extend to f32.
4276 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf ||
4277 Op.getValueType() == MVT::bf16) {
4278 Op = fpExtendHelper(Op, Chain, IsStrict, VT: MVT::f32, DL: dl, DAG);
4279 }
4280
4281 // NOTE: We need a variable that lives across makeLibCall so
4282 // CallOptions.setTypeListBeforeSoften can save a reference to it.
4283 EVT OpVT = Op.getValueType();
4284
4285 RTLIB::Libcall LC =
4286 IsSigned ? RTLIB::getFPTOSINT(OpVT, RetVT: VT) : RTLIB::getFPTOUINT(OpVT, RetVT: VT);
4287 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
4288 TargetLowering::MakeLibCallOptions CallOptions;
4289 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftenFloat)
4290 CallOptions.setTypeListBeforeSoften(OpsVT: OpVT, RetVT: VT);
4291 else
4292 CallOptions.setIsSigned(true); // FIXME: Is this needed?
4293 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op,
4294 CallOptions, dl, Chain);
4295 SplitInteger(Op: Tmp.first, Lo, Hi);
4296
4297 if (IsStrict)
4298 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4299}
4300
4301void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
4302 SDValue &Hi) {
4303 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
4304 SplitInteger(Op: Res, Lo, Hi);
4305}
4306
4307void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo,
4308 SDValue &Hi) {
4309 SDLoc dl(N);
4310 bool IsStrict = N->isStrictFPOpcode();
4311 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4312 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4313
4314 EVT VT = Op.getValueType();
4315
4316 if (VT == MVT::f16) {
4317 // Extend to f32.
4318 VT = MVT::f32;
4319 Op = fpExtendHelper(Op, Chain, IsStrict, VT, DL: dl, DAG);
4320 }
4321
4322 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4323 if (N->getOpcode() == ISD::LROUND ||
4324 N->getOpcode() == ISD::STRICT_LROUND) {
4325 LC = RTLIB::getLROUND(VT);
4326 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lround input type!");
4327 } else if (N->getOpcode() == ISD::LRINT ||
4328 N->getOpcode() == ISD::STRICT_LRINT) {
4329 LC = RTLIB::getLRINT(RetVT: VT);
4330 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lrint input type!");
4331 } else if (N->getOpcode() == ISD::LLROUND ||
4332 N->getOpcode() == ISD::STRICT_LLROUND) {
4333 LC = RTLIB::getLLROUND(VT);
4334 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
4335 } else if (N->getOpcode() == ISD::LLRINT ||
4336 N->getOpcode() == ISD::STRICT_LLRINT) {
4337 LC = RTLIB::getLLRINT(RetVT: VT);
4338 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
4339 } else
4340 llvm_unreachable("Unexpected opcode!");
4341
4342 EVT RetVT = N->getValueType(ResNo: 0);
4343
4344 TargetLowering::MakeLibCallOptions CallOptions;
4345 CallOptions.setIsSigned(true);
4346 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
4347 Ops: Op, CallOptions, dl,
4348 Chain);
4349 SplitInteger(Op: Tmp.first, Lo, Hi);
4350
4351 if (N->isStrictFPOpcode())
4352 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4353}
4354
4355void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
4356 SDValue &Lo, SDValue &Hi) {
4357 assert(!N->isAtomic() && "Should have been a ATOMIC_LOAD?");
4358
4359 if (ISD::isNormalLoad(N)) {
4360 ExpandRes_NormalLoad(N, Lo, Hi);
4361 return;
4362 }
4363
4364 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
4365
4366 EVT VT = N->getValueType(ResNo: 0);
4367 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4368 SDValue Ch = N->getChain();
4369 SDValue Ptr = N->getBasePtr();
4370 ISD::LoadExtType ExtType = N->getExtensionType();
4371 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4372 AAMDNodes AAInfo = N->getAAInfo();
4373 SDLoc dl(N);
4374
4375 assert(NVT.isByteSized() && "Expanded type not byte sized!");
4376
4377 if (N->getMemoryVT().bitsLE(VT: NVT)) {
4378 EVT MemVT = N->getMemoryVT();
4379
4380 Lo = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), MemVT,
4381 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4382
4383 // Remember the chain.
4384 Ch = Lo.getValue(R: 1);
4385
4386 if (ExtType == ISD::SEXTLOAD) {
4387 // The high part is obtained by SRA'ing all but one of the bits of the
4388 // lo part.
4389 unsigned LoSize = Lo.getValueSizeInBits();
4390 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4391 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
4392 } else if (ExtType == ISD::ZEXTLOAD) {
4393 // The high part is just a zero.
4394 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4395 } else {
4396 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
4397 // The high part is undefined.
4398 Hi = DAG.getUNDEF(VT: NVT);
4399 }
4400 } else if (DAG.getDataLayout().isLittleEndian()) {
4401 // Little-endian - low bits are at low addresses.
4402 Lo = DAG.getLoad(VT: NVT, dl, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
4403 MMOFlags, AAInfo);
4404
4405 unsigned ExcessBits =
4406 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4407 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
4408
4409 // Increment the pointer to the other half.
4410 unsigned IncrementSize = NVT.getSizeInBits()/8;
4411 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4412 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr,
4413 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize), MemVT: NEVT,
4414 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4415
4416 // Build a factor node to remember that this load is independent of the
4417 // other one.
4418 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4419 N2: Hi.getValue(R: 1));
4420 } else {
4421 // Big-endian - high bits are at low addresses. Favor aligned loads at
4422 // the cost of some bit-fiddling.
4423 EVT MemVT = N->getMemoryVT();
4424 unsigned EBytes = MemVT.getStoreSize();
4425 unsigned IncrementSize = NVT.getSizeInBits()/8;
4426 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4427
4428 // Load both the high bits and maybe some of the low bits.
4429 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(),
4430 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(),
4431 BitWidth: MemVT.getSizeInBits() - ExcessBits),
4432 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4433
4434 // Increment the pointer to the other half.
4435 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4436 // Load the rest of the low bits.
4437 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: NVT, Chain: Ch, Ptr,
4438 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
4439 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
4440 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4441
4442 // Build a factor node to remember that this load is independent of the
4443 // other one.
4444 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4445 N2: Hi.getValue(R: 1));
4446
4447 if (ExcessBits < NVT.getSizeInBits()) {
4448 // Transfer low bits from the bottom of Hi to the top of Lo.
4449 Lo = DAG.getNode(
4450 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Lo,
4451 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
4452 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
4453 // Move high bits to the right position in Hi.
4454 Hi = DAG.getNode(Opcode: ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
4455 N1: Hi,
4456 N2: DAG.getShiftAmountConstant(
4457 Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
4458 }
4459 }
4460
4461 // Legalize the chain result - switch anything that used the old chain to
4462 // use the new one.
4463 ReplaceValueWith(From: SDValue(N, 1), To: Ch);
4464}
4465
4466void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
4467 SDValue &Lo, SDValue &Hi) {
4468 SDLoc dl(N);
4469 SDValue LL, LH, RL, RH;
4470 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4471 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4472
4473 SDNodeFlags Flags;
4474 if (N->getOpcode() == ISD::OR)
4475 Flags.setDisjoint(N->getFlags().hasDisjoint());
4476
4477 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LL, N2: RL, Flags);
4478 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LH, N2: RH, Flags);
4479}
4480
4481void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
4482 SDValue &Lo, SDValue &Hi) {
4483 EVT VT = N->getValueType(ResNo: 0);
4484 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4485 SDLoc dl(N);
4486
4487 SDValue LL, LH, RL, RH;
4488 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4489 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4490
4491 if (TLI.expandMUL(N, Lo, Hi, HiLoVT: NVT, DAG,
4492 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4493 LL, LH, RL, RH))
4494 return;
4495
4496 // If nothing else, we can make a libcall.
4497 RTLIB::Libcall LC = RTLIB::getMUL(VT);
4498 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
4499 if (LCImpl == RTLIB::Unsupported) {
4500 // Perform a wide multiplication where the wide type is the original VT and
4501 // the 4 parts are the split arguments.
4502 TLI.forceExpandMultiply(DAG, dl, /*Signed=*/false, Lo, Hi, LHS: LL, RHS: RL, HiLHS: LH, HiRHS: RH);
4503 return;
4504 }
4505
4506 // Note that we don't need to do a wide MUL here since we don't care about the
4507 // upper half of the result if it exceeds VT.
4508 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4509 TargetLowering::MakeLibCallOptions CallOptions;
4510 CallOptions.setIsSigned(true);
4511 SplitInteger(Op: TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
4512 Hi);
4513}
4514
4515void DAGTypeLegalizer::ExpandIntRes_READCOUNTER(SDNode *N, SDValue &Lo,
4516 SDValue &Hi) {
4517 SDLoc DL(N);
4518 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4519 SDVTList VTs = DAG.getVTList(VT1: NVT, VT2: NVT, VT3: MVT::Other);
4520 SDValue R = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N: N->getOperand(Num: 0));
4521 Lo = R.getValue(R: 0);
4522 Hi = R.getValue(R: 1);
4523 ReplaceValueWith(From: SDValue(N, 1), To: R.getValue(R: 2));
4524}
4525
4526void DAGTypeLegalizer::ExpandIntRes_AVG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4527 SDValue Result = TLI.expandAVG(N, DAG);
4528 SplitInteger(Op: Result, Lo, Hi);
4529}
4530
4531void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
4532 SDValue &Hi) {
4533 SDValue Result = TLI.expandAddSubSat(Node: N, DAG);
4534 SplitInteger(Op: Result, Lo, Hi);
4535}
4536
4537void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
4538 SDValue &Hi) {
4539 SDValue Result = TLI.expandShlSat(Node: N, DAG);
4540 SplitInteger(Op: Result, Lo, Hi);
4541}
4542
4543/// This performs an expansion of the integer result for a fixed point
4544/// multiplication. The default expansion performs rounding down towards
4545/// negative infinity, though targets that do care about rounding should specify
4546/// a target hook for rounding and provide their own expansion or lowering of
4547/// fixed point multiplication to be consistent with rounding.
4548void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
4549 SDValue &Hi) {
4550 SDLoc dl(N);
4551 EVT VT = N->getValueType(ResNo: 0);
4552 unsigned VTSize = VT.getScalarSizeInBits();
4553 SDValue LHS = N->getOperand(Num: 0);
4554 SDValue RHS = N->getOperand(Num: 1);
4555 uint64_t Scale = N->getConstantOperandVal(Num: 2);
4556 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
4557 N->getOpcode() == ISD::UMULFIXSAT);
4558 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
4559 N->getOpcode() == ISD::SMULFIXSAT);
4560
4561 // Handle special case when scale is equal to zero.
4562 if (!Scale) {
4563 SDValue Result;
4564 if (!Saturating) {
4565 Result = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS);
4566 } else {
4567 EVT BoolVT = getSetCCResultType(VT);
4568 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
4569 Result = DAG.getNode(Opcode: MulOp, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: BoolVT), N1: LHS, N2: RHS);
4570 SDValue Product = Result.getValue(R: 0);
4571 SDValue Overflow = Result.getValue(R: 1);
4572 if (Signed) {
4573 APInt MinVal = APInt::getSignedMinValue(numBits: VTSize);
4574 APInt MaxVal = APInt::getSignedMaxValue(numBits: VTSize);
4575 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT);
4576 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4577 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
4578 // Xor the inputs, if resulting sign bit is 0 the product will be
4579 // positive, else negative.
4580 SDValue Xor = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4581 SDValue ProdNeg = DAG.getSetCC(DL: dl, VT: BoolVT, LHS: Xor, RHS: Zero, Cond: ISD::SETLT);
4582 Result = DAG.getSelect(DL: dl, VT, Cond: ProdNeg, LHS: SatMin, RHS: SatMax);
4583 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: Result, RHS: Product);
4584 } else {
4585 // For unsigned multiplication, we only need to check the max since we
4586 // can't really overflow towards zero.
4587 APInt MaxVal = APInt::getMaxValue(numBits: VTSize);
4588 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4589 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: SatMax, RHS: Product);
4590 }
4591 }
4592 SplitInteger(Op: Result, Lo, Hi);
4593 return;
4594 }
4595
4596 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
4597 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
4598 assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
4599
4600 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4601 SDValue LL, LH, RL, RH;
4602 GetExpandedInteger(Op: LHS, Lo&: LL, Hi&: LH);
4603 GetExpandedInteger(Op: RHS, Lo&: RL, Hi&: RH);
4604 SmallVector<SDValue, 4> Result;
4605
4606 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
4607 if (!TLI.expandMUL_LOHI(Opcode: LoHiOp, VT, dl, LHS, RHS, Result, HiLoVT: NVT, DAG,
4608 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4609 LL, LH, RL, RH)) {
4610 Result.clear();
4611 Result.resize(N: 4);
4612
4613 SDValue LoTmp, HiTmp;
4614 TLI.forceExpandWideMUL(DAG, dl, Signed, LHS, RHS, Lo&: LoTmp, Hi&: HiTmp);
4615 SplitInteger(Op: LoTmp, Lo&: Result[0], Hi&: Result[1]);
4616 SplitInteger(Op: HiTmp, Lo&: Result[2], Hi&: Result[3]);
4617 }
4618 assert(Result.size() == 4 && "Unexpected number of partlets in the result");
4619
4620 unsigned NVTSize = NVT.getScalarSizeInBits();
4621 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
4622 "the size of the current value type");
4623
4624 // After getting the multiplication result in 4 parts, we need to perform a
4625 // shift right by the amount of the scale to get the result in that scale.
4626 //
4627 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
4628 // 128 bits that are cut into 4 32-bit parts:
4629 //
4630 // HH HL LH LL
4631 // |---32---|---32---|---32---|---32---|
4632 // 128 96 64 32 0
4633 //
4634 // |------VTSize-----|
4635 //
4636 // |NVTSize-|
4637 //
4638 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
4639 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
4640 // amount and get Lo and Hi using two funnel shifts. Or for the special case
4641 // when Scale is a multiple of NVTSize we can just pick the result without
4642 // shifting.
4643 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
4644 if (Scale % NVTSize) {
4645 SDValue ShiftAmount = DAG.getShiftAmountConstant(Val: Scale % NVTSize, VT: NVT, DL: dl);
4646 Lo = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 1], N2: Result[Part0],
4647 N3: ShiftAmount);
4648 Hi = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 2], N2: Result[Part0 + 1],
4649 N3: ShiftAmount);
4650 } else {
4651 Lo = Result[Part0];
4652 Hi = Result[Part0 + 1];
4653 }
4654
4655 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
4656 if (!Saturating)
4657 return;
4658
4659 // Can not overflow when there is no integer part.
4660 if (Scale == VTSize)
4661 return;
4662
4663 // To handle saturation we must check for overflow in the multiplication.
4664 //
4665 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
4666 // aren't all zeroes.
4667 //
4668 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
4669 // aren't all ones or all zeroes.
4670 //
4671 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
4672 // highest bit of HH determines saturation direction in the event of signed
4673 // saturation.
4674
4675 SDValue ResultHL = Result[2];
4676 SDValue ResultHH = Result[3];
4677
4678 SDValue SatMax, SatMin;
4679 SDValue NVTZero = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4680 SDValue NVTNeg1 = DAG.getAllOnesConstant(DL: dl, VT: NVT);
4681 EVT BoolNVT = getSetCCResultType(VT: NVT);
4682
4683 if (!Signed) {
4684 if (Scale < NVTSize) {
4685 // Overflow happened if ((HH | (HL >> Scale)) != 0).
4686 SDValue HLAdjusted =
4687 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4688 N2: DAG.getShiftAmountConstant(Val: Scale, VT: NVT, DL: dl));
4689 SDValue Tmp = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: HLAdjusted, N2: ResultHH);
4690 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: Tmp, RHS: NVTZero, Cond: ISD::SETNE);
4691 } else if (Scale == NVTSize) {
4692 // Overflow happened if (HH != 0).
4693 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETNE);
4694 } else if (Scale < VTSize) {
4695 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
4696 SDValue HLAdjusted =
4697 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4698 N2: DAG.getShiftAmountConstant(Val: Scale - NVTSize, VT: NVT, DL: dl));
4699 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: HLAdjusted, RHS: NVTZero, Cond: ISD::SETNE);
4700 } else
4701 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
4702 "(and saturation can't happen with Scale==VTSize).");
4703
4704 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Hi);
4705 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Lo);
4706 return;
4707 }
4708
4709 if (Scale < NVTSize) {
4710 // The number of overflow bits we can check are VTSize - Scale + 1 (we
4711 // include the sign bit). If these top bits are > 0, then we overflowed past
4712 // the max value. If these top bits are < -1, then we overflowed past the
4713 // min value. Otherwise, we did not overflow.
4714 unsigned OverflowBits = VTSize - Scale + 1;
4715 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
4716 "Extent of overflow bits must start within HL");
4717 SDValue HLHiMask = DAG.getConstant(
4718 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits - NVTSize), DL: dl, VT: NVT);
4719 SDValue HLLoMask = DAG.getConstant(
4720 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: VTSize - OverflowBits), DL: dl, VT: NVT);
4721 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
4722 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4723 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4724 SDValue HLUGT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLLoMask, Cond: ISD::SETUGT);
4725 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4726 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLUGT));
4727 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
4728 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4729 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4730 SDValue HLULT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLHiMask, Cond: ISD::SETULT);
4731 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4732 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLULT));
4733 } else if (Scale == NVTSize) {
4734 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
4735 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4736 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4737 SDValue HLNeg = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETLT);
4738 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4739 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLNeg));
4740 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
4741 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4742 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4743 SDValue HLPos = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETGE);
4744 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4745 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLPos));
4746 } else if (Scale < VTSize) {
4747 // This is similar to the case when we saturate if Scale < NVTSize, but we
4748 // only need to check HH.
4749 unsigned OverflowBits = VTSize - Scale + 1;
4750 SDValue HHHiMask = DAG.getConstant(
4751 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits), DL: dl, VT: NVT);
4752 SDValue HHLoMask = DAG.getConstant(
4753 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: NVTSize - OverflowBits), DL: dl, VT: NVT);
4754 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHLoMask, Cond: ISD::SETGT);
4755 SatMin = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHHiMask, Cond: ISD::SETLT);
4756 } else
4757 llvm_unreachable("Illegal scale for signed fixed point mul.");
4758
4759 // Saturate to signed maximum.
4760 APInt MaxHi = APInt::getSignedMaxValue(numBits: NVTSize);
4761 APInt MaxLo = APInt::getAllOnes(numBits: NVTSize);
4762 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxHi, DL: dl, VT: NVT), RHS: Hi);
4763 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxLo, DL: dl, VT: NVT), RHS: Lo);
4764 // Saturate to signed minimum.
4765 APInt MinHi = APInt::getSignedMinValue(numBits: NVTSize);
4766 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: DAG.getConstant(Val: MinHi, DL: dl, VT: NVT), RHS: Hi);
4767 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: NVTZero, RHS: Lo);
4768}
4769
4770void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
4771 SDValue &Hi) {
4772 SDLoc dl(N);
4773 // Try expanding in the existing type first.
4774 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: N->getOperand(Num: 0),
4775 RHS: N->getOperand(Num: 1),
4776 Scale: N->getConstantOperandVal(Num: 2), DAG);
4777
4778 if (!Res)
4779 Res = earlyExpandDIVFIX(N, LHS: N->getOperand(Num: 0), RHS: N->getOperand(Num: 1),
4780 Scale: N->getConstantOperandVal(Num: 2), TLI, DAG);
4781 SplitInteger(Op: Res, Lo, Hi);
4782}
4783
4784void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
4785 SDValue &Lo, SDValue &Hi) {
4786 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
4787 "Node has unexpected Opcode");
4788 SDValue LHS = Node->getOperand(Num: 0);
4789 SDValue RHS = Node->getOperand(Num: 1);
4790 SDLoc dl(Node);
4791
4792 SDValue Ovf;
4793
4794 bool IsAdd = Node->getOpcode() == ISD::SADDO;
4795 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
4796
4797 bool HasCarryOp = TLI.isOperationLegalOrCustom(
4798 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
4799
4800 if (HasCarryOp) {
4801 // Expand the subcomponents.
4802 SDValue LHSL, LHSH, RHSL, RHSH;
4803 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
4804 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
4805 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: Node->getValueType(ResNo: 1));
4806
4807 Lo = DAG.getNode(Opcode: IsAdd ? ISD::UADDO : ISD::USUBO, DL: dl, VTList, Ops: {LHSL, RHSL});
4808 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4809
4810 Ovf = Hi.getValue(R: 1);
4811 } else {
4812 // Expand the result by simply replacing it with the equivalent
4813 // non-overflow-checking operation.
4814 SDValue Sum = DAG.getNode(Opcode: Node->getOpcode() == ISD::SADDO ?
4815 ISD::ADD : ISD::SUB, DL: dl, VT: LHS.getValueType(),
4816 N1: LHS, N2: RHS);
4817 SplitInteger(Op: Sum, Lo, Hi);
4818
4819 // Compute the overflow.
4820 //
4821 // LHSSign -> LHS < 0
4822 // RHSSign -> RHS < 0
4823 // SumSign -> Sum < 0
4824 //
4825 // Add:
4826 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4827 // Sub:
4828 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4829 //
4830 // To get better codegen we can rewrite this by doing bitwise math on
4831 // the integers and extract the final sign bit at the end. So the
4832 // above becomes:
4833 //
4834 // Add:
4835 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
4836 // Sub:
4837 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
4838 //
4839 // NOTE: This is different than the expansion we do in expandSADDSUBO
4840 // because it is more costly to determine the RHS is > 0 for SSUBO with the
4841 // integers split.
4842 EVT VT = LHS.getValueType();
4843 SDValue SignsMatch = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4844 if (IsAdd)
4845 SignsMatch = DAG.getNOT(DL: dl, Val: SignsMatch, VT);
4846
4847 SDValue SumSignNE = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: Sum);
4848 Ovf = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: SignsMatch, N2: SumSignNE);
4849 EVT OType = Node->getValueType(ResNo: 1);
4850 Ovf = DAG.getSetCC(DL: dl, VT: OType, LHS: Ovf, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETLT);
4851 }
4852
4853 // Use the calculated overflow everywhere.
4854 ReplaceValueWith(From: SDValue(Node, 1), To: Ovf);
4855}
4856
4857void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
4858 SDValue &Lo, SDValue &Hi) {
4859 EVT VT = N->getValueType(ResNo: 0);
4860 SDLoc dl(N);
4861 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4862
4863 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
4864 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
4865 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
4866 return;
4867 }
4868
4869 RTLIB::Libcall LC = RTLIB::getSDIV(VT);
4870 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
4871
4872 TargetLowering::MakeLibCallOptions CallOptions;
4873 CallOptions.setIsSigned(true);
4874 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
4875}
4876
4877void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
4878 SDValue &Hi) {
4879 SDLoc dl(N);
4880 SDValue Shiftee = N->getOperand(Num: 0);
4881 EVT VT = Shiftee.getValueType();
4882 SDValue ShAmt = N->getOperand(Num: 1);
4883 EVT ShAmtVT = ShAmt.getValueType();
4884
4885 EVT LoadVT = VT;
4886 do {
4887 LoadVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: LoadVT);
4888 } while (!TLI.isTypeLegal(VT: LoadVT));
4889
4890 const unsigned ShiftUnitInBits = LoadVT.getStoreSizeInBits();
4891 assert(ShiftUnitInBits <= VT.getScalarSizeInBits());
4892 assert(isPowerOf2_32(ShiftUnitInBits) &&
4893 "Shifting unit is not a a power of two!");
4894
4895 const bool IsOneStepShift =
4896 DAG.computeKnownBits(Op: ShAmt).countMinTrailingZeros() >=
4897 Log2_32(Value: ShiftUnitInBits);
4898
4899 // If we can't do it as one step, we'll have two uses of shift amount,
4900 // and thus must freeze it.
4901 if (!IsOneStepShift)
4902 ShAmt = DAG.getFreeze(V: ShAmt);
4903
4904 unsigned VTBitWidth = VT.getScalarSizeInBits();
4905 assert(VTBitWidth % 8 == 0 && "Shifting a not byte multiple value?");
4906 unsigned VTByteWidth = VTBitWidth / 8;
4907 assert(isPowerOf2_32(VTByteWidth) &&
4908 "Shiftee type size is not a power of two!");
4909 unsigned StackSlotByteWidth = 2 * VTByteWidth;
4910 unsigned StackSlotBitWidth = 8 * StackSlotByteWidth;
4911 EVT StackSlotVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StackSlotBitWidth);
4912
4913 // Get a temporary stack slot 2x the width of our VT.
4914 // FIXME: reuse stack slots?
4915 Align StackAlign = DAG.getReducedAlign(VT: StackSlotVT, /*UseABI=*/false);
4916 SDValue StackPtr =
4917 DAG.CreateStackTemporary(Bytes: StackSlotVT.getStoreSize(), Alignment: StackAlign);
4918 EVT PtrTy = StackPtr.getValueType();
4919 SDValue Ch = DAG.getEntryNode();
4920
4921 MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
4922 MF&: DAG.getMachineFunction(),
4923 FI: cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex());
4924
4925 // Extend the value, that is being shifted, to the entire stack slot's width.
4926 SDValue Init;
4927 if (N->getOpcode() != ISD::SHL) {
4928 unsigned WideningOpc =
4929 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4930 Init = DAG.getNode(Opcode: WideningOpc, DL: dl, VT: StackSlotVT, Operand: Shiftee);
4931 } else {
4932 // For left-shifts, pad the Shiftee's LSB with zeros to twice it's width.
4933 SDValue AllZeros = DAG.getConstant(Val: 0, DL: dl, VT);
4934 Init = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: StackSlotVT, N1: AllZeros, N2: Shiftee);
4935 }
4936 // And spill it into the stack slot.
4937 Ch = DAG.getStore(Chain: Ch, dl, Val: Init, Ptr: StackPtr, PtrInfo: StackPtrInfo, Alignment: StackAlign);
4938
4939 // Now, compute the full-byte offset into stack slot from where we can load.
4940 // We have shift amount, which is in bits. Offset should point to an aligned
4941 // address.
4942 SDNodeFlags Flags;
4943 Flags.setExact(IsOneStepShift);
4944 SDValue SrlTmp = DAG.getNode(
4945 Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: ShAmt,
4946 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT), Flags);
4947 SDValue BitOffset =
4948 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: ShAmtVT, N1: SrlTmp,
4949 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT));
4950
4951 SDValue ByteOffset =
4952 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: BitOffset,
4953 N2: DAG.getConstant(Val: 3, DL: dl, VT: ShAmtVT), Flags: SDNodeFlags::Exact);
4954 // And clamp it, because OOB load is an immediate UB,
4955 // while shift overflow would have *just* been poison.
4956 ByteOffset = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ByteOffset,
4957 N2: DAG.getConstant(Val: VTByteWidth - 1, DL: dl, VT: ShAmtVT));
4958 // We have exactly two strategies on indexing into stack slot here:
4959 // 1. upwards starting from the beginning of the slot
4960 // 2. downwards starting from the middle of the slot
4961 // On little-endian machine, we pick 1. for right shifts and 2. for left-shift
4962 // and vice versa on big-endian machine.
4963 bool WillIndexUpwards = N->getOpcode() != ISD::SHL;
4964 if (DAG.getDataLayout().isBigEndian())
4965 WillIndexUpwards = !WillIndexUpwards;
4966
4967 SDValue AdjStackPtr;
4968 if (WillIndexUpwards) {
4969 AdjStackPtr = StackPtr;
4970 } else {
4971 AdjStackPtr = DAG.getMemBasePlusOffset(
4972 Base: StackPtr, Offset: DAG.getConstant(Val: VTByteWidth, DL: dl, VT: PtrTy), DL: dl);
4973 ByteOffset = DAG.getNegative(Val: ByteOffset, DL: dl, VT: ShAmtVT);
4974 }
4975
4976 // Get the pointer somewhere into the stack slot from which we need to load.
4977 ByteOffset = DAG.getSExtOrTrunc(Op: ByteOffset, DL: dl, VT: PtrTy);
4978 AdjStackPtr = DAG.getMemBasePlusOffset(Base: AdjStackPtr, Offset: ByteOffset, DL: dl);
4979
4980 // And load it! While the load is not legal, legalizing it is obvious.
4981 SDValue Res =
4982 DAG.getLoad(VT, dl, Chain: Ch, Ptr: AdjStackPtr,
4983 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
4984 Alignment: commonAlignment(A: StackAlign, Offset: LoadVT.getStoreSize()));
4985
4986 // If we may still have a remaining bits to shift by, do so now.
4987 if (!IsOneStepShift) {
4988 SDValue ShAmtRem =
4989 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ShAmt,
4990 N2: DAG.getConstant(Val: ShiftUnitInBits - 1, DL: dl, VT: ShAmtVT));
4991 Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT, N1: Res, N2: ShAmtRem);
4992 }
4993
4994 // Finally, split the computed value.
4995 SplitInteger(Op: Res, Lo, Hi);
4996}
4997
4998void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
4999 SDValue &Lo, SDValue &Hi) {
5000 EVT VT = N->getValueType(ResNo: 0);
5001 unsigned Opc = N->getOpcode();
5002 SDLoc dl(N);
5003
5004 // If we can emit an efficient shift operation, do so now. Check to see if
5005 // the RHS is a constant.
5006 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1)))
5007 return ExpandShiftByConstant(N, Amt: CN->getAPIntValue(), Lo, Hi);
5008
5009 // If we can determine that the high bit of the shift is zero or one, even if
5010 // the low bits are variable, emit this shift in an optimized form.
5011 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
5012 return;
5013
5014 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
5015 unsigned PartsOpc;
5016 if (Opc == ISD::SHL) {
5017 PartsOpc = ISD::SHL_PARTS;
5018 } else if (Opc == ISD::SRL) {
5019 PartsOpc = ISD::SRL_PARTS;
5020 } else {
5021 assert(Opc == ISD::SRA && "Unknown shift!");
5022 PartsOpc = ISD::SRA_PARTS;
5023 }
5024
5025 // Next check to see if the target supports this SHL_PARTS operation or if it
5026 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
5027 // size, but create a libcall instead.
5028 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5029 TargetLowering::LegalizeAction Action = TLI.getOperationAction(Op: PartsOpc, VT: NVT);
5030 const bool LegalOrCustom =
5031 (Action == TargetLowering::Legal && TLI.isTypeLegal(VT: NVT)) ||
5032 Action == TargetLowering::Custom;
5033
5034 unsigned ExpansionFactor = 1;
5035 // That VT->NVT expansion is one step. But will we re-expand NVT?
5036 for (EVT TmpVT = NVT;;) {
5037 EVT NewTMPVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: TmpVT);
5038 if (NewTMPVT == TmpVT)
5039 break;
5040 TmpVT = NewTMPVT;
5041 ++ExpansionFactor;
5042 }
5043
5044 TargetLowering::ShiftLegalizationStrategy S =
5045 TLI.preferredShiftLegalizationStrategy(DAG, N, ExpansionFactor);
5046
5047 if (S == TargetLowering::ShiftLegalizationStrategy::ExpandThroughStack)
5048 return ExpandIntRes_ShiftThroughStack(N, Lo, Hi);
5049
5050 if (LegalOrCustom &&
5051 S != TargetLowering::ShiftLegalizationStrategy::LowerToLibcall) {
5052 // Expand the subcomponents.
5053 SDValue LHSL, LHSH;
5054 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
5055 EVT VT = LHSL.getValueType();
5056
5057 // If the shift amount operand is coming from a vector legalization it may
5058 // have an illegal type. Fix that first by casting the operand, otherwise
5059 // the new SHL_PARTS operation would need further legalization.
5060 SDValue ShiftOp = N->getOperand(Num: 1);
5061 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
5062 if (ShiftOp.getValueType() != ShiftTy)
5063 ShiftOp = DAG.getZExtOrTrunc(Op: ShiftOp, DL: dl, VT: ShiftTy);
5064
5065 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
5066 Lo = DAG.getNode(Opcode: PartsOpc, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5067 Hi = Lo.getValue(R: 1);
5068 return;
5069 }
5070
5071 // Otherwise, emit a libcall.
5072 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5073 bool isSigned;
5074 if (Opc == ISD::SHL) {
5075 isSigned = false; /*sign irrelevant*/
5076 LC = RTLIB::getSHL(VT);
5077 } else if (Opc == ISD::SRL) {
5078 isSigned = false;
5079 LC = RTLIB::getSRL(VT);
5080 } else {
5081 assert(Opc == ISD::SRA && "Unknown shift!");
5082 isSigned = true;
5083 LC = RTLIB::getSRA(VT);
5084 }
5085
5086 if (RTLIB::LibcallImpl LibcallImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
5087 EVT ShAmtTy =
5088 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
5089 SDValue ShAmt = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl, VT: ShAmtTy);
5090 SDValue Ops[2] = {N->getOperand(Num: 0), ShAmt};
5091 TargetLowering::MakeLibCallOptions CallOptions;
5092 CallOptions.setIsSigned(isSigned);
5093 SplitInteger(
5094 Op: TLI.makeLibCall(DAG, LibcallImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
5095 Hi);
5096 return;
5097 }
5098
5099 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
5100 llvm_unreachable("Unsupported shift!");
5101}
5102
5103void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
5104 SDValue &Lo, SDValue &Hi) {
5105 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5106 SDLoc dl(N);
5107 SDValue Op = N->getOperand(Num: 0);
5108 if (Op.getValueType().bitsLE(VT: NVT)) {
5109 // The low part is sign extension of the input (degenerates to a copy).
5110 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5111 // The high part is obtained by SRA'ing all but one of the bits of low part.
5112 unsigned LoSize = NVT.getSizeInBits();
5113 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
5114 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
5115 } else {
5116 // For example, extension of an i48 to an i64. The operand type necessarily
5117 // promotes to the result type, so will end up being expanded too.
5118 assert(getTypeAction(Op.getValueType()) ==
5119 TargetLowering::TypePromoteInteger &&
5120 "Only know how to promote this result!");
5121 SDValue Res = GetPromotedInteger(Op);
5122 assert(Res.getValueType() == N->getValueType(0) &&
5123 "Operand over promoted?");
5124 // Split the promoted operand. This will simplify when it is expanded.
5125 SplitInteger(Op: Res, Lo, Hi);
5126 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5127 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5128 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5129 BitWidth: ExcessBits)));
5130 }
5131}
5132
5133void DAGTypeLegalizer::
5134ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
5135 SDLoc dl(N);
5136 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5137 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
5138
5139 if (EVT.bitsLE(VT: Lo.getValueType())) {
5140 // sext_inreg the low part if needed.
5141 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Lo.getValueType(), N1: Lo,
5142 N2: N->getOperand(Num: 1));
5143
5144 // The high part gets the sign extension from the lo-part. This handles
5145 // things like sextinreg V:i64 from i8.
5146 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: Hi.getValueType(), N1: Lo,
5147 N2: DAG.getShiftAmountConstant(Val: Hi.getValueSizeInBits() - 1,
5148 VT: Hi.getValueType(), DL: dl));
5149 } else {
5150 // For example, extension of an i48 to an i64. Leave the low part alone,
5151 // sext_inreg the high part.
5152 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
5153 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5154 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5155 BitWidth: ExcessBits)));
5156 }
5157}
5158
5159void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
5160 SDValue &Lo, SDValue &Hi) {
5161 EVT VT = N->getValueType(ResNo: 0);
5162 SDLoc dl(N);
5163 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5164
5165 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5166 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5167 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5168 return;
5169 }
5170
5171 RTLIB::Libcall LC = RTLIB::getSREM(VT);
5172 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
5173
5174 TargetLowering::MakeLibCallOptions CallOptions;
5175 CallOptions.setIsSigned(true);
5176 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5177}
5178
5179void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
5180 SDValue &Lo, SDValue &Hi) {
5181 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5182 SDValue InOp = N->getOperand(Num: 0);
5183 EVT InVT = InOp.getValueType();
5184 SDLoc dl(N);
5185 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: InOp);
5186 Hi = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: InVT, N1: InOp,
5187 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits(), VT: InVT, DL: dl));
5188 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Hi);
5189}
5190
5191void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
5192 SDValue &Lo, SDValue &Hi) {
5193 EVT VT = N->getValueType(ResNo: 0);
5194 SDLoc dl(N);
5195
5196 if (N->getOpcode() == ISD::UMULO) {
5197 // This section expands the operation into the following sequence of
5198 // instructions. `iNh` here refers to a type which has half the bit width of
5199 // the type the original operation operated on.
5200 //
5201 // %0 = %LHS.HI != 0 && %RHS.HI != 0
5202 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
5203 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
5204 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
5205 // %4 = add iNh %1.0, %2.0 as iN
5206 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
5207 //
5208 // %lo = %3.LO
5209 // %hi = %5.0
5210 // %ovf = %0 || %1.1 || %2.1 || %5.1
5211 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
5212 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
5213 GetExpandedInteger(Op: LHS, Lo&: LHSLow, Hi&: LHSHigh);
5214 GetExpandedInteger(Op: RHS, Lo&: RHSLow, Hi&: RHSHigh);
5215 EVT HalfVT = LHSLow.getValueType();
5216 EVT BitVT = N->getValueType(ResNo: 1);
5217 SDVTList VTHalfWithO = DAG.getVTList(VT1: HalfVT, VT2: BitVT);
5218
5219 SDValue HalfZero = DAG.getConstant(Val: 0, DL: dl, VT: HalfVT);
5220 SDValue Overflow = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BitVT,
5221 N1: DAG.getSetCC(DL: dl, VT: BitVT, LHS: LHSHigh, RHS: HalfZero, Cond: ISD::SETNE),
5222 N2: DAG.getSetCC(DL: dl, VT: BitVT, LHS: RHSHigh, RHS: HalfZero, Cond: ISD::SETNE));
5223
5224 SDValue One = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: LHSHigh, N2: RHSLow);
5225 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: One.getValue(R: 1));
5226
5227 SDValue Two = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: RHSHigh, N2: LHSLow);
5228 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Two.getValue(R: 1));
5229
5230 SDValue HighSum = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: HalfVT, N1: One, N2: Two);
5231
5232 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
5233 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
5234 // operation recursively legalized?).
5235 //
5236 // Many backends understand this pattern and will convert into LOHI
5237 // themselves, if applicable.
5238 SDValue Three = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT,
5239 N1: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: LHSLow),
5240 N2: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: RHSLow));
5241 SplitInteger(Op: Three, Lo, Hi);
5242
5243 Hi = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList: VTHalfWithO, N1: Hi, N2: HighSum);
5244 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Hi.getValue(R: 1));
5245 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5246 return;
5247 }
5248
5249 Type *RetTy = VT.getTypeForEVT(Context&: *DAG.getContext());
5250 EVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
5251 Type *PtrTy = PtrVT.getTypeForEVT(Context&: *DAG.getContext());
5252
5253 // Replace this with a libcall that will check overflow.
5254 RTLIB::Libcall LC = RTLIB::getMULO(VT);
5255 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
5256
5257 // If we don't have the libcall or if the function we are compiling is the
5258 // implementation of the expected libcall (avoid inf-loop), expand inline.
5259 if (LCImpl == RTLIB::Unsupported ||
5260 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LCImpl) ==
5261 DAG.getMachineFunction().getName()) {
5262 // FIXME: This is not an optimal expansion, but better than crashing.
5263 SDValue MulLo, MulHi;
5264 TLI.forceExpandWideMUL(DAG, dl, /*Signed=*/true, LHS: N->getOperand(Num: 0),
5265 RHS: N->getOperand(Num: 1), Lo&: MulLo, Hi&: MulHi);
5266 SDValue SRA = DAG.getNode(
5267 Opcode: ISD::SRA, DL: dl, VT, N1: MulLo,
5268 N2: DAG.getShiftAmountConstant(Val: VT.getScalarSizeInBits() - 1, VT, DL: dl));
5269 SDValue Overflow =
5270 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: MulHi, RHS: SRA, Cond: ISD::SETNE);
5271 SplitInteger(Op: MulLo, Lo, Hi);
5272 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5273 return;
5274 }
5275
5276 SDValue Temp = DAG.CreateStackTemporary(VT: PtrVT);
5277 // Temporary for the overflow value, default it to zero.
5278 SDValue Chain =
5279 DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT), Ptr: Temp,
5280 PtrInfo: MachinePointerInfo());
5281
5282 TargetLowering::ArgListTy Args;
5283 for (const SDValue &Op : N->op_values()) {
5284 EVT ArgVT = Op.getValueType();
5285 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
5286 TargetLowering::ArgListEntry Entry(Op, ArgTy);
5287 Entry.IsSExt = true;
5288 Entry.IsZExt = false;
5289 Args.push_back(x: Entry);
5290 }
5291
5292 // Also pass the address of the overflow check.
5293 TargetLowering::ArgListEntry Entry(
5294 Temp, PointerType::getUnqual(C&: PtrTy->getContext()));
5295 Entry.IsSExt = true;
5296 Entry.IsZExt = false;
5297 Args.push_back(x: Entry);
5298
5299 SDValue Func = DAG.getExternalSymbol(LCImpl, VT: PtrVT);
5300
5301 TargetLowering::CallLoweringInfo CLI(DAG);
5302 CLI.setDebugLoc(dl)
5303 .setChain(Chain)
5304 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
5305 Target: Func, ArgsList: std::move(Args))
5306 .setSExtResult();
5307
5308 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
5309
5310 SplitInteger(Op: CallInfo.first, Lo, Hi);
5311 SDValue Temp2 =
5312 DAG.getLoad(VT: PtrVT, dl, Chain: CallInfo.second, Ptr: Temp, PtrInfo: MachinePointerInfo());
5313 SDValue Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Temp2,
5314 RHS: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT),
5315 Cond: ISD::SETNE);
5316 // Use the overflow from the libcall everywhere.
5317 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
5318}
5319
5320void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
5321 SDValue &Lo, SDValue &Hi) {
5322 EVT VT = N->getValueType(ResNo: 0);
5323 SDLoc dl(N);
5324 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5325
5326 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5327 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5328 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5329 return;
5330 }
5331
5332 // Try to expand UDIV by constant.
5333 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5334 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5335 // Only if the new type is legal.
5336 if (isTypeLegal(VT: NVT)) {
5337 SDValue InL, InH;
5338 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5339 SmallVector<SDValue> Result;
5340 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5341 Lo = Result[0];
5342 Hi = Result[1];
5343 return;
5344 }
5345 }
5346 }
5347
5348 RTLIB::Libcall LC = RTLIB::getUDIV(VT);
5349 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
5350
5351 TargetLowering::MakeLibCallOptions CallOptions;
5352 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5353}
5354
5355void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
5356 SDValue &Lo, SDValue &Hi) {
5357 EVT VT = N->getValueType(ResNo: 0);
5358 SDLoc dl(N);
5359 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5360
5361 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5362 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5363 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5364 return;
5365 }
5366
5367 // Try to expand UREM by constant.
5368 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5369 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5370 // Only if the new type is legal.
5371 if (isTypeLegal(VT: NVT)) {
5372 SDValue InL, InH;
5373 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5374 SmallVector<SDValue> Result;
5375 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5376 Lo = Result[0];
5377 Hi = Result[1];
5378 return;
5379 }
5380 }
5381 }
5382
5383 RTLIB::Libcall LC = RTLIB::getUREM(VT);
5384 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
5385
5386 TargetLowering::MakeLibCallOptions CallOptions;
5387 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5388}
5389
5390void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
5391 SDValue &Lo, SDValue &Hi) {
5392 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5393 SDLoc dl(N);
5394 SDValue Op = N->getOperand(Num: 0);
5395 if (Op.getValueType().bitsLE(VT: NVT)) {
5396 // The low part is zero extension of the input (degenerates to a copy).
5397 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5398 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // The high part is just a zero.
5399 } else {
5400 // For example, extension of an i48 to an i64. The operand type necessarily
5401 // promotes to the result type, so will end up being expanded too.
5402 assert(getTypeAction(Op.getValueType()) ==
5403 TargetLowering::TypePromoteInteger &&
5404 "Only know how to promote this result!");
5405 SDValue Res = GetPromotedInteger(Op);
5406 assert(Res.getValueType() == N->getValueType(0) &&
5407 "Operand over promoted?");
5408 // Split the promoted operand. This will simplify when it is expanded.
5409 SplitInteger(Op: Res, Lo, Hi);
5410 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5411 Hi = DAG.getZeroExtendInReg(Op: Hi, DL: dl,
5412 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
5413 BitWidth: ExcessBits));
5414 }
5415}
5416
5417void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
5418 SDValue &Lo, SDValue &Hi) {
5419 SDLoc dl(N);
5420 EVT VT = cast<AtomicSDNode>(Val: N)->getMemoryVT();
5421 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::i1, VT3: MVT::Other);
5422 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
5423 SDValue Swap = DAG.getAtomicCmpSwap(
5424 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
5425 MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(), VTs, Chain: N->getOperand(Num: 0),
5426 Ptr: N->getOperand(Num: 1), Cmp: Zero, Swp: Zero, MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5427
5428 ReplaceValueWith(From: SDValue(N, 0), To: Swap.getValue(R: 0));
5429 ReplaceValueWith(From: SDValue(N, 1), To: Swap.getValue(R: 2));
5430}
5431
5432void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
5433 SDValue &Lo, SDValue &Hi) {
5434 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
5435 // both halves independently.
5436 SDValue Res = TLI.expandVecReduce(Node: N, DAG);
5437 SplitInteger(Op: Res, Lo, Hi);
5438}
5439
5440void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
5441 SDValue &Lo, SDValue &Hi) {
5442 // Delegate to funnel-shift expansion.
5443 SDLoc DL(N);
5444 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR;
5445 SDValue Res = DAG.getNode(Opcode, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
5446 N2: N->getOperand(Num: 0), N3: N->getOperand(Num: 1));
5447 SplitInteger(Op: Res, Lo, Hi);
5448}
5449
5450void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
5451 SDValue &Hi) {
5452 // Values numbered from least significant to most significant.
5453 SDValue In1, In2, In3, In4;
5454 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: In3, Hi&: In4);
5455 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: In1, Hi&: In2);
5456 EVT HalfVT = In1.getValueType();
5457
5458 SDLoc DL(N);
5459 unsigned Opc = N->getOpcode();
5460 SDValue ShAmt = N->getOperand(Num: 2);
5461 EVT ShAmtVT = ShAmt.getValueType();
5462 EVT ShAmtCCVT = getSetCCResultType(VT: ShAmtVT);
5463
5464 // If the shift amount is at least half the bitwidth, swap the inputs.
5465 unsigned HalfVTBits = HalfVT.getScalarSizeInBits();
5466 SDValue AndNode = DAG.getNode(Opcode: ISD::AND, DL, VT: ShAmtVT, N1: ShAmt,
5467 N2: DAG.getConstant(Val: HalfVTBits, DL, VT: ShAmtVT));
5468 SDValue Cond =
5469 DAG.getSetCC(DL, VT: ShAmtCCVT, LHS: AndNode, RHS: DAG.getConstant(Val: 0, DL, VT: ShAmtVT),
5470 Cond: Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ);
5471
5472 // Expand to a pair of funnel shifts.
5473 EVT NewShAmtVT = TLI.getShiftAmountTy(LHSTy: HalfVT, DL: DAG.getDataLayout());
5474 SDValue NewShAmt = DAG.getAnyExtOrTrunc(Op: ShAmt, DL, VT: NewShAmtVT);
5475
5476 SDValue Select1 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In1, N3: In2);
5477 SDValue Select2 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In2, N3: In3);
5478 SDValue Select3 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In3, N3: In4);
5479 Lo = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select2, N2: Select1, N3: NewShAmt);
5480 Hi = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select3, N2: Select2, N3: NewShAmt);
5481}
5482
5483void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo, SDValue &Hi) {
5484 if (N->getOpcode() != ISD::CLMUL) {
5485 SDValue Res = TLI.expandCLMUL(N, DAG);
5486 return SplitInteger(Op: Res, Lo, Hi);
5487 }
5488
5489 SDValue LL, LH, RL, RH;
5490 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
5491 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
5492 EVT HalfVT = LL.getValueType();
5493 SDLoc DL(N);
5494
5495 // The low bits are a direct CLMUL of the the low bits.
5496 Lo = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RL);
5497
5498 // We compute two Hi-Lo cross-products, XOR them, and XOR it with the overflow
5499 // of the CLMUL of the low bits (given by CLMULH of the low bits) to yield the
5500 // final high bits.
5501 SDValue LoH = DAG.getNode(Opcode: ISD::CLMULH, DL, VT: HalfVT, N1: LL, N2: RL);
5502 SDValue HiLoCross1 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RH);
5503 SDValue HiLoCross2 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LH, N2: RL);
5504 SDValue HiLoCross = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: HiLoCross1, N2: HiLoCross2);
5505 Hi = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: LoH, N2: HiLoCross);
5506}
5507
5508void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
5509 SDValue &Hi) {
5510 EVT VT = N->getValueType(ResNo: 0);
5511 EVT HalfVT =
5512 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: N->getValueSizeInBits(ResNo: 0) / 2);
5513 SDLoc dl(N);
5514
5515 // We assume VSCALE(1) fits into a legal integer.
5516 APInt One(HalfVT.getSizeInBits(), 1);
5517 SDValue VScaleBase = DAG.getVScale(DL: dl, VT: HalfVT, MulImm: One);
5518 VScaleBase = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: VScaleBase);
5519 SDValue Res = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: VScaleBase, N2: N->getOperand(Num: 0));
5520 SplitInteger(Op: Res, Lo, Hi);
5521}
5522
5523void DAGTypeLegalizer::ExpandIntRes_READ_REGISTER(SDNode *N, SDValue &Lo,
5524 SDValue &Hi) {
5525 const Function &Fn = DAG.getMachineFunction().getFunction();
5526 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
5527 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
5528 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
5529 EVT LoVT, HiVT;
5530 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: N->getValueType(ResNo: 0));
5531 Lo = DAG.getPOISON(VT: LoVT);
5532 Hi = DAG.getPOISON(VT: HiVT);
5533}
5534
5535//===----------------------------------------------------------------------===//
5536// Integer Operand Expansion
5537//===----------------------------------------------------------------------===//
5538
5539/// ExpandIntegerOperand - This method is called when the specified operand of
5540/// the specified node is found to need expansion. At this point, all of the
5541/// result types of the node are known to be legal, but other operands of the
5542/// node may need promotion or expansion as well as the specified one.
5543bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
5544 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG));
5545 SDValue Res = SDValue();
5546
5547 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false))
5548 return false;
5549
5550 switch (N->getOpcode()) {
5551 default:
5552 #ifndef NDEBUG
5553 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
5554 N->dump(&DAG); dbgs() << "\n";
5555 #endif
5556 report_fatal_error(reason: "Do not know how to expand this operator's operand!");
5557
5558 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
5559 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
5560 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
5561 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
5562 case ISD::FAKE_USE:
5563 Res = ExpandOp_FAKE_USE(N);
5564 break;
5565 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
5566 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
5567 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
5568 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
5569 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
5570 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
5571 case ISD::STRICT_SINT_TO_FP:
5572 case ISD::SINT_TO_FP:
5573 case ISD::STRICT_UINT_TO_FP:
5574 case ISD::UINT_TO_FP: Res = ExpandIntOp_XINT_TO_FP(N); break;
5575 case ISD::STORE: Res = ExpandIntOp_STORE(N: cast<StoreSDNode>(Val: N), OpNo); break;
5576 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
5577
5578 case ISD::SHL:
5579 case ISD::SRA:
5580 case ISD::SRL:
5581 case ISD::ROTL:
5582 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
5583 case ISD::RETURNADDR:
5584 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
5585
5586 case ISD::SCMP:
5587 case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
5588
5589 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
5590 case ISD::STACKMAP:
5591 Res = ExpandIntOp_STACKMAP(N, OpNo);
5592 break;
5593 case ISD::PATCHPOINT:
5594 Res = ExpandIntOp_PATCHPOINT(N, OpNo);
5595 break;
5596 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
5597 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
5598 Res = ExpandIntOp_VP_STRIDED(N, OpNo);
5599 break;
5600 case ISD::WRITE_REGISTER:
5601 Res = ExpandIntOp_WRITE_REGISTER(N, OpNo);
5602 break;
5603 }
5604
5605 // If the result is null, the sub-method took care of registering results etc.
5606 if (!Res.getNode()) return false;
5607
5608 // If the result is N, the sub-method updated N in place. Tell the legalizer
5609 // core about this.
5610 if (Res.getNode() == N)
5611 return true;
5612
5613 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
5614 "Invalid operand expansion");
5615
5616 ReplaceValueWith(From: SDValue(N, 0), To: Res);
5617 return false;
5618}
5619
5620/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
5621/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
5622void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
5623 SDValue &NewRHS,
5624 ISD::CondCode &CCCode,
5625 const SDLoc &dl) {
5626 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5627 GetExpandedInteger(Op: NewLHS, Lo&: LHSLo, Hi&: LHSHi);
5628 GetExpandedInteger(Op: NewRHS, Lo&: RHSLo, Hi&: RHSHi);
5629
5630 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
5631 if (RHSLo == RHSHi && isAllOnesConstant(V: RHSLo)) {
5632 // Equality comparison to -1.
5633 NewLHS = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: LHSHi);
5634 NewRHS = RHSLo;
5635 return;
5636 }
5637
5638 NewLHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: RHSLo);
5639 NewRHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSHi, N2: RHSHi);
5640 NewLHS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NewLHS.getValueType(), N1: NewLHS, N2: NewRHS);
5641 NewRHS = DAG.getConstant(Val: 0, DL: dl, VT: NewLHS.getValueType());
5642 return;
5643 }
5644
5645 // If this is a comparison of the sign bit, just look at the top part.
5646 // X > -1, x < 0
5647 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Val&: NewRHS))
5648 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0
5649 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1
5650 NewLHS = LHSHi;
5651 NewRHS = RHSHi;
5652 return;
5653 }
5654
5655 // FIXME: This generated code sucks.
5656 ISD::CondCode LowCC;
5657 switch (CCCode) {
5658 default: llvm_unreachable("Unknown integer setcc!");
5659 case ISD::SETLT:
5660 case ISD::SETULT: LowCC = ISD::SETULT; break;
5661 case ISD::SETGT:
5662 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5663 case ISD::SETLE:
5664 case ISD::SETULE: LowCC = ISD::SETULE; break;
5665 case ISD::SETGE:
5666 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5667 }
5668
5669 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
5670 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
5671 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
5672
5673 // NOTE: on targets without efficient SELECT of bools, we can always use
5674 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5675 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
5676 nullptr);
5677 SDValue LoCmp, HiCmp;
5678 if (TLI.isTypeLegal(VT: LHSLo.getValueType()) &&
5679 TLI.isTypeLegal(VT: RHSLo.getValueType()))
5680 LoCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSLo.getValueType()), N0: LHSLo,
5681 N1: RHSLo, Cond: LowCC, foldBooleans: false, DCI&: DagCombineInfo, dl);
5682 if (!LoCmp.getNode())
5683 LoCmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LHSLo.getValueType()), LHS: LHSLo,
5684 RHS: RHSLo, Cond: LowCC);
5685 if (TLI.isTypeLegal(VT: LHSHi.getValueType()) &&
5686 TLI.isTypeLegal(VT: RHSHi.getValueType()))
5687 HiCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSHi.getValueType()), N0: LHSHi,
5688 N1: RHSHi, Cond: CCCode, foldBooleans: false, DCI&: DagCombineInfo, dl);
5689 if (!HiCmp.getNode())
5690 HiCmp =
5691 DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: getSetCCResultType(VT: LHSHi.getValueType()),
5692 N1: LHSHi, N2: RHSHi, N3: DAG.getCondCode(Cond: CCCode));
5693
5694 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(Val: LoCmp.getNode());
5695 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(Val: HiCmp.getNode());
5696
5697 bool EqAllowed = ISD::isTrueWhenEqual(Cond: CCCode);
5698
5699 // FIXME: Is the HiCmpC->isOne() here correct for
5700 // ZeroOrNegativeOneBooleanContent.
5701 if ((EqAllowed && (HiCmpC && HiCmpC->isZero())) ||
5702 (!EqAllowed &&
5703 ((HiCmpC && HiCmpC->isOne()) || (LoCmpC && LoCmpC->isZero())))) {
5704 // For LE / GE, if high part is known false, ignore the low part.
5705 // For LT / GT: if low part is known false, return the high part.
5706 // if high part is known true, ignore the low part.
5707 NewLHS = HiCmp;
5708 NewRHS = SDValue();
5709 return;
5710 }
5711
5712 if (LHSHi == RHSHi) {
5713 // Comparing the low bits is enough.
5714 NewLHS = LoCmp;
5715 NewRHS = SDValue();
5716 return;
5717 }
5718
5719 // Lower with SETCCCARRY if the target supports it.
5720 EVT HiVT = LHSHi.getValueType();
5721 EVT ExpandVT = TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: HiVT);
5722 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(Op: ISD::SETCCCARRY, VT: ExpandVT);
5723
5724 // FIXME: Make all targets support this, then remove the other lowering.
5725 if (HasSETCCCARRY) {
5726 // SETCCCARRY can detect < and >= directly. For > and <=, flip
5727 // operands and condition code.
5728 bool FlipOperands = false;
5729 switch (CCCode) {
5730 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
5731 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
5732 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
5733 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
5734 default: break;
5735 }
5736 if (FlipOperands) {
5737 std::swap(a&: LHSLo, b&: RHSLo);
5738 std::swap(a&: LHSHi, b&: RHSHi);
5739 }
5740 // Perform a wide subtraction, feeding the carry from the low part into
5741 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
5742 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
5743 // zero or positive iff LHS >= RHS.
5744 EVT LoVT = LHSLo.getValueType();
5745 SDVTList VTList = DAG.getVTList(VT1: LoVT, VT2: getSetCCResultType(VT: LoVT));
5746 SDValue LowCmp = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: LHSLo, N2: RHSLo);
5747 SDValue Res = DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: getSetCCResultType(VT: HiVT),
5748 N1: LHSHi, N2: RHSHi, N3: LowCmp.getValue(R: 1),
5749 N4: DAG.getCondCode(Cond: CCCode));
5750 NewLHS = Res;
5751 NewRHS = SDValue();
5752 return;
5753 }
5754
5755 NewLHS = TLI.SimplifySetCC(VT: getSetCCResultType(VT: HiVT), N0: LHSHi, N1: RHSHi, Cond: ISD::SETEQ,
5756 foldBooleans: false, DCI&: DagCombineInfo, dl);
5757 if (!NewLHS.getNode())
5758 NewLHS =
5759 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: HiVT), LHS: LHSHi, RHS: RHSHi, Cond: ISD::SETEQ);
5760 NewLHS = DAG.getSelect(DL: dl, VT: LoCmp.getValueType(), Cond: NewLHS, LHS: LoCmp, RHS: HiCmp);
5761 NewRHS = SDValue();
5762}
5763
5764SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
5765 SDValue NewLHS = N->getOperand(Num: 2), NewRHS = N->getOperand(Num: 3);
5766 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get();
5767 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5768
5769 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5770 // against zero to select between true and false values.
5771 if (!NewRHS.getNode()) {
5772 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5773 CCCode = ISD::SETNE;
5774 }
5775
5776 // Update N to have the operands specified.
5777 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
5778 Op2: DAG.getCondCode(Cond: CCCode), Op3: NewLHS, Op4: NewRHS,
5779 Op5: N->getOperand(Num: 4)), 0);
5780}
5781
5782SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
5783 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5784 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
5785 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5786
5787 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5788 // against zero to select between true and false values.
5789 if (!NewRHS.getNode()) {
5790 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5791 CCCode = ISD::SETNE;
5792 }
5793
5794 // Update N to have the operands specified.
5795 return SDValue(DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS,
5796 Op3: N->getOperand(Num: 2), Op4: N->getOperand(Num: 3),
5797 Op5: DAG.getCondCode(Cond: CCCode)), 0);
5798}
5799
5800SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
5801 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5802 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
5803 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5804
5805 // If ExpandSetCCOperands returned a scalar, use it.
5806 if (!NewRHS.getNode()) {
5807 assert(NewLHS.getValueType() == N->getValueType(0) &&
5808 "Unexpected setcc expansion!");
5809 return NewLHS;
5810 }
5811
5812 // Otherwise, update N to have the operands specified.
5813 return SDValue(
5814 DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS, Op3: DAG.getCondCode(Cond: CCCode)), 0);
5815}
5816
5817SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
5818 SDValue LHS = N->getOperand(Num: 0);
5819 SDValue RHS = N->getOperand(Num: 1);
5820 SDValue Carry = N->getOperand(Num: 2);
5821 SDValue Cond = N->getOperand(Num: 3);
5822 SDLoc dl = SDLoc(N);
5823
5824 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5825 GetExpandedInteger(Op: LHS, Lo&: LHSLo, Hi&: LHSHi);
5826 GetExpandedInteger(Op: RHS, Lo&: RHSLo, Hi&: RHSHi);
5827
5828 // Expand to a USUBO_CARRY for the low part and a SETCCCARRY for the high.
5829 SDVTList VTList = DAG.getVTList(VT1: LHSLo.getValueType(), VT2: Carry.getValueType());
5830 SDValue LowCmp =
5831 DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: LHSLo, N2: RHSLo, N3: Carry);
5832 return DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: N->getValueType(ResNo: 0), N1: LHSHi, N2: RHSHi,
5833 N3: LowCmp.getValue(R: 1), N4: Cond);
5834}
5835
5836SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
5837 // Split the operand and replace with SPLAT_VECTOR_PARTS.
5838 SDValue Lo, Hi;
5839 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5840 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Lo,
5841 N2: Hi);
5842}
5843
5844SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
5845 // The value being shifted is legal, but the shift amount is too big.
5846 // It follows that either the result of the shift is undefined, or the
5847 // upper half of the shift amount is zero. Just use the lower half.
5848 SDValue Lo, Hi;
5849 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo, Hi);
5850 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Lo), 0);
5851}
5852
5853SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
5854 return TLI.expandCMP(Node: N, DAG);
5855}
5856
5857SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
5858 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
5859 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
5860 // constant to valid type.
5861 SDValue Lo, Hi;
5862 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5863 return SDValue(DAG.UpdateNodeOperands(N, Op: Lo), 0);
5864}
5865
5866SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) {
5867 bool IsStrict = N->isStrictFPOpcode();
5868 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
5869 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
5870 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
5871 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
5872 EVT DstVT = N->getValueType(ResNo: 0);
5873 RTLIB::Libcall LC = IsSigned ? RTLIB::getSINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT)
5874 : RTLIB::getUINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT);
5875 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
5876 "Don't know how to expand this XINT_TO_FP!");
5877 TargetLowering::MakeLibCallOptions CallOptions;
5878 CallOptions.setIsSigned(true);
5879 std::pair<SDValue, SDValue> Tmp =
5880 TLI.makeLibCall(DAG, LC, RetVT: DstVT, Ops: Op, CallOptions, dl: SDLoc(N), Chain);
5881
5882 if (!IsStrict)
5883 return Tmp.first;
5884
5885 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
5886 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
5887 return SDValue();
5888}
5889
5890SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
5891 assert(!N->isAtomic() && "Should have been a ATOMIC_STORE?");
5892
5893 if (ISD::isNormalStore(N))
5894 return ExpandOp_NormalStore(N, OpNo);
5895
5896 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
5897 assert(OpNo == 1 && "Can only expand the stored value so far");
5898
5899 EVT VT = N->getOperand(Num: 1).getValueType();
5900 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5901 SDValue Ch = N->getChain();
5902 SDValue Ptr = N->getBasePtr();
5903 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
5904 AAMDNodes AAInfo = N->getAAInfo();
5905 SDLoc dl(N);
5906 SDValue Lo, Hi;
5907
5908 assert(NVT.isByteSized() && "Expanded type not byte sized!");
5909
5910 if (N->getMemoryVT().bitsLE(VT: NVT)) {
5911 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
5912 return DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(),
5913 SVT: N->getMemoryVT(), Alignment: N->getBaseAlign(), MMOFlags,
5914 AAInfo);
5915 }
5916
5917 if (DAG.getDataLayout().isLittleEndian()) {
5918 // Little-endian - low bits are at low addresses.
5919 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
5920
5921 Lo = DAG.getStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
5922 MMOFlags, AAInfo);
5923
5924 unsigned ExcessBits =
5925 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
5926 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
5927
5928 // Increment the pointer to the other half.
5929 unsigned IncrementSize = NVT.getSizeInBits()/8;
5930 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
5931 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr,
5932 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
5933 SVT: NEVT, Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
5934 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
5935 }
5936
5937 // Big-endian - high bits are at low addresses. Favor aligned stores at
5938 // the cost of some bit-fiddling.
5939 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
5940
5941 EVT ExtVT = N->getMemoryVT();
5942 unsigned EBytes = ExtVT.getStoreSize();
5943 unsigned IncrementSize = NVT.getSizeInBits()/8;
5944 unsigned ExcessBits = (EBytes - IncrementSize)*8;
5945 EVT HiVT = EVT::getIntegerVT(Context&: *DAG.getContext(),
5946 BitWidth: ExtVT.getSizeInBits() - ExcessBits);
5947
5948 if (ExcessBits < NVT.getSizeInBits()) {
5949 // Transfer high bits from the top of Lo to the bottom of Hi.
5950 Hi = DAG.getNode(
5951 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
5952 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
5953 Hi = DAG.getNode(
5954 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Hi,
5955 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Lo,
5956 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
5957 }
5958
5959 // Store both the high bits and maybe some of the low bits.
5960 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr, PtrInfo: N->getPointerInfo(), SVT: HiVT,
5961 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
5962
5963 // Increment the pointer to the other half.
5964 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
5965 // Store the lowest ExcessBits bits in the second half.
5966 Lo = DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr,
5967 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
5968 SVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
5969 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
5970 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
5971}
5972
5973SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
5974 SDValue InL, InH;
5975 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5976 // Just truncate the low part of the source.
5977 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: InL);
5978}
5979
5980SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
5981 SDLoc dl(N);
5982 SDValue Swap =
5983 DAG.getAtomic(Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(),
5984 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 2), Val: N->getOperand(Num: 1),
5985 MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5986 return Swap.getValue(R: 1);
5987}
5988
5989SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
5990 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
5991 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
5992
5993 SDValue Hi; // The upper half is dropped out.
5994 SmallVector<SDValue, 8> NewOps(N->ops());
5995 GetExpandedInteger(Op: NewOps[OpNo], Lo&: NewOps[OpNo], Hi);
5996
5997 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
5998}
5999
6000SDValue DAGTypeLegalizer::ExpandIntOp_WRITE_REGISTER(SDNode *N, unsigned OpNo) {
6001 const Function &Fn = DAG.getMachineFunction().getFunction();
6002 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6003 "cannot use llvm.write_register with illegal type", Fn,
6004 N->getDebugLoc()));
6005
6006 return N->getOperand(Num: 0);
6007}
6008
6009SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
6010 SDLoc dl(N);
6011
6012 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6013 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6014 EVT OutVT = V0.getValueType();
6015
6016 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: OutVT, N1: V0, N2: V1, N3: N->getOperand(Num: 2));
6017}
6018
6019SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(SDNode *N) {
6020 SDLoc DL(N);
6021 unsigned Factor = N->getNumOperands();
6022
6023 SmallVector<SDValue, 8> Ops(Factor);
6024 for (unsigned i = 0; i != Factor; i++)
6025 Ops[i] = GetPromotedInteger(Op: N->getOperand(Num: i));
6026
6027 SmallVector<EVT, 8> ResVTs(Factor, Ops[0].getValueType());
6028 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VTs: ResVTs), Ops);
6029
6030 for (unsigned i = 0; i != Factor; i++)
6031 SetPromotedInteger(Op: SDValue(N, i), Result: Res.getValue(R: i));
6032
6033 return SDValue();
6034}
6035
6036SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
6037
6038 EVT OutVT = N->getValueType(ResNo: 0);
6039 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6040 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6041 EVT NOutVTElem = NOutVT.getVectorElementType();
6042
6043 SDLoc dl(N);
6044 SDValue BaseIdx = N->getOperand(Num: 1);
6045
6046 // TODO: We may be able to use this for types other than scalable
6047 // vectors and fix those tests that expect BUILD_VECTOR to be used
6048 if (OutVT.isScalableVector()) {
6049 SDValue InOp0 = N->getOperand(Num: 0);
6050 EVT InVT = InOp0.getValueType();
6051
6052 // Try and extract from a smaller type so that it eventually falls
6053 // into the promotion code below.
6054 if (getTypeAction(VT: InVT) == TargetLowering::TypeSplitVector ||
6055 getTypeAction(VT: InVT) == TargetLowering::TypeLegal) {
6056 EVT NInVT = InVT.getHalfNumVectorElementsVT(Context&: *DAG.getContext());
6057 unsigned NElts = NInVT.getVectorMinNumElements();
6058 uint64_t IdxVal = BaseIdx->getAsZExtVal();
6059
6060 SDValue Step1 = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NInVT, N1: InOp0,
6061 N2: DAG.getConstant(Val: alignDown(Value: IdxVal, Align: NElts), DL: dl,
6062 VT: BaseIdx.getValueType()));
6063 SDValue Step2 = DAG.getNode(
6064 Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Step1,
6065 N2: DAG.getConstant(Val: IdxVal % NElts, DL: dl, VT: BaseIdx.getValueType()));
6066 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Step2);
6067 }
6068
6069 // Try and extract from a widened type.
6070 if (getTypeAction(VT: InVT) == TargetLowering::TypeWidenVector) {
6071 SDValue Ops[] = {GetWidenedVector(Op: InOp0), BaseIdx};
6072 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: OutVT, Ops);
6073 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6074 }
6075
6076 // Promote operands and see if this is handled by target lowering,
6077 // Otherwise, use the BUILD_VECTOR approach below
6078 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
6079 // Collect the (promoted) operands
6080 SDValue Ops[] = { GetPromotedInteger(Op: InOp0), BaseIdx };
6081
6082 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
6083 assert(PromEltVT.bitsLE(NOutVTElem) &&
6084 "Promoted operand has an element type greater than result");
6085
6086 EVT ExtVT = NOutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: PromEltVT);
6087 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: ExtVT, Ops);
6088 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6089 }
6090 }
6091
6092 if (OutVT.isScalableVector())
6093 report_fatal_error(reason: "Unable to promote scalable types using BUILD_VECTOR");
6094
6095 SDValue InOp0 = N->getOperand(Num: 0);
6096 if (getTypeAction(VT: InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
6097 InOp0 = GetPromotedInteger(Op: InOp0);
6098
6099 EVT InVT = InOp0.getValueType();
6100 EVT InSVT = InVT.getVectorElementType();
6101
6102 unsigned OutNumElems = OutVT.getVectorNumElements();
6103 SmallVector<SDValue, 8> Ops;
6104 Ops.reserve(N: OutNumElems);
6105 for (unsigned i = 0; i != OutNumElems; ++i) {
6106 // Extract the element from the original vector.
6107 SDValue Index = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: BaseIdx.getValueType(), N1: BaseIdx,
6108 N2: DAG.getConstant(Val: i, DL: dl, VT: BaseIdx.getValueType()));
6109 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: InSVT,
6110 N1: N->getOperand(Num: 0), N2: Index);
6111 SDValue Op = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NOutVTElem);
6112 // Insert the converted element to the new vector.
6113 Ops.push_back(Elt: Op);
6114 }
6115
6116 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6117}
6118
6119SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
6120 EVT OutVT = N->getValueType(ResNo: 0);
6121 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6122 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6123
6124 SDLoc dl(N);
6125 SDValue Vec = N->getOperand(Num: 0);
6126 SDValue SubVec = N->getOperand(Num: 1);
6127 SDValue Idx = N->getOperand(Num: 2);
6128
6129 EVT SubVecVT = SubVec.getValueType();
6130 EVT NSubVT =
6131 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NOutVT.getVectorElementType(),
6132 EC: SubVecVT.getVectorElementCount());
6133
6134 Vec = GetPromotedInteger(Op: Vec);
6135 SubVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NSubVT, Operand: SubVec);
6136
6137 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: NOutVT, N1: Vec, N2: SubVec, N3: Idx);
6138}
6139
6140SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
6141 SDLoc dl(N);
6142
6143 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6144 EVT OutVT = V0.getValueType();
6145
6146 return DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL: dl, VT: OutVT, Operand: V0);
6147}
6148
6149SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
6150 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(Val: N);
6151 EVT VT = N->getValueType(ResNo: 0);
6152 SDLoc dl(N);
6153
6154 ArrayRef<int> NewMask = SV->getMask().slice(N: 0, M: VT.getVectorNumElements());
6155
6156 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6157 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6158 EVT OutVT = V0.getValueType();
6159
6160 return DAG.getVectorShuffle(VT: OutVT, dl, N1: V0, N2: V1, Mask: NewMask);
6161}
6162
6163SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
6164 EVT OutVT = N->getValueType(ResNo: 0);
6165 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6166 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6167 unsigned NumElems = N->getNumOperands();
6168 EVT NOutVTElem = NOutVT.getVectorElementType();
6169 TargetLoweringBase::BooleanContent NOutBoolType = TLI.getBooleanContents(Type: NOutVT);
6170 unsigned NOutExtOpc = TargetLowering::getExtendForContent(Content: NOutBoolType);
6171 SDLoc dl(N);
6172
6173 SmallVector<SDValue, 8> Ops;
6174 Ops.reserve(N: NumElems);
6175 for (unsigned i = 0; i != NumElems; ++i) {
6176 SDValue Op = N->getOperand(Num: i);
6177 EVT OpVT = Op.getValueType();
6178 // BUILD_VECTOR integer operand types are allowed to be larger than the
6179 // result's element type. This may still be true after the promotion. For
6180 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
6181 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
6182 if (OpVT.bitsLT(VT: NOutVTElem)) {
6183 unsigned ExtOpc = ISD::ANY_EXTEND;
6184 // Attempt to extend constant bool vectors to match target's BooleanContent.
6185 // While not necessary, this improves chances of the constant correctly
6186 // folding with compare results (e.g. for NOT patterns).
6187 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant)
6188 ExtOpc = NOutExtOpc;
6189 Op = DAG.getNode(Opcode: ExtOpc, DL: dl, VT: NOutVTElem, Operand: Op);
6190 }
6191 Ops.push_back(Elt: Op);
6192 }
6193
6194 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6195}
6196
6197SDValue DAGTypeLegalizer::PromoteIntRes_ScalarOp(SDNode *N) {
6198
6199 SDLoc dl(N);
6200
6201 assert(!N->getOperand(0).getValueType().isVector() &&
6202 "Input must be a scalar");
6203
6204 EVT OutVT = N->getValueType(ResNo: 0);
6205 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6206 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6207 EVT NOutElemVT = NOutVT.getVectorElementType();
6208
6209 SDValue Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutElemVT, Operand: N->getOperand(Num: 0));
6210 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NOutVT, Operand: Op);
6211}
6212
6213SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
6214 SDLoc dl(N);
6215 EVT OutVT = N->getValueType(ResNo: 0);
6216 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6217 assert(NOutVT.isScalableVector() &&
6218 "Type must be promoted to a scalable vector type");
6219 const APInt &StepVal = N->getConstantOperandAPInt(Num: 0);
6220 return DAG.getStepVector(DL: dl, ResVT: NOutVT,
6221 StepVal: StepVal.sext(width: NOutVT.getScalarSizeInBits()));
6222}
6223
6224SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
6225 SDLoc dl(N);
6226
6227 EVT OutVT = N->getValueType(ResNo: 0);
6228 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6229 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6230
6231 unsigned NumOperands = N->getNumOperands();
6232 unsigned NumOutElem = NOutVT.getVectorMinNumElements();
6233 EVT OutElemTy = NOutVT.getVectorElementType();
6234 if (OutVT.isScalableVector()) {
6235 // Find the largest promoted element type for each of the operands.
6236 SDUse *MaxSizedValue = std::max_element(
6237 first: N->op_begin(), last: N->op_end(), comp: [](const SDValue &A, const SDValue &B) {
6238 EVT AVT = A.getValueType().getVectorElementType();
6239 EVT BVT = B.getValueType().getVectorElementType();
6240 return AVT.getScalarSizeInBits() < BVT.getScalarSizeInBits();
6241 });
6242 EVT MaxElementVT = MaxSizedValue->getValueType().getVectorElementType();
6243
6244 // Then promote all vectors to the largest element type.
6245 SmallVector<SDValue, 8> Ops;
6246 for (unsigned I = 0; I < NumOperands; ++I) {
6247 SDValue Op = N->getOperand(Num: I);
6248 EVT OpVT = Op.getValueType();
6249 if (getTypeAction(VT: OpVT) == TargetLowering::TypePromoteInteger)
6250 Op = GetPromotedInteger(Op);
6251 else
6252 assert(getTypeAction(OpVT) == TargetLowering::TypeLegal &&
6253 "Unhandled legalization type");
6254
6255 if (OpVT.getVectorElementType().getScalarSizeInBits() <
6256 MaxElementVT.getScalarSizeInBits())
6257 Op = DAG.getAnyExtOrTrunc(
6258 Op, DL: dl,
6259 VT: OpVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT));
6260 Ops.push_back(Elt: Op);
6261 }
6262
6263 // Do the CONCAT on the promoted type and finally truncate to (the promoted)
6264 // NOutVT.
6265 return DAG.getAnyExtOrTrunc(
6266 Op: DAG.getNode(
6267 Opcode: ISD::CONCAT_VECTORS, DL: dl,
6268 VT: OutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT),
6269 Ops),
6270 DL: dl, VT: NOutVT);
6271 }
6272
6273 unsigned NumElem = N->getOperand(Num: 0).getValueType().getVectorNumElements();
6274 assert(NumElem * NumOperands == NumOutElem &&
6275 "Unexpected number of elements");
6276
6277 // Take the elements from the first vector.
6278 SmallVector<SDValue, 8> Ops(NumOutElem);
6279 for (unsigned i = 0; i < NumOperands; ++i) {
6280 SDValue Op = N->getOperand(Num: i);
6281 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypePromoteInteger)
6282 Op = GetPromotedInteger(Op);
6283 EVT SclrTy = Op.getValueType().getVectorElementType();
6284 assert(NumElem == Op.getValueType().getVectorNumElements() &&
6285 "Unexpected number of elements");
6286
6287 for (unsigned j = 0; j < NumElem; ++j) {
6288 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Op,
6289 N2: DAG.getVectorIdxConstant(Val: j, DL: dl));
6290 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: OutElemTy);
6291 }
6292 }
6293
6294 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6295}
6296
6297SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
6298 EVT VT = N->getValueType(ResNo: 0);
6299 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6300 assert(NVT.isVector() && "This type must be promoted to a vector type");
6301
6302 SDLoc dl(N);
6303
6304 // For operands whose TypeAction is to promote, extend the promoted node
6305 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
6306 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
6307 // type..
6308 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
6309 == TargetLowering::TypePromoteInteger) {
6310 SDValue Promoted;
6311
6312 switch(N->getOpcode()) {
6313 case ISD::SIGN_EXTEND_VECTOR_INREG:
6314 Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
6315 break;
6316 case ISD::ZERO_EXTEND_VECTOR_INREG:
6317 Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
6318 break;
6319 case ISD::ANY_EXTEND_VECTOR_INREG:
6320 Promoted = GetPromotedInteger(Op: N->getOperand(Num: 0));
6321 break;
6322 default:
6323 llvm_unreachable("Node has unexpected Opcode");
6324 }
6325 unsigned NewSize = NVT.getSizeInBits();
6326 if (Promoted.getValueType().getSizeInBits() > NewSize) {
6327 EVT ExtractVT = EVT::getVectorVT(
6328 Context&: *DAG.getContext(), VT: Promoted.getValueType().getVectorElementType(),
6329 NumElements: NewSize / Promoted.getScalarValueSizeInBits());
6330
6331 Promoted = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: ExtractVT, N1: Promoted,
6332 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
6333 }
6334 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Promoted);
6335 }
6336
6337 // Directly extend to the appropriate transform-to type.
6338 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
6339}
6340
6341SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(SDNode *N) {
6342 EVT VT = N->getValueType(ResNo: 0);
6343 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6344 return DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6345}
6346
6347SDValue DAGTypeLegalizer::PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
6348 EVT VT = N->getValueType(ResNo: 0);
6349 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6350 return DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6351}
6352
6353SDValue DAGTypeLegalizer::PromoteIntRes_PARTIAL_REDUCE_MLA(SDNode *N) {
6354 SDLoc DL(N);
6355 EVT VT = N->getValueType(ResNo: 0);
6356 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6357 SDValue ExtAcc = GetPromotedInteger(Op: N->getOperand(Num: 0));
6358 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: ExtAcc, N2: N->getOperand(Num: 1),
6359 N3: N->getOperand(Num: 2));
6360}
6361
6362SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
6363 EVT OutVT = N->getValueType(ResNo: 0);
6364 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6365 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6366
6367 EVT NOutVTElem = NOutVT.getVectorElementType();
6368
6369 SDLoc dl(N);
6370 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6371
6372 SDValue ConvElem = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6373 VT: NOutVTElem, Operand: N->getOperand(Num: 1));
6374 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NOutVT,
6375 N1: V0, N2: ConvElem, N3: N->getOperand(Num: 2));
6376}
6377
6378SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
6379 // The VECREDUCE result size may be larger than the element size, so
6380 // we can simply change the result type.
6381 SDLoc dl(N);
6382 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6383 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Ops: N->ops());
6384}
6385
6386SDValue DAGTypeLegalizer::PromoteIntRes_VP_REDUCE(SDNode *N) {
6387 // The VP_REDUCE result size may be larger than the element size, so we can
6388 // simply change the result type. However the start value and result must be
6389 // the same.
6390 SDLoc DL(N);
6391 SDValue Start = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
6392 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: Start.getValueType(), N1: Start,
6393 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
6394}
6395
6396SDValue DAGTypeLegalizer::PromoteIntRes_PATCHPOINT(SDNode *N) {
6397 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6398 SDLoc dl(N);
6399
6400 assert(N->getNumValues() == 3 && "Expected 3 values for PATCHPOINT");
6401 SDVTList VTList = DAG.getVTList(VTs: {NVT, MVT::Other, MVT::Glue});
6402
6403 SmallVector<SDValue> Ops(N->ops());
6404 SDValue Res = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList, Ops);
6405
6406 // Replace chain and glue uses with the new patchpoint.
6407 SDValue From[] = {SDValue(N, 1), SDValue(N, 2)};
6408 SDValue To[] = {Res.getValue(R: 1), Res.getValue(R: 2)};
6409 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
6410
6411 return Res.getValue(R: 0);
6412}
6413
6414SDValue DAGTypeLegalizer::PromoteIntRes_READ_REGISTER(SDNode *N) {
6415 const Function &Fn = DAG.getMachineFunction().getFunction();
6416 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6417 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
6418
6419 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6420 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
6421 return DAG.getPOISON(VT: NVT);
6422}
6423
6424SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
6425 SDLoc dl(N);
6426 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6427 SDValue V1 = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl,
6428 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
6429 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl,
6430 VT: V0->getValueType(ResNo: 0).getScalarType(), N1: V0, N2: V1);
6431
6432 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
6433 // element types. If this is the case then we need to expand the outgoing
6434 // value and not truncate it.
6435 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6436}
6437
6438SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_SUBVECTOR(SDNode *N) {
6439 SDLoc dl(N);
6440 // The result type is equal to the first input operand's type, so the
6441 // type that needs promoting must be the second source vector.
6442 SDValue V0 = N->getOperand(Num: 0);
6443 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6444 SDValue Idx = N->getOperand(Num: 2);
6445 EVT PromVT = EVT::getVectorVT(Context&: *DAG.getContext(),
6446 VT: V1.getValueType().getVectorElementType(),
6447 EC: V0.getValueType().getVectorElementCount());
6448 V0 = DAG.getAnyExtOrTrunc(Op: V0, DL: dl, VT: PromVT);
6449 SDValue Ext = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: PromVT, N1: V0, N2: V1, N3: Idx);
6450 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6451}
6452
6453// FIXME: We wouldn't need this if clang could promote short integers
6454// that are arguments to FAKE_USE.
6455SDValue DAGTypeLegalizer::PromoteIntOp_FAKE_USE(SDNode *N) {
6456 SDLoc dl(N);
6457 SDValue V0 = N->getOperand(Num: 0);
6458 SDValue V1 = N->getOperand(Num: 1);
6459 EVT InVT1 = V1.getValueType();
6460 SDValue VPromoted =
6461 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6462 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT1), Operand: V1);
6463 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: N->getValueType(ResNo: 0), N1: V0, N2: VPromoted);
6464}
6465
6466SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
6467 SDLoc dl(N);
6468 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6469 MVT InVT = V0.getValueType().getSimpleVT();
6470 MVT OutVT = MVT::getVectorVT(VT: InVT.getVectorElementType(),
6471 NumElements: N->getValueType(ResNo: 0).getVectorNumElements());
6472 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: V0, N2: N->getOperand(Num: 1));
6473 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Ext);
6474}
6475
6476SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
6477 SDLoc dl(N);
6478
6479 EVT ResVT = N->getValueType(ResNo: 0);
6480 unsigned NumElems = N->getNumOperands();
6481
6482 if (ResVT.isScalableVector()) {
6483 SDValue ResVec = DAG.getUNDEF(VT: ResVT);
6484
6485 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
6486 SDValue Op = N->getOperand(Num: OpIdx);
6487 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
6488 ResVec = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: ResVT, N1: ResVec, N2: Op,
6489 N3: DAG.getIntPtrConstant(Val: OpIdx * OpNumElts, DL: dl));
6490 }
6491
6492 return ResVec;
6493 }
6494
6495 EVT RetSclrTy = N->getValueType(ResNo: 0).getVectorElementType();
6496
6497 SmallVector<SDValue, 8> NewOps;
6498 NewOps.reserve(N: NumElems);
6499
6500 // For each incoming vector
6501 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
6502 SDValue Incoming = GetPromotedInteger(Op: N->getOperand(Num: VecIdx));
6503 EVT SclrTy = Incoming->getValueType(ResNo: 0).getVectorElementType();
6504 unsigned NumElem = Incoming->getValueType(ResNo: 0).getVectorNumElements();
6505
6506 for (unsigned i=0; i<NumElem; ++i) {
6507 // Extract element from incoming vector
6508 SDValue Ex = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Incoming,
6509 N2: DAG.getVectorIdxConstant(Val: i, DL: dl));
6510 SDValue Tr = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RetSclrTy, Operand: Ex);
6511 NewOps.push_back(Elt: Tr);
6512 }
6513 }
6514
6515 return DAG.getBuildVector(VT: N->getValueType(ResNo: 0), DL: dl, Ops: NewOps);
6516}
6517
6518SDValue DAGTypeLegalizer::ExpandIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
6519 assert(OpNo > 1);
6520 SDValue Op = N->getOperand(Num: OpNo);
6521
6522 // FIXME: Non-constant operands are not yet handled:
6523 // - https://github.com/llvm/llvm-project/issues/26431
6524 // - https://github.com/llvm/llvm-project/issues/55957
6525 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6526 if (!CN)
6527 return SDValue();
6528
6529 // Copy operands before the one being expanded.
6530 SmallVector<SDValue> NewOps;
6531 for (unsigned I = 0; I < OpNo; I++)
6532 NewOps.push_back(Elt: N->getOperand(Num: I));
6533
6534 EVT Ty = Op.getValueType();
6535 SDLoc DL = SDLoc(N);
6536 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6537 NewOps.push_back(
6538 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6539 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6540 } else {
6541 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6542 return SDValue();
6543 }
6544
6545 // Copy remaining operands.
6546 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6547 NewOps.push_back(Elt: N->getOperand(Num: I));
6548
6549 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6550
6551 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6552 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6553
6554 return SDValue(); // Signal that we have replaced the node already.
6555}
6556
6557SDValue DAGTypeLegalizer::ExpandIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
6558 assert(OpNo >= 7);
6559 SDValue Op = N->getOperand(Num: OpNo);
6560
6561 // FIXME: Non-constant operands are not yet handled:
6562 // - https://github.com/llvm/llvm-project/issues/26431
6563 // - https://github.com/llvm/llvm-project/issues/55957
6564 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6565 if (!CN)
6566 return SDValue();
6567
6568 // Copy operands before the one being expanded.
6569 SmallVector<SDValue> NewOps;
6570 for (unsigned I = 0; I < OpNo; I++)
6571 NewOps.push_back(Elt: N->getOperand(Num: I));
6572
6573 EVT Ty = Op.getValueType();
6574 SDLoc DL = SDLoc(N);
6575 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6576 NewOps.push_back(
6577 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6578 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6579 } else {
6580 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6581 return SDValue();
6582 }
6583
6584 // Copy remaining operands.
6585 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6586 NewOps.push_back(Elt: N->getOperand(Num: I));
6587
6588 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6589
6590 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6591 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6592
6593 return SDValue(); // Signal that we have replaced the node already.
6594}
6595