1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetLowering.h"
24#include "llvm/IR/DerivedTypes.h"
25#include "llvm/IR/DiagnosticInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/KnownBits.h"
28#include "llvm/Support/raw_ostream.h"
29#include <algorithm>
30using namespace llvm;
31
32#define DEBUG_TYPE "legalize-types"
33
34//===----------------------------------------------------------------------===//
35// Integer Result Promotion
36//===----------------------------------------------------------------------===//
37
38/// PromoteIntegerResult - This method is called when a result of a node is
39/// found to be in need of promotion to a larger type. At this point, the node
40/// may also have invalid operands or may have other results that need
41/// expansion, we just know that (at least) one result needs promotion.
42void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
43 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG));
44 SDValue Res = SDValue();
45
46 // See if the target wants to custom expand this node.
47 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true)) {
48 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
49 return;
50 }
51
52 switch (N->getOpcode()) {
53 default:
54#ifndef NDEBUG
55 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
56 N->dump(&DAG); dbgs() << "\n";
57#endif
58 report_fatal_error(reason: "Do not know how to promote this operator!");
59 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
60 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
61 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
62 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
63 case ISD::VP_BITREVERSE:
64 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
65 case ISD::VP_BSWAP:
66 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
67 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
68 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
69 case ISD::VP_CTLZ_ZERO_UNDEF:
70 case ISD::VP_CTLZ:
71 case ISD::CTLZ_ZERO_UNDEF:
72 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
73 case ISD::CTLS: Res = PromoteIntRes_CTLS(N); break;
74 case ISD::PARITY:
75 case ISD::VP_CTPOP:
76 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
77 case ISD::VP_CTTZ_ZERO_UNDEF:
78 case ISD::VP_CTTZ:
79 case ISD::CTTZ_ZERO_UNDEF:
80 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
81 case ISD::CTTZ_ELTS_ZERO_POISON:
82 case ISD::CTTZ_ELTS:
83 case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
84 case ISD::VP_CTTZ_ELTS:
85 Res = PromoteIntRes_VP_CttzElements(N);
86 break;
87 case ISD::EXTRACT_VECTOR_ELT:
88 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
89 case ISD::LOAD: Res = PromoteIntRes_LOAD(N: cast<LoadSDNode>(Val: N)); break;
90 case ISD::VP_LOAD:
91 Res = PromoteIntRes_VP_LOAD(N: cast<VPLoadSDNode>(Val: N));
92 break;
93 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(N: cast<MaskedLoadSDNode>(Val: N));
94 break;
95 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(N: cast<MaskedGatherSDNode>(Val: N));
96 break;
97 case ISD::VECTOR_COMPRESS:
98 Res = PromoteIntRes_VECTOR_COMPRESS(N);
99 break;
100 case ISD::SELECT:
101 case ISD::VSELECT:
102 case ISD::VP_SELECT:
103 case ISD::VP_MERGE:
104 Res = PromoteIntRes_Select(N);
105 break;
106 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
107 case ISD::STRICT_FSETCC:
108 case ISD::STRICT_FSETCCS:
109 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
110 case ISD::SMIN:
111 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
112 case ISD::UMIN:
113 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
114
115 case ISD::SHL:
116 case ISD::VP_SHL: Res = PromoteIntRes_SHL(N); break;
117 case ISD::SIGN_EXTEND_INREG:
118 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
119 case ISD::SRA:
120 case ISD::VP_SRA: Res = PromoteIntRes_SRA(N); break;
121 case ISD::SRL:
122 case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
123 case ISD::VP_TRUNCATE:
124 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
125 case ISD::POISON:
126 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
127 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
128 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
129
130 case ISD::EXTRACT_SUBVECTOR:
131 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
132 case ISD::INSERT_SUBVECTOR:
133 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
134 case ISD::VECTOR_REVERSE:
135 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
136 case ISD::VECTOR_SHUFFLE:
137 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
138 case ISD::VECTOR_SPLICE_LEFT:
139 case ISD::VECTOR_SPLICE_RIGHT:
140 Res = PromoteIntRes_VECTOR_SPLICE(N);
141 break;
142 case ISD::VECTOR_INTERLEAVE:
143 case ISD::VECTOR_DEINTERLEAVE:
144 Res = PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(N);
145 return;
146 case ISD::INSERT_VECTOR_ELT:
147 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
148 case ISD::BUILD_VECTOR:
149 Res = PromoteIntRes_BUILD_VECTOR(N);
150 break;
151 case ISD::SPLAT_VECTOR:
152 case ISD::SCALAR_TO_VECTOR:
153 Res = PromoteIntRes_ScalarOp(N);
154 break;
155 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
156 case ISD::CONCAT_VECTORS:
157 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
158
159 case ISD::ANY_EXTEND_VECTOR_INREG:
160 case ISD::SIGN_EXTEND_VECTOR_INREG:
161 case ISD::ZERO_EXTEND_VECTOR_INREG:
162 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
163
164 case ISD::VECTOR_FIND_LAST_ACTIVE:
165 Res = PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(N);
166 break;
167
168 case ISD::GET_ACTIVE_LANE_MASK:
169 Res = PromoteIntRes_GET_ACTIVE_LANE_MASK(N);
170 break;
171
172 case ISD::PARTIAL_REDUCE_UMLA:
173 case ISD::PARTIAL_REDUCE_SMLA:
174 case ISD::PARTIAL_REDUCE_SUMLA:
175 Res = PromoteIntRes_PARTIAL_REDUCE_MLA(N);
176 break;
177
178 case ISD::SIGN_EXTEND:
179 case ISD::VP_SIGN_EXTEND:
180 case ISD::ZERO_EXTEND:
181 case ISD::VP_ZERO_EXTEND:
182 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
183
184 case ISD::VP_FP_TO_SINT:
185 case ISD::VP_FP_TO_UINT:
186 case ISD::STRICT_FP_TO_SINT:
187 case ISD::STRICT_FP_TO_UINT:
188 case ISD::FP_TO_SINT:
189 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
190
191 case ISD::FP_TO_SINT_SAT:
192 case ISD::FP_TO_UINT_SAT:
193 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
194
195 case ISD::FP_TO_BF16:
196 case ISD::FP_TO_FP16:
197 Res = PromoteIntRes_FP_TO_FP16_BF16(N);
198 break;
199 case ISD::STRICT_FP_TO_BF16:
200 case ISD::STRICT_FP_TO_FP16:
201 Res = PromoteIntRes_STRICT_FP_TO_FP16_BF16(N);
202 break;
203 case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break;
204
205 case ISD::AND:
206 case ISD::OR:
207 case ISD::XOR:
208 case ISD::ADD:
209 case ISD::SUB:
210 case ISD::MUL:
211 case ISD::VP_AND:
212 case ISD::VP_OR:
213 case ISD::VP_XOR:
214 case ISD::VP_ADD:
215 case ISD::VP_SUB:
216 case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
217
218 case ISD::ABDS:
219 case ISD::AVGCEILS:
220 case ISD::AVGFLOORS:
221 case ISD::VP_SMIN:
222 case ISD::VP_SMAX:
223 case ISD::SDIV:
224 case ISD::SREM:
225 case ISD::VP_SDIV:
226 case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
227
228 case ISD::ABDU:
229 case ISD::AVGCEILU:
230 case ISD::AVGFLOORU:
231 case ISD::VP_UMIN:
232 case ISD::VP_UMAX:
233 case ISD::UDIV:
234 case ISD::UREM:
235 case ISD::VP_UDIV:
236 case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
237
238 case ISD::SADDO:
239 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
240 case ISD::UADDO:
241 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
242 case ISD::SMULO:
243 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
244
245 case ISD::ADDE:
246 case ISD::SUBE:
247 case ISD::UADDO_CARRY:
248 case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break;
249
250 case ISD::SADDO_CARRY:
251 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
252
253 case ISD::SADDSAT:
254 case ISD::UADDSAT:
255 case ISD::SSUBSAT:
256 case ISD::USUBSAT:
257 case ISD::SSHLSAT:
258 case ISD::USHLSAT:
259 Res = PromoteIntRes_ADDSUBSHLSAT<EmptyMatchContext>(N);
260 break;
261 case ISD::VP_SADDSAT:
262 case ISD::VP_UADDSAT:
263 case ISD::VP_SSUBSAT:
264 case ISD::VP_USUBSAT:
265 Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
266 break;
267
268 case ISD::SCMP:
269 case ISD::UCMP:
270 Res = PromoteIntRes_CMP(N);
271 break;
272
273 case ISD::SMULFIX:
274 case ISD::SMULFIXSAT:
275 case ISD::UMULFIX:
276 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
277
278 case ISD::SDIVFIX:
279 case ISD::SDIVFIXSAT:
280 case ISD::UDIVFIX:
281 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
282
283 case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
284
285 case ISD::ATOMIC_LOAD:
286 Res = PromoteIntRes_Atomic0(N: cast<AtomicSDNode>(Val: N)); break;
287
288 case ISD::ATOMIC_LOAD_ADD:
289 case ISD::ATOMIC_LOAD_SUB:
290 case ISD::ATOMIC_LOAD_AND:
291 case ISD::ATOMIC_LOAD_CLR:
292 case ISD::ATOMIC_LOAD_OR:
293 case ISD::ATOMIC_LOAD_XOR:
294 case ISD::ATOMIC_LOAD_NAND:
295 case ISD::ATOMIC_LOAD_MIN:
296 case ISD::ATOMIC_LOAD_MAX:
297 case ISD::ATOMIC_LOAD_UMIN:
298 case ISD::ATOMIC_LOAD_UMAX:
299 case ISD::ATOMIC_SWAP:
300 Res = PromoteIntRes_Atomic1(N: cast<AtomicSDNode>(Val: N)); break;
301
302 case ISD::ATOMIC_CMP_SWAP:
303 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
304 Res = PromoteIntRes_AtomicCmpSwap(N: cast<AtomicSDNode>(Val: N), ResNo);
305 break;
306
307 case ISD::VECREDUCE_ADD:
308 case ISD::VECREDUCE_MUL:
309 case ISD::VECREDUCE_AND:
310 case ISD::VECREDUCE_OR:
311 case ISD::VECREDUCE_XOR:
312 case ISD::VECREDUCE_SMAX:
313 case ISD::VECREDUCE_SMIN:
314 case ISD::VECREDUCE_UMAX:
315 case ISD::VECREDUCE_UMIN:
316 Res = PromoteIntRes_VECREDUCE(N);
317 break;
318
319 case ISD::VP_REDUCE_ADD:
320 case ISD::VP_REDUCE_MUL:
321 case ISD::VP_REDUCE_AND:
322 case ISD::VP_REDUCE_OR:
323 case ISD::VP_REDUCE_XOR:
324 case ISD::VP_REDUCE_SMAX:
325 case ISD::VP_REDUCE_SMIN:
326 case ISD::VP_REDUCE_UMAX:
327 case ISD::VP_REDUCE_UMIN:
328 Res = PromoteIntRes_VP_REDUCE(N);
329 break;
330
331 case ISD::LOOP_DEPENDENCE_WAR_MASK:
332 case ISD::LOOP_DEPENDENCE_RAW_MASK:
333 Res = PromoteIntRes_LOOP_DEPENDENCE_MASK(N);
334 break;
335
336 case ISD::FREEZE:
337 Res = PromoteIntRes_FREEZE(N);
338 break;
339
340 case ISD::ROTL:
341 case ISD::ROTR:
342 Res = PromoteIntRes_Rotate(N);
343 break;
344
345 case ISD::FSHL:
346 case ISD::FSHR:
347 Res = PromoteIntRes_FunnelShift(N);
348 break;
349
350 case ISD::VP_FSHL:
351 case ISD::VP_FSHR:
352 Res = PromoteIntRes_VPFunnelShift(N);
353 break;
354
355 case ISD::CLMUL:
356 case ISD::CLMULH:
357 case ISD::CLMULR:
358 Res = PromoteIntRes_CLMUL(N);
359 break;
360
361 case ISD::IS_FPCLASS:
362 Res = PromoteIntRes_IS_FPCLASS(N);
363 break;
364 case ISD::FFREXP:
365 Res = PromoteIntRes_FFREXP(N);
366 break;
367
368 case ISD::LRINT:
369 case ISD::LLRINT:
370 Res = PromoteIntRes_XRINT(N);
371 break;
372
373 case ISD::PATCHPOINT:
374 Res = PromoteIntRes_PATCHPOINT(N);
375 break;
376 case ISD::READ_REGISTER:
377 Res = PromoteIntRes_READ_REGISTER(N);
378 break;
379 }
380
381 // If the result is null then the sub-method took care of registering it.
382 if (Res.getNode())
383 SetPromotedInteger(Op: SDValue(N, ResNo), Result: Res);
384}
385
386SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
387 unsigned ResNo) {
388 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
389 return GetPromotedInteger(Op);
390}
391
392SDValue DAGTypeLegalizer::PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
393 EVT VT = N->getValueType(ResNo: 0);
394 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
395 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: NewVT, Ops: N->ops());
396}
397
398SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
399 // Sign-extend the new bits, and continue the assertion.
400 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
401 return DAG.getNode(Opcode: ISD::AssertSext, DL: SDLoc(N),
402 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
403}
404
405SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
406 // Zero the new bits, and continue the assertion.
407 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
408 return DAG.getNode(Opcode: ISD::AssertZext, DL: SDLoc(N),
409 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
410}
411
412SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
413 EVT ResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
414 ISD::LoadExtType ExtType = N->getExtensionType();
415 if (ExtType == ISD::NON_EXTLOAD) {
416 switch (TLI.getExtendForAtomicOps()) {
417 case ISD::SIGN_EXTEND:
418 ExtType = ISD::SEXTLOAD;
419 break;
420 case ISD::ZERO_EXTEND:
421 ExtType = ISD::ZEXTLOAD;
422 break;
423 case ISD::ANY_EXTEND:
424 ExtType = ISD::EXTLOAD;
425 break;
426 default:
427 llvm_unreachable("Invalid atomic op extension");
428 }
429 }
430
431 SDValue Res =
432 DAG.getAtomicLoad(ExtType, dl: SDLoc(N), MemVT: N->getMemoryVT(), VT: ResVT,
433 Chain: N->getChain(), Ptr: N->getBasePtr(), MMO: N->getMemOperand());
434
435 // Legalize the chain result - switch anything that used the old chain to
436 // use the new one.
437 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
438 return Res;
439}
440
441SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
442 SDValue Op2 = N->getOperand(Num: 2);
443 switch (TLI.getExtendForAtomicRMWArg(Op: N->getOpcode())) {
444 case ISD::SIGN_EXTEND:
445 Op2 = SExtPromotedInteger(Op: Op2);
446 break;
447 case ISD::ZERO_EXTEND:
448 Op2 = ZExtPromotedInteger(Op: Op2);
449 break;
450 case ISD::ANY_EXTEND:
451 Op2 = GetPromotedInteger(Op: Op2);
452 break;
453 default:
454 llvm_unreachable("Invalid atomic op extension");
455 }
456 SDValue Res = DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N),
457 MemVT: N->getMemoryVT(),
458 Chain: N->getChain(), Ptr: N->getBasePtr(),
459 Val: Op2, MMO: N->getMemOperand());
460 // Legalize the chain result - switch anything that used the old chain to
461 // use the new one.
462 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
463 return Res;
464}
465
466SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
467 unsigned ResNo) {
468 if (ResNo == 1) {
469 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
470 EVT SVT = getSetCCResultType(VT: N->getOperand(Num: 2).getValueType());
471 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
472
473 // Only use the result of getSetCCResultType if it is legal,
474 // otherwise just use the promoted result type (NVT).
475 if (!TLI.isTypeLegal(VT: SVT))
476 SVT = NVT;
477
478 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: SVT, VT3: MVT::Other);
479 SDValue Res = DAG.getAtomicCmpSwap(
480 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs,
481 Chain: N->getChain(), Ptr: N->getBasePtr(), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
482 MMO: N->getMemOperand());
483 ReplaceValueWith(From: SDValue(N, 0), To: Res.getValue(R: 0));
484 ReplaceValueWith(From: SDValue(N, 2), To: Res.getValue(R: 2));
485 return DAG.getSExtOrTrunc(Op: Res.getValue(R: 1), DL: SDLoc(N), VT: NVT);
486 }
487
488 // Op2 is used for the comparison and thus must be extended according to the
489 // target's atomic operations. Op3 is merely stored and so can be left alone.
490 SDValue Op2 = N->getOperand(Num: 2);
491 SDValue Op3 = GetPromotedInteger(Op: N->getOperand(Num: 3));
492 switch (TLI.getExtendForAtomicCmpSwapArg()) {
493 case ISD::SIGN_EXTEND:
494 Op2 = SExtPromotedInteger(Op: Op2);
495 break;
496 case ISD::ZERO_EXTEND:
497 Op2 = ZExtPromotedInteger(Op: Op2);
498 break;
499 case ISD::ANY_EXTEND:
500 Op2 = GetPromotedInteger(Op: Op2);
501 break;
502 default:
503 llvm_unreachable("Invalid atomic op extension");
504 }
505
506 SDVTList VTs =
507 DAG.getVTList(VT1: Op2.getValueType(), VT2: N->getValueType(ResNo: 1), VT3: MVT::Other);
508 SDValue Res = DAG.getAtomicCmpSwap(
509 Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs, Chain: N->getChain(),
510 Ptr: N->getBasePtr(), Cmp: Op2, Swp: Op3, MMO: N->getMemOperand());
511 // Update the use to N with the newly created Res.
512 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
513 ReplaceValueWith(From: SDValue(N, i), To: Res.getValue(R: i));
514 return Res;
515}
516
517SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
518 SDValue InOp = N->getOperand(Num: 0);
519 EVT InVT = InOp.getValueType();
520 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
521 EVT OutVT = N->getValueType(ResNo: 0);
522 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
523 SDLoc dl(N);
524
525 switch (getTypeAction(VT: InVT)) {
526 case TargetLowering::TypeLegal:
527 break;
528 case TargetLowering::TypePromoteInteger:
529 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector() && !NInVT.isVector())
530 // The input promotes to the same size. Convert the promoted value.
531 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetPromotedInteger(Op: InOp));
532 break;
533 case TargetLowering::TypeSoftenFloat:
534 // Promote the integer operand by hand.
535 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftenedFloat(Op: InOp));
536 case TargetLowering::TypeSoftPromoteHalf:
537 // Promote the integer operand by hand.
538 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftPromotedHalf(Op: InOp));
539 case TargetLowering::TypeExpandInteger:
540 case TargetLowering::TypeExpandFloat:
541 break;
542 case TargetLowering::TypeScalarizeVector:
543 // Convert the element to an integer and promote it by hand.
544 if (!NOutVT.isVector())
545 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
546 Operand: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)));
547 break;
548 case TargetLowering::TypeScalarizeScalableVector:
549 report_fatal_error(reason: "Scalarization of scalable vectors is not supported.");
550 case TargetLowering::TypeSplitVector: {
551 if (!NOutVT.isVector()) {
552 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
553 // pieces of the input into integers and reassemble in the final type.
554 SDValue Lo, Hi;
555 GetSplitVector(Op: N->getOperand(Num: 0), Lo, Hi);
556 Lo = BitConvertToInteger(Op: Lo);
557 Hi = BitConvertToInteger(Op: Hi);
558
559 if (DAG.getDataLayout().isBigEndian())
560 std::swap(a&: Lo, b&: Hi);
561
562 InOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
563 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
564 BitWidth: NOutVT.getSizeInBits()),
565 Operand: JoinIntegers(Lo, Hi));
566 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: InOp);
567 }
568 break;
569 }
570 case TargetLowering::TypeWidenVector:
571 // The input is widened to the same size. Convert to the widened value.
572 // Make sure that the outgoing value is not a vector, because this would
573 // make us bitcast between two vectors which are legalized in different ways.
574 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector()) {
575 SDValue Res =
576 DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetWidenedVector(Op: InOp));
577
578 // For big endian targets we need to shift the casted value or the
579 // interesting bits will end up at the wrong place.
580 if (DAG.getDataLayout().isBigEndian()) {
581 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
582 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
583 Res = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NOutVT, N1: Res,
584 N2: DAG.getShiftAmountConstant(Val: ShiftAmt, VT: NOutVT, DL: dl));
585 }
586 return Res;
587 }
588 // If the output type is also a vector and widening it to the same size
589 // as the widened input type would be a legal type, we can widen the bitcast
590 // and handle the promotion after.
591 if (NOutVT.isVector()) {
592 TypeSize WidenInSize = NInVT.getSizeInBits();
593 TypeSize OutSize = OutVT.getSizeInBits();
594 if (WidenInSize.hasKnownScalarFactor(RHS: OutSize)) {
595 unsigned Scale = WidenInSize.getKnownScalarFactor(RHS: OutSize);
596 EVT WideOutVT =
597 EVT::getVectorVT(Context&: *DAG.getContext(), VT: OutVT.getVectorElementType(),
598 EC: OutVT.getVectorElementCount() * Scale);
599 if (isTypeLegal(VT: WideOutVT)) {
600 InOp = DAG.getBitcast(VT: WideOutVT, V: GetWidenedVector(Op: InOp));
601 InOp = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: InOp,
602 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
603 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: InOp);
604 }
605 }
606 }
607 }
608
609 // TODO: Handle big endian
610 if (!NOutVT.isVector() && InOp.getValueType().isVector() &&
611 DAG.getDataLayout().isLittleEndian()) {
612 // Pad the vector operand with undef and cast to a wider integer.
613 EVT EltVT = InOp.getValueType().getVectorElementType();
614 TypeSize EltSize = EltVT.getSizeInBits();
615 TypeSize OutSize = NOutVT.getSizeInBits();
616
617 if (OutSize.hasKnownScalarFactor(RHS: EltSize)) {
618 unsigned NumEltsWithPadding = OutSize.getKnownScalarFactor(RHS: EltSize);
619 EVT WideVecVT =
620 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
621
622 if (isTypeLegal(VT: WideVecVT)) {
623 SDValue Inserted = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: WideVecVT,
624 N1: DAG.getUNDEF(VT: WideVecVT), N2: InOp,
625 N3: DAG.getVectorIdxConstant(Val: 0, DL: dl));
626
627 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Inserted);
628 }
629 }
630 }
631
632 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
633 Operand: CreateStackStoreLoad(Op: InOp, DestVT: OutVT));
634}
635
636SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
637 SDValue V = GetPromotedInteger(Op: N->getOperand(Num: 0));
638 return DAG.getNode(Opcode: ISD::FREEZE, DL: SDLoc(N),
639 VT: V.getValueType(), Operand: V);
640}
641
642SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
643 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
644 EVT OVT = N->getValueType(ResNo: 0);
645 EVT NVT = Op.getValueType();
646 SDLoc dl(N);
647
648 // If the larger BSWAP isn't supported by the target, try to expand now.
649 // If we expand later we'll end up with more operations since we lost the
650 // original type. We only do this for scalars since we have a shuffle
651 // based lowering for vectors in LegalizeVectorOps.
652 if (!OVT.isVector() &&
653 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BSWAP, VT: NVT)) {
654 if (SDValue Res = TLI.expandBSWAP(N, DAG))
655 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
656 }
657
658 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
659 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
660 if (N->getOpcode() == ISD::BSWAP)
661 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: NVT, Operand: Op),
662 N2: ShAmt);
663 SDValue Mask = N->getOperand(Num: 1);
664 SDValue EVL = N->getOperand(Num: 2);
665 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
666 N1: DAG.getNode(Opcode: ISD::VP_BSWAP, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL), N2: ShAmt,
667 N3: Mask, N4: EVL);
668}
669
670SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
671 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
672 EVT OVT = N->getValueType(ResNo: 0);
673 EVT NVT = Op.getValueType();
674 SDLoc dl(N);
675
676 // If the larger BITREVERSE isn't supported by the target, try to expand now.
677 // If we expand later we'll end up with more operations since we lost the
678 // original type. We only do this for scalars since we have a shuffle
679 // based lowering for vectors in LegalizeVectorOps.
680 if (!OVT.isVector() && OVT.isSimple() &&
681 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BITREVERSE, VT: NVT)) {
682 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
683 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
684 }
685
686 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
687 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
688 if (N->getOpcode() == ISD::BITREVERSE)
689 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT,
690 N1: DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: NVT, Operand: Op), N2: ShAmt);
691 SDValue Mask = N->getOperand(Num: 1);
692 SDValue EVL = N->getOperand(Num: 2);
693 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
694 N1: DAG.getNode(Opcode: ISD::VP_BITREVERSE, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
695 N2: ShAmt, N3: Mask, N4: EVL);
696}
697
698SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
699 // The pair element type may be legal, or may not promote to the same type as
700 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
701 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N),
702 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
703 VT: N->getValueType(ResNo: 0)), Operand: JoinIntegers(Lo: N->getOperand(Num: 0),
704 Hi: N->getOperand(Num: 1)));
705}
706
707SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
708 EVT VT = N->getValueType(ResNo: 0);
709 // FIXME there is no actual debug info here
710 SDLoc dl(N);
711 // Zero extend things like i1, sign extend everything else. It shouldn't
712 // matter in theory which one we pick, but this tends to give better code?
713 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
714 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl,
715 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT),
716 Operand: SDValue(N, 0));
717 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
718 return Result;
719}
720
721SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
722 EVT OVT = N->getValueType(ResNo: 0);
723 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
724 SDLoc dl(N);
725
726 // If the larger CTLZ isn't supported by the target, try to expand now.
727 // If we expand later we'll end up with more operations since we lost the
728 // original type.
729 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
730 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ, VT: NVT) &&
731 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ_ZERO_UNDEF, VT: NVT)) {
732 if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
733 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
734 return Result;
735 }
736 }
737
738 unsigned CtlzOpcode = N->getOpcode();
739 if (CtlzOpcode == ISD::CTLZ || CtlzOpcode == ISD::VP_CTLZ) {
740 // Subtract off the extra leading bits in the bigger type.
741 SDValue ExtractLeadingBits = DAG.getConstant(
742 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
743 // Zero extend to the promoted type and do the count there.
744 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
745
746 // At this stage SUB is guaranteed to be positive no-wrap,
747 // that to be used in further KnownBits optimizations.
748 if (!N->isVPOpcode())
749 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT,
750 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Op),
751 N2: ExtractLeadingBits, Flags: SDNodeFlags::NoUnsignedWrap);
752 SDValue Mask = N->getOperand(Num: 1);
753 SDValue EVL = N->getOperand(Num: 2);
754 return DAG.getNode(Opcode: ISD::VP_SUB, DL: dl, VT: NVT,
755 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
756 N2: ExtractLeadingBits, N3: Mask, N4: EVL,
757 Flags: SDNodeFlags::NoUnsignedWrap);
758 }
759 if (CtlzOpcode == ISD::CTLZ_ZERO_UNDEF ||
760 CtlzOpcode == ISD::VP_CTLZ_ZERO_UNDEF) {
761 // Any Extend the argument
762 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
763 // Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
764 unsigned SHLAmount = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
765 auto ShiftConst =
766 DAG.getShiftAmountConstant(Val: SHLAmount, VT: Op.getValueType(), DL: dl);
767 if (!N->isVPOpcode()) {
768 Op = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst);
769 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, Operand: Op);
770 }
771
772 SDValue Mask = N->getOperand(Num: 1);
773 SDValue EVL = N->getOperand(Num: 2);
774 Op = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst, N3: Mask, N4: EVL);
775 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL);
776 }
777 llvm_unreachable("Invalid CTLZ Opcode");
778}
779
780SDValue DAGTypeLegalizer::PromoteIntRes_CTLS(SDNode *N) {
781 EVT OVT = N->getValueType(ResNo: 0);
782 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
783 SDLoc dl(N);
784
785 SDValue ExtractLeadingBits = DAG.getConstant(
786 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
787
788 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
789 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Op),
790 N2: ExtractLeadingBits);
791}
792
793SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
794 EVT OVT = N->getValueType(ResNo: 0);
795 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
796
797 // If the larger CTPOP isn't supported by the target, try to expand now.
798 // If we expand later we'll end up with more operations since we lost the
799 // original type.
800 // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
801 // TargetLowering.
802 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
803 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTPOP, VT: NVT)) {
804 if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
805 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Result);
806 return Result;
807 }
808 }
809
810 // Zero extend to the promoted type and do the count or parity there.
811 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
812 if (!N->isVPOpcode())
813 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), Operand: Op);
814
815 SDValue Mask = N->getOperand(Num: 1);
816 SDValue EVL = N->getOperand(Num: 2);
817 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), N1: Op, N2: Mask,
818 N3: EVL);
819}
820
821SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
822 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
823 EVT OVT = N->getValueType(ResNo: 0);
824 EVT NVT = Op.getValueType();
825 SDLoc dl(N);
826
827 // If the larger CTTZ isn't supported by the target, try to expand now.
828 // If we expand later we'll end up with more operations since we lost the
829 // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
830 // larger type.
831 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
832 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ, VT: NVT) &&
833 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ_ZERO_UNDEF, VT: NVT) &&
834 !TLI.isOperationLegal(Op: ISD::CTPOP, VT: NVT) &&
835 !TLI.isOperationLegal(Op: ISD::CTLZ, VT: NVT)) {
836 if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
837 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
838 return Result;
839 }
840 }
841
842 unsigned NewOpc = N->getOpcode();
843 if (NewOpc == ISD::CTTZ || NewOpc == ISD::VP_CTTZ) {
844 // The count is the same in the promoted type except if the original
845 // value was zero. This can be handled by setting the bit just off
846 // the top of the original type.
847 auto TopBit = APInt::getOneBitSet(numBits: NVT.getScalarSizeInBits(),
848 BitNo: OVT.getScalarSizeInBits());
849 if (NewOpc == ISD::CTTZ) {
850 Op = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
851 NewOpc = ISD::CTTZ_ZERO_UNDEF;
852 } else {
853 Op =
854 DAG.getNode(Opcode: ISD::VP_OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT),
855 N3: N->getOperand(Num: 1), N4: N->getOperand(Num: 2));
856 NewOpc = ISD::VP_CTTZ_ZERO_UNDEF;
857 }
858 }
859 if (!N->isVPOpcode())
860 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Op);
861 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, N1: Op, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
862}
863
864SDValue DAGTypeLegalizer::PromoteIntRes_VP_CttzElements(SDNode *N) {
865 SDLoc DL(N);
866 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
867 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NewVT, Ops: N->ops());
868}
869
870SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
871 SDLoc dl(N);
872 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
873
874 SDValue Op0 = N->getOperand(Num: 0);
875 SDValue Op1 = N->getOperand(Num: 1);
876
877 // If the input also needs to be promoted, do that first so we can get a
878 // get a good idea for the output type.
879 if (TLI.getTypeAction(Context&: *DAG.getContext(), VT: Op0.getValueType())
880 == TargetLowering::TypePromoteInteger) {
881 SDValue In = GetPromotedInteger(Op: Op0);
882
883 // If the new type is larger than NVT, use it. We probably won't need to
884 // promote it again.
885 EVT SVT = In.getValueType().getScalarType();
886 if (SVT.bitsGE(VT: NVT)) {
887 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SVT, N1: In, N2: Op1);
888 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NVT);
889 }
890 }
891
892 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NVT, N1: Op0, N2: Op1);
893}
894
895SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
896 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
897 unsigned NewOpc =
898 TLI.getPreferredFPToIntOpcode(Op: N->getOpcode(), FromVT: N->getValueType(ResNo: 0), ToVT: NVT);
899 SDLoc dl(N);
900
901 SDValue Res;
902 if (N->isStrictFPOpcode()) {
903 Res = DAG.getNode(Opcode: NewOpc, DL: dl, ResultTys: {NVT, MVT::Other},
904 Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1)});
905 // Legalize the chain result - switch anything that used the old chain to
906 // use the new one.
907 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
908 } else if (NewOpc == ISD::VP_FP_TO_SINT || NewOpc == ISD::VP_FP_TO_UINT) {
909 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1),
910 N->getOperand(Num: 2)});
911 } else {
912 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
913 }
914
915 // Assert that the converted value fits in the original type. If it doesn't
916 // (eg: because the value being converted is too big), then the result of the
917 // original operation was undefined anyway, so the assert is still correct.
918 //
919 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
920 // before legalization: fp-to-uint16, 65534. -> 0xfffe
921 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
922 return DAG.getNode(Opcode: (N->getOpcode() == ISD::FP_TO_UINT ||
923 N->getOpcode() == ISD::STRICT_FP_TO_UINT ||
924 N->getOpcode() == ISD::VP_FP_TO_UINT)
925 ? ISD::AssertZext
926 : ISD::AssertSext,
927 DL: dl, VT: NVT, N1: Res,
928 N2: DAG.getValueType(N->getValueType(ResNo: 0).getScalarType()));
929}
930
931SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
932 // Promote the result type, while keeping the original width in Op1.
933 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
934 SDLoc dl(N);
935 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
936 N2: N->getOperand(Num: 1));
937}
938
939SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16_BF16(SDNode *N) {
940 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
941 SDLoc dl(N);
942
943 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
944}
945
946SDValue DAGTypeLegalizer::PromoteIntRes_STRICT_FP_TO_FP16_BF16(SDNode *N) {
947 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
948 SDLoc dl(N);
949
950 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
951 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
952 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
953 return Res;
954}
955
956SDValue DAGTypeLegalizer::PromoteIntRes_XRINT(SDNode *N) {
957 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
958 SDLoc dl(N);
959 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
960}
961
962SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) {
963 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
964 SDLoc dl(N);
965
966 SDValue Res =
967 DAG.getNode(Opcode: N->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
968
969 // Legalize the chain result - switch anything that used the old chain to
970 // use the new one.
971 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
972 return Res;
973}
974
975SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
976 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
977 SDLoc dl(N);
978
979 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
980 == TargetLowering::TypePromoteInteger) {
981 SDValue Res = GetPromotedInteger(Op: N->getOperand(Num: 0));
982 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
983
984 // If the result and operand types are the same after promotion, simplify
985 // to an in-register extension. Unless this is a VP_*_EXTEND.
986 if (NVT == Res.getValueType() && N->getNumOperands() == 1) {
987 // The high bits are not guaranteed to be anything. Insert an extend.
988 if (N->getOpcode() == ISD::SIGN_EXTEND)
989 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
990 N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
991 if (N->getOpcode() == ISD::ZERO_EXTEND)
992 return DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: N->getOperand(Num: 0).getValueType());
993 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
994 return Res;
995 }
996 }
997
998 // Otherwise, just extend the original operand all the way to the larger type.
999 if (N->getNumOperands() != 1) {
1000 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
1001 assert(N->isVPOpcode() && "Expected VP opcode");
1002 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
1003 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
1004 }
1005 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
1006}
1007
1008SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
1009 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1010 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1011 ISD::LoadExtType ExtType =
1012 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
1013 SDLoc dl(N);
1014 SDValue Res = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
1015 MemVT: N->getMemoryVT(), MMO: N->getMemOperand());
1016
1017 // Legalize the chain result - switch anything that used the old chain to
1018 // use the new one.
1019 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1020 return Res;
1021}
1022
1023SDValue DAGTypeLegalizer::PromoteIntRes_VP_LOAD(VPLoadSDNode *N) {
1024 assert(!N->isIndexed() && "Indexed vp_load during type legalization!");
1025 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1026 ISD::LoadExtType ExtType = (N->getExtensionType() == ISD::NON_EXTLOAD)
1027 ? ISD::EXTLOAD
1028 : N->getExtensionType();
1029 SDLoc dl(N);
1030 SDValue Res =
1031 DAG.getExtLoadVP(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
1032 Mask: N->getMask(), EVL: N->getVectorLength(), MemVT: N->getMemoryVT(),
1033 MMO: N->getMemOperand(), IsExpanding: N->isExpandingLoad());
1034 // Legalize the chain result - switch anything that used the old chain to
1035 // use the new one.
1036 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1037 return Res;
1038}
1039
1040SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
1041 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1042 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1043
1044 ISD::LoadExtType ExtType = N->getExtensionType();
1045 if (ExtType == ISD::NON_EXTLOAD)
1046 ExtType = ISD::EXTLOAD;
1047
1048 SDLoc dl(N);
1049 SDValue Res = DAG.getMaskedLoad(VT: NVT, dl, Chain: N->getChain(), Base: N->getBasePtr(),
1050 Offset: N->getOffset(), Mask: N->getMask(), Src0: ExtPassThru,
1051 MemVT: N->getMemoryVT(), MMO: N->getMemOperand(),
1052 AM: N->getAddressingMode(), ExtType,
1053 IsExpanding: N->isExpandingLoad());
1054 // Legalize the chain result - switch anything that used the old chain to
1055 // use the new one.
1056 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1057 return Res;
1058}
1059
1060SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
1061 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1062 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1063 assert(NVT == ExtPassThru.getValueType() &&
1064 "Gather result type and the passThru argument type should be the same");
1065
1066 ISD::LoadExtType ExtType = N->getExtensionType();
1067 if (ExtType == ISD::NON_EXTLOAD)
1068 ExtType = ISD::EXTLOAD;
1069
1070 SDLoc dl(N);
1071 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
1072 N->getIndex(), N->getScale() };
1073 SDValue Res = DAG.getMaskedGather(VTs: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
1074 MemVT: N->getMemoryVT(), dl, Ops,
1075 MMO: N->getMemOperand(), IndexType: N->getIndexType(),
1076 ExtTy: ExtType);
1077 // Legalize the chain result - switch anything that used the old chain to
1078 // use the new one.
1079 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1080 return Res;
1081}
1082
1083SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_COMPRESS(SDNode *N) {
1084 SDValue Vec = GetPromotedInteger(Op: N->getOperand(Num: 0));
1085 SDValue Passthru = GetPromotedInteger(Op: N->getOperand(Num: 2));
1086 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT: Vec.getValueType(), N1: Vec,
1087 N2: N->getOperand(Num: 1), N3: Passthru);
1088}
1089
1090/// Promote the overflow flag of an overflowing arithmetic node.
1091SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
1092 // Change the return type of the boolean result while obeying
1093 // getSetCCResultType.
1094 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1095 EVT VT = N->getValueType(ResNo: 0);
1096 EVT SVT = getSetCCResultType(VT);
1097 SDValue Ops[3] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
1098 unsigned NumOps = N->getNumOperands();
1099 assert(NumOps <= 3 && "Too many operands");
1100 if (NumOps == 3)
1101 Ops[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: VT);
1102
1103 SDLoc dl(N);
1104 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: SVT),
1105 Ops: ArrayRef(Ops, NumOps));
1106
1107 // Modified the sum result - switch anything that used the old sum to use
1108 // the new one.
1109 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1110
1111 // Convert to the expected type.
1112 return DAG.getBoolExtOrTrunc(Op: Res.getValue(R: 1), SL: dl, VT: NVT, OpVT: VT);
1113}
1114
1115template <class MatchContextClass>
1116SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
1117 // If the promoted type is legal, we can convert this to:
1118 // 1. ANY_EXTEND iN to iM
1119 // 2. SHL by M-N
1120 // 3. [US][ADD|SUB|SHL]SAT
1121 // 4. L/ASHR by M-N
1122 // Else it is more efficient to convert this to a min and a max
1123 // operation in the higher precision arithmetic.
1124 SDLoc dl(N);
1125 SDValue Op1 = N->getOperand(Num: 0);
1126 SDValue Op2 = N->getOperand(Num: 1);
1127 MatchContextClass matcher(DAG, TLI, N);
1128
1129 unsigned Opcode = matcher.getRootBaseOpcode();
1130 unsigned OldBits = Op1.getScalarValueSizeInBits();
1131
1132 // USUBSAT can always be promoted as long as we have zero/sign-extended the
1133 // args.
1134 if (Opcode == ISD::USUBSAT) {
1135 SExtOrZExtPromotedOperands(LHS&: Op1, RHS&: Op2);
1136 return matcher.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
1137 }
1138
1139 if (Opcode == ISD::UADDSAT) {
1140 EVT OVT = Op1.getValueType();
1141 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1142 // We can promote if we use sign-extend. Do this if the target prefers.
1143 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT)) {
1144 Op1 = SExtPromotedInteger(Op: Op1);
1145 Op2 = SExtPromotedInteger(Op: Op2);
1146 return matcher.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2);
1147 }
1148
1149 Op1 = ZExtPromotedInteger(Op: Op1);
1150 Op2 = ZExtPromotedInteger(Op: Op2);
1151 unsigned NewBits = NVT.getScalarSizeInBits();
1152 APInt MaxVal = APInt::getLowBitsSet(numBits: NewBits, loBitsSet: OldBits);
1153 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: NVT);
1154 SDValue Add = matcher.getNode(ISD::ADD, dl, NVT, Op1, Op2);
1155 return matcher.getNode(ISD::UMIN, dl, NVT, Add, SatMax);
1156 }
1157
1158 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
1159
1160 // FIXME: We need vp-aware PromotedInteger functions.
1161 if (IsShift) {
1162 Op1 = GetPromotedInteger(Op: Op1);
1163 if (getTypeAction(VT: Op2.getValueType()) == TargetLowering::TypePromoteInteger)
1164 Op2 = ZExtPromotedInteger(Op: Op2);
1165 } else {
1166 Op1 = SExtPromotedInteger(Op: Op1);
1167 Op2 = SExtPromotedInteger(Op: Op2);
1168 }
1169 EVT PromotedType = Op1.getValueType();
1170 unsigned NewBits = PromotedType.getScalarSizeInBits();
1171
1172 // Shift cannot use a min/max expansion, we can't detect overflow if all of
1173 // the bits have been shifted out.
1174 if (IsShift || matcher.isOperationLegal(Opcode, PromotedType)) {
1175 unsigned ShiftOp;
1176 switch (Opcode) {
1177 case ISD::SADDSAT:
1178 case ISD::SSUBSAT:
1179 case ISD::SSHLSAT:
1180 ShiftOp = ISD::SRA;
1181 break;
1182 case ISD::USHLSAT:
1183 ShiftOp = ISD::SRL;
1184 break;
1185 default:
1186 llvm_unreachable("Expected opcode to be signed or unsigned saturation "
1187 "addition, subtraction or left shift");
1188 }
1189
1190 unsigned SHLAmount = NewBits - OldBits;
1191 SDValue ShiftAmount =
1192 DAG.getShiftAmountConstant(Val: SHLAmount, VT: PromotedType, DL: dl);
1193 Op1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1, N2: ShiftAmount);
1194 if (!IsShift)
1195 Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
1196
1197 SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
1198 return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
1199 }
1200
1201 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
1202 APInt MinVal = APInt::getSignedMinValue(numBits: OldBits).sext(width: NewBits);
1203 APInt MaxVal = APInt::getSignedMaxValue(numBits: OldBits).sext(width: NewBits);
1204 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT: PromotedType);
1205 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: PromotedType);
1206 SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
1207 Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
1208 Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
1209 return Result;
1210}
1211
1212SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
1213 // Can just promote the operands then continue with operation.
1214 SDLoc dl(N);
1215 SDValue Op1Promoted, Op2Promoted;
1216 bool Signed =
1217 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
1218 bool Saturating =
1219 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
1220 if (Signed) {
1221 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1222 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1223 } else {
1224 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1225 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1226 }
1227 EVT OldType = N->getOperand(Num: 0).getValueType();
1228 EVT PromotedType = Op1Promoted.getValueType();
1229 unsigned DiffSize =
1230 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
1231
1232 if (Saturating) {
1233 // Promoting the operand and result values changes the saturation width,
1234 // which is extends the values that we clamp to on saturation. This could be
1235 // resolved by shifting one of the operands the same amount, which would
1236 // also shift the result we compare against, then shifting back.
1237 Op1Promoted =
1238 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1239 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1240 SDValue Result = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1241 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1242 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1243 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result,
1244 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1245 }
1246 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted, N2: Op2Promoted,
1247 N3: N->getOperand(Num: 2));
1248}
1249
1250static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
1251 unsigned SatW, bool Signed,
1252 const TargetLowering &TLI,
1253 SelectionDAG &DAG) {
1254 EVT VT = V.getValueType();
1255 unsigned VTW = VT.getScalarSizeInBits();
1256
1257 if (!Signed) {
1258 // Saturate to the unsigned maximum by getting the minimum of V and the
1259 // maximum.
1260 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT, N1: V,
1261 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW),
1262 DL: dl, VT));
1263 }
1264
1265 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
1266 // signed minimum of it and V.
1267 V = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT, N1: V,
1268 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW - 1),
1269 DL: dl, VT));
1270 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
1271 // signed maximum of it and V.
1272 V = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT, N1: V,
1273 N2: DAG.getConstant(Val: APInt::getHighBitsSet(numBits: VTW, hiBitsSet: VTW - SatW + 1),
1274 DL: dl, VT));
1275 return V;
1276}
1277
1278static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
1279 unsigned Scale, const TargetLowering &TLI,
1280 SelectionDAG &DAG, unsigned SatW = 0) {
1281 EVT VT = LHS.getValueType();
1282 unsigned VTSize = VT.getScalarSizeInBits();
1283 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1284 N->getOpcode() == ISD::SDIVFIXSAT;
1285 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1286 N->getOpcode() == ISD::UDIVFIXSAT;
1287
1288 SDLoc dl(N);
1289 // Widen the types by a factor of two. This is guaranteed to expand, since it
1290 // will always have enough high bits in the LHS to shift into.
1291 EVT WideVT = VT.changeElementType(
1292 Context&: *DAG.getContext(), EltVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: VTSize * 2));
1293 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL: dl, VT: WideVT);
1294 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL: dl, VT: WideVT);
1295 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS, RHS, Scale,
1296 DAG);
1297 assert(Res && "Expanding DIVFIX with wide type failed?");
1298 if (Saturating) {
1299 // If the caller has told us to saturate at something less, use that width
1300 // instead of the type before doubling. However, it cannot be more than
1301 // what we just widened!
1302 assert(SatW <= VTSize &&
1303 "Tried to saturate to more than the original type?");
1304 Res = SaturateWidenedDIVFIX(V: Res, dl, SatW: SatW == 0 ? VTSize : SatW, Signed,
1305 TLI, DAG);
1306 }
1307 return DAG.getZExtOrTrunc(Op: Res, DL: dl, VT);
1308}
1309
1310SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1311 SDLoc dl(N);
1312 SDValue Op1Promoted, Op2Promoted;
1313 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1314 N->getOpcode() == ISD::SDIVFIXSAT;
1315 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1316 N->getOpcode() == ISD::UDIVFIXSAT;
1317 if (Signed) {
1318 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1319 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1320 } else {
1321 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1322 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1323 }
1324 EVT PromotedType = Op1Promoted.getValueType();
1325 unsigned Scale = N->getConstantOperandVal(Num: 2);
1326
1327 // If the type is already legal and the operation is legal in that type, we
1328 // should not early expand.
1329 if (TLI.isTypeLegal(VT: PromotedType)) {
1330 TargetLowering::LegalizeAction Action =
1331 TLI.getFixedPointOperationAction(Op: N->getOpcode(), VT: PromotedType, Scale);
1332 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1333 unsigned Diff = PromotedType.getScalarSizeInBits() -
1334 N->getValueType(ResNo: 0).getScalarSizeInBits();
1335 if (Saturating)
1336 Op1Promoted =
1337 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1338 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1339 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1340 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1341 if (Saturating)
1342 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL: dl, VT: PromotedType, N1: Res,
1343 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1344 return Res;
1345 }
1346 }
1347
1348 // See if we can perform the division in this type without expanding.
1349 if (SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: Op1Promoted,
1350 RHS: Op2Promoted, Scale, DAG)) {
1351 if (Saturating)
1352 Res = SaturateWidenedDIVFIX(V: Res, dl,
1353 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits(),
1354 Signed, TLI, DAG);
1355 return Res;
1356 }
1357 // If we cannot, expand it to twice the type width. If we are saturating, give
1358 // it the original width as a saturating width so we don't need to emit
1359 // two saturations.
1360 return earlyExpandDIVFIX(N, LHS: Op1Promoted, RHS: Op2Promoted, Scale, TLI, DAG,
1361 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits());
1362}
1363
1364SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1365 if (ResNo == 1)
1366 return PromoteIntRes_Overflow(N);
1367
1368 // The operation overflowed iff the result in the larger type is not the
1369 // sign extension of its truncation to the original type.
1370 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1371 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1372 EVT OVT = N->getOperand(Num: 0).getValueType();
1373 EVT NVT = LHS.getValueType();
1374 SDLoc dl(N);
1375
1376 // Do the arithmetic in the larger type.
1377 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1378 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1379
1380 // Calculate the overflow flag: sign extend the arithmetic result from
1381 // the original type.
1382 SDValue Ofl = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1383 N2: DAG.getValueType(OVT));
1384 // Overflowed if and only if this is not equal to Res.
1385 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1386
1387 // Use the calculated overflow everywhere.
1388 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1389
1390 return Res;
1391}
1392
1393SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
1394 EVT PromotedResultTy =
1395 TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1396 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: PromotedResultTy,
1397 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
1398}
1399
1400SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1401 SDValue Mask = N->getOperand(Num: 0);
1402
1403 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1404 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1405
1406 unsigned Opcode = N->getOpcode();
1407 if (Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE)
1408 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS,
1409 N4: N->getOperand(Num: 3));
1410 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS);
1411}
1412
1413SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1414 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1415 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 3));
1416 return DAG.getNode(Opcode: ISD::SELECT_CC, DL: SDLoc(N),
1417 VT: LHS.getValueType(), N1: N->getOperand(Num: 0),
1418 N2: N->getOperand(Num: 1), N3: LHS, N4: RHS, N5: N->getOperand(Num: 4));
1419}
1420
1421SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1422 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1423 EVT InVT = N->getOperand(Num: OpNo).getValueType();
1424 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1425
1426 EVT SVT = getSetCCResultType(VT: InVT);
1427
1428 // If we got back a type that needs to be promoted, this likely means the
1429 // the input type also needs to be promoted. So get the promoted type for
1430 // the input and try the query again.
1431 if (getTypeAction(VT: SVT) == TargetLowering::TypePromoteInteger) {
1432 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
1433 InVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
1434 SVT = getSetCCResultType(VT: InVT);
1435 } else {
1436 // Input type isn't promoted, just use the default promoted type.
1437 SVT = NVT;
1438 }
1439 }
1440
1441 SDLoc dl(N);
1442 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1443 "Vector compare must return a vector result!");
1444
1445 // Get the SETCC result using the canonical SETCC type.
1446 SDValue SetCC;
1447 if (N->isStrictFPOpcode()) {
1448 SDVTList VTs = DAG.getVTList(VTs: {SVT, MVT::Other});
1449 SDValue Opers[] = {N->getOperand(Num: 0), N->getOperand(Num: 1),
1450 N->getOperand(Num: 2), N->getOperand(Num: 3)};
1451 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: VTs, Ops: Opers, Flags: N->getFlags());
1452 // Legalize the chain result - switch anything that used the old chain to
1453 // use the new one.
1454 ReplaceValueWith(From: SDValue(N, 1), To: SetCC.getValue(R: 1));
1455 } else
1456 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: SVT, N1: N->getOperand(Num: 0),
1457 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), Flags: N->getFlags());
1458
1459 // Convert to the expected type.
1460 return DAG.getSExtOrTrunc(Op: SetCC, DL: dl, VT: NVT);
1461}
1462
1463SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
1464 SDLoc DL(N);
1465 SDValue Arg = N->getOperand(Num: 0);
1466 SDValue Test = N->getOperand(Num: 1);
1467 EVT NResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1468 return DAG.getNode(Opcode: ISD::IS_FPCLASS, DL, VT: NResVT, N1: Arg, N2: Test);
1469}
1470
1471SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
1472 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1473 EVT VT = N->getValueType(ResNo: 0);
1474
1475 SDLoc dl(N);
1476 SDValue Res =
1477 DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: NVT), N: N->getOperand(Num: 0));
1478
1479 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1480 return Res.getValue(R: 1);
1481}
1482
1483SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1484 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1485 SDValue RHS = N->getOperand(Num: 1);
1486 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1487 RHS = ZExtPromotedInteger(Op: RHS);
1488 if (N->getOpcode() != ISD::VP_SHL)
1489 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1490
1491 SDValue Mask = N->getOperand(Num: 2);
1492 SDValue EVL = N->getOperand(Num: 3);
1493 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1494 N3: Mask, N4: EVL);
1495}
1496
1497SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1498 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
1499 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: SDLoc(N),
1500 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
1501}
1502
1503SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1504 // The input may have strange things in the top bits of the registers, but
1505 // these operations don't care. They may have weird bits going out, but
1506 // that too is okay if they are integer operations.
1507 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1508 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1509 if (N->getNumOperands() == 2)
1510 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1511 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1512 assert(N->isVPOpcode() && "Expected VP opcode");
1513 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1514 N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
1515}
1516
1517SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1518 // Sign extend the input.
1519 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1520 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1521 if (N->getNumOperands() == 2)
1522 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1523 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1524 assert(N->isVPOpcode() && "Expected VP opcode");
1525 SDValue Mask = N->getOperand(Num: 2);
1526 SDValue EVL = N->getOperand(Num: 3);
1527 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1528 N3: Mask, N4: EVL);
1529}
1530
1531SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1532 // Zero extend the input.
1533 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1534 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1535 if (N->getNumOperands() == 2)
1536 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1537 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1538 assert(N->isVPOpcode() && "Expected VP opcode");
1539 // Zero extend the input.
1540 SDValue Mask = N->getOperand(Num: 2);
1541 SDValue EVL = N->getOperand(Num: 3);
1542 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1543 N3: Mask, N4: EVL);
1544}
1545
1546SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1547 SDValue LHS = N->getOperand(Num: 0);
1548 SDValue RHS = N->getOperand(Num: 1);
1549
1550 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1551 // whatever is best for the target and the promoted operands.
1552 SExtOrZExtPromotedOperands(LHS, RHS);
1553
1554 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N),
1555 VT: LHS.getValueType(), N1: LHS, N2: RHS);
1556}
1557
1558SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1559 // The input value must be properly sign extended.
1560 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1561 SDValue RHS = N->getOperand(Num: 1);
1562 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1563 RHS = ZExtPromotedInteger(Op: RHS);
1564 if (N->getOpcode() != ISD::VP_SRA)
1565 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1566
1567 SDValue Mask = N->getOperand(Num: 2);
1568 SDValue EVL = N->getOperand(Num: 3);
1569 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1570 N3: Mask, N4: EVL);
1571}
1572
1573SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1574 SDValue RHS = N->getOperand(Num: 1);
1575 // The input value must be properly zero extended.
1576 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1577 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1578 RHS = ZExtPromotedInteger(Op: RHS);
1579 if (N->getOpcode() != ISD::VP_SRL)
1580 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1581
1582 SDValue Mask = N->getOperand(Num: 2);
1583 SDValue EVL = N->getOperand(Num: 3);
1584 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1585 N3: Mask, N4: EVL);
1586}
1587
1588SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1589 // Lower the rotate to shifts and ORs which can be promoted.
1590 SDValue Res = TLI.expandROT(N, AllowVectorOps: true /*AllowVectorOps*/, DAG);
1591 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1592 return SDValue();
1593}
1594
1595SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1596 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1597 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1598 SDValue Amt = N->getOperand(Num: 2);
1599 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1600 Amt = ZExtPromotedInteger(Op: Amt);
1601 EVT AmtVT = Amt.getValueType();
1602
1603 SDLoc DL(N);
1604 EVT OldVT = N->getOperand(Num: 0).getValueType();
1605 EVT VT = Lo.getValueType();
1606 unsigned Opcode = N->getOpcode();
1607 bool IsFSHR = Opcode == ISD::FSHR;
1608 unsigned OldBits = OldVT.getScalarSizeInBits();
1609 unsigned NewBits = VT.getScalarSizeInBits();
1610
1611 // Amount has to be interpreted modulo the old bit width.
1612 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1613 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1614
1615 // If the promoted type is twice the size (or more), then we use the
1616 // traditional funnel 'double' shift codegen. This isn't necessary if the
1617 // shift amount is constant.
1618 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1619 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1620 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1621 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1622 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1623 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: HiShift);
1624 Lo = DAG.getZeroExtendInReg(Op: Lo, DL, VT: OldVT);
1625 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1626 Res = DAG.getNode(Opcode: IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1627 if (!IsFSHR)
1628 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1629 return Res;
1630 }
1631
1632 // Shift Lo up to occupy the upper bits of the promoted type.
1633 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Lo,
1634 N2: DAG.getShiftAmountConstant(Val: NewBits - OldBits, VT, DL));
1635
1636 // Increase Amount to shift the result into the lower bits of the promoted
1637 // type.
1638 if (IsFSHR)
1639 Amt = DAG.getNode(Opcode: ISD::ADD, DL, VT: AmtVT, N1: Amt,
1640 N2: DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT));
1641
1642 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt);
1643}
1644
1645// A vp version of PromoteIntRes_FunnelShift.
1646SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
1647 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1648 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1649 SDValue Amt = N->getOperand(Num: 2);
1650 SDValue Mask = N->getOperand(Num: 3);
1651 SDValue EVL = N->getOperand(Num: 4);
1652 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1653 Amt = ZExtPromotedInteger(Op: Amt);
1654 EVT AmtVT = Amt.getValueType();
1655
1656 SDLoc DL(N);
1657 EVT OldVT = N->getOperand(Num: 0).getValueType();
1658 EVT VT = Lo.getValueType();
1659 unsigned Opcode = N->getOpcode();
1660 bool IsFSHR = Opcode == ISD::VP_FSHR;
1661 unsigned OldBits = OldVT.getScalarSizeInBits();
1662 unsigned NewBits = VT.getScalarSizeInBits();
1663
1664 // Amount has to be interpreted modulo the old bit width.
1665 Amt = DAG.getNode(Opcode: ISD::VP_UREM, DL, VT: AmtVT, N1: Amt,
1666 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT), N3: Mask, N4: EVL);
1667
1668 // If the promoted type is twice the size (or more), then we use the
1669 // traditional funnel 'double' shift codegen. This isn't necessary if the
1670 // shift amount is constant.
1671 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1672 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1673 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1674 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1675 SDValue HiShift = DAG.getConstant(Val: OldBits, DL, VT);
1676 Hi = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Hi, N2: HiShift, N3: Mask, N4: EVL);
1677 Lo = DAG.getVPZeroExtendInReg(Op: Lo, Mask, EVL, DL, VT: OldVT);
1678 SDValue Res = DAG.getNode(Opcode: ISD::VP_OR, DL, VT, N1: Hi, N2: Lo, N3: Mask, N4: EVL);
1679 Res = DAG.getNode(Opcode: IsFSHR ? ISD::VP_SRL : ISD::VP_SHL, DL, VT, N1: Res, N2: Amt,
1680 N3: Mask, N4: EVL);
1681 if (!IsFSHR)
1682 Res = DAG.getNode(Opcode: ISD::VP_SRL, DL, VT, N1: Res, N2: HiShift, N3: Mask, N4: EVL);
1683 return Res;
1684 }
1685
1686 // Shift Lo up to occupy the upper bits of the promoted type.
1687 SDValue ShiftOffset = DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT);
1688 Lo = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Lo, N2: ShiftOffset, N3: Mask, N4: EVL);
1689
1690 // Increase Amount to shift the result into the lower bits of the promoted
1691 // type.
1692 if (IsFSHR)
1693 Amt = DAG.getNode(Opcode: ISD::VP_ADD, DL, VT: AmtVT, N1: Amt, N2: ShiftOffset, N3: Mask, N4: EVL);
1694
1695 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt, N4: Mask, N5: EVL);
1696}
1697
1698SDValue DAGTypeLegalizer::PromoteIntRes_CLMUL(SDNode *N) {
1699 unsigned Opcode = N->getOpcode();
1700
1701 SDLoc DL(N);
1702 EVT OldVT = N->getOperand(Num: 0).getValueType();
1703 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1704
1705 if (Opcode == ISD::CLMUL) {
1706 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CLMUL, VT)) {
1707 if (SDValue Res = TLI.expandCLMUL(N, DAG))
1708 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1709 }
1710 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1711 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1712 return DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1713 }
1714
1715 SDValue X = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1716 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1717
1718 unsigned OldBits = OldVT.getScalarSizeInBits();
1719 unsigned NewBits = VT.getScalarSizeInBits();
1720 if (NewBits < 2 * OldBits) {
1721 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1722 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1723 SDValue Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1724 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1725 SDValue Clmulh = DAG.getNode(Opcode: ISD::CLMULH, DL, VT, N1: X, N2: Y);
1726 ShAmt = Opcode == ISD::CLMULH ? NewBits - OldBits : NewBits - OldBits + 1;
1727 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Clmulh,
1728 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1729 return DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Lo, N2: Hi);
1730 }
1731
1732 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1733 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1734 return DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1735 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1736}
1737
1738SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1739 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1740 SDValue Res;
1741 SDValue InOp = N->getOperand(Num: 0);
1742 SDLoc dl(N);
1743
1744 switch (getTypeAction(VT: InOp.getValueType())) {
1745 default: llvm_unreachable("Unknown type action!");
1746 case TargetLowering::TypeLegal:
1747 case TargetLowering::TypeExpandInteger:
1748 Res = InOp;
1749 break;
1750 case TargetLowering::TypePromoteInteger:
1751 Res = GetPromotedInteger(Op: InOp);
1752 break;
1753 case TargetLowering::TypeSplitVector: {
1754 EVT InVT = InOp.getValueType();
1755 assert(InVT.isVector() && "Cannot split scalar types");
1756 ElementCount NumElts = InVT.getVectorElementCount();
1757 assert(NumElts == NVT.getVectorElementCount() &&
1758 "Dst and Src must have the same number of elements");
1759 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1760 "Promoted vector type must be a power of two");
1761
1762 SDValue EOp1, EOp2;
1763 GetSplitVector(Op: InOp, Lo&: EOp1, Hi&: EOp2);
1764
1765 EVT HalfNVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getScalarType(),
1766 EC: NumElts.divideCoefficientBy(RHS: 2));
1767 if (N->getOpcode() == ISD::TRUNCATE) {
1768 EOp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp1);
1769 EOp2 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp2);
1770 } else {
1771 assert(N->getOpcode() == ISD::VP_TRUNCATE &&
1772 "Expected VP_TRUNCATE opcode");
1773 SDValue MaskLo, MaskHi, EVLLo, EVLHi;
1774 std::tie(args&: MaskLo, args&: MaskHi) = SplitMask(Mask: N->getOperand(Num: 1));
1775 std::tie(args&: EVLLo, args&: EVLHi) =
1776 DAG.SplitEVL(N: N->getOperand(Num: 2), VecVT: N->getValueType(ResNo: 0), DL: dl);
1777 EOp1 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp1, N2: MaskLo, N3: EVLLo);
1778 EOp2 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp2, N2: MaskHi, N3: EVLHi);
1779 }
1780 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl, VT: NVT, N1: EOp1, N2: EOp2);
1781 }
1782 // TODO: VP_TRUNCATE need to handle when TypeWidenVector access to some
1783 // targets.
1784 case TargetLowering::TypeWidenVector: {
1785 SDValue WideInOp = GetWidenedVector(Op: InOp);
1786
1787 // Truncate widened InOp.
1788 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1789 EVT TruncVT = EVT::getVectorVT(Context&: *DAG.getContext(),
1790 VT: N->getValueType(ResNo: 0).getScalarType(), NumElements: NumElem);
1791 SDValue WideTrunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: TruncVT, Operand: WideInOp);
1792
1793 // Zero extend so that the elements are of same type as those of NVT
1794 EVT ExtVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getVectorElementType(),
1795 NumElements: NumElem);
1796 SDValue WideExt = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: ExtVT, Operand: WideTrunc);
1797
1798 // Extract the low NVT subvector.
1799 SDValue ZeroIdx = DAG.getVectorIdxConstant(Val: 0, DL: dl);
1800 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NVT, N1: WideExt, N2: ZeroIdx);
1801 }
1802 }
1803
1804 // Truncate to NVT instead of VT
1805 if (N->getOpcode() == ISD::VP_TRUNCATE)
1806 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: NVT, N1: Res, N2: N->getOperand(Num: 1),
1807 N3: N->getOperand(Num: 2));
1808 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Res);
1809}
1810
1811SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1812 if (ResNo == 1)
1813 return PromoteIntRes_Overflow(N);
1814
1815 // The operation overflowed iff the result in the larger type is not the
1816 // zero extension of its truncation to the original type.
1817 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1818 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1819 EVT OVT = N->getOperand(Num: 0).getValueType();
1820 EVT NVT = LHS.getValueType();
1821 SDLoc dl(N);
1822
1823 // Do the arithmetic in the larger type.
1824 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1825 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1826
1827 // Calculate the overflow flag: zero extend the arithmetic result from
1828 // the original type.
1829 SDValue Ofl = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: OVT);
1830 // Overflowed if and only if this is not equal to Res.
1831 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1832
1833 // Use the calculated overflow everywhere.
1834 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1835
1836 return Res;
1837}
1838
1839// Handle promotion for the ADDE/SUBE/UADDO_CARRY/USUBO_CARRY nodes. Notice that
1840// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1841// the UADDO_CARRY/USUBO_CARRY nodes in that the third operand is carry Boolean.
1842SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO_CARRY(SDNode *N,
1843 unsigned ResNo) {
1844 if (ResNo == 1)
1845 return PromoteIntRes_Overflow(N);
1846
1847 // We need to sign-extend the operands so the carry value computed by the
1848 // wide operation will be equivalent to the carry value computed by the
1849 // narrow operation.
1850 // An UADDO_CARRY can generate carry only if any of the operands has its
1851 // most significant bit set. Sign extension propagates the most significant
1852 // bit into the higher bits which means the extra bit that the narrow
1853 // addition would need (i.e. the carry) will be propagated through the higher
1854 // bits of the wide addition.
1855 // A USUBO_CARRY can generate borrow only if LHS < RHS and this property will
1856 // be preserved by sign extension.
1857 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1858 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1859
1860 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(ResNo: 1)};
1861
1862 // Do the arithmetic in the wide type.
1863 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VTList: DAG.getVTList(VTs: ValueVTs),
1864 N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
1865
1866 // Update the users of the original carry/borrow value.
1867 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1868
1869 return SDValue(Res.getNode(), 0);
1870}
1871
1872SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1873 unsigned ResNo) {
1874 assert(ResNo == 1 && "Don't know how to promote other results yet.");
1875 return PromoteIntRes_Overflow(N);
1876}
1877
1878SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1879 EVT OVT = N->getValueType(ResNo: 0);
1880 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1881
1882 // If a larger ABS or SMAX isn't supported by the target, try to expand now.
1883 // If we expand later we'll end up sign extending more than just the sra input
1884 // in sra+xor+sub expansion.
1885 if (!OVT.isVector() &&
1886 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS, VT: NVT) &&
1887 !TLI.isOperationLegal(Op: ISD::SMAX, VT: NVT)) {
1888 if (SDValue Res = TLI.expandABS(N, DAG))
1889 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Res);
1890 }
1891
1892 SDValue Op0 = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1893 return DAG.getNode(Opcode: ISD::ABS, DL: SDLoc(N), VT: Op0.getValueType(), Operand: Op0);
1894}
1895
1896SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1897 // Promote the overflow bit trivially.
1898 if (ResNo == 1)
1899 return PromoteIntRes_Overflow(N);
1900
1901 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
1902 SDLoc DL(N);
1903 EVT SmallVT = LHS.getValueType();
1904
1905 // To determine if the result overflowed in a larger type, we extend the
1906 // input to the larger type, do the multiply (checking if it overflows),
1907 // then also check the high bits of the result to see if overflow happened
1908 // there.
1909 if (N->getOpcode() == ISD::SMULO) {
1910 LHS = SExtPromotedInteger(Op: LHS);
1911 RHS = SExtPromotedInteger(Op: RHS);
1912 } else {
1913 LHS = ZExtPromotedInteger(Op: LHS);
1914 RHS = ZExtPromotedInteger(Op: RHS);
1915 }
1916 SDVTList VTs = DAG.getVTList(VT1: LHS.getValueType(), VT2: N->getValueType(ResNo: 1));
1917 SDValue Mul = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N1: LHS, N2: RHS);
1918
1919 // Overflow occurred if it occurred in the larger type, or if the high part
1920 // of the result does not zero/sign-extend the low part. Check this second
1921 // possibility first.
1922 SDValue Overflow;
1923 if (N->getOpcode() == ISD::UMULO) {
1924 // Unsigned overflow occurred if the high part is non-zero.
1925 unsigned Shift = SmallVT.getScalarSizeInBits();
1926 SDValue Hi =
1927 DAG.getNode(Opcode: ISD::SRL, DL, VT: Mul.getValueType(), N1: Mul,
1928 N2: DAG.getShiftAmountConstant(Val: Shift, VT: Mul.getValueType(), DL));
1929 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: Hi,
1930 RHS: DAG.getConstant(Val: 0, DL, VT: Hi.getValueType()),
1931 Cond: ISD::SETNE);
1932 } else {
1933 // Signed overflow occurred if the high part does not sign extend the low.
1934 SDValue SExt = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: Mul.getValueType(),
1935 N1: Mul, N2: DAG.getValueType(SmallVT));
1936 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: SExt, RHS: Mul, Cond: ISD::SETNE);
1937 }
1938
1939 // The only other way for overflow to occur is if the multiplication in the
1940 // larger type itself overflowed.
1941 Overflow = DAG.getNode(Opcode: ISD::OR, DL, VT: N->getValueType(ResNo: 1), N1: Overflow,
1942 N2: SDValue(Mul.getNode(), 1));
1943
1944 // Use the calculated overflow everywhere.
1945 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
1946 return Mul;
1947}
1948
1949SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1950 return DAG.getUNDEF(VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
1951 VT: N->getValueType(ResNo: 0)));
1952}
1953
1954SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1955 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1956
1957 const APInt &MulImm = N->getConstantOperandAPInt(Num: 0);
1958 return DAG.getVScale(DL: SDLoc(N), VT, MulImm: MulImm.sext(width: VT.getSizeInBits()));
1959}
1960
1961SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1962 SDValue Chain = N->getOperand(Num: 0); // Get the chain.
1963 SDValue Ptr = N->getOperand(Num: 1); // Get the pointer.
1964 EVT VT = N->getValueType(ResNo: 0);
1965 SDLoc dl(N);
1966
1967 MVT RegVT = TLI.getRegisterType(Context&: *DAG.getContext(), VT);
1968 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
1969 // The argument is passed as NumRegs registers of type RegVT.
1970
1971 SmallVector<SDValue, 8> Parts(NumRegs);
1972 for (unsigned i = 0; i < NumRegs; ++i) {
1973 Parts[i] = DAG.getVAArg(VT: RegVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2),
1974 Align: N->getConstantOperandVal(Num: 3));
1975 Chain = Parts[i].getValue(R: 1);
1976 }
1977
1978 // Handle endianness of the load.
1979 if (DAG.getDataLayout().isBigEndian())
1980 std::reverse(first: Parts.begin(), last: Parts.end());
1981
1982 // Assemble the parts in the promoted type.
1983 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1984 SDValue Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[0]);
1985 for (unsigned i = 1; i < NumRegs; ++i) {
1986 SDValue Part = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[i]);
1987 // Shift it to the right position and "or" it in.
1988 Part = DAG.getNode(
1989 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Part,
1990 N2: DAG.getShiftAmountConstant(Val: i * RegVT.getSizeInBits(), VT: NVT, DL: dl));
1991 Res = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Res, N2: Part);
1992 }
1993
1994 // Modified the chain result - switch anything that used the old chain to
1995 // use the new one.
1996 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
1997
1998 return Res;
1999}
2000
2001//===----------------------------------------------------------------------===//
2002// Integer Operand Promotion
2003//===----------------------------------------------------------------------===//
2004
2005/// PromoteIntegerOperand - This method is called when the specified operand of
2006/// the specified node is found to need promotion. At this point, all of the
2007/// result types of the node are known to be legal, but other operands of the
2008/// node may need promotion or expansion as well as the specified one.
2009bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
2010 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG));
2011 SDValue Res = SDValue();
2012 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false)) {
2013 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
2014 return false;
2015 }
2016
2017 switch (N->getOpcode()) {
2018 default:
2019 #ifndef NDEBUG
2020 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
2021 N->dump(&DAG); dbgs() << "\n";
2022 #endif
2023 report_fatal_error(reason: "Do not know how to promote this operator's operand!");
2024
2025 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
2026 case ISD::ANY_EXTEND_VECTOR_INREG:
2027 Res = PromoteIntOp_ANY_EXTEND_VECTOR_INREG(N);
2028 break;
2029 case ISD::ATOMIC_STORE:
2030 Res = PromoteIntOp_ATOMIC_STORE(N: cast<AtomicSDNode>(Val: N));
2031 break;
2032 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
2033 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
2034 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
2035 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
2036 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
2037 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
2038 case ISD::COND_LOOP:
2039 Res = PromoteIntOp_COND_LOOP(N, OpNo);
2040 break;
2041 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
2042 case ISD::FAKE_USE:
2043 Res = PromoteIntOp_FAKE_USE(N);
2044 break;
2045 case ISD::INSERT_VECTOR_ELT:
2046 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
2047 break;
2048 case ISD::SPLAT_VECTOR:
2049 case ISD::SCALAR_TO_VECTOR:
2050 Res = PromoteIntOp_ScalarOp(N);
2051 break;
2052 case ISD::VSELECT:
2053 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
2054 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
2055 case ISD::VP_SETCC:
2056 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
2057 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
2058 case ISD::VP_SIGN_EXTEND: Res = PromoteIntOp_VP_SIGN_EXTEND(N); break;
2059 case ISD::VP_SINT_TO_FP:
2060 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
2061 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
2062 case ISD::STORE: Res = PromoteIntOp_STORE(N: cast<StoreSDNode>(Val: N),
2063 OpNo); break;
2064 case ISD::VP_STORE:
2065 Res = PromoteIntOp_VP_STORE(N: cast<VPStoreSDNode>(Val: N), OpNo);
2066 break;
2067 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(N: cast<MaskedStoreSDNode>(Val: N),
2068 OpNo); break;
2069 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(N: cast<MaskedLoadSDNode>(Val: N),
2070 OpNo); break;
2071 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(N: cast<MaskedGatherSDNode>(Val: N),
2072 OpNo); break;
2073 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(N: cast<MaskedScatterSDNode>(Val: N),
2074 OpNo); break;
2075 case ISD::VECTOR_COMPRESS:
2076 Res = PromoteIntOp_VECTOR_COMPRESS(N, OpNo);
2077 break;
2078 case ISD::VP_TRUNCATE:
2079 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
2080 case ISD::BF16_TO_FP:
2081 case ISD::FP16_TO_FP:
2082 case ISD::VP_UINT_TO_FP:
2083 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
2084 case ISD::CONVERT_FROM_ARBITRARY_FP:
2085 Res = PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(N);
2086 break;
2087 case ISD::STRICT_FP16_TO_FP:
2088 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
2089 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
2090 case ISD::VP_ZERO_EXTEND: Res = PromoteIntOp_VP_ZERO_EXTEND(N); break;
2091 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
2092 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
2093
2094 case ISD::SHL:
2095 case ISD::SRA:
2096 case ISD::SRL:
2097 case ISD::ROTL:
2098 case ISD::ROTR:
2099 case ISD::SSHLSAT:
2100 case ISD::USHLSAT:
2101 Res = PromoteIntOp_Shift(N);
2102 break;
2103
2104 case ISD::SCMP:
2105 case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
2106
2107 case ISD::FSHL:
2108 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
2109
2110 case ISD::FRAMEADDR:
2111 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
2112
2113 case ISD::SMULFIX:
2114 case ISD::SMULFIXSAT:
2115 case ISD::UMULFIX:
2116 case ISD::UMULFIXSAT:
2117 case ISD::SDIVFIX:
2118 case ISD::SDIVFIXSAT:
2119 case ISD::UDIVFIX:
2120 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
2121 case ISD::FPOWI:
2122 case ISD::STRICT_FPOWI:
2123 case ISD::FLDEXP:
2124 case ISD::STRICT_FLDEXP: Res = PromoteIntOp_ExpOp(N); break;
2125 case ISD::VECREDUCE_ADD:
2126 case ISD::VECREDUCE_MUL:
2127 case ISD::VECREDUCE_AND:
2128 case ISD::VECREDUCE_OR:
2129 case ISD::VECREDUCE_XOR:
2130 case ISD::VECREDUCE_SMAX:
2131 case ISD::VECREDUCE_SMIN:
2132 case ISD::VECREDUCE_UMAX:
2133 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
2134 case ISD::VP_REDUCE_ADD:
2135 case ISD::VP_REDUCE_MUL:
2136 case ISD::VP_REDUCE_AND:
2137 case ISD::VP_REDUCE_OR:
2138 case ISD::VP_REDUCE_XOR:
2139 case ISD::VP_REDUCE_SMAX:
2140 case ISD::VP_REDUCE_SMIN:
2141 case ISD::VP_REDUCE_UMAX:
2142 case ISD::VP_REDUCE_UMIN:
2143 Res = PromoteIntOp_VP_REDUCE(N, OpNo);
2144 break;
2145
2146 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
2147 case ISD::STACKMAP:
2148 Res = PromoteIntOp_STACKMAP(N, OpNo);
2149 break;
2150 case ISD::PATCHPOINT:
2151 Res = PromoteIntOp_PATCHPOINT(N, OpNo);
2152 break;
2153 case ISD::WRITE_REGISTER:
2154 Res = PromoteIntOp_WRITE_REGISTER(N, OpNo);
2155 break;
2156 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
2157 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
2158 Res = PromoteIntOp_VP_STRIDED(N, OpNo);
2159 break;
2160 case ISD::EXPERIMENTAL_VP_SPLICE:
2161 Res = PromoteIntOp_VP_SPLICE(N, OpNo);
2162 break;
2163 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
2164 Res = PromoteIntOp_VECTOR_HISTOGRAM(N, OpNo);
2165 break;
2166 case ISD::VECTOR_FIND_LAST_ACTIVE:
2167 case ISD::CTTZ_ELTS:
2168 case ISD::CTTZ_ELTS_ZERO_POISON:
2169 Res = PromoteIntOp_UnaryBooleanVectorOp(N, OpNo);
2170 break;
2171 case ISD::GET_ACTIVE_LANE_MASK:
2172 Res = PromoteIntOp_GET_ACTIVE_LANE_MASK(N);
2173 break;
2174 case ISD::PARTIAL_REDUCE_UMLA:
2175 case ISD::PARTIAL_REDUCE_SMLA:
2176 case ISD::PARTIAL_REDUCE_SUMLA:
2177 Res = PromoteIntOp_PARTIAL_REDUCE_MLA(N);
2178 break;
2179 }
2180
2181 // If the result is null, the sub-method took care of registering results etc.
2182 if (!Res.getNode()) return false;
2183
2184 // If the result is N, the sub-method updated N in place. Tell the legalizer
2185 // core about this.
2186 if (Res.getNode() == N)
2187 return true;
2188
2189 const bool IsStrictFp = N->isStrictFPOpcode();
2190 assert(Res.getValueType() == N->getValueType(0) &&
2191 N->getNumValues() == (IsStrictFp ? 2 : 1) &&
2192 "Invalid operand expansion");
2193 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
2194 Res.dump());
2195
2196 ReplaceValueWith(From: SDValue(N, 0), To: Res);
2197 if (IsStrictFp)
2198 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res.getNode(), 1));
2199
2200 return false;
2201}
2202
2203// These operands can be either sign extended or zero extended as long as we
2204// treat them the same. If an extension is free, choose that. Otherwise, follow
2205// target preference.
2206void DAGTypeLegalizer::SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS) {
2207 SDValue OpL = GetPromotedInteger(Op: LHS);
2208 SDValue OpR = GetPromotedInteger(Op: RHS);
2209
2210 if (TLI.isSExtCheaperThanZExt(FromTy: LHS.getValueType(), ToTy: OpL.getValueType())) {
2211 // The target would prefer to promote the comparison operand with sign
2212 // extension. Honor that unless the promoted values are already zero
2213 // extended.
2214 unsigned OpLEffectiveBits =
2215 DAG.computeKnownBits(Op: OpL).countMaxActiveBits();
2216 unsigned OpREffectiveBits =
2217 DAG.computeKnownBits(Op: OpR).countMaxActiveBits();
2218 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2219 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2220 LHS = OpL;
2221 RHS = OpR;
2222 return;
2223 }
2224
2225 // The promoted values aren't zero extended, use a sext_inreg.
2226 LHS = SExtPromotedInteger(Op: LHS);
2227 RHS = SExtPromotedInteger(Op: RHS);
2228 return;
2229 }
2230
2231 // Prefer to promote the comparison operand with zero extension.
2232
2233 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
2234 // than the width of LHS/RHS, we can avoid/ inserting a zext_inreg operation
2235 // that we might not be able to remove.
2236 unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpL);
2237 unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpR);
2238 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2239 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2240 LHS = OpL;
2241 RHS = OpR;
2242 return;
2243 }
2244
2245 // Otherwise, use zext_inreg.
2246 LHS = ZExtPromotedInteger(Op: LHS);
2247 RHS = ZExtPromotedInteger(Op: RHS);
2248}
2249
2250/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
2251/// shared among BR_CC, SELECT_CC, and SETCC handlers.
2252void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
2253 ISD::CondCode CCCode) {
2254 // We have to insert explicit sign or zero extends. Note that we could
2255 // insert sign extends for ALL conditions. For those operations where either
2256 // zero or sign extension would be valid, we ask the target which extension
2257 // it would prefer.
2258
2259 // Signed comparisons always require sign extension.
2260 if (ISD::isSignedIntSetCC(Code: CCCode)) {
2261 LHS = SExtPromotedInteger(Op: LHS);
2262 RHS = SExtPromotedInteger(Op: RHS);
2263 return;
2264 }
2265
2266 assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
2267 "Unknown integer comparison!");
2268
2269 SExtOrZExtPromotedOperands(LHS, RHS);
2270}
2271
2272SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
2273 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2274 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2275}
2276
2277SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND_VECTOR_INREG(SDNode *N) {
2278 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2279 EVT ResVT = N->getValueType(ResNo: 0);
2280 EVT OpVT = Op.getValueType();
2281 EVT NewVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: OpVT.getScalarType(),
2282 NumElements: ResVT.getVectorNumElements());
2283 Op = DAG.getExtractSubvector(DL: SDLoc(Op), VT: NewVT, Vec: Op, Idx: 0);
2284 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: ResVT, Operand: Op);
2285}
2286
2287SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
2288 SDValue Op1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
2289 return DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(),
2290 Chain: N->getChain(), Ptr: Op1, Val: N->getBasePtr(), MMO: N->getMemOperand());
2291}
2292
2293SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
2294 EVT OutVT = N->getValueType(ResNo: 0);
2295 SDValue InOp = N->getOperand(Num: 0);
2296 EVT InVT = InOp.getValueType();
2297 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
2298 SDLoc dl(N);
2299
2300 switch (getTypeAction(VT: InVT)) {
2301 case TargetLowering::TypePromoteInteger: {
2302 // TODO: Handle big endian & vector input type.
2303 if (OutVT.isVector() && !InVT.isVector() &&
2304 DAG.getDataLayout().isLittleEndian()) {
2305 EVT EltVT = OutVT.getVectorElementType();
2306 TypeSize EltSize = EltVT.getSizeInBits();
2307 TypeSize NInSize = NInVT.getSizeInBits();
2308
2309 if (NInSize.hasKnownScalarFactor(RHS: EltSize)) {
2310 unsigned NumEltsWithPadding = NInSize.getKnownScalarFactor(RHS: EltSize);
2311 EVT WideVecVT =
2312 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
2313
2314 if (isTypeLegal(VT: WideVecVT)) {
2315 SDValue Promoted = GetPromotedInteger(Op: InOp);
2316 SDValue Cast = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: WideVecVT, Operand: Promoted);
2317 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Cast,
2318 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
2319 }
2320 }
2321 }
2322
2323 break;
2324 }
2325 default:
2326 break;
2327 }
2328
2329 // This should only occur in unusual situations like bitcasting to an
2330 // x86_fp80, so just turn it into a store+load
2331 return CreateStackStoreLoad(Op: InOp, DestVT: OutVT);
2332}
2333
2334SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
2335 assert(OpNo == 2 && "Don't know how to promote this operand!");
2336
2337 SDValue LHS = N->getOperand(Num: 2);
2338 SDValue RHS = N->getOperand(Num: 3);
2339 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get());
2340
2341 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
2342 // legal types.
2343 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2344 Op2: N->getOperand(Num: 1), Op3: LHS, Op4: RHS, Op5: N->getOperand(Num: 4)),
2345 0);
2346}
2347
2348SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
2349 assert(OpNo == 1 && "only know how to promote condition");
2350
2351 // Promote all the way up to the canonical SetCC type.
2352 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2353
2354 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
2355 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond,
2356 Op3: N->getOperand(Num: 2)), 0);
2357}
2358
2359SDValue DAGTypeLegalizer::PromoteIntOp_COND_LOOP(SDNode *N, unsigned OpNo) {
2360 assert(OpNo == 1 && "only know how to promote condition");
2361
2362 // Promote all the way up to the canonical SetCC type.
2363 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2364
2365 // The chain (Op#0) is always a legal type.
2366 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond), 0);
2367}
2368
2369SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
2370 // Since the result type is legal, the operands must promote to it.
2371 EVT OVT = N->getOperand(Num: 0).getValueType();
2372 SDValue Lo = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2373 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 1));
2374 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
2375 SDLoc dl(N);
2376
2377 Hi = DAG.getNode(
2378 Opcode: ISD::SHL, DL: dl, VT: N->getValueType(ResNo: 0), N1: Hi,
2379 N2: DAG.getShiftAmountConstant(Val: OVT.getSizeInBits(), VT: N->getValueType(ResNo: 0), DL: dl));
2380 return DAG.getNode(Opcode: ISD::OR, DL: dl, VT: N->getValueType(ResNo: 0), N1: Lo, N2: Hi);
2381}
2382
2383SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
2384 // The vector type is legal but the element type is not. This implies
2385 // that the vector is a power-of-two in length and that the element
2386 // type does not have a strange size (eg: it is not i1).
2387 EVT VecVT = N->getValueType(ResNo: 0);
2388 unsigned NumElts = VecVT.getVectorNumElements();
2389 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
2390 "Legal vector of one illegal element?");
2391
2392 // Promote the inserted value. The type does not need to match the
2393 // vector element type. Check that any extra bits introduced will be
2394 // truncated away.
2395 assert(N->getOperand(0).getValueSizeInBits() >=
2396 N->getValueType(0).getScalarSizeInBits() &&
2397 "Type of inserted value narrower than vector element type!");
2398
2399 SmallVector<SDValue, 16> NewOps;
2400 for (unsigned i = 0; i < NumElts; ++i)
2401 NewOps.push_back(Elt: GetPromotedInteger(Op: N->getOperand(Num: i)));
2402
2403 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2404}
2405
2406SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
2407 unsigned OpNo) {
2408 if (OpNo == 1) {
2409 // Promote the inserted value. This is valid because the type does not
2410 // have to match the vector element type.
2411
2412 // Check that any extra bits introduced will be truncated away.
2413 assert(N->getOperand(1).getValueSizeInBits() >=
2414 N->getValueType(0).getScalarSizeInBits() &&
2415 "Type of inserted value narrower than vector element type!");
2416 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2417 Op2: GetPromotedInteger(Op: N->getOperand(Num: 1)),
2418 Op3: N->getOperand(Num: 2)),
2419 0);
2420 }
2421
2422 assert(OpNo == 2 && "Different operand and result vector types?");
2423
2424 // Promote the index.
2425 SDValue Idx = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 2), DL: SDLoc(N),
2426 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
2427 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2428 Op2: N->getOperand(Num: 1), Op3: Idx), 0);
2429}
2430
2431SDValue DAGTypeLegalizer::PromoteIntOp_ScalarOp(SDNode *N) {
2432 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2433
2434 // Integer SPLAT_VECTOR/SCALAR_TO_VECTOR operands are implicitly truncated,
2435 // so just promote the operand in place.
2436 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2437}
2438
2439SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
2440 assert(OpNo == 0 && "Only know how to promote the condition!");
2441 SDValue Cond = N->getOperand(Num: 0);
2442 EVT OpTy = N->getOperand(Num: 1).getValueType();
2443
2444 if (N->getOpcode() == ISD::VSELECT)
2445 if (SDValue Res = WidenVSELECTMask(N))
2446 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
2447 N1: Res, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2448
2449 // Promote all the way up to the canonical SetCC type.
2450 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
2451 Cond = PromoteTargetBoolean(Bool: Cond, ValVT: OpVT);
2452
2453 return SDValue(DAG.UpdateNodeOperands(N, Op1: Cond, Op2: N->getOperand(Num: 1),
2454 Op3: N->getOperand(Num: 2)), 0);
2455}
2456
2457SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
2458 assert(OpNo == 0 && "Don't know how to promote this operand!");
2459
2460 SDValue LHS = N->getOperand(Num: 0);
2461 SDValue RHS = N->getOperand(Num: 1);
2462 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get());
2463
2464 // The CC (#4) and the possible return values (#2 and #3) have legal types.
2465 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2466 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)), 0);
2467}
2468
2469SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
2470 assert(OpNo == 0 && "Don't know how to promote this operand!");
2471
2472 SDValue LHS = N->getOperand(Num: 0);
2473 SDValue RHS = N->getOperand(Num: 1);
2474 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get());
2475
2476 // The CC (#2) is always legal.
2477 if (N->getOpcode() == ISD::SETCC)
2478 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2)), 0);
2479
2480 assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
2481
2482 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2483 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)),
2484 0);
2485}
2486
2487SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
2488 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2489 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2490}
2491
2492SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
2493 SDValue LHS = N->getOperand(Num: 0);
2494 SDValue RHS = N->getOperand(Num: 1);
2495
2496 if (N->getOpcode() == ISD::SCMP) {
2497 LHS = SExtPromotedInteger(Op: LHS);
2498 RHS = SExtPromotedInteger(Op: RHS);
2499 } else {
2500 SExtOrZExtPromotedOperands(LHS, RHS);
2501 }
2502
2503 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS), 0);
2504}
2505
2506SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
2507 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
2508 Op3: ZExtPromotedInteger(Op: N->getOperand(Num: 2))), 0);
2509}
2510
2511SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
2512 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2513 SDLoc dl(N);
2514 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Op);
2515 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Op.getValueType(),
2516 N1: Op, N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
2517}
2518
2519SDValue DAGTypeLegalizer::PromoteIntOp_VP_SIGN_EXTEND(SDNode *N) {
2520 SDLoc dl(N);
2521 EVT VT = N->getValueType(ResNo: 0);
2522 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2523 // FIXME: There is no VP_ANY_EXTEND yet.
2524 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2525 N3: N->getOperand(Num: 2));
2526 unsigned Diff =
2527 VT.getScalarSizeInBits() - N->getOperand(Num: 0).getScalarValueSizeInBits();
2528 SDValue ShAmt = DAG.getShiftAmountConstant(Val: Diff, VT, DL: dl);
2529 // FIXME: There is no VP_SIGN_EXTEND_INREG so use a pair of shifts.
2530 SDValue Shl = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT, N1: Op, N2: ShAmt, N3: N->getOperand(Num: 1),
2531 N4: N->getOperand(Num: 2));
2532 return DAG.getNode(Opcode: ISD::VP_SRA, DL: dl, VT, N1: Shl, N2: ShAmt, N3: N->getOperand(Num: 1),
2533 N4: N->getOperand(Num: 2));
2534}
2535
2536SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
2537 if (N->getOpcode() == ISD::VP_SINT_TO_FP)
2538 return SDValue(DAG.UpdateNodeOperands(N,
2539 Op1: SExtPromotedInteger(Op: N->getOperand(Num: 0)),
2540 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2541 0);
2542 return SDValue(DAG.UpdateNodeOperands(N,
2543 Op: SExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2544}
2545
2546SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
2547 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2548 Op2: SExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2549}
2550
2551SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
2552 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2553 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
2554 SDLoc dl(N);
2555
2556 SDValue Val = GetPromotedInteger(Op: N->getValue()); // Get promoted value.
2557
2558 // Truncate the value and store the result.
2559 return DAG.getTruncStore(Chain: Ch, dl, Val, Ptr,
2560 SVT: N->getMemoryVT(), MMO: N->getMemOperand());
2561}
2562
2563SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
2564 unsigned OpNo) {
2565
2566 assert(OpNo == 1 && "Unexpected operand for promotion");
2567 assert(!N->isIndexed() && "expecting unindexed vp_store!");
2568
2569 SDValue DataOp = GetPromotedInteger(Op: N->getValue());
2570 return DAG.getTruncStoreVP(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Ptr: N->getBasePtr(),
2571 Mask: N->getMask(), EVL: N->getVectorLength(),
2572 SVT: N->getMemoryVT(), MMO: N->getMemOperand(),
2573 IsCompressing: N->isCompressingStore());
2574}
2575
2576SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
2577 unsigned OpNo) {
2578 SDValue DataOp = N->getValue();
2579 SDValue Mask = N->getMask();
2580
2581 if (OpNo == 4) {
2582 // The Mask. Update in place.
2583 EVT DataVT = DataOp.getValueType();
2584 Mask = PromoteTargetBoolean(Bool: Mask, ValVT: DataVT);
2585 SmallVector<SDValue, 4> NewOps(N->ops());
2586 NewOps[4] = Mask;
2587 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2588 }
2589
2590 assert(OpNo == 1 && "Unexpected operand for promotion");
2591 DataOp = GetPromotedInteger(Op: DataOp);
2592
2593 return DAG.getMaskedStore(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Base: N->getBasePtr(),
2594 Offset: N->getOffset(), Mask, MemVT: N->getMemoryVT(),
2595 MMO: N->getMemOperand(), AM: N->getAddressingMode(),
2596 /*IsTruncating*/ true, IsCompressing: N->isCompressingStore());
2597}
2598
2599SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
2600 unsigned OpNo) {
2601 assert(OpNo == 3 && "Only know how to promote the mask!");
2602 EVT DataVT = N->getValueType(ResNo: 0);
2603 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2604 SmallVector<SDValue, 4> NewOps(N->ops());
2605 NewOps[OpNo] = Mask;
2606 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2607 if (Res == N)
2608 return SDValue(Res, 0);
2609
2610 // Update triggered CSE, do our own replacement since caller can't.
2611 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2612 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2613 return SDValue();
2614}
2615
2616SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
2617 unsigned OpNo) {
2618 SmallVector<SDValue, 5> NewOps(N->ops());
2619
2620 if (OpNo == 2) {
2621 // The Mask
2622 EVT DataVT = N->getValueType(ResNo: 0);
2623 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2624 } else if (OpNo == 4) {
2625 // The Index
2626 if (N->isIndexSigned())
2627 // Need to sign extend the index since the bits will likely be used.
2628 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2629 else
2630 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2631 } else
2632 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2633
2634 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2635 if (Res == N)
2636 return SDValue(Res, 0);
2637
2638 // Update triggered CSE, do our own replacement since caller can't.
2639 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2640 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2641 return SDValue();
2642}
2643
2644SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2645 unsigned OpNo) {
2646 bool TruncateStore = N->isTruncatingStore();
2647 SmallVector<SDValue, 5> NewOps(N->ops());
2648
2649 if (OpNo == 2) {
2650 // The Mask
2651 EVT DataVT = N->getValue().getValueType();
2652 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2653 } else if (OpNo == 4) {
2654 // The Index
2655 if (N->isIndexSigned())
2656 // Need to sign extend the index since the bits will likely be used.
2657 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2658 else
2659 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2660 } else {
2661 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2662 TruncateStore = true;
2663 }
2664
2665 return DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: N->getMemoryVT(),
2666 dl: SDLoc(N), Ops: NewOps, MMO: N->getMemOperand(),
2667 IndexType: N->getIndexType(), IsTruncating: TruncateStore);
2668}
2669
2670SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_COMPRESS(SDNode *N,
2671 unsigned OpNo) {
2672 assert(OpNo == 1 && "Can only promote VECTOR_COMPRESS mask.");
2673 SDValue Vec = N->getOperand(Num: 0);
2674 EVT VT = Vec.getValueType();
2675 SDValue Passthru = N->getOperand(Num: 2);
2676 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: VT);
2677 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT, N1: Vec, N2: Mask, N3: Passthru);
2678}
2679
2680SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2681 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2682 if (N->getOpcode() == ISD::VP_TRUNCATE)
2683 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Op,
2684 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2685 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2686}
2687
2688SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2689 if (N->getOpcode() == ISD::VP_UINT_TO_FP)
2690 return SDValue(DAG.UpdateNodeOperands(N,
2691 Op1: ZExtPromotedInteger(Op: N->getOperand(Num: 0)),
2692 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2693 0);
2694 return SDValue(DAG.UpdateNodeOperands(N,
2695 Op: ZExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2696}
2697
2698SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(SDNode *N) {
2699 return SDValue(DAG.UpdateNodeOperands(N, Op1: GetPromotedInteger(Op: N->getOperand(Num: 0)),
2700 Op2: N->getOperand(Num: 1)),
2701 0);
2702}
2703
2704SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2705 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2706 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2707}
2708
2709SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2710 SDLoc dl(N);
2711 SDValue Src = N->getOperand(Num: 0);
2712 SDValue Op = GetPromotedInteger(Op: Src);
2713 EVT VT = N->getValueType(ResNo: 0);
2714
2715 // If this zext has the nneg flag and the target prefers sext, see if the
2716 // promoted input is already sign extended.
2717 // TODO: Should we have some way to set nneg on ISD::AND instead?
2718 if (N->getFlags().hasNonNeg() && Op.getValueType() == VT &&
2719 TLI.isSExtCheaperThanZExt(FromTy: Src.getValueType(), ToTy: VT)) {
2720 unsigned OpEffectiveBits = DAG.ComputeMaxSignificantBits(Op);
2721 if (OpEffectiveBits <= Src.getScalarValueSizeInBits())
2722 return Op;
2723 }
2724
2725 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Op);
2726 return DAG.getZeroExtendInReg(Op, DL: dl, VT: Src.getValueType());
2727}
2728
2729SDValue DAGTypeLegalizer::PromoteIntOp_VP_ZERO_EXTEND(SDNode *N) {
2730 SDLoc dl(N);
2731 EVT VT = N->getValueType(ResNo: 0);
2732 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2733 // FIXME: There is no VP_ANY_EXTEND yet.
2734 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2735 N3: N->getOperand(Num: 2));
2736 return DAG.getVPZeroExtendInReg(Op, Mask: N->getOperand(Num: 1), EVL: N->getOperand(Num: 2), DL: dl,
2737 VT: N->getOperand(Num: 0).getValueType());
2738}
2739
2740SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2741 SDValue Op2 = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2742 return SDValue(
2743 DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1), Op3: Op2), 0);
2744}
2745
2746SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2747 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2748 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2749 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2750}
2751
2752SDValue DAGTypeLegalizer::PromoteIntOp_ExpOp(SDNode *N) {
2753 bool IsStrict = N->isStrictFPOpcode();
2754 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
2755
2756 bool IsPowI =
2757 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI;
2758 unsigned OpOffset = IsStrict ? 1 : 0;
2759
2760 // The integer operand is the last operand in FPOWI (or FLDEXP) (so the result
2761 // and floating point operand is already type legalized).
2762 RTLIB::Libcall LC = IsPowI ? RTLIB::getPOWI(RetVT: N->getValueType(ResNo: 0))
2763 : RTLIB::getLDEXP(RetVT: N->getValueType(ResNo: 0));
2764
2765 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
2766 if (LCImpl == RTLIB::Unsupported) {
2767 // Scalarize vector FPOWI instead of promoting the type. This allows the
2768 // scalar FPOWIs to be visited and converted to libcalls before promoting
2769 // the type.
2770 // FIXME: This should be done in LegalizeVectorOps/LegalizeDAG, but call
2771 // lowering needs the unpromoted EVT.
2772 if (IsPowI && N->getValueType(ResNo: 0).isVector())
2773 return DAG.UnrollVectorOp(N);
2774 SmallVector<SDValue, 3> NewOps(N->ops());
2775 NewOps[1 + OpOffset] = SExtPromotedInteger(Op: N->getOperand(Num: 1 + OpOffset));
2776 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2777 }
2778
2779 // We can't just promote the exponent type in FPOWI, since we want to lower
2780 // the node to a libcall and we if we promote to a type larger than
2781 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2782 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2783 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2784
2785 // The exponent should fit in a sizeof(int) type for the libcall to be valid.
2786 assert(DAG.getLibInfo().getIntSize() ==
2787 N->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&
2788 "POWI exponent should match with sizeof(int) when doing the libcall.");
2789 TargetLowering::MakeLibCallOptions CallOptions;
2790 CallOptions.setIsSigned(true);
2791 SDValue Ops[2] = {N->getOperand(Num: 0 + OpOffset), N->getOperand(Num: 1 + OpOffset)};
2792 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2793 DAG, LibcallImpl: LCImpl, RetVT: N->getValueType(ResNo: 0), Ops, CallOptions, dl: SDLoc(N), Chain);
2794 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
2795 if (IsStrict)
2796 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
2797 return SDValue();
2798}
2799
2800static unsigned getExtendForIntVecReduction(SDNode *N) {
2801 switch (N->getOpcode()) {
2802 default:
2803 llvm_unreachable("Expected integer vector reduction");
2804 case ISD::VECREDUCE_ADD:
2805 case ISD::VECREDUCE_MUL:
2806 case ISD::VECREDUCE_AND:
2807 case ISD::VECREDUCE_OR:
2808 case ISD::VECREDUCE_XOR:
2809 case ISD::VP_REDUCE_ADD:
2810 case ISD::VP_REDUCE_MUL:
2811 case ISD::VP_REDUCE_AND:
2812 case ISD::VP_REDUCE_OR:
2813 case ISD::VP_REDUCE_XOR:
2814 return ISD::ANY_EXTEND;
2815 case ISD::VECREDUCE_SMAX:
2816 case ISD::VECREDUCE_SMIN:
2817 case ISD::VP_REDUCE_SMAX:
2818 case ISD::VP_REDUCE_SMIN:
2819 return ISD::SIGN_EXTEND;
2820 case ISD::VECREDUCE_UMAX:
2821 case ISD::VECREDUCE_UMIN:
2822 case ISD::VP_REDUCE_UMAX:
2823 case ISD::VP_REDUCE_UMIN:
2824 return ISD::ZERO_EXTEND;
2825 }
2826}
2827
2828SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2829 switch (getExtendForIntVecReduction(N)) {
2830 default:
2831 llvm_unreachable("Impossible extension kind for integer reduction");
2832 case ISD::ANY_EXTEND:
2833 return GetPromotedInteger(Op: V);
2834 case ISD::SIGN_EXTEND:
2835 return SExtPromotedInteger(Op: V);
2836 case ISD::ZERO_EXTEND:
2837 return ZExtPromotedInteger(Op: V);
2838 }
2839}
2840
2841SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2842 SDLoc dl(N);
2843 SDValue Op = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
2844
2845 EVT OrigEltVT = N->getOperand(Num: 0).getValueType().getVectorElementType();
2846 EVT InVT = Op.getValueType();
2847 EVT EltVT = InVT.getVectorElementType();
2848 EVT ResVT = N->getValueType(ResNo: 0);
2849 unsigned Opcode = N->getOpcode();
2850
2851 // An i1 vecreduce_xor is equivalent to vecreduce_add, use that instead if
2852 // vecreduce_xor is not legal
2853 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 &&
2854 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_XOR, VT: InVT) &&
2855 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_ADD, VT: InVT))
2856 Opcode = ISD::VECREDUCE_ADD;
2857
2858 // An i1 vecreduce_or is equivalent to vecreduce_umax, use that instead if
2859 // vecreduce_or is not legal
2860 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 &&
2861 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_OR, VT: InVT) &&
2862 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMAX, VT: InVT)) {
2863 Opcode = ISD::VECREDUCE_UMAX;
2864 // Can't use promoteTargetBoolean here because we still need
2865 // to either sign_ext or zero_ext in the undefined case.
2866 switch (TLI.getBooleanContents(Type: InVT)) {
2867 case TargetLoweringBase::UndefinedBooleanContent:
2868 case TargetLoweringBase::ZeroOrOneBooleanContent:
2869 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2870 break;
2871 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2872 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2873 break;
2874 }
2875 }
2876
2877 // An i1 vecreduce_and is equivalent to vecreduce_umin, use that instead if
2878 // vecreduce_and is not legal
2879 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 &&
2880 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_AND, VT: InVT) &&
2881 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMIN, VT: InVT)) {
2882 Opcode = ISD::VECREDUCE_UMIN;
2883 // Can't use promoteTargetBoolean here because we still need
2884 // to either sign_ext or zero_ext in the undefined case.
2885 switch (TLI.getBooleanContents(Type: InVT)) {
2886 case TargetLoweringBase::UndefinedBooleanContent:
2887 case TargetLoweringBase::ZeroOrOneBooleanContent:
2888 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2889 break;
2890 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2891 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2892 break;
2893 }
2894 }
2895
2896 if (ResVT.bitsGE(VT: EltVT))
2897 return DAG.getNode(Opcode, DL: SDLoc(N), VT: ResVT, Operand: Op);
2898
2899 // Result size must be >= element size. If this is not the case after
2900 // promotion, also promote the result type and then truncate.
2901 SDValue Reduce = DAG.getNode(Opcode, DL: dl, VT: EltVT, Operand: Op);
2902 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: ResVT, Operand: Reduce);
2903}
2904
2905SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
2906 SDLoc DL(N);
2907 SDValue Op = N->getOperand(Num: OpNo);
2908 SmallVector<SDValue, 4> NewOps(N->ops());
2909
2910 if (OpNo == 2) { // Mask
2911 // Update in place.
2912 NewOps[2] = PromoteTargetBoolean(Bool: Op, ValVT: N->getOperand(Num: 1).getValueType());
2913 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2914 }
2915
2916 assert(OpNo == 1 && "Unexpected operand for promotion");
2917
2918 Op = PromoteIntOpVectorReduction(N, V: Op);
2919
2920 NewOps[OpNo] = Op;
2921
2922 EVT VT = N->getValueType(ResNo: 0);
2923 EVT EltVT = Op.getValueType().getScalarType();
2924
2925 if (VT.bitsGE(VT: EltVT))
2926 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT, Ops: NewOps);
2927
2928 // Result size must be >= element/start-value size. If this is not the case
2929 // after promotion, also promote both the start value and result type and
2930 // then truncate.
2931 NewOps[0] =
2932 DAG.getNode(Opcode: getExtendForIntVecReduction(N), DL, VT: EltVT, Operand: N->getOperand(Num: 0));
2933 SDValue Reduce = DAG.getNode(Opcode: N->getOpcode(), DL, VT: EltVT, Ops: NewOps);
2934 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT, Operand: Reduce);
2935}
2936
2937SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2938 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2939 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Op), 0);
2940}
2941
2942SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
2943 assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
2944 SmallVector<SDValue> NewOps(N->ops());
2945 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
2946 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2947}
2948
2949SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
2950 assert(OpNo >= 7);
2951 SmallVector<SDValue> NewOps(N->ops());
2952 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
2953 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2954}
2955
2956SDValue DAGTypeLegalizer::PromoteIntOp_WRITE_REGISTER(SDNode *N,
2957 unsigned OpNo) {
2958 const Function &Fn = DAG.getMachineFunction().getFunction();
2959 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
2960 "cannot use llvm.write_register with illegal type", Fn,
2961 N->getDebugLoc()));
2962 return N->getOperand(Num: 0);
2963}
2964
2965SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
2966 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
2967 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
2968
2969 SmallVector<SDValue, 8> NewOps(N->ops());
2970 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2971
2972 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2973}
2974
2975SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
2976 SmallVector<SDValue, 6> NewOps(N->ops());
2977
2978 if (OpNo == 2) { // Offset operand
2979 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2980 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2981 }
2982
2983 assert((OpNo == 4 || OpNo == 5) && "Unexpected operand for promotion");
2984
2985 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2986 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2987}
2988
2989SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_HISTOGRAM(SDNode *N,
2990 unsigned OpNo) {
2991 assert(OpNo == 1 && "Unexpected operand for promotion");
2992 SmallVector<SDValue, 7> NewOps(N->ops());
2993 NewOps[1] = GetPromotedInteger(Op: N->getOperand(Num: 1));
2994 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2995}
2996
2997SDValue DAGTypeLegalizer::PromoteIntOp_UnaryBooleanVectorOp(SDNode *N,
2998 unsigned OpNo) {
2999 assert(OpNo == 0 && "Unexpected operand for promotion");
3000 SDValue Op = N->getOperand(Num: 0);
3001
3002 SDValue NewOp;
3003 if (TLI.getBooleanContents(Type: Op.getValueType()) ==
3004 TargetLowering::ZeroOrNegativeOneBooleanContent)
3005 NewOp = SExtPromotedInteger(Op);
3006 else
3007 NewOp = ZExtPromotedInteger(Op);
3008
3009 return SDValue(DAG.UpdateNodeOperands(N, Op: NewOp), 0);
3010}
3011
3012SDValue DAGTypeLegalizer::PromoteIntOp_GET_ACTIVE_LANE_MASK(SDNode *N) {
3013 SmallVector<SDValue, 1> NewOps(N->ops());
3014 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3015 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3016 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3017}
3018
3019SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
3020 SmallVector<SDValue, 1> NewOps(N->ops());
3021 switch (N->getOpcode()) {
3022 case ISD::PARTIAL_REDUCE_SMLA:
3023 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3024 NewOps[2] = SExtPromotedInteger(Op: N->getOperand(Num: 2));
3025 break;
3026 case ISD::PARTIAL_REDUCE_UMLA:
3027 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3028 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3029 break;
3030 case ISD::PARTIAL_REDUCE_SUMLA:
3031 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3032 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3033 break;
3034 default:
3035 llvm_unreachable("unexpected opcode");
3036 }
3037 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3038}
3039
3040//===----------------------------------------------------------------------===//
3041// Integer Result Expansion
3042//===----------------------------------------------------------------------===//
3043
3044/// ExpandIntegerResult - This method is called when the specified result of the
3045/// specified node is found to need expansion. At this point, the node may also
3046/// have invalid operands or may have other results that need promotion, we just
3047/// know that (at least) one result needs expansion.
3048void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
3049 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG));
3050 SDValue Lo, Hi;
3051 Lo = Hi = SDValue();
3052
3053 // See if the target wants to custom expand this node.
3054 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true))
3055 return;
3056
3057 switch (N->getOpcode()) {
3058 default:
3059#ifndef NDEBUG
3060 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
3061 N->dump(&DAG); dbgs() << "\n";
3062#endif
3063 report_fatal_error(reason: "Do not know how to expand the result of this "
3064 "operator!");
3065
3066 case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
3067 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
3068 case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
3069 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
3070 case ISD::POISON:
3071 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
3072 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
3073 case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;
3074
3075 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
3076 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
3077 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
3078 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
3079 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
3080
3081 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
3082 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
3083 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
3084 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
3085 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
3086 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
3087 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
3088 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
3089 case ISD::ABDS:
3090 case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
3091 case ISD::CTLZ_ZERO_UNDEF:
3092 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
3093 case ISD::CTLS: ExpandIntRes_CTLS(N, Lo, Hi); break;
3094 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
3095 case ISD::CTTZ_ZERO_UNDEF:
3096 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
3097 case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
3098 case ISD::STRICT_FP_TO_SINT:
3099 case ISD::FP_TO_SINT:
3100 case ISD::STRICT_FP_TO_UINT:
3101 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_XINT(N, Lo, Hi); break;
3102 case ISD::FP_TO_SINT_SAT:
3103 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
3104 case ISD::STRICT_LROUND:
3105 case ISD::STRICT_LRINT:
3106 case ISD::LROUND:
3107 case ISD::LRINT:
3108 case ISD::STRICT_LLROUND:
3109 case ISD::STRICT_LLRINT:
3110 case ISD::LLROUND:
3111 case ISD::LLRINT: ExpandIntRes_XROUND_XRINT(N, Lo, Hi); break;
3112 case ISD::LOAD: ExpandIntRes_LOAD(N: cast<LoadSDNode>(Val: N), Lo, Hi); break;
3113 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
3114 case ISD::READCYCLECOUNTER:
3115 case ISD::READSTEADYCOUNTER: ExpandIntRes_READCOUNTER(N, Lo, Hi); break;
3116 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
3117 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
3118 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
3119 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
3120 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
3121 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
3122 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
3123 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
3124 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
3125
3126 case ISD::ATOMIC_LOAD_ADD:
3127 case ISD::ATOMIC_LOAD_SUB:
3128 case ISD::ATOMIC_LOAD_AND:
3129 case ISD::ATOMIC_LOAD_CLR:
3130 case ISD::ATOMIC_LOAD_OR:
3131 case ISD::ATOMIC_LOAD_XOR:
3132 case ISD::ATOMIC_LOAD_NAND:
3133 case ISD::ATOMIC_LOAD_MIN:
3134 case ISD::ATOMIC_LOAD_MAX:
3135 case ISD::ATOMIC_LOAD_UMIN:
3136 case ISD::ATOMIC_LOAD_UMAX:
3137 case ISD::ATOMIC_SWAP:
3138 case ISD::ATOMIC_CMP_SWAP: {
3139 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node: N);
3140 SplitInteger(Op: Tmp.first, Lo, Hi);
3141 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
3142 break;
3143 }
3144 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3145 AtomicSDNode *AN = cast<AtomicSDNode>(Val: N);
3146 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: MVT::Other);
3147 SDValue Tmp = DAG.getAtomicCmpSwap(
3148 Opcode: ISD::ATOMIC_CMP_SWAP, dl: SDLoc(N), MemVT: AN->getMemoryVT(), VTs,
3149 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 1), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
3150 MMO: AN->getMemOperand());
3151
3152 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
3153 // success simply by comparing the loaded value against the ingoing
3154 // comparison.
3155 SDValue Success = DAG.getSetCC(DL: SDLoc(N), VT: N->getValueType(ResNo: 1), LHS: Tmp,
3156 RHS: N->getOperand(Num: 2), Cond: ISD::SETEQ);
3157
3158 SplitInteger(Op: Tmp, Lo, Hi);
3159 ReplaceValueWith(From: SDValue(N, 1), To: Success);
3160 ReplaceValueWith(From: SDValue(N, 2), To: Tmp.getValue(R: 1));
3161 break;
3162 }
3163
3164 case ISD::AND:
3165 case ISD::OR:
3166 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
3167
3168 case ISD::UMAX:
3169 case ISD::SMAX:
3170 case ISD::UMIN:
3171 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
3172
3173 case ISD::SCMP:
3174 case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
3175
3176 case ISD::ADD:
3177 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
3178
3179 case ISD::ADDC:
3180 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
3181
3182 case ISD::ADDE:
3183 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
3184
3185 case ISD::UADDO_CARRY:
3186 case ISD::USUBO_CARRY: ExpandIntRes_UADDSUBO_CARRY(N, Lo, Hi); break;
3187
3188 case ISD::SADDO_CARRY:
3189 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
3190
3191 case ISD::SHL:
3192 case ISD::SRA:
3193 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
3194
3195 case ISD::SADDO:
3196 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
3197 case ISD::UADDO:
3198 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
3199 case ISD::UMULO:
3200 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3201
3202 case ISD::SADDSAT:
3203 case ISD::UADDSAT:
3204 case ISD::SSUBSAT:
3205 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
3206
3207 case ISD::SSHLSAT:
3208 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
3209
3210 case ISD::AVGCEILS:
3211 case ISD::AVGCEILU:
3212 case ISD::AVGFLOORS:
3213 case ISD::AVGFLOORU: ExpandIntRes_AVG(N, Lo, Hi); break;
3214
3215 case ISD::SMULFIX:
3216 case ISD::SMULFIXSAT:
3217 case ISD::UMULFIX:
3218 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
3219
3220 case ISD::SDIVFIX:
3221 case ISD::SDIVFIXSAT:
3222 case ISD::UDIVFIX:
3223 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
3224
3225 case ISD::VECREDUCE_ADD:
3226 case ISD::VECREDUCE_MUL:
3227 case ISD::VECREDUCE_AND:
3228 case ISD::VECREDUCE_OR:
3229 case ISD::VECREDUCE_XOR:
3230 case ISD::VECREDUCE_SMAX:
3231 case ISD::VECREDUCE_SMIN:
3232 case ISD::VECREDUCE_UMAX:
3233 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
3234
3235 case ISD::ROTL:
3236 case ISD::ROTR:
3237 ExpandIntRes_Rotate(N, Lo, Hi);
3238 break;
3239
3240 case ISD::FSHL:
3241 case ISD::FSHR:
3242 ExpandIntRes_FunnelShift(N, Lo, Hi);
3243 break;
3244
3245 case ISD::CLMUL:
3246 case ISD::CLMULR:
3247 case ISD::CLMULH:
3248 ExpandIntRes_CLMUL(N, Lo, Hi);
3249 break;
3250
3251 case ISD::VSCALE:
3252 ExpandIntRes_VSCALE(N, Lo, Hi);
3253 break;
3254
3255 case ISD::READ_REGISTER:
3256 ExpandIntRes_READ_REGISTER(N, Lo, Hi);
3257 break;
3258
3259 case ISD::CTTZ_ELTS:
3260 case ISD::CTTZ_ELTS_ZERO_POISON:
3261 ExpandIntRes_CTTZ_ELTS(N, Lo, Hi);
3262 break;
3263 }
3264
3265 // If Lo/Hi is null, the sub-method took care of registering results etc.
3266 if (Lo.getNode())
3267 SetExpandedInteger(Op: SDValue(N, ResNo), Lo, Hi);
3268}
3269
3270/// Lower an atomic node to the appropriate builtin call.
3271std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
3272 unsigned Opc = Node->getOpcode();
3273 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
3274 AtomicOrdering order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
3275 // Lower to outline atomic libcall if outline atomics enabled,
3276 // or to sync libcall otherwise
3277 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order: order, VT);
3278 EVT RetVT = Node->getValueType(ResNo: 0);
3279 TargetLowering::MakeLibCallOptions CallOptions;
3280 SmallVector<SDValue, 4> Ops;
3281
3282 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3283 if (LCImpl != RTLIB::Unsupported) {
3284 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
3285 Ops.push_back(Elt: Node->getOperand(Num: 1));
3286 } else {
3287 LC = RTLIB::getSYNC(Opc, VT);
3288 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3289 "Unexpected atomic op or value type!");
3290 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
3291 LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3292 }
3293 return TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT, Ops, CallOptions, dl: SDLoc(Node),
3294 Chain: Node->getOperand(Num: 0));
3295}
3296
3297/// N is a shift by a value that needs to be expanded,
3298/// and the shift amount is a constant 'Amt'. Expand the operation.
3299void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
3300 SDValue &Lo, SDValue &Hi) {
3301 SDLoc DL(N);
3302 // Expand the incoming operand to be shifted, so that we have its parts
3303 SDValue InL, InH;
3304 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3305
3306 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
3307 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
3308 if (!Amt) {
3309 Lo = InL;
3310 Hi = InH;
3311 return;
3312 }
3313
3314 EVT NVT = InL.getValueType();
3315 unsigned VTBits = N->getValueType(ResNo: 0).getSizeInBits();
3316 unsigned NVTBits = NVT.getSizeInBits();
3317
3318 if (N->getOpcode() == ISD::SHL) {
3319 if (Amt.uge(RHS: VTBits)) {
3320 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3321 } else if (Amt.ugt(RHS: NVTBits)) {
3322 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3323 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3324 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3325 } else if (Amt == NVTBits) {
3326 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3327 Hi = InL;
3328 } else {
3329 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3330 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3331 // Use FSHL if legal so we don't need to combine it later.
3332 if (TLI.isOperationLegal(Op: ISD::FSHL, VT: NVT)) {
3333 Hi = DAG.getNode(Opcode: ISD::FSHL, DL, VT: NVT, N1: InH, N2: InL,
3334 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3335 } else {
3336 Hi = DAG.getNode(
3337 Opcode: ISD::OR, DL, VT: NVT,
3338 N1: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3339 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3340 N2: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3341 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3342 }
3343 }
3344 return;
3345 }
3346
3347 if (N->getOpcode() == ISD::SRL) {
3348 if (Amt.uge(RHS: VTBits)) {
3349 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3350 } else if (Amt.ugt(RHS: NVTBits)) {
3351 Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3352 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3353 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3354 } else if (Amt == NVTBits) {
3355 Lo = InH;
3356 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3357 } else {
3358 // Use FSHR if legal so we don't need to combine it later.
3359 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3360 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3361 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3362 } else {
3363 Lo = DAG.getNode(
3364 Opcode: ISD::OR, DL, VT: NVT,
3365 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3366 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3367 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3368 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3369 }
3370 Hi = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3371 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3372 }
3373 return;
3374 }
3375
3376 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3377 if (Amt.uge(RHS: VTBits)) {
3378 Hi = Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3379 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3380 } else if (Amt.ugt(RHS: NVTBits)) {
3381 Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3382 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3383 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3384 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3385 } else if (Amt == NVTBits) {
3386 Lo = InH;
3387 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3388 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3389 } else {
3390 // Use FSHR if legal so we don't need to combine it later.
3391 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3392 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3393 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3394 } else {
3395 Lo = DAG.getNode(
3396 Opcode: ISD::OR, DL, VT: NVT,
3397 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3398 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3399 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3400 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3401 }
3402 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3403 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3404 }
3405}
3406
3407/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
3408/// this shift based on knowledge of the high bit of the shift amount. If we
3409/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
3410/// shift amount.
3411bool DAGTypeLegalizer::
3412ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3413 unsigned Opc = N->getOpcode();
3414 SDValue In = N->getOperand(Num: 0);
3415 SDValue Amt = N->getOperand(Num: 1);
3416 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3417 EVT ShTy = Amt.getValueType();
3418 unsigned ShBits = ShTy.getScalarSizeInBits();
3419 unsigned NVTBits = NVT.getScalarSizeInBits();
3420 assert(isPowerOf2_32(NVTBits) &&
3421 "Expanded integer type size not a power of two!");
3422 SDLoc dl(N);
3423
3424 APInt HighBitMask = APInt::getHighBitsSet(numBits: ShBits, hiBitsSet: ShBits - Log2_32(Value: NVTBits));
3425 KnownBits Known = DAG.computeKnownBits(Op: Amt);
3426
3427 // If we don't know anything about the high bits, exit.
3428 if (((Known.Zero | Known.One) & HighBitMask) == 0)
3429 return false;
3430
3431 // Get the incoming operand to be shifted.
3432 SDValue InL, InH;
3433 GetExpandedInteger(Op: In, Lo&: InL, Hi&: InH);
3434
3435 // If we know that any of the high bits of the shift amount are one, then we
3436 // can do this as a couple of simple shifts.
3437 if (Known.One.intersects(RHS: HighBitMask)) {
3438 // Mask out the high bit, which we know is set.
3439 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShTy, N1: Amt,
3440 N2: DAG.getConstant(Val: ~HighBitMask, DL: dl, VT: ShTy));
3441
3442 switch (Opc) {
3443 default: llvm_unreachable("Unknown shift");
3444 case ISD::SHL:
3445 Lo = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Low part is zero.
3446 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt); // High part from Lo part.
3447 return true;
3448 case ISD::SRL:
3449 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3450 Lo = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3451 return true;
3452 case ISD::SRA:
3453 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign extend high part.
3454 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3455 Lo = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3456 return true;
3457 }
3458 }
3459
3460 // If we know that all of the high bits of the shift amount are zero, then we
3461 // can do this as a couple of simple shifts.
3462 if (HighBitMask.isSubsetOf(RHS: Known.Zero)) {
3463 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
3464 // shift if x is zero. We can use XOR here because x is known to be smaller
3465 // than 32.
3466 SDValue Amt2 = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: ShTy, N1: Amt,
3467 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3468
3469 unsigned Op1, Op2;
3470 switch (Opc) {
3471 default: llvm_unreachable("Unknown shift");
3472 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
3473 case ISD::SRL:
3474 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
3475 }
3476
3477 // When shifting right the arithmetic for Lo and Hi is swapped.
3478 if (Opc != ISD::SHL)
3479 std::swap(a&: InL, b&: InH);
3480
3481 // Use a little trick to get the bits that move from Lo to Hi. First
3482 // shift by one bit.
3483 SDValue Sh1 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: InL, N2: DAG.getConstant(Val: 1, DL: dl, VT: ShTy));
3484 // Then compute the remaining shift with amount-1.
3485 SDValue Sh2 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: Sh1, N2: Amt2);
3486
3487 Lo = DAG.getNode(Opcode: Opc, DL: dl, VT: NVT, N1: InL, N2: Amt);
3488 Hi = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: Op1, DL: dl, VT: NVT, N1: InH, N2: Amt),N2: Sh2);
3489
3490 if (Opc != ISD::SHL)
3491 std::swap(a&: Hi, b&: Lo);
3492 return true;
3493 }
3494
3495 return false;
3496}
3497
3498/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
3499/// of any size.
3500bool DAGTypeLegalizer::
3501ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3502 SDValue Amt = N->getOperand(Num: 1);
3503 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3504 EVT ShTy = Amt.getValueType();
3505 unsigned NVTBits = NVT.getSizeInBits();
3506 assert(isPowerOf2_32(NVTBits) &&
3507 "Expanded integer type size not a power of two!");
3508 SDLoc dl(N);
3509
3510 // Get the incoming operand to be shifted.
3511 SDValue InL, InH;
3512 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3513
3514 SDValue NVBitsNode = DAG.getConstant(Val: NVTBits, DL: dl, VT: ShTy);
3515 SDValue AmtExcess = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: Amt, N2: NVBitsNode);
3516 SDValue AmtLack = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: NVBitsNode, N2: Amt);
3517 SDValue isShort = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3518 LHS: Amt, RHS: NVBitsNode, Cond: ISD::SETULT);
3519 SDValue isZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3520 LHS: Amt, RHS: DAG.getConstant(Val: 0, DL: dl, VT: ShTy),
3521 Cond: ISD::SETEQ);
3522
3523 SDValue LoS, HiS, LoL, HiL;
3524 switch (N->getOpcode()) {
3525 default: llvm_unreachable("Unknown shift");
3526 case ISD::SHL:
3527 // Short: ShAmt < NVTBits
3528 LoS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt);
3529 HiS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3530 N1: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: Amt),
3531 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: AmtLack));
3532
3533 // Long: ShAmt >= NVTBits
3534 LoL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Lo part is zero.
3535 HiL = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: AmtExcess); // Hi from Lo part.
3536
3537 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL);
3538 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InH,
3539 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL));
3540 return true;
3541 case ISD::SRL:
3542 // Short: ShAmt < NVTBits
3543 HiS = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt);
3544 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3545 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3546 // FIXME: If Amt is zero, the following shift generates an undefined result
3547 // on some architectures.
3548 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3549
3550 // Long: ShAmt >= NVTBits
3551 HiL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3552 LoL = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3553
3554 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3555 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3556 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3557 return true;
3558 case ISD::SRA:
3559 // Short: ShAmt < NVTBits
3560 HiS = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt);
3561 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3562 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3563 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3564
3565 // Long: ShAmt >= NVTBits
3566 HiL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign of Hi part.
3567 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3568 LoL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3569
3570 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3571 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3572 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3573 return true;
3574 }
3575}
3576
3577static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
3578
3579 switch (Op) {
3580 default: llvm_unreachable("invalid min/max opcode");
3581 case ISD::SMAX:
3582 return std::make_pair(x: ISD::SETGT, y: ISD::UMAX);
3583 case ISD::UMAX:
3584 return std::make_pair(x: ISD::SETUGT, y: ISD::UMAX);
3585 case ISD::SMIN:
3586 return std::make_pair(x: ISD::SETLT, y: ISD::UMIN);
3587 case ISD::UMIN:
3588 return std::make_pair(x: ISD::SETULT, y: ISD::UMIN);
3589 }
3590}
3591
3592void DAGTypeLegalizer::ExpandIntRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
3593 SDLoc DL(N);
3594
3595 SDValue LHS = N->getOperand(Num: 0);
3596 SDValue RHS = N->getOperand(Num: 1);
3597 EVT NewVT = getSetCCResultType(VT: LHS.getValueType());
3598
3599 // Taking the same approach as ScalarizeVecRes_SETCC
3600 SDValue Res = DAG.getNode(Opcode: ISD::SETCC, DL, VT: NewVT, N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
3601
3602 Res = DAG.getBoolExtOrTrunc(Op: Res, SL: DL, VT: N->getValueType(ResNo: 0), OpVT: NewVT);
3603 SplitInteger(Op: Res, Lo, Hi);
3604}
3605
3606void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
3607 SDValue &Lo, SDValue &Hi) {
3608 SDLoc DL(N);
3609
3610 SDValue LHS = N->getOperand(Num: 0);
3611 SDValue RHS = N->getOperand(Num: 1);
3612
3613 // If the upper halves are all sign bits, then we can perform the MINMAX on
3614 // the lower half and sign-extend the result to the upper half.
3615 unsigned NumBits = N->getValueType(ResNo: 0).getScalarSizeInBits();
3616 unsigned NumHalfBits = NumBits / 2;
3617 if (DAG.ComputeNumSignBits(Op: LHS) > NumHalfBits &&
3618 DAG.ComputeNumSignBits(Op: RHS) > NumHalfBits) {
3619 SDValue LHSL, LHSH, RHSL, RHSH;
3620 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3621 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3622 EVT NVT = LHSL.getValueType();
3623
3624 Lo = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: LHSL, N2: RHSL);
3625 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: Lo,
3626 N2: DAG.getShiftAmountConstant(Val: NumHalfBits - 1, VT: NVT, DL));
3627 return;
3628 }
3629
3630 // The Lo of smin(X, -1) is LHSL if X is negative. Otherwise it's -1.
3631 // The Lo of smax(X, 0) is 0 if X is negative. Otherwise it's LHSL.
3632 if ((N->getOpcode() == ISD::SMAX && isNullConstant(V: RHS)) ||
3633 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(V: RHS))) {
3634 SDValue LHSL, LHSH, RHSL, RHSH;
3635 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3636 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3637 EVT NVT = LHSL.getValueType();
3638 EVT CCT = getSetCCResultType(VT: NVT);
3639
3640 SDValue HiNeg =
3641 DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: DAG.getConstant(Val: 0, DL, VT: NVT), Cond: ISD::SETLT);
3642 if (N->getOpcode() == ISD::SMIN) {
3643 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: LHSL, RHS: DAG.getAllOnesConstant(DL, VT: NVT));
3644 } else {
3645 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: DAG.getConstant(Val: 0, DL, VT: NVT), RHS: LHSL);
3646 }
3647 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3648 return;
3649 }
3650
3651 const APInt *RHSVal = nullptr;
3652 if (auto *RHSConst = dyn_cast<ConstantSDNode>(Val&: RHS))
3653 RHSVal = &RHSConst->getAPIntValue();
3654
3655 // The high half of MIN/MAX is always just the the MIN/MAX of the
3656 // high halves of the operands. Expand this way if it appears profitable.
3657 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) &&
3658 (RHSVal->countLeadingOnes() >= NumHalfBits ||
3659 RHSVal->countLeadingZeros() >= NumHalfBits)) {
3660 SDValue LHSL, LHSH, RHSL, RHSH;
3661 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3662 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3663 EVT NVT = LHSL.getValueType();
3664 EVT CCT = getSetCCResultType(VT: NVT);
3665
3666 ISD::NodeType LoOpc;
3667 ISD::CondCode CondC;
3668 std::tie(args&: CondC, args&: LoOpc) = getExpandedMinMaxOps(Op: N->getOpcode());
3669
3670 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3671 // We need to know whether to select Lo part that corresponds to 'winning'
3672 // Hi part or if Hi parts are equal.
3673 SDValue IsHiLeft = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: CondC);
3674 SDValue IsHiEq = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: ISD::SETEQ);
3675
3676 // Lo part corresponding to the 'winning' Hi part
3677 SDValue LoCmp = DAG.getSelect(DL, VT: NVT, Cond: IsHiLeft, LHS: LHSL, RHS: RHSL);
3678
3679 // Recursed Lo part if Hi parts are equal, this uses unsigned version
3680 SDValue LoMinMax = DAG.getNode(Opcode: LoOpc, DL, VT: NVT, Ops: {LHSL, RHSL});
3681
3682 Lo = DAG.getSelect(DL, VT: NVT, Cond: IsHiEq, LHS: LoMinMax, RHS: LoCmp);
3683 return;
3684 }
3685
3686 // Expand to "a < b ? a : b" etc. Prefer ge/le if that simplifies
3687 // the compare.
3688 ISD::CondCode Pred;
3689 switch (N->getOpcode()) {
3690 default: llvm_unreachable("How did we get here?");
3691 case ISD::SMAX:
3692 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3693 Pred = ISD::SETGE;
3694 else
3695 Pred = ISD::SETGT;
3696 break;
3697 case ISD::SMIN:
3698 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3699 Pred = ISD::SETLE;
3700 else
3701 Pred = ISD::SETLT;
3702 break;
3703 case ISD::UMAX:
3704 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3705 Pred = ISD::SETUGE;
3706 else
3707 Pred = ISD::SETUGT;
3708 break;
3709 case ISD::UMIN:
3710 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3711 Pred = ISD::SETULE;
3712 else
3713 Pred = ISD::SETULT;
3714 break;
3715 }
3716 EVT VT = N->getValueType(ResNo: 0);
3717 EVT CCT = getSetCCResultType(VT);
3718 SDValue Cond = DAG.getSetCC(DL, VT: CCT, LHS, RHS, Cond: Pred);
3719 SDValue Result = DAG.getSelect(DL, VT, Cond, LHS, RHS);
3720 SplitInteger(Op: Result, Lo, Hi);
3721}
3722
3723void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
3724 SDValue ExpandedCMP = TLI.expandCMP(Node: N, DAG);
3725 SplitInteger(Op: ExpandedCMP, Lo, Hi);
3726}
3727
3728void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
3729 SDValue &Lo, SDValue &Hi) {
3730 SDLoc dl(N);
3731 // Expand the subcomponents.
3732 SDValue LHSL, LHSH, RHSL, RHSH;
3733 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3734 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3735
3736 EVT NVT = LHSL.getValueType();
3737 SDValue LoOps[2] = { LHSL, RHSL };
3738 SDValue HiOps[3] = { LHSH, RHSH };
3739
3740 bool HasOpCarry = TLI.isOperationLegalOrCustom(
3741 Op: N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
3742 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3743 if (HasOpCarry) {
3744 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
3745 if (N->getOpcode() == ISD::ADD) {
3746 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3747 HiOps[2] = Lo.getValue(R: 1);
3748 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3749 ? DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3750 : DAG.getNode(Opcode: ISD::UADDO_CARRY, DL: dl, VTList, Ops: HiOps);
3751 } else {
3752 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3753 HiOps[2] = Lo.getValue(R: 1);
3754 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3755 ? DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3756 : DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, Ops: HiOps);
3757 }
3758 return;
3759 }
3760
3761 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
3762 // them. TODO: Teach operation legalization how to expand unsupported
3763 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
3764 // a carry of type MVT::Glue, but there doesn't seem to be any way to
3765 // generate a value of this type in the expanded code sequence.
3766 bool hasCarry =
3767 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3768 ISD::ADDC : ISD::SUBC,
3769 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3770
3771 if (hasCarry) {
3772 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: MVT::Glue);
3773 if (N->getOpcode() == ISD::ADD) {
3774 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3775 HiOps[2] = Lo.getValue(R: 1);
3776 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3777 } else {
3778 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3779 HiOps[2] = Lo.getValue(R: 1);
3780 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3781 }
3782 return;
3783 }
3784
3785 bool hasOVF =
3786 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3787 ISD::UADDO : ISD::USUBO,
3788 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3789 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(Type: NVT);
3790
3791 if (hasOVF) {
3792 EVT OvfVT = getSetCCResultType(VT: NVT);
3793 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: OvfVT);
3794 int RevOpc;
3795 if (N->getOpcode() == ISD::ADD) {
3796 RevOpc = ISD::SUB;
3797 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3798 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3799 } else {
3800 RevOpc = ISD::ADD;
3801 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3802 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3803 }
3804 SDValue OVF = Lo.getValue(R: 1);
3805
3806 switch (BoolType) {
3807 case TargetLoweringBase::UndefinedBooleanContent:
3808 OVF = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: OvfVT, N1: DAG.getConstant(Val: 1, DL: dl, VT: OvfVT), N2: OVF);
3809 [[fallthrough]];
3810 case TargetLoweringBase::ZeroOrOneBooleanContent:
3811 OVF = DAG.getZExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3812 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Hi, N2: OVF);
3813 break;
3814 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3815 OVF = DAG.getSExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3816 Hi = DAG.getNode(Opcode: RevOpc, DL: dl, VT: NVT, N1: Hi, N2: OVF);
3817 }
3818 return;
3819 }
3820
3821 if (N->getOpcode() == ISD::ADD) {
3822 Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: LoOps);
3823 SDValue Cmp;
3824 // Special case: X+1 has a carry out if X+1==0. This may reduce the live
3825 // range of X. We assume comparing with 0 is cheap.
3826 if (isOneConstant(V: LoOps[1]))
3827 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
3828 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3829 else if (isAllOnesConstant(V: LoOps[1])) {
3830 if (isAllOnesConstant(V: HiOps[1]))
3831 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3832 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3833 else
3834 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3835 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
3836 } else
3837 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo, RHS: LoOps[0],
3838 Cond: ISD::SETULT);
3839
3840 SDValue Carry;
3841 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3842 Carry = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3843 else
3844 Carry = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3845 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3846
3847 if (isAllOnesConstant(V: LoOps[1]) && isAllOnesConstant(V: HiOps[1])) {
3848 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: HiOps[0], N2: Carry);
3849 } else {
3850 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3851 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Hi, N2: Carry);
3852 }
3853 } else {
3854 Lo = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: LoOps);
3855 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3856 SDValue Cmp =
3857 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LoOps[0].getValueType()),
3858 LHS: LoOps[0], RHS: LoOps[1], Cond: ISD::SETULT);
3859
3860 SDValue Borrow;
3861 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3862 Borrow = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3863 else
3864 Borrow = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3865 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3866
3867 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Hi, N2: Borrow);
3868 }
3869}
3870
3871void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
3872 SDValue &Lo, SDValue &Hi) {
3873 // Expand the subcomponents.
3874 SDValue LHSL, LHSH, RHSL, RHSH;
3875 SDLoc dl(N);
3876 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3877 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3878 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3879 SDValue LoOps[2] = { LHSL, RHSL };
3880 SDValue HiOps[3] = { LHSH, RHSH };
3881
3882 if (N->getOpcode() == ISD::ADDC) {
3883 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3884 HiOps[2] = Lo.getValue(R: 1);
3885 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3886 } else {
3887 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3888 HiOps[2] = Lo.getValue(R: 1);
3889 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3890 }
3891
3892 // Legalized the flag result - switch anything that used the old flag to
3893 // use the new one.
3894 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3895}
3896
3897void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
3898 SDValue &Lo, SDValue &Hi) {
3899 // Expand the subcomponents.
3900 SDValue LHSL, LHSH, RHSL, RHSH;
3901 SDLoc dl(N);
3902 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3903 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3904 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3905 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3906 SDValue HiOps[3] = { LHSH, RHSH };
3907
3908 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3909 HiOps[2] = Lo.getValue(R: 1);
3910 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
3911
3912 // Legalized the flag result - switch anything that used the old flag to
3913 // use the new one.
3914 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3915}
3916
3917void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
3918 SDValue &Lo, SDValue &Hi) {
3919 SDValue LHS = N->getOperand(Num: 0);
3920 SDValue RHS = N->getOperand(Num: 1);
3921 SDLoc dl(N);
3922
3923 SDValue Ovf;
3924
3925 unsigned CarryOp, NoCarryOp;
3926 ISD::CondCode Cond;
3927 switch(N->getOpcode()) {
3928 case ISD::UADDO:
3929 CarryOp = ISD::UADDO_CARRY;
3930 NoCarryOp = ISD::ADD;
3931 Cond = ISD::SETULT;
3932 break;
3933 case ISD::USUBO:
3934 CarryOp = ISD::USUBO_CARRY;
3935 NoCarryOp = ISD::SUB;
3936 Cond = ISD::SETUGT;
3937 break;
3938 default:
3939 llvm_unreachable("Node has unexpected Opcode");
3940 }
3941
3942 bool HasCarryOp = TLI.isOperationLegalOrCustom(
3943 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
3944
3945 if (HasCarryOp) {
3946 // Expand the subcomponents.
3947 SDValue LHSL, LHSH, RHSL, RHSH;
3948 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3949 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3950 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3951 SDValue LoOps[2] = { LHSL, RHSL };
3952 SDValue HiOps[3] = { LHSH, RHSH };
3953
3954 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3955 HiOps[2] = Lo.getValue(R: 1);
3956 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: HiOps);
3957
3958 Ovf = Hi.getValue(R: 1);
3959 } else {
3960 // Expand the result by simply replacing it with the equivalent
3961 // non-overflow-checking operation.
3962 SDValue Sum = DAG.getNode(Opcode: NoCarryOp, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS);
3963 SplitInteger(Op: Sum, Lo, Hi);
3964
3965 if (N->getOpcode() == ISD::UADDO && isOneConstant(V: RHS)) {
3966 // Special case: uaddo X, 1 overflowed if X+1 == 0. We can detect this
3967 // with (Lo | Hi) == 0.
3968 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Lo.getValueType(), N1: Lo, N2: Hi);
3969 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Or,
3970 RHS: DAG.getConstant(Val: 0, DL: dl, VT: Lo.getValueType()), Cond: ISD::SETEQ);
3971 } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(V: RHS)) {
3972 // Special case: uaddo X, -1 overflows if X == 0.
3973 Ovf =
3974 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS,
3975 RHS: DAG.getConstant(Val: 0, DL: dl, VT: LHS.getValueType()), Cond: ISD::SETNE);
3976 } else {
3977 // Calculate the overflow: addition overflows iff a + b < a, and
3978 // subtraction overflows iff a - b > a.
3979 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Sum, RHS: LHS, Cond);
3980 }
3981 }
3982
3983 // Legalized the flag result - switch anything that used the old flag to
3984 // use the new one.
3985 ReplaceValueWith(From: SDValue(N, 1), To: Ovf);
3986}
3987
3988void DAGTypeLegalizer::ExpandIntRes_UADDSUBO_CARRY(SDNode *N, SDValue &Lo,
3989 SDValue &Hi) {
3990 // Expand the subcomponents.
3991 SDValue LHSL, LHSH, RHSL, RHSH;
3992 SDLoc dl(N);
3993 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3994 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3995 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3996 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3997 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
3998
3999 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
4000 HiOps[2] = Lo.getValue(R: 1);
4001 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
4002
4003 // Legalized the flag result - switch anything that used the old flag to
4004 // use the new one.
4005 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4006}
4007
4008void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
4009 SDValue &Lo, SDValue &Hi) {
4010 // Expand the subcomponents.
4011 SDValue LHSL, LHSH, RHSL, RHSH;
4012 SDLoc dl(N);
4013 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4014 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4015 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4016
4017 // We need to use an unsigned carry op for the lo part.
4018 unsigned CarryOp =
4019 N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
4020 Lo = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSL, RHSL, N->getOperand(Num: 2) });
4021 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4022
4023 // Legalized the flag result - switch anything that used the old flag to
4024 // use the new one.
4025 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4026}
4027
4028void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
4029 SDValue &Lo, SDValue &Hi) {
4030 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4031 SDLoc dl(N);
4032 SDValue Op = N->getOperand(Num: 0);
4033 if (Op.getValueType().bitsLE(VT: NVT)) {
4034 // The low part is any extension of the input (which degenerates to a copy).
4035 Lo = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Op);
4036 Hi = DAG.getUNDEF(VT: NVT); // The high part is undefined.
4037 } else {
4038 // For example, extension of an i48 to an i64. The operand type necessarily
4039 // promotes to the result type, so will end up being expanded too.
4040 assert(getTypeAction(Op.getValueType()) ==
4041 TargetLowering::TypePromoteInteger &&
4042 "Only know how to promote this result!");
4043 SDValue Res = GetPromotedInteger(Op);
4044 assert(Res.getValueType() == N->getValueType(0) &&
4045 "Operand over promoted?");
4046 // Split the promoted operand. This will simplify when it is expanded.
4047 SplitInteger(Op: Res, Lo, Hi);
4048 }
4049}
4050
4051void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
4052 SDValue &Lo, SDValue &Hi) {
4053 SDLoc dl(N);
4054 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4055 EVT NVT = Lo.getValueType();
4056 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4057 unsigned NVTBits = NVT.getSizeInBits();
4058 unsigned EVTBits = EVT.getSizeInBits();
4059
4060 if (NVTBits < EVTBits) {
4061 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Hi,
4062 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4063 BitWidth: EVTBits - NVTBits)));
4064 } else {
4065 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4066 // The high part replicates the sign bit of Lo, make it explicit.
4067 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4068 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL: dl));
4069 }
4070}
4071
4072void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
4073 SDValue &Lo, SDValue &Hi) {
4074 SDLoc dl(N);
4075 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4076 EVT NVT = Lo.getValueType();
4077 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4078 unsigned NVTBits = NVT.getSizeInBits();
4079 unsigned EVTBits = EVT.getSizeInBits();
4080
4081 if (NVTBits < EVTBits) {
4082 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Hi,
4083 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4084 BitWidth: EVTBits - NVTBits)));
4085 } else {
4086 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4087 // The high part must be zero, make it explicit.
4088 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4089 }
4090}
4091
4092void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
4093 SDValue &Lo, SDValue &Hi) {
4094 SDLoc dl(N);
4095 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4096 Lo = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4097 Hi = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4098}
4099
4100void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
4101 SDValue &Lo, SDValue &Hi) {
4102 SDLoc dl(N);
4103 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4104 Lo = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4105 Hi = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4106}
4107
4108void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
4109 SDValue &Hi) {
4110 SDLoc dl(N);
4111 // parity(HiLo) -> parity(Lo^Hi)
4112 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4113 EVT NVT = Lo.getValueType();
4114 Lo =
4115 DAG.getNode(Opcode: ISD::PARITY, DL: dl, VT: NVT, Operand: DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Hi));
4116 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4117}
4118
4119void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
4120 SDValue &Lo, SDValue &Hi) {
4121 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4122 unsigned NBitWidth = NVT.getSizeInBits();
4123 auto Constant = cast<ConstantSDNode>(Val: N);
4124 const APInt &Cst = Constant->getAPIntValue();
4125 bool IsTarget = Constant->isTargetOpcode();
4126 bool IsOpaque = Constant->isOpaque();
4127 SDLoc dl(N);
4128 Lo = DAG.getConstant(Val: Cst.trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget, isOpaque: IsOpaque);
4129 Hi = DAG.getConstant(Val: Cst.lshr(shiftAmt: NBitWidth).trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget,
4130 isOpaque: IsOpaque);
4131}
4132
4133void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4134 SDLoc dl(N);
4135
4136 SDValue N0 = N->getOperand(Num: 0);
4137 GetExpandedInteger(Op: N0, Lo, Hi);
4138 EVT NVT = Lo.getValueType();
4139
4140 // If the upper half is all sign bits, then we can perform the ABS on the
4141 // lower half and zero-extend.
4142 if (DAG.ComputeNumSignBits(Op: N0) > NVT.getScalarSizeInBits()) {
4143 Lo = DAG.getNode(Opcode: ISD::ABS, DL: dl, VT: NVT, Operand: Lo);
4144 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4145 return;
4146 }
4147
4148 // If we have USUBO_CARRY, use the expanded form of the sra+xor+sub sequence
4149 // we use in LegalizeDAG. The SUB part of the expansion is based on
4150 // ExpandIntRes_ADDSUB which also uses USUBO_CARRY/USUBO after checking that
4151 // USUBO_CARRY is LegalOrCustom. Each of the pieces here can be further
4152 // expanded if needed. Shift expansion has a special case for filling with
4153 // sign bits so that we will only end up with one SRA.
4154 bool HasSubCarry = TLI.isOperationLegalOrCustom(
4155 Op: ISD::USUBO_CARRY, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
4156 if (HasSubCarry) {
4157 SDValue Sign = DAG.getNode(
4158 Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Hi,
4159 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - 1, VT: NVT, DL: dl));
4160 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
4161 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Sign);
4162 Hi = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Hi, N2: Sign);
4163 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: Lo, N2: Sign);
4164 Hi = DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: Hi, N2: Sign, N3: Lo.getValue(R: 1));
4165 return;
4166 }
4167
4168 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
4169 EVT VT = N->getValueType(ResNo: 0);
4170 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT,
4171 N1: DAG.getConstant(Val: 0, DL: dl, VT), N2: N0);
4172 SDValue NegLo, NegHi;
4173 SplitInteger(Op: Neg, Lo&: NegLo, Hi&: NegHi);
4174
4175 SDValue HiIsNeg = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4176 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETLT);
4177 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegLo, RHS: Lo);
4178 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegHi, RHS: Hi);
4179}
4180
4181void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
4182 SDValue &Lo, SDValue &Hi) {
4183 SDLoc dl(N);
4184 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
4185 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4186 EVT NVT = Lo.getValueType();
4187
4188 SDValue HiNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4189 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4190
4191 SDValue LoLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Lo);
4192 SDValue HiLZ = DAG.getNode(Opcode: ISD::CTLZ_ZERO_UNDEF, DL: dl, VT: NVT, Operand: Hi);
4193
4194 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiNotZero, LHS: HiLZ,
4195 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoLZ,
4196 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4197 VT: NVT)));
4198 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4199}
4200
4201void DAGTypeLegalizer::ExpandIntRes_CTLS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4202 SDLoc dl(N);
4203 // ctls(HiLo) -> if (IsAllSignBits = (ctls(Hi) == BW-1)) then
4204 // BW-1 + clz(IsNegative = (Hi < 0) ? ~Lo : Lo)
4205 // else ctls(Hi)
4206 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4207 EVT NVT = Lo.getValueType();
4208 unsigned NVTBits = NVT.getScalarSizeInBits();
4209
4210 SDValue Constant0 = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4211 SDValue ConstantBWM1 = DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: NVT);
4212
4213 SDValue HiCTLS = DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Hi);
4214 SDValue IsAllSignBits = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: HiCTLS,
4215 RHS: ConstantBWM1, Cond: ISD::SETEQ);
4216 SDValue IsNegative =
4217 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi, RHS: Constant0, Cond: ISD::SETLT);
4218 SDValue AdjustedLo =
4219 DAG.getSelect(DL: dl, VT: NVT, Cond: IsNegative, LHS: DAG.getNOT(DL: dl, Val: Lo, VT: NVT), RHS: Lo);
4220 SDValue LoCLZ = DAG.getNode(Opcode: ISD::CTLZ, DL: dl, VT: NVT, Operand: AdjustedLo);
4221 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: IsAllSignBits,
4222 LHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoCLZ, N2: ConstantBWM1),
4223 RHS: HiCTLS);
4224 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4225}
4226
4227void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
4228 SDValue Result = TLI.expandABD(N, DAG);
4229 SplitInteger(Op: Result, Lo, Hi);
4230}
4231
4232void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
4233 SDValue Op = N->getOperand(Num: 0);
4234 EVT VT = N->getValueType(ResNo: 0);
4235 SDLoc DL(N);
4236
4237 if (TLI.getOperationAction(Op: ISD::CTPOP, VT) == TargetLoweringBase::LibCall) {
4238 RTLIB::Libcall LC = RTLIB::getCTPOP(VT);
4239 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
4240 "LibCall explicitly requested, but not available");
4241
4242 if (RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
4243 TargetLowering::MakeLibCallOptions CallOptions;
4244 EVT IntVT =
4245 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
4246 SDValue Res =
4247 TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: IntVT, Ops: Op, CallOptions, dl: DL).first;
4248 SplitInteger(Op: DAG.getSExtOrTrunc(Op: Res, DL, VT), Lo, Hi);
4249 return;
4250 }
4251
4252 // If the function is not available, fall back on the expansion.
4253 }
4254
4255 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
4256 GetExpandedInteger(Op, Lo, Hi);
4257 EVT NVT = Lo.getValueType();
4258 Lo = DAG.getNode(Opcode: ISD::ADD, DL, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Lo),
4259 N2: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Hi));
4260 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
4261}
4262
4263void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
4264 SDValue &Lo, SDValue &Hi) {
4265 SDLoc dl(N);
4266 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
4267 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4268 EVT NVT = Lo.getValueType();
4269
4270 SDValue LoNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
4271 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4272
4273 SDValue LoLZ = DAG.getNode(Opcode: ISD::CTTZ_ZERO_UNDEF, DL: dl, VT: NVT, Operand: Lo);
4274 SDValue HiLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Hi);
4275
4276 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: LoNotZero, LHS: LoLZ,
4277 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: HiLZ,
4278 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4279 VT: NVT)));
4280 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4281}
4282
4283void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo,
4284 SDValue &Hi) {
4285 SDLoc dl(N);
4286 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4287 unsigned NBitWidth = NVT.getSizeInBits();
4288
4289 Lo = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
4290 SDValue Chain = Lo.getValue(R: 1);
4291 // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING
4292 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4293 N2: DAG.getShiftAmountConstant(Val: NBitWidth - 1, VT: NVT, DL: dl));
4294
4295 // Legalize the chain result - switch anything that used the old chain to
4296 // use the new one.
4297 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
4298}
4299
4300// Helper for producing an FP_EXTEND/STRICT_FP_EXTEND of Op.
4301static SDValue fpExtendHelper(SDValue Op, SDValue &Chain, bool IsStrict, EVT VT,
4302 SDLoc DL, SelectionDAG &DAG) {
4303 if (IsStrict) {
4304 Op = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL, ResultTys: {VT, MVT::Other}, Ops: {Chain, Op});
4305 Chain = Op.getValue(R: 1);
4306 return Op;
4307 }
4308 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT, Operand: Op);
4309}
4310
4311void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
4312 SDValue &Hi) {
4313 SDLoc dl(N);
4314 EVT VT = N->getValueType(ResNo: 0);
4315
4316 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
4317 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
4318 bool IsStrict = N->isStrictFPOpcode();
4319 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4320 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4321
4322 // If the input is bf16 or needs to be soft promoted, extend to f32.
4323 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf ||
4324 Op.getValueType() == MVT::bf16) {
4325 Op = fpExtendHelper(Op, Chain, IsStrict, VT: MVT::f32, DL: dl, DAG);
4326 }
4327
4328 // NOTE: We need a variable that lives across makeLibCall so
4329 // CallOptions.setTypeListBeforeSoften can save a reference to it.
4330 EVT OpVT = Op.getValueType();
4331
4332 RTLIB::Libcall LC =
4333 IsSigned ? RTLIB::getFPTOSINT(OpVT, RetVT: VT) : RTLIB::getFPTOUINT(OpVT, RetVT: VT);
4334 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
4335 TargetLowering::MakeLibCallOptions CallOptions;
4336 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftenFloat)
4337 CallOptions.setTypeListBeforeSoften(OpsVT: OpVT, RetVT: VT);
4338 else
4339 CallOptions.setIsSigned(true); // FIXME: Is this needed?
4340 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op,
4341 CallOptions, dl, Chain);
4342 SplitInteger(Op: Tmp.first, Lo, Hi);
4343
4344 if (IsStrict)
4345 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4346}
4347
4348void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
4349 SDValue &Hi) {
4350 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
4351 SplitInteger(Op: Res, Lo, Hi);
4352}
4353
4354void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo,
4355 SDValue &Hi) {
4356 SDLoc dl(N);
4357 bool IsStrict = N->isStrictFPOpcode();
4358 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4359 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4360
4361 EVT VT = Op.getValueType();
4362
4363 if (VT == MVT::f16) {
4364 // Extend to f32.
4365 VT = MVT::f32;
4366 Op = fpExtendHelper(Op, Chain, IsStrict, VT, DL: dl, DAG);
4367 }
4368
4369 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4370 if (N->getOpcode() == ISD::LROUND ||
4371 N->getOpcode() == ISD::STRICT_LROUND) {
4372 LC = RTLIB::getLROUND(VT);
4373 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lround input type!");
4374 } else if (N->getOpcode() == ISD::LRINT ||
4375 N->getOpcode() == ISD::STRICT_LRINT) {
4376 LC = RTLIB::getLRINT(RetVT: VT);
4377 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lrint input type!");
4378 } else if (N->getOpcode() == ISD::LLROUND ||
4379 N->getOpcode() == ISD::STRICT_LLROUND) {
4380 LC = RTLIB::getLLROUND(VT);
4381 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
4382 } else if (N->getOpcode() == ISD::LLRINT ||
4383 N->getOpcode() == ISD::STRICT_LLRINT) {
4384 LC = RTLIB::getLLRINT(RetVT: VT);
4385 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
4386 } else
4387 llvm_unreachable("Unexpected opcode!");
4388
4389 EVT RetVT = N->getValueType(ResNo: 0);
4390
4391 TargetLowering::MakeLibCallOptions CallOptions;
4392 CallOptions.setIsSigned(true);
4393 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
4394 Ops: Op, CallOptions, dl,
4395 Chain);
4396 SplitInteger(Op: Tmp.first, Lo, Hi);
4397
4398 if (N->isStrictFPOpcode())
4399 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4400}
4401
4402void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
4403 SDValue &Lo, SDValue &Hi) {
4404 assert(!N->isAtomic() && "Should have been a ATOMIC_LOAD?");
4405
4406 if (ISD::isNormalLoad(N)) {
4407 ExpandRes_NormalLoad(N, Lo, Hi);
4408 return;
4409 }
4410
4411 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
4412
4413 EVT VT = N->getValueType(ResNo: 0);
4414 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4415 SDValue Ch = N->getChain();
4416 SDValue Ptr = N->getBasePtr();
4417 ISD::LoadExtType ExtType = N->getExtensionType();
4418 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4419 AAMDNodes AAInfo = N->getAAInfo();
4420 SDLoc dl(N);
4421
4422 assert(NVT.isByteSized() && "Expanded type not byte sized!");
4423
4424 if (N->getMemoryVT().bitsLE(VT: NVT)) {
4425 EVT MemVT = N->getMemoryVT();
4426
4427 Lo = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), MemVT,
4428 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4429
4430 // Remember the chain.
4431 Ch = Lo.getValue(R: 1);
4432
4433 if (ExtType == ISD::SEXTLOAD) {
4434 // The high part is obtained by SRA'ing all but one of the bits of the
4435 // lo part.
4436 unsigned LoSize = Lo.getValueSizeInBits();
4437 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4438 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
4439 } else if (ExtType == ISD::ZEXTLOAD) {
4440 // The high part is just a zero.
4441 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4442 } else {
4443 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
4444 // The high part is undefined.
4445 Hi = DAG.getUNDEF(VT: NVT);
4446 }
4447 } else if (DAG.getDataLayout().isLittleEndian()) {
4448 // Little-endian - low bits are at low addresses.
4449 Lo = DAG.getLoad(VT: NVT, dl, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
4450 MMOFlags, AAInfo);
4451
4452 unsigned ExcessBits =
4453 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4454 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
4455
4456 // Increment the pointer to the other half.
4457 unsigned IncrementSize = NVT.getSizeInBits()/8;
4458 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4459 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr,
4460 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize), MemVT: NEVT,
4461 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4462
4463 // Build a factor node to remember that this load is independent of the
4464 // other one.
4465 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4466 N2: Hi.getValue(R: 1));
4467 } else {
4468 // Big-endian - high bits are at low addresses. Favor aligned loads at
4469 // the cost of some bit-fiddling.
4470 EVT MemVT = N->getMemoryVT();
4471 unsigned EBytes = MemVT.getStoreSize();
4472 unsigned IncrementSize = NVT.getSizeInBits()/8;
4473 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4474
4475 // Load both the high bits and maybe some of the low bits.
4476 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(),
4477 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(),
4478 BitWidth: MemVT.getSizeInBits() - ExcessBits),
4479 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4480
4481 // Increment the pointer to the other half.
4482 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4483 // Load the rest of the low bits.
4484 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: NVT, Chain: Ch, Ptr,
4485 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
4486 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
4487 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4488
4489 // Build a factor node to remember that this load is independent of the
4490 // other one.
4491 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4492 N2: Hi.getValue(R: 1));
4493
4494 if (ExcessBits < NVT.getSizeInBits()) {
4495 // Transfer low bits from the bottom of Hi to the top of Lo.
4496 Lo = DAG.getNode(
4497 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Lo,
4498 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
4499 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
4500 // Move high bits to the right position in Hi.
4501 Hi = DAG.getNode(Opcode: ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
4502 N1: Hi,
4503 N2: DAG.getShiftAmountConstant(
4504 Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
4505 }
4506 }
4507
4508 // Legalize the chain result - switch anything that used the old chain to
4509 // use the new one.
4510 ReplaceValueWith(From: SDValue(N, 1), To: Ch);
4511}
4512
4513void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
4514 SDValue &Lo, SDValue &Hi) {
4515 SDLoc dl(N);
4516 SDValue LL, LH, RL, RH;
4517 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4518 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4519
4520 SDNodeFlags Flags;
4521 if (N->getOpcode() == ISD::OR)
4522 Flags.setDisjoint(N->getFlags().hasDisjoint());
4523
4524 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LL, N2: RL, Flags);
4525 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LH, N2: RH, Flags);
4526}
4527
4528void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
4529 SDValue &Lo, SDValue &Hi) {
4530 EVT VT = N->getValueType(ResNo: 0);
4531 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4532 SDLoc dl(N);
4533
4534 SDValue LL, LH, RL, RH;
4535 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4536 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4537
4538 if (TLI.expandMUL(N, Lo, Hi, HiLoVT: NVT, DAG,
4539 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4540 LL, LH, RL, RH))
4541 return;
4542
4543 // If nothing else, we can make a libcall.
4544 RTLIB::Libcall LC = RTLIB::getMUL(VT);
4545 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
4546 if (LCImpl == RTLIB::Unsupported) {
4547 // Perform a wide multiplication where the wide type is the original VT and
4548 // the 4 parts are the split arguments.
4549 TLI.forceExpandMultiply(DAG, dl, /*Signed=*/false, Lo, Hi, LHS: LL, RHS: RL, HiLHS: LH, HiRHS: RH);
4550 return;
4551 }
4552
4553 // Note that we don't need to do a wide MUL here since we don't care about the
4554 // upper half of the result if it exceeds VT.
4555 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4556 TargetLowering::MakeLibCallOptions CallOptions;
4557 CallOptions.setIsSigned(true);
4558 SplitInteger(Op: TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
4559 Hi);
4560}
4561
4562void DAGTypeLegalizer::ExpandIntRes_READCOUNTER(SDNode *N, SDValue &Lo,
4563 SDValue &Hi) {
4564 SDLoc DL(N);
4565 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4566 SDVTList VTs = DAG.getVTList(VT1: NVT, VT2: NVT, VT3: MVT::Other);
4567 SDValue R = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N: N->getOperand(Num: 0));
4568 Lo = R.getValue(R: 0);
4569 Hi = R.getValue(R: 1);
4570 ReplaceValueWith(From: SDValue(N, 1), To: R.getValue(R: 2));
4571}
4572
4573void DAGTypeLegalizer::ExpandIntRes_AVG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4574 SDValue Result = TLI.expandAVG(N, DAG);
4575 SplitInteger(Op: Result, Lo, Hi);
4576}
4577
4578void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
4579 SDValue &Hi) {
4580 SDValue Result = TLI.expandAddSubSat(Node: N, DAG);
4581 SplitInteger(Op: Result, Lo, Hi);
4582}
4583
4584void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
4585 SDValue &Hi) {
4586 SDValue Result = TLI.expandShlSat(Node: N, DAG);
4587 SplitInteger(Op: Result, Lo, Hi);
4588}
4589
4590/// This performs an expansion of the integer result for a fixed point
4591/// multiplication. The default expansion performs rounding down towards
4592/// negative infinity, though targets that do care about rounding should specify
4593/// a target hook for rounding and provide their own expansion or lowering of
4594/// fixed point multiplication to be consistent with rounding.
4595void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
4596 SDValue &Hi) {
4597 SDLoc dl(N);
4598 EVT VT = N->getValueType(ResNo: 0);
4599 unsigned VTSize = VT.getScalarSizeInBits();
4600 SDValue LHS = N->getOperand(Num: 0);
4601 SDValue RHS = N->getOperand(Num: 1);
4602 uint64_t Scale = N->getConstantOperandVal(Num: 2);
4603 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
4604 N->getOpcode() == ISD::UMULFIXSAT);
4605 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
4606 N->getOpcode() == ISD::SMULFIXSAT);
4607
4608 // Handle special case when scale is equal to zero.
4609 if (!Scale) {
4610 SDValue Result;
4611 if (!Saturating) {
4612 Result = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS);
4613 } else {
4614 EVT BoolVT = getSetCCResultType(VT);
4615 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
4616 Result = DAG.getNode(Opcode: MulOp, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: BoolVT), N1: LHS, N2: RHS);
4617 SDValue Product = Result.getValue(R: 0);
4618 SDValue Overflow = Result.getValue(R: 1);
4619 if (Signed) {
4620 APInt MinVal = APInt::getSignedMinValue(numBits: VTSize);
4621 APInt MaxVal = APInt::getSignedMaxValue(numBits: VTSize);
4622 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT);
4623 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4624 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
4625 // Xor the inputs, if resulting sign bit is 0 the product will be
4626 // positive, else negative.
4627 SDValue Xor = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4628 SDValue ProdNeg = DAG.getSetCC(DL: dl, VT: BoolVT, LHS: Xor, RHS: Zero, Cond: ISD::SETLT);
4629 Result = DAG.getSelect(DL: dl, VT, Cond: ProdNeg, LHS: SatMin, RHS: SatMax);
4630 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: Result, RHS: Product);
4631 } else {
4632 // For unsigned multiplication, we only need to check the max since we
4633 // can't really overflow towards zero.
4634 APInt MaxVal = APInt::getMaxValue(numBits: VTSize);
4635 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4636 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: SatMax, RHS: Product);
4637 }
4638 }
4639 SplitInteger(Op: Result, Lo, Hi);
4640 return;
4641 }
4642
4643 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
4644 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
4645 assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
4646
4647 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4648 SDValue LL, LH, RL, RH;
4649 GetExpandedInteger(Op: LHS, Lo&: LL, Hi&: LH);
4650 GetExpandedInteger(Op: RHS, Lo&: RL, Hi&: RH);
4651 SmallVector<SDValue, 4> Result;
4652
4653 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
4654 if (!TLI.expandMUL_LOHI(Opcode: LoHiOp, VT, dl, LHS, RHS, Result, HiLoVT: NVT, DAG,
4655 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4656 LL, LH, RL, RH)) {
4657 Result.clear();
4658 Result.resize(N: 4);
4659
4660 SDValue LoTmp, HiTmp;
4661 TLI.forceExpandWideMUL(DAG, dl, Signed, LHS, RHS, Lo&: LoTmp, Hi&: HiTmp);
4662 SplitInteger(Op: LoTmp, Lo&: Result[0], Hi&: Result[1]);
4663 SplitInteger(Op: HiTmp, Lo&: Result[2], Hi&: Result[3]);
4664 }
4665 assert(Result.size() == 4 && "Unexpected number of partlets in the result");
4666
4667 unsigned NVTSize = NVT.getScalarSizeInBits();
4668 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
4669 "the size of the current value type");
4670
4671 // After getting the multiplication result in 4 parts, we need to perform a
4672 // shift right by the amount of the scale to get the result in that scale.
4673 //
4674 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
4675 // 128 bits that are cut into 4 32-bit parts:
4676 //
4677 // HH HL LH LL
4678 // |---32---|---32---|---32---|---32---|
4679 // 128 96 64 32 0
4680 //
4681 // |------VTSize-----|
4682 //
4683 // |NVTSize-|
4684 //
4685 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
4686 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
4687 // amount and get Lo and Hi using two funnel shifts. Or for the special case
4688 // when Scale is a multiple of NVTSize we can just pick the result without
4689 // shifting.
4690 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
4691 if (Scale % NVTSize) {
4692 SDValue ShiftAmount = DAG.getShiftAmountConstant(Val: Scale % NVTSize, VT: NVT, DL: dl);
4693 Lo = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 1], N2: Result[Part0],
4694 N3: ShiftAmount);
4695 Hi = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 2], N2: Result[Part0 + 1],
4696 N3: ShiftAmount);
4697 } else {
4698 Lo = Result[Part0];
4699 Hi = Result[Part0 + 1];
4700 }
4701
4702 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
4703 if (!Saturating)
4704 return;
4705
4706 // Can not overflow when there is no integer part.
4707 if (Scale == VTSize)
4708 return;
4709
4710 // To handle saturation we must check for overflow in the multiplication.
4711 //
4712 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
4713 // aren't all zeroes.
4714 //
4715 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
4716 // aren't all ones or all zeroes.
4717 //
4718 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
4719 // highest bit of HH determines saturation direction in the event of signed
4720 // saturation.
4721
4722 SDValue ResultHL = Result[2];
4723 SDValue ResultHH = Result[3];
4724
4725 SDValue SatMax, SatMin;
4726 SDValue NVTZero = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4727 SDValue NVTNeg1 = DAG.getAllOnesConstant(DL: dl, VT: NVT);
4728 EVT BoolNVT = getSetCCResultType(VT: NVT);
4729
4730 if (!Signed) {
4731 if (Scale < NVTSize) {
4732 // Overflow happened if ((HH | (HL >> Scale)) != 0).
4733 SDValue HLAdjusted =
4734 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4735 N2: DAG.getShiftAmountConstant(Val: Scale, VT: NVT, DL: dl));
4736 SDValue Tmp = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: HLAdjusted, N2: ResultHH);
4737 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: Tmp, RHS: NVTZero, Cond: ISD::SETNE);
4738 } else if (Scale == NVTSize) {
4739 // Overflow happened if (HH != 0).
4740 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETNE);
4741 } else if (Scale < VTSize) {
4742 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
4743 SDValue HLAdjusted =
4744 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4745 N2: DAG.getShiftAmountConstant(Val: Scale - NVTSize, VT: NVT, DL: dl));
4746 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: HLAdjusted, RHS: NVTZero, Cond: ISD::SETNE);
4747 } else
4748 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
4749 "(and saturation can't happen with Scale==VTSize).");
4750
4751 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Hi);
4752 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Lo);
4753 return;
4754 }
4755
4756 if (Scale < NVTSize) {
4757 // The number of overflow bits we can check are VTSize - Scale + 1 (we
4758 // include the sign bit). If these top bits are > 0, then we overflowed past
4759 // the max value. If these top bits are < -1, then we overflowed past the
4760 // min value. Otherwise, we did not overflow.
4761 unsigned OverflowBits = VTSize - Scale + 1;
4762 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
4763 "Extent of overflow bits must start within HL");
4764 SDValue HLHiMask = DAG.getConstant(
4765 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits - NVTSize), DL: dl, VT: NVT);
4766 SDValue HLLoMask = DAG.getConstant(
4767 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: VTSize - OverflowBits), DL: dl, VT: NVT);
4768 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
4769 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4770 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4771 SDValue HLUGT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLLoMask, Cond: ISD::SETUGT);
4772 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4773 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLUGT));
4774 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
4775 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4776 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4777 SDValue HLULT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLHiMask, Cond: ISD::SETULT);
4778 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4779 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLULT));
4780 } else if (Scale == NVTSize) {
4781 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
4782 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4783 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4784 SDValue HLNeg = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETLT);
4785 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4786 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLNeg));
4787 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
4788 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4789 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4790 SDValue HLPos = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETGE);
4791 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4792 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLPos));
4793 } else if (Scale < VTSize) {
4794 // This is similar to the case when we saturate if Scale < NVTSize, but we
4795 // only need to check HH.
4796 unsigned OverflowBits = VTSize - Scale + 1;
4797 SDValue HHHiMask = DAG.getConstant(
4798 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits), DL: dl, VT: NVT);
4799 SDValue HHLoMask = DAG.getConstant(
4800 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: NVTSize - OverflowBits), DL: dl, VT: NVT);
4801 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHLoMask, Cond: ISD::SETGT);
4802 SatMin = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHHiMask, Cond: ISD::SETLT);
4803 } else
4804 llvm_unreachable("Illegal scale for signed fixed point mul.");
4805
4806 // Saturate to signed maximum.
4807 APInt MaxHi = APInt::getSignedMaxValue(numBits: NVTSize);
4808 APInt MaxLo = APInt::getAllOnes(numBits: NVTSize);
4809 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxHi, DL: dl, VT: NVT), RHS: Hi);
4810 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxLo, DL: dl, VT: NVT), RHS: Lo);
4811 // Saturate to signed minimum.
4812 APInt MinHi = APInt::getSignedMinValue(numBits: NVTSize);
4813 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: DAG.getConstant(Val: MinHi, DL: dl, VT: NVT), RHS: Hi);
4814 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: NVTZero, RHS: Lo);
4815}
4816
4817void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
4818 SDValue &Hi) {
4819 SDLoc dl(N);
4820 // Try expanding in the existing type first.
4821 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: N->getOperand(Num: 0),
4822 RHS: N->getOperand(Num: 1),
4823 Scale: N->getConstantOperandVal(Num: 2), DAG);
4824
4825 if (!Res)
4826 Res = earlyExpandDIVFIX(N, LHS: N->getOperand(Num: 0), RHS: N->getOperand(Num: 1),
4827 Scale: N->getConstantOperandVal(Num: 2), TLI, DAG);
4828 SplitInteger(Op: Res, Lo, Hi);
4829}
4830
4831void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
4832 SDValue &Lo, SDValue &Hi) {
4833 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
4834 "Node has unexpected Opcode");
4835 SDValue LHS = Node->getOperand(Num: 0);
4836 SDValue RHS = Node->getOperand(Num: 1);
4837 SDLoc dl(Node);
4838
4839 SDValue Ovf;
4840
4841 bool IsAdd = Node->getOpcode() == ISD::SADDO;
4842 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
4843
4844 bool HasCarryOp = TLI.isOperationLegalOrCustom(
4845 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
4846
4847 if (HasCarryOp) {
4848 // Expand the subcomponents.
4849 SDValue LHSL, LHSH, RHSL, RHSH;
4850 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
4851 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
4852 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: Node->getValueType(ResNo: 1));
4853
4854 Lo = DAG.getNode(Opcode: IsAdd ? ISD::UADDO : ISD::USUBO, DL: dl, VTList, Ops: {LHSL, RHSL});
4855 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4856
4857 Ovf = Hi.getValue(R: 1);
4858 } else {
4859 // Expand the result by simply replacing it with the equivalent
4860 // non-overflow-checking operation.
4861 SDValue Sum = DAG.getNode(Opcode: Node->getOpcode() == ISD::SADDO ?
4862 ISD::ADD : ISD::SUB, DL: dl, VT: LHS.getValueType(),
4863 N1: LHS, N2: RHS);
4864 SplitInteger(Op: Sum, Lo, Hi);
4865
4866 // Compute the overflow.
4867 //
4868 // LHSSign -> LHS < 0
4869 // RHSSign -> RHS < 0
4870 // SumSign -> Sum < 0
4871 //
4872 // Add:
4873 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4874 // Sub:
4875 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4876 //
4877 // To get better codegen we can rewrite this by doing bitwise math on
4878 // the integers and extract the final sign bit at the end. So the
4879 // above becomes:
4880 //
4881 // Add:
4882 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
4883 // Sub:
4884 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
4885 //
4886 // NOTE: This is different than the expansion we do in expandSADDSUBO
4887 // because it is more costly to determine the RHS is > 0 for SSUBO with the
4888 // integers split.
4889 EVT VT = LHS.getValueType();
4890 SDValue SignsMatch = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4891 if (IsAdd)
4892 SignsMatch = DAG.getNOT(DL: dl, Val: SignsMatch, VT);
4893
4894 SDValue SumSignNE = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: Sum);
4895 Ovf = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: SignsMatch, N2: SumSignNE);
4896 EVT OType = Node->getValueType(ResNo: 1);
4897 Ovf = DAG.getSetCC(DL: dl, VT: OType, LHS: Ovf, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETLT);
4898 }
4899
4900 // Use the calculated overflow everywhere.
4901 ReplaceValueWith(From: SDValue(Node, 1), To: Ovf);
4902}
4903
4904void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
4905 SDValue &Lo, SDValue &Hi) {
4906 EVT VT = N->getValueType(ResNo: 0);
4907 SDLoc dl(N);
4908 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4909
4910 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
4911 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
4912 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
4913 return;
4914 }
4915
4916 RTLIB::Libcall LC = RTLIB::getSDIV(VT);
4917 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
4918
4919 TargetLowering::MakeLibCallOptions CallOptions;
4920 CallOptions.setIsSigned(true);
4921 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
4922}
4923
4924void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
4925 SDValue &Hi) {
4926 SDLoc dl(N);
4927 SDValue Shiftee = N->getOperand(Num: 0);
4928 EVT VT = Shiftee.getValueType();
4929 SDValue ShAmt = N->getOperand(Num: 1);
4930 EVT ShAmtVT = ShAmt.getValueType();
4931
4932 EVT LoadVT = VT;
4933 do {
4934 LoadVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: LoadVT);
4935 } while (!TLI.isTypeLegal(VT: LoadVT));
4936
4937 const unsigned ShiftUnitInBits = LoadVT.getStoreSizeInBits();
4938 assert(ShiftUnitInBits <= VT.getScalarSizeInBits());
4939 assert(isPowerOf2_32(ShiftUnitInBits) &&
4940 "Shifting unit is not a a power of two!");
4941
4942 const bool IsOneStepShift =
4943 DAG.computeKnownBits(Op: ShAmt).countMinTrailingZeros() >=
4944 Log2_32(Value: ShiftUnitInBits);
4945
4946 // If we can't do it as one step, we'll have two uses of shift amount,
4947 // and thus must freeze it.
4948 if (!IsOneStepShift)
4949 ShAmt = DAG.getFreeze(V: ShAmt);
4950
4951 unsigned VTBitWidth = VT.getScalarSizeInBits();
4952 assert(VTBitWidth % 8 == 0 && "Shifting a not byte multiple value?");
4953 unsigned VTByteWidth = VTBitWidth / 8;
4954 assert(isPowerOf2_32(VTByteWidth) &&
4955 "Shiftee type size is not a power of two!");
4956 unsigned StackSlotByteWidth = 2 * VTByteWidth;
4957 unsigned StackSlotBitWidth = 8 * StackSlotByteWidth;
4958 EVT StackSlotVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StackSlotBitWidth);
4959
4960 // Get a temporary stack slot 2x the width of our VT.
4961 // FIXME: reuse stack slots?
4962 Align StackAlign = DAG.getReducedAlign(VT: StackSlotVT, /*UseABI=*/false);
4963 SDValue StackPtr =
4964 DAG.CreateStackTemporary(Bytes: StackSlotVT.getStoreSize(), Alignment: StackAlign);
4965 EVT PtrTy = StackPtr.getValueType();
4966 SDValue Ch = DAG.getEntryNode();
4967
4968 MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
4969 MF&: DAG.getMachineFunction(),
4970 FI: cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex());
4971
4972 // Extend the value, that is being shifted, to the entire stack slot's width.
4973 SDValue Init;
4974 if (N->getOpcode() != ISD::SHL) {
4975 unsigned WideningOpc =
4976 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4977 Init = DAG.getNode(Opcode: WideningOpc, DL: dl, VT: StackSlotVT, Operand: Shiftee);
4978 } else {
4979 // For left-shifts, pad the Shiftee's LSB with zeros to twice it's width.
4980 SDValue AllZeros = DAG.getConstant(Val: 0, DL: dl, VT);
4981 Init = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: StackSlotVT, N1: AllZeros, N2: Shiftee);
4982 }
4983 // And spill it into the stack slot.
4984 Ch = DAG.getStore(Chain: Ch, dl, Val: Init, Ptr: StackPtr, PtrInfo: StackPtrInfo, Alignment: StackAlign);
4985
4986 // Now, compute the full-byte offset into stack slot from where we can load.
4987 // We have shift amount, which is in bits. Offset should point to an aligned
4988 // address.
4989 SDNodeFlags Flags;
4990 Flags.setExact(IsOneStepShift);
4991 SDValue SrlTmp = DAG.getNode(
4992 Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: ShAmt,
4993 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT), Flags);
4994 SDValue BitOffset =
4995 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: ShAmtVT, N1: SrlTmp,
4996 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT));
4997
4998 SDValue ByteOffset =
4999 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: BitOffset,
5000 N2: DAG.getConstant(Val: 3, DL: dl, VT: ShAmtVT), Flags: SDNodeFlags::Exact);
5001 // And clamp it, because OOB load is an immediate UB,
5002 // while shift overflow would have *just* been poison.
5003 ByteOffset = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ByteOffset,
5004 N2: DAG.getConstant(Val: VTByteWidth - 1, DL: dl, VT: ShAmtVT));
5005 // We have exactly two strategies on indexing into stack slot here:
5006 // 1. upwards starting from the beginning of the slot
5007 // 2. downwards starting from the middle of the slot
5008 // On little-endian machine, we pick 1. for right shifts and 2. for left-shift
5009 // and vice versa on big-endian machine.
5010 bool WillIndexUpwards = N->getOpcode() != ISD::SHL;
5011 if (DAG.getDataLayout().isBigEndian())
5012 WillIndexUpwards = !WillIndexUpwards;
5013
5014 SDValue AdjStackPtr;
5015 if (WillIndexUpwards) {
5016 AdjStackPtr = StackPtr;
5017 } else {
5018 AdjStackPtr = DAG.getMemBasePlusOffset(
5019 Base: StackPtr, Offset: DAG.getConstant(Val: VTByteWidth, DL: dl, VT: PtrTy), DL: dl);
5020 ByteOffset = DAG.getNegative(Val: ByteOffset, DL: dl, VT: ShAmtVT);
5021 }
5022
5023 // Get the pointer somewhere into the stack slot from which we need to load.
5024 ByteOffset = DAG.getSExtOrTrunc(Op: ByteOffset, DL: dl, VT: PtrTy);
5025 AdjStackPtr = DAG.getMemBasePlusOffset(Base: AdjStackPtr, Offset: ByteOffset, DL: dl);
5026
5027 // And load it! While the load is not legal, legalizing it is obvious.
5028 SDValue Res =
5029 DAG.getLoad(VT, dl, Chain: Ch, Ptr: AdjStackPtr,
5030 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
5031 Alignment: commonAlignment(A: StackAlign, Offset: LoadVT.getStoreSize()));
5032
5033 // If we may still have a remaining bits to shift by, do so now.
5034 if (!IsOneStepShift) {
5035 SDValue ShAmtRem =
5036 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ShAmt,
5037 N2: DAG.getConstant(Val: ShiftUnitInBits - 1, DL: dl, VT: ShAmtVT));
5038 Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT, N1: Res, N2: ShAmtRem);
5039 }
5040
5041 // Finally, split the computed value.
5042 SplitInteger(Op: Res, Lo, Hi);
5043}
5044
5045void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
5046 SDValue &Lo, SDValue &Hi) {
5047 EVT VT = N->getValueType(ResNo: 0);
5048 unsigned Opc = N->getOpcode();
5049 SDLoc dl(N);
5050
5051 // If we can emit an efficient shift operation, do so now. Check to see if
5052 // the RHS is a constant.
5053 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1)))
5054 return ExpandShiftByConstant(N, Amt: CN->getAPIntValue(), Lo, Hi);
5055
5056 // If we can determine that the high bit of the shift is zero or one, even if
5057 // the low bits are variable, emit this shift in an optimized form.
5058 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
5059 return;
5060
5061 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
5062 unsigned PartsOpc;
5063 if (Opc == ISD::SHL) {
5064 PartsOpc = ISD::SHL_PARTS;
5065 } else if (Opc == ISD::SRL) {
5066 PartsOpc = ISD::SRL_PARTS;
5067 } else {
5068 assert(Opc == ISD::SRA && "Unknown shift!");
5069 PartsOpc = ISD::SRA_PARTS;
5070 }
5071
5072 // Next check to see if the target supports this SHL_PARTS operation or if it
5073 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
5074 // size, but create a libcall instead.
5075 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5076 TargetLowering::LegalizeAction Action = TLI.getOperationAction(Op: PartsOpc, VT: NVT);
5077 const bool LegalOrCustom =
5078 (Action == TargetLowering::Legal && TLI.isTypeLegal(VT: NVT)) ||
5079 Action == TargetLowering::Custom;
5080
5081 unsigned ExpansionFactor = 1;
5082 // That VT->NVT expansion is one step. But will we re-expand NVT?
5083 for (EVT TmpVT = NVT;;) {
5084 EVT NewTMPVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: TmpVT);
5085 if (NewTMPVT == TmpVT)
5086 break;
5087 TmpVT = NewTMPVT;
5088 ++ExpansionFactor;
5089 }
5090
5091 TargetLowering::ShiftLegalizationStrategy S =
5092 TLI.preferredShiftLegalizationStrategy(DAG, N, ExpansionFactor);
5093
5094 if (S == TargetLowering::ShiftLegalizationStrategy::ExpandThroughStack)
5095 return ExpandIntRes_ShiftThroughStack(N, Lo, Hi);
5096
5097 if (LegalOrCustom &&
5098 S != TargetLowering::ShiftLegalizationStrategy::LowerToLibcall) {
5099 // Expand the subcomponents.
5100 SDValue LHSL, LHSH;
5101 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
5102 EVT VT = LHSL.getValueType();
5103
5104 // If the shift amount operand is coming from a vector legalization it may
5105 // have an illegal type. Fix that first by casting the operand, otherwise
5106 // the new SHL_PARTS operation would need further legalization.
5107 SDValue ShiftOp = N->getOperand(Num: 1);
5108 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
5109 if (ShiftOp.getValueType() != ShiftTy)
5110 ShiftOp = DAG.getZExtOrTrunc(Op: ShiftOp, DL: dl, VT: ShiftTy);
5111
5112 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
5113 Lo = DAG.getNode(Opcode: PartsOpc, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5114 Hi = Lo.getValue(R: 1);
5115 return;
5116 }
5117
5118 // Otherwise, emit a libcall.
5119 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5120 bool isSigned;
5121 if (Opc == ISD::SHL) {
5122 isSigned = false; /*sign irrelevant*/
5123 LC = RTLIB::getSHL(VT);
5124 } else if (Opc == ISD::SRL) {
5125 isSigned = false;
5126 LC = RTLIB::getSRL(VT);
5127 } else {
5128 assert(Opc == ISD::SRA && "Unknown shift!");
5129 isSigned = true;
5130 LC = RTLIB::getSRA(VT);
5131 }
5132
5133 if (RTLIB::LibcallImpl LibcallImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
5134 EVT ShAmtTy =
5135 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
5136 SDValue ShAmt = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl, VT: ShAmtTy);
5137 SDValue Ops[2] = {N->getOperand(Num: 0), ShAmt};
5138 TargetLowering::MakeLibCallOptions CallOptions;
5139 CallOptions.setIsSigned(isSigned);
5140 SplitInteger(
5141 Op: TLI.makeLibCall(DAG, LibcallImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
5142 Hi);
5143 return;
5144 }
5145
5146 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
5147 llvm_unreachable("Unsupported shift!");
5148}
5149
5150void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
5151 SDValue &Lo, SDValue &Hi) {
5152 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5153 SDLoc dl(N);
5154 SDValue Op = N->getOperand(Num: 0);
5155 if (Op.getValueType().bitsLE(VT: NVT)) {
5156 // The low part is sign extension of the input (degenerates to a copy).
5157 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5158 // The high part is obtained by SRA'ing all but one of the bits of low part.
5159 unsigned LoSize = NVT.getSizeInBits();
5160 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
5161 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
5162 } else {
5163 // For example, extension of an i48 to an i64. The operand type necessarily
5164 // promotes to the result type, so will end up being expanded too.
5165 assert(getTypeAction(Op.getValueType()) ==
5166 TargetLowering::TypePromoteInteger &&
5167 "Only know how to promote this result!");
5168 SDValue Res = GetPromotedInteger(Op);
5169 assert(Res.getValueType() == N->getValueType(0) &&
5170 "Operand over promoted?");
5171 // Split the promoted operand. This will simplify when it is expanded.
5172 SplitInteger(Op: Res, Lo, Hi);
5173 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5174 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5175 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5176 BitWidth: ExcessBits)));
5177 }
5178}
5179
5180void DAGTypeLegalizer::
5181ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
5182 SDLoc dl(N);
5183 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5184 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
5185
5186 if (EVT.bitsLE(VT: Lo.getValueType())) {
5187 // sext_inreg the low part if needed.
5188 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Lo.getValueType(), N1: Lo,
5189 N2: N->getOperand(Num: 1));
5190
5191 // The high part gets the sign extension from the lo-part. This handles
5192 // things like sextinreg V:i64 from i8.
5193 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: Hi.getValueType(), N1: Lo,
5194 N2: DAG.getShiftAmountConstant(Val: Hi.getValueSizeInBits() - 1,
5195 VT: Hi.getValueType(), DL: dl));
5196 } else {
5197 // For example, extension of an i48 to an i64. Leave the low part alone,
5198 // sext_inreg the high part.
5199 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
5200 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5201 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5202 BitWidth: ExcessBits)));
5203 }
5204}
5205
5206void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
5207 SDValue &Lo, SDValue &Hi) {
5208 EVT VT = N->getValueType(ResNo: 0);
5209 SDLoc dl(N);
5210 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5211
5212 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5213 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5214 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5215 return;
5216 }
5217
5218 RTLIB::Libcall LC = RTLIB::getSREM(VT);
5219 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
5220
5221 TargetLowering::MakeLibCallOptions CallOptions;
5222 CallOptions.setIsSigned(true);
5223 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5224}
5225
5226void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
5227 SDValue &Lo, SDValue &Hi) {
5228 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5229 SDValue InOp = N->getOperand(Num: 0);
5230 EVT InVT = InOp.getValueType();
5231 SDLoc dl(N);
5232 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: InOp);
5233 Hi = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: InVT, N1: InOp,
5234 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits(), VT: InVT, DL: dl));
5235 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Hi);
5236}
5237
5238void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
5239 SDValue &Lo, SDValue &Hi) {
5240 EVT VT = N->getValueType(ResNo: 0);
5241 SDLoc dl(N);
5242
5243 if (N->getOpcode() == ISD::UMULO) {
5244 // This section expands the operation into the following sequence of
5245 // instructions. `iNh` here refers to a type which has half the bit width of
5246 // the type the original operation operated on.
5247 //
5248 // %0 = %LHS.HI != 0 && %RHS.HI != 0
5249 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
5250 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
5251 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
5252 // %4 = add iNh %1.0, %2.0 as iN
5253 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
5254 //
5255 // %lo = %3.LO
5256 // %hi = %5.0
5257 // %ovf = %0 || %1.1 || %2.1 || %5.1
5258 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
5259 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
5260 GetExpandedInteger(Op: LHS, Lo&: LHSLow, Hi&: LHSHigh);
5261 GetExpandedInteger(Op: RHS, Lo&: RHSLow, Hi&: RHSHigh);
5262 EVT HalfVT = LHSLow.getValueType();
5263 EVT BitVT = N->getValueType(ResNo: 1);
5264 SDVTList VTHalfWithO = DAG.getVTList(VT1: HalfVT, VT2: BitVT);
5265
5266 SDValue HalfZero = DAG.getConstant(Val: 0, DL: dl, VT: HalfVT);
5267 SDValue Overflow = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BitVT,
5268 N1: DAG.getSetCC(DL: dl, VT: BitVT, LHS: LHSHigh, RHS: HalfZero, Cond: ISD::SETNE),
5269 N2: DAG.getSetCC(DL: dl, VT: BitVT, LHS: RHSHigh, RHS: HalfZero, Cond: ISD::SETNE));
5270
5271 SDValue One = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: LHSHigh, N2: RHSLow);
5272 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: One.getValue(R: 1));
5273
5274 SDValue Two = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: RHSHigh, N2: LHSLow);
5275 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Two.getValue(R: 1));
5276
5277 SDValue HighSum = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: HalfVT, N1: One, N2: Two);
5278
5279 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
5280 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
5281 // operation recursively legalized?).
5282 //
5283 // Many backends understand this pattern and will convert into LOHI
5284 // themselves, if applicable.
5285 SDValue Three = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT,
5286 N1: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: LHSLow),
5287 N2: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: RHSLow));
5288 SplitInteger(Op: Three, Lo, Hi);
5289
5290 Hi = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList: VTHalfWithO, N1: Hi, N2: HighSum);
5291 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Hi.getValue(R: 1));
5292 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5293 return;
5294 }
5295
5296 Type *RetTy = VT.getTypeForEVT(Context&: *DAG.getContext());
5297 EVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
5298 Type *PtrTy = PtrVT.getTypeForEVT(Context&: *DAG.getContext());
5299
5300 // Replace this with a libcall that will check overflow.
5301 RTLIB::Libcall LC = RTLIB::getMULO(VT);
5302 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
5303
5304 // If we don't have the libcall or if the function we are compiling is the
5305 // implementation of the expected libcall (avoid inf-loop), expand inline.
5306 if (LCImpl == RTLIB::Unsupported ||
5307 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LCImpl) ==
5308 DAG.getMachineFunction().getName()) {
5309 // FIXME: This is not an optimal expansion, but better than crashing.
5310 SDValue MulLo, MulHi;
5311 TLI.forceExpandWideMUL(DAG, dl, /*Signed=*/true, LHS: N->getOperand(Num: 0),
5312 RHS: N->getOperand(Num: 1), Lo&: MulLo, Hi&: MulHi);
5313 SDValue SRA = DAG.getNode(
5314 Opcode: ISD::SRA, DL: dl, VT, N1: MulLo,
5315 N2: DAG.getShiftAmountConstant(Val: VT.getScalarSizeInBits() - 1, VT, DL: dl));
5316 SDValue Overflow =
5317 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: MulHi, RHS: SRA, Cond: ISD::SETNE);
5318 SplitInteger(Op: MulLo, Lo, Hi);
5319 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5320 return;
5321 }
5322
5323 SDValue Temp = DAG.CreateStackTemporary(VT: PtrVT);
5324 // Temporary for the overflow value, default it to zero.
5325 SDValue Chain =
5326 DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT), Ptr: Temp,
5327 PtrInfo: MachinePointerInfo());
5328
5329 TargetLowering::ArgListTy Args;
5330 for (const SDValue &Op : N->op_values()) {
5331 EVT ArgVT = Op.getValueType();
5332 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
5333 TargetLowering::ArgListEntry Entry(Op, ArgTy);
5334 Entry.IsSExt = true;
5335 Entry.IsZExt = false;
5336 Args.push_back(x: Entry);
5337 }
5338
5339 // Also pass the address of the overflow check.
5340 TargetLowering::ArgListEntry Entry(
5341 Temp, PointerType::getUnqual(C&: PtrTy->getContext()));
5342 Entry.IsSExt = true;
5343 Entry.IsZExt = false;
5344 Args.push_back(x: Entry);
5345
5346 SDValue Func = DAG.getExternalSymbol(LCImpl, VT: PtrVT);
5347
5348 TargetLowering::CallLoweringInfo CLI(DAG);
5349 CLI.setDebugLoc(dl)
5350 .setChain(Chain)
5351 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
5352 Target: Func, ArgsList: std::move(Args))
5353 .setSExtResult();
5354
5355 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
5356
5357 SplitInteger(Op: CallInfo.first, Lo, Hi);
5358 SDValue Temp2 =
5359 DAG.getLoad(VT: PtrVT, dl, Chain: CallInfo.second, Ptr: Temp, PtrInfo: MachinePointerInfo());
5360 SDValue Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Temp2,
5361 RHS: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT),
5362 Cond: ISD::SETNE);
5363 // Use the overflow from the libcall everywhere.
5364 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
5365}
5366
5367void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
5368 SDValue &Lo, SDValue &Hi) {
5369 EVT VT = N->getValueType(ResNo: 0);
5370 SDLoc dl(N);
5371 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5372
5373 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5374 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5375 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5376 return;
5377 }
5378
5379 // Try to expand UDIV by constant.
5380 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5381 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5382 // Only if the new type is legal.
5383 if (isTypeLegal(VT: NVT)) {
5384 SDValue InL, InH;
5385 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5386 SmallVector<SDValue> Result;
5387 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5388 Lo = Result[0];
5389 Hi = Result[1];
5390 return;
5391 }
5392 }
5393 }
5394
5395 RTLIB::Libcall LC = RTLIB::getUDIV(VT);
5396 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
5397
5398 TargetLowering::MakeLibCallOptions CallOptions;
5399 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5400}
5401
5402void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
5403 SDValue &Lo, SDValue &Hi) {
5404 EVT VT = N->getValueType(ResNo: 0);
5405 SDLoc dl(N);
5406 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5407
5408 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5409 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5410 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5411 return;
5412 }
5413
5414 // Try to expand UREM by constant.
5415 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5416 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5417 // Only if the new type is legal.
5418 if (isTypeLegal(VT: NVT)) {
5419 SDValue InL, InH;
5420 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5421 SmallVector<SDValue> Result;
5422 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5423 Lo = Result[0];
5424 Hi = Result[1];
5425 return;
5426 }
5427 }
5428 }
5429
5430 RTLIB::Libcall LC = RTLIB::getUREM(VT);
5431 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
5432
5433 TargetLowering::MakeLibCallOptions CallOptions;
5434 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5435}
5436
5437void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
5438 SDValue &Lo, SDValue &Hi) {
5439 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5440 SDLoc dl(N);
5441 SDValue Op = N->getOperand(Num: 0);
5442 if (Op.getValueType().bitsLE(VT: NVT)) {
5443 // The low part is zero extension of the input (degenerates to a copy).
5444 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5445 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // The high part is just a zero.
5446 } else {
5447 // For example, extension of an i48 to an i64. The operand type necessarily
5448 // promotes to the result type, so will end up being expanded too.
5449 assert(getTypeAction(Op.getValueType()) ==
5450 TargetLowering::TypePromoteInteger &&
5451 "Only know how to promote this result!");
5452 SDValue Res = GetPromotedInteger(Op);
5453 assert(Res.getValueType() == N->getValueType(0) &&
5454 "Operand over promoted?");
5455 // Split the promoted operand. This will simplify when it is expanded.
5456 SplitInteger(Op: Res, Lo, Hi);
5457 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5458 Hi = DAG.getZeroExtendInReg(Op: Hi, DL: dl,
5459 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
5460 BitWidth: ExcessBits));
5461 }
5462}
5463
5464void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
5465 SDValue &Lo, SDValue &Hi) {
5466 SDLoc dl(N);
5467 EVT VT = cast<AtomicSDNode>(Val: N)->getMemoryVT();
5468 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::i1, VT3: MVT::Other);
5469 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
5470 SDValue Swap = DAG.getAtomicCmpSwap(
5471 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
5472 MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(), VTs, Chain: N->getOperand(Num: 0),
5473 Ptr: N->getOperand(Num: 1), Cmp: Zero, Swp: Zero, MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5474
5475 ReplaceValueWith(From: SDValue(N, 0), To: Swap.getValue(R: 0));
5476 ReplaceValueWith(From: SDValue(N, 1), To: Swap.getValue(R: 2));
5477}
5478
5479void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
5480 SDValue &Lo, SDValue &Hi) {
5481 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
5482 // both halves independently.
5483 SDValue Res = TLI.expandVecReduce(Node: N, DAG);
5484 SplitInteger(Op: Res, Lo, Hi);
5485}
5486
5487void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
5488 SDValue &Lo, SDValue &Hi) {
5489 // Delegate to funnel-shift expansion.
5490 SDLoc DL(N);
5491 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR;
5492 SDValue Res = DAG.getNode(Opcode, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
5493 N2: N->getOperand(Num: 0), N3: N->getOperand(Num: 1));
5494 SplitInteger(Op: Res, Lo, Hi);
5495}
5496
5497void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
5498 SDValue &Hi) {
5499 // Values numbered from least significant to most significant.
5500 SDValue In1, In2, In3, In4;
5501 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: In3, Hi&: In4);
5502 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: In1, Hi&: In2);
5503 EVT HalfVT = In1.getValueType();
5504
5505 SDLoc DL(N);
5506 unsigned Opc = N->getOpcode();
5507 SDValue ShAmt = N->getOperand(Num: 2);
5508 EVT ShAmtVT = ShAmt.getValueType();
5509 EVT ShAmtCCVT = getSetCCResultType(VT: ShAmtVT);
5510
5511 // If the shift amount is at least half the bitwidth, swap the inputs.
5512 unsigned HalfVTBits = HalfVT.getScalarSizeInBits();
5513 SDValue AndNode = DAG.getNode(Opcode: ISD::AND, DL, VT: ShAmtVT, N1: ShAmt,
5514 N2: DAG.getConstant(Val: HalfVTBits, DL, VT: ShAmtVT));
5515 SDValue Cond =
5516 DAG.getSetCC(DL, VT: ShAmtCCVT, LHS: AndNode, RHS: DAG.getConstant(Val: 0, DL, VT: ShAmtVT),
5517 Cond: Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ);
5518
5519 // Expand to a pair of funnel shifts.
5520 EVT NewShAmtVT = TLI.getShiftAmountTy(LHSTy: HalfVT, DL: DAG.getDataLayout());
5521 SDValue NewShAmt = DAG.getAnyExtOrTrunc(Op: ShAmt, DL, VT: NewShAmtVT);
5522
5523 SDValue Select1 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In1, N3: In2);
5524 SDValue Select2 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In2, N3: In3);
5525 SDValue Select3 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In3, N3: In4);
5526 Lo = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select2, N2: Select1, N3: NewShAmt);
5527 Hi = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select3, N2: Select2, N3: NewShAmt);
5528}
5529
5530void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo, SDValue &Hi) {
5531 if (N->getOpcode() != ISD::CLMUL) {
5532 SDValue Res = TLI.expandCLMUL(N, DAG);
5533 return SplitInteger(Op: Res, Lo, Hi);
5534 }
5535
5536 SDValue LL, LH, RL, RH;
5537 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
5538 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
5539 EVT HalfVT = LL.getValueType();
5540 SDLoc DL(N);
5541
5542 // The low bits are a direct CLMUL of the the low bits.
5543 Lo = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RL);
5544
5545 // We compute two Hi-Lo cross-products, XOR them, and XOR it with the overflow
5546 // of the CLMUL of the low bits (given by CLMULH of the low bits) to yield the
5547 // final high bits.
5548 SDValue LoH = DAG.getNode(Opcode: ISD::CLMULH, DL, VT: HalfVT, N1: LL, N2: RL);
5549 SDValue HiLoCross1 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RH);
5550 SDValue HiLoCross2 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LH, N2: RL);
5551 SDValue HiLoCross = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: HiLoCross1, N2: HiLoCross2);
5552 Hi = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: LoH, N2: HiLoCross);
5553}
5554
5555void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
5556 SDValue &Hi) {
5557 EVT VT = N->getValueType(ResNo: 0);
5558 EVT HalfVT =
5559 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: N->getValueSizeInBits(ResNo: 0) / 2);
5560 SDLoc dl(N);
5561
5562 // We assume VSCALE(1) fits into a legal integer.
5563 APInt One(HalfVT.getSizeInBits(), 1);
5564 SDValue VScaleBase = DAG.getVScale(DL: dl, VT: HalfVT, MulImm: One);
5565 VScaleBase = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: VScaleBase);
5566 SDValue Res = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: VScaleBase, N2: N->getOperand(Num: 0));
5567 SplitInteger(Op: Res, Lo, Hi);
5568}
5569
5570void DAGTypeLegalizer::ExpandIntRes_READ_REGISTER(SDNode *N, SDValue &Lo,
5571 SDValue &Hi) {
5572 const Function &Fn = DAG.getMachineFunction().getFunction();
5573 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
5574 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
5575 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
5576 EVT LoVT, HiVT;
5577 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: N->getValueType(ResNo: 0));
5578 Lo = DAG.getPOISON(VT: LoVT);
5579 Hi = DAG.getPOISON(VT: HiVT);
5580}
5581
5582void DAGTypeLegalizer::ExpandIntRes_CTTZ_ELTS(SDNode *N, SDValue &Lo,
5583 SDValue &Hi) {
5584 // Assume that the maximum number of vector elements fits in getVectorIdxTy
5585 // and expand to that.
5586 EVT VT = N->getSimpleValueType(ResNo: 0);
5587 EVT IdxVT = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
5588 assert(IdxVT.bitsLT(VT) &&
5589 "VectorIdxTy should be smaller than type to be expanded?");
5590
5591 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: IdxVT, Operand: N->getOperand(Num: 0));
5592 Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: SDLoc(N), VT, Operand: Res);
5593 SplitInteger(Op: Res, Lo, Hi);
5594}
5595
5596//===----------------------------------------------------------------------===//
5597// Integer Operand Expansion
5598//===----------------------------------------------------------------------===//
5599
5600/// ExpandIntegerOperand - This method is called when the specified operand of
5601/// the specified node is found to need expansion. At this point, all of the
5602/// result types of the node are known to be legal, but other operands of the
5603/// node may need promotion or expansion as well as the specified one.
5604bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
5605 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG));
5606 SDValue Res = SDValue();
5607
5608 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false))
5609 return false;
5610
5611 switch (N->getOpcode()) {
5612 default:
5613 #ifndef NDEBUG
5614 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
5615 N->dump(&DAG); dbgs() << "\n";
5616 #endif
5617 report_fatal_error(reason: "Do not know how to expand this operator's operand!");
5618
5619 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
5620 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
5621 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
5622 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
5623 case ISD::FAKE_USE:
5624 Res = ExpandOp_FAKE_USE(N);
5625 break;
5626 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
5627 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
5628 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
5629 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
5630 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
5631 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
5632 case ISD::STRICT_SINT_TO_FP:
5633 case ISD::SINT_TO_FP:
5634 case ISD::STRICT_UINT_TO_FP:
5635 case ISD::UINT_TO_FP: Res = ExpandIntOp_XINT_TO_FP(N); break;
5636 case ISD::STORE: Res = ExpandIntOp_STORE(N: cast<StoreSDNode>(Val: N), OpNo); break;
5637 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
5638
5639 case ISD::SHL:
5640 case ISD::SRA:
5641 case ISD::SRL:
5642 case ISD::ROTL:
5643 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
5644 case ISD::RETURNADDR:
5645 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
5646
5647 case ISD::SCMP:
5648 case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
5649
5650 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
5651 case ISD::STACKMAP:
5652 Res = ExpandIntOp_STACKMAP(N, OpNo);
5653 break;
5654 case ISD::PATCHPOINT:
5655 Res = ExpandIntOp_PATCHPOINT(N, OpNo);
5656 break;
5657 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
5658 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
5659 Res = ExpandIntOp_VP_STRIDED(N, OpNo);
5660 break;
5661 case ISD::WRITE_REGISTER:
5662 Res = ExpandIntOp_WRITE_REGISTER(N, OpNo);
5663 break;
5664 }
5665
5666 // If the result is null, the sub-method took care of registering results etc.
5667 if (!Res.getNode()) return false;
5668
5669 // If the result is N, the sub-method updated N in place. Tell the legalizer
5670 // core about this.
5671 if (Res.getNode() == N)
5672 return true;
5673
5674 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
5675 "Invalid operand expansion");
5676
5677 ReplaceValueWith(From: SDValue(N, 0), To: Res);
5678 return false;
5679}
5680
5681/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
5682/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
5683void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
5684 SDValue &NewRHS,
5685 ISD::CondCode &CCCode,
5686 const SDLoc &dl) {
5687 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5688 GetExpandedInteger(Op: NewLHS, Lo&: LHSLo, Hi&: LHSHi);
5689 GetExpandedInteger(Op: NewRHS, Lo&: RHSLo, Hi&: RHSHi);
5690
5691 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
5692 if (RHSLo == RHSHi && isAllOnesConstant(V: RHSLo)) {
5693 // Equality comparison to -1.
5694 NewLHS = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: LHSHi);
5695 NewRHS = RHSLo;
5696 return;
5697 }
5698
5699 NewLHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: RHSLo);
5700 NewRHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSHi, N2: RHSHi);
5701 NewLHS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NewLHS.getValueType(), N1: NewLHS, N2: NewRHS);
5702 NewRHS = DAG.getConstant(Val: 0, DL: dl, VT: NewLHS.getValueType());
5703 return;
5704 }
5705
5706 // If this is a comparison of the sign bit, just look at the top part.
5707 // X > -1, x < 0
5708 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Val&: NewRHS))
5709 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0
5710 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1
5711 NewLHS = LHSHi;
5712 NewRHS = RHSHi;
5713 return;
5714 }
5715
5716 // FIXME: This generated code sucks.
5717 ISD::CondCode LowCC;
5718 switch (CCCode) {
5719 default: llvm_unreachable("Unknown integer setcc!");
5720 case ISD::SETLT:
5721 case ISD::SETULT: LowCC = ISD::SETULT; break;
5722 case ISD::SETGT:
5723 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5724 case ISD::SETLE:
5725 case ISD::SETULE: LowCC = ISD::SETULE; break;
5726 case ISD::SETGE:
5727 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5728 }
5729
5730 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
5731 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
5732 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
5733
5734 // NOTE: on targets without efficient SELECT of bools, we can always use
5735 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5736 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
5737 nullptr);
5738 SDValue LoCmp, HiCmp;
5739 if (TLI.isTypeLegal(VT: LHSLo.getValueType()) &&
5740 TLI.isTypeLegal(VT: RHSLo.getValueType()))
5741 LoCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSLo.getValueType()), N0: LHSLo,
5742 N1: RHSLo, Cond: LowCC, foldBooleans: false, DCI&: DagCombineInfo, dl);
5743 if (!LoCmp.getNode())
5744 LoCmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LHSLo.getValueType()), LHS: LHSLo,
5745 RHS: RHSLo, Cond: LowCC);
5746 if (TLI.isTypeLegal(VT: LHSHi.getValueType()) &&
5747 TLI.isTypeLegal(VT: RHSHi.getValueType()))
5748 HiCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSHi.getValueType()), N0: LHSHi,
5749 N1: RHSHi, Cond: CCCode, foldBooleans: false, DCI&: DagCombineInfo, dl);
5750 if (!HiCmp.getNode())
5751 HiCmp =
5752 DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: getSetCCResultType(VT: LHSHi.getValueType()),
5753 N1: LHSHi, N2: RHSHi, N3: DAG.getCondCode(Cond: CCCode));
5754
5755 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(Val: LoCmp.getNode());
5756 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(Val: HiCmp.getNode());
5757
5758 bool EqAllowed = ISD::isTrueWhenEqual(Cond: CCCode);
5759
5760 // FIXME: Is the HiCmpC->isOne() here correct for
5761 // ZeroOrNegativeOneBooleanContent.
5762 if ((EqAllowed && (HiCmpC && HiCmpC->isZero())) ||
5763 (!EqAllowed &&
5764 ((HiCmpC && HiCmpC->isOne()) || (LoCmpC && LoCmpC->isZero())))) {
5765 // For LE / GE, if high part is known false, ignore the low part.
5766 // For LT / GT: if low part is known false, return the high part.
5767 // if high part is known true, ignore the low part.
5768 NewLHS = HiCmp;
5769 NewRHS = SDValue();
5770 return;
5771 }
5772
5773 if (LHSHi == RHSHi) {
5774 // Comparing the low bits is enough.
5775 NewLHS = LoCmp;
5776 NewRHS = SDValue();
5777 return;
5778 }
5779
5780 // Lower with SETCCCARRY if the target supports it.
5781 EVT HiVT = LHSHi.getValueType();
5782 EVT ExpandVT = TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: HiVT);
5783 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(Op: ISD::SETCCCARRY, VT: ExpandVT);
5784
5785 // FIXME: Make all targets support this, then remove the other lowering.
5786 if (HasSETCCCARRY) {
5787 // SETCCCARRY can detect < and >= directly. For > and <=, flip
5788 // operands and condition code.
5789 bool FlipOperands = false;
5790 switch (CCCode) {
5791 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
5792 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
5793 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
5794 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
5795 default: break;
5796 }
5797 if (FlipOperands) {
5798 std::swap(a&: LHSLo, b&: RHSLo);
5799 std::swap(a&: LHSHi, b&: RHSHi);
5800 }
5801 // Perform a wide subtraction, feeding the carry from the low part into
5802 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
5803 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
5804 // zero or positive iff LHS >= RHS.
5805 EVT LoVT = LHSLo.getValueType();
5806 SDVTList VTList = DAG.getVTList(VT1: LoVT, VT2: getSetCCResultType(VT: LoVT));
5807 SDValue LowCmp = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: LHSLo, N2: RHSLo);
5808 SDValue Res = DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: getSetCCResultType(VT: HiVT),
5809 N1: LHSHi, N2: RHSHi, N3: LowCmp.getValue(R: 1),
5810 N4: DAG.getCondCode(Cond: CCCode));
5811 NewLHS = Res;
5812 NewRHS = SDValue();
5813 return;
5814 }
5815
5816 NewLHS = TLI.SimplifySetCC(VT: getSetCCResultType(VT: HiVT), N0: LHSHi, N1: RHSHi, Cond: ISD::SETEQ,
5817 foldBooleans: false, DCI&: DagCombineInfo, dl);
5818 if (!NewLHS.getNode())
5819 NewLHS =
5820 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: HiVT), LHS: LHSHi, RHS: RHSHi, Cond: ISD::SETEQ);
5821 NewLHS = DAG.getSelect(DL: dl, VT: LoCmp.getValueType(), Cond: NewLHS, LHS: LoCmp, RHS: HiCmp);
5822 NewRHS = SDValue();
5823}
5824
5825SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
5826 SDValue NewLHS = N->getOperand(Num: 2), NewRHS = N->getOperand(Num: 3);
5827 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get();
5828 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5829
5830 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5831 // against zero to select between true and false values.
5832 if (!NewRHS.getNode()) {
5833 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5834 CCCode = ISD::SETNE;
5835 }
5836
5837 // Update N to have the operands specified.
5838 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
5839 Op2: DAG.getCondCode(Cond: CCCode), Op3: NewLHS, Op4: NewRHS,
5840 Op5: N->getOperand(Num: 4)), 0);
5841}
5842
5843SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
5844 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5845 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
5846 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5847
5848 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5849 // against zero to select between true and false values.
5850 if (!NewRHS.getNode()) {
5851 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5852 CCCode = ISD::SETNE;
5853 }
5854
5855 // Update N to have the operands specified.
5856 return SDValue(DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS,
5857 Op3: N->getOperand(Num: 2), Op4: N->getOperand(Num: 3),
5858 Op5: DAG.getCondCode(Cond: CCCode)), 0);
5859}
5860
5861SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
5862 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5863 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
5864 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5865
5866 // If ExpandSetCCOperands returned a scalar, use it.
5867 if (!NewRHS.getNode()) {
5868 assert(NewLHS.getValueType() == N->getValueType(0) &&
5869 "Unexpected setcc expansion!");
5870 return NewLHS;
5871 }
5872
5873 // Otherwise, update N to have the operands specified.
5874 return SDValue(
5875 DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS, Op3: DAG.getCondCode(Cond: CCCode)), 0);
5876}
5877
5878SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
5879 SDValue LHS = N->getOperand(Num: 0);
5880 SDValue RHS = N->getOperand(Num: 1);
5881 SDValue Carry = N->getOperand(Num: 2);
5882 SDValue Cond = N->getOperand(Num: 3);
5883 SDLoc dl = SDLoc(N);
5884
5885 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5886 GetExpandedInteger(Op: LHS, Lo&: LHSLo, Hi&: LHSHi);
5887 GetExpandedInteger(Op: RHS, Lo&: RHSLo, Hi&: RHSHi);
5888
5889 // Expand to a USUBO_CARRY for the low part and a SETCCCARRY for the high.
5890 SDVTList VTList = DAG.getVTList(VT1: LHSLo.getValueType(), VT2: Carry.getValueType());
5891 SDValue LowCmp =
5892 DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: LHSLo, N2: RHSLo, N3: Carry);
5893 return DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: N->getValueType(ResNo: 0), N1: LHSHi, N2: RHSHi,
5894 N3: LowCmp.getValue(R: 1), N4: Cond);
5895}
5896
5897SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
5898 // Split the operand and replace with SPLAT_VECTOR_PARTS.
5899 SDValue Lo, Hi;
5900 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5901 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Lo,
5902 N2: Hi);
5903}
5904
5905SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
5906 // The value being shifted is legal, but the shift amount is too big.
5907 // It follows that either the result of the shift is undefined, or the
5908 // upper half of the shift amount is zero. Just use the lower half.
5909 SDValue Lo, Hi;
5910 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo, Hi);
5911 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Lo), 0);
5912}
5913
5914SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
5915 return TLI.expandCMP(Node: N, DAG);
5916}
5917
5918SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
5919 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
5920 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
5921 // constant to valid type.
5922 SDValue Lo, Hi;
5923 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5924 return SDValue(DAG.UpdateNodeOperands(N, Op: Lo), 0);
5925}
5926
5927SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) {
5928 bool IsStrict = N->isStrictFPOpcode();
5929 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
5930 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
5931 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
5932 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
5933 EVT DstVT = N->getValueType(ResNo: 0);
5934 RTLIB::Libcall LC = IsSigned ? RTLIB::getSINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT)
5935 : RTLIB::getUINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT);
5936 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
5937 "Don't know how to expand this XINT_TO_FP!");
5938 TargetLowering::MakeLibCallOptions CallOptions;
5939 CallOptions.setIsSigned(true);
5940 std::pair<SDValue, SDValue> Tmp =
5941 TLI.makeLibCall(DAG, LC, RetVT: DstVT, Ops: Op, CallOptions, dl: SDLoc(N), Chain);
5942
5943 if (!IsStrict)
5944 return Tmp.first;
5945
5946 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
5947 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
5948 return SDValue();
5949}
5950
5951SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
5952 assert(!N->isAtomic() && "Should have been a ATOMIC_STORE?");
5953
5954 if (ISD::isNormalStore(N))
5955 return ExpandOp_NormalStore(N, OpNo);
5956
5957 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
5958 assert(OpNo == 1 && "Can only expand the stored value so far");
5959
5960 EVT VT = N->getOperand(Num: 1).getValueType();
5961 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5962 SDValue Ch = N->getChain();
5963 SDValue Ptr = N->getBasePtr();
5964 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
5965 AAMDNodes AAInfo = N->getAAInfo();
5966 SDLoc dl(N);
5967 SDValue Lo, Hi;
5968
5969 assert(NVT.isByteSized() && "Expanded type not byte sized!");
5970
5971 if (N->getMemoryVT().bitsLE(VT: NVT)) {
5972 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
5973 return DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(),
5974 SVT: N->getMemoryVT(), Alignment: N->getBaseAlign(), MMOFlags,
5975 AAInfo);
5976 }
5977
5978 if (DAG.getDataLayout().isLittleEndian()) {
5979 // Little-endian - low bits are at low addresses.
5980 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
5981
5982 Lo = DAG.getStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
5983 MMOFlags, AAInfo);
5984
5985 unsigned ExcessBits =
5986 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
5987 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
5988
5989 // Increment the pointer to the other half.
5990 unsigned IncrementSize = NVT.getSizeInBits()/8;
5991 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
5992 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr,
5993 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
5994 SVT: NEVT, Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
5995 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
5996 }
5997
5998 // Big-endian - high bits are at low addresses. Favor aligned stores at
5999 // the cost of some bit-fiddling.
6000 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6001
6002 EVT ExtVT = N->getMemoryVT();
6003 unsigned EBytes = ExtVT.getStoreSize();
6004 unsigned IncrementSize = NVT.getSizeInBits()/8;
6005 unsigned ExcessBits = (EBytes - IncrementSize)*8;
6006 EVT HiVT = EVT::getIntegerVT(Context&: *DAG.getContext(),
6007 BitWidth: ExtVT.getSizeInBits() - ExcessBits);
6008
6009 if (ExcessBits < NVT.getSizeInBits()) {
6010 // Transfer high bits from the top of Lo to the bottom of Hi.
6011 Hi = DAG.getNode(
6012 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
6013 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
6014 Hi = DAG.getNode(
6015 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Hi,
6016 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Lo,
6017 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
6018 }
6019
6020 // Store both the high bits and maybe some of the low bits.
6021 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr, PtrInfo: N->getPointerInfo(), SVT: HiVT,
6022 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
6023
6024 // Increment the pointer to the other half.
6025 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6026 // Store the lowest ExcessBits bits in the second half.
6027 Lo = DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr,
6028 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6029 SVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
6030 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
6031 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6032}
6033
6034SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
6035 SDValue InL, InH;
6036 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
6037 // Just truncate the low part of the source.
6038 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: InL);
6039}
6040
6041SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
6042 SDLoc dl(N);
6043 SDValue Swap =
6044 DAG.getAtomic(Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(),
6045 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 2), Val: N->getOperand(Num: 1),
6046 MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
6047 return Swap.getValue(R: 1);
6048}
6049
6050SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
6051 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
6052 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
6053
6054 SDValue Hi; // The upper half is dropped out.
6055 SmallVector<SDValue, 8> NewOps(N->ops());
6056 GetExpandedInteger(Op: NewOps[OpNo], Lo&: NewOps[OpNo], Hi);
6057
6058 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
6059}
6060
6061SDValue DAGTypeLegalizer::ExpandIntOp_WRITE_REGISTER(SDNode *N, unsigned OpNo) {
6062 const Function &Fn = DAG.getMachineFunction().getFunction();
6063 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6064 "cannot use llvm.write_register with illegal type", Fn,
6065 N->getDebugLoc()));
6066
6067 return N->getOperand(Num: 0);
6068}
6069
6070SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
6071 SDLoc dl(N);
6072
6073 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6074 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6075 EVT OutVT = V0.getValueType();
6076
6077 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: OutVT, N1: V0, N2: V1, N3: N->getOperand(Num: 2));
6078}
6079
6080SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(SDNode *N) {
6081 SDLoc DL(N);
6082 unsigned Factor = N->getNumOperands();
6083
6084 SmallVector<SDValue, 8> Ops(Factor);
6085 for (unsigned i = 0; i != Factor; i++)
6086 Ops[i] = GetPromotedInteger(Op: N->getOperand(Num: i));
6087
6088 SmallVector<EVT, 8> ResVTs(Factor, Ops[0].getValueType());
6089 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VTs: ResVTs), Ops);
6090
6091 for (unsigned i = 0; i != Factor; i++)
6092 SetPromotedInteger(Op: SDValue(N, i), Result: Res.getValue(R: i));
6093
6094 return SDValue();
6095}
6096
6097SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
6098
6099 EVT OutVT = N->getValueType(ResNo: 0);
6100 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6101 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6102 EVT NOutVTElem = NOutVT.getVectorElementType();
6103
6104 SDLoc dl(N);
6105 SDValue BaseIdx = N->getOperand(Num: 1);
6106
6107 // TODO: We may be able to use this for types other than scalable
6108 // vectors and fix those tests that expect BUILD_VECTOR to be used
6109 if (OutVT.isScalableVector()) {
6110 SDValue InOp0 = N->getOperand(Num: 0);
6111 EVT InVT = InOp0.getValueType();
6112
6113 // Try and extract from a smaller type so that it eventually falls
6114 // into the promotion code below.
6115 if (getTypeAction(VT: InVT) == TargetLowering::TypeSplitVector ||
6116 getTypeAction(VT: InVT) == TargetLowering::TypeLegal) {
6117 EVT NInVT = InVT.getHalfNumVectorElementsVT(Context&: *DAG.getContext());
6118 unsigned NElts = NInVT.getVectorMinNumElements();
6119 uint64_t IdxVal = BaseIdx->getAsZExtVal();
6120
6121 SDValue Step1 = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NInVT, N1: InOp0,
6122 N2: DAG.getConstant(Val: alignDown(Value: IdxVal, Align: NElts), DL: dl,
6123 VT: BaseIdx.getValueType()));
6124 SDValue Step2 = DAG.getNode(
6125 Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Step1,
6126 N2: DAG.getConstant(Val: IdxVal % NElts, DL: dl, VT: BaseIdx.getValueType()));
6127 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Step2);
6128 }
6129
6130 // Try and extract from a widened type.
6131 if (getTypeAction(VT: InVT) == TargetLowering::TypeWidenVector) {
6132 SDValue Ops[] = {GetWidenedVector(Op: InOp0), BaseIdx};
6133 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: OutVT, Ops);
6134 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6135 }
6136
6137 // Promote operands and see if this is handled by target lowering,
6138 // Otherwise, use the BUILD_VECTOR approach below
6139 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
6140 // Collect the (promoted) operands
6141 SDValue Ops[] = { GetPromotedInteger(Op: InOp0), BaseIdx };
6142
6143 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
6144 assert(PromEltVT.bitsLE(NOutVTElem) &&
6145 "Promoted operand has an element type greater than result");
6146
6147 EVT ExtVT = NOutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: PromEltVT);
6148 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: ExtVT, Ops);
6149 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6150 }
6151 }
6152
6153 if (OutVT.isScalableVector())
6154 report_fatal_error(reason: "Unable to promote scalable types using BUILD_VECTOR");
6155
6156 SDValue InOp0 = N->getOperand(Num: 0);
6157 if (getTypeAction(VT: InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
6158 InOp0 = GetPromotedInteger(Op: InOp0);
6159
6160 EVT InVT = InOp0.getValueType();
6161 EVT InSVT = InVT.getVectorElementType();
6162
6163 unsigned OutNumElems = OutVT.getVectorNumElements();
6164 SmallVector<SDValue, 8> Ops;
6165 Ops.reserve(N: OutNumElems);
6166 for (unsigned i = 0; i != OutNumElems; ++i) {
6167 // Extract the element from the original vector.
6168 SDValue Index = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: BaseIdx.getValueType(), N1: BaseIdx,
6169 N2: DAG.getConstant(Val: i, DL: dl, VT: BaseIdx.getValueType()));
6170 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: InSVT,
6171 N1: N->getOperand(Num: 0), N2: Index);
6172 SDValue Op = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NOutVTElem);
6173 // Insert the converted element to the new vector.
6174 Ops.push_back(Elt: Op);
6175 }
6176
6177 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6178}
6179
6180SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
6181 EVT OutVT = N->getValueType(ResNo: 0);
6182 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6183 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6184
6185 SDLoc dl(N);
6186 SDValue Vec = N->getOperand(Num: 0);
6187 SDValue SubVec = N->getOperand(Num: 1);
6188 SDValue Idx = N->getOperand(Num: 2);
6189
6190 EVT SubVecVT = SubVec.getValueType();
6191 EVT NSubVT =
6192 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NOutVT.getVectorElementType(),
6193 EC: SubVecVT.getVectorElementCount());
6194
6195 Vec = GetPromotedInteger(Op: Vec);
6196 SubVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NSubVT, Operand: SubVec);
6197
6198 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: NOutVT, N1: Vec, N2: SubVec, N3: Idx);
6199}
6200
6201SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
6202 SDLoc dl(N);
6203
6204 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6205 EVT OutVT = V0.getValueType();
6206
6207 return DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL: dl, VT: OutVT, Operand: V0);
6208}
6209
6210SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
6211 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(Val: N);
6212 EVT VT = N->getValueType(ResNo: 0);
6213 SDLoc dl(N);
6214
6215 ArrayRef<int> NewMask = SV->getMask().slice(N: 0, M: VT.getVectorNumElements());
6216
6217 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6218 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6219 EVT OutVT = V0.getValueType();
6220
6221 return DAG.getVectorShuffle(VT: OutVT, dl, N1: V0, N2: V1, Mask: NewMask);
6222}
6223
6224SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
6225 EVT OutVT = N->getValueType(ResNo: 0);
6226 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6227 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6228 unsigned NumElems = N->getNumOperands();
6229 EVT NOutVTElem = NOutVT.getVectorElementType();
6230 TargetLoweringBase::BooleanContent NOutBoolType = TLI.getBooleanContents(Type: NOutVT);
6231 unsigned NOutExtOpc = TargetLowering::getExtendForContent(Content: NOutBoolType);
6232 SDLoc dl(N);
6233
6234 SmallVector<SDValue, 8> Ops;
6235 Ops.reserve(N: NumElems);
6236 for (unsigned i = 0; i != NumElems; ++i) {
6237 SDValue Op = N->getOperand(Num: i);
6238 EVT OpVT = Op.getValueType();
6239 // BUILD_VECTOR integer operand types are allowed to be larger than the
6240 // result's element type. This may still be true after the promotion. For
6241 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
6242 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
6243 if (OpVT.bitsLT(VT: NOutVTElem)) {
6244 unsigned ExtOpc = ISD::ANY_EXTEND;
6245 // Attempt to extend constant bool vectors to match target's BooleanContent.
6246 // While not necessary, this improves chances of the constant correctly
6247 // folding with compare results (e.g. for NOT patterns).
6248 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant)
6249 ExtOpc = NOutExtOpc;
6250 Op = DAG.getNode(Opcode: ExtOpc, DL: dl, VT: NOutVTElem, Operand: Op);
6251 }
6252 Ops.push_back(Elt: Op);
6253 }
6254
6255 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6256}
6257
6258SDValue DAGTypeLegalizer::PromoteIntRes_ScalarOp(SDNode *N) {
6259
6260 SDLoc dl(N);
6261
6262 assert(!N->getOperand(0).getValueType().isVector() &&
6263 "Input must be a scalar");
6264
6265 EVT OutVT = N->getValueType(ResNo: 0);
6266 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6267 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6268 EVT NOutElemVT = NOutVT.getVectorElementType();
6269
6270 SDValue Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutElemVT, Operand: N->getOperand(Num: 0));
6271 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NOutVT, Operand: Op);
6272}
6273
6274SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
6275 SDLoc dl(N);
6276 EVT OutVT = N->getValueType(ResNo: 0);
6277 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6278 assert(NOutVT.isScalableVector() &&
6279 "Type must be promoted to a scalable vector type");
6280 const APInt &StepVal = N->getConstantOperandAPInt(Num: 0);
6281 return DAG.getStepVector(DL: dl, ResVT: NOutVT,
6282 StepVal: StepVal.sext(width: NOutVT.getScalarSizeInBits()));
6283}
6284
6285SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
6286 SDLoc dl(N);
6287
6288 EVT OutVT = N->getValueType(ResNo: 0);
6289 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6290 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6291
6292 unsigned NumOperands = N->getNumOperands();
6293 unsigned NumOutElem = NOutVT.getVectorMinNumElements();
6294 EVT OutElemTy = NOutVT.getVectorElementType();
6295 if (OutVT.isScalableVector()) {
6296 // Find the largest promoted element type for each of the operands.
6297 SDUse *MaxSizedValue = std::max_element(
6298 first: N->op_begin(), last: N->op_end(), comp: [](const SDValue &A, const SDValue &B) {
6299 EVT AVT = A.getValueType().getVectorElementType();
6300 EVT BVT = B.getValueType().getVectorElementType();
6301 return AVT.getScalarSizeInBits() < BVT.getScalarSizeInBits();
6302 });
6303 EVT MaxElementVT = MaxSizedValue->getValueType().getVectorElementType();
6304
6305 // Then promote all vectors to the largest element type.
6306 SmallVector<SDValue, 8> Ops;
6307 for (unsigned I = 0; I < NumOperands; ++I) {
6308 SDValue Op = N->getOperand(Num: I);
6309 EVT OpVT = Op.getValueType();
6310 if (getTypeAction(VT: OpVT) == TargetLowering::TypePromoteInteger)
6311 Op = GetPromotedInteger(Op);
6312 else
6313 assert(getTypeAction(OpVT) == TargetLowering::TypeLegal &&
6314 "Unhandled legalization type");
6315
6316 if (OpVT.getVectorElementType().getScalarSizeInBits() <
6317 MaxElementVT.getScalarSizeInBits())
6318 Op = DAG.getAnyExtOrTrunc(
6319 Op, DL: dl,
6320 VT: OpVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT));
6321 Ops.push_back(Elt: Op);
6322 }
6323
6324 // Do the CONCAT on the promoted type and finally truncate to (the promoted)
6325 // NOutVT.
6326 return DAG.getAnyExtOrTrunc(
6327 Op: DAG.getNode(
6328 Opcode: ISD::CONCAT_VECTORS, DL: dl,
6329 VT: OutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT),
6330 Ops),
6331 DL: dl, VT: NOutVT);
6332 }
6333
6334 unsigned NumElem = N->getOperand(Num: 0).getValueType().getVectorNumElements();
6335 assert(NumElem * NumOperands == NumOutElem &&
6336 "Unexpected number of elements");
6337
6338 // Take the elements from the first vector.
6339 SmallVector<SDValue, 8> Ops(NumOutElem);
6340 for (unsigned i = 0; i < NumOperands; ++i) {
6341 SDValue Op = N->getOperand(Num: i);
6342 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypePromoteInteger)
6343 Op = GetPromotedInteger(Op);
6344 EVT SclrTy = Op.getValueType().getVectorElementType();
6345 assert(NumElem == Op.getValueType().getVectorNumElements() &&
6346 "Unexpected number of elements");
6347
6348 for (unsigned j = 0; j < NumElem; ++j) {
6349 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Op,
6350 N2: DAG.getVectorIdxConstant(Val: j, DL: dl));
6351 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: OutElemTy);
6352 }
6353 }
6354
6355 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6356}
6357
6358SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
6359 EVT VT = N->getValueType(ResNo: 0);
6360 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6361 assert(NVT.isVector() && "This type must be promoted to a vector type");
6362
6363 SDLoc dl(N);
6364
6365 // For operands whose TypeAction is to promote, extend the promoted node
6366 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
6367 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
6368 // type..
6369 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
6370 == TargetLowering::TypePromoteInteger) {
6371 SDValue Promoted;
6372
6373 switch(N->getOpcode()) {
6374 case ISD::SIGN_EXTEND_VECTOR_INREG:
6375 Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
6376 break;
6377 case ISD::ZERO_EXTEND_VECTOR_INREG:
6378 Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
6379 break;
6380 case ISD::ANY_EXTEND_VECTOR_INREG:
6381 Promoted = GetPromotedInteger(Op: N->getOperand(Num: 0));
6382 break;
6383 default:
6384 llvm_unreachable("Node has unexpected Opcode");
6385 }
6386 unsigned NewSize = NVT.getSizeInBits();
6387 if (Promoted.getValueType().getSizeInBits() > NewSize) {
6388 EVT ExtractVT = EVT::getVectorVT(
6389 Context&: *DAG.getContext(), VT: Promoted.getValueType().getVectorElementType(),
6390 NumElements: NewSize / Promoted.getScalarValueSizeInBits());
6391
6392 Promoted = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: ExtractVT, N1: Promoted,
6393 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
6394 }
6395 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Promoted);
6396 }
6397
6398 // Directly extend to the appropriate transform-to type.
6399 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
6400}
6401
6402SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(SDNode *N) {
6403 EVT VT = N->getValueType(ResNo: 0);
6404 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6405 return DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6406}
6407
6408SDValue DAGTypeLegalizer::PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
6409 EVT VT = N->getValueType(ResNo: 0);
6410 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6411 return DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6412}
6413
6414SDValue DAGTypeLegalizer::PromoteIntRes_PARTIAL_REDUCE_MLA(SDNode *N) {
6415 SDLoc DL(N);
6416 EVT VT = N->getValueType(ResNo: 0);
6417 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6418 SDValue ExtAcc = GetPromotedInteger(Op: N->getOperand(Num: 0));
6419 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: ExtAcc, N2: N->getOperand(Num: 1),
6420 N3: N->getOperand(Num: 2));
6421}
6422
6423SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
6424 EVT OutVT = N->getValueType(ResNo: 0);
6425 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6426 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6427
6428 EVT NOutVTElem = NOutVT.getVectorElementType();
6429
6430 SDLoc dl(N);
6431 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6432
6433 SDValue ConvElem = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6434 VT: NOutVTElem, Operand: N->getOperand(Num: 1));
6435 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NOutVT,
6436 N1: V0, N2: ConvElem, N3: N->getOperand(Num: 2));
6437}
6438
6439SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
6440 // The VECREDUCE result size may be larger than the element size, so
6441 // we can simply change the result type.
6442 SDLoc dl(N);
6443 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6444 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Ops: N->ops());
6445}
6446
6447SDValue DAGTypeLegalizer::PromoteIntRes_VP_REDUCE(SDNode *N) {
6448 // The VP_REDUCE result size may be larger than the element size, so we can
6449 // simply change the result type. However the start value and result must be
6450 // the same.
6451 SDLoc DL(N);
6452 SDValue Start = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
6453 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: Start.getValueType(), N1: Start,
6454 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
6455}
6456
6457SDValue DAGTypeLegalizer::PromoteIntRes_PATCHPOINT(SDNode *N) {
6458 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6459 SDLoc dl(N);
6460
6461 assert(N->getNumValues() == 3 && "Expected 3 values for PATCHPOINT");
6462 SDVTList VTList = DAG.getVTList(VTs: {NVT, MVT::Other, MVT::Glue});
6463
6464 SmallVector<SDValue> Ops(N->ops());
6465 SDValue Res = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList, Ops);
6466
6467 // Replace chain and glue uses with the new patchpoint.
6468 SDValue From[] = {SDValue(N, 1), SDValue(N, 2)};
6469 SDValue To[] = {Res.getValue(R: 1), Res.getValue(R: 2)};
6470 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
6471
6472 return Res.getValue(R: 0);
6473}
6474
6475SDValue DAGTypeLegalizer::PromoteIntRes_READ_REGISTER(SDNode *N) {
6476 const Function &Fn = DAG.getMachineFunction().getFunction();
6477 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6478 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
6479
6480 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6481 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
6482 return DAG.getPOISON(VT: NVT);
6483}
6484
6485SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
6486 SDLoc dl(N);
6487 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6488 SDValue V1 = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl,
6489 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
6490 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl,
6491 VT: V0->getValueType(ResNo: 0).getScalarType(), N1: V0, N2: V1);
6492
6493 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
6494 // element types. If this is the case then we need to expand the outgoing
6495 // value and not truncate it.
6496 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6497}
6498
6499SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_SUBVECTOR(SDNode *N) {
6500 SDLoc dl(N);
6501 // The result type is equal to the first input operand's type, so the
6502 // type that needs promoting must be the second source vector.
6503 SDValue V0 = N->getOperand(Num: 0);
6504 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6505 SDValue Idx = N->getOperand(Num: 2);
6506 EVT PromVT = EVT::getVectorVT(Context&: *DAG.getContext(),
6507 VT: V1.getValueType().getVectorElementType(),
6508 EC: V0.getValueType().getVectorElementCount());
6509 V0 = DAG.getAnyExtOrTrunc(Op: V0, DL: dl, VT: PromVT);
6510 SDValue Ext = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: PromVT, N1: V0, N2: V1, N3: Idx);
6511 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6512}
6513
6514// FIXME: We wouldn't need this if clang could promote short integers
6515// that are arguments to FAKE_USE.
6516SDValue DAGTypeLegalizer::PromoteIntOp_FAKE_USE(SDNode *N) {
6517 SDLoc dl(N);
6518 SDValue V0 = N->getOperand(Num: 0);
6519 SDValue V1 = N->getOperand(Num: 1);
6520 EVT InVT1 = V1.getValueType();
6521 SDValue VPromoted =
6522 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6523 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT1), Operand: V1);
6524 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: N->getValueType(ResNo: 0), N1: V0, N2: VPromoted);
6525}
6526
6527SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
6528 SDLoc dl(N);
6529 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6530 MVT InVT = V0.getValueType().getSimpleVT();
6531 MVT OutVT = MVT::getVectorVT(VT: InVT.getVectorElementType(),
6532 NumElements: N->getValueType(ResNo: 0).getVectorNumElements());
6533 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: V0, N2: N->getOperand(Num: 1));
6534 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Ext);
6535}
6536
6537SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
6538 SDLoc dl(N);
6539
6540 EVT ResVT = N->getValueType(ResNo: 0);
6541 unsigned NumElems = N->getNumOperands();
6542
6543 if (ResVT.isScalableVector()) {
6544 SDValue ResVec = DAG.getUNDEF(VT: ResVT);
6545
6546 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
6547 SDValue Op = N->getOperand(Num: OpIdx);
6548 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
6549 ResVec = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: ResVT, N1: ResVec, N2: Op,
6550 N3: DAG.getIntPtrConstant(Val: OpIdx * OpNumElts, DL: dl));
6551 }
6552
6553 return ResVec;
6554 }
6555
6556 EVT RetSclrTy = N->getValueType(ResNo: 0).getVectorElementType();
6557
6558 SmallVector<SDValue, 8> NewOps;
6559 NewOps.reserve(N: NumElems);
6560
6561 // For each incoming vector
6562 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
6563 SDValue Incoming = GetPromotedInteger(Op: N->getOperand(Num: VecIdx));
6564 EVT SclrTy = Incoming->getValueType(ResNo: 0).getVectorElementType();
6565 unsigned NumElem = Incoming->getValueType(ResNo: 0).getVectorNumElements();
6566
6567 for (unsigned i=0; i<NumElem; ++i) {
6568 // Extract element from incoming vector
6569 SDValue Ex = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Incoming,
6570 N2: DAG.getVectorIdxConstant(Val: i, DL: dl));
6571 SDValue Tr = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RetSclrTy, Operand: Ex);
6572 NewOps.push_back(Elt: Tr);
6573 }
6574 }
6575
6576 return DAG.getBuildVector(VT: N->getValueType(ResNo: 0), DL: dl, Ops: NewOps);
6577}
6578
6579SDValue DAGTypeLegalizer::ExpandIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
6580 assert(OpNo > 1);
6581 SDValue Op = N->getOperand(Num: OpNo);
6582
6583 // FIXME: Non-constant operands are not yet handled:
6584 // - https://github.com/llvm/llvm-project/issues/26431
6585 // - https://github.com/llvm/llvm-project/issues/55957
6586 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6587 if (!CN)
6588 return SDValue();
6589
6590 // Copy operands before the one being expanded.
6591 SmallVector<SDValue> NewOps;
6592 for (unsigned I = 0; I < OpNo; I++)
6593 NewOps.push_back(Elt: N->getOperand(Num: I));
6594
6595 EVT Ty = Op.getValueType();
6596 SDLoc DL = SDLoc(N);
6597 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6598 NewOps.push_back(
6599 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6600 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6601 } else {
6602 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6603 return SDValue();
6604 }
6605
6606 // Copy remaining operands.
6607 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6608 NewOps.push_back(Elt: N->getOperand(Num: I));
6609
6610 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6611
6612 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6613 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6614
6615 return SDValue(); // Signal that we have replaced the node already.
6616}
6617
6618SDValue DAGTypeLegalizer::ExpandIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
6619 assert(OpNo >= 7);
6620 SDValue Op = N->getOperand(Num: OpNo);
6621
6622 // FIXME: Non-constant operands are not yet handled:
6623 // - https://github.com/llvm/llvm-project/issues/26431
6624 // - https://github.com/llvm/llvm-project/issues/55957
6625 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6626 if (!CN)
6627 return SDValue();
6628
6629 // Copy operands before the one being expanded.
6630 SmallVector<SDValue> NewOps;
6631 for (unsigned I = 0; I < OpNo; I++)
6632 NewOps.push_back(Elt: N->getOperand(Num: I));
6633
6634 EVT Ty = Op.getValueType();
6635 SDLoc DL = SDLoc(N);
6636 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6637 NewOps.push_back(
6638 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6639 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6640 } else {
6641 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6642 return SDValue();
6643 }
6644
6645 // Copy remaining operands.
6646 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6647 NewOps.push_back(Elt: N->getOperand(Num: I));
6648
6649 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6650
6651 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6652 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6653
6654 return SDValue(); // Signal that we have replaced the node already.
6655}
6656