1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetLowering.h"
24#include "llvm/IR/DerivedTypes.h"
25#include "llvm/IR/DiagnosticInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/KnownBits.h"
28#include "llvm/Support/raw_ostream.h"
29#include <algorithm>
30using namespace llvm;
31
32#define DEBUG_TYPE "legalize-types"
33
34//===----------------------------------------------------------------------===//
35// Integer Result Promotion
36//===----------------------------------------------------------------------===//
37
38/// PromoteIntegerResult - This method is called when a result of a node is
39/// found to be in need of promotion to a larger type. At this point, the node
40/// may also have invalid operands or may have other results that need
41/// expansion, we just know that (at least) one result needs promotion.
42void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
43 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG));
44 SDValue Res = SDValue();
45
46 // See if the target wants to custom expand this node.
47 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true)) {
48 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
49 return;
50 }
51
52 switch (N->getOpcode()) {
53 default:
54#ifndef NDEBUG
55 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
56 N->dump(&DAG); dbgs() << "\n";
57#endif
58 report_fatal_error(reason: "Do not know how to promote this operator!");
59 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
60 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
61 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
62 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
63 case ISD::VP_BITREVERSE:
64 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
65 case ISD::VP_BSWAP:
66 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
67 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
68 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
69 case ISD::VP_CTLZ_ZERO_POISON:
70 case ISD::VP_CTLZ:
71 case ISD::CTLZ_ZERO_POISON:
72 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
73 case ISD::CTLS: Res = PromoteIntRes_CTLS(N); break;
74 case ISD::PARITY:
75 case ISD::VP_CTPOP:
76 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
77 case ISD::VP_CTTZ_ZERO_POISON:
78 case ISD::VP_CTTZ:
79 case ISD::CTTZ_ZERO_POISON:
80 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
81 case ISD::CTTZ_ELTS_ZERO_POISON:
82 case ISD::CTTZ_ELTS:
83 case ISD::VP_CTTZ_ELTS_ZERO_POISON:
84 case ISD::VP_CTTZ_ELTS:
85 Res = PromoteIntRes_VP_CttzElements(N);
86 break;
87 case ISD::EXTRACT_VECTOR_ELT:
88 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
89 case ISD::LOAD: Res = PromoteIntRes_LOAD(N: cast<LoadSDNode>(Val: N)); break;
90 case ISD::VP_LOAD:
91 Res = PromoteIntRes_VP_LOAD(N: cast<VPLoadSDNode>(Val: N));
92 break;
93 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(N: cast<MaskedLoadSDNode>(Val: N));
94 break;
95 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(N: cast<MaskedGatherSDNode>(Val: N));
96 break;
97 case ISD::VECTOR_COMPRESS:
98 Res = PromoteIntRes_VECTOR_COMPRESS(N);
99 break;
100 case ISD::SELECT:
101 case ISD::VSELECT:
102 case ISD::VP_SELECT:
103 case ISD::VP_MERGE:
104 Res = PromoteIntRes_Select(N);
105 break;
106 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
107 case ISD::STRICT_FSETCC:
108 case ISD::STRICT_FSETCCS:
109 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
110 case ISD::SMIN:
111 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
112 case ISD::UMIN:
113 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
114
115 case ISD::SHL:
116 case ISD::VP_SHL: Res = PromoteIntRes_SHL(N); break;
117 case ISD::SIGN_EXTEND_INREG:
118 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
119 case ISD::SRA:
120 case ISD::VP_SRA: Res = PromoteIntRes_SRA(N); break;
121 case ISD::SRL:
122 case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
123 case ISD::VP_TRUNCATE:
124 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
125 case ISD::POISON:
126 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
127 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
128 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
129
130 case ISD::EXTRACT_SUBVECTOR:
131 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
132 case ISD::INSERT_SUBVECTOR:
133 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
134 case ISD::VECTOR_REVERSE:
135 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
136 case ISD::VECTOR_SHUFFLE:
137 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
138 case ISD::VECTOR_SPLICE_LEFT:
139 case ISD::VECTOR_SPLICE_RIGHT:
140 Res = PromoteIntRes_VECTOR_SPLICE(N);
141 break;
142 case ISD::VECTOR_INTERLEAVE:
143 case ISD::VECTOR_DEINTERLEAVE:
144 Res = PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(N);
145 return;
146 case ISD::INSERT_VECTOR_ELT:
147 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
148 case ISD::BUILD_VECTOR:
149 Res = PromoteIntRes_BUILD_VECTOR(N);
150 break;
151 case ISD::SPLAT_VECTOR:
152 case ISD::SCALAR_TO_VECTOR:
153 Res = PromoteIntRes_ScalarOp(N);
154 break;
155 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
156 case ISD::CONCAT_VECTORS:
157 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
158
159 case ISD::ANY_EXTEND_VECTOR_INREG:
160 case ISD::SIGN_EXTEND_VECTOR_INREG:
161 case ISD::ZERO_EXTEND_VECTOR_INREG:
162 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
163
164 case ISD::VECTOR_FIND_LAST_ACTIVE:
165 Res = PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(N);
166 break;
167
168 case ISD::GET_ACTIVE_LANE_MASK:
169 Res = PromoteIntRes_GET_ACTIVE_LANE_MASK(N);
170 break;
171
172 case ISD::PARTIAL_REDUCE_UMLA:
173 case ISD::PARTIAL_REDUCE_SMLA:
174 case ISD::PARTIAL_REDUCE_SUMLA:
175 Res = PromoteIntRes_PARTIAL_REDUCE_MLA(N);
176 break;
177
178 case ISD::SIGN_EXTEND:
179 case ISD::VP_SIGN_EXTEND:
180 case ISD::ZERO_EXTEND:
181 case ISD::VP_ZERO_EXTEND:
182 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
183
184 case ISD::VP_FP_TO_SINT:
185 case ISD::VP_FP_TO_UINT:
186 case ISD::STRICT_FP_TO_SINT:
187 case ISD::STRICT_FP_TO_UINT:
188 case ISD::FP_TO_SINT:
189 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
190
191 case ISD::FP_TO_SINT_SAT:
192 case ISD::FP_TO_UINT_SAT:
193 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
194
195 case ISD::FP_TO_BF16:
196 case ISD::FP_TO_FP16:
197 Res = PromoteIntRes_FP_TO_FP16_BF16(N);
198 break;
199 case ISD::CONVERT_TO_ARBITRARY_FP:
200 Res = PromoteIntRes_CONVERT_TO_ARBITRARY_FP(N);
201 break;
202 case ISD::STRICT_FP_TO_BF16:
203 case ISD::STRICT_FP_TO_FP16:
204 Res = PromoteIntRes_STRICT_FP_TO_FP16_BF16(N);
205 break;
206 case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break;
207
208 case ISD::AND:
209 case ISD::OR:
210 case ISD::XOR:
211 case ISD::ADD:
212 case ISD::SUB:
213 case ISD::MUL:
214 case ISD::VP_AND:
215 case ISD::VP_OR:
216 case ISD::VP_XOR:
217 case ISD::VP_ADD:
218 case ISD::VP_SUB:
219 case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
220
221 case ISD::ABDS:
222 case ISD::AVGCEILS:
223 case ISD::AVGFLOORS:
224 case ISD::VP_SMIN:
225 case ISD::VP_SMAX:
226 case ISD::SDIV:
227 case ISD::SREM:
228 case ISD::VP_SDIV:
229 case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
230
231 case ISD::ABDU:
232 case ISD::AVGCEILU:
233 case ISD::AVGFLOORU:
234 case ISD::VP_UMIN:
235 case ISD::VP_UMAX:
236 case ISD::UDIV:
237 case ISD::UREM:
238 case ISD::VP_UDIV:
239 case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
240
241 case ISD::MASKED_UDIV:
242 case ISD::MASKED_UREM:
243 Res = PromoteIntRes_ZExtMaskedIntBinOp(N);
244 break;
245 case ISD::MASKED_SDIV:
246 case ISD::MASKED_SREM:
247 Res = PromoteIntRes_SExtMaskedIntBinOp(N);
248 break;
249
250 case ISD::SADDO:
251 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
252 case ISD::UADDO:
253 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
254 case ISD::SMULO:
255 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
256
257 case ISD::ADDE:
258 case ISD::SUBE:
259 case ISD::UADDO_CARRY:
260 case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break;
261
262 case ISD::SADDO_CARRY:
263 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
264
265 case ISD::SADDSAT:
266 case ISD::UADDSAT:
267 case ISD::SSUBSAT:
268 case ISD::USUBSAT:
269 case ISD::SSHLSAT:
270 case ISD::USHLSAT:
271 Res = PromoteIntRes_ADDSUBSHLSAT<EmptyMatchContext>(N);
272 break;
273 case ISD::VP_SADDSAT:
274 case ISD::VP_UADDSAT:
275 case ISD::VP_SSUBSAT:
276 case ISD::VP_USUBSAT:
277 Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
278 break;
279
280 case ISD::SCMP:
281 case ISD::UCMP:
282 Res = PromoteIntRes_CMP(N);
283 break;
284
285 case ISD::SMULFIX:
286 case ISD::SMULFIXSAT:
287 case ISD::UMULFIX:
288 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
289
290 case ISD::SDIVFIX:
291 case ISD::SDIVFIXSAT:
292 case ISD::UDIVFIX:
293 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
294
295 case ISD::ABS:
296 case ISD::ABS_MIN_POISON:
297 Res = PromoteIntRes_ABS(N);
298 break;
299
300 case ISD::ATOMIC_LOAD:
301 Res = PromoteIntRes_Atomic0(N: cast<AtomicSDNode>(Val: N)); break;
302
303 case ISD::ATOMIC_LOAD_ADD:
304 case ISD::ATOMIC_LOAD_SUB:
305 case ISD::ATOMIC_LOAD_AND:
306 case ISD::ATOMIC_LOAD_CLR:
307 case ISD::ATOMIC_LOAD_OR:
308 case ISD::ATOMIC_LOAD_XOR:
309 case ISD::ATOMIC_LOAD_NAND:
310 case ISD::ATOMIC_LOAD_MIN:
311 case ISD::ATOMIC_LOAD_MAX:
312 case ISD::ATOMIC_LOAD_UMIN:
313 case ISD::ATOMIC_LOAD_UMAX:
314 case ISD::ATOMIC_SWAP:
315 Res = PromoteIntRes_Atomic1(N: cast<AtomicSDNode>(Val: N)); break;
316
317 case ISD::ATOMIC_CMP_SWAP:
318 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
319 Res = PromoteIntRes_AtomicCmpSwap(N: cast<AtomicSDNode>(Val: N), ResNo);
320 break;
321
322 case ISD::VECREDUCE_ADD:
323 case ISD::VECREDUCE_MUL:
324 case ISD::VECREDUCE_AND:
325 case ISD::VECREDUCE_OR:
326 case ISD::VECREDUCE_XOR:
327 case ISD::VECREDUCE_SMAX:
328 case ISD::VECREDUCE_SMIN:
329 case ISD::VECREDUCE_UMAX:
330 case ISD::VECREDUCE_UMIN:
331 Res = PromoteIntRes_VECREDUCE(N);
332 break;
333
334 case ISD::VP_REDUCE_ADD:
335 case ISD::VP_REDUCE_MUL:
336 case ISD::VP_REDUCE_AND:
337 case ISD::VP_REDUCE_OR:
338 case ISD::VP_REDUCE_XOR:
339 case ISD::VP_REDUCE_SMAX:
340 case ISD::VP_REDUCE_SMIN:
341 case ISD::VP_REDUCE_UMAX:
342 case ISD::VP_REDUCE_UMIN:
343 Res = PromoteIntRes_VP_REDUCE(N);
344 break;
345
346 case ISD::LOOP_DEPENDENCE_WAR_MASK:
347 case ISD::LOOP_DEPENDENCE_RAW_MASK:
348 Res = PromoteIntRes_LOOP_DEPENDENCE_MASK(N);
349 break;
350
351 case ISD::FREEZE:
352 Res = PromoteIntRes_FREEZE(N);
353 break;
354
355 case ISD::ROTL:
356 case ISD::ROTR:
357 Res = PromoteIntRes_Rotate(N);
358 break;
359
360 case ISD::FSHL:
361 case ISD::FSHR:
362 Res = PromoteIntRes_FunnelShift(N);
363 break;
364
365 case ISD::VP_FSHL:
366 case ISD::VP_FSHR:
367 Res = PromoteIntRes_VPFunnelShift(N);
368 break;
369
370 case ISD::CLMUL:
371 case ISD::CLMULH:
372 case ISD::CLMULR:
373 Res = PromoteIntRes_CLMUL(N);
374 break;
375
376 case ISD::PEXT:
377 Res = PromoteIntRes_PEXT(N);
378 break;
379
380 case ISD::PDEP:
381 Res = PromoteIntRes_PDEP(N);
382 break;
383
384 case ISD::IS_FPCLASS:
385 Res = PromoteIntRes_IS_FPCLASS(N);
386 break;
387 case ISD::FFREXP:
388 Res = PromoteIntRes_FFREXP(N);
389 break;
390
391 case ISD::LRINT:
392 case ISD::LLRINT:
393 Res = PromoteIntRes_XRINT(N);
394 break;
395
396 case ISD::PATCHPOINT:
397 Res = PromoteIntRes_PATCHPOINT(N);
398 break;
399 case ISD::READ_REGISTER:
400 Res = PromoteIntRes_READ_REGISTER(N);
401 break;
402 }
403
404 // If the result is null then the sub-method took care of registering it.
405 if (Res.getNode())
406 SetPromotedInteger(Op: SDValue(N, ResNo), Result: Res);
407}
408
409SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
410 unsigned ResNo) {
411 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
412 return GetPromotedInteger(Op);
413}
414
415SDValue DAGTypeLegalizer::PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
416 EVT VT = N->getValueType(ResNo: 0);
417 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
418 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: NewVT, Ops: N->ops());
419}
420
421SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
422 // Sign-extend the new bits, and continue the assertion.
423 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
424 return DAG.getNode(Opcode: ISD::AssertSext, DL: SDLoc(N),
425 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
426}
427
428SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
429 // Zero the new bits, and continue the assertion.
430 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
431 return DAG.getNode(Opcode: ISD::AssertZext, DL: SDLoc(N),
432 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
433}
434
435SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
436 EVT ResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
437 ISD::LoadExtType ExtType = N->getExtensionType();
438 if (ExtType == ISD::NON_EXTLOAD) {
439 switch (TLI.getExtendForAtomicOps()) {
440 case ISD::SIGN_EXTEND:
441 ExtType = ISD::SEXTLOAD;
442 break;
443 case ISD::ZERO_EXTEND:
444 ExtType = ISD::ZEXTLOAD;
445 break;
446 case ISD::ANY_EXTEND:
447 ExtType = ISD::EXTLOAD;
448 break;
449 default:
450 llvm_unreachable("Invalid atomic op extension");
451 }
452 }
453
454 SDValue Res =
455 DAG.getAtomicLoad(ExtType, dl: SDLoc(N), MemVT: N->getMemoryVT(), VT: ResVT,
456 Chain: N->getChain(), Ptr: N->getBasePtr(), MMO: N->getMemOperand());
457
458 // Legalize the chain result - switch anything that used the old chain to
459 // use the new one.
460 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
461 return Res;
462}
463
464SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
465 SDValue Op2 = N->getOperand(Num: 2);
466 switch (TLI.getExtendForAtomicRMWArg(Op: N->getOpcode())) {
467 case ISD::SIGN_EXTEND:
468 Op2 = SExtPromotedInteger(Op: Op2);
469 break;
470 case ISD::ZERO_EXTEND:
471 Op2 = ZExtPromotedInteger(Op: Op2);
472 break;
473 case ISD::ANY_EXTEND:
474 Op2 = GetPromotedInteger(Op: Op2);
475 break;
476 default:
477 llvm_unreachable("Invalid atomic op extension");
478 }
479 SDValue Res = DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N),
480 MemVT: N->getMemoryVT(),
481 Chain: N->getChain(), Ptr: N->getBasePtr(),
482 Val: Op2, MMO: N->getMemOperand());
483 // Legalize the chain result - switch anything that used the old chain to
484 // use the new one.
485 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
486 return Res;
487}
488
489SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
490 unsigned ResNo) {
491 if (ResNo == 1) {
492 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
493 EVT SVT = getSetCCResultType(VT: N->getOperand(Num: 2).getValueType());
494 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
495
496 // Only use the result of getSetCCResultType if it is legal,
497 // otherwise just use the promoted result type (NVT).
498 if (!TLI.isTypeLegal(VT: SVT))
499 SVT = NVT;
500
501 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: SVT, VT3: MVT::Other);
502 SDValue Res = DAG.getAtomicCmpSwap(
503 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs,
504 Chain: N->getChain(), Ptr: N->getBasePtr(), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
505 MMO: N->getMemOperand());
506 ReplaceValueWith(From: SDValue(N, 0), To: Res.getValue(R: 0));
507 ReplaceValueWith(From: SDValue(N, 2), To: Res.getValue(R: 2));
508 return DAG.getSExtOrTrunc(Op: Res.getValue(R: 1), DL: SDLoc(N), VT: NVT);
509 }
510
511 // Op2 is used for the comparison and thus must be extended according to the
512 // target's atomic operations. Op3 is merely stored and so can be left alone.
513 SDValue Op2 = N->getOperand(Num: 2);
514 SDValue Op3 = GetPromotedInteger(Op: N->getOperand(Num: 3));
515 switch (TLI.getExtendForAtomicCmpSwapArg()) {
516 case ISD::SIGN_EXTEND:
517 Op2 = SExtPromotedInteger(Op: Op2);
518 break;
519 case ISD::ZERO_EXTEND:
520 Op2 = ZExtPromotedInteger(Op: Op2);
521 break;
522 case ISD::ANY_EXTEND:
523 Op2 = GetPromotedInteger(Op: Op2);
524 break;
525 default:
526 llvm_unreachable("Invalid atomic op extension");
527 }
528
529 SDVTList VTs =
530 DAG.getVTList(VT1: Op2.getValueType(), VT2: N->getValueType(ResNo: 1), VT3: MVT::Other);
531 SDValue Res = DAG.getAtomicCmpSwap(
532 Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs, Chain: N->getChain(),
533 Ptr: N->getBasePtr(), Cmp: Op2, Swp: Op3, MMO: N->getMemOperand());
534 // Update the use to N with the newly created Res.
535 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
536 ReplaceValueWith(From: SDValue(N, i), To: Res.getValue(R: i));
537 return Res;
538}
539
540SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
541 SDValue InOp = N->getOperand(Num: 0);
542 EVT InVT = InOp.getValueType();
543 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
544 EVT OutVT = N->getValueType(ResNo: 0);
545 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
546 SDLoc dl(N);
547
548 switch (getTypeAction(VT: InVT)) {
549 case TargetLowering::TypeLegal:
550 break;
551 case TargetLowering::TypePromoteInteger:
552 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector() && !NInVT.isVector())
553 // The input promotes to the same size. Convert the promoted value.
554 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetPromotedInteger(Op: InOp));
555 break;
556 case TargetLowering::TypeSoftenFloat:
557 // Promote the integer operand by hand.
558 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftenedFloat(Op: InOp));
559 case TargetLowering::TypeSoftPromoteHalf:
560 // Promote the integer operand by hand.
561 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftPromotedHalf(Op: InOp));
562 case TargetLowering::TypeExpandInteger:
563 case TargetLowering::TypeExpandFloat:
564 break;
565 case TargetLowering::TypeScalarizeVector:
566 // Convert the element to an integer and promote it by hand.
567 if (!NOutVT.isVector())
568 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
569 Operand: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)));
570 break;
571 case TargetLowering::TypeScalarizeScalableVector:
572 report_fatal_error(reason: "Scalarization of scalable vectors is not supported.");
573 case TargetLowering::TypeSplitVector: {
574 if (!NOutVT.isVector()) {
575 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
576 // pieces of the input into integers and reassemble in the final type.
577 SDValue Lo, Hi;
578 GetSplitVector(Op: N->getOperand(Num: 0), Lo, Hi);
579 Lo = BitConvertToInteger(Op: Lo);
580 Hi = BitConvertToInteger(Op: Hi);
581
582 if (DAG.getDataLayout().isBigEndian())
583 std::swap(a&: Lo, b&: Hi);
584
585 InOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
586 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
587 BitWidth: NOutVT.getSizeInBits()),
588 Operand: JoinIntegers(Lo, Hi));
589 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: InOp);
590 }
591 break;
592 }
593 case TargetLowering::TypeWidenVector:
594 // The input is widened to the same size. Convert to the widened value.
595 // Make sure that the outgoing value is not a vector, because this would
596 // make us bitcast between two vectors which are legalized in different ways.
597 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector()) {
598 SDValue Res =
599 DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetWidenedVector(Op: InOp));
600
601 // For big endian targets we need to shift the casted value or the
602 // interesting bits will end up at the wrong place.
603 if (DAG.getDataLayout().isBigEndian()) {
604 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
605 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
606 Res = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NOutVT, N1: Res,
607 N2: DAG.getShiftAmountConstant(Val: ShiftAmt, VT: NOutVT, DL: dl));
608 }
609 return Res;
610 }
611 // If the output type is also a vector and widening it to the same size
612 // as the widened input type would be a legal type, we can widen the bitcast
613 // and handle the promotion after.
614 if (NOutVT.isVector()) {
615 TypeSize WidenInSize = NInVT.getSizeInBits();
616 TypeSize OutSize = OutVT.getSizeInBits();
617 if (WidenInSize.hasKnownScalarFactor(RHS: OutSize)) {
618 unsigned Scale = WidenInSize.getKnownScalarFactor(RHS: OutSize);
619 EVT WideOutVT =
620 EVT::getVectorVT(Context&: *DAG.getContext(), VT: OutVT.getVectorElementType(),
621 EC: OutVT.getVectorElementCount() * Scale);
622 if (isTypeLegal(VT: WideOutVT)) {
623 InOp = DAG.getBitcast(VT: WideOutVT, V: GetWidenedVector(Op: InOp));
624 InOp = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: InOp,
625 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
626 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: InOp);
627 }
628 }
629 }
630 }
631
632 // TODO: Handle big endian
633 if (!NOutVT.isVector() && InOp.getValueType().isVector() &&
634 DAG.getDataLayout().isLittleEndian()) {
635 // Pad the vector operand with undef and cast to a wider integer.
636 EVT EltVT = InOp.getValueType().getVectorElementType();
637 TypeSize EltSize = EltVT.getSizeInBits();
638 TypeSize OutSize = NOutVT.getSizeInBits();
639
640 if (OutSize.hasKnownScalarFactor(RHS: EltSize)) {
641 unsigned NumEltsWithPadding = OutSize.getKnownScalarFactor(RHS: EltSize);
642 EVT WideVecVT =
643 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
644
645 if (isTypeLegal(VT: WideVecVT)) {
646 SDValue Inserted = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: WideVecVT,
647 N1: DAG.getUNDEF(VT: WideVecVT), N2: InOp,
648 N3: DAG.getVectorIdxConstant(Val: 0, DL: dl));
649
650 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Inserted);
651 }
652 }
653 }
654
655 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
656 Operand: CreateStackStoreLoad(Op: InOp, DestVT: OutVT));
657}
658
659SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
660 SDValue V = GetPromotedInteger(Op: N->getOperand(Num: 0));
661 return DAG.getNode(Opcode: ISD::FREEZE, DL: SDLoc(N),
662 VT: V.getValueType(), Operand: V);
663}
664
665SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
666 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
667 EVT OVT = N->getValueType(ResNo: 0);
668 EVT NVT = Op.getValueType();
669 SDLoc dl(N);
670
671 // If the larger BSWAP isn't supported by the target, try to expand now.
672 // If we expand later we'll end up with more operations since we lost the
673 // original type. We only do this for scalars since we have a shuffle
674 // based lowering for vectors in LegalizeVectorOps.
675 if (!OVT.isVector() &&
676 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BSWAP, VT: NVT)) {
677 if (SDValue Res = TLI.expandBSWAP(N, DAG))
678 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
679 }
680
681 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
682 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
683 if (N->getOpcode() == ISD::BSWAP)
684 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: NVT, Operand: Op),
685 N2: ShAmt);
686 SDValue Mask = N->getOperand(Num: 1);
687 SDValue EVL = N->getOperand(Num: 2);
688 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
689 N1: DAG.getNode(Opcode: ISD::VP_BSWAP, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL), N2: ShAmt,
690 N3: Mask, N4: EVL);
691}
692
693SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
694 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
695 EVT OVT = N->getValueType(ResNo: 0);
696 EVT NVT = Op.getValueType();
697 SDLoc dl(N);
698
699 // If the larger BITREVERSE isn't supported by the target, try to expand now.
700 // If we expand later we'll end up with more operations since we lost the
701 // original type. We only do this for scalars since we have a shuffle
702 // based lowering for vectors in LegalizeVectorOps.
703 if (!OVT.isVector() && OVT.isSimple() &&
704 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BITREVERSE, VT: NVT)) {
705 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
706 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
707 }
708
709 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
710 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
711 if (N->getOpcode() == ISD::BITREVERSE)
712 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT,
713 N1: DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: NVT, Operand: Op), N2: ShAmt);
714 SDValue Mask = N->getOperand(Num: 1);
715 SDValue EVL = N->getOperand(Num: 2);
716 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
717 N1: DAG.getNode(Opcode: ISD::VP_BITREVERSE, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
718 N2: ShAmt, N3: Mask, N4: EVL);
719}
720
721SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
722 // The pair element type may be legal, or may not promote to the same type as
723 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
724 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N),
725 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
726 VT: N->getValueType(ResNo: 0)), Operand: JoinIntegers(Lo: N->getOperand(Num: 0),
727 Hi: N->getOperand(Num: 1)));
728}
729
730SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
731 EVT VT = N->getValueType(ResNo: 0);
732 // FIXME there is no actual debug info here
733 SDLoc dl(N);
734 // Zero extend things like i1, sign extend everything else. It shouldn't
735 // matter in theory which one we pick, but this tends to give better code?
736 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
737 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl,
738 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT),
739 Operand: SDValue(N, 0));
740 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
741 return Result;
742}
743
744SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
745 EVT OVT = N->getValueType(ResNo: 0);
746 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
747 SDLoc dl(N);
748
749 // If the larger CTLZ isn't supported by the target, try to expand now.
750 // If we expand later we'll end up with more operations since we lost the
751 // original type.
752 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
753 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ, VT: NVT) &&
754 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ_ZERO_POISON, VT: NVT)) {
755 if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
756 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
757 return Result;
758 }
759 }
760
761 unsigned CtlzOpcode = N->getOpcode();
762 if (CtlzOpcode == ISD::CTLZ || CtlzOpcode == ISD::VP_CTLZ) {
763 // Subtract off the extra leading bits in the bigger type.
764 SDValue ExtractLeadingBits = DAG.getConstant(
765 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
766 // Zero extend to the promoted type and do the count there.
767 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
768
769 // At this stage SUB is guaranteed to be positive no-wrap,
770 // that to be used in further KnownBits optimizations.
771 if (!N->isVPOpcode())
772 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT,
773 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Op),
774 N2: ExtractLeadingBits, Flags: SDNodeFlags::NoUnsignedWrap);
775 SDValue Mask = N->getOperand(Num: 1);
776 SDValue EVL = N->getOperand(Num: 2);
777 return DAG.getNode(Opcode: ISD::VP_SUB, DL: dl, VT: NVT,
778 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
779 N2: ExtractLeadingBits, N3: Mask, N4: EVL,
780 Flags: SDNodeFlags::NoUnsignedWrap);
781 }
782 if (CtlzOpcode == ISD::CTLZ_ZERO_POISON ||
783 CtlzOpcode == ISD::VP_CTLZ_ZERO_POISON) {
784 // Any Extend the argument
785 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
786 // Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
787 unsigned SHLAmount = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
788 auto ShiftConst =
789 DAG.getShiftAmountConstant(Val: SHLAmount, VT: Op.getValueType(), DL: dl);
790 if (!N->isVPOpcode()) {
791 Op = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst);
792 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, Operand: Op);
793 }
794
795 SDValue Mask = N->getOperand(Num: 1);
796 SDValue EVL = N->getOperand(Num: 2);
797 Op = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst, N3: Mask, N4: EVL);
798 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL);
799 }
800 llvm_unreachable("Invalid CTLZ Opcode");
801}
802
803SDValue DAGTypeLegalizer::PromoteIntRes_CTLS(SDNode *N) {
804 EVT OVT = N->getValueType(ResNo: 0);
805 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
806 SDLoc dl(N);
807
808 SDValue ExtractLeadingBits = DAG.getConstant(
809 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
810
811 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
812 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Op),
813 N2: ExtractLeadingBits);
814}
815
816SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
817 EVT OVT = N->getValueType(ResNo: 0);
818 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
819
820 // If the larger CTPOP isn't supported by the target, try to expand now.
821 // If we expand later we'll end up with more operations since we lost the
822 // original type.
823 // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
824 // TargetLowering.
825 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
826 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTPOP, VT: NVT)) {
827 if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
828 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Result);
829 return Result;
830 }
831 }
832
833 // Zero extend to the promoted type and do the count or parity there.
834 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
835 if (!N->isVPOpcode())
836 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), Operand: Op);
837
838 SDValue Mask = N->getOperand(Num: 1);
839 SDValue EVL = N->getOperand(Num: 2);
840 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), N1: Op, N2: Mask,
841 N3: EVL);
842}
843
844SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
845 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
846 EVT OVT = N->getValueType(ResNo: 0);
847 EVT NVT = Op.getValueType();
848 SDLoc dl(N);
849
850 // If the larger CTTZ isn't supported by the target, try to expand now.
851 // If we expand later we'll end up with more operations since we lost the
852 // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
853 // larger type.
854 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
855 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ, VT: NVT) &&
856 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ_ZERO_POISON, VT: NVT) &&
857 !TLI.isOperationLegal(Op: ISD::CTPOP, VT: NVT) &&
858 !TLI.isOperationLegal(Op: ISD::CTLZ, VT: NVT)) {
859 if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
860 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
861 return Result;
862 }
863 }
864
865 unsigned NewOpc = N->getOpcode();
866 if (NewOpc == ISD::CTTZ || NewOpc == ISD::VP_CTTZ) {
867 // The count is the same in the promoted type except if the original
868 // value was zero. This can be handled by setting the bit just off
869 // the top of the original type.
870 auto TopBit = APInt::getOneBitSet(numBits: NVT.getScalarSizeInBits(),
871 BitNo: OVT.getScalarSizeInBits());
872 if (NewOpc == ISD::CTTZ) {
873 Op = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
874 NewOpc = ISD::CTTZ_ZERO_POISON;
875 } else {
876 Op =
877 DAG.getNode(Opcode: ISD::VP_OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT),
878 N3: N->getOperand(Num: 1), N4: N->getOperand(Num: 2));
879 NewOpc = ISD::VP_CTTZ_ZERO_POISON;
880 }
881 }
882 if (!N->isVPOpcode())
883 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Op);
884 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, N1: Op, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
885}
886
887SDValue DAGTypeLegalizer::PromoteIntRes_VP_CttzElements(SDNode *N) {
888 SDLoc DL(N);
889 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
890 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NewVT, Ops: N->ops());
891}
892
893SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
894 SDLoc dl(N);
895 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
896
897 SDValue Op0 = N->getOperand(Num: 0);
898 SDValue Op1 = N->getOperand(Num: 1);
899
900 // If the input also needs to be promoted, do that first so we can get a
901 // get a good idea for the output type.
902 if (TLI.getTypeAction(Context&: *DAG.getContext(), VT: Op0.getValueType())
903 == TargetLowering::TypePromoteInteger) {
904 SDValue In = GetPromotedInteger(Op: Op0);
905
906 // If the new type is larger than NVT, use it. We probably won't need to
907 // promote it again.
908 EVT SVT = In.getValueType().getScalarType();
909 if (SVT.bitsGE(VT: NVT)) {
910 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SVT, N1: In, N2: Op1);
911 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NVT);
912 }
913 }
914
915 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NVT, N1: Op0, N2: Op1);
916}
917
918SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
919 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
920 unsigned NewOpc =
921 TLI.getPreferredFPToIntOpcode(Op: N->getOpcode(), FromVT: N->getValueType(ResNo: 0), ToVT: NVT);
922 SDLoc dl(N);
923
924 SDValue Res;
925 if (N->isStrictFPOpcode()) {
926 Res = DAG.getNode(Opcode: NewOpc, DL: dl, ResultTys: {NVT, MVT::Other},
927 Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1)});
928 // Legalize the chain result - switch anything that used the old chain to
929 // use the new one.
930 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
931 } else if (NewOpc == ISD::VP_FP_TO_SINT || NewOpc == ISD::VP_FP_TO_UINT) {
932 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1),
933 N->getOperand(Num: 2)});
934 } else {
935 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
936 }
937
938 // Assert that the converted value fits in the original type. If it doesn't
939 // (eg: because the value being converted is too big), then the result of the
940 // original operation was undefined anyway, so the assert is still correct.
941 //
942 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
943 // before legalization: fp-to-uint16, 65534. -> 0xfffe
944 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
945 return DAG.getNode(Opcode: (N->getOpcode() == ISD::FP_TO_UINT ||
946 N->getOpcode() == ISD::STRICT_FP_TO_UINT ||
947 N->getOpcode() == ISD::VP_FP_TO_UINT)
948 ? ISD::AssertZext
949 : ISD::AssertSext,
950 DL: dl, VT: NVT, N1: Res,
951 N2: DAG.getValueType(N->getValueType(ResNo: 0).getScalarType()));
952}
953
954SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
955 // Promote the result type, while keeping the original width in Op1.
956 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
957 SDLoc dl(N);
958 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
959 N2: N->getOperand(Num: 1));
960}
961
962SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16_BF16(SDNode *N) {
963 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
964 SDLoc dl(N);
965
966 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
967}
968
969// TODO: CONVERT_TO_ARBITRARY_FP also needs an ExpandIntegerResult handler for
970// wider arbitrary FP formats whose integer result requires expansion.
971SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_TO_ARBITRARY_FP(SDNode *N) {
972 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
973 SDLoc dl(N);
974
975 return DAG.getNode(Opcode: ISD::CONVERT_TO_ARBITRARY_FP, DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
976 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
977}
978
979SDValue DAGTypeLegalizer::PromoteIntRes_STRICT_FP_TO_FP16_BF16(SDNode *N) {
980 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
981 SDLoc dl(N);
982
983 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
984 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
985 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
986 return Res;
987}
988
989SDValue DAGTypeLegalizer::PromoteIntRes_XRINT(SDNode *N) {
990 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
991 SDLoc dl(N);
992 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
993}
994
995SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) {
996 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
997 SDLoc dl(N);
998
999 SDValue Res =
1000 DAG.getNode(Opcode: N->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
1001
1002 // Legalize the chain result - switch anything that used the old chain to
1003 // use the new one.
1004 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1005 return Res;
1006}
1007
1008SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
1009 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1010 SDLoc dl(N);
1011
1012 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
1013 == TargetLowering::TypePromoteInteger) {
1014 SDValue Res = GetPromotedInteger(Op: N->getOperand(Num: 0));
1015 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
1016
1017 // If the result and operand types are the same after promotion, simplify
1018 // to an in-register extension. Unless this is a VP_*_EXTEND.
1019 if (NVT == Res.getValueType() && N->getNumOperands() == 1) {
1020 // The high bits are not guaranteed to be anything. Insert an extend.
1021 if (N->getOpcode() == ISD::SIGN_EXTEND)
1022 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1023 N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
1024 if (N->getOpcode() == ISD::ZERO_EXTEND)
1025 return DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: N->getOperand(Num: 0).getValueType());
1026 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
1027 return Res;
1028 }
1029 }
1030
1031 // Otherwise, just extend the original operand all the way to the larger type.
1032 if (N->getNumOperands() != 1) {
1033 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
1034 assert(N->isVPOpcode() && "Expected VP opcode");
1035 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
1036 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
1037 }
1038 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
1039}
1040
1041SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
1042 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1043 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1044 ISD::LoadExtType ExtType =
1045 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
1046 SDLoc dl(N);
1047 SDValue Res = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
1048 MemVT: N->getMemoryVT(), MMO: N->getMemOperand());
1049
1050 // Legalize the chain result - switch anything that used the old chain to
1051 // use the new one.
1052 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1053 return Res;
1054}
1055
1056SDValue DAGTypeLegalizer::PromoteIntRes_VP_LOAD(VPLoadSDNode *N) {
1057 assert(!N->isIndexed() && "Indexed vp_load during type legalization!");
1058 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1059 ISD::LoadExtType ExtType = (N->getExtensionType() == ISD::NON_EXTLOAD)
1060 ? ISD::EXTLOAD
1061 : N->getExtensionType();
1062 SDLoc dl(N);
1063 SDValue Res =
1064 DAG.getExtLoadVP(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
1065 Mask: N->getMask(), EVL: N->getVectorLength(), MemVT: N->getMemoryVT(),
1066 MMO: N->getMemOperand(), IsExpanding: N->isExpandingLoad());
1067 // Legalize the chain result - switch anything that used the old chain to
1068 // use the new one.
1069 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1070 return Res;
1071}
1072
1073SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
1074 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1075 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1076
1077 ISD::LoadExtType ExtType = N->getExtensionType();
1078 if (ExtType == ISD::NON_EXTLOAD)
1079 ExtType = ISD::EXTLOAD;
1080
1081 SDLoc dl(N);
1082 SDValue Res = DAG.getMaskedLoad(VT: NVT, dl, Chain: N->getChain(), Base: N->getBasePtr(),
1083 Offset: N->getOffset(), Mask: N->getMask(), Src0: ExtPassThru,
1084 MemVT: N->getMemoryVT(), MMO: N->getMemOperand(),
1085 AM: N->getAddressingMode(), ExtType,
1086 IsExpanding: N->isExpandingLoad());
1087 // Legalize the chain result - switch anything that used the old chain to
1088 // use the new one.
1089 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1090 return Res;
1091}
1092
1093SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
1094 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1095 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1096 assert(NVT == ExtPassThru.getValueType() &&
1097 "Gather result type and the passThru argument type should be the same");
1098
1099 ISD::LoadExtType ExtType = N->getExtensionType();
1100 if (ExtType == ISD::NON_EXTLOAD)
1101 ExtType = ISD::EXTLOAD;
1102
1103 SDLoc dl(N);
1104 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
1105 N->getIndex(), N->getScale() };
1106 SDValue Res = DAG.getMaskedGather(VTs: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
1107 MemVT: N->getMemoryVT(), dl, Ops,
1108 MMO: N->getMemOperand(), IndexType: N->getIndexType(),
1109 ExtTy: ExtType);
1110 // Legalize the chain result - switch anything that used the old chain to
1111 // use the new one.
1112 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1113 return Res;
1114}
1115
1116SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_COMPRESS(SDNode *N) {
1117 SDValue Vec = GetPromotedInteger(Op: N->getOperand(Num: 0));
1118 SDValue Passthru = GetPromotedInteger(Op: N->getOperand(Num: 2));
1119 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT: Vec.getValueType(), N1: Vec,
1120 N2: N->getOperand(Num: 1), N3: Passthru);
1121}
1122
1123/// Promote the overflow flag of an overflowing arithmetic node.
1124SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
1125 // Change the return type of the boolean result while obeying
1126 // getSetCCResultType.
1127 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1128 EVT VT = N->getValueType(ResNo: 0);
1129 EVT SVT = getSetCCResultType(VT);
1130 SDValue Ops[3] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
1131 unsigned NumOps = N->getNumOperands();
1132 assert(NumOps <= 3 && "Too many operands");
1133 if (NumOps == 3)
1134 Ops[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: VT);
1135
1136 SDLoc dl(N);
1137 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: SVT),
1138 Ops: ArrayRef(Ops, NumOps));
1139
1140 // Modified the sum result - switch anything that used the old sum to use
1141 // the new one.
1142 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1143
1144 // Convert to the expected type.
1145 return DAG.getBoolExtOrTrunc(Op: Res.getValue(R: 1), SL: dl, VT: NVT, OpVT: VT);
1146}
1147
1148template <class MatchContextClass>
1149SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
1150 // If the promoted type is legal, we can convert this to:
1151 // 1. ANY_EXTEND iN to iM
1152 // 2. SHL by M-N
1153 // 3. [US][ADD|SUB|SHL]SAT
1154 // 4. L/ASHR by M-N
1155 // Else it is more efficient to convert this to a min and a max
1156 // operation in the higher precision arithmetic.
1157 SDLoc dl(N);
1158 SDValue Op1 = N->getOperand(Num: 0);
1159 SDValue Op2 = N->getOperand(Num: 1);
1160 MatchContextClass matcher(DAG, TLI, N);
1161
1162 unsigned Opcode = matcher.getRootBaseOpcode();
1163 unsigned OldBits = Op1.getScalarValueSizeInBits();
1164
1165 // USUBSAT can always be promoted as long as we have zero/sign-extended the
1166 // args.
1167 if (Opcode == ISD::USUBSAT) {
1168 SExtOrZExtPromotedOperands(LHS&: Op1, RHS&: Op2);
1169 return matcher.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
1170 }
1171
1172 if (Opcode == ISD::UADDSAT) {
1173 EVT OVT = Op1.getValueType();
1174 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1175 // We can promote if we use sign-extend. Do this if the target prefers.
1176 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT)) {
1177 Op1 = SExtPromotedInteger(Op: Op1);
1178 Op2 = SExtPromotedInteger(Op: Op2);
1179 return matcher.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2);
1180 }
1181
1182 Op1 = ZExtPromotedInteger(Op: Op1);
1183 Op2 = ZExtPromotedInteger(Op: Op2);
1184 unsigned NewBits = NVT.getScalarSizeInBits();
1185 APInt MaxVal = APInt::getLowBitsSet(numBits: NewBits, loBitsSet: OldBits);
1186 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: NVT);
1187 SDValue Add = matcher.getNode(ISD::ADD, dl, NVT, Op1, Op2);
1188 return matcher.getNode(ISD::UMIN, dl, NVT, Add, SatMax);
1189 }
1190
1191 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
1192
1193 // FIXME: We need vp-aware PromotedInteger functions.
1194 if (IsShift) {
1195 Op1 = GetPromotedInteger(Op: Op1);
1196 if (getTypeAction(VT: Op2.getValueType()) == TargetLowering::TypePromoteInteger)
1197 Op2 = ZExtPromotedInteger(Op: Op2);
1198 } else {
1199 Op1 = SExtPromotedInteger(Op: Op1);
1200 Op2 = SExtPromotedInteger(Op: Op2);
1201 }
1202 EVT PromotedType = Op1.getValueType();
1203 unsigned NewBits = PromotedType.getScalarSizeInBits();
1204
1205 // Shift cannot use a min/max expansion, we can't detect overflow if all of
1206 // the bits have been shifted out.
1207 if (IsShift || matcher.isOperationLegal(Opcode, PromotedType)) {
1208 unsigned ShiftOp;
1209 switch (Opcode) {
1210 case ISD::SADDSAT:
1211 case ISD::SSUBSAT:
1212 case ISD::SSHLSAT:
1213 ShiftOp = ISD::SRA;
1214 break;
1215 case ISD::USHLSAT:
1216 ShiftOp = ISD::SRL;
1217 break;
1218 default:
1219 llvm_unreachable("Expected opcode to be signed or unsigned saturation "
1220 "addition, subtraction or left shift");
1221 }
1222
1223 unsigned SHLAmount = NewBits - OldBits;
1224 SDValue ShiftAmount =
1225 DAG.getShiftAmountConstant(Val: SHLAmount, VT: PromotedType, DL: dl);
1226 Op1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1, N2: ShiftAmount);
1227 if (!IsShift)
1228 Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
1229
1230 SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
1231 return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
1232 }
1233
1234 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
1235 APInt MinVal = APInt::getSignedMinValue(numBits: OldBits).sext(width: NewBits);
1236 APInt MaxVal = APInt::getSignedMaxValue(numBits: OldBits).sext(width: NewBits);
1237 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT: PromotedType);
1238 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: PromotedType);
1239 SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
1240 Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
1241 Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
1242 return Result;
1243}
1244
1245SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
1246 // Can just promote the operands then continue with operation.
1247 SDLoc dl(N);
1248 SDValue Op1Promoted, Op2Promoted;
1249 bool Signed =
1250 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
1251 bool Saturating =
1252 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
1253 if (Signed) {
1254 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1255 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1256 } else {
1257 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1258 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1259 }
1260 EVT OldType = N->getOperand(Num: 0).getValueType();
1261 EVT PromotedType = Op1Promoted.getValueType();
1262 unsigned DiffSize =
1263 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
1264
1265 if (Saturating) {
1266 // Promoting the operand and result values changes the saturation width,
1267 // which is extends the values that we clamp to on saturation. This could be
1268 // resolved by shifting one of the operands the same amount, which would
1269 // also shift the result we compare against, then shifting back.
1270 Op1Promoted =
1271 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1272 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1273 SDValue Result = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1274 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1275 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1276 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result,
1277 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1278 }
1279 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted, N2: Op2Promoted,
1280 N3: N->getOperand(Num: 2));
1281}
1282
1283static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
1284 unsigned SatW, bool Signed,
1285 const TargetLowering &TLI,
1286 SelectionDAG &DAG) {
1287 EVT VT = V.getValueType();
1288 unsigned VTW = VT.getScalarSizeInBits();
1289
1290 if (!Signed) {
1291 // Saturate to the unsigned maximum by getting the minimum of V and the
1292 // maximum.
1293 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT, N1: V,
1294 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW),
1295 DL: dl, VT));
1296 }
1297
1298 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
1299 // signed minimum of it and V.
1300 V = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT, N1: V,
1301 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW - 1),
1302 DL: dl, VT));
1303 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
1304 // signed maximum of it and V.
1305 V = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT, N1: V,
1306 N2: DAG.getConstant(Val: APInt::getHighBitsSet(numBits: VTW, hiBitsSet: VTW - SatW + 1),
1307 DL: dl, VT));
1308 return V;
1309}
1310
1311static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
1312 unsigned Scale, const TargetLowering &TLI,
1313 SelectionDAG &DAG, unsigned SatW = 0) {
1314 EVT VT = LHS.getValueType();
1315 unsigned VTSize = VT.getScalarSizeInBits();
1316 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1317 N->getOpcode() == ISD::SDIVFIXSAT;
1318 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1319 N->getOpcode() == ISD::UDIVFIXSAT;
1320
1321 SDLoc dl(N);
1322 // Widen the types by a factor of two. This is guaranteed to expand, since it
1323 // will always have enough high bits in the LHS to shift into.
1324 EVT WideVT = VT.changeElementType(
1325 Context&: *DAG.getContext(), EltVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: VTSize * 2));
1326 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL: dl, VT: WideVT);
1327 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL: dl, VT: WideVT);
1328 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS, RHS, Scale,
1329 DAG);
1330 assert(Res && "Expanding DIVFIX with wide type failed?");
1331 if (Saturating) {
1332 // If the caller has told us to saturate at something less, use that width
1333 // instead of the type before doubling. However, it cannot be more than
1334 // what we just widened!
1335 assert(SatW <= VTSize &&
1336 "Tried to saturate to more than the original type?");
1337 Res = SaturateWidenedDIVFIX(V: Res, dl, SatW: SatW == 0 ? VTSize : SatW, Signed,
1338 TLI, DAG);
1339 }
1340 return DAG.getZExtOrTrunc(Op: Res, DL: dl, VT);
1341}
1342
1343SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1344 SDLoc dl(N);
1345 SDValue Op1Promoted, Op2Promoted;
1346 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1347 N->getOpcode() == ISD::SDIVFIXSAT;
1348 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1349 N->getOpcode() == ISD::UDIVFIXSAT;
1350 if (Signed) {
1351 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1352 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1353 } else {
1354 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1355 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1356 }
1357 EVT PromotedType = Op1Promoted.getValueType();
1358 unsigned Scale = N->getConstantOperandVal(Num: 2);
1359
1360 // If the type is already legal and the operation is legal in that type, we
1361 // should not early expand.
1362 if (TLI.isTypeLegal(VT: PromotedType)) {
1363 TargetLowering::LegalizeAction Action =
1364 TLI.getFixedPointOperationAction(Op: N->getOpcode(), VT: PromotedType, Scale);
1365 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1366 unsigned Diff = PromotedType.getScalarSizeInBits() -
1367 N->getValueType(ResNo: 0).getScalarSizeInBits();
1368 if (Saturating)
1369 Op1Promoted =
1370 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1371 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1372 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1373 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1374 if (Saturating)
1375 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL: dl, VT: PromotedType, N1: Res,
1376 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1377 return Res;
1378 }
1379 }
1380
1381 // See if we can perform the division in this type without expanding.
1382 if (SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: Op1Promoted,
1383 RHS: Op2Promoted, Scale, DAG)) {
1384 if (Saturating)
1385 Res = SaturateWidenedDIVFIX(V: Res, dl,
1386 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits(),
1387 Signed, TLI, DAG);
1388 return Res;
1389 }
1390 // If we cannot, expand it to twice the type width. If we are saturating, give
1391 // it the original width as a saturating width so we don't need to emit
1392 // two saturations.
1393 return earlyExpandDIVFIX(N, LHS: Op1Promoted, RHS: Op2Promoted, Scale, TLI, DAG,
1394 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits());
1395}
1396
1397SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1398 if (ResNo == 1)
1399 return PromoteIntRes_Overflow(N);
1400
1401 // The operation overflowed iff the result in the larger type is not the
1402 // sign extension of its truncation to the original type.
1403 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1404 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1405 EVT OVT = N->getOperand(Num: 0).getValueType();
1406 EVT NVT = LHS.getValueType();
1407 SDLoc dl(N);
1408
1409 // Do the arithmetic in the larger type.
1410 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1411 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1412
1413 // Calculate the overflow flag: sign extend the arithmetic result from
1414 // the original type.
1415 SDValue Ofl = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1416 N2: DAG.getValueType(OVT));
1417 // Overflowed if and only if this is not equal to Res.
1418 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1419
1420 // Use the calculated overflow everywhere.
1421 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1422
1423 return Res;
1424}
1425
1426SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
1427 EVT PromotedResultTy =
1428 TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1429 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: PromotedResultTy,
1430 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
1431}
1432
1433SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1434 SDValue Mask = N->getOperand(Num: 0);
1435
1436 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1437 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1438
1439 unsigned Opcode = N->getOpcode();
1440 if (Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE)
1441 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS,
1442 N4: N->getOperand(Num: 3));
1443 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS);
1444}
1445
1446SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1447 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1448 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 3));
1449 return DAG.getNode(Opcode: ISD::SELECT_CC, DL: SDLoc(N),
1450 VT: LHS.getValueType(), N1: N->getOperand(Num: 0),
1451 N2: N->getOperand(Num: 1), N3: LHS, N4: RHS, N5: N->getOperand(Num: 4));
1452}
1453
1454SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1455 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1456 EVT InVT = N->getOperand(Num: OpNo).getValueType();
1457 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1458
1459 EVT SVT = getSetCCResultType(VT: InVT);
1460
1461 // If we got back a type that needs to be promoted, this likely means the
1462 // the input type also needs to be promoted. So get the promoted type for
1463 // the input and try the query again.
1464 if (getTypeAction(VT: SVT) == TargetLowering::TypePromoteInteger) {
1465 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
1466 InVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
1467 SVT = getSetCCResultType(VT: InVT);
1468 } else {
1469 // Input type isn't promoted, just use the default promoted type.
1470 SVT = NVT;
1471 }
1472 }
1473
1474 SDLoc dl(N);
1475 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1476 "Vector compare must return a vector result!");
1477
1478 // Get the SETCC result using the canonical SETCC type.
1479 SDValue SetCC;
1480 if (N->isStrictFPOpcode()) {
1481 SDVTList VTs = DAG.getVTList(VTs: {SVT, MVT::Other});
1482 SDValue Opers[] = {N->getOperand(Num: 0), N->getOperand(Num: 1),
1483 N->getOperand(Num: 2), N->getOperand(Num: 3)};
1484 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: VTs, Ops: Opers, Flags: N->getFlags());
1485 // Legalize the chain result - switch anything that used the old chain to
1486 // use the new one.
1487 ReplaceValueWith(From: SDValue(N, 1), To: SetCC.getValue(R: 1));
1488 } else
1489 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: SVT, N1: N->getOperand(Num: 0),
1490 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), Flags: N->getFlags());
1491
1492 // Convert to the expected type.
1493 return DAG.getSExtOrTrunc(Op: SetCC, DL: dl, VT: NVT);
1494}
1495
1496SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
1497 SDLoc DL(N);
1498 SDValue Arg = N->getOperand(Num: 0);
1499 SDValue Test = N->getOperand(Num: 1);
1500 EVT NResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1501 return DAG.getNode(Opcode: ISD::IS_FPCLASS, DL, VT: NResVT, N1: Arg, N2: Test);
1502}
1503
1504SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
1505 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1506 EVT VT = N->getValueType(ResNo: 0);
1507
1508 SDLoc dl(N);
1509 SDValue Res =
1510 DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: NVT), N: N->getOperand(Num: 0));
1511
1512 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1513 return Res.getValue(R: 1);
1514}
1515
1516SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1517 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1518 SDValue RHS = N->getOperand(Num: 1);
1519 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1520 RHS = ZExtPromotedInteger(Op: RHS);
1521 if (N->getOpcode() != ISD::VP_SHL)
1522 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1523
1524 SDValue Mask = N->getOperand(Num: 2);
1525 SDValue EVL = N->getOperand(Num: 3);
1526 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1527 N3: Mask, N4: EVL);
1528}
1529
1530SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1531 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
1532 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: SDLoc(N),
1533 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
1534}
1535
1536SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1537 // The input may have strange things in the top bits of the registers, but
1538 // these operations don't care. They may have weird bits going out, but
1539 // that too is okay if they are integer operations.
1540 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1541 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1542 if (N->getNumOperands() == 2)
1543 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1544 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1545 assert(N->isVPOpcode() && "Expected VP opcode");
1546 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1547 N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
1548}
1549
1550SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1551 // Sign extend the input.
1552 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1553 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1554 if (N->getNumOperands() == 2)
1555 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1556 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1557 assert(N->isVPOpcode() && "Expected VP opcode");
1558 SDValue Mask = N->getOperand(Num: 2);
1559 SDValue EVL = N->getOperand(Num: 3);
1560 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1561 N3: Mask, N4: EVL);
1562}
1563
1564SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1565 // Zero extend the input.
1566 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1567 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1568 if (N->getNumOperands() == 2)
1569 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1570 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1571 assert(N->isVPOpcode() && "Expected VP opcode");
1572 // Zero extend the input.
1573 SDValue Mask = N->getOperand(Num: 2);
1574 SDValue EVL = N->getOperand(Num: 3);
1575 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1576 N3: Mask, N4: EVL);
1577}
1578
1579SDValue DAGTypeLegalizer::PromoteIntRes_ZExtMaskedIntBinOp(SDNode *N) {
1580 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1581 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1582 SDValue Mask = N->getOperand(Num: 2);
1583 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1584 N3: Mask);
1585}
1586
1587SDValue DAGTypeLegalizer::PromoteIntRes_SExtMaskedIntBinOp(SDNode *N) {
1588 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1589 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1590 SDValue Mask = N->getOperand(Num: 2);
1591 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1592 N3: Mask);
1593}
1594
1595SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1596 SDValue LHS = N->getOperand(Num: 0);
1597 SDValue RHS = N->getOperand(Num: 1);
1598
1599 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1600 // whatever is best for the target and the promoted operands.
1601 SExtOrZExtPromotedOperands(LHS, RHS);
1602
1603 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N),
1604 VT: LHS.getValueType(), N1: LHS, N2: RHS);
1605}
1606
1607SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1608 // The input value must be properly sign extended.
1609 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1610 SDValue RHS = N->getOperand(Num: 1);
1611 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1612 RHS = ZExtPromotedInteger(Op: RHS);
1613 if (N->getOpcode() != ISD::VP_SRA)
1614 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1615
1616 SDValue Mask = N->getOperand(Num: 2);
1617 SDValue EVL = N->getOperand(Num: 3);
1618 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1619 N3: Mask, N4: EVL);
1620}
1621
1622SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1623 SDValue RHS = N->getOperand(Num: 1);
1624 // The input value must be properly zero extended.
1625 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1626 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1627 RHS = ZExtPromotedInteger(Op: RHS);
1628 if (N->getOpcode() != ISD::VP_SRL)
1629 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1630
1631 SDValue Mask = N->getOperand(Num: 2);
1632 SDValue EVL = N->getOperand(Num: 3);
1633 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1634 N3: Mask, N4: EVL);
1635}
1636
1637SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1638 // Lower the rotate to shifts and ORs which can be promoted.
1639 SDValue Res = TLI.expandROT(N, AllowVectorOps: true /*AllowVectorOps*/, DAG);
1640 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1641 return SDValue();
1642}
1643
1644SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1645 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1646 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1647 SDValue Amt = N->getOperand(Num: 2);
1648 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1649 Amt = ZExtPromotedInteger(Op: Amt);
1650 EVT AmtVT = Amt.getValueType();
1651
1652 SDLoc DL(N);
1653 EVT OldVT = N->getOperand(Num: 0).getValueType();
1654 EVT VT = Lo.getValueType();
1655 unsigned Opcode = N->getOpcode();
1656 bool IsFSHR = Opcode == ISD::FSHR;
1657 unsigned OldBits = OldVT.getScalarSizeInBits();
1658 unsigned NewBits = VT.getScalarSizeInBits();
1659
1660 // Amount has to be interpreted modulo the old bit width.
1661 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1662 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1663
1664 // If the promoted type is twice the size (or more), then we use the
1665 // traditional funnel 'double' shift codegen. This isn't necessary if the
1666 // shift amount is constant.
1667 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1668 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1669 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1670 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1671 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1672 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: HiShift);
1673 Lo = DAG.getZeroExtendInReg(Op: Lo, DL, VT: OldVT);
1674 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1675 Res = DAG.getNode(Opcode: IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1676 if (!IsFSHR)
1677 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1678 return Res;
1679 }
1680
1681 // Shift Lo up to occupy the upper bits of the promoted type.
1682 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Lo,
1683 N2: DAG.getShiftAmountConstant(Val: NewBits - OldBits, VT, DL));
1684
1685 // Increase Amount to shift the result into the lower bits of the promoted
1686 // type.
1687 if (IsFSHR)
1688 Amt = DAG.getNode(Opcode: ISD::ADD, DL, VT: AmtVT, N1: Amt,
1689 N2: DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT));
1690
1691 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt);
1692}
1693
1694// A vp version of PromoteIntRes_FunnelShift.
1695SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
1696 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1697 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1698 SDValue Amt = N->getOperand(Num: 2);
1699 SDValue Mask = N->getOperand(Num: 3);
1700 SDValue EVL = N->getOperand(Num: 4);
1701 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1702 Amt = ZExtPromotedInteger(Op: Amt);
1703 EVT AmtVT = Amt.getValueType();
1704
1705 SDLoc DL(N);
1706 EVT OldVT = N->getOperand(Num: 0).getValueType();
1707 EVT VT = Lo.getValueType();
1708 unsigned Opcode = N->getOpcode();
1709 bool IsFSHR = Opcode == ISD::VP_FSHR;
1710 unsigned OldBits = OldVT.getScalarSizeInBits();
1711 unsigned NewBits = VT.getScalarSizeInBits();
1712
1713 // Amount has to be interpreted modulo the old bit width.
1714 Amt = DAG.getNode(Opcode: ISD::VP_UREM, DL, VT: AmtVT, N1: Amt,
1715 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT), N3: Mask, N4: EVL);
1716
1717 // If the promoted type is twice the size (or more), then we use the
1718 // traditional funnel 'double' shift codegen. This isn't necessary if the
1719 // shift amount is constant.
1720 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1721 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1722 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1723 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1724 SDValue HiShift = DAG.getConstant(Val: OldBits, DL, VT);
1725 Hi = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Hi, N2: HiShift, N3: Mask, N4: EVL);
1726 Lo = DAG.getVPZeroExtendInReg(Op: Lo, Mask, EVL, DL, VT: OldVT);
1727 SDValue Res = DAG.getNode(Opcode: ISD::VP_OR, DL, VT, N1: Hi, N2: Lo, N3: Mask, N4: EVL);
1728 Res = DAG.getNode(Opcode: IsFSHR ? ISD::VP_SRL : ISD::VP_SHL, DL, VT, N1: Res, N2: Amt,
1729 N3: Mask, N4: EVL);
1730 if (!IsFSHR)
1731 Res = DAG.getNode(Opcode: ISD::VP_SRL, DL, VT, N1: Res, N2: HiShift, N3: Mask, N4: EVL);
1732 return Res;
1733 }
1734
1735 // Shift Lo up to occupy the upper bits of the promoted type.
1736 SDValue ShiftOffset = DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT);
1737 Lo = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Lo, N2: ShiftOffset, N3: Mask, N4: EVL);
1738
1739 // Increase Amount to shift the result into the lower bits of the promoted
1740 // type.
1741 if (IsFSHR)
1742 Amt = DAG.getNode(Opcode: ISD::VP_ADD, DL, VT: AmtVT, N1: Amt, N2: ShiftOffset, N3: Mask, N4: EVL);
1743
1744 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt, N4: Mask, N5: EVL);
1745}
1746
1747SDValue DAGTypeLegalizer::PromoteIntRes_CLMUL(SDNode *N) {
1748 unsigned Opcode = N->getOpcode();
1749
1750 SDLoc DL(N);
1751 EVT OldVT = N->getOperand(Num: 0).getValueType();
1752 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1753
1754 if (Opcode == ISD::CLMUL) {
1755 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CLMUL, VT)) {
1756 if (SDValue Res = TLI.expandCLMUL(N, DAG))
1757 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1758 }
1759 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1760 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1761 return DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1762 }
1763
1764 SDValue X = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1765 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1766
1767 unsigned OldBits = OldVT.getScalarSizeInBits();
1768 unsigned NewBits = VT.getScalarSizeInBits();
1769 if (NewBits < 2 * OldBits) {
1770 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1771 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1772 SDValue Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1773 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1774 SDValue Clmulh = DAG.getNode(Opcode: ISD::CLMULH, DL, VT, N1: X, N2: Y);
1775 ShAmt = Opcode == ISD::CLMULH ? NewBits - OldBits : NewBits - OldBits + 1;
1776 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Clmulh,
1777 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1778 return DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Lo, N2: Hi);
1779 }
1780
1781 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1782 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1783 return DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1784 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1785}
1786
1787SDValue DAGTypeLegalizer::PromoteIntRes_PEXT(SDNode *N) {
1788 SDLoc DL(N);
1789 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1790 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::PEXT, VT)) {
1791 if (SDValue Res = TLI.expandPEXT(N, DAG))
1792 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1793 }
1794 // Only the mask operand needs zero-extension because the implicit AND from
1795 // masking clears the corresponding bits in X anyway.
1796 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1797 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1798 return DAG.getNode(Opcode: ISD::PEXT, DL, VT, N1: X, N2: Y);
1799}
1800
1801SDValue DAGTypeLegalizer::PromoteIntRes_PDEP(SDNode *N) {
1802 SDLoc DL(N);
1803 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1804 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::PDEP, VT)) {
1805 if (SDValue Res = TLI.expandPDEP(N, DAG))
1806 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1807 }
1808 // Neither operand needs zero-extension because the upper operand bits could
1809 // only result in depositing result bits that will be discarded.
1810 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1811 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1812 return DAG.getNode(Opcode: ISD::PDEP, DL, VT, N1: X, N2: Y);
1813}
1814
1815SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1816 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1817 SDValue Res;
1818 SDValue InOp = N->getOperand(Num: 0);
1819 SDLoc dl(N);
1820
1821 switch (getTypeAction(VT: InOp.getValueType())) {
1822 default: llvm_unreachable("Unknown type action!");
1823 case TargetLowering::TypeLegal:
1824 case TargetLowering::TypeExpandInteger:
1825 Res = InOp;
1826 break;
1827 case TargetLowering::TypePromoteInteger:
1828 Res = GetPromotedInteger(Op: InOp);
1829 break;
1830 case TargetLowering::TypeSplitVector: {
1831 EVT InVT = InOp.getValueType();
1832 assert(InVT.isVector() && "Cannot split scalar types");
1833 ElementCount NumElts = InVT.getVectorElementCount();
1834 assert(NumElts == NVT.getVectorElementCount() &&
1835 "Dst and Src must have the same number of elements");
1836 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1837 "Promoted vector type must be a power of two");
1838
1839 SDValue EOp1, EOp2;
1840 GetSplitVector(Op: InOp, Lo&: EOp1, Hi&: EOp2);
1841
1842 EVT HalfNVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getScalarType(),
1843 EC: NumElts.divideCoefficientBy(RHS: 2));
1844 if (N->getOpcode() == ISD::TRUNCATE) {
1845 EOp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp1);
1846 EOp2 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp2);
1847 } else {
1848 assert(N->getOpcode() == ISD::VP_TRUNCATE &&
1849 "Expected VP_TRUNCATE opcode");
1850 SDValue MaskLo, MaskHi, EVLLo, EVLHi;
1851 std::tie(args&: MaskLo, args&: MaskHi) = SplitMask(Mask: N->getOperand(Num: 1));
1852 std::tie(args&: EVLLo, args&: EVLHi) =
1853 DAG.SplitEVL(N: N->getOperand(Num: 2), VecVT: N->getValueType(ResNo: 0), DL: dl);
1854 EOp1 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp1, N2: MaskLo, N3: EVLLo);
1855 EOp2 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp2, N2: MaskHi, N3: EVLHi);
1856 }
1857 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl, VT: NVT, N1: EOp1, N2: EOp2);
1858 }
1859 // TODO: VP_TRUNCATE need to handle when TypeWidenVector access to some
1860 // targets.
1861 case TargetLowering::TypeWidenVector: {
1862 SDValue WideInOp = GetWidenedVector(Op: InOp);
1863
1864 // Truncate widened InOp.
1865 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1866 EVT TruncVT = EVT::getVectorVT(Context&: *DAG.getContext(),
1867 VT: N->getValueType(ResNo: 0).getScalarType(), NumElements: NumElem);
1868 SDValue WideTrunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: TruncVT, Operand: WideInOp);
1869
1870 // Zero extend so that the elements are of same type as those of NVT
1871 EVT ExtVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getVectorElementType(),
1872 NumElements: NumElem);
1873 SDValue WideExt = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: ExtVT, Operand: WideTrunc);
1874
1875 // Extract the low NVT subvector.
1876 SDValue ZeroIdx = DAG.getVectorIdxConstant(Val: 0, DL: dl);
1877 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NVT, N1: WideExt, N2: ZeroIdx);
1878 }
1879 }
1880
1881 // Truncate to NVT instead of VT
1882 if (N->getOpcode() == ISD::VP_TRUNCATE)
1883 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: NVT, N1: Res, N2: N->getOperand(Num: 1),
1884 N3: N->getOperand(Num: 2));
1885 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Res);
1886}
1887
1888SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1889 if (ResNo == 1)
1890 return PromoteIntRes_Overflow(N);
1891
1892 // The operation overflowed iff the result in the larger type is not the
1893 // zero extension of its truncation to the original type.
1894 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1895 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1896 EVT OVT = N->getOperand(Num: 0).getValueType();
1897 EVT NVT = LHS.getValueType();
1898 SDLoc dl(N);
1899
1900 // Do the arithmetic in the larger type.
1901 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1902 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1903
1904 // Calculate the overflow flag: zero extend the arithmetic result from
1905 // the original type.
1906 SDValue Ofl = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: OVT);
1907 // Overflowed if and only if this is not equal to Res.
1908 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1909
1910 // Use the calculated overflow everywhere.
1911 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1912
1913 return Res;
1914}
1915
1916// Handle promotion for the ADDE/SUBE/UADDO_CARRY/USUBO_CARRY nodes. Notice that
1917// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1918// the UADDO_CARRY/USUBO_CARRY nodes in that the third operand is carry Boolean.
1919SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO_CARRY(SDNode *N,
1920 unsigned ResNo) {
1921 if (ResNo == 1)
1922 return PromoteIntRes_Overflow(N);
1923
1924 // We need to sign-extend the operands so the carry value computed by the
1925 // wide operation will be equivalent to the carry value computed by the
1926 // narrow operation.
1927 // An UADDO_CARRY can generate carry only if any of the operands has its
1928 // most significant bit set. Sign extension propagates the most significant
1929 // bit into the higher bits which means the extra bit that the narrow
1930 // addition would need (i.e. the carry) will be propagated through the higher
1931 // bits of the wide addition.
1932 // A USUBO_CARRY can generate borrow only if LHS < RHS and this property will
1933 // be preserved by sign extension.
1934 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1935 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1936
1937 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(ResNo: 1)};
1938
1939 // Do the arithmetic in the wide type.
1940 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VTList: DAG.getVTList(VTs: ValueVTs),
1941 N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
1942
1943 // Update the users of the original carry/borrow value.
1944 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1945
1946 return SDValue(Res.getNode(), 0);
1947}
1948
1949SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1950 unsigned ResNo) {
1951 assert(ResNo == 1 && "Don't know how to promote other results yet.");
1952 return PromoteIntRes_Overflow(N);
1953}
1954
1955SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1956 EVT OVT = N->getValueType(ResNo: 0);
1957 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1958
1959 // If a larger ABS or SMAX isn't supported by the target, try to expand now.
1960 // If we expand later we'll end up sign extending more than just the sra input
1961 // in sra+xor+sub expansion.
1962 if (!OVT.isVector() &&
1963 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS, VT: NVT) &&
1964 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS_MIN_POISON, VT: NVT) &&
1965 !TLI.isOperationLegal(Op: ISD::SMAX, VT: NVT)) {
1966 if (SDValue Res = TLI.expandABS(N, DAG))
1967 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Res);
1968 }
1969
1970 SDValue Op0 = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1971 return DAG.getNode(Opcode: ISD::ABS_MIN_POISON, DL: SDLoc(N), VT: Op0.getValueType(), Operand: Op0);
1972}
1973
1974SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1975 // Promote the overflow bit trivially.
1976 if (ResNo == 1)
1977 return PromoteIntRes_Overflow(N);
1978
1979 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
1980 SDLoc DL(N);
1981 EVT SmallVT = LHS.getValueType();
1982
1983 // To determine if the result overflowed in a larger type, we extend the
1984 // input to the larger type, do the multiply (checking if it overflows),
1985 // then also check the high bits of the result to see if overflow happened
1986 // there.
1987 if (N->getOpcode() == ISD::SMULO) {
1988 LHS = SExtPromotedInteger(Op: LHS);
1989 RHS = SExtPromotedInteger(Op: RHS);
1990 } else {
1991 LHS = ZExtPromotedInteger(Op: LHS);
1992 RHS = ZExtPromotedInteger(Op: RHS);
1993 }
1994 SDVTList VTs = DAG.getVTList(VT1: LHS.getValueType(), VT2: N->getValueType(ResNo: 1));
1995 SDValue Mul = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N1: LHS, N2: RHS);
1996
1997 // Overflow occurred if it occurred in the larger type, or if the high part
1998 // of the result does not zero/sign-extend the low part. Check this second
1999 // possibility first.
2000 SDValue Overflow;
2001 if (N->getOpcode() == ISD::UMULO) {
2002 // Unsigned overflow occurred if the high part is non-zero.
2003 unsigned Shift = SmallVT.getScalarSizeInBits();
2004 SDValue Hi =
2005 DAG.getNode(Opcode: ISD::SRL, DL, VT: Mul.getValueType(), N1: Mul,
2006 N2: DAG.getShiftAmountConstant(Val: Shift, VT: Mul.getValueType(), DL));
2007 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: Hi,
2008 RHS: DAG.getConstant(Val: 0, DL, VT: Hi.getValueType()),
2009 Cond: ISD::SETNE);
2010 } else {
2011 // Signed overflow occurred if the high part does not sign extend the low.
2012 SDValue SExt = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: Mul.getValueType(),
2013 N1: Mul, N2: DAG.getValueType(SmallVT));
2014 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: SExt, RHS: Mul, Cond: ISD::SETNE);
2015 }
2016
2017 // The only other way for overflow to occur is if the multiplication in the
2018 // larger type itself overflowed.
2019 Overflow = DAG.getNode(Opcode: ISD::OR, DL, VT: N->getValueType(ResNo: 1), N1: Overflow,
2020 N2: SDValue(Mul.getNode(), 1));
2021
2022 // Use the calculated overflow everywhere.
2023 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
2024 return Mul;
2025}
2026
2027SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
2028 return DAG.getUNDEF(VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
2029 VT: N->getValueType(ResNo: 0)));
2030}
2031
2032SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
2033 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
2034
2035 const APInt &MulImm = N->getConstantOperandAPInt(Num: 0);
2036 return DAG.getVScale(DL: SDLoc(N), VT, MulImm: MulImm.sext(width: VT.getSizeInBits()));
2037}
2038
2039SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
2040 SDValue Chain = N->getOperand(Num: 0); // Get the chain.
2041 SDValue Ptr = N->getOperand(Num: 1); // Get the pointer.
2042 EVT VT = N->getValueType(ResNo: 0);
2043 SDLoc dl(N);
2044
2045 MVT RegVT = TLI.getRegisterType(Context&: *DAG.getContext(), VT);
2046 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
2047 // The argument is passed as NumRegs registers of type RegVT.
2048
2049 SmallVector<SDValue, 8> Parts(NumRegs);
2050 for (unsigned i = 0; i < NumRegs; ++i) {
2051 Parts[i] = DAG.getVAArg(VT: RegVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2),
2052 Align: N->getConstantOperandVal(Num: 3));
2053 Chain = Parts[i].getValue(R: 1);
2054 }
2055
2056 // Handle endianness of the load.
2057 if (DAG.getDataLayout().isBigEndian())
2058 std::reverse(first: Parts.begin(), last: Parts.end());
2059
2060 // Assemble the parts in the promoted type.
2061 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
2062 SDValue Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[0]);
2063 for (unsigned i = 1; i < NumRegs; ++i) {
2064 SDValue Part = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[i]);
2065 // Shift it to the right position and "or" it in.
2066 Part = DAG.getNode(
2067 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Part,
2068 N2: DAG.getShiftAmountConstant(Val: i * RegVT.getSizeInBits(), VT: NVT, DL: dl));
2069 Res = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Res, N2: Part);
2070 }
2071
2072 // Modified the chain result - switch anything that used the old chain to
2073 // use the new one.
2074 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
2075
2076 return Res;
2077}
2078
2079//===----------------------------------------------------------------------===//
2080// Integer Operand Promotion
2081//===----------------------------------------------------------------------===//
2082
2083/// PromoteIntegerOperand - This method is called when the specified operand of
2084/// the specified node is found to need promotion. At this point, all of the
2085/// result types of the node are known to be legal, but other operands of the
2086/// node may need promotion or expansion as well as the specified one.
2087bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
2088 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG));
2089 SDValue Res = SDValue();
2090 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false)) {
2091 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
2092 return false;
2093 }
2094
2095 switch (N->getOpcode()) {
2096 default:
2097 #ifndef NDEBUG
2098 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
2099 N->dump(&DAG); dbgs() << "\n";
2100 #endif
2101 report_fatal_error(reason: "Do not know how to promote this operator's operand!");
2102
2103 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
2104 case ISD::ANY_EXTEND_VECTOR_INREG:
2105 Res = PromoteIntOp_ANY_EXTEND_VECTOR_INREG(N);
2106 break;
2107 case ISD::ATOMIC_STORE:
2108 Res = PromoteIntOp_ATOMIC_STORE(N: cast<AtomicSDNode>(Val: N));
2109 break;
2110 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
2111 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
2112 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
2113 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
2114 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
2115 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
2116 case ISD::COND_LOOP:
2117 Res = PromoteIntOp_COND_LOOP(N, OpNo);
2118 break;
2119 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
2120 case ISD::FAKE_USE:
2121 Res = PromoteIntOp_FAKE_USE(N);
2122 break;
2123 case ISD::INSERT_VECTOR_ELT:
2124 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
2125 break;
2126 case ISD::SPLAT_VECTOR:
2127 case ISD::SCALAR_TO_VECTOR:
2128 Res = PromoteIntOp_ScalarOp(N);
2129 break;
2130 case ISD::VSELECT:
2131 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
2132 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
2133 case ISD::VP_SETCC:
2134 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
2135 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
2136 case ISD::VP_SIGN_EXTEND: Res = PromoteIntOp_VP_SIGN_EXTEND(N); break;
2137 case ISD::VP_SINT_TO_FP:
2138 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
2139 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
2140 case ISD::STORE: Res = PromoteIntOp_STORE(N: cast<StoreSDNode>(Val: N),
2141 OpNo); break;
2142 case ISD::VP_STORE:
2143 Res = PromoteIntOp_VP_STORE(N: cast<VPStoreSDNode>(Val: N), OpNo);
2144 break;
2145 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(N: cast<MaskedStoreSDNode>(Val: N),
2146 OpNo); break;
2147 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(N: cast<MaskedLoadSDNode>(Val: N),
2148 OpNo); break;
2149 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(N: cast<MaskedGatherSDNode>(Val: N),
2150 OpNo); break;
2151 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(N: cast<MaskedScatterSDNode>(Val: N),
2152 OpNo); break;
2153 case ISD::VECTOR_COMPRESS:
2154 Res = PromoteIntOp_VECTOR_COMPRESS(N, OpNo);
2155 break;
2156 case ISD::VP_TRUNCATE:
2157 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
2158 case ISD::BF16_TO_FP:
2159 case ISD::FP16_TO_FP:
2160 case ISD::VP_UINT_TO_FP:
2161 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
2162 case ISD::CONVERT_FROM_ARBITRARY_FP:
2163 Res = PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(N);
2164 break;
2165 case ISD::STRICT_FP16_TO_FP:
2166 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
2167 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
2168 case ISD::VP_ZERO_EXTEND: Res = PromoteIntOp_VP_ZERO_EXTEND(N); break;
2169 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
2170 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
2171
2172 case ISD::SHL:
2173 case ISD::SRA:
2174 case ISD::SRL:
2175 case ISD::ROTL:
2176 case ISD::ROTR:
2177 case ISD::SSHLSAT:
2178 case ISD::USHLSAT:
2179 Res = PromoteIntOp_Shift(N);
2180 break;
2181
2182 case ISD::SCMP:
2183 case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
2184
2185 case ISD::FSHL:
2186 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
2187
2188 case ISD::FRAMEADDR:
2189 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
2190
2191 case ISD::SMULFIX:
2192 case ISD::SMULFIXSAT:
2193 case ISD::UMULFIX:
2194 case ISD::UMULFIXSAT:
2195 case ISD::SDIVFIX:
2196 case ISD::SDIVFIXSAT:
2197 case ISD::UDIVFIX:
2198 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
2199 case ISD::FPOWI:
2200 case ISD::STRICT_FPOWI:
2201 case ISD::FLDEXP:
2202 case ISD::STRICT_FLDEXP: Res = PromoteIntOp_ExpOp(N); break;
2203 case ISD::VECREDUCE_ADD:
2204 case ISD::VECREDUCE_MUL:
2205 case ISD::VECREDUCE_AND:
2206 case ISD::VECREDUCE_OR:
2207 case ISD::VECREDUCE_XOR:
2208 case ISD::VECREDUCE_SMAX:
2209 case ISD::VECREDUCE_SMIN:
2210 case ISD::VECREDUCE_UMAX:
2211 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
2212 case ISD::VP_REDUCE_ADD:
2213 case ISD::VP_REDUCE_MUL:
2214 case ISD::VP_REDUCE_AND:
2215 case ISD::VP_REDUCE_OR:
2216 case ISD::VP_REDUCE_XOR:
2217 case ISD::VP_REDUCE_SMAX:
2218 case ISD::VP_REDUCE_SMIN:
2219 case ISD::VP_REDUCE_UMAX:
2220 case ISD::VP_REDUCE_UMIN:
2221 Res = PromoteIntOp_VP_REDUCE(N, OpNo);
2222 break;
2223
2224 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
2225 case ISD::STACKMAP:
2226 Res = PromoteIntOp_STACKMAP(N, OpNo);
2227 break;
2228 case ISD::PATCHPOINT:
2229 Res = PromoteIntOp_PATCHPOINT(N, OpNo);
2230 break;
2231 case ISD::WRITE_REGISTER:
2232 Res = PromoteIntOp_WRITE_REGISTER(N, OpNo);
2233 break;
2234 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
2235 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
2236 Res = PromoteIntOp_VP_STRIDED(N, OpNo);
2237 break;
2238 case ISD::EXPERIMENTAL_VP_SPLICE:
2239 Res = PromoteIntOp_VP_SPLICE(N, OpNo);
2240 break;
2241 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
2242 Res = PromoteIntOp_VECTOR_HISTOGRAM(N, OpNo);
2243 break;
2244 case ISD::VECTOR_FIND_LAST_ACTIVE:
2245 case ISD::CTTZ_ELTS:
2246 case ISD::CTTZ_ELTS_ZERO_POISON:
2247 Res = PromoteIntOp_UnaryBooleanVectorOp(N, OpNo);
2248 break;
2249 case ISD::GET_ACTIVE_LANE_MASK:
2250 Res = PromoteIntOp_GET_ACTIVE_LANE_MASK(N);
2251 break;
2252 case ISD::MASKED_UDIV:
2253 case ISD::MASKED_SDIV:
2254 case ISD::MASKED_UREM:
2255 case ISD::MASKED_SREM:
2256 Res = PromoteIntOp_MaskedBinOp(N, OpNo);
2257 break;
2258 case ISD::PARTIAL_REDUCE_UMLA:
2259 case ISD::PARTIAL_REDUCE_SMLA:
2260 case ISD::PARTIAL_REDUCE_SUMLA:
2261 Res = PromoteIntOp_PARTIAL_REDUCE_MLA(N);
2262 break;
2263 case ISD::LOOP_DEPENDENCE_RAW_MASK:
2264 case ISD::LOOP_DEPENDENCE_WAR_MASK:
2265 Res = PromoteIntOp_LOOP_DEPENDENCE_MASK(N);
2266 break;
2267 }
2268
2269 // If the result is null, the sub-method took care of registering results etc.
2270 if (!Res.getNode()) return false;
2271
2272 // If the result is N, the sub-method updated N in place. Tell the legalizer
2273 // core about this.
2274 if (Res.getNode() == N)
2275 return true;
2276
2277 const bool IsStrictFp = N->isStrictFPOpcode();
2278 assert(Res.getValueType() == N->getValueType(0) &&
2279 N->getNumValues() == (IsStrictFp ? 2 : 1) &&
2280 "Invalid operand expansion");
2281 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
2282 Res.dump());
2283
2284 ReplaceValueWith(From: SDValue(N, 0), To: Res);
2285 if (IsStrictFp)
2286 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res.getNode(), 1));
2287
2288 return false;
2289}
2290
2291// These operands can be either sign extended or zero extended as long as we
2292// treat them the same. If an extension is free, choose that. Otherwise, follow
2293// target preference.
2294void DAGTypeLegalizer::SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS) {
2295 SDValue OpL = GetPromotedInteger(Op: LHS);
2296 SDValue OpR = GetPromotedInteger(Op: RHS);
2297
2298 if (TLI.isSExtCheaperThanZExt(FromTy: LHS.getValueType(), ToTy: OpL.getValueType())) {
2299 // The target would prefer to promote the comparison operand with sign
2300 // extension. Honor that unless the promoted values are already zero
2301 // extended.
2302 unsigned OpLEffectiveBits =
2303 DAG.computeKnownBits(Op: OpL).countMaxActiveBits();
2304 unsigned OpREffectiveBits =
2305 DAG.computeKnownBits(Op: OpR).countMaxActiveBits();
2306 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2307 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2308 LHS = OpL;
2309 RHS = OpR;
2310 return;
2311 }
2312
2313 // The promoted values aren't zero extended, use a sext_inreg.
2314 LHS = SExtPromotedInteger(Op: LHS);
2315 RHS = SExtPromotedInteger(Op: RHS);
2316 return;
2317 }
2318
2319 // Prefer to promote the comparison operand with zero extension.
2320
2321 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
2322 // than the width of LHS/RHS, we can avoid inserting a zext_inreg operation
2323 // that we might not be able to remove.
2324 unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpL);
2325 unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpR);
2326 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2327 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2328 LHS = OpL;
2329 RHS = OpR;
2330 return;
2331 }
2332
2333 // Otherwise, use zext_inreg.
2334 LHS = ZExtPromotedInteger(Op: LHS);
2335 RHS = ZExtPromotedInteger(Op: RHS);
2336}
2337
2338/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
2339/// shared among BR_CC, SELECT_CC, and SETCC handlers.
2340void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
2341 ISD::CondCode CCCode) {
2342 // We have to insert explicit sign or zero extends. Note that we could
2343 // insert sign extends for ALL conditions. For those operations where either
2344 // zero or sign extension would be valid, we ask the target which extension
2345 // it would prefer.
2346
2347 // Signed comparisons always require sign extension.
2348 if (ISD::isSignedIntSetCC(Code: CCCode)) {
2349 LHS = SExtPromotedInteger(Op: LHS);
2350 RHS = SExtPromotedInteger(Op: RHS);
2351 return;
2352 }
2353
2354 assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
2355 "Unknown integer comparison!");
2356
2357 SExtOrZExtPromotedOperands(LHS, RHS);
2358}
2359
2360SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
2361 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2362 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2363}
2364
2365SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND_VECTOR_INREG(SDNode *N) {
2366 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2367 EVT ResVT = N->getValueType(ResNo: 0);
2368 EVT OpVT = Op.getValueType();
2369 EVT NewVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: OpVT.getScalarType(),
2370 NumElements: ResVT.getVectorNumElements());
2371 Op = DAG.getExtractSubvector(DL: SDLoc(Op), VT: NewVT, Vec: Op, Idx: 0);
2372 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: ResVT, Operand: Op);
2373}
2374
2375SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
2376 SDValue Op1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
2377 return DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(),
2378 Chain: N->getChain(), Ptr: Op1, Val: N->getBasePtr(), MMO: N->getMemOperand());
2379}
2380
2381SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
2382 EVT OutVT = N->getValueType(ResNo: 0);
2383 SDValue InOp = N->getOperand(Num: 0);
2384 EVT InVT = InOp.getValueType();
2385 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
2386 SDLoc dl(N);
2387
2388 switch (getTypeAction(VT: InVT)) {
2389 case TargetLowering::TypePromoteInteger: {
2390 // TODO: Handle big endian & vector input type.
2391 if (OutVT.isVector() && !InVT.isVector() &&
2392 DAG.getDataLayout().isLittleEndian()) {
2393 EVT EltVT = OutVT.getVectorElementType();
2394 TypeSize EltSize = EltVT.getSizeInBits();
2395 TypeSize NInSize = NInVT.getSizeInBits();
2396
2397 if (NInSize.hasKnownScalarFactor(RHS: EltSize)) {
2398 unsigned NumEltsWithPadding = NInSize.getKnownScalarFactor(RHS: EltSize);
2399 EVT WideVecVT =
2400 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
2401
2402 if (isTypeLegal(VT: WideVecVT)) {
2403 SDValue Promoted = GetPromotedInteger(Op: InOp);
2404 SDValue Cast = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: WideVecVT, Operand: Promoted);
2405 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Cast,
2406 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
2407 }
2408 }
2409 }
2410
2411 break;
2412 }
2413 default:
2414 break;
2415 }
2416
2417 // This should only occur in unusual situations like bitcasting to an
2418 // x86_fp80, so just turn it into a store+load
2419 return CreateStackStoreLoad(Op: InOp, DestVT: OutVT);
2420}
2421
2422SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
2423 assert(OpNo == 2 && "Don't know how to promote this operand!");
2424
2425 SDValue LHS = N->getOperand(Num: 2);
2426 SDValue RHS = N->getOperand(Num: 3);
2427 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get());
2428
2429 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
2430 // legal types.
2431 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2432 Op2: N->getOperand(Num: 1), Op3: LHS, Op4: RHS, Op5: N->getOperand(Num: 4)),
2433 0);
2434}
2435
2436SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
2437 assert(OpNo == 1 && "only know how to promote condition");
2438
2439 // Promote all the way up to the canonical SetCC type.
2440 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2441
2442 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
2443 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond,
2444 Op3: N->getOperand(Num: 2)), 0);
2445}
2446
2447SDValue DAGTypeLegalizer::PromoteIntOp_COND_LOOP(SDNode *N, unsigned OpNo) {
2448 assert(OpNo == 1 && "only know how to promote condition");
2449
2450 // Promote all the way up to the canonical SetCC type.
2451 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2452
2453 // The chain (Op#0) is always a legal type.
2454 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond), 0);
2455}
2456
2457SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
2458 // Since the result type is legal, the operands must promote to it.
2459 EVT OVT = N->getOperand(Num: 0).getValueType();
2460 SDValue Lo = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2461 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 1));
2462 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
2463 SDLoc dl(N);
2464
2465 Hi = DAG.getNode(
2466 Opcode: ISD::SHL, DL: dl, VT: N->getValueType(ResNo: 0), N1: Hi,
2467 N2: DAG.getShiftAmountConstant(Val: OVT.getSizeInBits(), VT: N->getValueType(ResNo: 0), DL: dl));
2468 return DAG.getNode(Opcode: ISD::OR, DL: dl, VT: N->getValueType(ResNo: 0), N1: Lo, N2: Hi);
2469}
2470
2471SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
2472 // The vector type is legal but the element type is not. This implies
2473 // that the vector is a power-of-two in length and that the element
2474 // type does not have a strange size (eg: it is not i1).
2475 EVT VecVT = N->getValueType(ResNo: 0);
2476 unsigned NumElts = VecVT.getVectorNumElements();
2477 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
2478 "Legal vector of one illegal element?");
2479
2480 // Promote the inserted value. The type does not need to match the
2481 // vector element type. Check that any extra bits introduced will be
2482 // truncated away.
2483 assert(N->getOperand(0).getValueSizeInBits() >=
2484 N->getValueType(0).getScalarSizeInBits() &&
2485 "Type of inserted value narrower than vector element type!");
2486
2487 SmallVector<SDValue, 16> NewOps;
2488 for (unsigned i = 0; i < NumElts; ++i)
2489 NewOps.push_back(Elt: GetPromotedInteger(Op: N->getOperand(Num: i)));
2490
2491 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2492}
2493
2494SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
2495 unsigned OpNo) {
2496 if (OpNo == 1) {
2497 // Promote the inserted value. This is valid because the type does not
2498 // have to match the vector element type.
2499
2500 // Check that any extra bits introduced will be truncated away.
2501 assert(N->getOperand(1).getValueSizeInBits() >=
2502 N->getValueType(0).getScalarSizeInBits() &&
2503 "Type of inserted value narrower than vector element type!");
2504 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2505 Op2: GetPromotedInteger(Op: N->getOperand(Num: 1)),
2506 Op3: N->getOperand(Num: 2)),
2507 0);
2508 }
2509
2510 assert(OpNo == 2 && "Different operand and result vector types?");
2511
2512 // Promote the index.
2513 SDValue Idx = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 2), DL: SDLoc(N),
2514 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
2515 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2516 Op2: N->getOperand(Num: 1), Op3: Idx), 0);
2517}
2518
2519SDValue DAGTypeLegalizer::PromoteIntOp_ScalarOp(SDNode *N) {
2520 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2521
2522 // Integer SPLAT_VECTOR/SCALAR_TO_VECTOR operands are implicitly truncated,
2523 // so just promote the operand in place.
2524 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2525}
2526
2527SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
2528 assert(OpNo == 0 && "Only know how to promote the condition!");
2529 SDValue Cond = N->getOperand(Num: 0);
2530 EVT OpTy = N->getOperand(Num: 1).getValueType();
2531
2532 if (N->getOpcode() == ISD::VSELECT)
2533 if (SDValue Res = WidenVSELECTMask(N))
2534 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
2535 N1: Res, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2536
2537 // Promote all the way up to the canonical SetCC type.
2538 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
2539 Cond = PromoteTargetBoolean(Bool: Cond, ValVT: OpVT);
2540
2541 return SDValue(DAG.UpdateNodeOperands(N, Op1: Cond, Op2: N->getOperand(Num: 1),
2542 Op3: N->getOperand(Num: 2)), 0);
2543}
2544
2545SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
2546 assert(OpNo == 0 && "Don't know how to promote this operand!");
2547
2548 SDValue LHS = N->getOperand(Num: 0);
2549 SDValue RHS = N->getOperand(Num: 1);
2550 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get());
2551
2552 // The CC (#4) and the possible return values (#2 and #3) have legal types.
2553 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2554 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)), 0);
2555}
2556
2557SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
2558 assert(OpNo == 0 && "Don't know how to promote this operand!");
2559
2560 SDValue LHS = N->getOperand(Num: 0);
2561 SDValue RHS = N->getOperand(Num: 1);
2562 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get());
2563
2564 // The CC (#2) is always legal.
2565 if (N->getOpcode() == ISD::SETCC)
2566 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2)), 0);
2567
2568 assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
2569
2570 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2571 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)),
2572 0);
2573}
2574
2575SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
2576 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2577 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2578}
2579
2580SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
2581 SDValue LHS = N->getOperand(Num: 0);
2582 SDValue RHS = N->getOperand(Num: 1);
2583
2584 if (N->getOpcode() == ISD::SCMP) {
2585 LHS = SExtPromotedInteger(Op: LHS);
2586 RHS = SExtPromotedInteger(Op: RHS);
2587 } else {
2588 SExtOrZExtPromotedOperands(LHS, RHS);
2589 }
2590
2591 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS), 0);
2592}
2593
2594SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
2595 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
2596 Op3: ZExtPromotedInteger(Op: N->getOperand(Num: 2))), 0);
2597}
2598
2599SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
2600 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2601 SDLoc dl(N);
2602 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Op);
2603 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Op.getValueType(),
2604 N1: Op, N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
2605}
2606
2607SDValue DAGTypeLegalizer::PromoteIntOp_VP_SIGN_EXTEND(SDNode *N) {
2608 SDLoc dl(N);
2609 EVT VT = N->getValueType(ResNo: 0);
2610 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2611 // FIXME: There is no VP_ANY_EXTEND yet.
2612 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2613 N3: N->getOperand(Num: 2));
2614 unsigned Diff =
2615 VT.getScalarSizeInBits() - N->getOperand(Num: 0).getScalarValueSizeInBits();
2616 SDValue ShAmt = DAG.getShiftAmountConstant(Val: Diff, VT, DL: dl);
2617 // FIXME: There is no VP_SIGN_EXTEND_INREG so use a pair of shifts.
2618 SDValue Shl = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT, N1: Op, N2: ShAmt, N3: N->getOperand(Num: 1),
2619 N4: N->getOperand(Num: 2));
2620 return DAG.getNode(Opcode: ISD::VP_SRA, DL: dl, VT, N1: Shl, N2: ShAmt, N3: N->getOperand(Num: 1),
2621 N4: N->getOperand(Num: 2));
2622}
2623
2624SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
2625 if (N->getOpcode() == ISD::VP_SINT_TO_FP)
2626 return SDValue(DAG.UpdateNodeOperands(N,
2627 Op1: SExtPromotedInteger(Op: N->getOperand(Num: 0)),
2628 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2629 0);
2630 return SDValue(DAG.UpdateNodeOperands(N,
2631 Op: SExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2632}
2633
2634SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
2635 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2636 Op2: SExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2637}
2638
2639SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
2640 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2641 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
2642 SDLoc dl(N);
2643
2644 SDValue Val = GetPromotedInteger(Op: N->getValue()); // Get promoted value.
2645
2646 // Truncate the value and store the result.
2647 return DAG.getTruncStore(Chain: Ch, dl, Val, Ptr,
2648 SVT: N->getMemoryVT(), MMO: N->getMemOperand());
2649}
2650
2651SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
2652 unsigned OpNo) {
2653
2654 assert(OpNo == 1 && "Unexpected operand for promotion");
2655 assert(!N->isIndexed() && "expecting unindexed vp_store!");
2656
2657 SDValue DataOp = GetPromotedInteger(Op: N->getValue());
2658 return DAG.getTruncStoreVP(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Ptr: N->getBasePtr(),
2659 Mask: N->getMask(), EVL: N->getVectorLength(),
2660 SVT: N->getMemoryVT(), MMO: N->getMemOperand(),
2661 IsCompressing: N->isCompressingStore());
2662}
2663
2664SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
2665 unsigned OpNo) {
2666 SDValue DataOp = N->getValue();
2667 SDValue Mask = N->getMask();
2668
2669 if (OpNo == 4) {
2670 // The Mask. Update in place.
2671 EVT DataVT = DataOp.getValueType();
2672 Mask = PromoteTargetBoolean(Bool: Mask, ValVT: DataVT);
2673 SmallVector<SDValue, 4> NewOps(N->ops());
2674 NewOps[4] = Mask;
2675 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2676 }
2677
2678 assert(OpNo == 1 && "Unexpected operand for promotion");
2679 DataOp = GetPromotedInteger(Op: DataOp);
2680
2681 return DAG.getMaskedStore(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Base: N->getBasePtr(),
2682 Offset: N->getOffset(), Mask, MemVT: N->getMemoryVT(),
2683 MMO: N->getMemOperand(), AM: N->getAddressingMode(),
2684 /*IsTruncating*/ true, IsCompressing: N->isCompressingStore());
2685}
2686
2687SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
2688 unsigned OpNo) {
2689 assert(OpNo == 3 && "Only know how to promote the mask!");
2690 EVT DataVT = N->getValueType(ResNo: 0);
2691 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2692 SmallVector<SDValue, 4> NewOps(N->ops());
2693 NewOps[OpNo] = Mask;
2694 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2695 if (Res == N)
2696 return SDValue(Res, 0);
2697
2698 // Update triggered CSE, do our own replacement since caller can't.
2699 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2700 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2701 return SDValue();
2702}
2703
2704SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
2705 unsigned OpNo) {
2706 SmallVector<SDValue, 5> NewOps(N->ops());
2707
2708 if (OpNo == 2) {
2709 // The Mask
2710 EVT DataVT = N->getValueType(ResNo: 0);
2711 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2712 } else if (OpNo == 4) {
2713 // The Index
2714 if (N->isIndexSigned())
2715 // Need to sign extend the index since the bits will likely be used.
2716 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2717 else
2718 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2719 } else
2720 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2721
2722 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2723 if (Res == N)
2724 return SDValue(Res, 0);
2725
2726 // Update triggered CSE, do our own replacement since caller can't.
2727 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2728 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2729 return SDValue();
2730}
2731
2732SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2733 unsigned OpNo) {
2734 bool TruncateStore = N->isTruncatingStore();
2735 SmallVector<SDValue, 5> NewOps(N->ops());
2736
2737 if (OpNo == 2) {
2738 // The Mask
2739 EVT DataVT = N->getValue().getValueType();
2740 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2741 } else if (OpNo == 4) {
2742 // The Index
2743 if (N->isIndexSigned())
2744 // Need to sign extend the index since the bits will likely be used.
2745 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2746 else
2747 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2748 } else {
2749 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2750 TruncateStore = true;
2751 }
2752
2753 return DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: N->getMemoryVT(),
2754 dl: SDLoc(N), Ops: NewOps, MMO: N->getMemOperand(),
2755 IndexType: N->getIndexType(), IsTruncating: TruncateStore);
2756}
2757
2758SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_COMPRESS(SDNode *N,
2759 unsigned OpNo) {
2760 assert(OpNo == 1 && "Can only promote VECTOR_COMPRESS mask.");
2761 SDValue Vec = N->getOperand(Num: 0);
2762 EVT VT = Vec.getValueType();
2763 SDValue Passthru = N->getOperand(Num: 2);
2764 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: VT);
2765 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT, N1: Vec, N2: Mask, N3: Passthru);
2766}
2767
2768SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2769 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2770 if (N->getOpcode() == ISD::VP_TRUNCATE)
2771 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Op,
2772 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2773 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2774}
2775
2776SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2777 if (N->getOpcode() == ISD::VP_UINT_TO_FP)
2778 return SDValue(DAG.UpdateNodeOperands(N,
2779 Op1: ZExtPromotedInteger(Op: N->getOperand(Num: 0)),
2780 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2781 0);
2782 return SDValue(DAG.UpdateNodeOperands(N,
2783 Op: ZExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2784}
2785
2786SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(SDNode *N) {
2787 return SDValue(DAG.UpdateNodeOperands(N, Op1: GetPromotedInteger(Op: N->getOperand(Num: 0)),
2788 Op2: N->getOperand(Num: 1)),
2789 0);
2790}
2791
2792SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2793 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2794 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2795}
2796
2797SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2798 SDLoc dl(N);
2799 SDValue Src = N->getOperand(Num: 0);
2800 SDValue Op = GetPromotedInteger(Op: Src);
2801 EVT VT = N->getValueType(ResNo: 0);
2802
2803 // If this zext has the nneg flag and the target prefers sext, see if the
2804 // promoted input is already sign extended.
2805 // TODO: Should we have some way to set nneg on ISD::AND instead?
2806 if (N->getFlags().hasNonNeg() && Op.getValueType() == VT &&
2807 TLI.isSExtCheaperThanZExt(FromTy: Src.getValueType(), ToTy: VT)) {
2808 unsigned OpEffectiveBits = DAG.ComputeMaxSignificantBits(Op);
2809 if (OpEffectiveBits <= Src.getScalarValueSizeInBits())
2810 return Op;
2811 }
2812
2813 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Op);
2814 return DAG.getZeroExtendInReg(Op, DL: dl, VT: Src.getValueType());
2815}
2816
2817SDValue DAGTypeLegalizer::PromoteIntOp_VP_ZERO_EXTEND(SDNode *N) {
2818 SDLoc dl(N);
2819 EVT VT = N->getValueType(ResNo: 0);
2820 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2821 // FIXME: There is no VP_ANY_EXTEND yet.
2822 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2823 N3: N->getOperand(Num: 2));
2824 return DAG.getVPZeroExtendInReg(Op, Mask: N->getOperand(Num: 1), EVL: N->getOperand(Num: 2), DL: dl,
2825 VT: N->getOperand(Num: 0).getValueType());
2826}
2827
2828SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2829 SDValue Op2 = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2830 return SDValue(
2831 DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1), Op3: Op2), 0);
2832}
2833
2834SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2835 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2836 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2837 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2838}
2839
2840SDValue DAGTypeLegalizer::PromoteIntOp_ExpOp(SDNode *N) {
2841 bool IsStrict = N->isStrictFPOpcode();
2842 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
2843
2844 bool IsPowI =
2845 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI;
2846 unsigned OpOffset = IsStrict ? 1 : 0;
2847
2848 // The integer operand is the last operand in FPOWI (or FLDEXP) (so the result
2849 // and floating point operand is already type legalized).
2850 RTLIB::Libcall LC = IsPowI ? RTLIB::getPOWI(RetVT: N->getValueType(ResNo: 0))
2851 : RTLIB::getLDEXP(RetVT: N->getValueType(ResNo: 0));
2852
2853 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
2854 if (LCImpl == RTLIB::Unsupported) {
2855 // Scalarize vector FPOWI instead of promoting the type. This allows the
2856 // scalar FPOWIs to be visited and converted to libcalls before promoting
2857 // the type.
2858 // FIXME: This should be done in LegalizeVectorOps/LegalizeDAG, but call
2859 // lowering needs the unpromoted EVT.
2860 if (IsPowI && N->getValueType(ResNo: 0).isVector())
2861 return DAG.UnrollVectorOp(N);
2862 SmallVector<SDValue, 3> NewOps(N->ops());
2863 NewOps[1 + OpOffset] = SExtPromotedInteger(Op: N->getOperand(Num: 1 + OpOffset));
2864 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2865 }
2866
2867 // We can't just promote the exponent type in FPOWI, since we want to lower
2868 // the node to a libcall and we if we promote to a type larger than
2869 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2870 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2871 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2872
2873 // A wider-than-int exponent can't be passed in an int (there's no wider
2874 // libcall), so bail like the soften/expand paths. A narrower one is
2875 // sign-extended to int by the makeLibCall below.
2876 if (N->getOperand(Num: 1 + OpOffset).getScalarValueSizeInBits() >
2877 DAG.getLibInfo().getIntSize()) {
2878 const Function &Fn = DAG.getMachineFunction().getFunction();
2879 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
2880 Twine(IsPowI ? "powi" : "ldexp") +
2881 " exponent does not match sizeof(int)",
2882 Fn, N->getDebugLoc()));
2883 if (IsStrict)
2884 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
2885 ReplaceValueWith(From: SDValue(N, 0), To: DAG.getPOISON(VT: N->getValueType(ResNo: 0)));
2886 return SDValue();
2887 }
2888
2889 TargetLowering::MakeLibCallOptions CallOptions;
2890 CallOptions.setIsSigned(true);
2891 SDValue Ops[2] = {N->getOperand(Num: 0 + OpOffset), N->getOperand(Num: 1 + OpOffset)};
2892 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2893 DAG, LibcallImpl: LCImpl, RetVT: N->getValueType(ResNo: 0), Ops, CallOptions, dl: SDLoc(N), Chain);
2894 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
2895 if (IsStrict)
2896 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
2897 return SDValue();
2898}
2899
2900static unsigned getExtendForIntVecReduction(SDNode *N) {
2901 switch (N->getOpcode()) {
2902 default:
2903 llvm_unreachable("Expected integer vector reduction");
2904 case ISD::VECREDUCE_ADD:
2905 case ISD::VECREDUCE_MUL:
2906 case ISD::VECREDUCE_AND:
2907 case ISD::VECREDUCE_OR:
2908 case ISD::VECREDUCE_XOR:
2909 case ISD::VP_REDUCE_ADD:
2910 case ISD::VP_REDUCE_MUL:
2911 case ISD::VP_REDUCE_AND:
2912 case ISD::VP_REDUCE_OR:
2913 case ISD::VP_REDUCE_XOR:
2914 return ISD::ANY_EXTEND;
2915 case ISD::VECREDUCE_SMAX:
2916 case ISD::VECREDUCE_SMIN:
2917 case ISD::VP_REDUCE_SMAX:
2918 case ISD::VP_REDUCE_SMIN:
2919 return ISD::SIGN_EXTEND;
2920 case ISD::VECREDUCE_UMAX:
2921 case ISD::VECREDUCE_UMIN:
2922 case ISD::VP_REDUCE_UMAX:
2923 case ISD::VP_REDUCE_UMIN:
2924 return ISD::ZERO_EXTEND;
2925 }
2926}
2927
2928SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2929 switch (getExtendForIntVecReduction(N)) {
2930 default:
2931 llvm_unreachable("Impossible extension kind for integer reduction");
2932 case ISD::ANY_EXTEND:
2933 return GetPromotedInteger(Op: V);
2934 case ISD::SIGN_EXTEND:
2935 return SExtPromotedInteger(Op: V);
2936 case ISD::ZERO_EXTEND:
2937 return ZExtPromotedInteger(Op: V);
2938 }
2939}
2940
2941SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2942 SDLoc dl(N);
2943 SDValue Op = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
2944
2945 EVT OrigEltVT = N->getOperand(Num: 0).getValueType().getVectorElementType();
2946 EVT InVT = Op.getValueType();
2947 EVT EltVT = InVT.getVectorElementType();
2948 EVT ResVT = N->getValueType(ResNo: 0);
2949 unsigned Opcode = N->getOpcode();
2950
2951 // An i1 vecreduce_xor is equivalent to vecreduce_add, use that instead if
2952 // vecreduce_xor is not legal
2953 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 &&
2954 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_XOR, VT: InVT) &&
2955 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_ADD, VT: InVT))
2956 Opcode = ISD::VECREDUCE_ADD;
2957
2958 // An i1 vecreduce_or is equivalent to vecreduce_umax, use that instead if
2959 // vecreduce_or is not legal
2960 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 &&
2961 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_OR, VT: InVT) &&
2962 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMAX, VT: InVT)) {
2963 Opcode = ISD::VECREDUCE_UMAX;
2964 // Can't use promoteTargetBoolean here because we still need
2965 // to either sign_ext or zero_ext in the undefined case.
2966 switch (TLI.getBooleanContents(Type: InVT)) {
2967 case TargetLoweringBase::UndefinedBooleanContent:
2968 case TargetLoweringBase::ZeroOrOneBooleanContent:
2969 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2970 break;
2971 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2972 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2973 break;
2974 }
2975 }
2976
2977 // An i1 vecreduce_and is equivalent to vecreduce_umin, use that instead if
2978 // vecreduce_and is not legal
2979 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 &&
2980 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_AND, VT: InVT) &&
2981 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMIN, VT: InVT)) {
2982 Opcode = ISD::VECREDUCE_UMIN;
2983 // Can't use promoteTargetBoolean here because we still need
2984 // to either sign_ext or zero_ext in the undefined case.
2985 switch (TLI.getBooleanContents(Type: InVT)) {
2986 case TargetLoweringBase::UndefinedBooleanContent:
2987 case TargetLoweringBase::ZeroOrOneBooleanContent:
2988 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2989 break;
2990 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2991 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2992 break;
2993 }
2994 }
2995
2996 if (ResVT.bitsGE(VT: EltVT))
2997 return DAG.getNode(Opcode, DL: SDLoc(N), VT: ResVT, Operand: Op);
2998
2999 // Result size must be >= element size. If this is not the case after
3000 // promotion, also promote the result type and then truncate.
3001 SDValue Reduce = DAG.getNode(Opcode, DL: dl, VT: EltVT, Operand: Op);
3002 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: ResVT, Operand: Reduce);
3003}
3004
3005SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
3006 SDLoc DL(N);
3007 SDValue Op = N->getOperand(Num: OpNo);
3008 SmallVector<SDValue, 4> NewOps(N->ops());
3009
3010 if (OpNo == 2) { // Mask
3011 // Update in place.
3012 NewOps[2] = PromoteTargetBoolean(Bool: Op, ValVT: N->getOperand(Num: 1).getValueType());
3013 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3014 }
3015
3016 assert(OpNo == 1 && "Unexpected operand for promotion");
3017
3018 Op = PromoteIntOpVectorReduction(N, V: Op);
3019
3020 NewOps[OpNo] = Op;
3021
3022 EVT VT = N->getValueType(ResNo: 0);
3023 EVT EltVT = Op.getValueType().getScalarType();
3024
3025 if (VT.bitsGE(VT: EltVT))
3026 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT, Ops: NewOps);
3027
3028 // Result size must be >= element/start-value size. If this is not the case
3029 // after promotion, also promote both the start value and result type and
3030 // then truncate.
3031 NewOps[0] =
3032 DAG.getNode(Opcode: getExtendForIntVecReduction(N), DL, VT: EltVT, Operand: N->getOperand(Num: 0));
3033 SDValue Reduce = DAG.getNode(Opcode: N->getOpcode(), DL, VT: EltVT, Ops: NewOps);
3034 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT, Operand: Reduce);
3035}
3036
3037SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
3038 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3039 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Op), 0);
3040}
3041
3042SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
3043 assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
3044 SmallVector<SDValue> NewOps(N->ops());
3045 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
3046 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3047}
3048
3049SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
3050 assert(OpNo >= 7);
3051 SmallVector<SDValue> NewOps(N->ops());
3052 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
3053 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3054}
3055
3056SDValue DAGTypeLegalizer::PromoteIntOp_WRITE_REGISTER(SDNode *N,
3057 unsigned OpNo) {
3058 const Function &Fn = DAG.getMachineFunction().getFunction();
3059 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
3060 "cannot use llvm.write_register with illegal type", Fn,
3061 N->getDebugLoc()));
3062 return N->getOperand(Num: 0);
3063}
3064
3065SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
3066 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
3067 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
3068
3069 SmallVector<SDValue, 8> NewOps(N->ops());
3070 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
3071 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
3072 if (Res == N)
3073 return SDValue(Res, 0);
3074
3075 // Update triggered CSE, do our own replacement since caller can't.
3076 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
3077 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
3078 return SDValue();
3079}
3080
3081SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
3082 SmallVector<SDValue, 6> NewOps(N->ops());
3083
3084 if (OpNo == 2) { // Offset operand
3085 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
3086 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3087 }
3088
3089 assert((OpNo == 4 || OpNo == 5) && "Unexpected operand for promotion");
3090
3091 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
3092 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3093}
3094
3095SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_HISTOGRAM(SDNode *N,
3096 unsigned OpNo) {
3097 assert(OpNo == 1 && "Unexpected operand for promotion");
3098 SmallVector<SDValue, 7> NewOps(N->ops());
3099 NewOps[1] = GetPromotedInteger(Op: N->getOperand(Num: 1));
3100 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3101}
3102
3103SDValue DAGTypeLegalizer::PromoteIntOp_UnaryBooleanVectorOp(SDNode *N,
3104 unsigned OpNo) {
3105 assert(OpNo == 0 && "Unexpected operand for promotion");
3106 SDValue Op = N->getOperand(Num: 0);
3107
3108 SDValue NewOp;
3109 if (TLI.getBooleanContents(Type: Op.getValueType()) ==
3110 TargetLowering::ZeroOrNegativeOneBooleanContent)
3111 NewOp = SExtPromotedInteger(Op);
3112 else
3113 NewOp = ZExtPromotedInteger(Op);
3114
3115 return SDValue(DAG.UpdateNodeOperands(N, Op: NewOp), 0);
3116}
3117
3118SDValue DAGTypeLegalizer::PromoteIntOp_GET_ACTIVE_LANE_MASK(SDNode *N) {
3119 SmallVector<SDValue, 1> NewOps(N->ops());
3120 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3121 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3122 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3123}
3124
3125SDValue DAGTypeLegalizer::PromoteIntOp_MaskedBinOp(SDNode *N, unsigned OpNo) {
3126 assert(OpNo == 2);
3127 SmallVector<SDValue, 3> NewOps(N->ops());
3128 NewOps[2] = PromoteTargetBoolean(Bool: NewOps[2], ValVT: N->getValueType(ResNo: 0));
3129 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3130}
3131
3132SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
3133 SmallVector<SDValue, 1> NewOps(N->ops());
3134 switch (N->getOpcode()) {
3135 case ISD::PARTIAL_REDUCE_SMLA:
3136 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3137 NewOps[2] = SExtPromotedInteger(Op: N->getOperand(Num: 2));
3138 break;
3139 case ISD::PARTIAL_REDUCE_UMLA:
3140 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3141 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3142 break;
3143 case ISD::PARTIAL_REDUCE_SUMLA:
3144 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3145 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3146 break;
3147 default:
3148 llvm_unreachable("unexpected opcode");
3149 }
3150 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3151}
3152
3153SDValue DAGTypeLegalizer::PromoteIntOp_LOOP_DEPENDENCE_MASK(SDNode *N) {
3154 SDValue NewOps[4];
3155 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3156 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3157 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3158 NewOps[3] = N->getOperand(Num: 3);
3159 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3160}
3161
3162//===----------------------------------------------------------------------===//
3163// Integer Result Expansion
3164//===----------------------------------------------------------------------===//
3165
3166/// ExpandIntegerResult - This method is called when the specified result of the
3167/// specified node is found to need expansion. At this point, the node may also
3168/// have invalid operands or may have other results that need promotion, we just
3169/// know that (at least) one result needs expansion.
3170void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
3171 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG));
3172 SDValue Lo, Hi;
3173 Lo = Hi = SDValue();
3174
3175 // See if the target wants to custom expand this node.
3176 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true))
3177 return;
3178
3179 switch (N->getOpcode()) {
3180 default:
3181#ifndef NDEBUG
3182 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
3183 N->dump(&DAG); dbgs() << "\n";
3184#endif
3185 report_fatal_error(reason: "Do not know how to expand the result of this "
3186 "operator!");
3187
3188 case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
3189 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
3190 case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
3191 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
3192 case ISD::POISON:
3193 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
3194 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
3195 case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;
3196
3197 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
3198 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
3199 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
3200 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
3201 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
3202
3203 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
3204 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
3205 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
3206 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
3207 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
3208 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
3209 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
3210 case ISD::ABS:
3211 case ISD::ABS_MIN_POISON:
3212 ExpandIntRes_ABS(N, Lo, Hi);
3213 break;
3214 case ISD::ABDS:
3215 case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
3216 case ISD::CTLZ_ZERO_POISON:
3217 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
3218 case ISD::CTLS: ExpandIntRes_CTLS(N, Lo, Hi); break;
3219 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
3220 case ISD::CTTZ_ZERO_POISON:
3221 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
3222 case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
3223 case ISD::STRICT_FP_TO_SINT:
3224 case ISD::FP_TO_SINT:
3225 case ISD::STRICT_FP_TO_UINT:
3226 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_XINT(N, Lo, Hi); break;
3227 case ISD::FP_TO_SINT_SAT:
3228 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
3229 case ISD::STRICT_LROUND:
3230 case ISD::STRICT_LRINT:
3231 case ISD::LROUND:
3232 case ISD::LRINT:
3233 case ISD::STRICT_LLROUND:
3234 case ISD::STRICT_LLRINT:
3235 case ISD::LLROUND:
3236 case ISD::LLRINT: ExpandIntRes_XROUND_XRINT(N, Lo, Hi); break;
3237 case ISD::LOAD: ExpandIntRes_LOAD(N: cast<LoadSDNode>(Val: N), Lo, Hi); break;
3238 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
3239 case ISD::READCYCLECOUNTER:
3240 case ISD::READSTEADYCOUNTER: ExpandIntRes_READCOUNTER(N, Lo, Hi); break;
3241 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
3242 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
3243 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
3244 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
3245 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
3246 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
3247 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
3248 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
3249 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
3250
3251 case ISD::ATOMIC_LOAD_ADD:
3252 case ISD::ATOMIC_LOAD_SUB:
3253 case ISD::ATOMIC_LOAD_AND:
3254 case ISD::ATOMIC_LOAD_CLR:
3255 case ISD::ATOMIC_LOAD_OR:
3256 case ISD::ATOMIC_LOAD_XOR:
3257 case ISD::ATOMIC_LOAD_NAND:
3258 case ISD::ATOMIC_LOAD_MIN:
3259 case ISD::ATOMIC_LOAD_MAX:
3260 case ISD::ATOMIC_LOAD_UMIN:
3261 case ISD::ATOMIC_LOAD_UMAX:
3262 case ISD::ATOMIC_SWAP:
3263 case ISD::ATOMIC_CMP_SWAP: {
3264 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node: N);
3265 SplitInteger(Op: Tmp.first, Lo, Hi);
3266 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
3267 break;
3268 }
3269 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3270 AtomicSDNode *AN = cast<AtomicSDNode>(Val: N);
3271 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: MVT::Other);
3272 SDValue Tmp = DAG.getAtomicCmpSwap(
3273 Opcode: ISD::ATOMIC_CMP_SWAP, dl: SDLoc(N), MemVT: AN->getMemoryVT(), VTs,
3274 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 1), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
3275 MMO: AN->getMemOperand());
3276
3277 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
3278 // success simply by comparing the loaded value against the ingoing
3279 // comparison.
3280 SDValue Success = DAG.getSetCC(DL: SDLoc(N), VT: N->getValueType(ResNo: 1), LHS: Tmp,
3281 RHS: N->getOperand(Num: 2), Cond: ISD::SETEQ);
3282
3283 SplitInteger(Op: Tmp, Lo, Hi);
3284 ReplaceValueWith(From: SDValue(N, 1), To: Success);
3285 ReplaceValueWith(From: SDValue(N, 2), To: Tmp.getValue(R: 1));
3286 break;
3287 }
3288
3289 case ISD::AND:
3290 case ISD::OR:
3291 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
3292
3293 case ISD::UMAX:
3294 case ISD::SMAX:
3295 case ISD::UMIN:
3296 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
3297
3298 case ISD::SCMP:
3299 case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
3300
3301 case ISD::ADD:
3302 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
3303
3304 case ISD::ADDC:
3305 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
3306
3307 case ISD::ADDE:
3308 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
3309
3310 case ISD::UADDO_CARRY:
3311 case ISD::USUBO_CARRY: ExpandIntRes_UADDSUBO_CARRY(N, Lo, Hi); break;
3312
3313 case ISD::SADDO_CARRY:
3314 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
3315
3316 case ISD::SHL:
3317 case ISD::SRA:
3318 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
3319
3320 case ISD::SADDO:
3321 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
3322 case ISD::UADDO:
3323 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
3324 case ISD::UMULO:
3325 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3326
3327 case ISD::SADDSAT:
3328 case ISD::UADDSAT:
3329 case ISD::SSUBSAT:
3330 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
3331
3332 case ISD::SSHLSAT:
3333 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
3334
3335 case ISD::AVGCEILS:
3336 case ISD::AVGCEILU:
3337 case ISD::AVGFLOORS:
3338 case ISD::AVGFLOORU: ExpandIntRes_AVG(N, Lo, Hi); break;
3339
3340 case ISD::SMULFIX:
3341 case ISD::SMULFIXSAT:
3342 case ISD::UMULFIX:
3343 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
3344
3345 case ISD::SDIVFIX:
3346 case ISD::SDIVFIXSAT:
3347 case ISD::UDIVFIX:
3348 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
3349
3350 case ISD::VECREDUCE_ADD:
3351 case ISD::VECREDUCE_MUL:
3352 case ISD::VECREDUCE_AND:
3353 case ISD::VECREDUCE_OR:
3354 case ISD::VECREDUCE_XOR:
3355 case ISD::VECREDUCE_SMAX:
3356 case ISD::VECREDUCE_SMIN:
3357 case ISD::VECREDUCE_UMAX:
3358 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
3359
3360 case ISD::ROTL:
3361 case ISD::ROTR:
3362 ExpandIntRes_Rotate(N, Lo, Hi);
3363 break;
3364
3365 case ISD::FSHL:
3366 case ISD::FSHR:
3367 ExpandIntRes_FunnelShift(N, Lo, Hi);
3368 break;
3369
3370 case ISD::CLMUL:
3371 case ISD::CLMULR:
3372 case ISD::CLMULH:
3373 ExpandIntRes_CLMUL(N, Lo, Hi);
3374 break;
3375
3376 case ISD::PEXT:
3377 ExpandIntRes_PEXT(N, Lo, Hi);
3378 break;
3379
3380 case ISD::PDEP:
3381 ExpandIntRes_PDEP(N, Lo, Hi);
3382 break;
3383
3384 case ISD::VSCALE:
3385 ExpandIntRes_VSCALE(N, Lo, Hi);
3386 break;
3387
3388 case ISD::READ_REGISTER:
3389 ExpandIntRes_READ_REGISTER(N, Lo, Hi);
3390 break;
3391
3392 case ISD::CTTZ_ELTS:
3393 case ISD::CTTZ_ELTS_ZERO_POISON:
3394 ExpandIntRes_CTTZ_ELTS(N, Lo, Hi);
3395 break;
3396 }
3397
3398 // If Lo/Hi is null, the sub-method took care of registering results etc.
3399 if (Lo.getNode())
3400 SetExpandedInteger(Op: SDValue(N, ResNo), Lo, Hi);
3401}
3402
3403/// Lower an atomic node to the appropriate builtin call.
3404std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
3405 unsigned Opc = Node->getOpcode();
3406 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
3407 AtomicOrdering order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
3408 // Lower to outline atomic libcall if outline atomics enabled,
3409 // or to sync libcall otherwise
3410 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order: order, VT);
3411 EVT RetVT = Node->getValueType(ResNo: 0);
3412 TargetLowering::MakeLibCallOptions CallOptions;
3413 SmallVector<SDValue, 4> Ops;
3414
3415 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3416 if (LCImpl != RTLIB::Unsupported) {
3417 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
3418 Ops.push_back(Elt: Node->getOperand(Num: 1));
3419 } else {
3420 LC = RTLIB::getSYNC(Opc, VT);
3421 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3422 "Unexpected atomic op or value type!");
3423 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
3424 LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3425 }
3426 return TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT, Ops, CallOptions, dl: SDLoc(Node),
3427 Chain: Node->getOperand(Num: 0));
3428}
3429
3430/// N is a shift by a value that needs to be expanded,
3431/// and the shift amount is a constant 'Amt'. Expand the operation.
3432void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
3433 SDValue &Lo, SDValue &Hi) {
3434 SDLoc DL(N);
3435 // Expand the incoming operand to be shifted, so that we have its parts
3436 SDValue InL, InH;
3437 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3438
3439 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
3440 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
3441 if (!Amt) {
3442 Lo = InL;
3443 Hi = InH;
3444 return;
3445 }
3446
3447 EVT NVT = InL.getValueType();
3448 unsigned VTBits = N->getValueType(ResNo: 0).getSizeInBits();
3449 unsigned NVTBits = NVT.getSizeInBits();
3450
3451 if (N->getOpcode() == ISD::SHL) {
3452 if (Amt.uge(RHS: VTBits)) {
3453 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3454 } else if (Amt.ugt(RHS: NVTBits)) {
3455 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3456 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3457 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3458 } else if (Amt == NVTBits) {
3459 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3460 Hi = InL;
3461 } else {
3462 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3463 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3464 // Use FSHL if legal so we don't need to combine it later.
3465 if (TLI.isOperationLegal(Op: ISD::FSHL, VT: NVT)) {
3466 Hi = DAG.getNode(Opcode: ISD::FSHL, DL, VT: NVT, N1: InH, N2: InL,
3467 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3468 } else {
3469 Hi = DAG.getNode(
3470 Opcode: ISD::OR, DL, VT: NVT,
3471 N1: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3472 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3473 N2: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3474 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3475 }
3476 }
3477 return;
3478 }
3479
3480 if (N->getOpcode() == ISD::SRL) {
3481 if (Amt.uge(RHS: VTBits)) {
3482 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3483 } else if (Amt.ugt(RHS: NVTBits)) {
3484 Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3485 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3486 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3487 } else if (Amt == NVTBits) {
3488 Lo = InH;
3489 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3490 } else {
3491 // Use FSHR if legal so we don't need to combine it later.
3492 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3493 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3494 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3495 } else {
3496 Lo = DAG.getNode(
3497 Opcode: ISD::OR, DL, VT: NVT,
3498 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3499 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3500 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3501 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3502 }
3503 Hi = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3504 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3505 }
3506 return;
3507 }
3508
3509 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3510 if (Amt.uge(RHS: VTBits)) {
3511 Hi = Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3512 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3513 } else if (Amt.ugt(RHS: NVTBits)) {
3514 Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3515 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3516 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3517 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3518 } else if (Amt == NVTBits) {
3519 Lo = InH;
3520 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3521 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3522 } else {
3523 // Use FSHR if legal so we don't need to combine it later.
3524 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3525 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3526 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3527 } else {
3528 Lo = DAG.getNode(
3529 Opcode: ISD::OR, DL, VT: NVT,
3530 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3531 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3532 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3533 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3534 }
3535 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3536 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3537 }
3538}
3539
3540/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
3541/// this shift based on knowledge of the high bit of the shift amount. If we
3542/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
3543/// shift amount.
3544bool DAGTypeLegalizer::
3545ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3546 unsigned Opc = N->getOpcode();
3547 SDValue In = N->getOperand(Num: 0);
3548 SDValue Amt = N->getOperand(Num: 1);
3549 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3550 EVT ShTy = Amt.getValueType();
3551 unsigned ShBits = ShTy.getScalarSizeInBits();
3552 unsigned NVTBits = NVT.getScalarSizeInBits();
3553 assert(isPowerOf2_32(NVTBits) &&
3554 "Expanded integer type size not a power of two!");
3555 SDLoc dl(N);
3556
3557 APInt HighBitMask = APInt::getHighBitsSet(numBits: ShBits, hiBitsSet: ShBits - Log2_32(Value: NVTBits));
3558 KnownBits Known = DAG.computeKnownBits(Op: Amt);
3559
3560 // If we don't know anything about the high bits, exit.
3561 if (((Known.Zero | Known.One) & HighBitMask) == 0)
3562 return false;
3563
3564 // Get the incoming operand to be shifted.
3565 SDValue InL, InH;
3566 GetExpandedInteger(Op: In, Lo&: InL, Hi&: InH);
3567
3568 // If we know that any of the high bits of the shift amount are one, then we
3569 // can do this as a couple of simple shifts.
3570 if (Known.One.intersects(RHS: HighBitMask)) {
3571 // Mask out the high bit, which we know is set.
3572 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShTy, N1: Amt,
3573 N2: DAG.getConstant(Val: ~HighBitMask, DL: dl, VT: ShTy));
3574
3575 switch (Opc) {
3576 default: llvm_unreachable("Unknown shift");
3577 case ISD::SHL:
3578 Lo = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Low part is zero.
3579 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt); // High part from Lo part.
3580 return true;
3581 case ISD::SRL:
3582 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3583 Lo = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3584 return true;
3585 case ISD::SRA:
3586 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign extend high part.
3587 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3588 Lo = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3589 return true;
3590 }
3591 }
3592
3593 // If we know that all of the high bits of the shift amount are zero, then we
3594 // can do this as a couple of simple shifts.
3595 if (HighBitMask.isSubsetOf(RHS: Known.Zero)) {
3596 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
3597 // shift if x is zero. We can use XOR here because x is known to be smaller
3598 // than 32.
3599 SDValue Amt2 = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: ShTy, N1: Amt,
3600 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3601
3602 unsigned Op1, Op2;
3603 switch (Opc) {
3604 default: llvm_unreachable("Unknown shift");
3605 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
3606 case ISD::SRL:
3607 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
3608 }
3609
3610 // When shifting right the arithmetic for Lo and Hi is swapped.
3611 if (Opc != ISD::SHL)
3612 std::swap(a&: InL, b&: InH);
3613
3614 // Use a little trick to get the bits that move from Lo to Hi. First
3615 // shift by one bit.
3616 SDValue Sh1 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: InL, N2: DAG.getConstant(Val: 1, DL: dl, VT: ShTy));
3617 // Then compute the remaining shift with amount-1.
3618 SDValue Sh2 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: Sh1, N2: Amt2);
3619
3620 Lo = DAG.getNode(Opcode: Opc, DL: dl, VT: NVT, N1: InL, N2: Amt);
3621 Hi = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: Op1, DL: dl, VT: NVT, N1: InH, N2: Amt),N2: Sh2);
3622
3623 if (Opc != ISD::SHL)
3624 std::swap(a&: Hi, b&: Lo);
3625 return true;
3626 }
3627
3628 return false;
3629}
3630
3631/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
3632/// of any size.
3633bool DAGTypeLegalizer::
3634ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3635 SDValue Amt = N->getOperand(Num: 1);
3636 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3637 EVT ShTy = Amt.getValueType();
3638 unsigned NVTBits = NVT.getSizeInBits();
3639 assert(isPowerOf2_32(NVTBits) &&
3640 "Expanded integer type size not a power of two!");
3641 SDLoc dl(N);
3642
3643 // Get the incoming operand to be shifted.
3644 SDValue InL, InH;
3645 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3646
3647 SDValue NVBitsNode = DAG.getConstant(Val: NVTBits, DL: dl, VT: ShTy);
3648 SDValue AmtExcess = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: Amt, N2: NVBitsNode);
3649 SDValue AmtLack = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: NVBitsNode, N2: Amt);
3650 SDValue isShort = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3651 LHS: Amt, RHS: NVBitsNode, Cond: ISD::SETULT);
3652 SDValue isZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3653 LHS: Amt, RHS: DAG.getConstant(Val: 0, DL: dl, VT: ShTy),
3654 Cond: ISD::SETEQ);
3655
3656 SDValue LoS, HiS, LoL, HiL;
3657 switch (N->getOpcode()) {
3658 default: llvm_unreachable("Unknown shift");
3659 case ISD::SHL:
3660 // Short: ShAmt < NVTBits
3661 LoS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt);
3662 HiS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3663 N1: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: Amt),
3664 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: AmtLack));
3665
3666 // Long: ShAmt >= NVTBits
3667 LoL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Lo part is zero.
3668 HiL = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: AmtExcess); // Hi from Lo part.
3669
3670 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL);
3671 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InH,
3672 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL));
3673 return true;
3674 case ISD::SRL:
3675 // Short: ShAmt < NVTBits
3676 HiS = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt);
3677 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3678 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3679 // FIXME: If Amt is zero, the following shift generates an undefined result
3680 // on some architectures.
3681 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3682
3683 // Long: ShAmt >= NVTBits
3684 HiL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3685 LoL = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3686
3687 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3688 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3689 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3690 return true;
3691 case ISD::SRA:
3692 // Short: ShAmt < NVTBits
3693 HiS = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt);
3694 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3695 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3696 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3697
3698 // Long: ShAmt >= NVTBits
3699 HiL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign of Hi part.
3700 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3701 LoL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3702
3703 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3704 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3705 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3706 return true;
3707 }
3708}
3709
3710static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
3711
3712 switch (Op) {
3713 default: llvm_unreachable("invalid min/max opcode");
3714 case ISD::SMAX:
3715 return std::make_pair(x: ISD::SETGT, y: ISD::UMAX);
3716 case ISD::UMAX:
3717 return std::make_pair(x: ISD::SETUGT, y: ISD::UMAX);
3718 case ISD::SMIN:
3719 return std::make_pair(x: ISD::SETLT, y: ISD::UMIN);
3720 case ISD::UMIN:
3721 return std::make_pair(x: ISD::SETULT, y: ISD::UMIN);
3722 }
3723}
3724
3725void DAGTypeLegalizer::ExpandIntRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
3726 SDLoc DL(N);
3727
3728 SDValue LHS = N->getOperand(Num: 0);
3729 SDValue RHS = N->getOperand(Num: 1);
3730 EVT NewVT = getSetCCResultType(VT: LHS.getValueType());
3731
3732 // Taking the same approach as ScalarizeVecRes_SETCC
3733 SDValue Res = DAG.getNode(Opcode: ISD::SETCC, DL, VT: NewVT, N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
3734
3735 Res = DAG.getBoolExtOrTrunc(Op: Res, SL: DL, VT: N->getValueType(ResNo: 0), OpVT: NewVT);
3736 SplitInteger(Op: Res, Lo, Hi);
3737}
3738
3739void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
3740 SDValue &Lo, SDValue &Hi) {
3741 SDLoc DL(N);
3742
3743 SDValue LHS = N->getOperand(Num: 0);
3744 SDValue RHS = N->getOperand(Num: 1);
3745
3746 // If the upper halves are all sign bits, then we can perform the MINMAX on
3747 // the lower half and sign-extend the result to the upper half.
3748 unsigned NumBits = N->getValueType(ResNo: 0).getScalarSizeInBits();
3749 unsigned NumHalfBits = NumBits / 2;
3750 if (DAG.ComputeNumSignBits(Op: LHS) > NumHalfBits &&
3751 DAG.ComputeNumSignBits(Op: RHS) > NumHalfBits) {
3752 SDValue LHSL, LHSH, RHSL, RHSH;
3753 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3754 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3755 EVT NVT = LHSL.getValueType();
3756
3757 Lo = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: LHSL, N2: RHSL);
3758 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: Lo,
3759 N2: DAG.getShiftAmountConstant(Val: NumHalfBits - 1, VT: NVT, DL));
3760 return;
3761 }
3762
3763 // The Lo of smin(X, -1) is LHSL if X is negative. Otherwise it's -1.
3764 // The Lo of smax(X, 0) is 0 if X is negative. Otherwise it's LHSL.
3765 if ((N->getOpcode() == ISD::SMAX && isNullConstant(V: RHS)) ||
3766 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(V: RHS))) {
3767 SDValue LHSL, LHSH, RHSL, RHSH;
3768 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3769 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3770 EVT NVT = LHSL.getValueType();
3771 EVT CCT = getSetCCResultType(VT: NVT);
3772
3773 SDValue HiNeg =
3774 DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: DAG.getConstant(Val: 0, DL, VT: NVT), Cond: ISD::SETLT);
3775 if (N->getOpcode() == ISD::SMIN) {
3776 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: LHSL, RHS: DAG.getAllOnesConstant(DL, VT: NVT));
3777 } else {
3778 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: DAG.getConstant(Val: 0, DL, VT: NVT), RHS: LHSL);
3779 }
3780 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3781 return;
3782 }
3783
3784 const APInt *RHSVal = nullptr;
3785 if (auto *RHSConst = dyn_cast<ConstantSDNode>(Val&: RHS))
3786 RHSVal = &RHSConst->getAPIntValue();
3787
3788 // The high half of MIN/MAX is always just the the MIN/MAX of the
3789 // high halves of the operands. Expand this way if it appears profitable.
3790 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) &&
3791 (RHSVal->countLeadingOnes() >= NumHalfBits ||
3792 RHSVal->countLeadingZeros() >= NumHalfBits)) {
3793 SDValue LHSL, LHSH, RHSL, RHSH;
3794 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3795 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3796 EVT NVT = LHSL.getValueType();
3797 EVT CCT = getSetCCResultType(VT: NVT);
3798
3799 ISD::NodeType LoOpc;
3800 ISD::CondCode CondC;
3801 std::tie(args&: CondC, args&: LoOpc) = getExpandedMinMaxOps(Op: N->getOpcode());
3802
3803 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3804 // We need to know whether to select Lo part that corresponds to 'winning'
3805 // Hi part or if Hi parts are equal.
3806 SDValue IsHiLeft = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: CondC);
3807 SDValue IsHiEq = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: ISD::SETEQ);
3808
3809 // Lo part corresponding to the 'winning' Hi part
3810 SDValue LoCmp = DAG.getSelect(DL, VT: NVT, Cond: IsHiLeft, LHS: LHSL, RHS: RHSL);
3811
3812 // Recursed Lo part if Hi parts are equal, this uses unsigned version
3813 SDValue LoMinMax = DAG.getNode(Opcode: LoOpc, DL, VT: NVT, Ops: {LHSL, RHSL});
3814
3815 Lo = DAG.getSelect(DL, VT: NVT, Cond: IsHiEq, LHS: LoMinMax, RHS: LoCmp);
3816 return;
3817 }
3818
3819 // Expand to "a < b ? a : b" etc. Prefer ge/le if that simplifies
3820 // the compare.
3821 ISD::CondCode Pred;
3822 switch (N->getOpcode()) {
3823 default: llvm_unreachable("How did we get here?");
3824 case ISD::SMAX:
3825 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3826 Pred = ISD::SETGE;
3827 else
3828 Pred = ISD::SETGT;
3829 break;
3830 case ISD::SMIN:
3831 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3832 Pred = ISD::SETLE;
3833 else
3834 Pred = ISD::SETLT;
3835 break;
3836 case ISD::UMAX:
3837 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3838 Pred = ISD::SETUGE;
3839 else
3840 Pred = ISD::SETUGT;
3841 break;
3842 case ISD::UMIN:
3843 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3844 Pred = ISD::SETULE;
3845 else
3846 Pred = ISD::SETULT;
3847 break;
3848 }
3849 EVT VT = N->getValueType(ResNo: 0);
3850 EVT CCT = getSetCCResultType(VT);
3851 SDValue Cond = DAG.getSetCC(DL, VT: CCT, LHS, RHS, Cond: Pred);
3852 SDValue Result = DAG.getSelect(DL, VT, Cond, LHS, RHS);
3853 SplitInteger(Op: Result, Lo, Hi);
3854}
3855
3856void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
3857 SDValue ExpandedCMP = TLI.expandCMP(Node: N, DAG);
3858 SplitInteger(Op: ExpandedCMP, Lo, Hi);
3859}
3860
3861void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
3862 SDValue &Lo, SDValue &Hi) {
3863 SDLoc dl(N);
3864 // Expand the subcomponents.
3865 SDValue LHSL, LHSH, RHSL, RHSH;
3866 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3867 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3868
3869 EVT NVT = LHSL.getValueType();
3870 SDValue LoOps[2] = { LHSL, RHSL };
3871 SDValue HiOps[3] = { LHSH, RHSH };
3872
3873 bool HasOpCarry = TLI.isOperationLegalOrCustom(
3874 Op: N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
3875 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3876 if (HasOpCarry) {
3877 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
3878 if (N->getOpcode() == ISD::ADD) {
3879 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3880 HiOps[2] = Lo.getValue(R: 1);
3881 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3882 ? DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3883 : DAG.getNode(Opcode: ISD::UADDO_CARRY, DL: dl, VTList, Ops: HiOps);
3884 } else {
3885 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3886 HiOps[2] = Lo.getValue(R: 1);
3887 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3888 ? DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3889 : DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, Ops: HiOps);
3890 }
3891 return;
3892 }
3893
3894 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
3895 // them. TODO: Teach operation legalization how to expand unsupported
3896 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
3897 // a carry of type MVT::Glue, but there doesn't seem to be any way to
3898 // generate a value of this type in the expanded code sequence.
3899 bool hasCarry =
3900 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3901 ISD::ADDC : ISD::SUBC,
3902 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3903
3904 if (hasCarry) {
3905 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: MVT::Glue);
3906 if (N->getOpcode() == ISD::ADD) {
3907 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3908 HiOps[2] = Lo.getValue(R: 1);
3909 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3910 } else {
3911 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3912 HiOps[2] = Lo.getValue(R: 1);
3913 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3914 }
3915 return;
3916 }
3917
3918 bool hasOVF =
3919 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3920 ISD::UADDO : ISD::USUBO,
3921 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3922 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(Type: NVT);
3923
3924 if (hasOVF) {
3925 EVT OvfVT = getSetCCResultType(VT: NVT);
3926 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: OvfVT);
3927 int RevOpc;
3928 if (N->getOpcode() == ISD::ADD) {
3929 RevOpc = ISD::SUB;
3930 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3931 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3932 } else {
3933 RevOpc = ISD::ADD;
3934 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3935 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3936 }
3937 SDValue OVF = Lo.getValue(R: 1);
3938
3939 switch (BoolType) {
3940 case TargetLoweringBase::UndefinedBooleanContent:
3941 OVF = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: OvfVT, N1: DAG.getConstant(Val: 1, DL: dl, VT: OvfVT), N2: OVF);
3942 [[fallthrough]];
3943 case TargetLoweringBase::ZeroOrOneBooleanContent:
3944 OVF = DAG.getZExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3945 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Hi, N2: OVF);
3946 break;
3947 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3948 OVF = DAG.getSExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3949 Hi = DAG.getNode(Opcode: RevOpc, DL: dl, VT: NVT, N1: Hi, N2: OVF);
3950 }
3951 return;
3952 }
3953
3954 if (N->getOpcode() == ISD::ADD) {
3955 Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: LoOps);
3956 SDValue Cmp;
3957 // Special case: X+1 has a carry out if X+1==0. This may reduce the live
3958 // range of X. We assume comparing with 0 is cheap.
3959 if (isOneConstant(V: LoOps[1]))
3960 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
3961 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3962 else if (isAllOnesConstant(V: LoOps[1])) {
3963 if (isAllOnesConstant(V: HiOps[1]))
3964 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3965 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3966 else
3967 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3968 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
3969 } else
3970 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo, RHS: LoOps[0],
3971 Cond: ISD::SETULT);
3972
3973 SDValue Carry;
3974 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3975 Carry = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3976 else
3977 Carry = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3978 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3979
3980 if (isAllOnesConstant(V: LoOps[1]) && isAllOnesConstant(V: HiOps[1])) {
3981 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: HiOps[0], N2: Carry);
3982 } else {
3983 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3984 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Hi, N2: Carry);
3985 }
3986 } else {
3987 Lo = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: LoOps);
3988 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3989 SDValue Cmp =
3990 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LoOps[0].getValueType()),
3991 LHS: LoOps[0], RHS: LoOps[1], Cond: ISD::SETULT);
3992
3993 SDValue Borrow;
3994 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3995 Borrow = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3996 else
3997 Borrow = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3998 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3999
4000 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Hi, N2: Borrow);
4001 }
4002}
4003
4004void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
4005 SDValue &Lo, SDValue &Hi) {
4006 // Expand the subcomponents.
4007 SDValue LHSL, LHSH, RHSL, RHSH;
4008 SDLoc dl(N);
4009 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4010 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4011 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
4012 SDValue LoOps[2] = { LHSL, RHSL };
4013 SDValue HiOps[3] = { LHSH, RHSH };
4014
4015 if (N->getOpcode() == ISD::ADDC) {
4016 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
4017 HiOps[2] = Lo.getValue(R: 1);
4018 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
4019 } else {
4020 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
4021 HiOps[2] = Lo.getValue(R: 1);
4022 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
4023 }
4024
4025 // Legalized the flag result - switch anything that used the old flag to
4026 // use the new one.
4027 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4028}
4029
4030void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
4031 SDValue &Lo, SDValue &Hi) {
4032 // Expand the subcomponents.
4033 SDValue LHSL, LHSH, RHSL, RHSH;
4034 SDLoc dl(N);
4035 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4036 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4037 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
4038 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
4039 SDValue HiOps[3] = { LHSH, RHSH };
4040
4041 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
4042 HiOps[2] = Lo.getValue(R: 1);
4043 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
4044
4045 // Legalized the flag result - switch anything that used the old flag to
4046 // use the new one.
4047 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4048}
4049
4050void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
4051 SDValue &Lo, SDValue &Hi) {
4052 SDValue LHS = N->getOperand(Num: 0);
4053 SDValue RHS = N->getOperand(Num: 1);
4054 SDLoc dl(N);
4055
4056 SDValue Ovf;
4057
4058 unsigned CarryOp, NoCarryOp;
4059 ISD::CondCode Cond;
4060 switch(N->getOpcode()) {
4061 case ISD::UADDO:
4062 CarryOp = ISD::UADDO_CARRY;
4063 NoCarryOp = ISD::ADD;
4064 Cond = ISD::SETULT;
4065 break;
4066 case ISD::USUBO:
4067 CarryOp = ISD::USUBO_CARRY;
4068 NoCarryOp = ISD::SUB;
4069 Cond = ISD::SETUGT;
4070 break;
4071 default:
4072 llvm_unreachable("Node has unexpected Opcode");
4073 }
4074
4075 bool HasCarryOp = TLI.isOperationLegalOrCustom(
4076 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
4077
4078 if (HasCarryOp) {
4079 // Expand the subcomponents.
4080 SDValue LHSL, LHSH, RHSL, RHSH;
4081 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
4082 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
4083 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4084 SDValue LoOps[2] = { LHSL, RHSL };
4085 SDValue HiOps[3] = { LHSH, RHSH };
4086
4087 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
4088 HiOps[2] = Lo.getValue(R: 1);
4089 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: HiOps);
4090
4091 Ovf = Hi.getValue(R: 1);
4092 } else {
4093 // Expand the result by simply replacing it with the equivalent
4094 // non-overflow-checking operation.
4095 SDValue Sum = DAG.getNode(Opcode: NoCarryOp, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS);
4096 SplitInteger(Op: Sum, Lo, Hi);
4097
4098 if (N->getOpcode() == ISD::UADDO && isOneConstant(V: RHS)) {
4099 // Special case: uaddo X, 1 overflowed if X+1 == 0. We can detect this
4100 // with (Lo | Hi) == 0.
4101 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Lo.getValueType(), N1: Lo, N2: Hi);
4102 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Or,
4103 RHS: DAG.getConstant(Val: 0, DL: dl, VT: Lo.getValueType()), Cond: ISD::SETEQ);
4104 } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(V: RHS)) {
4105 // Special case: uaddo X, -1 overflows if X == 0.
4106 Ovf =
4107 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS,
4108 RHS: DAG.getConstant(Val: 0, DL: dl, VT: LHS.getValueType()), Cond: ISD::SETNE);
4109 } else {
4110 // Calculate the overflow: addition overflows iff a + b < a, and
4111 // subtraction overflows iff a - b > a.
4112 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Sum, RHS: LHS, Cond);
4113 }
4114 }
4115
4116 // Legalized the flag result - switch anything that used the old flag to
4117 // use the new one.
4118 ReplaceValueWith(From: SDValue(N, 1), To: Ovf);
4119}
4120
4121void DAGTypeLegalizer::ExpandIntRes_UADDSUBO_CARRY(SDNode *N, SDValue &Lo,
4122 SDValue &Hi) {
4123 // Expand the subcomponents.
4124 SDValue LHSL, LHSH, RHSL, RHSH;
4125 SDLoc dl(N);
4126 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4127 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4128 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4129 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
4130 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
4131
4132 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
4133 HiOps[2] = Lo.getValue(R: 1);
4134 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
4135
4136 // Legalized the flag result - switch anything that used the old flag to
4137 // use the new one.
4138 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4139}
4140
4141void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
4142 SDValue &Lo, SDValue &Hi) {
4143 // Expand the subcomponents.
4144 SDValue LHSL, LHSH, RHSL, RHSH;
4145 SDLoc dl(N);
4146 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4147 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4148 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4149
4150 // We need to use an unsigned carry op for the lo part.
4151 unsigned CarryOp =
4152 N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
4153 Lo = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSL, RHSL, N->getOperand(Num: 2) });
4154 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4155
4156 // Legalized the flag result - switch anything that used the old flag to
4157 // use the new one.
4158 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4159}
4160
4161void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
4162 SDValue &Lo, SDValue &Hi) {
4163 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4164 SDLoc dl(N);
4165 SDValue Op = N->getOperand(Num: 0);
4166 if (Op.getValueType().bitsLE(VT: NVT)) {
4167 // The low part is any extension of the input (which degenerates to a copy).
4168 Lo = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Op);
4169 Hi = DAG.getUNDEF(VT: NVT); // The high part is undefined.
4170 } else {
4171 // For example, extension of an i48 to an i64. The operand type necessarily
4172 // promotes to the result type, so will end up being expanded too.
4173 assert(getTypeAction(Op.getValueType()) ==
4174 TargetLowering::TypePromoteInteger &&
4175 "Only know how to promote this result!");
4176 SDValue Res = GetPromotedInteger(Op);
4177 assert(Res.getValueType() == N->getValueType(0) &&
4178 "Operand over promoted?");
4179 // Split the promoted operand. This will simplify when it is expanded.
4180 SplitInteger(Op: Res, Lo, Hi);
4181 }
4182}
4183
4184void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
4185 SDValue &Lo, SDValue &Hi) {
4186 SDLoc dl(N);
4187 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4188 EVT NVT = Lo.getValueType();
4189 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4190 unsigned NVTBits = NVT.getSizeInBits();
4191 unsigned EVTBits = EVT.getSizeInBits();
4192
4193 if (NVTBits < EVTBits) {
4194 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Hi,
4195 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4196 BitWidth: EVTBits - NVTBits)));
4197 } else {
4198 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4199 // The high part replicates the sign bit of Lo, make it explicit.
4200 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4201 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL: dl));
4202 }
4203}
4204
4205void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
4206 SDValue &Lo, SDValue &Hi) {
4207 SDLoc dl(N);
4208 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4209 EVT NVT = Lo.getValueType();
4210 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4211 unsigned NVTBits = NVT.getSizeInBits();
4212 unsigned EVTBits = EVT.getSizeInBits();
4213
4214 if (NVTBits < EVTBits) {
4215 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Hi,
4216 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4217 BitWidth: EVTBits - NVTBits)));
4218 } else {
4219 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4220 // The high part must be zero, make it explicit.
4221 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4222 }
4223}
4224
4225void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
4226 SDValue &Lo, SDValue &Hi) {
4227 SDLoc dl(N);
4228 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4229 Lo = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4230 Hi = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4231}
4232
4233void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
4234 SDValue &Lo, SDValue &Hi) {
4235 SDLoc dl(N);
4236 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4237 Lo = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4238 Hi = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4239}
4240
4241void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
4242 SDValue &Hi) {
4243 SDLoc dl(N);
4244 // parity(HiLo) -> parity(Lo^Hi)
4245 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4246 EVT NVT = Lo.getValueType();
4247 Lo =
4248 DAG.getNode(Opcode: ISD::PARITY, DL: dl, VT: NVT, Operand: DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Hi));
4249 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4250}
4251
4252void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
4253 SDValue &Lo, SDValue &Hi) {
4254 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4255 unsigned NBitWidth = NVT.getSizeInBits();
4256 auto Constant = cast<ConstantSDNode>(Val: N);
4257 const APInt &Cst = Constant->getAPIntValue();
4258 bool IsTarget = Constant->isTargetOpcode();
4259 bool IsOpaque = Constant->isOpaque();
4260 SDLoc dl(N);
4261 Lo = DAG.getConstant(Val: Cst.trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget, isOpaque: IsOpaque);
4262 Hi = DAG.getConstant(Val: Cst.lshr(shiftAmt: NBitWidth).trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget,
4263 isOpaque: IsOpaque);
4264}
4265
4266void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4267 SDLoc dl(N);
4268
4269 SDValue N0 = N->getOperand(Num: 0);
4270 GetExpandedInteger(Op: N0, Lo, Hi);
4271 EVT NVT = Lo.getValueType();
4272
4273 // If the upper half is all sign bits, then we can perform the ABS on the
4274 // lower half and zero-extend. We could use ISD::ABS_MIN_POISON here if
4275 // DAG.ComputeNumSignBits(N0) is larger than NVT.getScalarSizeInBits() + 1.
4276 unsigned NumSignBits = DAG.ComputeNumSignBits(Op: N0);
4277 if (NumSignBits > NVT.getScalarSizeInBits()) {
4278 unsigned AbsOpc = NumSignBits > NVT.getScalarSizeInBits() + 1
4279 ? ISD::ABS_MIN_POISON
4280 : ISD::ABS;
4281 Lo = DAG.getNode(Opcode: AbsOpc, DL: dl, VT: NVT, Operand: Lo);
4282 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4283 return;
4284 }
4285
4286 // If we have USUBO_CARRY, use the expanded form of the sra+xor+sub sequence
4287 // we use in LegalizeDAG. The SUB part of the expansion is based on
4288 // ExpandIntRes_ADDSUB which also uses USUBO_CARRY/USUBO after checking that
4289 // USUBO_CARRY is LegalOrCustom. Each of the pieces here can be further
4290 // expanded if needed. Shift expansion has a special case for filling with
4291 // sign bits so that we will only end up with one SRA.
4292 bool HasSubCarry = TLI.isOperationLegalOrCustom(
4293 Op: ISD::USUBO_CARRY, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
4294 if (HasSubCarry) {
4295 SDValue Sign = DAG.getNode(
4296 Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Hi,
4297 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - 1, VT: NVT, DL: dl));
4298 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
4299 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Sign);
4300 Hi = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Hi, N2: Sign);
4301 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: Lo, N2: Sign);
4302 Hi = DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: Hi, N2: Sign, N3: Lo.getValue(R: 1));
4303 return;
4304 }
4305
4306 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
4307 EVT VT = N->getValueType(ResNo: 0);
4308 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT,
4309 N1: DAG.getConstant(Val: 0, DL: dl, VT), N2: N0);
4310 SDValue NegLo, NegHi;
4311 SplitInteger(Op: Neg, Lo&: NegLo, Hi&: NegHi);
4312
4313 SDValue HiIsNeg = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4314 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETLT);
4315 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegLo, RHS: Lo);
4316 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegHi, RHS: Hi);
4317}
4318
4319void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
4320 SDValue &Lo, SDValue &Hi) {
4321 SDLoc dl(N);
4322 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
4323 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4324 EVT NVT = Lo.getValueType();
4325
4326 SDValue HiNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4327 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4328
4329 SDValue LoLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Lo);
4330 SDValue HiLZ = DAG.getNode(Opcode: ISD::CTLZ_ZERO_POISON, DL: dl, VT: NVT, Operand: Hi);
4331
4332 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiNotZero, LHS: HiLZ,
4333 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoLZ,
4334 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4335 VT: NVT)));
4336 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4337}
4338
4339void DAGTypeLegalizer::ExpandIntRes_CTLS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4340 SDLoc dl(N);
4341 // ctls(HiLo) -> if (IsAllSignBits = (ctls(Hi) == BW-1)) then
4342 // BW-1 + clz(IsNegative = (Hi < 0) ? ~Lo : Lo)
4343 // else ctls(Hi)
4344 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4345 EVT NVT = Lo.getValueType();
4346 unsigned NVTBits = NVT.getScalarSizeInBits();
4347
4348 SDValue Constant0 = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4349 SDValue ConstantBWM1 = DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: NVT);
4350
4351 SDValue HiCTLS = DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Hi);
4352 SDValue IsAllSignBits = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: HiCTLS,
4353 RHS: ConstantBWM1, Cond: ISD::SETEQ);
4354 SDValue IsNegative =
4355 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi, RHS: Constant0, Cond: ISD::SETLT);
4356 SDValue AdjustedLo =
4357 DAG.getSelect(DL: dl, VT: NVT, Cond: IsNegative, LHS: DAG.getNOT(DL: dl, Val: Lo, VT: NVT), RHS: Lo);
4358 SDValue LoCLZ = DAG.getNode(Opcode: ISD::CTLZ, DL: dl, VT: NVT, Operand: AdjustedLo);
4359 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: IsAllSignBits,
4360 LHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoCLZ, N2: ConstantBWM1),
4361 RHS: HiCTLS);
4362 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4363}
4364
4365void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
4366 SDValue Result = TLI.expandABD(N, DAG);
4367 SplitInteger(Op: Result, Lo, Hi);
4368}
4369
4370void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
4371 SDValue Op = N->getOperand(Num: 0);
4372 EVT VT = N->getValueType(ResNo: 0);
4373 SDLoc DL(N);
4374
4375 if (TLI.getOperationAction(Op: ISD::CTPOP, VT) == TargetLoweringBase::LibCall) {
4376 RTLIB::Libcall LC = RTLIB::getCTPOP(VT);
4377 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
4378 "LibCall explicitly requested, but not available");
4379
4380 if (RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
4381 TargetLowering::MakeLibCallOptions CallOptions;
4382 EVT IntVT =
4383 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
4384 SDValue Res =
4385 TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: IntVT, Ops: Op, CallOptions, dl: DL).first;
4386 SplitInteger(Op: DAG.getSExtOrTrunc(Op: Res, DL, VT), Lo, Hi);
4387 return;
4388 }
4389
4390 // If the function is not available, fall back on the expansion.
4391 }
4392
4393 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
4394 GetExpandedInteger(Op, Lo, Hi);
4395 EVT NVT = Lo.getValueType();
4396 Lo = DAG.getNode(Opcode: ISD::ADD, DL, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Lo),
4397 N2: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Hi));
4398 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
4399}
4400
4401void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
4402 SDValue &Lo, SDValue &Hi) {
4403 SDLoc dl(N);
4404 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
4405 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4406 EVT NVT = Lo.getValueType();
4407
4408 SDValue LoNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
4409 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4410
4411 SDValue LoLZ = DAG.getNode(Opcode: ISD::CTTZ_ZERO_POISON, DL: dl, VT: NVT, Operand: Lo);
4412 SDValue HiLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Hi);
4413
4414 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: LoNotZero, LHS: LoLZ,
4415 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: HiLZ,
4416 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4417 VT: NVT)));
4418 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4419}
4420
4421void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo,
4422 SDValue &Hi) {
4423 SDLoc dl(N);
4424 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4425 unsigned NBitWidth = NVT.getSizeInBits();
4426
4427 Lo = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
4428 SDValue Chain = Lo.getValue(R: 1);
4429 // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING
4430 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4431 N2: DAG.getShiftAmountConstant(Val: NBitWidth - 1, VT: NVT, DL: dl));
4432
4433 // Legalize the chain result - switch anything that used the old chain to
4434 // use the new one.
4435 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
4436}
4437
4438// Helper for producing an FP_EXTEND/STRICT_FP_EXTEND of Op.
4439static SDValue fpExtendHelper(SDValue Op, SDValue &Chain, bool IsStrict, EVT VT,
4440 SDLoc DL, SelectionDAG &DAG) {
4441 if (IsStrict) {
4442 Op = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL, ResultTys: {VT, MVT::Other}, Ops: {Chain, Op});
4443 Chain = Op.getValue(R: 1);
4444 return Op;
4445 }
4446 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT, Operand: Op);
4447}
4448
4449void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
4450 SDValue &Hi) {
4451 SDLoc dl(N);
4452 EVT VT = N->getValueType(ResNo: 0);
4453
4454 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
4455 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
4456 bool IsStrict = N->isStrictFPOpcode();
4457 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4458 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4459
4460 // If the input is bf16 or needs to be soft promoted, extend to f32.
4461 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf ||
4462 Op.getValueType() == MVT::bf16) {
4463 Op = fpExtendHelper(Op, Chain, IsStrict, VT: MVT::f32, DL: dl, DAG);
4464 }
4465
4466 // NOTE: We need a variable that lives across makeLibCall so
4467 // CallOptions.setTypeListBeforeSoften can save a reference to it.
4468 EVT OpVT = Op.getValueType();
4469
4470 RTLIB::Libcall LC =
4471 IsSigned ? RTLIB::getFPTOSINT(OpVT, RetVT: VT) : RTLIB::getFPTOUINT(OpVT, RetVT: VT);
4472 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
4473 TargetLowering::MakeLibCallOptions CallOptions;
4474 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftenFloat)
4475 CallOptions.setTypeListBeforeSoften(OpsVT: OpVT, RetVT: VT);
4476 else
4477 CallOptions.setIsSigned(true); // FIXME: Is this needed?
4478 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op,
4479 CallOptions, dl, Chain);
4480 SplitInteger(Op: Tmp.first, Lo, Hi);
4481
4482 if (IsStrict)
4483 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4484}
4485
4486void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
4487 SDValue &Hi) {
4488 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
4489 SplitInteger(Op: Res, Lo, Hi);
4490}
4491
4492void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo,
4493 SDValue &Hi) {
4494 SDLoc dl(N);
4495 bool IsStrict = N->isStrictFPOpcode();
4496 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4497 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4498
4499 EVT VT = Op.getValueType();
4500
4501 if (VT == MVT::f16) {
4502 // Extend to f32.
4503 VT = MVT::f32;
4504 Op = fpExtendHelper(Op, Chain, IsStrict, VT, DL: dl, DAG);
4505 }
4506
4507 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4508 if (N->getOpcode() == ISD::LROUND ||
4509 N->getOpcode() == ISD::STRICT_LROUND) {
4510 LC = RTLIB::getLROUND(VT);
4511 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lround input type!");
4512 } else if (N->getOpcode() == ISD::LRINT ||
4513 N->getOpcode() == ISD::STRICT_LRINT) {
4514 LC = RTLIB::getLRINT(RetVT: VT);
4515 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lrint input type!");
4516 } else if (N->getOpcode() == ISD::LLROUND ||
4517 N->getOpcode() == ISD::STRICT_LLROUND) {
4518 LC = RTLIB::getLLROUND(VT);
4519 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
4520 } else if (N->getOpcode() == ISD::LLRINT ||
4521 N->getOpcode() == ISD::STRICT_LLRINT) {
4522 LC = RTLIB::getLLRINT(RetVT: VT);
4523 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
4524 } else
4525 llvm_unreachable("Unexpected opcode!");
4526
4527 EVT RetVT = N->getValueType(ResNo: 0);
4528
4529 TargetLowering::MakeLibCallOptions CallOptions;
4530 CallOptions.setIsSigned(true);
4531 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
4532 Ops: Op, CallOptions, dl,
4533 Chain);
4534 SplitInteger(Op: Tmp.first, Lo, Hi);
4535
4536 if (N->isStrictFPOpcode())
4537 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4538}
4539
4540void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
4541 SDValue &Lo, SDValue &Hi) {
4542 assert(!N->isAtomic() && "Should have been a ATOMIC_LOAD?");
4543
4544 if (ISD::isNormalLoad(N)) {
4545 ExpandRes_NormalLoad(N, Lo, Hi);
4546 return;
4547 }
4548
4549 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
4550
4551 EVT VT = N->getValueType(ResNo: 0);
4552 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4553 SDValue Ch = N->getChain();
4554 SDValue Ptr = N->getBasePtr();
4555 ISD::LoadExtType ExtType = N->getExtensionType();
4556 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4557 AAMDNodes AAInfo = N->getAAInfo();
4558 SDLoc dl(N);
4559
4560 assert(NVT.isByteSized() && "Expanded type not byte sized!");
4561
4562 if (N->getMemoryVT().bitsLE(VT: NVT)) {
4563 EVT MemVT = N->getMemoryVT();
4564
4565 Lo = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), MemVT,
4566 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4567
4568 // Remember the chain.
4569 Ch = Lo.getValue(R: 1);
4570
4571 if (ExtType == ISD::SEXTLOAD) {
4572 // The high part is obtained by SRA'ing all but one of the bits of the
4573 // lo part.
4574 unsigned LoSize = Lo.getValueSizeInBits();
4575 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4576 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
4577 } else if (ExtType == ISD::ZEXTLOAD) {
4578 // The high part is just a zero.
4579 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4580 } else {
4581 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
4582 // The high part is undefined.
4583 Hi = DAG.getUNDEF(VT: NVT);
4584 }
4585 } else if (DAG.getDataLayout().isLittleEndian()) {
4586 // Little-endian - low bits are at low addresses.
4587 Lo = DAG.getLoad(VT: NVT, dl, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
4588 MMOFlags, AAInfo);
4589
4590 unsigned ExcessBits =
4591 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4592 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
4593
4594 // Increment the pointer to the other half.
4595 unsigned IncrementSize = NVT.getSizeInBits()/8;
4596 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4597 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr,
4598 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize), MemVT: NEVT,
4599 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4600
4601 // Build a factor node to remember that this load is independent of the
4602 // other one.
4603 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4604 N2: Hi.getValue(R: 1));
4605 } else {
4606 // Big-endian - high bits are at low addresses. Favor aligned loads at
4607 // the cost of some bit-fiddling.
4608 EVT MemVT = N->getMemoryVT();
4609 unsigned EBytes = MemVT.getStoreSize();
4610 unsigned IncrementSize = NVT.getSizeInBits()/8;
4611 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4612
4613 // Load both the high bits and maybe some of the low bits.
4614 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(),
4615 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(),
4616 BitWidth: MemVT.getSizeInBits() - ExcessBits),
4617 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4618
4619 // Increment the pointer to the other half.
4620 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4621 // Load the rest of the low bits.
4622 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: NVT, Chain: Ch, Ptr,
4623 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
4624 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
4625 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4626
4627 // Build a factor node to remember that this load is independent of the
4628 // other one.
4629 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4630 N2: Hi.getValue(R: 1));
4631
4632 if (ExcessBits < NVT.getSizeInBits()) {
4633 // Transfer low bits from the bottom of Hi to the top of Lo.
4634 Lo = DAG.getNode(
4635 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Lo,
4636 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
4637 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
4638 // Move high bits to the right position in Hi.
4639 Hi = DAG.getNode(Opcode: ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
4640 N1: Hi,
4641 N2: DAG.getShiftAmountConstant(
4642 Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
4643 }
4644 }
4645
4646 // Legalize the chain result - switch anything that used the old chain to
4647 // use the new one.
4648 ReplaceValueWith(From: SDValue(N, 1), To: Ch);
4649}
4650
4651void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
4652 SDValue &Lo, SDValue &Hi) {
4653 SDLoc dl(N);
4654 SDValue LL, LH, RL, RH;
4655 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4656 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4657
4658 SDNodeFlags Flags;
4659 if (N->getOpcode() == ISD::OR)
4660 Flags.setDisjoint(N->getFlags().hasDisjoint());
4661
4662 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LL, N2: RL, Flags);
4663 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LH, N2: RH, Flags);
4664}
4665
4666void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
4667 SDValue &Lo, SDValue &Hi) {
4668 EVT VT = N->getValueType(ResNo: 0);
4669 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4670 SDLoc dl(N);
4671
4672 SDValue LL, LH, RL, RH;
4673 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4674 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4675
4676 if (TLI.expandMUL(N, Lo, Hi, HiLoVT: NVT, DAG,
4677 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4678 LL, LH, RL, RH))
4679 return;
4680
4681 // If nothing else, we can make a libcall.
4682 RTLIB::Libcall LC = RTLIB::getMUL(VT);
4683 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
4684 if (LCImpl == RTLIB::Unsupported) {
4685 // Perform a wide multiplication where the wide type is the original VT and
4686 // the 4 parts are the split arguments.
4687 TLI.forceExpandMultiply(DAG, dl, /*Signed=*/false, Lo, Hi, LHS: LL, RHS: RL, HiLHS: LH, HiRHS: RH);
4688 return;
4689 }
4690
4691 // Note that we don't need to do a wide MUL here since we don't care about the
4692 // upper half of the result if it exceeds VT.
4693 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4694 TargetLowering::MakeLibCallOptions CallOptions;
4695 CallOptions.setIsSigned(true);
4696 SplitInteger(Op: TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
4697 Hi);
4698}
4699
4700void DAGTypeLegalizer::ExpandIntRes_READCOUNTER(SDNode *N, SDValue &Lo,
4701 SDValue &Hi) {
4702 SDLoc DL(N);
4703 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4704 SDVTList VTs = DAG.getVTList(VT1: NVT, VT2: NVT, VT3: MVT::Other);
4705 SDValue R = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N: N->getOperand(Num: 0));
4706 Lo = R.getValue(R: 0);
4707 Hi = R.getValue(R: 1);
4708 ReplaceValueWith(From: SDValue(N, 1), To: R.getValue(R: 2));
4709}
4710
4711void DAGTypeLegalizer::ExpandIntRes_AVG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4712 SDValue Result = TLI.expandAVG(N, DAG);
4713 SplitInteger(Op: Result, Lo, Hi);
4714}
4715
4716void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
4717 SDValue &Hi) {
4718 SDValue Result = TLI.expandAddSubSat(Node: N, DAG);
4719 SplitInteger(Op: Result, Lo, Hi);
4720}
4721
4722void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
4723 SDValue &Hi) {
4724 SDValue Result = TLI.expandShlSat(Node: N, DAG);
4725 SplitInteger(Op: Result, Lo, Hi);
4726}
4727
4728/// This performs an expansion of the integer result for a fixed point
4729/// multiplication. The default expansion performs rounding down towards
4730/// negative infinity, though targets that do care about rounding should specify
4731/// a target hook for rounding and provide their own expansion or lowering of
4732/// fixed point multiplication to be consistent with rounding.
4733void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
4734 SDValue &Hi) {
4735 SDLoc dl(N);
4736 EVT VT = N->getValueType(ResNo: 0);
4737 unsigned VTSize = VT.getScalarSizeInBits();
4738 SDValue LHS = N->getOperand(Num: 0);
4739 SDValue RHS = N->getOperand(Num: 1);
4740 uint64_t Scale = N->getConstantOperandVal(Num: 2);
4741 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
4742 N->getOpcode() == ISD::UMULFIXSAT);
4743 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
4744 N->getOpcode() == ISD::SMULFIXSAT);
4745
4746 // Handle special case when scale is equal to zero.
4747 if (!Scale) {
4748 SDValue Result;
4749 if (!Saturating) {
4750 Result = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS);
4751 } else {
4752 EVT BoolVT = getSetCCResultType(VT);
4753 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
4754 Result = DAG.getNode(Opcode: MulOp, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: BoolVT), N1: LHS, N2: RHS);
4755 SDValue Product = Result.getValue(R: 0);
4756 SDValue Overflow = Result.getValue(R: 1);
4757 if (Signed) {
4758 APInt MinVal = APInt::getSignedMinValue(numBits: VTSize);
4759 APInt MaxVal = APInt::getSignedMaxValue(numBits: VTSize);
4760 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT);
4761 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4762 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
4763 // Xor the inputs, if resulting sign bit is 0 the product will be
4764 // positive, else negative.
4765 SDValue Xor = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4766 SDValue ProdNeg = DAG.getSetCC(DL: dl, VT: BoolVT, LHS: Xor, RHS: Zero, Cond: ISD::SETLT);
4767 Result = DAG.getSelect(DL: dl, VT, Cond: ProdNeg, LHS: SatMin, RHS: SatMax);
4768 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: Result, RHS: Product);
4769 } else {
4770 // For unsigned multiplication, we only need to check the max since we
4771 // can't really overflow towards zero.
4772 APInt MaxVal = APInt::getMaxValue(numBits: VTSize);
4773 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4774 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: SatMax, RHS: Product);
4775 }
4776 }
4777 SplitInteger(Op: Result, Lo, Hi);
4778 return;
4779 }
4780
4781 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
4782 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
4783 assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
4784
4785 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4786 SDValue LL, LH, RL, RH;
4787 GetExpandedInteger(Op: LHS, Lo&: LL, Hi&: LH);
4788 GetExpandedInteger(Op: RHS, Lo&: RL, Hi&: RH);
4789 SmallVector<SDValue, 4> Result;
4790
4791 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
4792 if (!TLI.expandMUL_LOHI(Opcode: LoHiOp, VT, dl, LHS, RHS, Result, HiLoVT: NVT, DAG,
4793 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4794 LL, LH, RL, RH)) {
4795 Result.clear();
4796 Result.resize(N: 4);
4797
4798 SDValue LoTmp, HiTmp;
4799 TLI.forceExpandWideMUL(DAG, dl, Signed, LHS, RHS, Lo&: LoTmp, Hi&: HiTmp);
4800 SplitInteger(Op: LoTmp, Lo&: Result[0], Hi&: Result[1]);
4801 SplitInteger(Op: HiTmp, Lo&: Result[2], Hi&: Result[3]);
4802 }
4803 assert(Result.size() == 4 && "Unexpected number of partlets in the result");
4804
4805 unsigned NVTSize = NVT.getScalarSizeInBits();
4806 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
4807 "the size of the current value type");
4808
4809 // After getting the multiplication result in 4 parts, we need to perform a
4810 // shift right by the amount of the scale to get the result in that scale.
4811 //
4812 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
4813 // 128 bits that are cut into 4 32-bit parts:
4814 //
4815 // HH HL LH LL
4816 // |---32---|---32---|---32---|---32---|
4817 // 128 96 64 32 0
4818 //
4819 // |------VTSize-----|
4820 //
4821 // |NVTSize-|
4822 //
4823 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
4824 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
4825 // amount and get Lo and Hi using two funnel shifts. Or for the special case
4826 // when Scale is a multiple of NVTSize we can just pick the result without
4827 // shifting.
4828 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
4829 if (Scale % NVTSize) {
4830 SDValue ShiftAmount = DAG.getShiftAmountConstant(Val: Scale % NVTSize, VT: NVT, DL: dl);
4831 Lo = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 1], N2: Result[Part0],
4832 N3: ShiftAmount);
4833 Hi = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 2], N2: Result[Part0 + 1],
4834 N3: ShiftAmount);
4835 } else {
4836 Lo = Result[Part0];
4837 Hi = Result[Part0 + 1];
4838 }
4839
4840 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
4841 if (!Saturating)
4842 return;
4843
4844 // Can not overflow when there is no integer part.
4845 if (Scale == VTSize)
4846 return;
4847
4848 // To handle saturation we must check for overflow in the multiplication.
4849 //
4850 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
4851 // aren't all zeroes.
4852 //
4853 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
4854 // aren't all ones or all zeroes.
4855 //
4856 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
4857 // highest bit of HH determines saturation direction in the event of signed
4858 // saturation.
4859
4860 SDValue ResultHL = Result[2];
4861 SDValue ResultHH = Result[3];
4862
4863 SDValue SatMax, SatMin;
4864 SDValue NVTZero = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4865 SDValue NVTNeg1 = DAG.getAllOnesConstant(DL: dl, VT: NVT);
4866 EVT BoolNVT = getSetCCResultType(VT: NVT);
4867
4868 if (!Signed) {
4869 if (Scale < NVTSize) {
4870 // Overflow happened if ((HH | (HL >> Scale)) != 0).
4871 SDValue HLAdjusted =
4872 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4873 N2: DAG.getShiftAmountConstant(Val: Scale, VT: NVT, DL: dl));
4874 SDValue Tmp = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: HLAdjusted, N2: ResultHH);
4875 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: Tmp, RHS: NVTZero, Cond: ISD::SETNE);
4876 } else if (Scale == NVTSize) {
4877 // Overflow happened if (HH != 0).
4878 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETNE);
4879 } else if (Scale < VTSize) {
4880 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
4881 SDValue HLAdjusted =
4882 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4883 N2: DAG.getShiftAmountConstant(Val: Scale - NVTSize, VT: NVT, DL: dl));
4884 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: HLAdjusted, RHS: NVTZero, Cond: ISD::SETNE);
4885 } else
4886 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
4887 "(and saturation can't happen with Scale==VTSize).");
4888
4889 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Hi);
4890 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Lo);
4891 return;
4892 }
4893
4894 if (Scale < NVTSize) {
4895 // The number of overflow bits we can check are VTSize - Scale + 1 (we
4896 // include the sign bit). If these top bits are > 0, then we overflowed past
4897 // the max value. If these top bits are < -1, then we overflowed past the
4898 // min value. Otherwise, we did not overflow.
4899 unsigned OverflowBits = VTSize - Scale + 1;
4900 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
4901 "Extent of overflow bits must start within HL");
4902 SDValue HLHiMask = DAG.getConstant(
4903 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits - NVTSize), DL: dl, VT: NVT);
4904 SDValue HLLoMask = DAG.getConstant(
4905 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: VTSize - OverflowBits), DL: dl, VT: NVT);
4906 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
4907 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4908 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4909 SDValue HLUGT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLLoMask, Cond: ISD::SETUGT);
4910 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4911 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLUGT));
4912 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
4913 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4914 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4915 SDValue HLULT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLHiMask, Cond: ISD::SETULT);
4916 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4917 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLULT));
4918 } else if (Scale == NVTSize) {
4919 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
4920 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4921 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4922 SDValue HLNeg = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETLT);
4923 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4924 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLNeg));
4925 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
4926 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4927 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4928 SDValue HLPos = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETGE);
4929 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4930 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLPos));
4931 } else if (Scale < VTSize) {
4932 // This is similar to the case when we saturate if Scale < NVTSize, but we
4933 // only need to check HH.
4934 unsigned OverflowBits = VTSize - Scale + 1;
4935 SDValue HHHiMask = DAG.getConstant(
4936 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits), DL: dl, VT: NVT);
4937 SDValue HHLoMask = DAG.getConstant(
4938 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: NVTSize - OverflowBits), DL: dl, VT: NVT);
4939 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHLoMask, Cond: ISD::SETGT);
4940 SatMin = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHHiMask, Cond: ISD::SETLT);
4941 } else
4942 llvm_unreachable("Illegal scale for signed fixed point mul.");
4943
4944 // Saturate to signed maximum.
4945 APInt MaxHi = APInt::getSignedMaxValue(numBits: NVTSize);
4946 APInt MaxLo = APInt::getAllOnes(numBits: NVTSize);
4947 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxHi, DL: dl, VT: NVT), RHS: Hi);
4948 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxLo, DL: dl, VT: NVT), RHS: Lo);
4949 // Saturate to signed minimum.
4950 APInt MinHi = APInt::getSignedMinValue(numBits: NVTSize);
4951 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: DAG.getConstant(Val: MinHi, DL: dl, VT: NVT), RHS: Hi);
4952 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: NVTZero, RHS: Lo);
4953}
4954
4955void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
4956 SDValue &Hi) {
4957 SDLoc dl(N);
4958 // Try expanding in the existing type first.
4959 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: N->getOperand(Num: 0),
4960 RHS: N->getOperand(Num: 1),
4961 Scale: N->getConstantOperandVal(Num: 2), DAG);
4962
4963 if (!Res)
4964 Res = earlyExpandDIVFIX(N, LHS: N->getOperand(Num: 0), RHS: N->getOperand(Num: 1),
4965 Scale: N->getConstantOperandVal(Num: 2), TLI, DAG);
4966 SplitInteger(Op: Res, Lo, Hi);
4967}
4968
4969void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
4970 SDValue &Lo, SDValue &Hi) {
4971 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
4972 "Node has unexpected Opcode");
4973 SDValue LHS = Node->getOperand(Num: 0);
4974 SDValue RHS = Node->getOperand(Num: 1);
4975 SDLoc dl(Node);
4976
4977 SDValue Ovf;
4978
4979 bool IsAdd = Node->getOpcode() == ISD::SADDO;
4980 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
4981
4982 bool HasCarryOp = TLI.isOperationLegalOrCustom(
4983 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
4984
4985 if (HasCarryOp) {
4986 // Expand the subcomponents.
4987 SDValue LHSL, LHSH, RHSL, RHSH;
4988 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
4989 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
4990 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: Node->getValueType(ResNo: 1));
4991
4992 Lo = DAG.getNode(Opcode: IsAdd ? ISD::UADDO : ISD::USUBO, DL: dl, VTList, Ops: {LHSL, RHSL});
4993 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4994
4995 Ovf = Hi.getValue(R: 1);
4996 } else {
4997 // Expand the result by simply replacing it with the equivalent
4998 // non-overflow-checking operation.
4999 SDValue Sum = DAG.getNode(Opcode: Node->getOpcode() == ISD::SADDO ?
5000 ISD::ADD : ISD::SUB, DL: dl, VT: LHS.getValueType(),
5001 N1: LHS, N2: RHS);
5002 SplitInteger(Op: Sum, Lo, Hi);
5003
5004 // Compute the overflow.
5005 //
5006 // LHSSign -> LHS < 0
5007 // RHSSign -> RHS < 0
5008 // SumSign -> Sum < 0
5009 //
5010 // Add:
5011 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
5012 // Sub:
5013 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
5014 //
5015 // To get better codegen we can rewrite this by doing bitwise math on
5016 // the integers and extract the final sign bit at the end. So the
5017 // above becomes:
5018 //
5019 // Add:
5020 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
5021 // Sub:
5022 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
5023 //
5024 // NOTE: This is different than the expansion we do in expandSADDSUBO
5025 // because it is more costly to implement the same overflow predicate with
5026 // SETCC nodes when the integers are split.
5027 EVT VT = LHS.getValueType();
5028 SDValue SignsMatch = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
5029 if (IsAdd)
5030 SignsMatch = DAG.getNOT(DL: dl, Val: SignsMatch, VT);
5031
5032 SDValue SumSignNE = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: Sum);
5033 Ovf = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: SignsMatch, N2: SumSignNE);
5034 EVT OType = Node->getValueType(ResNo: 1);
5035 Ovf = DAG.getSetCC(DL: dl, VT: OType, LHS: Ovf, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETLT);
5036 }
5037
5038 // Use the calculated overflow everywhere.
5039 ReplaceValueWith(From: SDValue(Node, 1), To: Ovf);
5040}
5041
5042void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
5043 SDValue &Lo, SDValue &Hi) {
5044 EVT VT = N->getValueType(ResNo: 0);
5045 SDLoc dl(N);
5046 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5047
5048 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5049 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5050 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5051 return;
5052 }
5053
5054 RTLIB::Libcall LC = RTLIB::getSDIV(VT);
5055 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
5056
5057 TargetLowering::MakeLibCallOptions CallOptions;
5058 CallOptions.setIsSigned(true);
5059 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5060}
5061
5062void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
5063 SDValue &Hi) {
5064 SDLoc dl(N);
5065 SDValue Shiftee = N->getOperand(Num: 0);
5066 EVT VT = Shiftee.getValueType();
5067 SDValue ShAmt = N->getOperand(Num: 1);
5068 EVT ShAmtVT = ShAmt.getValueType();
5069
5070 EVT LoadVT = VT;
5071 do {
5072 LoadVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: LoadVT);
5073 } while (!TLI.isTypeLegal(VT: LoadVT));
5074
5075 const unsigned ShiftUnitInBits = LoadVT.getStoreSizeInBits();
5076 assert(ShiftUnitInBits <= VT.getScalarSizeInBits());
5077 assert(isPowerOf2_32(ShiftUnitInBits) &&
5078 "Shifting unit is not a a power of two!");
5079
5080 const bool IsOneStepShift =
5081 DAG.computeKnownBits(Op: ShAmt).countMinTrailingZeros() >=
5082 Log2_32(Value: ShiftUnitInBits);
5083
5084 // If we can't do it as one step, we'll have two uses of shift amount,
5085 // and thus must freeze it.
5086 if (!IsOneStepShift)
5087 ShAmt = DAG.getFreeze(V: ShAmt);
5088
5089 unsigned VTBitWidth = VT.getScalarSizeInBits();
5090 assert(VTBitWidth % 8 == 0 && "Shifting a not byte multiple value?");
5091 unsigned VTByteWidth = VTBitWidth / 8;
5092 assert(isPowerOf2_32(VTByteWidth) &&
5093 "Shiftee type size is not a power of two!");
5094 unsigned StackSlotByteWidth = 2 * VTByteWidth;
5095 unsigned StackSlotBitWidth = 8 * StackSlotByteWidth;
5096 EVT StackSlotVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StackSlotBitWidth);
5097
5098 // Get a temporary stack slot 2x the width of our VT.
5099 // FIXME: reuse stack slots?
5100 Align StackAlign = DAG.getReducedAlign(VT: StackSlotVT, /*UseABI=*/false);
5101 SDValue StackPtr =
5102 DAG.CreateStackTemporary(Bytes: StackSlotVT.getStoreSize(), Alignment: StackAlign);
5103 EVT PtrTy = StackPtr.getValueType();
5104 SDValue Ch = DAG.getEntryNode();
5105
5106 MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
5107 MF&: DAG.getMachineFunction(),
5108 FI: cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex());
5109
5110 // Extend the value, that is being shifted, to the entire stack slot's width.
5111 SDValue Init;
5112 if (N->getOpcode() != ISD::SHL) {
5113 unsigned WideningOpc =
5114 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5115 Init = DAG.getNode(Opcode: WideningOpc, DL: dl, VT: StackSlotVT, Operand: Shiftee);
5116 } else {
5117 // For left-shifts, pad the Shiftee's LSB with zeros to twice it's width.
5118 SDValue AllZeros = DAG.getConstant(Val: 0, DL: dl, VT);
5119 Init = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: StackSlotVT, N1: AllZeros, N2: Shiftee);
5120 }
5121 // And spill it into the stack slot.
5122 Ch = DAG.getStore(Chain: Ch, dl, Val: Init, Ptr: StackPtr, PtrInfo: StackPtrInfo, Alignment: StackAlign);
5123
5124 // Now, compute the full-byte offset into stack slot from where we can load.
5125 // We have shift amount, which is in bits. Offset should point to an aligned
5126 // address.
5127 SDNodeFlags Flags;
5128 Flags.setExact(IsOneStepShift);
5129 SDValue SrlTmp = DAG.getNode(
5130 Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: ShAmt,
5131 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT), Flags);
5132 SDValue BitOffset =
5133 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: ShAmtVT, N1: SrlTmp,
5134 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT));
5135
5136 SDValue ByteOffset =
5137 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: BitOffset,
5138 N2: DAG.getConstant(Val: 3, DL: dl, VT: ShAmtVT), Flags: SDNodeFlags::Exact);
5139 // And clamp it, because OOB load is an immediate UB,
5140 // while shift overflow would have *just* been poison.
5141 ByteOffset = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ByteOffset,
5142 N2: DAG.getConstant(Val: VTByteWidth - 1, DL: dl, VT: ShAmtVT));
5143 // We have exactly two strategies on indexing into stack slot here:
5144 // 1. upwards starting from the beginning of the slot
5145 // 2. downwards starting from the middle of the slot
5146 // On little-endian machine, we pick 1. for right shifts and 2. for left-shift
5147 // and vice versa on big-endian machine.
5148 bool WillIndexUpwards = N->getOpcode() != ISD::SHL;
5149 if (DAG.getDataLayout().isBigEndian())
5150 WillIndexUpwards = !WillIndexUpwards;
5151
5152 SDValue AdjStackPtr;
5153 if (WillIndexUpwards) {
5154 AdjStackPtr = StackPtr;
5155 } else {
5156 AdjStackPtr = DAG.getMemBasePlusOffset(
5157 Base: StackPtr, Offset: DAG.getConstant(Val: VTByteWidth, DL: dl, VT: PtrTy), DL: dl);
5158 ByteOffset = DAG.getNegative(Val: ByteOffset, DL: dl, VT: ShAmtVT);
5159 }
5160
5161 // Get the pointer somewhere into the stack slot from which we need to load.
5162 ByteOffset = DAG.getSExtOrTrunc(Op: ByteOffset, DL: dl, VT: PtrTy);
5163 AdjStackPtr = DAG.getMemBasePlusOffset(Base: AdjStackPtr, Offset: ByteOffset, DL: dl);
5164
5165 // And load it! While the load is not legal, legalizing it is obvious.
5166 SDValue Res =
5167 DAG.getLoad(VT, dl, Chain: Ch, Ptr: AdjStackPtr,
5168 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
5169 Alignment: commonAlignment(A: StackAlign, Offset: LoadVT.getStoreSize()));
5170
5171 // If we may still have a remaining bits to shift by, do so now.
5172 if (!IsOneStepShift) {
5173 SDValue ShAmtRem =
5174 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ShAmt,
5175 N2: DAG.getConstant(Val: ShiftUnitInBits - 1, DL: dl, VT: ShAmtVT));
5176 Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT, N1: Res, N2: ShAmtRem);
5177 }
5178
5179 // Finally, split the computed value.
5180 SplitInteger(Op: Res, Lo, Hi);
5181}
5182
5183void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
5184 SDValue &Lo, SDValue &Hi) {
5185 EVT VT = N->getValueType(ResNo: 0);
5186 unsigned Opc = N->getOpcode();
5187 SDLoc dl(N);
5188
5189 // If we can emit an efficient shift operation, do so now. Check to see if
5190 // the RHS is a constant.
5191 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1)))
5192 return ExpandShiftByConstant(N, Amt: CN->getAPIntValue(), Lo, Hi);
5193
5194 // If we can determine that the high bit of the shift is zero or one, even if
5195 // the low bits are variable, emit this shift in an optimized form.
5196 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
5197 return;
5198
5199 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
5200 unsigned PartsOpc;
5201 if (Opc == ISD::SHL) {
5202 PartsOpc = ISD::SHL_PARTS;
5203 } else if (Opc == ISD::SRL) {
5204 PartsOpc = ISD::SRL_PARTS;
5205 } else {
5206 assert(Opc == ISD::SRA && "Unknown shift!");
5207 PartsOpc = ISD::SRA_PARTS;
5208 }
5209
5210 // Next check to see if the target supports this SHL_PARTS operation or if it
5211 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
5212 // size, but create a libcall instead.
5213 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5214 TargetLowering::LegalizeAction Action = TLI.getOperationAction(Op: PartsOpc, VT: NVT);
5215 const bool LegalOrCustom =
5216 (Action == TargetLowering::Legal && TLI.isTypeLegal(VT: NVT)) ||
5217 Action == TargetLowering::Custom;
5218
5219 unsigned ExpansionFactor = 1;
5220 // That VT->NVT expansion is one step. But will we re-expand NVT?
5221 for (EVT TmpVT = NVT;;) {
5222 EVT NewTMPVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: TmpVT);
5223 if (NewTMPVT == TmpVT)
5224 break;
5225 TmpVT = NewTMPVT;
5226 ++ExpansionFactor;
5227 }
5228
5229 TargetLowering::ShiftLegalizationStrategy S =
5230 TLI.preferredShiftLegalizationStrategy(DAG, N, ExpansionFactor);
5231
5232 if (S == TargetLowering::ShiftLegalizationStrategy::ExpandThroughStack)
5233 return ExpandIntRes_ShiftThroughStack(N, Lo, Hi);
5234
5235 if (LegalOrCustom &&
5236 S != TargetLowering::ShiftLegalizationStrategy::LowerToLibcall) {
5237 // Expand the subcomponents.
5238 SDValue LHSL, LHSH;
5239 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
5240 EVT VT = LHSL.getValueType();
5241
5242 // If the shift amount operand is coming from a vector legalization it may
5243 // have an illegal type. Fix that first by casting the operand, otherwise
5244 // the new SHL_PARTS operation would need further legalization.
5245 SDValue ShiftOp = N->getOperand(Num: 1);
5246 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
5247 if (ShiftOp.getValueType() != ShiftTy)
5248 ShiftOp = DAG.getZExtOrTrunc(Op: ShiftOp, DL: dl, VT: ShiftTy);
5249
5250 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
5251 Lo = DAG.getNode(Opcode: PartsOpc, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5252 Hi = Lo.getValue(R: 1);
5253 return;
5254 }
5255
5256 // Otherwise, emit a libcall.
5257 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5258 bool isSigned;
5259 if (Opc == ISD::SHL) {
5260 isSigned = false; /*sign irrelevant*/
5261 LC = RTLIB::getSHL(VT);
5262 } else if (Opc == ISD::SRL) {
5263 isSigned = false;
5264 LC = RTLIB::getSRL(VT);
5265 } else {
5266 assert(Opc == ISD::SRA && "Unknown shift!");
5267 isSigned = true;
5268 LC = RTLIB::getSRA(VT);
5269 }
5270
5271 if (RTLIB::LibcallImpl LibcallImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
5272 EVT ShAmtTy =
5273 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
5274 SDValue ShAmt = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl, VT: ShAmtTy);
5275 SDValue Ops[2] = {N->getOperand(Num: 0), ShAmt};
5276 TargetLowering::MakeLibCallOptions CallOptions;
5277 CallOptions.setIsSigned(isSigned);
5278 SplitInteger(
5279 Op: TLI.makeLibCall(DAG, LibcallImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
5280 Hi);
5281 return;
5282 }
5283
5284 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
5285 llvm_unreachable("Unsupported shift!");
5286}
5287
5288void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
5289 SDValue &Lo, SDValue &Hi) {
5290 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5291 SDLoc dl(N);
5292 SDValue Op = N->getOperand(Num: 0);
5293 if (Op.getValueType().bitsLE(VT: NVT)) {
5294 // The low part is sign extension of the input (degenerates to a copy).
5295 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5296 // The high part is obtained by SRA'ing all but one of the bits of low part.
5297 unsigned LoSize = NVT.getSizeInBits();
5298 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
5299 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
5300 } else {
5301 // For example, extension of an i48 to an i64. The operand type necessarily
5302 // promotes to the result type, so will end up being expanded too.
5303 assert(getTypeAction(Op.getValueType()) ==
5304 TargetLowering::TypePromoteInteger &&
5305 "Only know how to promote this result!");
5306 SDValue Res = GetPromotedInteger(Op);
5307 assert(Res.getValueType() == N->getValueType(0) &&
5308 "Operand over promoted?");
5309 // Split the promoted operand. This will simplify when it is expanded.
5310 SplitInteger(Op: Res, Lo, Hi);
5311 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5312 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5313 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5314 BitWidth: ExcessBits)));
5315 }
5316}
5317
5318void DAGTypeLegalizer::
5319ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
5320 SDLoc dl(N);
5321 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5322 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
5323
5324 if (EVT.bitsLE(VT: Lo.getValueType())) {
5325 // sext_inreg the low part if needed.
5326 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Lo.getValueType(), N1: Lo,
5327 N2: N->getOperand(Num: 1));
5328
5329 // The high part gets the sign extension from the lo-part. This handles
5330 // things like sextinreg V:i64 from i8.
5331 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: Hi.getValueType(), N1: Lo,
5332 N2: DAG.getShiftAmountConstant(Val: Hi.getValueSizeInBits() - 1,
5333 VT: Hi.getValueType(), DL: dl));
5334 } else {
5335 // For example, extension of an i48 to an i64. Leave the low part alone,
5336 // sext_inreg the high part.
5337 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
5338 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5339 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5340 BitWidth: ExcessBits)));
5341 }
5342}
5343
5344void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
5345 SDValue &Lo, SDValue &Hi) {
5346 EVT VT = N->getValueType(ResNo: 0);
5347 SDLoc dl(N);
5348 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5349
5350 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5351 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5352 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5353 return;
5354 }
5355
5356 RTLIB::Libcall LC = RTLIB::getSREM(VT);
5357 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
5358
5359 TargetLowering::MakeLibCallOptions CallOptions;
5360 CallOptions.setIsSigned(true);
5361 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5362}
5363
5364void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
5365 SDValue &Lo, SDValue &Hi) {
5366 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5367 SDValue InOp = N->getOperand(Num: 0);
5368 EVT InVT = InOp.getValueType();
5369 SDLoc dl(N);
5370 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: InOp);
5371 Hi = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: InVT, N1: InOp,
5372 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits(), VT: InVT, DL: dl));
5373 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Hi);
5374}
5375
5376void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
5377 SDValue &Lo, SDValue &Hi) {
5378 EVT VT = N->getValueType(ResNo: 0);
5379 SDLoc dl(N);
5380
5381 if (N->getOpcode() == ISD::UMULO) {
5382 // This section expands the operation into the following sequence of
5383 // instructions. `iNh` here refers to a type which has half the bit width of
5384 // the type the original operation operated on.
5385 //
5386 // %0 = %LHS.HI != 0 && %RHS.HI != 0
5387 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
5388 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
5389 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
5390 // %4 = add iNh %1.0, %2.0 as iN
5391 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
5392 //
5393 // %lo = %3.LO
5394 // %hi = %5.0
5395 // %ovf = %0 || %1.1 || %2.1 || %5.1
5396 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
5397 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
5398 GetExpandedInteger(Op: LHS, Lo&: LHSLow, Hi&: LHSHigh);
5399 GetExpandedInteger(Op: RHS, Lo&: RHSLow, Hi&: RHSHigh);
5400 EVT HalfVT = LHSLow.getValueType();
5401 EVT BitVT = N->getValueType(ResNo: 1);
5402 SDVTList VTHalfWithO = DAG.getVTList(VT1: HalfVT, VT2: BitVT);
5403
5404 SDValue HalfZero = DAG.getConstant(Val: 0, DL: dl, VT: HalfVT);
5405 SDValue Overflow = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BitVT,
5406 N1: DAG.getSetCC(DL: dl, VT: BitVT, LHS: LHSHigh, RHS: HalfZero, Cond: ISD::SETNE),
5407 N2: DAG.getSetCC(DL: dl, VT: BitVT, LHS: RHSHigh, RHS: HalfZero, Cond: ISD::SETNE));
5408
5409 SDValue One = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: LHSHigh, N2: RHSLow);
5410 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: One.getValue(R: 1));
5411
5412 SDValue Two = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: RHSHigh, N2: LHSLow);
5413 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Two.getValue(R: 1));
5414
5415 SDValue HighSum = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: HalfVT, N1: One, N2: Two);
5416
5417 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
5418 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
5419 // operation recursively legalized?).
5420 //
5421 // Many backends understand this pattern and will convert into LOHI
5422 // themselves, if applicable.
5423 SDValue Three = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT,
5424 N1: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: LHSLow),
5425 N2: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: RHSLow));
5426 SplitInteger(Op: Three, Lo, Hi);
5427
5428 Hi = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList: VTHalfWithO, N1: Hi, N2: HighSum);
5429 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Hi.getValue(R: 1));
5430 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5431 return;
5432 }
5433
5434 Type *RetTy = VT.getTypeForEVT(Context&: *DAG.getContext());
5435 EVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
5436 Type *PtrTy = PtrVT.getTypeForEVT(Context&: *DAG.getContext());
5437
5438 // Replace this with a libcall that will check overflow.
5439 RTLIB::Libcall LC = RTLIB::getMULO(VT);
5440 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
5441
5442 // If we don't have the libcall or if the function we are compiling is the
5443 // implementation of the expected libcall (avoid inf-loop), expand inline.
5444 if (LCImpl == RTLIB::Unsupported ||
5445 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LCImpl) ==
5446 DAG.getMachineFunction().getName()) {
5447 // FIXME: This is not an optimal expansion, but better than crashing.
5448 SDValue MulLo, MulHi;
5449 TLI.forceExpandWideMUL(DAG, dl, /*Signed=*/true, LHS: N->getOperand(Num: 0),
5450 RHS: N->getOperand(Num: 1), Lo&: MulLo, Hi&: MulHi);
5451 SDValue SRA = DAG.getNode(
5452 Opcode: ISD::SRA, DL: dl, VT, N1: MulLo,
5453 N2: DAG.getShiftAmountConstant(Val: VT.getScalarSizeInBits() - 1, VT, DL: dl));
5454 SDValue Overflow =
5455 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: MulHi, RHS: SRA, Cond: ISD::SETNE);
5456 SplitInteger(Op: MulLo, Lo, Hi);
5457 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5458 return;
5459 }
5460
5461 SDValue Temp = DAG.CreateStackTemporary(VT: PtrVT);
5462 // Temporary for the overflow value, default it to zero.
5463 SDValue Chain =
5464 DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT), Ptr: Temp,
5465 PtrInfo: MachinePointerInfo());
5466
5467 TargetLowering::ArgListTy Args;
5468 for (const SDValue &Op : N->op_values()) {
5469 EVT ArgVT = Op.getValueType();
5470 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
5471 TargetLowering::ArgListEntry Entry(Op, ArgTy);
5472 Entry.IsSExt = true;
5473 Entry.IsZExt = false;
5474 Args.push_back(x: Entry);
5475 }
5476
5477 // Also pass the address of the overflow check.
5478 TargetLowering::ArgListEntry Entry(
5479 Temp, PointerType::getUnqual(C&: PtrTy->getContext()));
5480 Entry.IsSExt = true;
5481 Entry.IsZExt = false;
5482 Args.push_back(x: Entry);
5483
5484 SDValue Func = DAG.getExternalSymbol(LCImpl, VT: PtrVT);
5485
5486 TargetLowering::CallLoweringInfo CLI(DAG);
5487 CLI.setDebugLoc(dl)
5488 .setChain(Chain)
5489 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
5490 Target: Func, ArgsList: std::move(Args))
5491 .setSExtResult();
5492
5493 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
5494
5495 SplitInteger(Op: CallInfo.first, Lo, Hi);
5496 SDValue Temp2 =
5497 DAG.getLoad(VT: PtrVT, dl, Chain: CallInfo.second, Ptr: Temp, PtrInfo: MachinePointerInfo());
5498 SDValue Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Temp2,
5499 RHS: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT),
5500 Cond: ISD::SETNE);
5501 // Use the overflow from the libcall everywhere.
5502 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
5503}
5504
5505void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
5506 SDValue &Lo, SDValue &Hi) {
5507 EVT VT = N->getValueType(ResNo: 0);
5508 SDLoc dl(N);
5509 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5510
5511 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5512 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5513 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5514 return;
5515 }
5516
5517 // Try to expand UDIV by constant.
5518 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5519 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5520 // Only if the new type is legal.
5521 if (isTypeLegal(VT: NVT)) {
5522 SDValue InL, InH;
5523 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5524 SmallVector<SDValue> Result;
5525 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5526 Lo = Result[0];
5527 Hi = Result[1];
5528 return;
5529 }
5530 }
5531 }
5532
5533 RTLIB::Libcall LC = RTLIB::getUDIV(VT);
5534 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
5535
5536 TargetLowering::MakeLibCallOptions CallOptions;
5537 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5538}
5539
5540void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
5541 SDValue &Lo, SDValue &Hi) {
5542 EVT VT = N->getValueType(ResNo: 0);
5543 SDLoc dl(N);
5544 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5545
5546 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5547 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5548 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5549 return;
5550 }
5551
5552 // Try to expand UREM by constant.
5553 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5554 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5555 // Only if the new type is legal.
5556 if (isTypeLegal(VT: NVT)) {
5557 SDValue InL, InH;
5558 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5559 SmallVector<SDValue> Result;
5560 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5561 Lo = Result[0];
5562 Hi = Result[1];
5563 return;
5564 }
5565 }
5566 }
5567
5568 RTLIB::Libcall LC = RTLIB::getUREM(VT);
5569 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
5570
5571 TargetLowering::MakeLibCallOptions CallOptions;
5572 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5573}
5574
5575void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
5576 SDValue &Lo, SDValue &Hi) {
5577 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5578 SDLoc dl(N);
5579 SDValue Op = N->getOperand(Num: 0);
5580 if (Op.getValueType().bitsLE(VT: NVT)) {
5581 // The low part is zero extension of the input (degenerates to a copy).
5582 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5583 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // The high part is just a zero.
5584 } else {
5585 // For example, extension of an i48 to an i64. The operand type necessarily
5586 // promotes to the result type, so will end up being expanded too.
5587 assert(getTypeAction(Op.getValueType()) ==
5588 TargetLowering::TypePromoteInteger &&
5589 "Only know how to promote this result!");
5590 SDValue Res = GetPromotedInteger(Op);
5591 assert(Res.getValueType() == N->getValueType(0) &&
5592 "Operand over promoted?");
5593 // Split the promoted operand. This will simplify when it is expanded.
5594 SplitInteger(Op: Res, Lo, Hi);
5595 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5596 Hi = DAG.getZeroExtendInReg(Op: Hi, DL: dl,
5597 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
5598 BitWidth: ExcessBits));
5599 }
5600}
5601
5602void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
5603 SDValue &Lo, SDValue &Hi) {
5604 SDLoc dl(N);
5605 EVT VT = cast<AtomicSDNode>(Val: N)->getMemoryVT();
5606 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::i1, VT3: MVT::Other);
5607 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
5608 SDValue Swap = DAG.getAtomicCmpSwap(
5609 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
5610 MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(), VTs, Chain: N->getOperand(Num: 0),
5611 Ptr: N->getOperand(Num: 1), Cmp: Zero, Swp: Zero, MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5612
5613 ReplaceValueWith(From: SDValue(N, 0), To: Swap.getValue(R: 0));
5614 ReplaceValueWith(From: SDValue(N, 1), To: Swap.getValue(R: 2));
5615}
5616
5617void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
5618 SDValue &Lo, SDValue &Hi) {
5619 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
5620 // both halves independently.
5621 SDValue Res = TLI.expandVecReduce(Node: N, DAG);
5622 SplitInteger(Op: Res, Lo, Hi);
5623}
5624
5625void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
5626 SDValue &Lo, SDValue &Hi) {
5627 // Delegate to funnel-shift expansion.
5628 SDLoc DL(N);
5629 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR;
5630 SDValue Res = DAG.getNode(Opcode, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
5631 N2: N->getOperand(Num: 0), N3: N->getOperand(Num: 1));
5632 SplitInteger(Op: Res, Lo, Hi);
5633}
5634
5635void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
5636 SDValue &Hi) {
5637 // Values numbered from least significant to most significant.
5638 SDValue In1, In2, In3, In4;
5639 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: In3, Hi&: In4);
5640 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: In1, Hi&: In2);
5641 EVT HalfVT = In1.getValueType();
5642
5643 SDLoc DL(N);
5644 unsigned Opc = N->getOpcode();
5645 SDValue ShAmt = N->getOperand(Num: 2);
5646 EVT ShAmtVT = ShAmt.getValueType();
5647 EVT ShAmtCCVT = getSetCCResultType(VT: ShAmtVT);
5648
5649 // If the shift amount is at least half the bitwidth, swap the inputs.
5650 unsigned HalfVTBits = HalfVT.getScalarSizeInBits();
5651 SDValue AndNode = DAG.getNode(Opcode: ISD::AND, DL, VT: ShAmtVT, N1: ShAmt,
5652 N2: DAG.getConstant(Val: HalfVTBits, DL, VT: ShAmtVT));
5653 SDValue Cond =
5654 DAG.getSetCC(DL, VT: ShAmtCCVT, LHS: AndNode, RHS: DAG.getConstant(Val: 0, DL, VT: ShAmtVT),
5655 Cond: Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ);
5656
5657 // Expand to a pair of funnel shifts.
5658 EVT NewShAmtVT = TLI.getShiftAmountTy(LHSTy: HalfVT, DL: DAG.getDataLayout());
5659 SDValue NewShAmt = DAG.getAnyExtOrTrunc(Op: ShAmt, DL, VT: NewShAmtVT);
5660
5661 SDValue Select1 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In1, N3: In2);
5662 SDValue Select2 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In2, N3: In3);
5663 SDValue Select3 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In3, N3: In4);
5664 Lo = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select2, N2: Select1, N3: NewShAmt);
5665 Hi = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select3, N2: Select2, N3: NewShAmt);
5666}
5667
5668void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo, SDValue &Hi) {
5669 if (N->getOpcode() != ISD::CLMUL) {
5670 SDValue Res = TLI.expandCLMUL(N, DAG);
5671 return SplitInteger(Op: Res, Lo, Hi);
5672 }
5673
5674 SDValue LL, LH, RL, RH;
5675 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
5676 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
5677 EVT HalfVT = LL.getValueType();
5678 SDLoc DL(N);
5679
5680 // The low bits are a direct CLMUL of the the low bits.
5681 Lo = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RL);
5682
5683 // We compute two Hi-Lo cross-products, XOR them, and XOR it with the overflow
5684 // of the CLMUL of the low bits (given by CLMULH of the low bits) to yield the
5685 // final high bits.
5686 SDValue LoH = DAG.getNode(Opcode: ISD::CLMULH, DL, VT: HalfVT, N1: LL, N2: RL);
5687 SDValue HiLoCross1 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RH);
5688 SDValue HiLoCross2 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LH, N2: RL);
5689 SDValue HiLoCross = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: HiLoCross1, N2: HiLoCross2);
5690 Hi = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: LoH, N2: HiLoCross);
5691}
5692
5693void DAGTypeLegalizer::ExpandIntRes_PEXT(SDNode *N, SDValue &Lo, SDValue &Hi) {
5694 SDValue Res = TLI.expandPEXT(N, DAG);
5695 SplitInteger(Op: Res, Lo, Hi);
5696}
5697
5698void DAGTypeLegalizer::ExpandIntRes_PDEP(SDNode *N, SDValue &Lo, SDValue &Hi) {
5699 SDValue Res = TLI.expandPDEP(N, DAG);
5700 SplitInteger(Op: Res, Lo, Hi);
5701}
5702
5703void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
5704 SDValue &Hi) {
5705 EVT VT = N->getValueType(ResNo: 0);
5706 EVT HalfVT =
5707 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: N->getValueSizeInBits(ResNo: 0) / 2);
5708 SDLoc dl(N);
5709
5710 // We assume VSCALE(1) fits into a legal integer.
5711 APInt One(HalfVT.getSizeInBits(), 1);
5712 SDValue VScaleBase = DAG.getVScale(DL: dl, VT: HalfVT, MulImm: One);
5713 VScaleBase = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: VScaleBase);
5714 SDValue Res = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: VScaleBase, N2: N->getOperand(Num: 0));
5715 SplitInteger(Op: Res, Lo, Hi);
5716}
5717
5718void DAGTypeLegalizer::ExpandIntRes_READ_REGISTER(SDNode *N, SDValue &Lo,
5719 SDValue &Hi) {
5720 const Function &Fn = DAG.getMachineFunction().getFunction();
5721 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
5722 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
5723 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
5724 EVT LoVT, HiVT;
5725 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: N->getValueType(ResNo: 0));
5726 Lo = DAG.getPOISON(VT: LoVT);
5727 Hi = DAG.getPOISON(VT: HiVT);
5728}
5729
5730void DAGTypeLegalizer::ExpandIntRes_CTTZ_ELTS(SDNode *N, SDValue &Lo,
5731 SDValue &Hi) {
5732 // Assume that the maximum number of vector elements fits in getVectorIdxTy
5733 // and expand to that.
5734 EVT VT = N->getSimpleValueType(ResNo: 0);
5735 EVT IdxVT = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
5736 assert(IdxVT.bitsLT(VT) &&
5737 "VectorIdxTy should be smaller than type to be expanded?");
5738
5739 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: IdxVT, Operand: N->getOperand(Num: 0));
5740 Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: SDLoc(N), VT, Operand: Res);
5741 SplitInteger(Op: Res, Lo, Hi);
5742}
5743
5744//===----------------------------------------------------------------------===//
5745// Integer Operand Expansion
5746//===----------------------------------------------------------------------===//
5747
5748/// ExpandIntegerOperand - This method is called when the specified operand of
5749/// the specified node is found to need expansion. At this point, all of the
5750/// result types of the node are known to be legal, but other operands of the
5751/// node may need promotion or expansion as well as the specified one.
5752bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
5753 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG));
5754 SDValue Res = SDValue();
5755
5756 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false))
5757 return false;
5758
5759 switch (N->getOpcode()) {
5760 default:
5761 #ifndef NDEBUG
5762 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
5763 N->dump(&DAG); dbgs() << "\n";
5764 #endif
5765 report_fatal_error(reason: "Do not know how to expand this operator's operand!");
5766
5767 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
5768 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
5769 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
5770 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
5771 case ISD::FAKE_USE:
5772 Res = ExpandOp_FAKE_USE(N);
5773 break;
5774 case ISD::LOOP_DEPENDENCE_RAW_MASK:
5775 case ISD::LOOP_DEPENDENCE_WAR_MASK:
5776 Res = TLI.expandLoopDependenceMask(N, DAG);
5777 break;
5778 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
5779 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
5780 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
5781 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
5782 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
5783 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
5784 case ISD::STRICT_SINT_TO_FP:
5785 case ISD::SINT_TO_FP:
5786 case ISD::STRICT_UINT_TO_FP:
5787 case ISD::UINT_TO_FP: Res = ExpandIntOp_XINT_TO_FP(N); break;
5788 case ISD::STORE: Res = ExpandIntOp_STORE(N: cast<StoreSDNode>(Val: N), OpNo); break;
5789 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
5790
5791 case ISD::SHL:
5792 case ISD::SRA:
5793 case ISD::SRL:
5794 case ISD::ROTL:
5795 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
5796 case ISD::RETURNADDR:
5797 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
5798
5799 case ISD::SCMP:
5800 case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
5801
5802 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
5803 case ISD::STACKMAP:
5804 Res = ExpandIntOp_STACKMAP(N, OpNo);
5805 break;
5806 case ISD::PATCHPOINT:
5807 Res = ExpandIntOp_PATCHPOINT(N, OpNo);
5808 break;
5809 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
5810 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
5811 Res = ExpandIntOp_VP_STRIDED(N, OpNo);
5812 break;
5813 case ISD::WRITE_REGISTER:
5814 Res = ExpandIntOp_WRITE_REGISTER(N, OpNo);
5815 break;
5816 }
5817
5818 // If the result is null, the sub-method took care of registering results etc.
5819 if (!Res.getNode()) return false;
5820
5821 // If the result is N, the sub-method updated N in place. Tell the legalizer
5822 // core about this.
5823 if (Res.getNode() == N)
5824 return true;
5825
5826 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
5827 "Invalid operand expansion");
5828
5829 ReplaceValueWith(From: SDValue(N, 0), To: Res);
5830 return false;
5831}
5832
5833/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
5834/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
5835void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
5836 SDValue &NewRHS,
5837 ISD::CondCode &CCCode,
5838 const SDLoc &dl) {
5839 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5840 GetExpandedInteger(Op: NewLHS, Lo&: LHSLo, Hi&: LHSHi);
5841 GetExpandedInteger(Op: NewRHS, Lo&: RHSLo, Hi&: RHSHi);
5842
5843 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
5844 if (RHSLo == RHSHi && isAllOnesConstant(V: RHSLo)) {
5845 // Equality comparison to -1.
5846 NewLHS = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: LHSHi);
5847 NewRHS = RHSLo;
5848 return;
5849 }
5850
5851 NewLHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: RHSLo);
5852 NewRHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSHi, N2: RHSHi);
5853 NewLHS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NewLHS.getValueType(), N1: NewLHS, N2: NewRHS);
5854 NewRHS = DAG.getConstant(Val: 0, DL: dl, VT: NewLHS.getValueType());
5855 return;
5856 }
5857
5858 // If this is a comparison of the sign bit, just look at the top part.
5859 // X > -1, x < 0
5860 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Val&: NewRHS))
5861 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0
5862 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1
5863 NewLHS = LHSHi;
5864 NewRHS = RHSHi;
5865 return;
5866 }
5867
5868 // FIXME: This generated code sucks.
5869 ISD::CondCode LowCC;
5870 switch (CCCode) {
5871 default: llvm_unreachable("Unknown integer setcc!");
5872 case ISD::SETLT:
5873 case ISD::SETULT: LowCC = ISD::SETULT; break;
5874 case ISD::SETGT:
5875 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5876 case ISD::SETLE:
5877 case ISD::SETULE: LowCC = ISD::SETULE; break;
5878 case ISD::SETGE:
5879 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5880 }
5881
5882 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
5883 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
5884 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
5885
5886 // NOTE: on targets without efficient SELECT of bools, we can always use
5887 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5888 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
5889 nullptr);
5890 SDValue LoCmp, HiCmp;
5891 if (TLI.isTypeLegal(VT: LHSLo.getValueType()))
5892 LoCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSLo.getValueType()), N0: LHSLo,
5893 N1: RHSLo, Cond: LowCC, foldBooleans: false, DCI&: DagCombineInfo, dl);
5894 if (!LoCmp.getNode())
5895 LoCmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LHSLo.getValueType()), LHS: LHSLo,
5896 RHS: RHSLo, Cond: LowCC);
5897 if (TLI.isTypeLegal(VT: LHSHi.getValueType()))
5898 HiCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSHi.getValueType()), N0: LHSHi,
5899 N1: RHSHi, Cond: CCCode, foldBooleans: false, DCI&: DagCombineInfo, dl);
5900 if (!HiCmp.getNode())
5901 HiCmp =
5902 DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: getSetCCResultType(VT: LHSHi.getValueType()),
5903 N1: LHSHi, N2: RHSHi, N3: DAG.getCondCode(Cond: CCCode));
5904
5905 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(Val: LoCmp.getNode());
5906 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(Val: HiCmp.getNode());
5907
5908 bool EqAllowed = ISD::isTrueWhenEqual(Cond: CCCode);
5909
5910 // FIXME: Is the HiCmpC->isOne() here correct for
5911 // ZeroOrNegativeOneBooleanContent.
5912 if ((EqAllowed && (HiCmpC && HiCmpC->isZero())) ||
5913 (!EqAllowed &&
5914 ((HiCmpC && HiCmpC->isOne()) || (LoCmpC && LoCmpC->isZero())))) {
5915 // For LE / GE, if high part is known false, ignore the low part.
5916 // For LT / GT: if low part is known false, return the high part.
5917 // if high part is known true, ignore the low part.
5918 NewLHS = HiCmp;
5919 NewRHS = SDValue();
5920 return;
5921 }
5922
5923 if (LHSHi == RHSHi) {
5924 // Comparing the low bits is enough.
5925 NewLHS = LoCmp;
5926 NewRHS = SDValue();
5927 return;
5928 }
5929
5930 // Lower with SETCCCARRY if the target supports it.
5931 EVT HiVT = LHSHi.getValueType();
5932 EVT ExpandVT = TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: HiVT);
5933 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(Op: ISD::SETCCCARRY, VT: ExpandVT);
5934
5935 // FIXME: Make all targets support this, then remove the other lowering.
5936 if (HasSETCCCARRY) {
5937 // SETCCCARRY can detect < and >= directly. For > and <=, flip
5938 // operands and condition code.
5939 bool FlipOperands = false;
5940 switch (CCCode) {
5941 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
5942 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
5943 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
5944 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
5945 default: break;
5946 }
5947 if (FlipOperands) {
5948 std::swap(a&: LHSLo, b&: RHSLo);
5949 std::swap(a&: LHSHi, b&: RHSHi);
5950 }
5951 // Perform a wide subtraction, feeding the carry from the low part into
5952 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
5953 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
5954 // zero or positive iff LHS >= RHS.
5955 EVT LoVT = LHSLo.getValueType();
5956 SDVTList VTList = DAG.getVTList(VT1: LoVT, VT2: getSetCCResultType(VT: LoVT));
5957 SDValue LowCmp = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: LHSLo, N2: RHSLo);
5958 SDValue Res = DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: getSetCCResultType(VT: HiVT),
5959 N1: LHSHi, N2: RHSHi, N3: LowCmp.getValue(R: 1),
5960 N4: DAG.getCondCode(Cond: CCCode));
5961 NewLHS = Res;
5962 NewRHS = SDValue();
5963 return;
5964 }
5965
5966 NewLHS = TLI.SimplifySetCC(VT: getSetCCResultType(VT: HiVT), N0: LHSHi, N1: RHSHi, Cond: ISD::SETEQ,
5967 foldBooleans: false, DCI&: DagCombineInfo, dl);
5968 if (!NewLHS.getNode())
5969 NewLHS =
5970 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: HiVT), LHS: LHSHi, RHS: RHSHi, Cond: ISD::SETEQ);
5971 NewLHS = DAG.getSelect(DL: dl, VT: LoCmp.getValueType(), Cond: NewLHS, LHS: LoCmp, RHS: HiCmp);
5972 NewRHS = SDValue();
5973}
5974
5975SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
5976 SDValue NewLHS = N->getOperand(Num: 2), NewRHS = N->getOperand(Num: 3);
5977 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get();
5978 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5979
5980 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5981 // against zero to select between true and false values.
5982 if (!NewRHS.getNode()) {
5983 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5984 CCCode = ISD::SETNE;
5985 }
5986
5987 // Update N to have the operands specified.
5988 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
5989 Op2: DAG.getCondCode(Cond: CCCode), Op3: NewLHS, Op4: NewRHS,
5990 Op5: N->getOperand(Num: 4)), 0);
5991}
5992
5993SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
5994 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5995 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
5996 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5997
5998 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5999 // against zero to select between true and false values.
6000 if (!NewRHS.getNode()) {
6001 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
6002 CCCode = ISD::SETNE;
6003 }
6004
6005 // Update N to have the operands specified.
6006 return SDValue(DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS,
6007 Op3: N->getOperand(Num: 2), Op4: N->getOperand(Num: 3),
6008 Op5: DAG.getCondCode(Cond: CCCode)), 0);
6009}
6010
6011SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
6012 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
6013 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
6014 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
6015
6016 // If ExpandSetCCOperands returned a scalar, use it.
6017 if (!NewRHS.getNode()) {
6018 assert(NewLHS.getValueType() == N->getValueType(0) &&
6019 "Unexpected setcc expansion!");
6020 return NewLHS;
6021 }
6022
6023 // Otherwise, update N to have the operands specified.
6024 return SDValue(
6025 DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS, Op3: DAG.getCondCode(Cond: CCCode)), 0);
6026}
6027
6028SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
6029 SDValue LHS = N->getOperand(Num: 0);
6030 SDValue RHS = N->getOperand(Num: 1);
6031 SDValue Carry = N->getOperand(Num: 2);
6032 SDValue Cond = N->getOperand(Num: 3);
6033 SDLoc dl = SDLoc(N);
6034
6035 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
6036 GetExpandedInteger(Op: LHS, Lo&: LHSLo, Hi&: LHSHi);
6037 GetExpandedInteger(Op: RHS, Lo&: RHSLo, Hi&: RHSHi);
6038
6039 // Expand to a USUBO_CARRY for the low part and a SETCCCARRY for the high.
6040 SDVTList VTList = DAG.getVTList(VT1: LHSLo.getValueType(), VT2: Carry.getValueType());
6041 SDValue LowCmp =
6042 DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: LHSLo, N2: RHSLo, N3: Carry);
6043 return DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: N->getValueType(ResNo: 0), N1: LHSHi, N2: RHSHi,
6044 N3: LowCmp.getValue(R: 1), N4: Cond);
6045}
6046
6047SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
6048 // Split the operand and replace with SPLAT_VECTOR_PARTS.
6049 SDValue Lo, Hi;
6050 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
6051 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Lo,
6052 N2: Hi);
6053}
6054
6055SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
6056 // The value being shifted is legal, but the shift amount is too big.
6057 // It follows that either the result of the shift is undefined, or the
6058 // upper half of the shift amount is zero. Just use the lower half.
6059 SDValue Lo, Hi;
6060 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo, Hi);
6061 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Lo), 0);
6062}
6063
6064SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
6065 return TLI.expandCMP(Node: N, DAG);
6066}
6067
6068SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
6069 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
6070 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
6071 // constant to valid type.
6072 SDValue Lo, Hi;
6073 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
6074 return SDValue(DAG.UpdateNodeOperands(N, Op: Lo), 0);
6075}
6076
6077SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) {
6078 bool IsStrict = N->isStrictFPOpcode();
6079 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
6080 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
6081 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
6082 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
6083 EVT DstVT = N->getValueType(ResNo: 0);
6084 RTLIB::Libcall LC = IsSigned ? RTLIB::getSINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT)
6085 : RTLIB::getUINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT);
6086 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
6087 "Don't know how to expand this XINT_TO_FP!");
6088 TargetLowering::MakeLibCallOptions CallOptions;
6089 CallOptions.setIsSigned(true);
6090 std::pair<SDValue, SDValue> Tmp =
6091 TLI.makeLibCall(DAG, LC, RetVT: DstVT, Ops: Op, CallOptions, dl: SDLoc(N), Chain);
6092
6093 if (!IsStrict)
6094 return Tmp.first;
6095
6096 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
6097 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
6098 return SDValue();
6099}
6100
6101SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
6102 assert(!N->isAtomic() && "Should have been a ATOMIC_STORE?");
6103
6104 if (ISD::isNormalStore(N))
6105 return ExpandOp_NormalStore(N, OpNo);
6106
6107 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
6108 assert(OpNo == 1 && "Can only expand the stored value so far");
6109
6110 EVT VT = N->getOperand(Num: 1).getValueType();
6111 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6112 SDValue Ch = N->getChain();
6113 SDValue Ptr = N->getBasePtr();
6114 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
6115 AAMDNodes AAInfo = N->getAAInfo();
6116 SDLoc dl(N);
6117 SDValue Lo, Hi;
6118
6119 assert(NVT.isByteSized() && "Expanded type not byte sized!");
6120
6121 if (N->getMemoryVT().bitsLE(VT: NVT)) {
6122 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6123 return DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(),
6124 SVT: N->getMemoryVT(), Alignment: N->getBaseAlign(), MMOFlags,
6125 AAInfo);
6126 }
6127
6128 if (DAG.getDataLayout().isLittleEndian()) {
6129 // Little-endian - low bits are at low addresses.
6130 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6131
6132 Lo = DAG.getStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
6133 MMOFlags, AAInfo);
6134
6135 unsigned ExcessBits =
6136 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
6137 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
6138
6139 // Increment the pointer to the other half.
6140 unsigned IncrementSize = NVT.getSizeInBits()/8;
6141 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6142 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr,
6143 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6144 SVT: NEVT, Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
6145 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6146 }
6147
6148 // Big-endian - high bits are at low addresses. Favor aligned stores at
6149 // the cost of some bit-fiddling.
6150 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6151
6152 EVT ExtVT = N->getMemoryVT();
6153 unsigned EBytes = ExtVT.getStoreSize();
6154 unsigned IncrementSize = NVT.getSizeInBits()/8;
6155 unsigned ExcessBits = (EBytes - IncrementSize)*8;
6156 EVT HiVT = EVT::getIntegerVT(Context&: *DAG.getContext(),
6157 BitWidth: ExtVT.getSizeInBits() - ExcessBits);
6158
6159 if (ExcessBits < NVT.getSizeInBits()) {
6160 // Transfer high bits from the top of Lo to the bottom of Hi.
6161 Hi = DAG.getNode(
6162 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
6163 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
6164 Hi = DAG.getNode(
6165 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Hi,
6166 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Lo,
6167 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
6168 }
6169
6170 // Store both the high bits and maybe some of the low bits.
6171 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr, PtrInfo: N->getPointerInfo(), SVT: HiVT,
6172 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
6173
6174 // Increment the pointer to the other half.
6175 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6176 // Store the lowest ExcessBits bits in the second half.
6177 Lo = DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr,
6178 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6179 SVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
6180 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
6181 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6182}
6183
6184SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
6185 SDValue InL, InH;
6186 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
6187 // Just truncate the low part of the source.
6188 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: InL);
6189}
6190
6191SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
6192 SDLoc dl(N);
6193 SDValue Swap =
6194 DAG.getAtomic(Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(),
6195 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 2), Val: N->getOperand(Num: 1),
6196 MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
6197 return Swap.getValue(R: 1);
6198}
6199
6200SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
6201 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
6202 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
6203
6204 SDValue Hi; // The upper half is dropped out.
6205 SmallVector<SDValue, 8> NewOps(N->ops());
6206 GetExpandedInteger(Op: NewOps[OpNo], Lo&: NewOps[OpNo], Hi);
6207
6208 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
6209}
6210
6211SDValue DAGTypeLegalizer::ExpandIntOp_WRITE_REGISTER(SDNode *N, unsigned OpNo) {
6212 const Function &Fn = DAG.getMachineFunction().getFunction();
6213 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6214 "cannot use llvm.write_register with illegal type", Fn,
6215 N->getDebugLoc()));
6216
6217 return N->getOperand(Num: 0);
6218}
6219
6220SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
6221 SDLoc dl(N);
6222
6223 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6224 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6225 EVT OutVT = V0.getValueType();
6226
6227 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: OutVT, N1: V0, N2: V1, N3: N->getOperand(Num: 2));
6228}
6229
6230SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(SDNode *N) {
6231 SDLoc DL(N);
6232 unsigned Factor = N->getNumOperands();
6233
6234 SmallVector<SDValue, 8> Ops(Factor);
6235 for (unsigned i = 0; i != Factor; i++)
6236 Ops[i] = GetPromotedInteger(Op: N->getOperand(Num: i));
6237
6238 SmallVector<EVT, 8> ResVTs(Factor, Ops[0].getValueType());
6239 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VTs: ResVTs), Ops);
6240
6241 for (unsigned i = 0; i != Factor; i++)
6242 SetPromotedInteger(Op: SDValue(N, i), Result: Res.getValue(R: i));
6243
6244 return SDValue();
6245}
6246
6247SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
6248
6249 EVT OutVT = N->getValueType(ResNo: 0);
6250 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6251 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6252 EVT NOutVTElem = NOutVT.getVectorElementType();
6253
6254 SDLoc dl(N);
6255 SDValue BaseIdx = N->getOperand(Num: 1);
6256
6257 // TODO: We may be able to use this for types other than scalable
6258 // vectors and fix those tests that expect BUILD_VECTOR to be used
6259 if (OutVT.isScalableVector()) {
6260 SDValue InOp0 = N->getOperand(Num: 0);
6261 EVT InVT = InOp0.getValueType();
6262
6263 // Try and extract from a smaller type so that it eventually falls
6264 // into the promotion code below.
6265 if (getTypeAction(VT: InVT) == TargetLowering::TypeSplitVector ||
6266 getTypeAction(VT: InVT) == TargetLowering::TypeLegal) {
6267 EVT NInVT = InVT.getHalfNumVectorElementsVT(Context&: *DAG.getContext());
6268 unsigned NElts = NInVT.getVectorMinNumElements();
6269 uint64_t IdxVal = BaseIdx->getAsZExtVal();
6270
6271 SDValue Step1 = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NInVT, N1: InOp0,
6272 N2: DAG.getConstant(Val: alignDown(Value: IdxVal, Align: NElts), DL: dl,
6273 VT: BaseIdx.getValueType()));
6274 SDValue Step2 = DAG.getNode(
6275 Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Step1,
6276 N2: DAG.getConstant(Val: IdxVal % NElts, DL: dl, VT: BaseIdx.getValueType()));
6277 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Step2);
6278 }
6279
6280 // Try and extract from a widened type.
6281 if (getTypeAction(VT: InVT) == TargetLowering::TypeWidenVector) {
6282 SDValue Ops[] = {GetWidenedVector(Op: InOp0), BaseIdx};
6283 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: OutVT, Ops);
6284 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6285 }
6286
6287 // Promote operands and see if this is handled by target lowering,
6288 // Otherwise, use the BUILD_VECTOR approach below
6289 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
6290 // Collect the (promoted) operands
6291 SDValue Ops[] = { GetPromotedInteger(Op: InOp0), BaseIdx };
6292
6293 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
6294 assert(PromEltVT.bitsLE(NOutVTElem) &&
6295 "Promoted operand has an element type greater than result");
6296
6297 EVT ExtVT = NOutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: PromEltVT);
6298 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: ExtVT, Ops);
6299 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6300 }
6301 }
6302
6303 if (OutVT.isScalableVector())
6304 report_fatal_error(reason: "Unable to promote scalable types using BUILD_VECTOR");
6305
6306 SDValue InOp0 = N->getOperand(Num: 0);
6307 if (getTypeAction(VT: InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
6308 InOp0 = GetPromotedInteger(Op: InOp0);
6309
6310 EVT InVT = InOp0.getValueType();
6311 EVT InSVT = InVT.getVectorElementType();
6312
6313 unsigned OutNumElems = OutVT.getVectorNumElements();
6314 SmallVector<SDValue, 8> Ops;
6315 Ops.reserve(N: OutNumElems);
6316 for (unsigned i = 0; i != OutNumElems; ++i) {
6317 // Extract the element from the original vector.
6318 SDValue Index = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: BaseIdx.getValueType(), N1: BaseIdx,
6319 N2: DAG.getConstant(Val: i, DL: dl, VT: BaseIdx.getValueType()));
6320 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: InSVT,
6321 N1: N->getOperand(Num: 0), N2: Index);
6322 SDValue Op = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NOutVTElem);
6323 // Insert the converted element to the new vector.
6324 Ops.push_back(Elt: Op);
6325 }
6326
6327 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6328}
6329
6330SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
6331 EVT OutVT = N->getValueType(ResNo: 0);
6332 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6333 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6334
6335 SDLoc dl(N);
6336 SDValue Vec = N->getOperand(Num: 0);
6337 SDValue SubVec = N->getOperand(Num: 1);
6338 SDValue Idx = N->getOperand(Num: 2);
6339
6340 EVT SubVecVT = SubVec.getValueType();
6341 EVT NSubVT =
6342 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NOutVT.getVectorElementType(),
6343 EC: SubVecVT.getVectorElementCount());
6344
6345 Vec = GetPromotedInteger(Op: Vec);
6346 SubVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NSubVT, Operand: SubVec);
6347
6348 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: NOutVT, N1: Vec, N2: SubVec, N3: Idx);
6349}
6350
6351SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
6352 SDLoc dl(N);
6353
6354 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6355 EVT OutVT = V0.getValueType();
6356
6357 return DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL: dl, VT: OutVT, Operand: V0);
6358}
6359
6360SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
6361 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(Val: N);
6362 EVT VT = N->getValueType(ResNo: 0);
6363 SDLoc dl(N);
6364
6365 ArrayRef<int> NewMask = SV->getMask().slice(N: 0, M: VT.getVectorNumElements());
6366
6367 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6368 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6369 EVT OutVT = V0.getValueType();
6370
6371 return DAG.getVectorShuffle(VT: OutVT, dl, N1: V0, N2: V1, Mask: NewMask);
6372}
6373
6374SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
6375 EVT OutVT = N->getValueType(ResNo: 0);
6376 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6377 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6378 unsigned NumElems = N->getNumOperands();
6379 EVT NOutVTElem = NOutVT.getVectorElementType();
6380 TargetLoweringBase::BooleanContent NOutBoolType = TLI.getBooleanContents(Type: NOutVT);
6381 unsigned NOutExtOpc = TargetLowering::getExtendForContent(Content: NOutBoolType);
6382 SDLoc dl(N);
6383
6384 SmallVector<SDValue, 8> Ops;
6385 Ops.reserve(N: NumElems);
6386 for (unsigned i = 0; i != NumElems; ++i) {
6387 SDValue Op = N->getOperand(Num: i);
6388 EVT OpVT = Op.getValueType();
6389 // BUILD_VECTOR integer operand types are allowed to be larger than the
6390 // result's element type. This may still be true after the promotion. For
6391 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
6392 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
6393 if (OpVT.bitsLT(VT: NOutVTElem)) {
6394 unsigned ExtOpc = ISD::ANY_EXTEND;
6395 // Attempt to extend constant bool vectors to match target's BooleanContent.
6396 // While not necessary, this improves chances of the constant correctly
6397 // folding with compare results (e.g. for NOT patterns).
6398 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant)
6399 ExtOpc = NOutExtOpc;
6400 Op = DAG.getNode(Opcode: ExtOpc, DL: dl, VT: NOutVTElem, Operand: Op);
6401 }
6402 Ops.push_back(Elt: Op);
6403 }
6404
6405 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6406}
6407
6408SDValue DAGTypeLegalizer::PromoteIntRes_ScalarOp(SDNode *N) {
6409
6410 SDLoc dl(N);
6411
6412 assert(!N->getOperand(0).getValueType().isVector() &&
6413 "Input must be a scalar");
6414
6415 EVT OutVT = N->getValueType(ResNo: 0);
6416 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6417 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6418 EVT NOutElemVT = NOutVT.getVectorElementType();
6419
6420 SDValue Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutElemVT, Operand: N->getOperand(Num: 0));
6421 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NOutVT, Operand: Op);
6422}
6423
6424SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
6425 SDLoc dl(N);
6426 EVT OutVT = N->getValueType(ResNo: 0);
6427 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6428 assert(NOutVT.isScalableVector() &&
6429 "Type must be promoted to a scalable vector type");
6430 const APInt &StepVal = N->getConstantOperandAPInt(Num: 0);
6431 return DAG.getStepVector(DL: dl, ResVT: NOutVT,
6432 StepVal: StepVal.sext(width: NOutVT.getScalarSizeInBits()));
6433}
6434
6435SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
6436 SDLoc dl(N);
6437
6438 EVT OutVT = N->getValueType(ResNo: 0);
6439 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6440 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6441
6442 unsigned NumOperands = N->getNumOperands();
6443 unsigned NumOutElem = NOutVT.getVectorMinNumElements();
6444 EVT OutElemTy = NOutVT.getVectorElementType();
6445 if (OutVT.isScalableVector()) {
6446 // Find the largest promoted element type for each of the operands.
6447 SDUse *MaxSizedValue = std::max_element(
6448 first: N->op_begin(), last: N->op_end(), comp: [](const SDValue &A, const SDValue &B) {
6449 EVT AVT = A.getValueType().getVectorElementType();
6450 EVT BVT = B.getValueType().getVectorElementType();
6451 return AVT.getScalarSizeInBits() < BVT.getScalarSizeInBits();
6452 });
6453 EVT MaxElementVT = MaxSizedValue->getValueType().getVectorElementType();
6454
6455 // Then promote all vectors to the largest element type.
6456 SmallVector<SDValue, 8> Ops;
6457 for (unsigned I = 0; I < NumOperands; ++I) {
6458 SDValue Op = N->getOperand(Num: I);
6459 EVT OpVT = Op.getValueType();
6460 if (getTypeAction(VT: OpVT) == TargetLowering::TypePromoteInteger)
6461 Op = GetPromotedInteger(Op);
6462 else
6463 assert(getTypeAction(OpVT) == TargetLowering::TypeLegal &&
6464 "Unhandled legalization type");
6465
6466 if (OpVT.getVectorElementType().getScalarSizeInBits() <
6467 MaxElementVT.getScalarSizeInBits())
6468 Op = DAG.getAnyExtOrTrunc(
6469 Op, DL: dl,
6470 VT: OpVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT));
6471 Ops.push_back(Elt: Op);
6472 }
6473
6474 // Do the CONCAT on the promoted type and finally truncate to (the promoted)
6475 // NOutVT.
6476 return DAG.getAnyExtOrTrunc(
6477 Op: DAG.getNode(
6478 Opcode: ISD::CONCAT_VECTORS, DL: dl,
6479 VT: OutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT),
6480 Ops),
6481 DL: dl, VT: NOutVT);
6482 }
6483
6484 unsigned NumElem = N->getOperand(Num: 0).getValueType().getVectorNumElements();
6485 assert(NumElem * NumOperands == NumOutElem &&
6486 "Unexpected number of elements");
6487
6488 // Take the elements from the first vector.
6489 SmallVector<SDValue, 8> Ops(NumOutElem);
6490 for (unsigned i = 0; i < NumOperands; ++i) {
6491 SDValue Op = N->getOperand(Num: i);
6492 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypePromoteInteger)
6493 Op = GetPromotedInteger(Op);
6494 EVT SclrTy = Op.getValueType().getVectorElementType();
6495 assert(NumElem == Op.getValueType().getVectorNumElements() &&
6496 "Unexpected number of elements");
6497
6498 for (unsigned j = 0; j < NumElem; ++j) {
6499 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Op,
6500 N2: DAG.getVectorIdxConstant(Val: j, DL: dl));
6501 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: OutElemTy);
6502 }
6503 }
6504
6505 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6506}
6507
6508SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
6509 EVT VT = N->getValueType(ResNo: 0);
6510 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6511 assert(NVT.isVector() && "This type must be promoted to a vector type");
6512
6513 SDLoc dl(N);
6514
6515 // For operands whose TypeAction is to promote, extend the promoted node
6516 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
6517 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
6518 // type..
6519 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
6520 == TargetLowering::TypePromoteInteger) {
6521 SDValue Promoted;
6522
6523 switch(N->getOpcode()) {
6524 case ISD::SIGN_EXTEND_VECTOR_INREG:
6525 Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
6526 break;
6527 case ISD::ZERO_EXTEND_VECTOR_INREG:
6528 Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
6529 break;
6530 case ISD::ANY_EXTEND_VECTOR_INREG:
6531 Promoted = GetPromotedInteger(Op: N->getOperand(Num: 0));
6532 break;
6533 default:
6534 llvm_unreachable("Node has unexpected Opcode");
6535 }
6536 unsigned NewSize = NVT.getSizeInBits();
6537 if (Promoted.getValueType().getSizeInBits() > NewSize) {
6538 EVT ExtractVT = EVT::getVectorVT(
6539 Context&: *DAG.getContext(), VT: Promoted.getValueType().getVectorElementType(),
6540 NumElements: NewSize / Promoted.getScalarValueSizeInBits());
6541
6542 Promoted = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: ExtractVT, N1: Promoted,
6543 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
6544 }
6545 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Promoted);
6546 }
6547
6548 // Directly extend to the appropriate transform-to type.
6549 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
6550}
6551
6552SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(SDNode *N) {
6553 EVT VT = N->getValueType(ResNo: 0);
6554 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6555 return DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6556}
6557
6558SDValue DAGTypeLegalizer::PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
6559 EVT VT = N->getValueType(ResNo: 0);
6560 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6561 return DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6562}
6563
6564SDValue DAGTypeLegalizer::PromoteIntRes_PARTIAL_REDUCE_MLA(SDNode *N) {
6565 SDLoc DL(N);
6566 EVT VT = N->getValueType(ResNo: 0);
6567 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6568 SDValue ExtAcc = GetPromotedInteger(Op: N->getOperand(Num: 0));
6569 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: ExtAcc, N2: N->getOperand(Num: 1),
6570 N3: N->getOperand(Num: 2));
6571}
6572
6573SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
6574 EVT OutVT = N->getValueType(ResNo: 0);
6575 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6576 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6577
6578 EVT NOutVTElem = NOutVT.getVectorElementType();
6579
6580 SDLoc dl(N);
6581 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6582
6583 SDValue ConvElem = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6584 VT: NOutVTElem, Operand: N->getOperand(Num: 1));
6585 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NOutVT,
6586 N1: V0, N2: ConvElem, N3: N->getOperand(Num: 2));
6587}
6588
6589SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
6590 // The VECREDUCE result size may be larger than the element size, so
6591 // we can simply change the result type.
6592 SDLoc dl(N);
6593 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6594 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Ops: N->ops());
6595}
6596
6597SDValue DAGTypeLegalizer::PromoteIntRes_VP_REDUCE(SDNode *N) {
6598 // The VP_REDUCE result size may be larger than the element size, so we can
6599 // simply change the result type. However the start value and result must be
6600 // the same.
6601 SDLoc DL(N);
6602 SDValue Start = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
6603 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: Start.getValueType(), N1: Start,
6604 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
6605}
6606
6607SDValue DAGTypeLegalizer::PromoteIntRes_PATCHPOINT(SDNode *N) {
6608 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6609 SDLoc dl(N);
6610
6611 assert(N->getNumValues() == 3 && "Expected 3 values for PATCHPOINT");
6612 SDVTList VTList = DAG.getVTList(VTs: {NVT, MVT::Other, MVT::Glue});
6613
6614 SmallVector<SDValue> Ops(N->ops());
6615 SDValue Res = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList, Ops);
6616
6617 // Replace chain and glue uses with the new patchpoint.
6618 SDValue From[] = {SDValue(N, 1), SDValue(N, 2)};
6619 SDValue To[] = {Res.getValue(R: 1), Res.getValue(R: 2)};
6620 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
6621
6622 return Res.getValue(R: 0);
6623}
6624
6625SDValue DAGTypeLegalizer::PromoteIntRes_READ_REGISTER(SDNode *N) {
6626 const Function &Fn = DAG.getMachineFunction().getFunction();
6627 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6628 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
6629
6630 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6631 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
6632 return DAG.getPOISON(VT: NVT);
6633}
6634
6635SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
6636 SDLoc dl(N);
6637 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6638 SDValue V1 = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl,
6639 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
6640 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl,
6641 VT: V0->getValueType(ResNo: 0).getScalarType(), N1: V0, N2: V1);
6642
6643 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
6644 // element types. If this is the case then we need to expand the outgoing
6645 // value and not truncate it.
6646 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6647}
6648
6649SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_SUBVECTOR(SDNode *N) {
6650 SDLoc dl(N);
6651 // The result type is equal to the first input operand's type, so the
6652 // type that needs promoting must be the second source vector.
6653 SDValue V0 = N->getOperand(Num: 0);
6654 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6655 SDValue Idx = N->getOperand(Num: 2);
6656 EVT PromVT = EVT::getVectorVT(Context&: *DAG.getContext(),
6657 VT: V1.getValueType().getVectorElementType(),
6658 EC: V0.getValueType().getVectorElementCount());
6659 V0 = DAG.getAnyExtOrTrunc(Op: V0, DL: dl, VT: PromVT);
6660 SDValue Ext = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: PromVT, N1: V0, N2: V1, N3: Idx);
6661 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6662}
6663
6664// FIXME: We wouldn't need this if clang could promote short integers
6665// that are arguments to FAKE_USE.
6666SDValue DAGTypeLegalizer::PromoteIntOp_FAKE_USE(SDNode *N) {
6667 SDLoc dl(N);
6668 SDValue V0 = N->getOperand(Num: 0);
6669 SDValue V1 = N->getOperand(Num: 1);
6670 EVT InVT1 = V1.getValueType();
6671 SDValue VPromoted =
6672 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6673 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT1), Operand: V1);
6674 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: N->getValueType(ResNo: 0), N1: V0, N2: VPromoted);
6675}
6676
6677SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
6678 SDLoc dl(N);
6679 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6680 MVT InVT = V0.getValueType().getSimpleVT();
6681 MVT OutVT = MVT::getVectorVT(VT: InVT.getVectorElementType(),
6682 NumElements: N->getValueType(ResNo: 0).getVectorNumElements());
6683 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: V0, N2: N->getOperand(Num: 1));
6684 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Ext);
6685}
6686
6687SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
6688 SDLoc dl(N);
6689
6690 EVT ResVT = N->getValueType(ResNo: 0);
6691 unsigned NumElems = N->getNumOperands();
6692
6693 if (ResVT.isScalableVector()) {
6694 SDValue ResVec = DAG.getUNDEF(VT: ResVT);
6695
6696 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
6697 SDValue Op = N->getOperand(Num: OpIdx);
6698 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
6699 ResVec = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: ResVT, N1: ResVec, N2: Op,
6700 N3: DAG.getIntPtrConstant(Val: OpIdx * OpNumElts, DL: dl));
6701 }
6702
6703 return ResVec;
6704 }
6705
6706 EVT RetSclrTy = N->getValueType(ResNo: 0).getVectorElementType();
6707
6708 SmallVector<SDValue, 8> NewOps;
6709 NewOps.reserve(N: NumElems);
6710
6711 // For each incoming vector
6712 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
6713 SDValue Incoming = GetPromotedInteger(Op: N->getOperand(Num: VecIdx));
6714 EVT SclrTy = Incoming->getValueType(ResNo: 0).getVectorElementType();
6715 unsigned NumElem = Incoming->getValueType(ResNo: 0).getVectorNumElements();
6716
6717 for (unsigned i=0; i<NumElem; ++i) {
6718 // Extract element from incoming vector
6719 SDValue Ex = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Incoming,
6720 N2: DAG.getVectorIdxConstant(Val: i, DL: dl));
6721 SDValue Tr = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RetSclrTy, Operand: Ex);
6722 NewOps.push_back(Elt: Tr);
6723 }
6724 }
6725
6726 return DAG.getBuildVector(VT: N->getValueType(ResNo: 0), DL: dl, Ops: NewOps);
6727}
6728
6729SDValue DAGTypeLegalizer::ExpandIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
6730 assert(OpNo > 1);
6731 SDValue Op = N->getOperand(Num: OpNo);
6732
6733 // FIXME: Non-constant operands are not yet handled:
6734 // - https://github.com/llvm/llvm-project/issues/26431
6735 // - https://github.com/llvm/llvm-project/issues/55957
6736 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6737 if (!CN)
6738 return SDValue();
6739
6740 // Copy operands before the one being expanded.
6741 SmallVector<SDValue> NewOps;
6742 for (unsigned I = 0; I < OpNo; I++)
6743 NewOps.push_back(Elt: N->getOperand(Num: I));
6744
6745 EVT Ty = Op.getValueType();
6746 SDLoc DL = SDLoc(N);
6747 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6748 NewOps.push_back(
6749 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6750 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6751 } else {
6752 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6753 return SDValue();
6754 }
6755
6756 // Copy remaining operands.
6757 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6758 NewOps.push_back(Elt: N->getOperand(Num: I));
6759
6760 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6761
6762 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6763 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6764
6765 return SDValue(); // Signal that we have replaced the node already.
6766}
6767
6768SDValue DAGTypeLegalizer::ExpandIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
6769 assert(OpNo >= 7);
6770 SDValue Op = N->getOperand(Num: OpNo);
6771
6772 // FIXME: Non-constant operands are not yet handled:
6773 // - https://github.com/llvm/llvm-project/issues/26431
6774 // - https://github.com/llvm/llvm-project/issues/55957
6775 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6776 if (!CN)
6777 return SDValue();
6778
6779 // Copy operands before the one being expanded.
6780 SmallVector<SDValue> NewOps;
6781 for (unsigned I = 0; I < OpNo; I++)
6782 NewOps.push_back(Elt: N->getOperand(Num: I));
6783
6784 EVT Ty = Op.getValueType();
6785 SDLoc DL = SDLoc(N);
6786 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6787 NewOps.push_back(
6788 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6789 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6790 } else {
6791 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6792 return SDValue();
6793 }
6794
6795 // Copy remaining operands.
6796 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6797 NewOps.push_back(Elt: N->getOperand(Num: I));
6798
6799 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6800
6801 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6802 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6803
6804 return SDValue(); // Signal that we have replaced the node already.
6805}
6806