1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetLowering.h"
24#include "llvm/IR/DerivedTypes.h"
25#include "llvm/IR/DiagnosticInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/KnownBits.h"
28#include "llvm/Support/raw_ostream.h"
29#include <algorithm>
30using namespace llvm;
31
32#define DEBUG_TYPE "legalize-types"
33
34//===----------------------------------------------------------------------===//
35// Integer Result Promotion
36//===----------------------------------------------------------------------===//
37
38/// PromoteIntegerResult - This method is called when a result of a node is
39/// found to be in need of promotion to a larger type. At this point, the node
40/// may also have invalid operands or may have other results that need
41/// expansion, we just know that (at least) one result needs promotion.
42void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
43 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG));
44 SDValue Res = SDValue();
45
46 // See if the target wants to custom expand this node.
47 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true)) {
48 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
49 return;
50 }
51
52 switch (N->getOpcode()) {
53 default:
54#ifndef NDEBUG
55 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
56 N->dump(&DAG); dbgs() << "\n";
57#endif
58 report_fatal_error(reason: "Do not know how to promote this operator!");
59 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
60 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
61 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
62 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
63 case ISD::VP_BITREVERSE:
64 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
65 case ISD::VP_BSWAP:
66 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
67 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
68 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
69 case ISD::VP_CTLZ_ZERO_POISON:
70 case ISD::VP_CTLZ:
71 case ISD::CTLZ_ZERO_POISON:
72 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
73 case ISD::CTLS: Res = PromoteIntRes_CTLS(N); break;
74 case ISD::PARITY:
75 case ISD::VP_CTPOP:
76 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
77 case ISD::VP_CTTZ_ZERO_POISON:
78 case ISD::VP_CTTZ:
79 case ISD::CTTZ_ZERO_POISON:
80 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
81 case ISD::CTTZ_ELTS_ZERO_POISON:
82 case ISD::CTTZ_ELTS:
83 case ISD::VP_CTTZ_ELTS_ZERO_POISON:
84 case ISD::VP_CTTZ_ELTS:
85 Res = PromoteIntRes_VP_CttzElements(N);
86 break;
87 case ISD::EXTRACT_VECTOR_ELT:
88 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
89 case ISD::LOAD: Res = PromoteIntRes_LOAD(N: cast<LoadSDNode>(Val: N)); break;
90 case ISD::VP_LOAD:
91 Res = PromoteIntRes_VP_LOAD(N: cast<VPLoadSDNode>(Val: N));
92 break;
93 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(N: cast<MaskedLoadSDNode>(Val: N));
94 break;
95 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(N: cast<MaskedGatherSDNode>(Val: N));
96 break;
97 case ISD::VECTOR_COMPRESS:
98 Res = PromoteIntRes_VECTOR_COMPRESS(N);
99 break;
100 case ISD::SELECT:
101 case ISD::VSELECT:
102 case ISD::VP_SELECT:
103 case ISD::VP_MERGE:
104 Res = PromoteIntRes_Select(N);
105 break;
106 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
107 case ISD::STRICT_FSETCC:
108 case ISD::STRICT_FSETCCS:
109 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
110 case ISD::SMIN:
111 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
112 case ISD::UMIN:
113 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
114
115 case ISD::SHL:
116 case ISD::VP_SHL: Res = PromoteIntRes_SHL(N); break;
117 case ISD::SIGN_EXTEND_INREG:
118 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
119 case ISD::SRA:
120 case ISD::VP_SRA: Res = PromoteIntRes_SRA(N); break;
121 case ISD::SRL:
122 case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
123 case ISD::VP_TRUNCATE:
124 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
125 case ISD::POISON:
126 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
127 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
128 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
129
130 case ISD::EXTRACT_SUBVECTOR:
131 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
132 case ISD::INSERT_SUBVECTOR:
133 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
134 case ISD::VECTOR_REVERSE:
135 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
136 case ISD::VECTOR_SHUFFLE:
137 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
138 case ISD::VECTOR_SPLICE_LEFT:
139 case ISD::VECTOR_SPLICE_RIGHT:
140 Res = PromoteIntRes_VECTOR_SPLICE(N);
141 break;
142 case ISD::VECTOR_INTERLEAVE:
143 case ISD::VECTOR_DEINTERLEAVE:
144 Res = PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(N);
145 return;
146 case ISD::INSERT_VECTOR_ELT:
147 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
148 case ISD::BUILD_VECTOR:
149 Res = PromoteIntRes_BUILD_VECTOR(N);
150 break;
151 case ISD::SPLAT_VECTOR:
152 case ISD::SCALAR_TO_VECTOR:
153 Res = PromoteIntRes_ScalarOp(N);
154 break;
155 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
156 case ISD::CONCAT_VECTORS:
157 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
158
159 case ISD::ANY_EXTEND_VECTOR_INREG:
160 case ISD::SIGN_EXTEND_VECTOR_INREG:
161 case ISD::ZERO_EXTEND_VECTOR_INREG:
162 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
163
164 case ISD::VECTOR_FIND_LAST_ACTIVE:
165 Res = PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(N);
166 break;
167
168 case ISD::GET_ACTIVE_LANE_MASK:
169 Res = PromoteIntRes_GET_ACTIVE_LANE_MASK(N);
170 break;
171
172 case ISD::PARTIAL_REDUCE_UMLA:
173 case ISD::PARTIAL_REDUCE_SMLA:
174 case ISD::PARTIAL_REDUCE_SUMLA:
175 Res = PromoteIntRes_PARTIAL_REDUCE_MLA(N);
176 break;
177
178 case ISD::SIGN_EXTEND:
179 case ISD::VP_SIGN_EXTEND:
180 case ISD::ZERO_EXTEND:
181 case ISD::VP_ZERO_EXTEND:
182 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
183
184 case ISD::VP_FP_TO_SINT:
185 case ISD::VP_FP_TO_UINT:
186 case ISD::STRICT_FP_TO_SINT:
187 case ISD::STRICT_FP_TO_UINT:
188 case ISD::FP_TO_SINT:
189 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
190
191 case ISD::FP_TO_SINT_SAT:
192 case ISD::FP_TO_UINT_SAT:
193 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
194
195 case ISD::FP_TO_BF16:
196 case ISD::FP_TO_FP16:
197 Res = PromoteIntRes_FP_TO_FP16_BF16(N);
198 break;
199 case ISD::CONVERT_TO_ARBITRARY_FP:
200 Res = PromoteIntRes_CONVERT_TO_ARBITRARY_FP(N);
201 break;
202 case ISD::STRICT_FP_TO_BF16:
203 case ISD::STRICT_FP_TO_FP16:
204 Res = PromoteIntRes_STRICT_FP_TO_FP16_BF16(N);
205 break;
206 case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break;
207
208 case ISD::AND:
209 case ISD::OR:
210 case ISD::XOR:
211 case ISD::ADD:
212 case ISD::SUB:
213 case ISD::MUL:
214 case ISD::VP_AND:
215 case ISD::VP_OR:
216 case ISD::VP_XOR:
217 case ISD::VP_ADD:
218 case ISD::VP_SUB:
219 case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
220
221 case ISD::ABDS:
222 case ISD::AVGCEILS:
223 case ISD::AVGFLOORS:
224 case ISD::VP_SMIN:
225 case ISD::VP_SMAX:
226 case ISD::SDIV:
227 case ISD::SREM:
228 case ISD::VP_SDIV:
229 case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
230
231 case ISD::ABDU:
232 case ISD::AVGCEILU:
233 case ISD::AVGFLOORU:
234 case ISD::VP_UMIN:
235 case ISD::VP_UMAX:
236 case ISD::UDIV:
237 case ISD::UREM:
238 case ISD::VP_UDIV:
239 case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
240
241 case ISD::MASKED_UDIV:
242 case ISD::MASKED_UREM:
243 Res = PromoteIntRes_ZExtMaskedIntBinOp(N);
244 break;
245 case ISD::MASKED_SDIV:
246 case ISD::MASKED_SREM:
247 Res = PromoteIntRes_SExtMaskedIntBinOp(N);
248 break;
249
250 case ISD::SADDO:
251 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
252 case ISD::UADDO:
253 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
254 case ISD::SMULO:
255 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
256
257 case ISD::ADDE:
258 case ISD::SUBE:
259 case ISD::UADDO_CARRY:
260 case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break;
261
262 case ISD::SADDO_CARRY:
263 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
264
265 case ISD::SADDSAT:
266 case ISD::UADDSAT:
267 case ISD::SSUBSAT:
268 case ISD::USUBSAT:
269 case ISD::SSHLSAT:
270 case ISD::USHLSAT:
271 Res = PromoteIntRes_ADDSUBSHLSAT<EmptyMatchContext>(N);
272 break;
273 case ISD::VP_SADDSAT:
274 case ISD::VP_UADDSAT:
275 case ISD::VP_SSUBSAT:
276 case ISD::VP_USUBSAT:
277 Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
278 break;
279
280 case ISD::SCMP:
281 case ISD::UCMP:
282 Res = PromoteIntRes_CMP(N);
283 break;
284
285 case ISD::SMULFIX:
286 case ISD::SMULFIXSAT:
287 case ISD::UMULFIX:
288 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
289
290 case ISD::SDIVFIX:
291 case ISD::SDIVFIXSAT:
292 case ISD::UDIVFIX:
293 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
294
295 case ISD::ABS:
296 case ISD::ABS_MIN_POISON:
297 Res = PromoteIntRes_ABS(N);
298 break;
299
300 case ISD::ATOMIC_LOAD:
301 Res = PromoteIntRes_Atomic0(N: cast<AtomicSDNode>(Val: N)); break;
302
303 case ISD::ATOMIC_LOAD_ADD:
304 case ISD::ATOMIC_LOAD_SUB:
305 case ISD::ATOMIC_LOAD_AND:
306 case ISD::ATOMIC_LOAD_CLR:
307 case ISD::ATOMIC_LOAD_OR:
308 case ISD::ATOMIC_LOAD_XOR:
309 case ISD::ATOMIC_LOAD_NAND:
310 case ISD::ATOMIC_LOAD_MIN:
311 case ISD::ATOMIC_LOAD_MAX:
312 case ISD::ATOMIC_LOAD_UMIN:
313 case ISD::ATOMIC_LOAD_UMAX:
314 case ISD::ATOMIC_SWAP:
315 Res = PromoteIntRes_Atomic1(N: cast<AtomicSDNode>(Val: N)); break;
316
317 case ISD::ATOMIC_CMP_SWAP:
318 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
319 Res = PromoteIntRes_AtomicCmpSwap(N: cast<AtomicSDNode>(Val: N), ResNo);
320 break;
321
322 case ISD::VECREDUCE_ADD:
323 case ISD::VECREDUCE_MUL:
324 case ISD::VECREDUCE_AND:
325 case ISD::VECREDUCE_OR:
326 case ISD::VECREDUCE_XOR:
327 case ISD::VECREDUCE_SMAX:
328 case ISD::VECREDUCE_SMIN:
329 case ISD::VECREDUCE_UMAX:
330 case ISD::VECREDUCE_UMIN:
331 Res = PromoteIntRes_VECREDUCE(N);
332 break;
333
334 case ISD::VP_REDUCE_ADD:
335 case ISD::VP_REDUCE_MUL:
336 case ISD::VP_REDUCE_AND:
337 case ISD::VP_REDUCE_OR:
338 case ISD::VP_REDUCE_XOR:
339 case ISD::VP_REDUCE_SMAX:
340 case ISD::VP_REDUCE_SMIN:
341 case ISD::VP_REDUCE_UMAX:
342 case ISD::VP_REDUCE_UMIN:
343 Res = PromoteIntRes_VP_REDUCE(N);
344 break;
345
346 case ISD::LOOP_DEPENDENCE_WAR_MASK:
347 case ISD::LOOP_DEPENDENCE_RAW_MASK:
348 Res = PromoteIntRes_LOOP_DEPENDENCE_MASK(N);
349 break;
350
351 case ISD::FREEZE:
352 Res = PromoteIntRes_FREEZE(N);
353 break;
354
355 case ISD::ROTL:
356 case ISD::ROTR:
357 Res = PromoteIntRes_Rotate(N);
358 break;
359
360 case ISD::FSHL:
361 case ISD::FSHR:
362 Res = PromoteIntRes_FunnelShift(N);
363 break;
364
365 case ISD::VP_FSHL:
366 case ISD::VP_FSHR:
367 Res = PromoteIntRes_VPFunnelShift(N);
368 break;
369
370 case ISD::CLMUL:
371 case ISD::CLMULH:
372 case ISD::CLMULR:
373 Res = PromoteIntRes_CLMUL(N);
374 break;
375
376 case ISD::PEXT:
377 Res = PromoteIntRes_PEXT(N);
378 break;
379
380 case ISD::PDEP:
381 Res = PromoteIntRes_PDEP(N);
382 break;
383
384 case ISD::IS_FPCLASS:
385 Res = PromoteIntRes_IS_FPCLASS(N);
386 break;
387 case ISD::FFREXP:
388 Res = PromoteIntRes_FFREXP(N);
389 break;
390
391 case ISD::LRINT:
392 case ISD::LLRINT:
393 Res = PromoteIntRes_XRINT(N);
394 break;
395
396 case ISD::PATCHPOINT:
397 Res = PromoteIntRes_PATCHPOINT(N);
398 break;
399 case ISD::READ_REGISTER:
400 Res = PromoteIntRes_READ_REGISTER(N);
401 break;
402 }
403
404 // If the result is null then the sub-method took care of registering it.
405 if (Res.getNode())
406 SetPromotedInteger(Op: SDValue(N, ResNo), Result: Res);
407}
408
409SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
410 unsigned ResNo) {
411 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
412 return GetPromotedInteger(Op);
413}
414
415SDValue DAGTypeLegalizer::PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
416 EVT VT = N->getValueType(ResNo: 0);
417 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
418 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: NewVT, Ops: N->ops());
419}
420
421SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
422 // Sign-extend the new bits, and continue the assertion.
423 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
424 return DAG.getNode(Opcode: ISD::AssertSext, DL: SDLoc(N),
425 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
426}
427
428SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
429 // Zero the new bits, and continue the assertion.
430 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
431 return DAG.getNode(Opcode: ISD::AssertZext, DL: SDLoc(N),
432 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
433}
434
435SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
436 EVT ResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
437 ISD::LoadExtType ExtType = N->getExtensionType();
438 if (ExtType == ISD::NON_EXTLOAD) {
439 switch (TLI.getExtendForAtomicOps()) {
440 case ISD::SIGN_EXTEND:
441 ExtType = ISD::SEXTLOAD;
442 break;
443 case ISD::ZERO_EXTEND:
444 ExtType = ISD::ZEXTLOAD;
445 break;
446 case ISD::ANY_EXTEND:
447 ExtType = ISD::EXTLOAD;
448 break;
449 default:
450 llvm_unreachable("Invalid atomic op extension");
451 }
452 }
453
454 SDValue Res =
455 DAG.getAtomicLoad(ExtType, dl: SDLoc(N), MemVT: N->getMemoryVT(), VT: ResVT,
456 Chain: N->getChain(), Ptr: N->getBasePtr(), MMO: N->getMemOperand());
457
458 // Legalize the chain result - switch anything that used the old chain to
459 // use the new one.
460 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
461 return Res;
462}
463
464SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
465 SDValue Op2 = N->getOperand(Num: 2);
466 switch (TLI.getExtendForAtomicRMWArg(Op: N->getOpcode())) {
467 case ISD::SIGN_EXTEND:
468 Op2 = SExtPromotedInteger(Op: Op2);
469 break;
470 case ISD::ZERO_EXTEND:
471 Op2 = ZExtPromotedInteger(Op: Op2);
472 break;
473 case ISD::ANY_EXTEND:
474 Op2 = GetPromotedInteger(Op: Op2);
475 break;
476 default:
477 llvm_unreachable("Invalid atomic op extension");
478 }
479 SDValue Res = DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N),
480 MemVT: N->getMemoryVT(),
481 Chain: N->getChain(), Ptr: N->getBasePtr(),
482 Val: Op2, MMO: N->getMemOperand());
483 // Legalize the chain result - switch anything that used the old chain to
484 // use the new one.
485 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
486 return Res;
487}
488
489SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
490 unsigned ResNo) {
491 if (ResNo == 1) {
492 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
493 EVT SVT = getSetCCResultType(VT: N->getOperand(Num: 2).getValueType());
494 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
495
496 // Only use the result of getSetCCResultType if it is legal,
497 // otherwise just use the promoted result type (NVT).
498 if (!TLI.isTypeLegal(VT: SVT))
499 SVT = NVT;
500
501 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: SVT, VT3: MVT::Other);
502 SDValue Res = DAG.getAtomicCmpSwap(
503 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs,
504 Chain: N->getChain(), Ptr: N->getBasePtr(), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
505 MMO: N->getMemOperand());
506 ReplaceValueWith(From: SDValue(N, 0), To: Res.getValue(R: 0));
507 ReplaceValueWith(From: SDValue(N, 2), To: Res.getValue(R: 2));
508 return DAG.getSExtOrTrunc(Op: Res.getValue(R: 1), DL: SDLoc(N), VT: NVT);
509 }
510
511 // Op2 is used for the comparison and thus must be extended according to the
512 // target's atomic operations. Op3 is merely stored and so can be left alone.
513 SDValue Op2 = N->getOperand(Num: 2);
514 SDValue Op3 = GetPromotedInteger(Op: N->getOperand(Num: 3));
515 switch (TLI.getExtendForAtomicCmpSwapArg()) {
516 case ISD::SIGN_EXTEND:
517 Op2 = SExtPromotedInteger(Op: Op2);
518 break;
519 case ISD::ZERO_EXTEND:
520 Op2 = ZExtPromotedInteger(Op: Op2);
521 break;
522 case ISD::ANY_EXTEND:
523 Op2 = GetPromotedInteger(Op: Op2);
524 break;
525 default:
526 llvm_unreachable("Invalid atomic op extension");
527 }
528
529 SDVTList VTs =
530 DAG.getVTList(VT1: Op2.getValueType(), VT2: N->getValueType(ResNo: 1), VT3: MVT::Other);
531 SDValue Res = DAG.getAtomicCmpSwap(
532 Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs, Chain: N->getChain(),
533 Ptr: N->getBasePtr(), Cmp: Op2, Swp: Op3, MMO: N->getMemOperand());
534 // Update the use to N with the newly created Res.
535 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
536 ReplaceValueWith(From: SDValue(N, i), To: Res.getValue(R: i));
537 return Res;
538}
539
540SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
541 SDValue InOp = N->getOperand(Num: 0);
542 EVT InVT = InOp.getValueType();
543 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
544 EVT OutVT = N->getValueType(ResNo: 0);
545 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
546 SDLoc dl(N);
547
548 switch (getTypeAction(VT: InVT)) {
549 case TargetLowering::TypeLegal:
550 break;
551 case TargetLowering::TypePromoteInteger:
552 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector() && !NInVT.isVector())
553 // The input promotes to the same size. Convert the promoted value.
554 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetPromotedInteger(Op: InOp));
555 break;
556 case TargetLowering::TypeSoftenFloat:
557 // Promote the integer operand by hand.
558 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftenedFloat(Op: InOp));
559 case TargetLowering::TypeSoftPromoteHalf:
560 // Promote the integer operand by hand.
561 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftPromotedHalf(Op: InOp));
562 case TargetLowering::TypeExpandInteger:
563 case TargetLowering::TypeExpandFloat:
564 break;
565 case TargetLowering::TypeScalarizeVector:
566 // Convert the element to an integer and promote it by hand.
567 if (!NOutVT.isVector())
568 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
569 Operand: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)));
570 break;
571 case TargetLowering::TypeScalarizeScalableVector:
572 report_fatal_error(reason: "Scalarization of scalable vectors is not supported.");
573 case TargetLowering::TypeSplitVector: {
574 if (!NOutVT.isVector()) {
575 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
576 // pieces of the input into integers and reassemble in the final type.
577 SDValue Lo, Hi;
578 GetSplitVector(Op: N->getOperand(Num: 0), Lo, Hi);
579 Lo = BitConvertToInteger(Op: Lo);
580 Hi = BitConvertToInteger(Op: Hi);
581
582 if (DAG.getDataLayout().isBigEndian())
583 std::swap(a&: Lo, b&: Hi);
584
585 InOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
586 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
587 BitWidth: NOutVT.getSizeInBits()),
588 Operand: JoinIntegers(Lo, Hi));
589 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: InOp);
590 }
591 break;
592 }
593 case TargetLowering::TypeWidenVector:
594 // The input is widened to the same size. Convert to the widened value.
595 // Make sure that the outgoing value is not a vector, because this would
596 // make us bitcast between two vectors which are legalized in different ways.
597 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector()) {
598 SDValue Res =
599 DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetWidenedVector(Op: InOp));
600
601 // For big endian targets we need to shift the casted value or the
602 // interesting bits will end up at the wrong place.
603 if (DAG.getDataLayout().isBigEndian()) {
604 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
605 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
606 Res = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NOutVT, N1: Res,
607 N2: DAG.getShiftAmountConstant(Val: ShiftAmt, VT: NOutVT, DL: dl));
608 }
609 return Res;
610 }
611 // If the output type is also a vector and widening it to the same size
612 // as the widened input type would be a legal type, we can widen the bitcast
613 // and handle the promotion after.
614 if (NOutVT.isVector()) {
615 TypeSize WidenInSize = NInVT.getSizeInBits();
616 TypeSize OutSize = OutVT.getSizeInBits();
617 if (WidenInSize.hasKnownScalarFactor(RHS: OutSize)) {
618 unsigned Scale = WidenInSize.getKnownScalarFactor(RHS: OutSize);
619 EVT WideOutVT =
620 EVT::getVectorVT(Context&: *DAG.getContext(), VT: OutVT.getVectorElementType(),
621 EC: OutVT.getVectorElementCount() * Scale);
622 if (isTypeLegal(VT: WideOutVT)) {
623 InOp = DAG.getBitcast(VT: WideOutVT, V: GetWidenedVector(Op: InOp));
624 InOp = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: InOp,
625 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
626 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: InOp);
627 }
628 }
629 }
630 }
631
632 // TODO: Handle big endian
633 if (!NOutVT.isVector() && InOp.getValueType().isVector() &&
634 DAG.getDataLayout().isLittleEndian()) {
635 // Pad the vector operand with undef and cast to a wider integer.
636 EVT EltVT = InOp.getValueType().getVectorElementType();
637 TypeSize EltSize = EltVT.getSizeInBits();
638 TypeSize OutSize = NOutVT.getSizeInBits();
639
640 if (OutSize.hasKnownScalarFactor(RHS: EltSize)) {
641 unsigned NumEltsWithPadding = OutSize.getKnownScalarFactor(RHS: EltSize);
642 EVT WideVecVT =
643 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
644
645 if (isTypeLegal(VT: WideVecVT)) {
646 SDValue Inserted = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: WideVecVT,
647 N1: DAG.getUNDEF(VT: WideVecVT), N2: InOp,
648 N3: DAG.getVectorIdxConstant(Val: 0, DL: dl));
649
650 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Inserted);
651 }
652 }
653 }
654
655 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
656 Operand: CreateStackStoreLoad(Op: InOp, DestVT: OutVT));
657}
658
659SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
660 SDValue V = GetPromotedInteger(Op: N->getOperand(Num: 0));
661 return DAG.getNode(Opcode: ISD::FREEZE, DL: SDLoc(N),
662 VT: V.getValueType(), Operand: V);
663}
664
665SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
666 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
667 EVT OVT = N->getValueType(ResNo: 0);
668 EVT NVT = Op.getValueType();
669 SDLoc dl(N);
670
671 // If the larger BSWAP isn't supported by the target, try to expand now.
672 // If we expand later we'll end up with more operations since we lost the
673 // original type. We only do this for scalars since we have a shuffle
674 // based lowering for vectors in LegalizeVectorOps.
675 if (!OVT.isVector() &&
676 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BSWAP, VT: NVT)) {
677 if (SDValue Res = TLI.expandBSWAP(N, DAG))
678 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
679 }
680
681 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
682 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
683 if (N->getOpcode() == ISD::BSWAP)
684 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: NVT, Operand: Op),
685 N2: ShAmt);
686 SDValue Mask = N->getOperand(Num: 1);
687 SDValue EVL = N->getOperand(Num: 2);
688 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
689 N1: DAG.getNode(Opcode: ISD::VP_BSWAP, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL), N2: ShAmt,
690 N3: Mask, N4: EVL);
691}
692
693SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
694 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
695 EVT OVT = N->getValueType(ResNo: 0);
696 EVT NVT = Op.getValueType();
697 SDLoc dl(N);
698
699 // If the larger BITREVERSE isn't supported by the target, try to expand now.
700 // If we expand later we'll end up with more operations since we lost the
701 // original type. We only do this for scalars since we have a shuffle
702 // based lowering for vectors in LegalizeVectorOps.
703 if (!OVT.isVector() && OVT.isSimple() &&
704 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BITREVERSE, VT: NVT)) {
705 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
706 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
707 }
708
709 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
710 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
711 if (N->getOpcode() == ISD::BITREVERSE)
712 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT,
713 N1: DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: NVT, Operand: Op), N2: ShAmt);
714 SDValue Mask = N->getOperand(Num: 1);
715 SDValue EVL = N->getOperand(Num: 2);
716 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
717 N1: DAG.getNode(Opcode: ISD::VP_BITREVERSE, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
718 N2: ShAmt, N3: Mask, N4: EVL);
719}
720
721SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
722 // The pair element type may be legal, or may not promote to the same type as
723 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
724 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N),
725 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
726 VT: N->getValueType(ResNo: 0)), Operand: JoinIntegers(Lo: N->getOperand(Num: 0),
727 Hi: N->getOperand(Num: 1)));
728}
729
730SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
731 EVT VT = N->getValueType(ResNo: 0);
732 // FIXME there is no actual debug info here
733 SDLoc dl(N);
734 // Zero extend things like i1, sign extend everything else. It shouldn't
735 // matter in theory which one we pick, but this tends to give better code?
736 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
737 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl,
738 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT),
739 Operand: SDValue(N, 0));
740 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
741 return Result;
742}
743
744SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
745 EVT OVT = N->getValueType(ResNo: 0);
746 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
747 SDLoc dl(N);
748
749 // If the larger CTLZ isn't supported by the target, try to expand now.
750 // If we expand later we'll end up with more operations since we lost the
751 // original type.
752 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
753 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ, VT: NVT) &&
754 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ_ZERO_POISON, VT: NVT)) {
755 if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
756 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
757 return Result;
758 }
759 }
760
761 unsigned CtlzOpcode = N->getOpcode();
762 if (CtlzOpcode == ISD::CTLZ || CtlzOpcode == ISD::VP_CTLZ) {
763 // Subtract off the extra leading bits in the bigger type.
764 SDValue ExtractLeadingBits = DAG.getConstant(
765 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
766 // Zero extend to the promoted type and do the count there.
767 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
768
769 // At this stage SUB is guaranteed to be positive no-wrap,
770 // that to be used in further KnownBits optimizations.
771 if (!N->isVPOpcode())
772 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT,
773 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Op),
774 N2: ExtractLeadingBits, Flags: SDNodeFlags::NoUnsignedWrap);
775 SDValue Mask = N->getOperand(Num: 1);
776 SDValue EVL = N->getOperand(Num: 2);
777 return DAG.getNode(Opcode: ISD::VP_SUB, DL: dl, VT: NVT,
778 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
779 N2: ExtractLeadingBits, N3: Mask, N4: EVL,
780 Flags: SDNodeFlags::NoUnsignedWrap);
781 }
782 if (CtlzOpcode == ISD::CTLZ_ZERO_POISON ||
783 CtlzOpcode == ISD::VP_CTLZ_ZERO_POISON) {
784 // Any Extend the argument
785 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
786 // Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
787 unsigned SHLAmount = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
788 auto ShiftConst =
789 DAG.getShiftAmountConstant(Val: SHLAmount, VT: Op.getValueType(), DL: dl);
790 if (!N->isVPOpcode()) {
791 Op = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst);
792 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, Operand: Op);
793 }
794
795 SDValue Mask = N->getOperand(Num: 1);
796 SDValue EVL = N->getOperand(Num: 2);
797 Op = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst, N3: Mask, N4: EVL);
798 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL);
799 }
800 llvm_unreachable("Invalid CTLZ Opcode");
801}
802
803SDValue DAGTypeLegalizer::PromoteIntRes_CTLS(SDNode *N) {
804 EVT OVT = N->getValueType(ResNo: 0);
805 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
806 SDLoc dl(N);
807
808 SDValue ExtractLeadingBits = DAG.getConstant(
809 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
810
811 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
812 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Op),
813 N2: ExtractLeadingBits);
814}
815
816SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
817 EVT OVT = N->getValueType(ResNo: 0);
818 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
819
820 // If the larger CTPOP isn't supported by the target, try to expand now.
821 // If we expand later we'll end up with more operations since we lost the
822 // original type.
823 // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
824 // TargetLowering.
825 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
826 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTPOP, VT: NVT)) {
827 if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
828 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Result);
829 return Result;
830 }
831 }
832
833 // Zero extend to the promoted type and do the count or parity there.
834 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
835 if (!N->isVPOpcode())
836 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), Operand: Op);
837
838 SDValue Mask = N->getOperand(Num: 1);
839 SDValue EVL = N->getOperand(Num: 2);
840 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), N1: Op, N2: Mask,
841 N3: EVL);
842}
843
844SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
845 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
846 EVT OVT = N->getValueType(ResNo: 0);
847 EVT NVT = Op.getValueType();
848 SDLoc dl(N);
849
850 // If the larger CTTZ isn't supported by the target, try to expand now.
851 // If we expand later we'll end up with more operations since we lost the
852 // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
853 // larger type.
854 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
855 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ, VT: NVT) &&
856 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ_ZERO_POISON, VT: NVT) &&
857 !TLI.isOperationLegal(Op: ISD::CTPOP, VT: NVT) &&
858 !TLI.isOperationLegal(Op: ISD::CTLZ, VT: NVT)) {
859 if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
860 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
861 return Result;
862 }
863 }
864
865 unsigned NewOpc = N->getOpcode();
866 if (NewOpc == ISD::CTTZ || NewOpc == ISD::VP_CTTZ) {
867 // The count is the same in the promoted type except if the original
868 // value was zero. This can be handled by setting the bit just off
869 // the top of the original type.
870 auto TopBit = APInt::getOneBitSet(numBits: NVT.getScalarSizeInBits(),
871 BitNo: OVT.getScalarSizeInBits());
872 if (NewOpc == ISD::CTTZ) {
873 Op = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
874 NewOpc = ISD::CTTZ_ZERO_POISON;
875 } else {
876 Op =
877 DAG.getNode(Opcode: ISD::VP_OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT),
878 N3: N->getOperand(Num: 1), N4: N->getOperand(Num: 2));
879 NewOpc = ISD::VP_CTTZ_ZERO_POISON;
880 }
881 }
882 if (!N->isVPOpcode())
883 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Op);
884 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, N1: Op, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
885}
886
887SDValue DAGTypeLegalizer::PromoteIntRes_VP_CttzElements(SDNode *N) {
888 SDLoc DL(N);
889 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
890 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NewVT, Ops: N->ops());
891}
892
893SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
894 SDLoc dl(N);
895 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
896
897 SDValue Op0 = N->getOperand(Num: 0);
898 SDValue Op1 = N->getOperand(Num: 1);
899
900 // If the input also needs to be promoted, do that first so we can get a
901 // get a good idea for the output type.
902 if (TLI.getTypeAction(Context&: *DAG.getContext(), VT: Op0.getValueType())
903 == TargetLowering::TypePromoteInteger) {
904 SDValue In = GetPromotedInteger(Op: Op0);
905
906 // If the new type is larger than NVT, use it. We probably won't need to
907 // promote it again.
908 EVT SVT = In.getValueType().getScalarType();
909 if (SVT.bitsGE(VT: NVT)) {
910 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SVT, N1: In, N2: Op1);
911 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NVT);
912 }
913 }
914
915 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NVT, N1: Op0, N2: Op1);
916}
917
918SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
919 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
920 unsigned NewOpc =
921 TLI.getPreferredFPToIntOpcode(Op: N->getOpcode(), FromVT: N->getValueType(ResNo: 0), ToVT: NVT);
922 SDLoc dl(N);
923
924 SDValue Res;
925 if (N->isStrictFPOpcode()) {
926 Res = DAG.getNode(Opcode: NewOpc, DL: dl, ResultTys: {NVT, MVT::Other},
927 Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1)});
928 // Legalize the chain result - switch anything that used the old chain to
929 // use the new one.
930 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
931 } else if (NewOpc == ISD::VP_FP_TO_SINT || NewOpc == ISD::VP_FP_TO_UINT) {
932 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1),
933 N->getOperand(Num: 2)});
934 } else {
935 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
936 }
937
938 // Assert that the converted value fits in the original type. If it doesn't
939 // (eg: because the value being converted is too big), then the result of the
940 // original operation was undefined anyway, so the assert is still correct.
941 //
942 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
943 // before legalization: fp-to-uint16, 65534. -> 0xfffe
944 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
945 return DAG.getNode(Opcode: (N->getOpcode() == ISD::FP_TO_UINT ||
946 N->getOpcode() == ISD::STRICT_FP_TO_UINT ||
947 N->getOpcode() == ISD::VP_FP_TO_UINT)
948 ? ISD::AssertZext
949 : ISD::AssertSext,
950 DL: dl, VT: NVT, N1: Res,
951 N2: DAG.getValueType(N->getValueType(ResNo: 0).getScalarType()));
952}
953
954SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
955 // Promote the result type, while keeping the original width in Op1.
956 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
957 SDLoc dl(N);
958 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
959 N2: N->getOperand(Num: 1));
960}
961
962SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16_BF16(SDNode *N) {
963 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
964 SDLoc dl(N);
965
966 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
967}
968
969// TODO: CONVERT_TO_ARBITRARY_FP also needs an ExpandIntegerResult handler for
970// wider arbitrary FP formats whose integer result requires expansion.
971SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_TO_ARBITRARY_FP(SDNode *N) {
972 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
973 SDLoc dl(N);
974
975 return DAG.getNode(Opcode: ISD::CONVERT_TO_ARBITRARY_FP, DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
976 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
977}
978
979SDValue DAGTypeLegalizer::PromoteIntRes_STRICT_FP_TO_FP16_BF16(SDNode *N) {
980 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
981 SDLoc dl(N);
982
983 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
984 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
985 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
986 return Res;
987}
988
989SDValue DAGTypeLegalizer::PromoteIntRes_XRINT(SDNode *N) {
990 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
991 SDLoc dl(N);
992 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
993}
994
995SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) {
996 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
997 SDLoc dl(N);
998
999 SDValue Res =
1000 DAG.getNode(Opcode: N->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
1001
1002 // Legalize the chain result - switch anything that used the old chain to
1003 // use the new one.
1004 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1005 return Res;
1006}
1007
1008SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
1009 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1010 SDLoc dl(N);
1011
1012 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
1013 == TargetLowering::TypePromoteInteger) {
1014 SDValue Res = GetPromotedInteger(Op: N->getOperand(Num: 0));
1015 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
1016
1017 // If the result and operand types are the same after promotion, simplify
1018 // to an in-register extension. Unless this is a VP_*_EXTEND.
1019 if (NVT == Res.getValueType() && N->getNumOperands() == 1) {
1020 // The high bits are not guaranteed to be anything. Insert an extend.
1021 if (N->getOpcode() == ISD::SIGN_EXTEND)
1022 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1023 N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
1024 if (N->getOpcode() == ISD::ZERO_EXTEND)
1025 return DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: N->getOperand(Num: 0).getValueType());
1026 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
1027 return Res;
1028 }
1029 }
1030
1031 // Otherwise, just extend the original operand all the way to the larger type.
1032 if (N->getNumOperands() != 1) {
1033 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
1034 assert(N->isVPOpcode() && "Expected VP opcode");
1035 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
1036 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
1037 }
1038 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
1039}
1040
1041SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
1042 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1043 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1044 ISD::LoadExtType ExtType =
1045 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
1046 SDLoc dl(N);
1047 SDValue Res = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
1048 MemVT: N->getMemoryVT(), MMO: N->getMemOperand());
1049
1050 // Legalize the chain result - switch anything that used the old chain to
1051 // use the new one.
1052 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1053 return Res;
1054}
1055
1056SDValue DAGTypeLegalizer::PromoteIntRes_VP_LOAD(VPLoadSDNode *N) {
1057 assert(!N->isIndexed() && "Indexed vp_load during type legalization!");
1058 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1059 ISD::LoadExtType ExtType = (N->getExtensionType() == ISD::NON_EXTLOAD)
1060 ? ISD::EXTLOAD
1061 : N->getExtensionType();
1062 SDLoc dl(N);
1063 SDValue Res =
1064 DAG.getExtLoadVP(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
1065 Mask: N->getMask(), EVL: N->getVectorLength(), MemVT: N->getMemoryVT(),
1066 MMO: N->getMemOperand(), IsExpanding: N->isExpandingLoad());
1067 // Legalize the chain result - switch anything that used the old chain to
1068 // use the new one.
1069 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1070 return Res;
1071}
1072
1073SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
1074 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1075 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1076
1077 ISD::LoadExtType ExtType = N->getExtensionType();
1078 if (ExtType == ISD::NON_EXTLOAD)
1079 ExtType = ISD::EXTLOAD;
1080
1081 SDLoc dl(N);
1082 SDValue Res = DAG.getMaskedLoad(VT: NVT, dl, Chain: N->getChain(), Base: N->getBasePtr(),
1083 Offset: N->getOffset(), Mask: N->getMask(), Src0: ExtPassThru,
1084 MemVT: N->getMemoryVT(), MMO: N->getMemOperand(),
1085 AM: N->getAddressingMode(), ExtType,
1086 IsExpanding: N->isExpandingLoad());
1087 // Legalize the chain result - switch anything that used the old chain to
1088 // use the new one.
1089 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1090 return Res;
1091}
1092
1093SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
1094 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1095 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1096 assert(NVT == ExtPassThru.getValueType() &&
1097 "Gather result type and the passThru argument type should be the same");
1098
1099 ISD::LoadExtType ExtType = N->getExtensionType();
1100 if (ExtType == ISD::NON_EXTLOAD)
1101 ExtType = ISD::EXTLOAD;
1102
1103 SDLoc dl(N);
1104 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
1105 N->getIndex(), N->getScale() };
1106 SDValue Res = DAG.getMaskedGather(VTs: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
1107 MemVT: N->getMemoryVT(), dl, Ops,
1108 MMO: N->getMemOperand(), IndexType: N->getIndexType(),
1109 ExtTy: ExtType);
1110 // Legalize the chain result - switch anything that used the old chain to
1111 // use the new one.
1112 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1113 return Res;
1114}
1115
1116SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_COMPRESS(SDNode *N) {
1117 SDValue Vec = GetPromotedInteger(Op: N->getOperand(Num: 0));
1118 SDValue Passthru = GetPromotedInteger(Op: N->getOperand(Num: 2));
1119 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT: Vec.getValueType(), N1: Vec,
1120 N2: N->getOperand(Num: 1), N3: Passthru);
1121}
1122
1123/// Promote the overflow flag of an overflowing arithmetic node.
1124SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
1125 // Change the return type of the boolean result while obeying
1126 // getSetCCResultType.
1127 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1128 EVT VT = N->getValueType(ResNo: 0);
1129 EVT SVT = getSetCCResultType(VT);
1130 SDValue Ops[3] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
1131 unsigned NumOps = N->getNumOperands();
1132 assert(NumOps <= 3 && "Too many operands");
1133 if (NumOps == 3)
1134 Ops[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: VT);
1135
1136 SDLoc dl(N);
1137 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: SVT),
1138 Ops: ArrayRef(Ops, NumOps));
1139
1140 // Modified the sum result - switch anything that used the old sum to use
1141 // the new one.
1142 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1143
1144 // Convert to the expected type.
1145 return DAG.getBoolExtOrTrunc(Op: Res.getValue(R: 1), SL: dl, VT: NVT, OpVT: VT);
1146}
1147
1148template <class MatchContextClass>
1149SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
1150 // If the promoted type is legal, we can convert this to:
1151 // 1. ANY_EXTEND iN to iM
1152 // 2. SHL by M-N
1153 // 3. [US][ADD|SUB|SHL]SAT
1154 // 4. L/ASHR by M-N
1155 // Else it is more efficient to convert this to a min and a max
1156 // operation in the higher precision arithmetic.
1157 SDLoc dl(N);
1158 SDValue Op1 = N->getOperand(Num: 0);
1159 SDValue Op2 = N->getOperand(Num: 1);
1160 MatchContextClass matcher(DAG, TLI, N);
1161
1162 unsigned Opcode = matcher.getRootBaseOpcode();
1163 unsigned OldBits = Op1.getScalarValueSizeInBits();
1164
1165 // USUBSAT can always be promoted as long as we have zero/sign-extended the
1166 // args.
1167 if (Opcode == ISD::USUBSAT) {
1168 SExtOrZExtPromotedOperands(LHS&: Op1, RHS&: Op2);
1169 return matcher.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
1170 }
1171
1172 if (Opcode == ISD::UADDSAT) {
1173 EVT OVT = Op1.getValueType();
1174 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1175 // We can promote if we use sign-extend. Do this if the target prefers.
1176 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT)) {
1177 Op1 = SExtPromotedInteger(Op: Op1);
1178 Op2 = SExtPromotedInteger(Op: Op2);
1179 return matcher.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2);
1180 }
1181
1182 Op1 = ZExtPromotedInteger(Op: Op1);
1183 Op2 = ZExtPromotedInteger(Op: Op2);
1184 unsigned NewBits = NVT.getScalarSizeInBits();
1185 APInt MaxVal = APInt::getLowBitsSet(numBits: NewBits, loBitsSet: OldBits);
1186 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: NVT);
1187 SDValue Add = matcher.getNode(ISD::ADD, dl, NVT, Op1, Op2);
1188 return matcher.getNode(ISD::UMIN, dl, NVT, Add, SatMax);
1189 }
1190
1191 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
1192
1193 // FIXME: We need vp-aware PromotedInteger functions.
1194 if (IsShift) {
1195 Op1 = GetPromotedInteger(Op: Op1);
1196 if (getTypeAction(VT: Op2.getValueType()) == TargetLowering::TypePromoteInteger)
1197 Op2 = ZExtPromotedInteger(Op: Op2);
1198 } else {
1199 Op1 = SExtPromotedInteger(Op: Op1);
1200 Op2 = SExtPromotedInteger(Op: Op2);
1201 }
1202 EVT PromotedType = Op1.getValueType();
1203 unsigned NewBits = PromotedType.getScalarSizeInBits();
1204
1205 // Shift cannot use a min/max expansion, we can't detect overflow if all of
1206 // the bits have been shifted out.
1207 if (IsShift || matcher.isOperationLegal(Opcode, PromotedType)) {
1208 unsigned ShiftOp;
1209 switch (Opcode) {
1210 case ISD::SADDSAT:
1211 case ISD::SSUBSAT:
1212 case ISD::SSHLSAT:
1213 ShiftOp = ISD::SRA;
1214 break;
1215 case ISD::USHLSAT:
1216 ShiftOp = ISD::SRL;
1217 break;
1218 default:
1219 llvm_unreachable("Expected opcode to be signed or unsigned saturation "
1220 "addition, subtraction or left shift");
1221 }
1222
1223 unsigned SHLAmount = NewBits - OldBits;
1224 SDValue ShiftAmount =
1225 DAG.getShiftAmountConstant(Val: SHLAmount, VT: PromotedType, DL: dl);
1226 Op1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1, N2: ShiftAmount);
1227 if (!IsShift)
1228 Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
1229
1230 SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
1231 return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
1232 }
1233
1234 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
1235 APInt MinVal = APInt::getSignedMinValue(numBits: OldBits).sext(width: NewBits);
1236 APInt MaxVal = APInt::getSignedMaxValue(numBits: OldBits).sext(width: NewBits);
1237 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT: PromotedType);
1238 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: PromotedType);
1239 SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
1240 Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
1241 Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
1242 return Result;
1243}
1244
1245SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
1246 // Can just promote the operands then continue with operation.
1247 SDLoc dl(N);
1248 SDValue Op1Promoted, Op2Promoted;
1249 bool Signed =
1250 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
1251 bool Saturating =
1252 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
1253 if (Signed) {
1254 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1255 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1256 } else {
1257 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1258 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1259 }
1260 EVT OldType = N->getOperand(Num: 0).getValueType();
1261 EVT PromotedType = Op1Promoted.getValueType();
1262 unsigned DiffSize =
1263 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
1264
1265 if (Saturating) {
1266 // Promoting the operand and result values changes the saturation width,
1267 // which is extends the values that we clamp to on saturation. This could be
1268 // resolved by shifting one of the operands the same amount, which would
1269 // also shift the result we compare against, then shifting back.
1270 Op1Promoted =
1271 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1272 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1273 SDValue Result = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1274 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1275 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1276 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result,
1277 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1278 }
1279 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted, N2: Op2Promoted,
1280 N3: N->getOperand(Num: 2));
1281}
1282
1283static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
1284 unsigned SatW, bool Signed,
1285 const TargetLowering &TLI,
1286 SelectionDAG &DAG) {
1287 EVT VT = V.getValueType();
1288 unsigned VTW = VT.getScalarSizeInBits();
1289
1290 if (!Signed) {
1291 // Saturate to the unsigned maximum by getting the minimum of V and the
1292 // maximum.
1293 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT, N1: V,
1294 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW),
1295 DL: dl, VT));
1296 }
1297
1298 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
1299 // signed minimum of it and V.
1300 V = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT, N1: V,
1301 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW - 1),
1302 DL: dl, VT));
1303 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
1304 // signed maximum of it and V.
1305 V = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT, N1: V,
1306 N2: DAG.getConstant(Val: APInt::getHighBitsSet(numBits: VTW, hiBitsSet: VTW - SatW + 1),
1307 DL: dl, VT));
1308 return V;
1309}
1310
1311static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
1312 unsigned Scale, const TargetLowering &TLI,
1313 SelectionDAG &DAG, unsigned SatW = 0) {
1314 EVT VT = LHS.getValueType();
1315 unsigned VTSize = VT.getScalarSizeInBits();
1316 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1317 N->getOpcode() == ISD::SDIVFIXSAT;
1318 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1319 N->getOpcode() == ISD::UDIVFIXSAT;
1320
1321 SDLoc dl(N);
1322 // Widen the types by a factor of two. This is guaranteed to expand, since it
1323 // will always have enough high bits in the LHS to shift into.
1324 EVT WideVT = VT.changeElementType(
1325 Context&: *DAG.getContext(), EltVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: VTSize * 2));
1326 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL: dl, VT: WideVT);
1327 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL: dl, VT: WideVT);
1328 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS, RHS, Scale,
1329 DAG);
1330 assert(Res && "Expanding DIVFIX with wide type failed?");
1331 if (Saturating) {
1332 // If the caller has told us to saturate at something less, use that width
1333 // instead of the type before doubling. However, it cannot be more than
1334 // what we just widened!
1335 assert(SatW <= VTSize &&
1336 "Tried to saturate to more than the original type?");
1337 Res = SaturateWidenedDIVFIX(V: Res, dl, SatW: SatW == 0 ? VTSize : SatW, Signed,
1338 TLI, DAG);
1339 }
1340 return DAG.getZExtOrTrunc(Op: Res, DL: dl, VT);
1341}
1342
1343SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1344 SDLoc dl(N);
1345 SDValue Op1Promoted, Op2Promoted;
1346 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1347 N->getOpcode() == ISD::SDIVFIXSAT;
1348 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1349 N->getOpcode() == ISD::UDIVFIXSAT;
1350 if (Signed) {
1351 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1352 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1353 } else {
1354 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1355 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1356 }
1357 EVT PromotedType = Op1Promoted.getValueType();
1358 unsigned Scale = N->getConstantOperandVal(Num: 2);
1359
1360 // If the type is already legal and the operation is legal in that type, we
1361 // should not early expand.
1362 if (TLI.isTypeLegal(VT: PromotedType)) {
1363 TargetLowering::LegalizeAction Action =
1364 TLI.getFixedPointOperationAction(Op: N->getOpcode(), VT: PromotedType, Scale);
1365 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1366 unsigned Diff = PromotedType.getScalarSizeInBits() -
1367 N->getValueType(ResNo: 0).getScalarSizeInBits();
1368 if (Saturating)
1369 Op1Promoted =
1370 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1371 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1372 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1373 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1374 if (Saturating)
1375 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL: dl, VT: PromotedType, N1: Res,
1376 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1377 return Res;
1378 }
1379 }
1380
1381 // See if we can perform the division in this type without expanding.
1382 if (SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: Op1Promoted,
1383 RHS: Op2Promoted, Scale, DAG)) {
1384 if (Saturating)
1385 Res = SaturateWidenedDIVFIX(V: Res, dl,
1386 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits(),
1387 Signed, TLI, DAG);
1388 return Res;
1389 }
1390 // If we cannot, expand it to twice the type width. If we are saturating, give
1391 // it the original width as a saturating width so we don't need to emit
1392 // two saturations.
1393 return earlyExpandDIVFIX(N, LHS: Op1Promoted, RHS: Op2Promoted, Scale, TLI, DAG,
1394 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits());
1395}
1396
1397SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1398 if (ResNo == 1)
1399 return PromoteIntRes_Overflow(N);
1400
1401 // The operation overflowed iff the result in the larger type is not the
1402 // sign extension of its truncation to the original type.
1403 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1404 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1405 EVT OVT = N->getOperand(Num: 0).getValueType();
1406 EVT NVT = LHS.getValueType();
1407 SDLoc dl(N);
1408
1409 // Do the arithmetic in the larger type.
1410 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1411 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1412
1413 // Calculate the overflow flag: sign extend the arithmetic result from
1414 // the original type.
1415 SDValue Ofl = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1416 N2: DAG.getValueType(OVT));
1417 // Overflowed if and only if this is not equal to Res.
1418 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1419
1420 // Use the calculated overflow everywhere.
1421 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1422
1423 return Res;
1424}
1425
1426SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
1427 EVT PromotedResultTy =
1428 TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1429 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: PromotedResultTy,
1430 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
1431}
1432
1433SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1434 SDValue Mask = N->getOperand(Num: 0);
1435
1436 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1437 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1438
1439 unsigned Opcode = N->getOpcode();
1440 if (Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE)
1441 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS,
1442 N4: N->getOperand(Num: 3));
1443 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS);
1444}
1445
1446SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1447 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1448 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 3));
1449 return DAG.getNode(Opcode: ISD::SELECT_CC, DL: SDLoc(N),
1450 VT: LHS.getValueType(), N1: N->getOperand(Num: 0),
1451 N2: N->getOperand(Num: 1), N3: LHS, N4: RHS, N5: N->getOperand(Num: 4));
1452}
1453
1454SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1455 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1456 EVT InVT = N->getOperand(Num: OpNo).getValueType();
1457 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1458
1459 EVT SVT = getSetCCResultType(VT: InVT);
1460
1461 // If we got back a type that needs to be promoted, this likely means the
1462 // the input type also needs to be promoted. So get the promoted type for
1463 // the input and try the query again.
1464 if (getTypeAction(VT: SVT) == TargetLowering::TypePromoteInteger) {
1465 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
1466 InVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
1467 SVT = getSetCCResultType(VT: InVT);
1468 } else {
1469 // Input type isn't promoted, just use the default promoted type.
1470 SVT = NVT;
1471 }
1472 }
1473
1474 SDLoc dl(N);
1475 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1476 "Vector compare must return a vector result!");
1477
1478 // Get the SETCC result using the canonical SETCC type.
1479 SDValue SetCC;
1480 if (N->isStrictFPOpcode()) {
1481 SDVTList VTs = DAG.getVTList(VTs: {SVT, MVT::Other});
1482 SDValue Opers[] = {N->getOperand(Num: 0), N->getOperand(Num: 1),
1483 N->getOperand(Num: 2), N->getOperand(Num: 3)};
1484 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: VTs, Ops: Opers, Flags: N->getFlags());
1485 // Legalize the chain result - switch anything that used the old chain to
1486 // use the new one.
1487 ReplaceValueWith(From: SDValue(N, 1), To: SetCC.getValue(R: 1));
1488 } else
1489 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: SVT, N1: N->getOperand(Num: 0),
1490 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), Flags: N->getFlags());
1491
1492 // Convert to the expected type.
1493 return DAG.getSExtOrTrunc(Op: SetCC, DL: dl, VT: NVT);
1494}
1495
1496SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
1497 SDLoc DL(N);
1498 SDValue Arg = N->getOperand(Num: 0);
1499 SDValue Test = N->getOperand(Num: 1);
1500 EVT NResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1501 return DAG.getNode(Opcode: ISD::IS_FPCLASS, DL, VT: NResVT, N1: Arg, N2: Test);
1502}
1503
1504SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
1505 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1506 EVT VT = N->getValueType(ResNo: 0);
1507
1508 SDLoc dl(N);
1509 SDValue Res =
1510 DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: NVT), N: N->getOperand(Num: 0));
1511
1512 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1513 return Res.getValue(R: 1);
1514}
1515
1516SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1517 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1518 SDValue RHS = N->getOperand(Num: 1);
1519 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1520 RHS = ZExtPromotedInteger(Op: RHS);
1521 if (N->getOpcode() != ISD::VP_SHL)
1522 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1523
1524 SDValue Mask = N->getOperand(Num: 2);
1525 SDValue EVL = N->getOperand(Num: 3);
1526 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1527 N3: Mask, N4: EVL);
1528}
1529
1530SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1531 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
1532 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: SDLoc(N),
1533 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
1534}
1535
1536SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1537 // The input may have strange things in the top bits of the registers, but
1538 // these operations don't care. They may have weird bits going out, but
1539 // that too is okay if they are integer operations.
1540 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1541 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1542 if (N->getNumOperands() == 2)
1543 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1544 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1545 assert(N->isVPOpcode() && "Expected VP opcode");
1546 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1547 N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
1548}
1549
1550SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1551 // Sign extend the input.
1552 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1553 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1554 if (N->getNumOperands() == 2)
1555 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1556 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1557 assert(N->isVPOpcode() && "Expected VP opcode");
1558 SDValue Mask = N->getOperand(Num: 2);
1559 SDValue EVL = N->getOperand(Num: 3);
1560 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1561 N3: Mask, N4: EVL);
1562}
1563
1564SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1565 // Zero extend the input.
1566 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1567 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1568 if (N->getNumOperands() == 2)
1569 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1570 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1571 assert(N->isVPOpcode() && "Expected VP opcode");
1572 // Zero extend the input.
1573 SDValue Mask = N->getOperand(Num: 2);
1574 SDValue EVL = N->getOperand(Num: 3);
1575 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1576 N3: Mask, N4: EVL);
1577}
1578
1579SDValue DAGTypeLegalizer::PromoteIntRes_ZExtMaskedIntBinOp(SDNode *N) {
1580 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1581 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1582 SDValue Mask = N->getOperand(Num: 2);
1583 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1584 N3: Mask);
1585}
1586
1587SDValue DAGTypeLegalizer::PromoteIntRes_SExtMaskedIntBinOp(SDNode *N) {
1588 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1589 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1590 SDValue Mask = N->getOperand(Num: 2);
1591 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1592 N3: Mask);
1593}
1594
1595SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1596 SDValue LHS = N->getOperand(Num: 0);
1597 SDValue RHS = N->getOperand(Num: 1);
1598
1599 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1600 // whatever is best for the target and the promoted operands.
1601 SExtOrZExtPromotedOperands(LHS, RHS);
1602
1603 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N),
1604 VT: LHS.getValueType(), N1: LHS, N2: RHS);
1605}
1606
1607SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1608 // The input value must be properly sign extended.
1609 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1610 SDValue RHS = N->getOperand(Num: 1);
1611 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1612 RHS = ZExtPromotedInteger(Op: RHS);
1613 if (N->getOpcode() != ISD::VP_SRA)
1614 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1615
1616 SDValue Mask = N->getOperand(Num: 2);
1617 SDValue EVL = N->getOperand(Num: 3);
1618 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1619 N3: Mask, N4: EVL);
1620}
1621
1622SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1623 SDValue RHS = N->getOperand(Num: 1);
1624 // The input value must be properly zero extended.
1625 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1626 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1627 RHS = ZExtPromotedInteger(Op: RHS);
1628 if (N->getOpcode() != ISD::VP_SRL)
1629 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1630
1631 SDValue Mask = N->getOperand(Num: 2);
1632 SDValue EVL = N->getOperand(Num: 3);
1633 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1634 N3: Mask, N4: EVL);
1635}
1636
1637SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1638 EVT OldVT = N->getValueType(ResNo: 0);
1639 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1640 SDValue Amt = N->getOperand(Num: 1);
1641 unsigned Opcode = N->getOpcode();
1642 unsigned OldBits = OldVT.getScalarSizeInBits();
1643 unsigned NewBits = VT.getScalarSizeInBits();
1644
1645 // If the promoted type is twice the size (or more), then we can concatenate
1646 // the value with itself and treat this similar to a funnel shift. This isn't
1647 // necessary if the rotate amount is constant or if shl/srl of the original
1648 // type are custom lowered.
1649 // rotl(x,amt) -> (((aext(x) << bw) | zext(x)) << (amt % bw)) >> bw.
1650 // rotr(x,amt) -> (((aext(x) << bw) | zext(x)) >> (amt % bw)).
1651 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1652 !TLI.isOperationLegalOrCustom(Op: Opcode, VT) &&
1653 TLI.getOperationAction(Op: ISD::SHL, VT: OldVT) != TargetLowering::Custom &&
1654 TLI.getOperationAction(Op: ISD::SRL, VT: OldVT) != TargetLowering::Custom) {
1655 SDValue Op0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
1656 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1657 Amt = ZExtPromotedInteger(Op: Amt);
1658 EVT AmtVT = Amt.getValueType();
1659
1660 SDLoc DL(N);
1661 // Amount has to be interpreted modulo the old bit width.
1662 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1663 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1664 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1665 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Op0, N2: HiShift);
1666 SDValue Lo = DAG.getZeroExtendInReg(Op: Op0, DL, VT: OldVT);
1667 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1668 bool IsROTR = N->getOpcode() == ISD::ROTR;
1669 Res = DAG.getNode(Opcode: IsROTR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1670 // FIXME: We can avoid this by using ROTL when the promoted type is exactly
1671 // twice the size.
1672 if (!IsROTR)
1673 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1674 return Res;
1675 }
1676
1677 // Lower the rotate to shifts and ORs which can be promoted.
1678 SDValue Res = TLI.expandROT(N, AllowVectorOps: true /*AllowVectorOps*/, DAG);
1679 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1680 return SDValue();
1681}
1682
1683SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1684 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1685 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1686 SDValue Amt = N->getOperand(Num: 2);
1687 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1688 Amt = ZExtPromotedInteger(Op: Amt);
1689 EVT AmtVT = Amt.getValueType();
1690
1691 SDLoc DL(N);
1692 EVT OldVT = N->getOperand(Num: 0).getValueType();
1693 EVT VT = Lo.getValueType();
1694 unsigned Opcode = N->getOpcode();
1695 bool IsFSHR = Opcode == ISD::FSHR;
1696 unsigned OldBits = OldVT.getScalarSizeInBits();
1697 unsigned NewBits = VT.getScalarSizeInBits();
1698
1699 // Amount has to be interpreted modulo the old bit width.
1700 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1701 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1702
1703 // If the promoted type is twice the size (or more), then we use the
1704 // traditional funnel 'double' shift codegen. This isn't necessary if the
1705 // shift amount is constant.
1706 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1707 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1708 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1709 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1710 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1711 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: HiShift);
1712 Lo = DAG.getZeroExtendInReg(Op: Lo, DL, VT: OldVT);
1713 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1714 Res = DAG.getNode(Opcode: IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1715 if (!IsFSHR)
1716 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1717 return Res;
1718 }
1719
1720 // Shift Lo up to occupy the upper bits of the promoted type.
1721 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Lo,
1722 N2: DAG.getShiftAmountConstant(Val: NewBits - OldBits, VT, DL));
1723
1724 // Increase Amount to shift the result into the lower bits of the promoted
1725 // type.
1726 if (IsFSHR)
1727 Amt = DAG.getNode(Opcode: ISD::ADD, DL, VT: AmtVT, N1: Amt,
1728 N2: DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT));
1729
1730 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt);
1731}
1732
1733// A vp version of PromoteIntRes_FunnelShift.
1734SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
1735 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1736 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1737 SDValue Amt = N->getOperand(Num: 2);
1738 SDValue Mask = N->getOperand(Num: 3);
1739 SDValue EVL = N->getOperand(Num: 4);
1740 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1741 Amt = ZExtPromotedInteger(Op: Amt);
1742 EVT AmtVT = Amt.getValueType();
1743
1744 SDLoc DL(N);
1745 EVT OldVT = N->getOperand(Num: 0).getValueType();
1746 EVT VT = Lo.getValueType();
1747 unsigned Opcode = N->getOpcode();
1748 bool IsFSHR = Opcode == ISD::VP_FSHR;
1749 unsigned OldBits = OldVT.getScalarSizeInBits();
1750 unsigned NewBits = VT.getScalarSizeInBits();
1751
1752 // Amount has to be interpreted modulo the old bit width.
1753 Amt = DAG.getNode(Opcode: ISD::VP_UREM, DL, VT: AmtVT, N1: Amt,
1754 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT), N3: Mask, N4: EVL);
1755
1756 // If the promoted type is twice the size (or more), then we use the
1757 // traditional funnel 'double' shift codegen. This isn't necessary if the
1758 // shift amount is constant.
1759 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1760 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1761 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1762 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1763 SDValue HiShift = DAG.getConstant(Val: OldBits, DL, VT);
1764 Hi = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Hi, N2: HiShift, N3: Mask, N4: EVL);
1765 Lo = DAG.getVPZeroExtendInReg(Op: Lo, Mask, EVL, DL, VT: OldVT);
1766 SDValue Res = DAG.getNode(Opcode: ISD::VP_OR, DL, VT, N1: Hi, N2: Lo, N3: Mask, N4: EVL);
1767 Res = DAG.getNode(Opcode: IsFSHR ? ISD::VP_SRL : ISD::VP_SHL, DL, VT, N1: Res, N2: Amt,
1768 N3: Mask, N4: EVL);
1769 if (!IsFSHR)
1770 Res = DAG.getNode(Opcode: ISD::VP_SRL, DL, VT, N1: Res, N2: HiShift, N3: Mask, N4: EVL);
1771 return Res;
1772 }
1773
1774 // Shift Lo up to occupy the upper bits of the promoted type.
1775 SDValue ShiftOffset = DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT);
1776 Lo = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Lo, N2: ShiftOffset, N3: Mask, N4: EVL);
1777
1778 // Increase Amount to shift the result into the lower bits of the promoted
1779 // type.
1780 if (IsFSHR)
1781 Amt = DAG.getNode(Opcode: ISD::VP_ADD, DL, VT: AmtVT, N1: Amt, N2: ShiftOffset, N3: Mask, N4: EVL);
1782
1783 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt, N4: Mask, N5: EVL);
1784}
1785
1786SDValue DAGTypeLegalizer::PromoteIntRes_CLMUL(SDNode *N) {
1787 unsigned Opcode = N->getOpcode();
1788
1789 SDLoc DL(N);
1790 EVT OldVT = N->getOperand(Num: 0).getValueType();
1791 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1792
1793 if (Opcode == ISD::CLMUL) {
1794 // Avoid the generic expansion if the cross-product expansion in
1795 // ExpandIntRes_CLMUL would produce a better result.
1796 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CLMUL, VT) &&
1797 !(getTypeAction(VT) == TargetLowering::TypeExpandInteger &&
1798 TLI.isOperationLegalOrCustom(
1799 Op: ISD::CLMUL, VT: TLI.getRegisterType(Context&: *DAG.getContext(), VT)))) {
1800 if (SDValue Res = TLI.expandCLMUL(N, DAG))
1801 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1802 }
1803 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1804 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1805 return DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1806 }
1807
1808 SDValue X = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1809 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1810
1811 unsigned OldBits = OldVT.getScalarSizeInBits();
1812 unsigned NewBits = VT.getScalarSizeInBits();
1813 if (NewBits < 2 * OldBits) {
1814 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1815 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1816 SDValue Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1817 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1818 SDValue Clmulh = DAG.getNode(Opcode: ISD::CLMULH, DL, VT, N1: X, N2: Y);
1819 ShAmt = Opcode == ISD::CLMULH ? NewBits - OldBits : NewBits - OldBits + 1;
1820 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Clmulh,
1821 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1822 return DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Lo, N2: Hi);
1823 }
1824
1825 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1826 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1827 return DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1828 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1829}
1830
1831SDValue DAGTypeLegalizer::PromoteIntRes_PEXT(SDNode *N) {
1832 SDLoc DL(N);
1833 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1834 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::PEXT, VT)) {
1835 if (SDValue Res = TLI.expandPEXT(N, DAG))
1836 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1837 }
1838 // Only the mask operand needs zero-extension because the implicit AND from
1839 // masking clears the corresponding bits in X anyway.
1840 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1841 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1842 return DAG.getNode(Opcode: ISD::PEXT, DL, VT, N1: X, N2: Y);
1843}
1844
1845SDValue DAGTypeLegalizer::PromoteIntRes_PDEP(SDNode *N) {
1846 SDLoc DL(N);
1847 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1848 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::PDEP, VT)) {
1849 if (SDValue Res = TLI.expandPDEP(N, DAG))
1850 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1851 }
1852 // Neither operand needs zero-extension because the upper operand bits could
1853 // only result in depositing result bits that will be discarded.
1854 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1855 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1856 return DAG.getNode(Opcode: ISD::PDEP, DL, VT, N1: X, N2: Y);
1857}
1858
1859SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1860 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1861 SDValue Res;
1862 SDValue InOp = N->getOperand(Num: 0);
1863 SDLoc dl(N);
1864
1865 switch (getTypeAction(VT: InOp.getValueType())) {
1866 default: llvm_unreachable("Unknown type action!");
1867 case TargetLowering::TypeLegal:
1868 case TargetLowering::TypeExpandInteger:
1869 Res = InOp;
1870 break;
1871 case TargetLowering::TypePromoteInteger:
1872 Res = GetPromotedInteger(Op: InOp);
1873 break;
1874 case TargetLowering::TypeSplitVector: {
1875 EVT InVT = InOp.getValueType();
1876 assert(InVT.isVector() && "Cannot split scalar types");
1877 ElementCount NumElts = InVT.getVectorElementCount();
1878 assert(NumElts == NVT.getVectorElementCount() &&
1879 "Dst and Src must have the same number of elements");
1880 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1881 "Promoted vector type must be a power of two");
1882
1883 SDValue EOp1, EOp2;
1884 GetSplitVector(Op: InOp, Lo&: EOp1, Hi&: EOp2);
1885
1886 EVT HalfNVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getScalarType(),
1887 EC: NumElts.divideCoefficientBy(RHS: 2));
1888 if (N->getOpcode() == ISD::TRUNCATE) {
1889 EOp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp1);
1890 EOp2 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp2);
1891 } else {
1892 assert(N->getOpcode() == ISD::VP_TRUNCATE &&
1893 "Expected VP_TRUNCATE opcode");
1894 SDValue MaskLo, MaskHi, EVLLo, EVLHi;
1895 std::tie(args&: MaskLo, args&: MaskHi) = SplitMask(Mask: N->getOperand(Num: 1));
1896 std::tie(args&: EVLLo, args&: EVLHi) =
1897 DAG.SplitEVL(N: N->getOperand(Num: 2), VecVT: N->getValueType(ResNo: 0), DL: dl);
1898 EOp1 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp1, N2: MaskLo, N3: EVLLo);
1899 EOp2 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp2, N2: MaskHi, N3: EVLHi);
1900 }
1901 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl, VT: NVT, N1: EOp1, N2: EOp2);
1902 }
1903 // TODO: VP_TRUNCATE need to handle when TypeWidenVector access to some
1904 // targets.
1905 case TargetLowering::TypeWidenVector: {
1906 SDValue WideInOp = GetWidenedVector(Op: InOp);
1907
1908 // Truncate widened InOp.
1909 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1910 EVT TruncVT = EVT::getVectorVT(Context&: *DAG.getContext(),
1911 VT: N->getValueType(ResNo: 0).getScalarType(), NumElements: NumElem);
1912 SDValue WideTrunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: TruncVT, Operand: WideInOp);
1913
1914 // Zero extend so that the elements are of same type as those of NVT
1915 EVT ExtVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getVectorElementType(),
1916 NumElements: NumElem);
1917 SDValue WideExt = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: ExtVT, Operand: WideTrunc);
1918
1919 // Extract the low NVT subvector.
1920 SDValue ZeroIdx = DAG.getVectorIdxConstant(Val: 0, DL: dl);
1921 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NVT, N1: WideExt, N2: ZeroIdx);
1922 }
1923 }
1924
1925 // Truncate to NVT instead of VT
1926 if (N->getOpcode() == ISD::VP_TRUNCATE)
1927 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: NVT, N1: Res, N2: N->getOperand(Num: 1),
1928 N3: N->getOperand(Num: 2));
1929 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Res);
1930}
1931
1932SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1933 if (ResNo == 1)
1934 return PromoteIntRes_Overflow(N);
1935
1936 // The operation overflowed iff the result in the larger type is not the
1937 // zero extension of its truncation to the original type.
1938 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1939 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1940 EVT OVT = N->getOperand(Num: 0).getValueType();
1941 EVT NVT = LHS.getValueType();
1942 SDLoc dl(N);
1943
1944 // Do the arithmetic in the larger type.
1945 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1946 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1947
1948 // Calculate the overflow flag: zero extend the arithmetic result from
1949 // the original type.
1950 SDValue Ofl = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: OVT);
1951 // Overflowed if and only if this is not equal to Res.
1952 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1953
1954 // Use the calculated overflow everywhere.
1955 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1956
1957 return Res;
1958}
1959
1960// Handle promotion for the ADDE/SUBE/UADDO_CARRY/USUBO_CARRY nodes. Notice that
1961// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1962// the UADDO_CARRY/USUBO_CARRY nodes in that the third operand is carry Boolean.
1963SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO_CARRY(SDNode *N,
1964 unsigned ResNo) {
1965 if (ResNo == 1)
1966 return PromoteIntRes_Overflow(N);
1967
1968 // We need to sign-extend the operands so the carry value computed by the
1969 // wide operation will be equivalent to the carry value computed by the
1970 // narrow operation.
1971 // An UADDO_CARRY can generate carry only if any of the operands has its
1972 // most significant bit set. Sign extension propagates the most significant
1973 // bit into the higher bits which means the extra bit that the narrow
1974 // addition would need (i.e. the carry) will be propagated through the higher
1975 // bits of the wide addition.
1976 // A USUBO_CARRY can generate borrow only if LHS < RHS and this property will
1977 // be preserved by sign extension.
1978 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1979 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1980
1981 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(ResNo: 1)};
1982
1983 // Do the arithmetic in the wide type.
1984 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VTList: DAG.getVTList(VTs: ValueVTs),
1985 N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
1986
1987 // Update the users of the original carry/borrow value.
1988 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1989
1990 return SDValue(Res.getNode(), 0);
1991}
1992
1993SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1994 unsigned ResNo) {
1995 assert(ResNo == 1 && "Don't know how to promote other results yet.");
1996 return PromoteIntRes_Overflow(N);
1997}
1998
1999SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
2000 EVT OVT = N->getValueType(ResNo: 0);
2001 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
2002
2003 // If a larger ABS or SMAX isn't supported by the target, try to expand now.
2004 // If we expand later we'll end up sign extending more than just the sra input
2005 // in sra+xor+sub expansion.
2006 if (!OVT.isVector() &&
2007 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS, VT: NVT) &&
2008 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS_MIN_POISON, VT: NVT) &&
2009 !TLI.isOperationLegal(Op: ISD::SMAX, VT: NVT)) {
2010 if (SDValue Res = TLI.expandABS(N, DAG))
2011 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Res);
2012 }
2013
2014 SDValue Op0 = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2015 return DAG.getNode(Opcode: ISD::ABS_MIN_POISON, DL: SDLoc(N), VT: Op0.getValueType(), Operand: Op0);
2016}
2017
2018SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
2019 // Promote the overflow bit trivially.
2020 if (ResNo == 1)
2021 return PromoteIntRes_Overflow(N);
2022
2023 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
2024 SDLoc DL(N);
2025 EVT SmallVT = LHS.getValueType();
2026
2027 // To determine if the result overflowed in a larger type, we extend the
2028 // input to the larger type, do the multiply (checking if it overflows),
2029 // then also check the high bits of the result to see if overflow happened
2030 // there.
2031 if (N->getOpcode() == ISD::SMULO) {
2032 LHS = SExtPromotedInteger(Op: LHS);
2033 RHS = SExtPromotedInteger(Op: RHS);
2034 } else {
2035 LHS = ZExtPromotedInteger(Op: LHS);
2036 RHS = ZExtPromotedInteger(Op: RHS);
2037 }
2038 SDVTList VTs = DAG.getVTList(VT1: LHS.getValueType(), VT2: N->getValueType(ResNo: 1));
2039 SDValue Mul = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N1: LHS, N2: RHS);
2040
2041 // Overflow occurred if it occurred in the larger type, or if the high part
2042 // of the result does not zero/sign-extend the low part. Check this second
2043 // possibility first.
2044 SDValue Overflow;
2045 if (N->getOpcode() == ISD::UMULO) {
2046 // Unsigned overflow occurred if the high part is non-zero.
2047 unsigned Shift = SmallVT.getScalarSizeInBits();
2048 SDValue Hi =
2049 DAG.getNode(Opcode: ISD::SRL, DL, VT: Mul.getValueType(), N1: Mul,
2050 N2: DAG.getShiftAmountConstant(Val: Shift, VT: Mul.getValueType(), DL));
2051 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: Hi,
2052 RHS: DAG.getConstant(Val: 0, DL, VT: Hi.getValueType()),
2053 Cond: ISD::SETNE);
2054 } else {
2055 // Signed overflow occurred if the high part does not sign extend the low.
2056 SDValue SExt = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: Mul.getValueType(),
2057 N1: Mul, N2: DAG.getValueType(SmallVT));
2058 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: SExt, RHS: Mul, Cond: ISD::SETNE);
2059 }
2060
2061 // The only other way for overflow to occur is if the multiplication in the
2062 // larger type itself overflowed.
2063 Overflow = DAG.getNode(Opcode: ISD::OR, DL, VT: N->getValueType(ResNo: 1), N1: Overflow,
2064 N2: SDValue(Mul.getNode(), 1));
2065
2066 // Use the calculated overflow everywhere.
2067 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
2068 return Mul;
2069}
2070
2071SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
2072 return DAG.getUNDEF(VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
2073 VT: N->getValueType(ResNo: 0)));
2074}
2075
2076SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
2077 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
2078
2079 const APInt &MulImm = N->getConstantOperandAPInt(Num: 0);
2080 return DAG.getVScale(DL: SDLoc(N), VT, MulImm: MulImm.sext(width: VT.getSizeInBits()));
2081}
2082
2083SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
2084 SDValue Chain = N->getOperand(Num: 0); // Get the chain.
2085 SDValue Ptr = N->getOperand(Num: 1); // Get the pointer.
2086 EVT VT = N->getValueType(ResNo: 0);
2087 SDLoc dl(N);
2088
2089 MVT RegVT = TLI.getRegisterType(Context&: *DAG.getContext(), VT);
2090 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
2091 // The argument is passed as NumRegs registers of type RegVT.
2092
2093 SmallVector<SDValue, 8> Parts(NumRegs);
2094 for (unsigned i = 0; i < NumRegs; ++i) {
2095 Parts[i] = DAG.getVAArg(VT: RegVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2),
2096 Align: N->getConstantOperandVal(Num: 3));
2097 Chain = Parts[i].getValue(R: 1);
2098 }
2099
2100 // Handle endianness of the load.
2101 if (DAG.getDataLayout().isBigEndian())
2102 std::reverse(first: Parts.begin(), last: Parts.end());
2103
2104 // Assemble the parts in the promoted type.
2105 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
2106 SDValue Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[0]);
2107 for (unsigned i = 1; i < NumRegs; ++i) {
2108 SDValue Part = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[i]);
2109 // Shift it to the right position and "or" it in.
2110 Part = DAG.getNode(
2111 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Part,
2112 N2: DAG.getShiftAmountConstant(Val: i * RegVT.getSizeInBits(), VT: NVT, DL: dl));
2113 Res = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Res, N2: Part);
2114 }
2115
2116 // Modified the chain result - switch anything that used the old chain to
2117 // use the new one.
2118 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
2119
2120 return Res;
2121}
2122
2123//===----------------------------------------------------------------------===//
2124// Integer Operand Promotion
2125//===----------------------------------------------------------------------===//
2126
2127/// PromoteIntegerOperand - This method is called when the specified operand of
2128/// the specified node is found to need promotion. At this point, all of the
2129/// result types of the node are known to be legal, but other operands of the
2130/// node may need promotion or expansion as well as the specified one.
2131bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
2132 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG));
2133 SDValue Res = SDValue();
2134 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false)) {
2135 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
2136 return false;
2137 }
2138
2139 switch (N->getOpcode()) {
2140 default:
2141 #ifndef NDEBUG
2142 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
2143 N->dump(&DAG); dbgs() << "\n";
2144 #endif
2145 report_fatal_error(reason: "Do not know how to promote this operator's operand!");
2146
2147 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
2148 case ISD::ANY_EXTEND_VECTOR_INREG:
2149 Res = PromoteIntOp_ANY_EXTEND_VECTOR_INREG(N);
2150 break;
2151 case ISD::ATOMIC_STORE:
2152 Res = PromoteIntOp_ATOMIC_STORE(N: cast<AtomicSDNode>(Val: N));
2153 break;
2154 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
2155 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
2156 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
2157 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
2158 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
2159 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
2160 case ISD::COND_LOOP:
2161 Res = PromoteIntOp_COND_LOOP(N, OpNo);
2162 break;
2163 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
2164 case ISD::FAKE_USE:
2165 Res = PromoteIntOp_FAKE_USE(N);
2166 break;
2167 case ISD::INSERT_VECTOR_ELT:
2168 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
2169 break;
2170 case ISD::SPLAT_VECTOR:
2171 case ISD::SCALAR_TO_VECTOR:
2172 Res = PromoteIntOp_ScalarOp(N);
2173 break;
2174 case ISD::VSELECT:
2175 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
2176 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
2177 case ISD::VP_SETCC:
2178 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
2179 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
2180 case ISD::VP_SIGN_EXTEND: Res = PromoteIntOp_VP_SIGN_EXTEND(N); break;
2181 case ISD::VP_SINT_TO_FP:
2182 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
2183 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
2184 case ISD::STORE: Res = PromoteIntOp_STORE(N: cast<StoreSDNode>(Val: N),
2185 OpNo); break;
2186 case ISD::VP_STORE:
2187 Res = PromoteIntOp_VP_STORE(N: cast<VPStoreSDNode>(Val: N), OpNo);
2188 break;
2189 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(N: cast<MaskedStoreSDNode>(Val: N),
2190 OpNo); break;
2191 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(N: cast<MaskedLoadSDNode>(Val: N),
2192 OpNo); break;
2193 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(N: cast<MaskedGatherSDNode>(Val: N),
2194 OpNo); break;
2195 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(N: cast<MaskedScatterSDNode>(Val: N),
2196 OpNo); break;
2197 case ISD::VECTOR_COMPRESS:
2198 Res = PromoteIntOp_VECTOR_COMPRESS(N, OpNo);
2199 break;
2200 case ISD::VP_TRUNCATE:
2201 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
2202 case ISD::BF16_TO_FP:
2203 case ISD::FP16_TO_FP:
2204 case ISD::VP_UINT_TO_FP:
2205 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
2206 case ISD::CONVERT_FROM_ARBITRARY_FP:
2207 Res = PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(N);
2208 break;
2209 case ISD::STRICT_FP16_TO_FP:
2210 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
2211 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
2212 case ISD::VP_ZERO_EXTEND: Res = PromoteIntOp_VP_ZERO_EXTEND(N); break;
2213 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
2214 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
2215
2216 case ISD::SHL:
2217 case ISD::SRA:
2218 case ISD::SRL:
2219 case ISD::ROTL:
2220 case ISD::ROTR:
2221 case ISD::SSHLSAT:
2222 case ISD::USHLSAT:
2223 Res = PromoteIntOp_Shift(N);
2224 break;
2225
2226 case ISD::SCMP:
2227 case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
2228
2229 case ISD::FSHL:
2230 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
2231
2232 case ISD::FRAMEADDR:
2233 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
2234
2235 case ISD::SMULFIX:
2236 case ISD::SMULFIXSAT:
2237 case ISD::UMULFIX:
2238 case ISD::UMULFIXSAT:
2239 case ISD::SDIVFIX:
2240 case ISD::SDIVFIXSAT:
2241 case ISD::UDIVFIX:
2242 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
2243 case ISD::FPOWI:
2244 case ISD::STRICT_FPOWI:
2245 case ISD::FLDEXP:
2246 case ISD::STRICT_FLDEXP: Res = PromoteIntOp_ExpOp(N); break;
2247 case ISD::VECREDUCE_ADD:
2248 case ISD::VECREDUCE_MUL:
2249 case ISD::VECREDUCE_AND:
2250 case ISD::VECREDUCE_OR:
2251 case ISD::VECREDUCE_XOR:
2252 case ISD::VECREDUCE_SMAX:
2253 case ISD::VECREDUCE_SMIN:
2254 case ISD::VECREDUCE_UMAX:
2255 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
2256 case ISD::VP_REDUCE_ADD:
2257 case ISD::VP_REDUCE_MUL:
2258 case ISD::VP_REDUCE_AND:
2259 case ISD::VP_REDUCE_OR:
2260 case ISD::VP_REDUCE_XOR:
2261 case ISD::VP_REDUCE_SMAX:
2262 case ISD::VP_REDUCE_SMIN:
2263 case ISD::VP_REDUCE_UMAX:
2264 case ISD::VP_REDUCE_UMIN:
2265 Res = PromoteIntOp_VP_REDUCE(N, OpNo);
2266 break;
2267
2268 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
2269 case ISD::STACKMAP:
2270 Res = PromoteIntOp_STACKMAP(N, OpNo);
2271 break;
2272 case ISD::PATCHPOINT:
2273 Res = PromoteIntOp_PATCHPOINT(N, OpNo);
2274 break;
2275 case ISD::WRITE_REGISTER:
2276 Res = PromoteIntOp_WRITE_REGISTER(N, OpNo);
2277 break;
2278 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
2279 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
2280 Res = PromoteIntOp_VP_STRIDED(N, OpNo);
2281 break;
2282 case ISD::EXPERIMENTAL_VP_SPLICE:
2283 Res = PromoteIntOp_VP_SPLICE(N, OpNo);
2284 break;
2285 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
2286 Res = PromoteIntOp_VECTOR_HISTOGRAM(N, OpNo);
2287 break;
2288 case ISD::VECTOR_FIND_LAST_ACTIVE:
2289 case ISD::CTTZ_ELTS:
2290 case ISD::CTTZ_ELTS_ZERO_POISON:
2291 Res = PromoteIntOp_UnaryBooleanVectorOp(N, OpNo);
2292 break;
2293 case ISD::GET_ACTIVE_LANE_MASK:
2294 Res = PromoteIntOp_GET_ACTIVE_LANE_MASK(N);
2295 break;
2296 case ISD::MASKED_UDIV:
2297 case ISD::MASKED_SDIV:
2298 case ISD::MASKED_UREM:
2299 case ISD::MASKED_SREM:
2300 Res = PromoteIntOp_MaskedBinOp(N, OpNo);
2301 break;
2302 case ISD::PARTIAL_REDUCE_UMLA:
2303 case ISD::PARTIAL_REDUCE_SMLA:
2304 case ISD::PARTIAL_REDUCE_SUMLA:
2305 Res = PromoteIntOp_PARTIAL_REDUCE_MLA(N);
2306 break;
2307 case ISD::LOOP_DEPENDENCE_RAW_MASK:
2308 case ISD::LOOP_DEPENDENCE_WAR_MASK:
2309 Res = PromoteIntOp_LOOP_DEPENDENCE_MASK(N);
2310 break;
2311 }
2312
2313 // If the result is null, the sub-method took care of registering results etc.
2314 if (!Res.getNode()) return false;
2315
2316 // If the result is N, the sub-method updated N in place. Tell the legalizer
2317 // core about this.
2318 if (Res.getNode() == N)
2319 return true;
2320
2321 const bool IsStrictFp = N->isStrictFPOpcode();
2322 assert(Res.getValueType() == N->getValueType(0) &&
2323 N->getNumValues() == (IsStrictFp ? 2 : 1) &&
2324 "Invalid operand expansion");
2325 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
2326 Res.dump());
2327
2328 ReplaceValueWith(From: SDValue(N, 0), To: Res);
2329 if (IsStrictFp)
2330 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res.getNode(), 1));
2331
2332 return false;
2333}
2334
2335// These operands can be either sign extended or zero extended as long as we
2336// treat them the same. If an extension is free, choose that. Otherwise, follow
2337// target preference.
2338void DAGTypeLegalizer::SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS) {
2339 SDValue OpL = GetPromotedInteger(Op: LHS);
2340 SDValue OpR = GetPromotedInteger(Op: RHS);
2341
2342 if (TLI.isSExtCheaperThanZExt(FromTy: LHS.getValueType(), ToTy: OpL.getValueType())) {
2343 // The target would prefer to promote the comparison operand with sign
2344 // extension. Honor that unless the promoted values are already zero
2345 // extended.
2346 unsigned OpLEffectiveBits =
2347 DAG.computeKnownBits(Op: OpL).countMaxActiveBits();
2348 unsigned OpREffectiveBits =
2349 DAG.computeKnownBits(Op: OpR).countMaxActiveBits();
2350 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2351 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2352 LHS = OpL;
2353 RHS = OpR;
2354 return;
2355 }
2356
2357 // The promoted values aren't zero extended, use a sext_inreg.
2358 LHS = SExtPromotedInteger(Op: LHS);
2359 RHS = SExtPromotedInteger(Op: RHS);
2360 return;
2361 }
2362
2363 // Prefer to promote the comparison operand with zero extension.
2364
2365 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
2366 // than the width of LHS/RHS, we can avoid inserting a zext_inreg operation
2367 // that we might not be able to remove.
2368 unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpL);
2369 unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpR);
2370 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2371 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2372 LHS = OpL;
2373 RHS = OpR;
2374 return;
2375 }
2376
2377 // Otherwise, use zext_inreg.
2378 LHS = ZExtPromotedInteger(Op: LHS);
2379 RHS = ZExtPromotedInteger(Op: RHS);
2380}
2381
2382/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
2383/// shared among BR_CC, SELECT_CC, and SETCC handlers.
2384void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
2385 ISD::CondCode CCCode) {
2386 // We have to insert explicit sign or zero extends. Note that we could
2387 // insert sign extends for ALL conditions. For those operations where either
2388 // zero or sign extension would be valid, we ask the target which extension
2389 // it would prefer.
2390
2391 // Signed comparisons always require sign extension.
2392 if (ISD::isSignedIntSetCC(Code: CCCode)) {
2393 LHS = SExtPromotedInteger(Op: LHS);
2394 RHS = SExtPromotedInteger(Op: RHS);
2395 return;
2396 }
2397
2398 assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
2399 "Unknown integer comparison!");
2400
2401 SExtOrZExtPromotedOperands(LHS, RHS);
2402}
2403
2404SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
2405 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2406 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2407}
2408
2409SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND_VECTOR_INREG(SDNode *N) {
2410 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2411 EVT ResVT = N->getValueType(ResNo: 0);
2412 EVT OpVT = Op.getValueType();
2413 EVT NewVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: OpVT.getScalarType(),
2414 NumElements: ResVT.getVectorNumElements());
2415 Op = DAG.getExtractSubvector(DL: SDLoc(Op), VT: NewVT, Vec: Op, Idx: 0);
2416 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: ResVT, Operand: Op);
2417}
2418
2419SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
2420 SDValue Op1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
2421 return DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(),
2422 Chain: N->getChain(), Ptr: Op1, Val: N->getBasePtr(), MMO: N->getMemOperand());
2423}
2424
2425SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
2426 EVT OutVT = N->getValueType(ResNo: 0);
2427 SDValue InOp = N->getOperand(Num: 0);
2428 EVT InVT = InOp.getValueType();
2429 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
2430 SDLoc dl(N);
2431
2432 switch (getTypeAction(VT: InVT)) {
2433 case TargetLowering::TypePromoteInteger: {
2434 // TODO: Handle big endian & vector input type.
2435 if (OutVT.isVector() && !InVT.isVector() &&
2436 DAG.getDataLayout().isLittleEndian()) {
2437 EVT EltVT = OutVT.getVectorElementType();
2438 TypeSize EltSize = EltVT.getSizeInBits();
2439 TypeSize NInSize = NInVT.getSizeInBits();
2440
2441 if (NInSize.hasKnownScalarFactor(RHS: EltSize)) {
2442 unsigned NumEltsWithPadding = NInSize.getKnownScalarFactor(RHS: EltSize);
2443 EVT WideVecVT =
2444 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
2445
2446 if (isTypeLegal(VT: WideVecVT)) {
2447 SDValue Promoted = GetPromotedInteger(Op: InOp);
2448 SDValue Cast = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: WideVecVT, Operand: Promoted);
2449 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Cast,
2450 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
2451 }
2452 }
2453 }
2454
2455 break;
2456 }
2457 default:
2458 break;
2459 }
2460
2461 // This should only occur in unusual situations like bitcasting to an
2462 // x86_fp80, so just turn it into a store+load
2463 return CreateStackStoreLoad(Op: InOp, DestVT: OutVT);
2464}
2465
2466SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
2467 assert(OpNo == 2 && "Don't know how to promote this operand!");
2468
2469 SDValue LHS = N->getOperand(Num: 2);
2470 SDValue RHS = N->getOperand(Num: 3);
2471 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get());
2472
2473 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
2474 // legal types.
2475 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2476 Op2: N->getOperand(Num: 1), Op3: LHS, Op4: RHS, Op5: N->getOperand(Num: 4)),
2477 0);
2478}
2479
2480SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
2481 assert(OpNo == 1 && "only know how to promote condition");
2482
2483 // Promote all the way up to the canonical SetCC type.
2484 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2485
2486 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
2487 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond,
2488 Op3: N->getOperand(Num: 2)), 0);
2489}
2490
2491SDValue DAGTypeLegalizer::PromoteIntOp_COND_LOOP(SDNode *N, unsigned OpNo) {
2492 assert(OpNo == 1 && "only know how to promote condition");
2493
2494 // Promote all the way up to the canonical SetCC type.
2495 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2496
2497 // The chain (Op#0) is always a legal type.
2498 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond), 0);
2499}
2500
2501SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
2502 // Since the result type is legal, the operands must promote to it.
2503 EVT OVT = N->getOperand(Num: 0).getValueType();
2504 SDValue Lo = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2505 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 1));
2506 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
2507 SDLoc dl(N);
2508
2509 Hi = DAG.getNode(
2510 Opcode: ISD::SHL, DL: dl, VT: N->getValueType(ResNo: 0), N1: Hi,
2511 N2: DAG.getShiftAmountConstant(Val: OVT.getSizeInBits(), VT: N->getValueType(ResNo: 0), DL: dl));
2512 return DAG.getNode(Opcode: ISD::OR, DL: dl, VT: N->getValueType(ResNo: 0), N1: Lo, N2: Hi);
2513}
2514
2515SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
2516 // The vector type is legal but the element type is not. This implies
2517 // that the vector is a power-of-two in length and that the element
2518 // type does not have a strange size (eg: it is not i1).
2519 EVT VecVT = N->getValueType(ResNo: 0);
2520 unsigned NumElts = VecVT.getVectorNumElements();
2521 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
2522 "Legal vector of one illegal element?");
2523
2524 // Promote the inserted value. The type does not need to match the
2525 // vector element type. Check that any extra bits introduced will be
2526 // truncated away.
2527 assert(N->getOperand(0).getValueSizeInBits() >=
2528 N->getValueType(0).getScalarSizeInBits() &&
2529 "Type of inserted value narrower than vector element type!");
2530
2531 SmallVector<SDValue, 16> NewOps;
2532 for (unsigned i = 0; i < NumElts; ++i)
2533 NewOps.push_back(Elt: GetPromotedInteger(Op: N->getOperand(Num: i)));
2534
2535 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2536}
2537
2538SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
2539 unsigned OpNo) {
2540 if (OpNo == 1) {
2541 // Promote the inserted value. This is valid because the type does not
2542 // have to match the vector element type.
2543
2544 // Check that any extra bits introduced will be truncated away.
2545 assert(N->getOperand(1).getValueSizeInBits() >=
2546 N->getValueType(0).getScalarSizeInBits() &&
2547 "Type of inserted value narrower than vector element type!");
2548 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2549 Op2: GetPromotedInteger(Op: N->getOperand(Num: 1)),
2550 Op3: N->getOperand(Num: 2)),
2551 0);
2552 }
2553
2554 assert(OpNo == 2 && "Different operand and result vector types?");
2555
2556 // Promote the index.
2557 SDValue Idx = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 2), DL: SDLoc(N),
2558 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
2559 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2560 Op2: N->getOperand(Num: 1), Op3: Idx), 0);
2561}
2562
2563SDValue DAGTypeLegalizer::PromoteIntOp_ScalarOp(SDNode *N) {
2564 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2565
2566 // Integer SPLAT_VECTOR/SCALAR_TO_VECTOR operands are implicitly truncated,
2567 // so just promote the operand in place.
2568 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2569}
2570
2571SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
2572 assert(OpNo == 0 && "Only know how to promote the condition!");
2573 SDValue Cond = N->getOperand(Num: 0);
2574 EVT OpTy = N->getOperand(Num: 1).getValueType();
2575
2576 if (N->getOpcode() == ISD::VSELECT)
2577 if (SDValue Res = WidenVSELECTMask(N))
2578 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
2579 N1: Res, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2580
2581 // Promote all the way up to the canonical SetCC type.
2582 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
2583 Cond = PromoteTargetBoolean(Bool: Cond, ValVT: OpVT);
2584
2585 return SDValue(DAG.UpdateNodeOperands(N, Op1: Cond, Op2: N->getOperand(Num: 1),
2586 Op3: N->getOperand(Num: 2)), 0);
2587}
2588
2589SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
2590 assert(OpNo == 0 && "Don't know how to promote this operand!");
2591
2592 SDValue LHS = N->getOperand(Num: 0);
2593 SDValue RHS = N->getOperand(Num: 1);
2594 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get());
2595
2596 // The CC (#4) and the possible return values (#2 and #3) have legal types.
2597 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2598 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)), 0);
2599}
2600
2601SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
2602 assert(OpNo == 0 && "Don't know how to promote this operand!");
2603
2604 SDValue LHS = N->getOperand(Num: 0);
2605 SDValue RHS = N->getOperand(Num: 1);
2606 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get());
2607
2608 // The CC (#2) is always legal.
2609 if (N->getOpcode() == ISD::SETCC)
2610 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2)), 0);
2611
2612 assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
2613
2614 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2615 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)),
2616 0);
2617}
2618
2619SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
2620 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2621 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2622}
2623
2624SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
2625 SDValue LHS = N->getOperand(Num: 0);
2626 SDValue RHS = N->getOperand(Num: 1);
2627
2628 if (N->getOpcode() == ISD::SCMP) {
2629 LHS = SExtPromotedInteger(Op: LHS);
2630 RHS = SExtPromotedInteger(Op: RHS);
2631 } else {
2632 SExtOrZExtPromotedOperands(LHS, RHS);
2633 }
2634
2635 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS), 0);
2636}
2637
2638SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
2639 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
2640 Op3: ZExtPromotedInteger(Op: N->getOperand(Num: 2))), 0);
2641}
2642
2643SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
2644 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2645 SDLoc dl(N);
2646 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Op);
2647 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Op.getValueType(),
2648 N1: Op, N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
2649}
2650
2651SDValue DAGTypeLegalizer::PromoteIntOp_VP_SIGN_EXTEND(SDNode *N) {
2652 SDLoc dl(N);
2653 EVT VT = N->getValueType(ResNo: 0);
2654 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2655 // FIXME: There is no VP_ANY_EXTEND yet.
2656 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2657 N3: N->getOperand(Num: 2));
2658 unsigned Diff =
2659 VT.getScalarSizeInBits() - N->getOperand(Num: 0).getScalarValueSizeInBits();
2660 SDValue ShAmt = DAG.getShiftAmountConstant(Val: Diff, VT, DL: dl);
2661 // FIXME: There is no VP_SIGN_EXTEND_INREG so use a pair of shifts.
2662 SDValue Shl = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT, N1: Op, N2: ShAmt, N3: N->getOperand(Num: 1),
2663 N4: N->getOperand(Num: 2));
2664 return DAG.getNode(Opcode: ISD::VP_SRA, DL: dl, VT, N1: Shl, N2: ShAmt, N3: N->getOperand(Num: 1),
2665 N4: N->getOperand(Num: 2));
2666}
2667
2668SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
2669 if (N->getOpcode() == ISD::VP_SINT_TO_FP)
2670 return SDValue(DAG.UpdateNodeOperands(N,
2671 Op1: SExtPromotedInteger(Op: N->getOperand(Num: 0)),
2672 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2673 0);
2674 return SDValue(DAG.UpdateNodeOperands(N,
2675 Op: SExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2676}
2677
2678SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
2679 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2680 Op2: SExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2681}
2682
2683SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
2684 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2685 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
2686 SDLoc dl(N);
2687
2688 SDValue Val = GetPromotedInteger(Op: N->getValue()); // Get promoted value.
2689
2690 // Truncate the value and store the result.
2691 return DAG.getTruncStore(Chain: Ch, dl, Val, Ptr,
2692 SVT: N->getMemoryVT(), MMO: N->getMemOperand());
2693}
2694
2695SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
2696 unsigned OpNo) {
2697
2698 assert(OpNo == 1 && "Unexpected operand for promotion");
2699 assert(!N->isIndexed() && "expecting unindexed vp_store!");
2700
2701 SDValue DataOp = GetPromotedInteger(Op: N->getValue());
2702 return DAG.getTruncStoreVP(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Ptr: N->getBasePtr(),
2703 Mask: N->getMask(), EVL: N->getVectorLength(),
2704 SVT: N->getMemoryVT(), MMO: N->getMemOperand(),
2705 IsCompressing: N->isCompressingStore());
2706}
2707
2708SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
2709 unsigned OpNo) {
2710 SDValue DataOp = N->getValue();
2711 SDValue Mask = N->getMask();
2712
2713 if (OpNo == 4) {
2714 // The Mask. Update in place.
2715 EVT DataVT = DataOp.getValueType();
2716 Mask = PromoteTargetBoolean(Bool: Mask, ValVT: DataVT);
2717 SmallVector<SDValue, 4> NewOps(N->ops());
2718 NewOps[4] = Mask;
2719 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2720 }
2721
2722 assert(OpNo == 1 && "Unexpected operand for promotion");
2723 DataOp = GetPromotedInteger(Op: DataOp);
2724
2725 return DAG.getMaskedStore(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Base: N->getBasePtr(),
2726 Offset: N->getOffset(), Mask, MemVT: N->getMemoryVT(),
2727 MMO: N->getMemOperand(), AM: N->getAddressingMode(),
2728 /*IsTruncating*/ true, IsCompressing: N->isCompressingStore());
2729}
2730
2731SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
2732 unsigned OpNo) {
2733 assert(OpNo == 3 && "Only know how to promote the mask!");
2734 EVT DataVT = N->getValueType(ResNo: 0);
2735 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2736 SmallVector<SDValue, 4> NewOps(N->ops());
2737 NewOps[OpNo] = Mask;
2738 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2739 if (Res == N)
2740 return SDValue(Res, 0);
2741
2742 // Update triggered CSE, do our own replacement since caller can't.
2743 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2744 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2745 return SDValue();
2746}
2747
2748SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
2749 unsigned OpNo) {
2750 SmallVector<SDValue, 5> NewOps(N->ops());
2751
2752 if (OpNo == 2) {
2753 // The Mask
2754 EVT DataVT = N->getValueType(ResNo: 0);
2755 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2756 } else if (OpNo == 4) {
2757 // The Index
2758 if (N->isIndexSigned())
2759 // Need to sign extend the index since the bits will likely be used.
2760 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2761 else
2762 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2763 } else
2764 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2765
2766 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2767 if (Res == N)
2768 return SDValue(Res, 0);
2769
2770 // Update triggered CSE, do our own replacement since caller can't.
2771 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2772 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2773 return SDValue();
2774}
2775
2776SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2777 unsigned OpNo) {
2778 bool TruncateStore = N->isTruncatingStore();
2779 SmallVector<SDValue, 5> NewOps(N->ops());
2780
2781 if (OpNo == 2) {
2782 // The Mask
2783 EVT DataVT = N->getValue().getValueType();
2784 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2785 } else if (OpNo == 4) {
2786 // The Index
2787 if (N->isIndexSigned())
2788 // Need to sign extend the index since the bits will likely be used.
2789 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2790 else
2791 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2792 } else {
2793 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2794 TruncateStore = true;
2795 }
2796
2797 return DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: N->getMemoryVT(),
2798 dl: SDLoc(N), Ops: NewOps, MMO: N->getMemOperand(),
2799 IndexType: N->getIndexType(), IsTruncating: TruncateStore);
2800}
2801
2802SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_COMPRESS(SDNode *N,
2803 unsigned OpNo) {
2804 assert(OpNo == 1 && "Can only promote VECTOR_COMPRESS mask.");
2805 SDValue Vec = N->getOperand(Num: 0);
2806 EVT VT = Vec.getValueType();
2807 SDValue Passthru = N->getOperand(Num: 2);
2808 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: VT);
2809 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT, N1: Vec, N2: Mask, N3: Passthru);
2810}
2811
2812SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2813 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2814 if (N->getOpcode() == ISD::VP_TRUNCATE)
2815 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Op,
2816 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2817 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2818}
2819
2820SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2821 if (N->getOpcode() == ISD::VP_UINT_TO_FP)
2822 return SDValue(DAG.UpdateNodeOperands(N,
2823 Op1: ZExtPromotedInteger(Op: N->getOperand(Num: 0)),
2824 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2825 0);
2826 return SDValue(DAG.UpdateNodeOperands(N,
2827 Op: ZExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2828}
2829
2830SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(SDNode *N) {
2831 return SDValue(DAG.UpdateNodeOperands(N, Op1: GetPromotedInteger(Op: N->getOperand(Num: 0)),
2832 Op2: N->getOperand(Num: 1)),
2833 0);
2834}
2835
2836SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2837 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2838 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2839}
2840
2841SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2842 SDLoc dl(N);
2843 SDValue Src = N->getOperand(Num: 0);
2844 SDValue Op = GetPromotedInteger(Op: Src);
2845 EVT VT = N->getValueType(ResNo: 0);
2846
2847 // If this zext has the nneg flag and the target prefers sext, see if the
2848 // promoted input is already sign extended.
2849 // TODO: Should we have some way to set nneg on ISD::AND instead?
2850 if (N->getFlags().hasNonNeg() && Op.getValueType() == VT &&
2851 TLI.isSExtCheaperThanZExt(FromTy: Src.getValueType(), ToTy: VT)) {
2852 unsigned OpEffectiveBits = DAG.ComputeMaxSignificantBits(Op);
2853 if (OpEffectiveBits <= Src.getScalarValueSizeInBits())
2854 return Op;
2855 }
2856
2857 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Op);
2858 return DAG.getZeroExtendInReg(Op, DL: dl, VT: Src.getValueType());
2859}
2860
2861SDValue DAGTypeLegalizer::PromoteIntOp_VP_ZERO_EXTEND(SDNode *N) {
2862 SDLoc dl(N);
2863 EVT VT = N->getValueType(ResNo: 0);
2864 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2865 // FIXME: There is no VP_ANY_EXTEND yet.
2866 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2867 N3: N->getOperand(Num: 2));
2868 return DAG.getVPZeroExtendInReg(Op, Mask: N->getOperand(Num: 1), EVL: N->getOperand(Num: 2), DL: dl,
2869 VT: N->getOperand(Num: 0).getValueType());
2870}
2871
2872SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2873 SDValue Op2 = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2874 return SDValue(
2875 DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1), Op3: Op2), 0);
2876}
2877
2878SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2879 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2880 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2881 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2882}
2883
2884SDValue DAGTypeLegalizer::PromoteIntOp_ExpOp(SDNode *N) {
2885 bool IsStrict = N->isStrictFPOpcode();
2886 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
2887
2888 bool IsPowI =
2889 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI;
2890 unsigned OpOffset = IsStrict ? 1 : 0;
2891
2892 // The integer operand is the last operand in FPOWI (or FLDEXP) (so the result
2893 // and floating point operand is already type legalized).
2894 RTLIB::Libcall LC = IsPowI ? RTLIB::getPOWI(RetVT: N->getValueType(ResNo: 0))
2895 : RTLIB::getLDEXP(RetVT: N->getValueType(ResNo: 0));
2896
2897 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
2898 if (LCImpl == RTLIB::Unsupported) {
2899 // Scalarize vector FPOWI instead of promoting the type. This allows the
2900 // scalar FPOWIs to be visited and converted to libcalls before promoting
2901 // the type.
2902 // FIXME: This should be done in LegalizeVectorOps/LegalizeDAG, but call
2903 // lowering needs the unpromoted EVT.
2904 if (IsPowI && N->getValueType(ResNo: 0).isVector())
2905 return DAG.UnrollVectorOp(N);
2906 SmallVector<SDValue, 3> NewOps(N->ops());
2907 NewOps[1 + OpOffset] = SExtPromotedInteger(Op: N->getOperand(Num: 1 + OpOffset));
2908 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2909 }
2910
2911 // We can't just promote the exponent type in FPOWI, since we want to lower
2912 // the node to a libcall and we if we promote to a type larger than
2913 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2914 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2915 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2916
2917 // A wider-than-int exponent can't be passed in an int (there's no wider
2918 // libcall), so bail like the soften/expand paths. A narrower one is
2919 // sign-extended to int by the makeLibCall below.
2920 if (N->getOperand(Num: 1 + OpOffset).getScalarValueSizeInBits() >
2921 DAG.getLibInfo().getIntSize()) {
2922 const Function &Fn = DAG.getMachineFunction().getFunction();
2923 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
2924 Twine(IsPowI ? "powi" : "ldexp") +
2925 " exponent does not match sizeof(int)",
2926 Fn, N->getDebugLoc()));
2927 if (IsStrict)
2928 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
2929 ReplaceValueWith(From: SDValue(N, 0), To: DAG.getPOISON(VT: N->getValueType(ResNo: 0)));
2930 return SDValue();
2931 }
2932
2933 TargetLowering::MakeLibCallOptions CallOptions;
2934 CallOptions.setIsSigned(true);
2935 SDValue Ops[2] = {N->getOperand(Num: 0 + OpOffset), N->getOperand(Num: 1 + OpOffset)};
2936 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2937 DAG, LibcallImpl: LCImpl, RetVT: N->getValueType(ResNo: 0), Ops, CallOptions, dl: SDLoc(N), Chain);
2938 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
2939 if (IsStrict)
2940 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
2941 return SDValue();
2942}
2943
2944static unsigned getExtendForIntVecReduction(SDNode *N) {
2945 switch (N->getOpcode()) {
2946 default:
2947 llvm_unreachable("Expected integer vector reduction");
2948 case ISD::VECREDUCE_ADD:
2949 case ISD::VECREDUCE_MUL:
2950 case ISD::VECREDUCE_AND:
2951 case ISD::VECREDUCE_OR:
2952 case ISD::VECREDUCE_XOR:
2953 case ISD::VP_REDUCE_ADD:
2954 case ISD::VP_REDUCE_MUL:
2955 case ISD::VP_REDUCE_AND:
2956 case ISD::VP_REDUCE_OR:
2957 case ISD::VP_REDUCE_XOR:
2958 return ISD::ANY_EXTEND;
2959 case ISD::VECREDUCE_SMAX:
2960 case ISD::VECREDUCE_SMIN:
2961 case ISD::VP_REDUCE_SMAX:
2962 case ISD::VP_REDUCE_SMIN:
2963 return ISD::SIGN_EXTEND;
2964 case ISD::VECREDUCE_UMAX:
2965 case ISD::VECREDUCE_UMIN:
2966 case ISD::VP_REDUCE_UMAX:
2967 case ISD::VP_REDUCE_UMIN:
2968 return ISD::ZERO_EXTEND;
2969 }
2970}
2971
2972SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2973 switch (getExtendForIntVecReduction(N)) {
2974 default:
2975 llvm_unreachable("Impossible extension kind for integer reduction");
2976 case ISD::ANY_EXTEND:
2977 return GetPromotedInteger(Op: V);
2978 case ISD::SIGN_EXTEND:
2979 return SExtPromotedInteger(Op: V);
2980 case ISD::ZERO_EXTEND:
2981 return ZExtPromotedInteger(Op: V);
2982 }
2983}
2984
2985SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2986 SDLoc dl(N);
2987 SDValue Op = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
2988
2989 EVT OrigEltVT = N->getOperand(Num: 0).getValueType().getVectorElementType();
2990 EVT InVT = Op.getValueType();
2991 EVT EltVT = InVT.getVectorElementType();
2992 EVT ResVT = N->getValueType(ResNo: 0);
2993 unsigned Opcode = N->getOpcode();
2994
2995 // An i1 vecreduce_xor is equivalent to vecreduce_add, use that instead if
2996 // vecreduce_xor is not legal
2997 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 &&
2998 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_XOR, VT: InVT) &&
2999 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_ADD, VT: InVT))
3000 Opcode = ISD::VECREDUCE_ADD;
3001
3002 // An i1 vecreduce_or is equivalent to vecreduce_umax, use that instead if
3003 // vecreduce_or is not legal
3004 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 &&
3005 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_OR, VT: InVT) &&
3006 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMAX, VT: InVT)) {
3007 Opcode = ISD::VECREDUCE_UMAX;
3008 // Can't use promoteTargetBoolean here because we still need
3009 // to either sign_ext or zero_ext in the undefined case.
3010 switch (TLI.getBooleanContents(Type: InVT)) {
3011 case TargetLoweringBase::UndefinedBooleanContent:
3012 case TargetLoweringBase::ZeroOrOneBooleanContent:
3013 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3014 break;
3015 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3016 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
3017 break;
3018 }
3019 }
3020
3021 // An i1 vecreduce_and is equivalent to vecreduce_umin, use that instead if
3022 // vecreduce_and is not legal
3023 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 &&
3024 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_AND, VT: InVT) &&
3025 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMIN, VT: InVT)) {
3026 Opcode = ISD::VECREDUCE_UMIN;
3027 // Can't use promoteTargetBoolean here because we still need
3028 // to either sign_ext or zero_ext in the undefined case.
3029 switch (TLI.getBooleanContents(Type: InVT)) {
3030 case TargetLoweringBase::UndefinedBooleanContent:
3031 case TargetLoweringBase::ZeroOrOneBooleanContent:
3032 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3033 break;
3034 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3035 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
3036 break;
3037 }
3038 }
3039
3040 if (ResVT.bitsGE(VT: EltVT))
3041 return DAG.getNode(Opcode, DL: SDLoc(N), VT: ResVT, Operand: Op);
3042
3043 // Result size must be >= element size. If this is not the case after
3044 // promotion, also promote the result type and then truncate.
3045 SDValue Reduce = DAG.getNode(Opcode, DL: dl, VT: EltVT, Operand: Op);
3046 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: ResVT, Operand: Reduce);
3047}
3048
3049SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
3050 SDLoc DL(N);
3051 SDValue Op = N->getOperand(Num: OpNo);
3052 SmallVector<SDValue, 4> NewOps(N->ops());
3053
3054 if (OpNo == 2) { // Mask
3055 // Update in place.
3056 NewOps[2] = PromoteTargetBoolean(Bool: Op, ValVT: N->getOperand(Num: 1).getValueType());
3057 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3058 }
3059
3060 assert(OpNo == 1 && "Unexpected operand for promotion");
3061
3062 Op = PromoteIntOpVectorReduction(N, V: Op);
3063
3064 NewOps[OpNo] = Op;
3065
3066 EVT VT = N->getValueType(ResNo: 0);
3067 EVT EltVT = Op.getValueType().getScalarType();
3068
3069 if (VT.bitsGE(VT: EltVT))
3070 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT, Ops: NewOps);
3071
3072 // Result size must be >= element/start-value size. If this is not the case
3073 // after promotion, also promote both the start value and result type and
3074 // then truncate.
3075 NewOps[0] =
3076 DAG.getNode(Opcode: getExtendForIntVecReduction(N), DL, VT: EltVT, Operand: N->getOperand(Num: 0));
3077 SDValue Reduce = DAG.getNode(Opcode: N->getOpcode(), DL, VT: EltVT, Ops: NewOps);
3078 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT, Operand: Reduce);
3079}
3080
3081SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
3082 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3083 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Op), 0);
3084}
3085
3086SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
3087 assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
3088 SmallVector<SDValue> NewOps(N->ops());
3089 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
3090 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3091}
3092
3093SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
3094 assert(OpNo >= 7);
3095 SmallVector<SDValue> NewOps(N->ops());
3096 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
3097 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3098}
3099
3100SDValue DAGTypeLegalizer::PromoteIntOp_WRITE_REGISTER(SDNode *N,
3101 unsigned OpNo) {
3102 const Function &Fn = DAG.getMachineFunction().getFunction();
3103 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
3104 "cannot use llvm.write_register with illegal type", Fn,
3105 N->getDebugLoc()));
3106 return N->getOperand(Num: 0);
3107}
3108
3109SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
3110 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
3111 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
3112
3113 SmallVector<SDValue, 8> NewOps(N->ops());
3114 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
3115 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
3116 if (Res == N)
3117 return SDValue(Res, 0);
3118
3119 // Update triggered CSE, do our own replacement since caller can't.
3120 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
3121 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
3122 return SDValue();
3123}
3124
3125SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
3126 SmallVector<SDValue, 6> NewOps(N->ops());
3127
3128 if (OpNo == 2) { // Offset operand
3129 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
3130 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3131 }
3132
3133 assert((OpNo == 4 || OpNo == 5) && "Unexpected operand for promotion");
3134
3135 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
3136 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3137}
3138
3139SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_HISTOGRAM(SDNode *N,
3140 unsigned OpNo) {
3141 assert(OpNo == 1 && "Unexpected operand for promotion");
3142 SmallVector<SDValue, 7> NewOps(N->ops());
3143 NewOps[1] = GetPromotedInteger(Op: N->getOperand(Num: 1));
3144 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3145}
3146
3147SDValue DAGTypeLegalizer::PromoteIntOp_UnaryBooleanVectorOp(SDNode *N,
3148 unsigned OpNo) {
3149 assert(OpNo == 0 && "Unexpected operand for promotion");
3150 SDValue Op = N->getOperand(Num: 0);
3151
3152 SDValue NewOp;
3153 if (TLI.getBooleanContents(Type: Op.getValueType()) ==
3154 TargetLowering::ZeroOrNegativeOneBooleanContent)
3155 NewOp = SExtPromotedInteger(Op);
3156 else
3157 NewOp = ZExtPromotedInteger(Op);
3158
3159 return SDValue(DAG.UpdateNodeOperands(N, Op: NewOp), 0);
3160}
3161
3162SDValue DAGTypeLegalizer::PromoteIntOp_GET_ACTIVE_LANE_MASK(SDNode *N) {
3163 SmallVector<SDValue, 1> NewOps(N->ops());
3164 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3165 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3166 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3167}
3168
3169SDValue DAGTypeLegalizer::PromoteIntOp_MaskedBinOp(SDNode *N, unsigned OpNo) {
3170 assert(OpNo == 2);
3171 SmallVector<SDValue, 3> NewOps(N->ops());
3172 NewOps[2] = PromoteTargetBoolean(Bool: NewOps[2], ValVT: N->getValueType(ResNo: 0));
3173 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3174}
3175
3176SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
3177 SmallVector<SDValue, 1> NewOps(N->ops());
3178 switch (N->getOpcode()) {
3179 case ISD::PARTIAL_REDUCE_SMLA:
3180 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3181 NewOps[2] = SExtPromotedInteger(Op: N->getOperand(Num: 2));
3182 break;
3183 case ISD::PARTIAL_REDUCE_UMLA:
3184 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3185 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3186 break;
3187 case ISD::PARTIAL_REDUCE_SUMLA:
3188 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3189 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3190 break;
3191 default:
3192 llvm_unreachable("unexpected opcode");
3193 }
3194 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3195}
3196
3197SDValue DAGTypeLegalizer::PromoteIntOp_LOOP_DEPENDENCE_MASK(SDNode *N) {
3198 SDValue NewOps[4];
3199 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3200 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3201 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3202 NewOps[3] = N->getOperand(Num: 3);
3203 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3204}
3205
3206//===----------------------------------------------------------------------===//
3207// Integer Result Expansion
3208//===----------------------------------------------------------------------===//
3209
3210/// ExpandIntegerResult - This method is called when the specified result of the
3211/// specified node is found to need expansion. At this point, the node may also
3212/// have invalid operands or may have other results that need promotion, we just
3213/// know that (at least) one result needs expansion.
3214void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
3215 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG));
3216 SDValue Lo, Hi;
3217 Lo = Hi = SDValue();
3218
3219 // See if the target wants to custom expand this node.
3220 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true))
3221 return;
3222
3223 switch (N->getOpcode()) {
3224 default:
3225#ifndef NDEBUG
3226 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
3227 N->dump(&DAG); dbgs() << "\n";
3228#endif
3229 report_fatal_error(reason: "Do not know how to expand the result of this "
3230 "operator!");
3231
3232 case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
3233 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
3234 case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
3235 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
3236 case ISD::POISON:
3237 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
3238 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
3239 case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;
3240
3241 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
3242 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
3243 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
3244 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
3245 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
3246
3247 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
3248 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
3249 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
3250 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
3251 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
3252 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
3253 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
3254 case ISD::ABS:
3255 case ISD::ABS_MIN_POISON:
3256 ExpandIntRes_ABS(N, Lo, Hi);
3257 break;
3258 case ISD::ABDS:
3259 case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
3260 case ISD::CTLZ_ZERO_POISON:
3261 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
3262 case ISD::CTLS: ExpandIntRes_CTLS(N, Lo, Hi); break;
3263 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
3264 case ISD::CTTZ_ZERO_POISON:
3265 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
3266 case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
3267 case ISD::STRICT_FP_TO_SINT:
3268 case ISD::FP_TO_SINT:
3269 case ISD::STRICT_FP_TO_UINT:
3270 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_XINT(N, Lo, Hi); break;
3271 case ISD::FP_TO_SINT_SAT:
3272 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
3273 case ISD::STRICT_LROUND:
3274 case ISD::STRICT_LRINT:
3275 case ISD::LROUND:
3276 case ISD::LRINT:
3277 case ISD::STRICT_LLROUND:
3278 case ISD::STRICT_LLRINT:
3279 case ISD::LLROUND:
3280 case ISD::LLRINT: ExpandIntRes_XROUND_XRINT(N, Lo, Hi); break;
3281 case ISD::LOAD: ExpandIntRes_LOAD(N: cast<LoadSDNode>(Val: N), Lo, Hi); break;
3282 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
3283 case ISD::READCYCLECOUNTER:
3284 case ISD::READSTEADYCOUNTER: ExpandIntRes_READCOUNTER(N, Lo, Hi); break;
3285 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
3286 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
3287 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
3288 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
3289 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
3290 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
3291 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
3292 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
3293 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
3294
3295 case ISD::ATOMIC_LOAD_ADD:
3296 case ISD::ATOMIC_LOAD_SUB:
3297 case ISD::ATOMIC_LOAD_AND:
3298 case ISD::ATOMIC_LOAD_CLR:
3299 case ISD::ATOMIC_LOAD_OR:
3300 case ISD::ATOMIC_LOAD_XOR:
3301 case ISD::ATOMIC_LOAD_NAND:
3302 case ISD::ATOMIC_LOAD_MIN:
3303 case ISD::ATOMIC_LOAD_MAX:
3304 case ISD::ATOMIC_LOAD_UMIN:
3305 case ISD::ATOMIC_LOAD_UMAX:
3306 case ISD::ATOMIC_SWAP:
3307 case ISD::ATOMIC_CMP_SWAP: {
3308 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node: N);
3309 SplitInteger(Op: Tmp.first, Lo, Hi);
3310 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
3311 break;
3312 }
3313 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3314 AtomicSDNode *AN = cast<AtomicSDNode>(Val: N);
3315 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: MVT::Other);
3316 SDValue Tmp = DAG.getAtomicCmpSwap(
3317 Opcode: ISD::ATOMIC_CMP_SWAP, dl: SDLoc(N), MemVT: AN->getMemoryVT(), VTs,
3318 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 1), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
3319 MMO: AN->getMemOperand());
3320
3321 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
3322 // success simply by comparing the loaded value against the ingoing
3323 // comparison.
3324 SDValue Success = DAG.getSetCC(DL: SDLoc(N), VT: N->getValueType(ResNo: 1), LHS: Tmp,
3325 RHS: N->getOperand(Num: 2), Cond: ISD::SETEQ);
3326
3327 SplitInteger(Op: Tmp, Lo, Hi);
3328 ReplaceValueWith(From: SDValue(N, 1), To: Success);
3329 ReplaceValueWith(From: SDValue(N, 2), To: Tmp.getValue(R: 1));
3330 break;
3331 }
3332
3333 case ISD::AND:
3334 case ISD::OR:
3335 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
3336
3337 case ISD::UMAX:
3338 case ISD::SMAX:
3339 case ISD::UMIN:
3340 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
3341
3342 case ISD::SCMP:
3343 case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
3344
3345 case ISD::ADD:
3346 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
3347
3348 case ISD::ADDC:
3349 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
3350
3351 case ISD::ADDE:
3352 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
3353
3354 case ISD::UADDO_CARRY:
3355 case ISD::USUBO_CARRY: ExpandIntRes_UADDSUBO_CARRY(N, Lo, Hi); break;
3356
3357 case ISD::SADDO_CARRY:
3358 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
3359
3360 case ISD::SHL:
3361 case ISD::SRA:
3362 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
3363
3364 case ISD::SADDO:
3365 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
3366 case ISD::UADDO:
3367 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
3368 case ISD::UMULO:
3369 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3370
3371 case ISD::SADDSAT:
3372 case ISD::UADDSAT:
3373 case ISD::SSUBSAT:
3374 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
3375
3376 case ISD::SSHLSAT:
3377 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
3378
3379 case ISD::AVGCEILS:
3380 case ISD::AVGCEILU:
3381 case ISD::AVGFLOORS:
3382 case ISD::AVGFLOORU: ExpandIntRes_AVG(N, Lo, Hi); break;
3383
3384 case ISD::SMULFIX:
3385 case ISD::SMULFIXSAT:
3386 case ISD::UMULFIX:
3387 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
3388
3389 case ISD::SDIVFIX:
3390 case ISD::SDIVFIXSAT:
3391 case ISD::UDIVFIX:
3392 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
3393
3394 case ISD::VECREDUCE_ADD:
3395 case ISD::VECREDUCE_MUL:
3396 case ISD::VECREDUCE_AND:
3397 case ISD::VECREDUCE_OR:
3398 case ISD::VECREDUCE_XOR:
3399 case ISD::VECREDUCE_SMAX:
3400 case ISD::VECREDUCE_SMIN:
3401 case ISD::VECREDUCE_UMAX:
3402 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
3403
3404 case ISD::ROTL:
3405 case ISD::ROTR:
3406 ExpandIntRes_Rotate(N, Lo, Hi);
3407 break;
3408
3409 case ISD::FSHL:
3410 case ISD::FSHR:
3411 ExpandIntRes_FunnelShift(N, Lo, Hi);
3412 break;
3413
3414 case ISD::CLMUL:
3415 case ISD::CLMULR:
3416 case ISD::CLMULH:
3417 ExpandIntRes_CLMUL(N, Lo, Hi);
3418 break;
3419
3420 case ISD::PEXT:
3421 ExpandIntRes_PEXT(N, Lo, Hi);
3422 break;
3423
3424 case ISD::PDEP:
3425 ExpandIntRes_PDEP(N, Lo, Hi);
3426 break;
3427
3428 case ISD::VSCALE:
3429 ExpandIntRes_VSCALE(N, Lo, Hi);
3430 break;
3431
3432 case ISD::READ_REGISTER:
3433 ExpandIntRes_READ_REGISTER(N, Lo, Hi);
3434 break;
3435
3436 case ISD::CTTZ_ELTS:
3437 case ISD::CTTZ_ELTS_ZERO_POISON:
3438 ExpandIntRes_CTTZ_ELTS(N, Lo, Hi);
3439 break;
3440 }
3441
3442 // If Lo/Hi is null, the sub-method took care of registering results etc.
3443 if (Lo.getNode())
3444 SetExpandedInteger(Op: SDValue(N, ResNo), Lo, Hi);
3445}
3446
3447/// Lower an atomic node to the appropriate builtin call.
3448std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
3449 unsigned Opc = Node->getOpcode();
3450 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
3451 AtomicOrdering order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
3452 // Lower to outline atomic libcall if outline atomics enabled,
3453 // or to sync libcall otherwise
3454 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order: order, VT);
3455 EVT RetVT = Node->getValueType(ResNo: 0);
3456 TargetLowering::MakeLibCallOptions CallOptions;
3457 SmallVector<SDValue, 4> Ops;
3458
3459 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3460 if (LCImpl != RTLIB::Unsupported) {
3461 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
3462 Ops.push_back(Elt: Node->getOperand(Num: 1));
3463 } else {
3464 LC = RTLIB::getSYNC(Opc, VT);
3465 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3466 "Unexpected atomic op or value type!");
3467 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
3468 LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3469 }
3470 return TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT, Ops, CallOptions, dl: SDLoc(Node),
3471 Chain: Node->getOperand(Num: 0));
3472}
3473
3474/// N is a shift by a value that needs to be expanded,
3475/// and the shift amount is a constant 'Amt'. Expand the operation.
3476void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
3477 SDValue &Lo, SDValue &Hi) {
3478 SDLoc DL(N);
3479 // Expand the incoming operand to be shifted, so that we have its parts
3480 SDValue InL, InH;
3481 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3482
3483 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
3484 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
3485 if (!Amt) {
3486 Lo = InL;
3487 Hi = InH;
3488 return;
3489 }
3490
3491 EVT NVT = InL.getValueType();
3492 unsigned VTBits = N->getValueType(ResNo: 0).getSizeInBits();
3493 unsigned NVTBits = NVT.getSizeInBits();
3494
3495 if (N->getOpcode() == ISD::SHL) {
3496 if (Amt.uge(RHS: VTBits)) {
3497 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3498 } else if (Amt.ugt(RHS: NVTBits)) {
3499 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3500 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3501 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3502 } else if (Amt == NVTBits) {
3503 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3504 Hi = InL;
3505 } else {
3506 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3507 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3508 // Use FSHL if legal so we don't need to combine it later.
3509 if (TLI.isOperationLegal(Op: ISD::FSHL, VT: NVT)) {
3510 Hi = DAG.getNode(Opcode: ISD::FSHL, DL, VT: NVT, N1: InH, N2: InL,
3511 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3512 } else {
3513 Hi = DAG.getNode(
3514 Opcode: ISD::OR, DL, VT: NVT,
3515 N1: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3516 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3517 N2: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3518 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3519 }
3520 }
3521 return;
3522 }
3523
3524 if (N->getOpcode() == ISD::SRL) {
3525 if (Amt.uge(RHS: VTBits)) {
3526 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3527 } else if (Amt.ugt(RHS: NVTBits)) {
3528 Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3529 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3530 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3531 } else if (Amt == NVTBits) {
3532 Lo = InH;
3533 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3534 } else {
3535 // Use FSHR if legal so we don't need to combine it later.
3536 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3537 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3538 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3539 } else {
3540 Lo = DAG.getNode(
3541 Opcode: ISD::OR, DL, VT: NVT,
3542 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3543 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3544 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3545 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3546 }
3547 Hi = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3548 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3549 }
3550 return;
3551 }
3552
3553 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3554 if (Amt.uge(RHS: VTBits)) {
3555 Hi = Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3556 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3557 } else if (Amt.ugt(RHS: NVTBits)) {
3558 Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3559 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3560 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3561 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3562 } else if (Amt == NVTBits) {
3563 Lo = InH;
3564 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3565 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3566 } else {
3567 // Use FSHR if legal so we don't need to combine it later.
3568 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3569 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3570 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3571 } else {
3572 Lo = DAG.getNode(
3573 Opcode: ISD::OR, DL, VT: NVT,
3574 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3575 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3576 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3577 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3578 }
3579 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3580 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3581 }
3582}
3583
3584/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
3585/// this shift based on knowledge of the high bit of the shift amount. If we
3586/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
3587/// shift amount.
3588bool DAGTypeLegalizer::
3589ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3590 unsigned Opc = N->getOpcode();
3591 SDValue In = N->getOperand(Num: 0);
3592 SDValue Amt = N->getOperand(Num: 1);
3593 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3594 EVT ShTy = Amt.getValueType();
3595 unsigned ShBits = ShTy.getScalarSizeInBits();
3596 unsigned NVTBits = NVT.getScalarSizeInBits();
3597 assert(isPowerOf2_32(NVTBits) &&
3598 "Expanded integer type size not a power of two!");
3599 SDLoc dl(N);
3600
3601 APInt HighBitMask = APInt::getHighBitsSet(numBits: ShBits, hiBitsSet: ShBits - Log2_32(Value: NVTBits));
3602 KnownBits Known = DAG.computeKnownBits(Op: Amt);
3603
3604 // If we don't know anything about the high bits, exit.
3605 if (((Known.Zero | Known.One) & HighBitMask) == 0)
3606 return false;
3607
3608 // Get the incoming operand to be shifted.
3609 SDValue InL, InH;
3610 GetExpandedInteger(Op: In, Lo&: InL, Hi&: InH);
3611
3612 // If we know that any of the high bits of the shift amount are one, then we
3613 // can do this as a couple of simple shifts.
3614 if (Known.One.intersects(RHS: HighBitMask)) {
3615 // Mask out the high bit, which we know is set.
3616 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShTy, N1: Amt,
3617 N2: DAG.getConstant(Val: ~HighBitMask, DL: dl, VT: ShTy));
3618
3619 switch (Opc) {
3620 default: llvm_unreachable("Unknown shift");
3621 case ISD::SHL:
3622 Lo = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Low part is zero.
3623 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt); // High part from Lo part.
3624 return true;
3625 case ISD::SRL:
3626 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3627 Lo = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3628 return true;
3629 case ISD::SRA:
3630 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign extend high part.
3631 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3632 Lo = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3633 return true;
3634 }
3635 }
3636
3637 // If we know that all of the high bits of the shift amount are zero, then we
3638 // can do this as a couple of simple shifts.
3639 if (HighBitMask.isSubsetOf(RHS: Known.Zero)) {
3640 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
3641 // shift if x is zero. We can use XOR here because x is known to be smaller
3642 // than 32.
3643 SDValue Amt2 = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: ShTy, N1: Amt,
3644 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3645
3646 unsigned Op1, Op2;
3647 switch (Opc) {
3648 default: llvm_unreachable("Unknown shift");
3649 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
3650 case ISD::SRL:
3651 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
3652 }
3653
3654 // When shifting right the arithmetic for Lo and Hi is swapped.
3655 if (Opc != ISD::SHL)
3656 std::swap(a&: InL, b&: InH);
3657
3658 // Use a little trick to get the bits that move from Lo to Hi. First
3659 // shift by one bit.
3660 SDValue Sh1 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: InL, N2: DAG.getConstant(Val: 1, DL: dl, VT: ShTy));
3661 // Then compute the remaining shift with amount-1.
3662 SDValue Sh2 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: Sh1, N2: Amt2);
3663
3664 Lo = DAG.getNode(Opcode: Opc, DL: dl, VT: NVT, N1: InL, N2: Amt);
3665 Hi = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: Op1, DL: dl, VT: NVT, N1: InH, N2: Amt),N2: Sh2);
3666
3667 if (Opc != ISD::SHL)
3668 std::swap(a&: Hi, b&: Lo);
3669 return true;
3670 }
3671
3672 return false;
3673}
3674
3675/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
3676/// of any size.
3677bool DAGTypeLegalizer::
3678ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3679 SDValue Amt = N->getOperand(Num: 1);
3680 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3681 EVT ShTy = Amt.getValueType();
3682 unsigned NVTBits = NVT.getSizeInBits();
3683 assert(isPowerOf2_32(NVTBits) &&
3684 "Expanded integer type size not a power of two!");
3685 SDLoc dl(N);
3686
3687 // Get the incoming operand to be shifted.
3688 SDValue InL, InH;
3689 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3690
3691 SDValue NVBitsNode = DAG.getConstant(Val: NVTBits, DL: dl, VT: ShTy);
3692 SDValue AmtExcess = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: Amt, N2: NVBitsNode);
3693 SDValue AmtLack = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: NVBitsNode, N2: Amt);
3694 SDValue isShort = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3695 LHS: Amt, RHS: NVBitsNode, Cond: ISD::SETULT);
3696 SDValue isZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3697 LHS: Amt, RHS: DAG.getConstant(Val: 0, DL: dl, VT: ShTy),
3698 Cond: ISD::SETEQ);
3699
3700 SDValue LoS, HiS, LoL, HiL;
3701 switch (N->getOpcode()) {
3702 default: llvm_unreachable("Unknown shift");
3703 case ISD::SHL:
3704 // Short: ShAmt < NVTBits
3705 LoS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt);
3706 HiS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3707 N1: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: Amt),
3708 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: AmtLack));
3709
3710 // Long: ShAmt >= NVTBits
3711 LoL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Lo part is zero.
3712 HiL = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: AmtExcess); // Hi from Lo part.
3713
3714 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL);
3715 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InH,
3716 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL));
3717 return true;
3718 case ISD::SRL:
3719 // Short: ShAmt < NVTBits
3720 HiS = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt);
3721 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3722 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3723 // FIXME: If Amt is zero, the following shift generates an undefined result
3724 // on some architectures.
3725 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3726
3727 // Long: ShAmt >= NVTBits
3728 HiL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3729 LoL = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3730
3731 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3732 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3733 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3734 return true;
3735 case ISD::SRA:
3736 // Short: ShAmt < NVTBits
3737 HiS = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt);
3738 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3739 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3740 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3741
3742 // Long: ShAmt >= NVTBits
3743 HiL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign of Hi part.
3744 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3745 LoL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3746
3747 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3748 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3749 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3750 return true;
3751 }
3752}
3753
3754static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
3755
3756 switch (Op) {
3757 default: llvm_unreachable("invalid min/max opcode");
3758 case ISD::SMAX:
3759 return std::make_pair(x: ISD::SETGT, y: ISD::UMAX);
3760 case ISD::UMAX:
3761 return std::make_pair(x: ISD::SETUGT, y: ISD::UMAX);
3762 case ISD::SMIN:
3763 return std::make_pair(x: ISD::SETLT, y: ISD::UMIN);
3764 case ISD::UMIN:
3765 return std::make_pair(x: ISD::SETULT, y: ISD::UMIN);
3766 }
3767}
3768
3769void DAGTypeLegalizer::ExpandIntRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
3770 SDLoc DL(N);
3771
3772 SDValue LHS = N->getOperand(Num: 0);
3773 SDValue RHS = N->getOperand(Num: 1);
3774 EVT NewVT = getSetCCResultType(VT: LHS.getValueType());
3775
3776 // Taking the same approach as ScalarizeVecRes_SETCC
3777 SDValue Res = DAG.getNode(Opcode: ISD::SETCC, DL, VT: NewVT, N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
3778
3779 Res = DAG.getBoolExtOrTrunc(Op: Res, SL: DL, VT: N->getValueType(ResNo: 0), OpVT: NewVT);
3780 SplitInteger(Op: Res, Lo, Hi);
3781}
3782
3783void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
3784 SDValue &Lo, SDValue &Hi) {
3785 SDLoc DL(N);
3786
3787 SDValue LHS = N->getOperand(Num: 0);
3788 SDValue RHS = N->getOperand(Num: 1);
3789
3790 // If the upper halves are all sign bits, then we can perform the MINMAX on
3791 // the lower half and sign-extend the result to the upper half.
3792 unsigned NumBits = N->getValueType(ResNo: 0).getScalarSizeInBits();
3793 unsigned NumHalfBits = NumBits / 2;
3794 if (DAG.ComputeNumSignBits(Op: LHS) > NumHalfBits &&
3795 DAG.ComputeNumSignBits(Op: RHS) > NumHalfBits) {
3796 SDValue LHSL, LHSH, RHSL, RHSH;
3797 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3798 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3799 EVT NVT = LHSL.getValueType();
3800
3801 Lo = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: LHSL, N2: RHSL);
3802 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: Lo,
3803 N2: DAG.getShiftAmountConstant(Val: NumHalfBits - 1, VT: NVT, DL));
3804 return;
3805 }
3806
3807 // The Lo of smin(X, -1) is LHSL if X is negative. Otherwise it's -1.
3808 // The Lo of smax(X, 0) is 0 if X is negative. Otherwise it's LHSL.
3809 if ((N->getOpcode() == ISD::SMAX && isNullConstant(V: RHS)) ||
3810 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(V: RHS))) {
3811 SDValue LHSL, LHSH, RHSL, RHSH;
3812 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3813 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3814 EVT NVT = LHSL.getValueType();
3815 EVT CCT = getSetCCResultType(VT: NVT);
3816
3817 SDValue HiNeg =
3818 DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: DAG.getConstant(Val: 0, DL, VT: NVT), Cond: ISD::SETLT);
3819 if (N->getOpcode() == ISD::SMIN) {
3820 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: LHSL, RHS: DAG.getAllOnesConstant(DL, VT: NVT));
3821 } else {
3822 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: DAG.getConstant(Val: 0, DL, VT: NVT), RHS: LHSL);
3823 }
3824 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3825 return;
3826 }
3827
3828 const APInt *RHSVal = nullptr;
3829 if (auto *RHSConst = dyn_cast<ConstantSDNode>(Val&: RHS))
3830 RHSVal = &RHSConst->getAPIntValue();
3831
3832 // The high half of MIN/MAX is always just the the MIN/MAX of the
3833 // high halves of the operands. Expand this way if it appears profitable.
3834 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) &&
3835 (RHSVal->countLeadingOnes() >= NumHalfBits ||
3836 RHSVal->countLeadingZeros() >= NumHalfBits)) {
3837 SDValue LHSL, LHSH, RHSL, RHSH;
3838 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3839 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3840 EVT NVT = LHSL.getValueType();
3841 EVT CCT = getSetCCResultType(VT: NVT);
3842
3843 ISD::NodeType LoOpc;
3844 ISD::CondCode CondC;
3845 std::tie(args&: CondC, args&: LoOpc) = getExpandedMinMaxOps(Op: N->getOpcode());
3846
3847 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3848 // We need to know whether to select Lo part that corresponds to 'winning'
3849 // Hi part or if Hi parts are equal.
3850 SDValue IsHiLeft = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: CondC);
3851 SDValue IsHiEq = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: ISD::SETEQ);
3852
3853 // Lo part corresponding to the 'winning' Hi part
3854 SDValue LoCmp = DAG.getSelect(DL, VT: NVT, Cond: IsHiLeft, LHS: LHSL, RHS: RHSL);
3855
3856 // Recursed Lo part if Hi parts are equal, this uses unsigned version
3857 SDValue LoMinMax = DAG.getNode(Opcode: LoOpc, DL, VT: NVT, Ops: {LHSL, RHSL});
3858
3859 Lo = DAG.getSelect(DL, VT: NVT, Cond: IsHiEq, LHS: LoMinMax, RHS: LoCmp);
3860 return;
3861 }
3862
3863 // Expand to "a < b ? a : b" etc. Prefer ge/le if that simplifies
3864 // the compare.
3865 ISD::CondCode Pred;
3866 switch (N->getOpcode()) {
3867 default: llvm_unreachable("How did we get here?");
3868 case ISD::SMAX:
3869 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3870 Pred = ISD::SETGE;
3871 else
3872 Pred = ISD::SETGT;
3873 break;
3874 case ISD::SMIN:
3875 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3876 Pred = ISD::SETLE;
3877 else
3878 Pred = ISD::SETLT;
3879 break;
3880 case ISD::UMAX:
3881 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3882 Pred = ISD::SETUGE;
3883 else
3884 Pred = ISD::SETUGT;
3885 break;
3886 case ISD::UMIN:
3887 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3888 Pred = ISD::SETULE;
3889 else
3890 Pred = ISD::SETULT;
3891 break;
3892 }
3893 EVT VT = N->getValueType(ResNo: 0);
3894 EVT CCT = getSetCCResultType(VT);
3895 SDValue Cond = DAG.getSetCC(DL, VT: CCT, LHS, RHS, Cond: Pred);
3896 SDValue Result = DAG.getSelect(DL, VT, Cond, LHS, RHS);
3897 SplitInteger(Op: Result, Lo, Hi);
3898}
3899
3900void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
3901 SDValue ExpandedCMP = TLI.expandCMP(Node: N, DAG);
3902 SplitInteger(Op: ExpandedCMP, Lo, Hi);
3903}
3904
3905void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
3906 SDValue &Lo, SDValue &Hi) {
3907 SDLoc dl(N);
3908 // Expand the subcomponents.
3909 SDValue LHSL, LHSH, RHSL, RHSH;
3910 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3911 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3912
3913 EVT NVT = LHSL.getValueType();
3914 SDValue LoOps[2] = { LHSL, RHSL };
3915 SDValue HiOps[3] = { LHSH, RHSH };
3916
3917 bool HasOpCarry = TLI.isOperationLegalOrCustom(
3918 Op: N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
3919 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3920 if (HasOpCarry) {
3921 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
3922 if (N->getOpcode() == ISD::ADD) {
3923 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3924 HiOps[2] = Lo.getValue(R: 1);
3925 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3926 ? DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3927 : DAG.getNode(Opcode: ISD::UADDO_CARRY, DL: dl, VTList, Ops: HiOps);
3928 } else {
3929 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3930 HiOps[2] = Lo.getValue(R: 1);
3931 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3932 ? DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3933 : DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, Ops: HiOps);
3934 }
3935 return;
3936 }
3937
3938 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
3939 // them. TODO: Teach operation legalization how to expand unsupported
3940 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
3941 // a carry of type MVT::Glue, but there doesn't seem to be any way to
3942 // generate a value of this type in the expanded code sequence.
3943 bool hasCarry =
3944 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3945 ISD::ADDC : ISD::SUBC,
3946 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3947
3948 if (hasCarry) {
3949 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: MVT::Glue);
3950 if (N->getOpcode() == ISD::ADD) {
3951 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3952 HiOps[2] = Lo.getValue(R: 1);
3953 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3954 } else {
3955 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3956 HiOps[2] = Lo.getValue(R: 1);
3957 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3958 }
3959 return;
3960 }
3961
3962 bool hasOVF =
3963 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3964 ISD::UADDO : ISD::USUBO,
3965 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3966 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(Type: NVT);
3967
3968 if (hasOVF) {
3969 EVT OvfVT = getSetCCResultType(VT: NVT);
3970 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: OvfVT);
3971 int RevOpc;
3972 if (N->getOpcode() == ISD::ADD) {
3973 RevOpc = ISD::SUB;
3974 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3975 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3976 } else {
3977 RevOpc = ISD::ADD;
3978 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3979 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3980 }
3981 SDValue OVF = Lo.getValue(R: 1);
3982
3983 switch (BoolType) {
3984 case TargetLoweringBase::UndefinedBooleanContent:
3985 OVF = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: OvfVT, N1: DAG.getConstant(Val: 1, DL: dl, VT: OvfVT), N2: OVF);
3986 [[fallthrough]];
3987 case TargetLoweringBase::ZeroOrOneBooleanContent:
3988 OVF = DAG.getZExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3989 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Hi, N2: OVF);
3990 break;
3991 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3992 OVF = DAG.getSExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3993 Hi = DAG.getNode(Opcode: RevOpc, DL: dl, VT: NVT, N1: Hi, N2: OVF);
3994 }
3995 return;
3996 }
3997
3998 if (N->getOpcode() == ISD::ADD) {
3999 Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: LoOps);
4000 SDValue Cmp;
4001 // Special case: X+1 has a carry out if X+1==0. This may reduce the live
4002 // range of X. We assume comparing with 0 is cheap.
4003 if (isOneConstant(V: LoOps[1]))
4004 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
4005 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
4006 else if (isAllOnesConstant(V: LoOps[1])) {
4007 if (isAllOnesConstant(V: HiOps[1]))
4008 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
4009 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
4010 else
4011 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
4012 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4013 } else
4014 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo, RHS: LoOps[0],
4015 Cond: ISD::SETULT);
4016
4017 SDValue Carry;
4018 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
4019 Carry = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
4020 else
4021 Carry = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
4022 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
4023
4024 if (isAllOnesConstant(V: LoOps[1]) && isAllOnesConstant(V: HiOps[1])) {
4025 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: HiOps[0], N2: Carry);
4026 } else {
4027 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
4028 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Hi, N2: Carry);
4029 }
4030 } else {
4031 Lo = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: LoOps);
4032 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
4033 SDValue Cmp =
4034 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LoOps[0].getValueType()),
4035 LHS: LoOps[0], RHS: LoOps[1], Cond: ISD::SETULT);
4036
4037 SDValue Borrow;
4038 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
4039 Borrow = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
4040 else
4041 Borrow = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
4042 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
4043
4044 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Hi, N2: Borrow);
4045 }
4046}
4047
4048void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
4049 SDValue &Lo, SDValue &Hi) {
4050 // Expand the subcomponents.
4051 SDValue LHSL, LHSH, RHSL, RHSH;
4052 SDLoc dl(N);
4053 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4054 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4055 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
4056 SDValue LoOps[2] = { LHSL, RHSL };
4057 SDValue HiOps[3] = { LHSH, RHSH };
4058
4059 if (N->getOpcode() == ISD::ADDC) {
4060 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
4061 HiOps[2] = Lo.getValue(R: 1);
4062 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
4063 } else {
4064 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
4065 HiOps[2] = Lo.getValue(R: 1);
4066 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
4067 }
4068
4069 // Legalized the flag result - switch anything that used the old flag to
4070 // use the new one.
4071 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4072}
4073
4074void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
4075 SDValue &Lo, SDValue &Hi) {
4076 // Expand the subcomponents.
4077 SDValue LHSL, LHSH, RHSL, RHSH;
4078 SDLoc dl(N);
4079 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4080 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4081 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
4082 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
4083 SDValue HiOps[3] = { LHSH, RHSH };
4084
4085 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
4086 HiOps[2] = Lo.getValue(R: 1);
4087 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
4088
4089 // Legalized the flag result - switch anything that used the old flag to
4090 // use the new one.
4091 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4092}
4093
4094void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
4095 SDValue &Lo, SDValue &Hi) {
4096 SDValue LHS = N->getOperand(Num: 0);
4097 SDValue RHS = N->getOperand(Num: 1);
4098 SDLoc dl(N);
4099
4100 SDValue Ovf;
4101
4102 unsigned CarryOp, NoCarryOp;
4103 ISD::CondCode Cond;
4104 switch(N->getOpcode()) {
4105 case ISD::UADDO:
4106 CarryOp = ISD::UADDO_CARRY;
4107 NoCarryOp = ISD::ADD;
4108 Cond = ISD::SETULT;
4109 break;
4110 case ISD::USUBO:
4111 CarryOp = ISD::USUBO_CARRY;
4112 NoCarryOp = ISD::SUB;
4113 Cond = ISD::SETUGT;
4114 break;
4115 default:
4116 llvm_unreachable("Node has unexpected Opcode");
4117 }
4118
4119 bool HasCarryOp = TLI.isOperationLegalOrCustom(
4120 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
4121
4122 if (HasCarryOp) {
4123 // Expand the subcomponents.
4124 SDValue LHSL, LHSH, RHSL, RHSH;
4125 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
4126 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
4127 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4128 SDValue LoOps[2] = { LHSL, RHSL };
4129 SDValue HiOps[3] = { LHSH, RHSH };
4130
4131 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
4132 HiOps[2] = Lo.getValue(R: 1);
4133 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: HiOps);
4134
4135 Ovf = Hi.getValue(R: 1);
4136 } else {
4137 // Expand the result by simply replacing it with the equivalent
4138 // non-overflow-checking operation.
4139 SDValue Sum = DAG.getNode(Opcode: NoCarryOp, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS);
4140 SplitInteger(Op: Sum, Lo, Hi);
4141
4142 if (N->getOpcode() == ISD::UADDO && isOneConstant(V: RHS)) {
4143 // Special case: uaddo X, 1 overflowed if X+1 == 0. We can detect this
4144 // with (Lo | Hi) == 0.
4145 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Lo.getValueType(), N1: Lo, N2: Hi);
4146 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Or,
4147 RHS: DAG.getConstant(Val: 0, DL: dl, VT: Lo.getValueType()), Cond: ISD::SETEQ);
4148 } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(V: RHS)) {
4149 // Special case: uaddo X, -1 overflows if X == 0.
4150 Ovf =
4151 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS,
4152 RHS: DAG.getConstant(Val: 0, DL: dl, VT: LHS.getValueType()), Cond: ISD::SETNE);
4153 } else {
4154 // Calculate the overflow: addition overflows iff a + b < a, and
4155 // subtraction overflows iff a - b > a.
4156 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Sum, RHS: LHS, Cond);
4157 }
4158 }
4159
4160 // Legalized the flag result - switch anything that used the old flag to
4161 // use the new one.
4162 ReplaceValueWith(From: SDValue(N, 1), To: Ovf);
4163}
4164
4165void DAGTypeLegalizer::ExpandIntRes_UADDSUBO_CARRY(SDNode *N, SDValue &Lo,
4166 SDValue &Hi) {
4167 // Expand the subcomponents.
4168 SDValue LHSL, LHSH, RHSL, RHSH;
4169 SDLoc dl(N);
4170 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4171 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4172 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4173 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
4174 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
4175
4176 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
4177 HiOps[2] = Lo.getValue(R: 1);
4178 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
4179
4180 // Legalized the flag result - switch anything that used the old flag to
4181 // use the new one.
4182 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4183}
4184
4185void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
4186 SDValue &Lo, SDValue &Hi) {
4187 // Expand the subcomponents.
4188 SDValue LHSL, LHSH, RHSL, RHSH;
4189 SDLoc dl(N);
4190 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4191 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4192 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4193
4194 // We need to use an unsigned carry op for the lo part.
4195 unsigned CarryOp =
4196 N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
4197 Lo = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSL, RHSL, N->getOperand(Num: 2) });
4198 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4199
4200 // Legalized the flag result - switch anything that used the old flag to
4201 // use the new one.
4202 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4203}
4204
4205void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
4206 SDValue &Lo, SDValue &Hi) {
4207 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4208 SDLoc dl(N);
4209 SDValue Op = N->getOperand(Num: 0);
4210 if (Op.getValueType().bitsLE(VT: NVT)) {
4211 // The low part is any extension of the input (which degenerates to a copy).
4212 Lo = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Op);
4213 Hi = DAG.getUNDEF(VT: NVT); // The high part is undefined.
4214 } else {
4215 // For example, extension of an i48 to an i64. The operand type necessarily
4216 // promotes to the result type, so will end up being expanded too.
4217 assert(getTypeAction(Op.getValueType()) ==
4218 TargetLowering::TypePromoteInteger &&
4219 "Only know how to promote this result!");
4220 SDValue Res = GetPromotedInteger(Op);
4221 assert(Res.getValueType() == N->getValueType(0) &&
4222 "Operand over promoted?");
4223 // Split the promoted operand. This will simplify when it is expanded.
4224 SplitInteger(Op: Res, Lo, Hi);
4225 }
4226}
4227
4228void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
4229 SDValue &Lo, SDValue &Hi) {
4230 SDLoc dl(N);
4231 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4232 EVT NVT = Lo.getValueType();
4233 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4234 unsigned NVTBits = NVT.getSizeInBits();
4235 unsigned EVTBits = EVT.getSizeInBits();
4236
4237 if (NVTBits < EVTBits) {
4238 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Hi,
4239 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4240 BitWidth: EVTBits - NVTBits)));
4241 } else {
4242 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4243 // The high part replicates the sign bit of Lo, make it explicit.
4244 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4245 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL: dl));
4246 }
4247}
4248
4249void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
4250 SDValue &Lo, SDValue &Hi) {
4251 SDLoc dl(N);
4252 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4253 EVT NVT = Lo.getValueType();
4254 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4255 unsigned NVTBits = NVT.getSizeInBits();
4256 unsigned EVTBits = EVT.getSizeInBits();
4257
4258 if (NVTBits < EVTBits) {
4259 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Hi,
4260 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4261 BitWidth: EVTBits - NVTBits)));
4262 } else {
4263 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4264 // The high part must be zero, make it explicit.
4265 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4266 }
4267}
4268
4269void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
4270 SDValue &Lo, SDValue &Hi) {
4271 SDLoc dl(N);
4272 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4273 Lo = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4274 Hi = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4275}
4276
4277void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
4278 SDValue &Lo, SDValue &Hi) {
4279 SDLoc dl(N);
4280 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4281 Lo = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4282 Hi = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4283}
4284
4285void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
4286 SDValue &Hi) {
4287 SDLoc dl(N);
4288 // parity(HiLo) -> parity(Lo^Hi)
4289 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4290 EVT NVT = Lo.getValueType();
4291 Lo =
4292 DAG.getNode(Opcode: ISD::PARITY, DL: dl, VT: NVT, Operand: DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Hi));
4293 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4294}
4295
4296void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
4297 SDValue &Lo, SDValue &Hi) {
4298 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4299 unsigned NBitWidth = NVT.getSizeInBits();
4300 auto Constant = cast<ConstantSDNode>(Val: N);
4301 const APInt &Cst = Constant->getAPIntValue();
4302 bool IsTarget = Constant->isTargetOpcode();
4303 bool IsOpaque = Constant->isOpaque();
4304 SDLoc dl(N);
4305 Lo = DAG.getConstant(Val: Cst.trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget, isOpaque: IsOpaque);
4306 Hi = DAG.getConstant(Val: Cst.lshr(shiftAmt: NBitWidth).trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget,
4307 isOpaque: IsOpaque);
4308}
4309
4310void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4311 SDLoc dl(N);
4312
4313 SDValue N0 = N->getOperand(Num: 0);
4314 GetExpandedInteger(Op: N0, Lo, Hi);
4315 EVT NVT = Lo.getValueType();
4316
4317 // If the upper half is all sign bits, then we can perform the ABS on the
4318 // lower half and zero-extend. We could use ISD::ABS_MIN_POISON here if
4319 // DAG.ComputeNumSignBits(N0) is larger than NVT.getScalarSizeInBits() + 1.
4320 unsigned NumSignBits = DAG.ComputeNumSignBits(Op: N0);
4321 if (NumSignBits > NVT.getScalarSizeInBits()) {
4322 unsigned AbsOpc = NumSignBits > NVT.getScalarSizeInBits() + 1
4323 ? ISD::ABS_MIN_POISON
4324 : ISD::ABS;
4325 Lo = DAG.getNode(Opcode: AbsOpc, DL: dl, VT: NVT, Operand: Lo);
4326 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4327 return;
4328 }
4329
4330 // If we have USUBO_CARRY, use the expanded form of the sra+xor+sub sequence
4331 // we use in LegalizeDAG. The SUB part of the expansion is based on
4332 // ExpandIntRes_ADDSUB which also uses USUBO_CARRY/USUBO after checking that
4333 // USUBO_CARRY is LegalOrCustom. Each of the pieces here can be further
4334 // expanded if needed. Shift expansion has a special case for filling with
4335 // sign bits so that we will only end up with one SRA.
4336 bool HasSubCarry = TLI.isOperationLegalOrCustom(
4337 Op: ISD::USUBO_CARRY, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
4338 if (HasSubCarry) {
4339 SDValue Sign = DAG.getNode(
4340 Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Hi,
4341 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - 1, VT: NVT, DL: dl));
4342 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
4343 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Sign);
4344 Hi = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Hi, N2: Sign);
4345 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: Lo, N2: Sign);
4346 Hi = DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: Hi, N2: Sign, N3: Lo.getValue(R: 1));
4347 return;
4348 }
4349
4350 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
4351 EVT VT = N->getValueType(ResNo: 0);
4352 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT,
4353 N1: DAG.getConstant(Val: 0, DL: dl, VT), N2: N0);
4354 SDValue NegLo, NegHi;
4355 SplitInteger(Op: Neg, Lo&: NegLo, Hi&: NegHi);
4356
4357 SDValue HiIsNeg = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4358 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETLT);
4359 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegLo, RHS: Lo);
4360 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegHi, RHS: Hi);
4361}
4362
4363void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
4364 SDValue &Lo, SDValue &Hi) {
4365 SDLoc dl(N);
4366 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
4367 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4368 EVT NVT = Lo.getValueType();
4369
4370 SDValue HiNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4371 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4372
4373 SDValue LoLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Lo);
4374 SDValue HiLZ = DAG.getNode(Opcode: ISD::CTLZ_ZERO_POISON, DL: dl, VT: NVT, Operand: Hi);
4375
4376 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiNotZero, LHS: HiLZ,
4377 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoLZ,
4378 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4379 VT: NVT)));
4380 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4381}
4382
4383void DAGTypeLegalizer::ExpandIntRes_CTLS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4384 SDLoc dl(N);
4385 // ctls(HiLo) -> if (IsAllSignBits = (ctls(Hi) == BW-1)) then
4386 // BW-1 + clz(IsNegative = (Hi < 0) ? ~Lo : Lo)
4387 // else ctls(Hi)
4388 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4389 EVT NVT = Lo.getValueType();
4390 unsigned NVTBits = NVT.getScalarSizeInBits();
4391
4392 SDValue Constant0 = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4393 SDValue ConstantBWM1 = DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: NVT);
4394
4395 SDValue HiCTLS = DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Hi);
4396 SDValue IsAllSignBits = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: HiCTLS,
4397 RHS: ConstantBWM1, Cond: ISD::SETEQ);
4398 SDValue IsNegative =
4399 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi, RHS: Constant0, Cond: ISD::SETLT);
4400 SDValue AdjustedLo =
4401 DAG.getSelect(DL: dl, VT: NVT, Cond: IsNegative, LHS: DAG.getNOT(DL: dl, Val: Lo, VT: NVT), RHS: Lo);
4402 SDValue LoCLZ = DAG.getNode(Opcode: ISD::CTLZ, DL: dl, VT: NVT, Operand: AdjustedLo);
4403 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: IsAllSignBits,
4404 LHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoCLZ, N2: ConstantBWM1),
4405 RHS: HiCTLS);
4406 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4407}
4408
4409void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
4410 SDValue Result = TLI.expandABD(N, DAG);
4411 SplitInteger(Op: Result, Lo, Hi);
4412}
4413
4414void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
4415 SDValue Op = N->getOperand(Num: 0);
4416 EVT VT = N->getValueType(ResNo: 0);
4417 SDLoc DL(N);
4418
4419 if (TLI.getOperationAction(Op: ISD::CTPOP, VT) == TargetLoweringBase::LibCall) {
4420 RTLIB::Libcall LC = RTLIB::getCTPOP(VT);
4421 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
4422 "LibCall explicitly requested, but not available");
4423
4424 if (RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
4425 TargetLowering::MakeLibCallOptions CallOptions;
4426 EVT IntVT =
4427 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
4428 SDValue Res =
4429 TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: IntVT, Ops: Op, CallOptions, dl: DL).first;
4430 SplitInteger(Op: DAG.getSExtOrTrunc(Op: Res, DL, VT), Lo, Hi);
4431 return;
4432 }
4433
4434 // If the function is not available, fall back on the expansion.
4435 }
4436
4437 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
4438 GetExpandedInteger(Op, Lo, Hi);
4439 EVT NVT = Lo.getValueType();
4440 Lo = DAG.getNode(Opcode: ISD::ADD, DL, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Lo),
4441 N2: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Hi));
4442 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
4443}
4444
4445void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
4446 SDValue &Lo, SDValue &Hi) {
4447 SDLoc dl(N);
4448 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
4449 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4450 EVT NVT = Lo.getValueType();
4451
4452 SDValue LoNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
4453 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4454
4455 SDValue LoLZ = DAG.getNode(Opcode: ISD::CTTZ_ZERO_POISON, DL: dl, VT: NVT, Operand: Lo);
4456 SDValue HiLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Hi);
4457
4458 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: LoNotZero, LHS: LoLZ,
4459 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: HiLZ,
4460 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4461 VT: NVT)));
4462 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4463}
4464
4465void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo,
4466 SDValue &Hi) {
4467 SDLoc dl(N);
4468 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4469 unsigned NBitWidth = NVT.getSizeInBits();
4470
4471 Lo = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
4472 SDValue Chain = Lo.getValue(R: 1);
4473 // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING
4474 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4475 N2: DAG.getShiftAmountConstant(Val: NBitWidth - 1, VT: NVT, DL: dl));
4476
4477 // Legalize the chain result - switch anything that used the old chain to
4478 // use the new one.
4479 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
4480}
4481
4482// Helper for producing an FP_EXTEND/STRICT_FP_EXTEND of Op.
4483static SDValue fpExtendHelper(SDValue Op, SDValue &Chain, bool IsStrict, EVT VT,
4484 SDLoc DL, SelectionDAG &DAG) {
4485 if (IsStrict) {
4486 Op = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL, ResultTys: {VT, MVT::Other}, Ops: {Chain, Op});
4487 Chain = Op.getValue(R: 1);
4488 return Op;
4489 }
4490 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT, Operand: Op);
4491}
4492
4493void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
4494 SDValue &Hi) {
4495 SDLoc dl(N);
4496 EVT VT = N->getValueType(ResNo: 0);
4497
4498 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
4499 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
4500 bool IsStrict = N->isStrictFPOpcode();
4501 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4502 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4503
4504 // If the input is bf16 or needs to be soft promoted, extend to f32.
4505 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf ||
4506 Op.getValueType() == MVT::bf16) {
4507 Op = fpExtendHelper(Op, Chain, IsStrict, VT: MVT::f32, DL: dl, DAG);
4508 }
4509
4510 // NOTE: We need a variable that lives across makeLibCall so
4511 // CallOptions.setTypeListBeforeSoften can save a reference to it.
4512 EVT OpVT = Op.getValueType();
4513
4514 RTLIB::Libcall LC =
4515 IsSigned ? RTLIB::getFPTOSINT(OpVT, RetVT: VT) : RTLIB::getFPTOUINT(OpVT, RetVT: VT);
4516 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
4517 TargetLowering::MakeLibCallOptions CallOptions;
4518 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftenFloat)
4519 CallOptions.setTypeListBeforeSoften(OpsVT: OpVT, RetVT: VT);
4520 else
4521 CallOptions.setIsSigned(true); // FIXME: Is this needed?
4522 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op,
4523 CallOptions, dl, Chain);
4524 SplitInteger(Op: Tmp.first, Lo, Hi);
4525
4526 if (IsStrict)
4527 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4528}
4529
4530void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
4531 SDValue &Hi) {
4532 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
4533 SplitInteger(Op: Res, Lo, Hi);
4534}
4535
4536void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo,
4537 SDValue &Hi) {
4538 SDLoc dl(N);
4539 bool IsStrict = N->isStrictFPOpcode();
4540 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4541 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4542
4543 EVT VT = Op.getValueType();
4544
4545 if (VT == MVT::f16) {
4546 // Extend to f32.
4547 VT = MVT::f32;
4548 Op = fpExtendHelper(Op, Chain, IsStrict, VT, DL: dl, DAG);
4549 }
4550
4551 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4552 if (N->getOpcode() == ISD::LROUND ||
4553 N->getOpcode() == ISD::STRICT_LROUND) {
4554 LC = RTLIB::getLROUND(VT);
4555 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lround input type!");
4556 } else if (N->getOpcode() == ISD::LRINT ||
4557 N->getOpcode() == ISD::STRICT_LRINT) {
4558 LC = RTLIB::getLRINT(RetVT: VT);
4559 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lrint input type!");
4560 } else if (N->getOpcode() == ISD::LLROUND ||
4561 N->getOpcode() == ISD::STRICT_LLROUND) {
4562 LC = RTLIB::getLLROUND(VT);
4563 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
4564 } else if (N->getOpcode() == ISD::LLRINT ||
4565 N->getOpcode() == ISD::STRICT_LLRINT) {
4566 LC = RTLIB::getLLRINT(RetVT: VT);
4567 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
4568 } else
4569 llvm_unreachable("Unexpected opcode!");
4570
4571 EVT RetVT = N->getValueType(ResNo: 0);
4572
4573 TargetLowering::MakeLibCallOptions CallOptions;
4574 CallOptions.setIsSigned(true);
4575 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
4576 Ops: Op, CallOptions, dl,
4577 Chain);
4578 SplitInteger(Op: Tmp.first, Lo, Hi);
4579
4580 if (N->isStrictFPOpcode())
4581 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4582}
4583
4584void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
4585 SDValue &Lo, SDValue &Hi) {
4586 assert(!N->isAtomic() && "Should have been a ATOMIC_LOAD?");
4587
4588 if (ISD::isNormalLoad(N)) {
4589 ExpandRes_NormalLoad(N, Lo, Hi);
4590 return;
4591 }
4592
4593 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
4594
4595 EVT VT = N->getValueType(ResNo: 0);
4596 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4597 SDValue Ch = N->getChain();
4598 SDValue Ptr = N->getBasePtr();
4599 ISD::LoadExtType ExtType = N->getExtensionType();
4600 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4601 AAMDNodes AAInfo = N->getAAInfo();
4602 SDLoc dl(N);
4603
4604 assert(NVT.isByteSized() && "Expanded type not byte sized!");
4605
4606 if (N->getMemoryVT().bitsLE(VT: NVT)) {
4607 EVT MemVT = N->getMemoryVT();
4608
4609 Lo = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), MemVT,
4610 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4611
4612 // Remember the chain.
4613 Ch = Lo.getValue(R: 1);
4614
4615 if (ExtType == ISD::SEXTLOAD) {
4616 // The high part is obtained by SRA'ing all but one of the bits of the
4617 // lo part.
4618 unsigned LoSize = Lo.getValueSizeInBits();
4619 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4620 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
4621 } else if (ExtType == ISD::ZEXTLOAD) {
4622 // The high part is just a zero.
4623 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4624 } else {
4625 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
4626 // The high part is undefined.
4627 Hi = DAG.getUNDEF(VT: NVT);
4628 }
4629 } else if (DAG.getDataLayout().isLittleEndian()) {
4630 // Little-endian - low bits are at low addresses.
4631 Lo = DAG.getLoad(VT: NVT, dl, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
4632 MMOFlags, AAInfo);
4633
4634 unsigned ExcessBits =
4635 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4636 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
4637
4638 // Increment the pointer to the other half.
4639 unsigned IncrementSize = NVT.getSizeInBits()/8;
4640 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4641 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr,
4642 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize), MemVT: NEVT,
4643 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4644
4645 // Build a factor node to remember that this load is independent of the
4646 // other one.
4647 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4648 N2: Hi.getValue(R: 1));
4649 } else {
4650 // Big-endian - high bits are at low addresses. Favor aligned loads at
4651 // the cost of some bit-fiddling.
4652 EVT MemVT = N->getMemoryVT();
4653 unsigned EBytes = MemVT.getStoreSize();
4654 unsigned IncrementSize = NVT.getSizeInBits()/8;
4655 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4656
4657 // Load both the high bits and maybe some of the low bits.
4658 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(),
4659 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(),
4660 BitWidth: MemVT.getSizeInBits() - ExcessBits),
4661 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4662
4663 // Increment the pointer to the other half.
4664 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4665 // Load the rest of the low bits.
4666 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: NVT, Chain: Ch, Ptr,
4667 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
4668 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
4669 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4670
4671 // Build a factor node to remember that this load is independent of the
4672 // other one.
4673 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4674 N2: Hi.getValue(R: 1));
4675
4676 if (ExcessBits < NVT.getSizeInBits()) {
4677 // Transfer low bits from the bottom of Hi to the top of Lo.
4678 Lo = DAG.getNode(
4679 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Lo,
4680 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
4681 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
4682 // Move high bits to the right position in Hi.
4683 Hi = DAG.getNode(Opcode: ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
4684 N1: Hi,
4685 N2: DAG.getShiftAmountConstant(
4686 Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
4687 }
4688 }
4689
4690 // Legalize the chain result - switch anything that used the old chain to
4691 // use the new one.
4692 ReplaceValueWith(From: SDValue(N, 1), To: Ch);
4693}
4694
4695void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
4696 SDValue &Lo, SDValue &Hi) {
4697 SDLoc dl(N);
4698 SDValue LL, LH, RL, RH;
4699 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4700 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4701
4702 SDNodeFlags Flags;
4703 if (N->getOpcode() == ISD::OR)
4704 Flags.setDisjoint(N->getFlags().hasDisjoint());
4705
4706 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LL, N2: RL, Flags);
4707 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LH, N2: RH, Flags);
4708}
4709
4710void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
4711 SDValue &Lo, SDValue &Hi) {
4712 EVT VT = N->getValueType(ResNo: 0);
4713 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4714 SDLoc dl(N);
4715
4716 SDValue LL, LH, RL, RH;
4717 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4718 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4719
4720 if (TLI.expandMUL(N, Lo, Hi, HiLoVT: NVT, DAG,
4721 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4722 LL, LH, RL, RH))
4723 return;
4724
4725 // If nothing else, we can make a libcall.
4726 RTLIB::Libcall LC = RTLIB::getMUL(VT);
4727 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
4728 if (LCImpl == RTLIB::Unsupported) {
4729 // Perform a wide multiplication where the wide type is the original VT and
4730 // the 4 parts are the split arguments.
4731 TLI.forceExpandMultiply(DAG, dl, /*Signed=*/false, Lo, Hi, LHS: LL, RHS: RL, HiLHS: LH, HiRHS: RH);
4732 return;
4733 }
4734
4735 // Note that we don't need to do a wide MUL here since we don't care about the
4736 // upper half of the result if it exceeds VT.
4737 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4738 TargetLowering::MakeLibCallOptions CallOptions;
4739 CallOptions.setIsSigned(true);
4740 SplitInteger(Op: TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
4741 Hi);
4742}
4743
4744void DAGTypeLegalizer::ExpandIntRes_READCOUNTER(SDNode *N, SDValue &Lo,
4745 SDValue &Hi) {
4746 SDLoc DL(N);
4747 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4748 SDVTList VTs = DAG.getVTList(VT1: NVT, VT2: NVT, VT3: MVT::Other);
4749 SDValue R = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N: N->getOperand(Num: 0));
4750 Lo = R.getValue(R: 0);
4751 Hi = R.getValue(R: 1);
4752 ReplaceValueWith(From: SDValue(N, 1), To: R.getValue(R: 2));
4753}
4754
4755void DAGTypeLegalizer::ExpandIntRes_AVG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4756 SDValue Result = TLI.expandAVG(N, DAG);
4757 SplitInteger(Op: Result, Lo, Hi);
4758}
4759
4760void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
4761 SDValue &Hi) {
4762 SDValue Result = TLI.expandAddSubSat(Node: N, DAG);
4763 SplitInteger(Op: Result, Lo, Hi);
4764}
4765
4766void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
4767 SDValue &Hi) {
4768 SDValue Result = TLI.expandShlSat(Node: N, DAG);
4769 SplitInteger(Op: Result, Lo, Hi);
4770}
4771
4772/// This performs an expansion of the integer result for a fixed point
4773/// multiplication. The default expansion performs rounding down towards
4774/// negative infinity, though targets that do care about rounding should specify
4775/// a target hook for rounding and provide their own expansion or lowering of
4776/// fixed point multiplication to be consistent with rounding.
4777void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
4778 SDValue &Hi) {
4779 SDLoc dl(N);
4780 EVT VT = N->getValueType(ResNo: 0);
4781 unsigned VTSize = VT.getScalarSizeInBits();
4782 SDValue LHS = N->getOperand(Num: 0);
4783 SDValue RHS = N->getOperand(Num: 1);
4784 uint64_t Scale = N->getConstantOperandVal(Num: 2);
4785 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
4786 N->getOpcode() == ISD::UMULFIXSAT);
4787 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
4788 N->getOpcode() == ISD::SMULFIXSAT);
4789
4790 // Handle special case when scale is equal to zero.
4791 if (!Scale) {
4792 SDValue Result;
4793 if (!Saturating) {
4794 Result = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS);
4795 } else {
4796 EVT BoolVT = getSetCCResultType(VT);
4797 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
4798 Result = DAG.getNode(Opcode: MulOp, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: BoolVT), N1: LHS, N2: RHS);
4799 SDValue Product = Result.getValue(R: 0);
4800 SDValue Overflow = Result.getValue(R: 1);
4801 if (Signed) {
4802 APInt MinVal = APInt::getSignedMinValue(numBits: VTSize);
4803 APInt MaxVal = APInt::getSignedMaxValue(numBits: VTSize);
4804 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT);
4805 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4806 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
4807 // Xor the inputs, if resulting sign bit is 0 the product will be
4808 // positive, else negative.
4809 SDValue Xor = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4810 SDValue ProdNeg = DAG.getSetCC(DL: dl, VT: BoolVT, LHS: Xor, RHS: Zero, Cond: ISD::SETLT);
4811 Result = DAG.getSelect(DL: dl, VT, Cond: ProdNeg, LHS: SatMin, RHS: SatMax);
4812 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: Result, RHS: Product);
4813 } else {
4814 // For unsigned multiplication, we only need to check the max since we
4815 // can't really overflow towards zero.
4816 APInt MaxVal = APInt::getMaxValue(numBits: VTSize);
4817 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4818 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: SatMax, RHS: Product);
4819 }
4820 }
4821 SplitInteger(Op: Result, Lo, Hi);
4822 return;
4823 }
4824
4825 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
4826 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
4827 assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
4828
4829 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4830 SDValue LL, LH, RL, RH;
4831 GetExpandedInteger(Op: LHS, Lo&: LL, Hi&: LH);
4832 GetExpandedInteger(Op: RHS, Lo&: RL, Hi&: RH);
4833 SmallVector<SDValue, 4> Result;
4834
4835 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
4836 if (!TLI.expandMUL_LOHI(Opcode: LoHiOp, VT, dl, LHS, RHS, Result, HiLoVT: NVT, DAG,
4837 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4838 LL, LH, RL, RH)) {
4839 Result.clear();
4840 Result.resize(N: 4);
4841
4842 SDValue LoTmp, HiTmp;
4843 TLI.forceExpandWideMUL(DAG, dl, Signed, LHS, RHS, Lo&: LoTmp, Hi&: HiTmp);
4844 SplitInteger(Op: LoTmp, Lo&: Result[0], Hi&: Result[1]);
4845 SplitInteger(Op: HiTmp, Lo&: Result[2], Hi&: Result[3]);
4846 }
4847 assert(Result.size() == 4 && "Unexpected number of partlets in the result");
4848
4849 unsigned NVTSize = NVT.getScalarSizeInBits();
4850 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
4851 "the size of the current value type");
4852
4853 // After getting the multiplication result in 4 parts, we need to perform a
4854 // shift right by the amount of the scale to get the result in that scale.
4855 //
4856 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
4857 // 128 bits that are cut into 4 32-bit parts:
4858 //
4859 // HH HL LH LL
4860 // |---32---|---32---|---32---|---32---|
4861 // 128 96 64 32 0
4862 //
4863 // |------VTSize-----|
4864 //
4865 // |NVTSize-|
4866 //
4867 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
4868 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
4869 // amount and get Lo and Hi using two funnel shifts. Or for the special case
4870 // when Scale is a multiple of NVTSize we can just pick the result without
4871 // shifting.
4872 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
4873 if (Scale % NVTSize) {
4874 SDValue ShiftAmount = DAG.getShiftAmountConstant(Val: Scale % NVTSize, VT: NVT, DL: dl);
4875 Lo = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 1], N2: Result[Part0],
4876 N3: ShiftAmount);
4877 Hi = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 2], N2: Result[Part0 + 1],
4878 N3: ShiftAmount);
4879 } else {
4880 Lo = Result[Part0];
4881 Hi = Result[Part0 + 1];
4882 }
4883
4884 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
4885 if (!Saturating)
4886 return;
4887
4888 // Can not overflow when there is no integer part.
4889 if (Scale == VTSize)
4890 return;
4891
4892 // To handle saturation we must check for overflow in the multiplication.
4893 //
4894 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
4895 // aren't all zeroes.
4896 //
4897 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
4898 // aren't all ones or all zeroes.
4899 //
4900 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
4901 // highest bit of HH determines saturation direction in the event of signed
4902 // saturation.
4903
4904 SDValue ResultHL = Result[2];
4905 SDValue ResultHH = Result[3];
4906
4907 SDValue SatMax, SatMin;
4908 SDValue NVTZero = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4909 SDValue NVTNeg1 = DAG.getAllOnesConstant(DL: dl, VT: NVT);
4910 EVT BoolNVT = getSetCCResultType(VT: NVT);
4911
4912 if (!Signed) {
4913 if (Scale < NVTSize) {
4914 // Overflow happened if ((HH | (HL >> Scale)) != 0).
4915 SDValue HLAdjusted =
4916 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4917 N2: DAG.getShiftAmountConstant(Val: Scale, VT: NVT, DL: dl));
4918 SDValue Tmp = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: HLAdjusted, N2: ResultHH);
4919 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: Tmp, RHS: NVTZero, Cond: ISD::SETNE);
4920 } else if (Scale == NVTSize) {
4921 // Overflow happened if (HH != 0).
4922 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETNE);
4923 } else if (Scale < VTSize) {
4924 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
4925 SDValue HLAdjusted =
4926 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4927 N2: DAG.getShiftAmountConstant(Val: Scale - NVTSize, VT: NVT, DL: dl));
4928 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: HLAdjusted, RHS: NVTZero, Cond: ISD::SETNE);
4929 } else
4930 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
4931 "(and saturation can't happen with Scale==VTSize).");
4932
4933 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Hi);
4934 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Lo);
4935 return;
4936 }
4937
4938 if (Scale < NVTSize) {
4939 // The number of overflow bits we can check are VTSize - Scale + 1 (we
4940 // include the sign bit). If these top bits are > 0, then we overflowed past
4941 // the max value. If these top bits are < -1, then we overflowed past the
4942 // min value. Otherwise, we did not overflow.
4943 unsigned OverflowBits = VTSize - Scale + 1;
4944 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
4945 "Extent of overflow bits must start within HL");
4946 SDValue HLHiMask = DAG.getConstant(
4947 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits - NVTSize), DL: dl, VT: NVT);
4948 SDValue HLLoMask = DAG.getConstant(
4949 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: VTSize - OverflowBits), DL: dl, VT: NVT);
4950 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
4951 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4952 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4953 SDValue HLUGT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLLoMask, Cond: ISD::SETUGT);
4954 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4955 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLUGT));
4956 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
4957 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4958 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4959 SDValue HLULT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLHiMask, Cond: ISD::SETULT);
4960 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4961 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLULT));
4962 } else if (Scale == NVTSize) {
4963 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
4964 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4965 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4966 SDValue HLNeg = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETLT);
4967 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4968 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLNeg));
4969 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
4970 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4971 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4972 SDValue HLPos = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETGE);
4973 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4974 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLPos));
4975 } else if (Scale < VTSize) {
4976 // This is similar to the case when we saturate if Scale < NVTSize, but we
4977 // only need to check HH.
4978 unsigned OverflowBits = VTSize - Scale + 1;
4979 SDValue HHHiMask = DAG.getConstant(
4980 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits), DL: dl, VT: NVT);
4981 SDValue HHLoMask = DAG.getConstant(
4982 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: NVTSize - OverflowBits), DL: dl, VT: NVT);
4983 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHLoMask, Cond: ISD::SETGT);
4984 SatMin = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHHiMask, Cond: ISD::SETLT);
4985 } else
4986 llvm_unreachable("Illegal scale for signed fixed point mul.");
4987
4988 // Saturate to signed maximum.
4989 APInt MaxHi = APInt::getSignedMaxValue(numBits: NVTSize);
4990 APInt MaxLo = APInt::getAllOnes(numBits: NVTSize);
4991 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxHi, DL: dl, VT: NVT), RHS: Hi);
4992 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxLo, DL: dl, VT: NVT), RHS: Lo);
4993 // Saturate to signed minimum.
4994 APInt MinHi = APInt::getSignedMinValue(numBits: NVTSize);
4995 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: DAG.getConstant(Val: MinHi, DL: dl, VT: NVT), RHS: Hi);
4996 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: NVTZero, RHS: Lo);
4997}
4998
4999void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
5000 SDValue &Hi) {
5001 SDLoc dl(N);
5002 // Try expanding in the existing type first.
5003 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: N->getOperand(Num: 0),
5004 RHS: N->getOperand(Num: 1),
5005 Scale: N->getConstantOperandVal(Num: 2), DAG);
5006
5007 if (!Res)
5008 Res = earlyExpandDIVFIX(N, LHS: N->getOperand(Num: 0), RHS: N->getOperand(Num: 1),
5009 Scale: N->getConstantOperandVal(Num: 2), TLI, DAG);
5010 SplitInteger(Op: Res, Lo, Hi);
5011}
5012
5013void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
5014 SDValue &Lo, SDValue &Hi) {
5015 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
5016 "Node has unexpected Opcode");
5017 SDValue LHS = Node->getOperand(Num: 0);
5018 SDValue RHS = Node->getOperand(Num: 1);
5019 SDLoc dl(Node);
5020
5021 SDValue Ovf;
5022
5023 bool IsAdd = Node->getOpcode() == ISD::SADDO;
5024 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
5025
5026 bool HasCarryOp = TLI.isOperationLegalOrCustom(
5027 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
5028
5029 if (HasCarryOp) {
5030 // Expand the subcomponents.
5031 SDValue LHSL, LHSH, RHSL, RHSH;
5032 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
5033 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
5034 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: Node->getValueType(ResNo: 1));
5035
5036 Lo = DAG.getNode(Opcode: IsAdd ? ISD::UADDO : ISD::USUBO, DL: dl, VTList, Ops: {LHSL, RHSL});
5037 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
5038
5039 Ovf = Hi.getValue(R: 1);
5040 } else {
5041 // Expand the result by simply replacing it with the equivalent
5042 // non-overflow-checking operation.
5043 SDValue Sum = DAG.getNode(Opcode: Node->getOpcode() == ISD::SADDO ?
5044 ISD::ADD : ISD::SUB, DL: dl, VT: LHS.getValueType(),
5045 N1: LHS, N2: RHS);
5046 SplitInteger(Op: Sum, Lo, Hi);
5047
5048 // Compute the overflow.
5049 //
5050 // LHSSign -> LHS < 0
5051 // RHSSign -> RHS < 0
5052 // SumSign -> Sum < 0
5053 //
5054 // Add:
5055 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
5056 // Sub:
5057 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
5058 //
5059 // To get better codegen we can rewrite this by doing bitwise math on
5060 // the integers and extract the final sign bit at the end. So the
5061 // above becomes:
5062 //
5063 // Add:
5064 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
5065 // Sub:
5066 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
5067 //
5068 // NOTE: This is different than the expansion we do in expandSADDSUBO
5069 // because it is more costly to implement the same overflow predicate with
5070 // SETCC nodes when the integers are split.
5071 EVT VT = LHS.getValueType();
5072 SDValue SignsMatch = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
5073 if (IsAdd)
5074 SignsMatch = DAG.getNOT(DL: dl, Val: SignsMatch, VT);
5075
5076 SDValue SumSignNE = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: Sum);
5077 Ovf = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: SignsMatch, N2: SumSignNE);
5078 EVT OType = Node->getValueType(ResNo: 1);
5079 Ovf = DAG.getSetCC(DL: dl, VT: OType, LHS: Ovf, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETLT);
5080 }
5081
5082 // Use the calculated overflow everywhere.
5083 ReplaceValueWith(From: SDValue(Node, 1), To: Ovf);
5084}
5085
5086void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
5087 SDValue &Lo, SDValue &Hi) {
5088 EVT VT = N->getValueType(ResNo: 0);
5089 SDLoc dl(N);
5090 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5091
5092 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5093 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5094 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5095 return;
5096 }
5097
5098 RTLIB::Libcall LC = RTLIB::getSDIV(VT);
5099 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
5100
5101 TargetLowering::MakeLibCallOptions CallOptions;
5102 CallOptions.setIsSigned(true);
5103 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5104}
5105
5106void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
5107 SDValue &Hi) {
5108 SDLoc dl(N);
5109 SDValue Shiftee = N->getOperand(Num: 0);
5110 EVT VT = Shiftee.getValueType();
5111 SDValue ShAmt = N->getOperand(Num: 1);
5112 EVT ShAmtVT = ShAmt.getValueType();
5113
5114 EVT LoadVT = VT;
5115 do {
5116 LoadVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: LoadVT);
5117 } while (!TLI.isTypeLegal(VT: LoadVT));
5118
5119 const unsigned ShiftUnitInBits = LoadVT.getStoreSizeInBits();
5120 assert(ShiftUnitInBits <= VT.getScalarSizeInBits());
5121 assert(isPowerOf2_32(ShiftUnitInBits) &&
5122 "Shifting unit is not a a power of two!");
5123
5124 const bool IsOneStepShift =
5125 DAG.computeKnownBits(Op: ShAmt).countMinTrailingZeros() >=
5126 Log2_32(Value: ShiftUnitInBits);
5127
5128 // If we can't do it as one step, we'll have two uses of shift amount,
5129 // and thus must freeze it.
5130 if (!IsOneStepShift)
5131 ShAmt = DAG.getFreeze(V: ShAmt);
5132
5133 unsigned VTBitWidth = VT.getScalarSizeInBits();
5134 assert(VTBitWidth % 8 == 0 && "Shifting a not byte multiple value?");
5135 unsigned VTByteWidth = VTBitWidth / 8;
5136 assert(isPowerOf2_32(VTByteWidth) &&
5137 "Shiftee type size is not a power of two!");
5138 unsigned StackSlotByteWidth = 2 * VTByteWidth;
5139 unsigned StackSlotBitWidth = 8 * StackSlotByteWidth;
5140 EVT StackSlotVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StackSlotBitWidth);
5141
5142 // Get a temporary stack slot 2x the width of our VT.
5143 // FIXME: reuse stack slots?
5144 Align StackAlign = DAG.getReducedAlign(VT: StackSlotVT, /*UseABI=*/false);
5145 SDValue StackPtr =
5146 DAG.CreateStackTemporary(Bytes: StackSlotVT.getStoreSize(), Alignment: StackAlign);
5147 EVT PtrTy = StackPtr.getValueType();
5148 SDValue Ch = DAG.getEntryNode();
5149
5150 MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
5151 MF&: DAG.getMachineFunction(),
5152 FI: cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex());
5153
5154 // Extend the value, that is being shifted, to the entire stack slot's width.
5155 SDValue Init;
5156 if (N->getOpcode() != ISD::SHL) {
5157 unsigned WideningOpc =
5158 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5159 Init = DAG.getNode(Opcode: WideningOpc, DL: dl, VT: StackSlotVT, Operand: Shiftee);
5160 } else {
5161 // For left-shifts, pad the Shiftee's LSB with zeros to twice it's width.
5162 SDValue AllZeros = DAG.getConstant(Val: 0, DL: dl, VT);
5163 Init = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: StackSlotVT, N1: AllZeros, N2: Shiftee);
5164 }
5165 // And spill it into the stack slot.
5166 Ch = DAG.getStore(Chain: Ch, dl, Val: Init, Ptr: StackPtr, PtrInfo: StackPtrInfo, Alignment: StackAlign);
5167
5168 // Now, compute the full-byte offset into stack slot from where we can load.
5169 // We have shift amount, which is in bits. Offset should point to an aligned
5170 // address.
5171 SDNodeFlags Flags;
5172 Flags.setExact(IsOneStepShift);
5173 SDValue SrlTmp = DAG.getNode(
5174 Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: ShAmt,
5175 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT), Flags);
5176 SDValue BitOffset =
5177 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: ShAmtVT, N1: SrlTmp,
5178 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT));
5179
5180 SDValue ByteOffset =
5181 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: BitOffset,
5182 N2: DAG.getConstant(Val: 3, DL: dl, VT: ShAmtVT), Flags: SDNodeFlags::Exact);
5183 // And clamp it, because OOB load is an immediate UB,
5184 // while shift overflow would have *just* been poison.
5185 ByteOffset = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ByteOffset,
5186 N2: DAG.getConstant(Val: VTByteWidth - 1, DL: dl, VT: ShAmtVT));
5187 // We have exactly two strategies on indexing into stack slot here:
5188 // 1. upwards starting from the beginning of the slot
5189 // 2. downwards starting from the middle of the slot
5190 // On little-endian machine, we pick 1. for right shifts and 2. for left-shift
5191 // and vice versa on big-endian machine.
5192 bool WillIndexUpwards = N->getOpcode() != ISD::SHL;
5193 if (DAG.getDataLayout().isBigEndian())
5194 WillIndexUpwards = !WillIndexUpwards;
5195
5196 SDValue AdjStackPtr;
5197 if (WillIndexUpwards) {
5198 AdjStackPtr = StackPtr;
5199 } else {
5200 AdjStackPtr = DAG.getMemBasePlusOffset(
5201 Base: StackPtr, Offset: DAG.getConstant(Val: VTByteWidth, DL: dl, VT: PtrTy), DL: dl);
5202 ByteOffset = DAG.getNegative(Val: ByteOffset, DL: dl, VT: ShAmtVT);
5203 }
5204
5205 // Get the pointer somewhere into the stack slot from which we need to load.
5206 ByteOffset = DAG.getSExtOrTrunc(Op: ByteOffset, DL: dl, VT: PtrTy);
5207 AdjStackPtr = DAG.getMemBasePlusOffset(Base: AdjStackPtr, Offset: ByteOffset, DL: dl);
5208
5209 // And load it! While the load is not legal, legalizing it is obvious.
5210 SDValue Res =
5211 DAG.getLoad(VT, dl, Chain: Ch, Ptr: AdjStackPtr,
5212 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
5213 Alignment: commonAlignment(A: StackAlign, Offset: LoadVT.getStoreSize()));
5214
5215 // If we may still have a remaining bits to shift by, do so now.
5216 if (!IsOneStepShift) {
5217 SDValue ShAmtRem =
5218 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ShAmt,
5219 N2: DAG.getConstant(Val: ShiftUnitInBits - 1, DL: dl, VT: ShAmtVT));
5220 Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT, N1: Res, N2: ShAmtRem);
5221 }
5222
5223 // Finally, split the computed value.
5224 SplitInteger(Op: Res, Lo, Hi);
5225}
5226
5227void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
5228 SDValue &Lo, SDValue &Hi) {
5229 EVT VT = N->getValueType(ResNo: 0);
5230 unsigned Opc = N->getOpcode();
5231 SDLoc dl(N);
5232
5233 // If we can emit an efficient shift operation, do so now. Check to see if
5234 // the RHS is a constant.
5235 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1)))
5236 return ExpandShiftByConstant(N, Amt: CN->getAPIntValue(), Lo, Hi);
5237
5238 // If we can determine that the high bit of the shift is zero or one, even if
5239 // the low bits are variable, emit this shift in an optimized form.
5240 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
5241 return;
5242
5243 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
5244 unsigned PartsOpc;
5245 if (Opc == ISD::SHL) {
5246 PartsOpc = ISD::SHL_PARTS;
5247 } else if (Opc == ISD::SRL) {
5248 PartsOpc = ISD::SRL_PARTS;
5249 } else {
5250 assert(Opc == ISD::SRA && "Unknown shift!");
5251 PartsOpc = ISD::SRA_PARTS;
5252 }
5253
5254 // Next check to see if the target supports this SHL_PARTS operation or if it
5255 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
5256 // size, but create a libcall instead.
5257 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5258 TargetLowering::LegalizeAction Action = TLI.getOperationAction(Op: PartsOpc, VT: NVT);
5259 const bool LegalOrCustom =
5260 (Action == TargetLowering::Legal && TLI.isTypeLegal(VT: NVT)) ||
5261 Action == TargetLowering::Custom;
5262
5263 unsigned ExpansionFactor = 1;
5264 // That VT->NVT expansion is one step. But will we re-expand NVT?
5265 for (EVT TmpVT = NVT;;) {
5266 EVT NewTMPVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: TmpVT);
5267 if (NewTMPVT == TmpVT)
5268 break;
5269 TmpVT = NewTMPVT;
5270 ++ExpansionFactor;
5271 }
5272
5273 TargetLowering::ShiftLegalizationStrategy S =
5274 TLI.preferredShiftLegalizationStrategy(DAG, N, ExpansionFactor);
5275
5276 if (S == TargetLowering::ShiftLegalizationStrategy::ExpandThroughStack)
5277 return ExpandIntRes_ShiftThroughStack(N, Lo, Hi);
5278
5279 if (LegalOrCustom &&
5280 S != TargetLowering::ShiftLegalizationStrategy::LowerToLibcall) {
5281 // Expand the subcomponents.
5282 SDValue LHSL, LHSH;
5283 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
5284 EVT VT = LHSL.getValueType();
5285
5286 // If the shift amount operand is coming from a vector legalization it may
5287 // have an illegal type. Fix that first by casting the operand, otherwise
5288 // the new SHL_PARTS operation would need further legalization.
5289 SDValue ShiftOp = N->getOperand(Num: 1);
5290 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
5291 if (ShiftOp.getValueType() != ShiftTy)
5292 ShiftOp = DAG.getZExtOrTrunc(Op: ShiftOp, DL: dl, VT: ShiftTy);
5293
5294 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
5295 Lo = DAG.getNode(Opcode: PartsOpc, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5296 Hi = Lo.getValue(R: 1);
5297 return;
5298 }
5299
5300 // Otherwise, emit a libcall.
5301 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5302 bool isSigned;
5303 if (Opc == ISD::SHL) {
5304 isSigned = false; /*sign irrelevant*/
5305 LC = RTLIB::getSHL(VT);
5306 } else if (Opc == ISD::SRL) {
5307 isSigned = false;
5308 LC = RTLIB::getSRL(VT);
5309 } else {
5310 assert(Opc == ISD::SRA && "Unknown shift!");
5311 isSigned = true;
5312 LC = RTLIB::getSRA(VT);
5313 }
5314
5315 if (RTLIB::LibcallImpl LibcallImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
5316 EVT ShAmtTy =
5317 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
5318 SDValue ShAmt = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl, VT: ShAmtTy);
5319 SDValue Ops[2] = {N->getOperand(Num: 0), ShAmt};
5320 TargetLowering::MakeLibCallOptions CallOptions;
5321 CallOptions.setIsSigned(isSigned);
5322 SplitInteger(
5323 Op: TLI.makeLibCall(DAG, LibcallImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
5324 Hi);
5325 return;
5326 }
5327
5328 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
5329 llvm_unreachable("Unsupported shift!");
5330}
5331
5332void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
5333 SDValue &Lo, SDValue &Hi) {
5334 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5335 SDLoc dl(N);
5336 SDValue Op = N->getOperand(Num: 0);
5337 if (Op.getValueType().bitsLE(VT: NVT)) {
5338 // The low part is sign extension of the input (degenerates to a copy).
5339 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5340 // The high part is obtained by SRA'ing all but one of the bits of low part.
5341 unsigned LoSize = NVT.getSizeInBits();
5342 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
5343 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
5344 } else {
5345 // For example, extension of an i48 to an i64. The operand type necessarily
5346 // promotes to the result type, so will end up being expanded too.
5347 assert(getTypeAction(Op.getValueType()) ==
5348 TargetLowering::TypePromoteInteger &&
5349 "Only know how to promote this result!");
5350 SDValue Res = GetPromotedInteger(Op);
5351 assert(Res.getValueType() == N->getValueType(0) &&
5352 "Operand over promoted?");
5353 // Split the promoted operand. This will simplify when it is expanded.
5354 SplitInteger(Op: Res, Lo, Hi);
5355 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5356 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5357 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5358 BitWidth: ExcessBits)));
5359 }
5360}
5361
5362void DAGTypeLegalizer::
5363ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
5364 SDLoc dl(N);
5365 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5366 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
5367
5368 if (EVT.bitsLE(VT: Lo.getValueType())) {
5369 // sext_inreg the low part if needed.
5370 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Lo.getValueType(), N1: Lo,
5371 N2: N->getOperand(Num: 1));
5372
5373 // The high part gets the sign extension from the lo-part. This handles
5374 // things like sextinreg V:i64 from i8.
5375 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: Hi.getValueType(), N1: Lo,
5376 N2: DAG.getShiftAmountConstant(Val: Hi.getValueSizeInBits() - 1,
5377 VT: Hi.getValueType(), DL: dl));
5378 } else {
5379 // For example, extension of an i48 to an i64. Leave the low part alone,
5380 // sext_inreg the high part.
5381 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
5382 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5383 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5384 BitWidth: ExcessBits)));
5385 }
5386}
5387
5388void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
5389 SDValue &Lo, SDValue &Hi) {
5390 EVT VT = N->getValueType(ResNo: 0);
5391 SDLoc dl(N);
5392 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5393
5394 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5395 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5396 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5397 return;
5398 }
5399
5400 RTLIB::Libcall LC = RTLIB::getSREM(VT);
5401 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
5402
5403 TargetLowering::MakeLibCallOptions CallOptions;
5404 CallOptions.setIsSigned(true);
5405 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5406}
5407
5408void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
5409 SDValue &Lo, SDValue &Hi) {
5410 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5411 SDValue InOp = N->getOperand(Num: 0);
5412 EVT InVT = InOp.getValueType();
5413 SDLoc dl(N);
5414 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: InOp);
5415 Hi = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: InVT, N1: InOp,
5416 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits(), VT: InVT, DL: dl));
5417 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Hi);
5418}
5419
5420void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
5421 SDValue &Lo, SDValue &Hi) {
5422 EVT VT = N->getValueType(ResNo: 0);
5423 SDLoc dl(N);
5424
5425 if (N->getOpcode() == ISD::UMULO) {
5426 // This section expands the operation into the following sequence of
5427 // instructions. `iNh` here refers to a type which has half the bit width of
5428 // the type the original operation operated on.
5429 //
5430 // %0 = %LHS.HI != 0 && %RHS.HI != 0
5431 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
5432 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
5433 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
5434 // %4 = add iNh %1.0, %2.0 as iN
5435 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
5436 //
5437 // %lo = %3.LO
5438 // %hi = %5.0
5439 // %ovf = %0 || %1.1 || %2.1 || %5.1
5440 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
5441 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
5442 GetExpandedInteger(Op: LHS, Lo&: LHSLow, Hi&: LHSHigh);
5443 GetExpandedInteger(Op: RHS, Lo&: RHSLow, Hi&: RHSHigh);
5444 EVT HalfVT = LHSLow.getValueType();
5445 EVT BitVT = N->getValueType(ResNo: 1);
5446 SDVTList VTHalfWithO = DAG.getVTList(VT1: HalfVT, VT2: BitVT);
5447
5448 SDValue HalfZero = DAG.getConstant(Val: 0, DL: dl, VT: HalfVT);
5449 SDValue Overflow = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BitVT,
5450 N1: DAG.getSetCC(DL: dl, VT: BitVT, LHS: LHSHigh, RHS: HalfZero, Cond: ISD::SETNE),
5451 N2: DAG.getSetCC(DL: dl, VT: BitVT, LHS: RHSHigh, RHS: HalfZero, Cond: ISD::SETNE));
5452
5453 SDValue One = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: LHSHigh, N2: RHSLow);
5454 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: One.getValue(R: 1));
5455
5456 SDValue Two = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: RHSHigh, N2: LHSLow);
5457 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Two.getValue(R: 1));
5458
5459 SDValue HighSum = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: HalfVT, N1: One, N2: Two);
5460
5461 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
5462 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
5463 // operation recursively legalized?).
5464 //
5465 // Many backends understand this pattern and will convert into LOHI
5466 // themselves, if applicable.
5467 SDValue Three = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT,
5468 N1: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: LHSLow),
5469 N2: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: RHSLow));
5470 SplitInteger(Op: Three, Lo, Hi);
5471
5472 Hi = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList: VTHalfWithO, N1: Hi, N2: HighSum);
5473 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Hi.getValue(R: 1));
5474 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5475 return;
5476 }
5477
5478 Type *RetTy = VT.getTypeForEVT(Context&: *DAG.getContext());
5479 EVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
5480 Type *PtrTy = PtrVT.getTypeForEVT(Context&: *DAG.getContext());
5481
5482 // Replace this with a libcall that will check overflow.
5483 RTLIB::Libcall LC = RTLIB::getMULO(VT);
5484 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
5485
5486 // If we don't have the libcall or if the function we are compiling is the
5487 // implementation of the expected libcall (avoid inf-loop), expand inline.
5488 if (LCImpl == RTLIB::Unsupported ||
5489 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LCImpl) ==
5490 DAG.getMachineFunction().getName()) {
5491 // FIXME: This is not an optimal expansion, but better than crashing.
5492 SDValue MulLo, MulHi;
5493 TLI.forceExpandWideMUL(DAG, dl, /*Signed=*/true, LHS: N->getOperand(Num: 0),
5494 RHS: N->getOperand(Num: 1), Lo&: MulLo, Hi&: MulHi);
5495 SDValue SRA = DAG.getNode(
5496 Opcode: ISD::SRA, DL: dl, VT, N1: MulLo,
5497 N2: DAG.getShiftAmountConstant(Val: VT.getScalarSizeInBits() - 1, VT, DL: dl));
5498 SDValue Overflow =
5499 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: MulHi, RHS: SRA, Cond: ISD::SETNE);
5500 SplitInteger(Op: MulLo, Lo, Hi);
5501 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5502 return;
5503 }
5504
5505 SDValue Temp = DAG.CreateStackTemporary(VT: PtrVT);
5506 // Temporary for the overflow value, default it to zero.
5507 SDValue Chain =
5508 DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT), Ptr: Temp,
5509 PtrInfo: MachinePointerInfo());
5510
5511 TargetLowering::ArgListTy Args;
5512 for (const SDValue &Op : N->op_values()) {
5513 EVT ArgVT = Op.getValueType();
5514 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
5515 TargetLowering::ArgListEntry Entry(Op, ArgTy);
5516 Entry.IsSExt = true;
5517 Entry.IsZExt = false;
5518 Args.push_back(x: Entry);
5519 }
5520
5521 // Also pass the address of the overflow check.
5522 TargetLowering::ArgListEntry Entry(
5523 Temp, PointerType::getUnqual(C&: PtrTy->getContext()));
5524 Entry.IsSExt = true;
5525 Entry.IsZExt = false;
5526 Args.push_back(x: Entry);
5527
5528 SDValue Func = DAG.getExternalSymbol(LCImpl, VT: PtrVT);
5529
5530 TargetLowering::CallLoweringInfo CLI(DAG);
5531 CLI.setDebugLoc(dl)
5532 .setChain(Chain)
5533 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
5534 Target: Func, ArgsList: std::move(Args))
5535 .setSExtResult();
5536
5537 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
5538
5539 SplitInteger(Op: CallInfo.first, Lo, Hi);
5540 SDValue Temp2 =
5541 DAG.getLoad(VT: PtrVT, dl, Chain: CallInfo.second, Ptr: Temp, PtrInfo: MachinePointerInfo());
5542 SDValue Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Temp2,
5543 RHS: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT),
5544 Cond: ISD::SETNE);
5545 // Use the overflow from the libcall everywhere.
5546 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
5547}
5548
5549void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
5550 SDValue &Lo, SDValue &Hi) {
5551 EVT VT = N->getValueType(ResNo: 0);
5552 SDLoc dl(N);
5553 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5554
5555 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5556 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5557 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5558 return;
5559 }
5560
5561 // Try to expand UDIV by constant.
5562 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5563 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5564 // Only if the new type is legal.
5565 if (isTypeLegal(VT: NVT)) {
5566 SDValue InL, InH;
5567 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5568 SmallVector<SDValue> Result;
5569 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5570 Lo = Result[0];
5571 Hi = Result[1];
5572 return;
5573 }
5574 }
5575 }
5576
5577 RTLIB::Libcall LC = RTLIB::getUDIV(VT);
5578 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
5579
5580 TargetLowering::MakeLibCallOptions CallOptions;
5581 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5582}
5583
5584void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
5585 SDValue &Lo, SDValue &Hi) {
5586 EVT VT = N->getValueType(ResNo: 0);
5587 SDLoc dl(N);
5588 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5589
5590 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5591 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5592 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5593 return;
5594 }
5595
5596 // Try to expand UREM by constant.
5597 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5598 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5599 // Only if the new type is legal.
5600 if (isTypeLegal(VT: NVT)) {
5601 SDValue InL, InH;
5602 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5603 SmallVector<SDValue> Result;
5604 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5605 Lo = Result[0];
5606 Hi = Result[1];
5607 return;
5608 }
5609 }
5610 }
5611
5612 RTLIB::Libcall LC = RTLIB::getUREM(VT);
5613 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
5614
5615 TargetLowering::MakeLibCallOptions CallOptions;
5616 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5617}
5618
5619void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
5620 SDValue &Lo, SDValue &Hi) {
5621 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5622 SDLoc dl(N);
5623 SDValue Op = N->getOperand(Num: 0);
5624 if (Op.getValueType().bitsLE(VT: NVT)) {
5625 // The low part is zero extension of the input (degenerates to a copy).
5626 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5627 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // The high part is just a zero.
5628 } else {
5629 // For example, extension of an i48 to an i64. The operand type necessarily
5630 // promotes to the result type, so will end up being expanded too.
5631 assert(getTypeAction(Op.getValueType()) ==
5632 TargetLowering::TypePromoteInteger &&
5633 "Only know how to promote this result!");
5634 SDValue Res = GetPromotedInteger(Op);
5635 assert(Res.getValueType() == N->getValueType(0) &&
5636 "Operand over promoted?");
5637 // Split the promoted operand. This will simplify when it is expanded.
5638 SplitInteger(Op: Res, Lo, Hi);
5639 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5640 Hi = DAG.getZeroExtendInReg(Op: Hi, DL: dl,
5641 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
5642 BitWidth: ExcessBits));
5643 }
5644}
5645
5646void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
5647 SDValue &Lo, SDValue &Hi) {
5648 SDLoc dl(N);
5649 EVT VT = cast<AtomicSDNode>(Val: N)->getMemoryVT();
5650 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::i1, VT3: MVT::Other);
5651 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
5652 SDValue Swap = DAG.getAtomicCmpSwap(
5653 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
5654 MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(), VTs, Chain: N->getOperand(Num: 0),
5655 Ptr: N->getOperand(Num: 1), Cmp: Zero, Swp: Zero, MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5656
5657 ReplaceValueWith(From: SDValue(N, 0), To: Swap.getValue(R: 0));
5658 ReplaceValueWith(From: SDValue(N, 1), To: Swap.getValue(R: 2));
5659}
5660
5661void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
5662 SDValue &Lo, SDValue &Hi) {
5663 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
5664 // both halves independently.
5665 SDValue Res = TLI.expandVecReduce(Node: N, DAG);
5666 SplitInteger(Op: Res, Lo, Hi);
5667}
5668
5669void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
5670 SDValue &Lo, SDValue &Hi) {
5671 // Delegate to funnel-shift expansion.
5672 SDLoc DL(N);
5673 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR;
5674 SDValue Res = DAG.getNode(Opcode, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
5675 N2: N->getOperand(Num: 0), N3: N->getOperand(Num: 1));
5676 SplitInteger(Op: Res, Lo, Hi);
5677}
5678
5679void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
5680 SDValue &Hi) {
5681 // Values numbered from least significant to most significant.
5682 SDValue In1, In2, In3, In4;
5683 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: In3, Hi&: In4);
5684 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: In1, Hi&: In2);
5685 EVT HalfVT = In1.getValueType();
5686
5687 SDLoc DL(N);
5688 unsigned Opc = N->getOpcode();
5689 SDValue ShAmt = N->getOperand(Num: 2);
5690 EVT ShAmtVT = ShAmt.getValueType();
5691 EVT ShAmtCCVT = getSetCCResultType(VT: ShAmtVT);
5692
5693 // If the shift amount is at least half the bitwidth, swap the inputs.
5694 unsigned HalfVTBits = HalfVT.getScalarSizeInBits();
5695 SDValue AndNode = DAG.getNode(Opcode: ISD::AND, DL, VT: ShAmtVT, N1: ShAmt,
5696 N2: DAG.getConstant(Val: HalfVTBits, DL, VT: ShAmtVT));
5697 SDValue Cond =
5698 DAG.getSetCC(DL, VT: ShAmtCCVT, LHS: AndNode, RHS: DAG.getConstant(Val: 0, DL, VT: ShAmtVT),
5699 Cond: Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ);
5700
5701 // Expand to a pair of funnel shifts.
5702 EVT NewShAmtVT = TLI.getShiftAmountTy(LHSTy: HalfVT, DL: DAG.getDataLayout());
5703 SDValue NewShAmt = DAG.getAnyExtOrTrunc(Op: ShAmt, DL, VT: NewShAmtVT);
5704
5705 SDValue Select1 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In1, N3: In2);
5706 SDValue Select2 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In2, N3: In3);
5707 SDValue Select3 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In3, N3: In4);
5708 Lo = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select2, N2: Select1, N3: NewShAmt);
5709 Hi = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select3, N2: Select2, N3: NewShAmt);
5710}
5711
5712void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo, SDValue &Hi) {
5713 if (N->getOpcode() != ISD::CLMUL) {
5714 SDValue Res = TLI.expandCLMUL(N, DAG);
5715 return SplitInteger(Op: Res, Lo, Hi);
5716 }
5717
5718 SDValue LL, LH, RL, RH;
5719 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
5720 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
5721 EVT HalfVT = LL.getValueType();
5722 SDLoc DL(N);
5723
5724 // The low bits are a direct CLMUL of the the low bits.
5725 Lo = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RL);
5726
5727 // We compute two Hi-Lo cross-products, XOR them, and XOR it with the overflow
5728 // of the CLMUL of the low bits (given by CLMULH of the low bits) to yield the
5729 // final high bits.
5730 SDValue LoH = DAG.getNode(Opcode: ISD::CLMULH, DL, VT: HalfVT, N1: LL, N2: RL);
5731 SDValue HiLoCross1 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RH);
5732 SDValue HiLoCross2 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LH, N2: RL);
5733 SDValue HiLoCross = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: HiLoCross1, N2: HiLoCross2);
5734 Hi = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: LoH, N2: HiLoCross);
5735}
5736
5737void DAGTypeLegalizer::ExpandIntRes_PEXT(SDNode *N, SDValue &Lo, SDValue &Hi) {
5738 SDValue Res = TLI.expandPEXT(N, DAG);
5739 SplitInteger(Op: Res, Lo, Hi);
5740}
5741
5742void DAGTypeLegalizer::ExpandIntRes_PDEP(SDNode *N, SDValue &Lo, SDValue &Hi) {
5743 SDValue Res = TLI.expandPDEP(N, DAG);
5744 SplitInteger(Op: Res, Lo, Hi);
5745}
5746
5747void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
5748 SDValue &Hi) {
5749 EVT VT = N->getValueType(ResNo: 0);
5750 EVT HalfVT =
5751 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: N->getValueSizeInBits(ResNo: 0) / 2);
5752 SDLoc dl(N);
5753
5754 // We assume VSCALE(1) fits into a legal integer.
5755 APInt One(HalfVT.getSizeInBits(), 1);
5756 SDValue VScaleBase = DAG.getVScale(DL: dl, VT: HalfVT, MulImm: One);
5757 VScaleBase = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: VScaleBase);
5758 SDValue Res = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: VScaleBase, N2: N->getOperand(Num: 0));
5759 SplitInteger(Op: Res, Lo, Hi);
5760}
5761
5762void DAGTypeLegalizer::ExpandIntRes_READ_REGISTER(SDNode *N, SDValue &Lo,
5763 SDValue &Hi) {
5764 const Function &Fn = DAG.getMachineFunction().getFunction();
5765 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
5766 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
5767 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
5768 EVT LoVT, HiVT;
5769 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: N->getValueType(ResNo: 0));
5770 Lo = DAG.getPOISON(VT: LoVT);
5771 Hi = DAG.getPOISON(VT: HiVT);
5772}
5773
5774void DAGTypeLegalizer::ExpandIntRes_CTTZ_ELTS(SDNode *N, SDValue &Lo,
5775 SDValue &Hi) {
5776 // Assume that the maximum number of vector elements fits in getVectorIdxTy
5777 // and expand to that.
5778 EVT VT = N->getSimpleValueType(ResNo: 0);
5779 EVT IdxVT = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
5780 assert(IdxVT.bitsLT(VT) &&
5781 "VectorIdxTy should be smaller than type to be expanded?");
5782
5783 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: IdxVT, Operand: N->getOperand(Num: 0));
5784 Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: SDLoc(N), VT, Operand: Res);
5785 SplitInteger(Op: Res, Lo, Hi);
5786}
5787
5788//===----------------------------------------------------------------------===//
5789// Integer Operand Expansion
5790//===----------------------------------------------------------------------===//
5791
5792/// ExpandIntegerOperand - This method is called when the specified operand of
5793/// the specified node is found to need expansion. At this point, all of the
5794/// result types of the node are known to be legal, but other operands of the
5795/// node may need promotion or expansion as well as the specified one.
5796bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
5797 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG));
5798 SDValue Res = SDValue();
5799
5800 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false))
5801 return false;
5802
5803 switch (N->getOpcode()) {
5804 default:
5805 #ifndef NDEBUG
5806 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
5807 N->dump(&DAG); dbgs() << "\n";
5808 #endif
5809 report_fatal_error(reason: "Do not know how to expand this operator's operand!");
5810
5811 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
5812 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
5813 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
5814 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
5815 case ISD::FAKE_USE:
5816 Res = ExpandOp_FAKE_USE(N);
5817 break;
5818 case ISD::LOOP_DEPENDENCE_RAW_MASK:
5819 case ISD::LOOP_DEPENDENCE_WAR_MASK:
5820 Res = TLI.expandLoopDependenceMask(N, DAG);
5821 break;
5822 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
5823 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
5824 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
5825 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
5826 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
5827 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
5828 case ISD::STRICT_SINT_TO_FP:
5829 case ISD::SINT_TO_FP:
5830 case ISD::STRICT_UINT_TO_FP:
5831 case ISD::UINT_TO_FP: Res = ExpandIntOp_XINT_TO_FP(N); break;
5832 case ISD::STORE: Res = ExpandIntOp_STORE(N: cast<StoreSDNode>(Val: N), OpNo); break;
5833 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
5834
5835 case ISD::SHL:
5836 case ISD::SRA:
5837 case ISD::SRL:
5838 case ISD::ROTL:
5839 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
5840 case ISD::RETURNADDR:
5841 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
5842
5843 case ISD::SCMP:
5844 case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
5845
5846 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
5847 case ISD::STACKMAP:
5848 Res = ExpandIntOp_STACKMAP(N, OpNo);
5849 break;
5850 case ISD::PATCHPOINT:
5851 Res = ExpandIntOp_PATCHPOINT(N, OpNo);
5852 break;
5853 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
5854 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
5855 Res = ExpandIntOp_VP_STRIDED(N, OpNo);
5856 break;
5857 case ISD::WRITE_REGISTER:
5858 Res = ExpandIntOp_WRITE_REGISTER(N, OpNo);
5859 break;
5860 }
5861
5862 // If the result is null, the sub-method took care of registering results etc.
5863 if (!Res.getNode()) return false;
5864
5865 // If the result is N, the sub-method updated N in place. Tell the legalizer
5866 // core about this.
5867 if (Res.getNode() == N)
5868 return true;
5869
5870 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
5871 "Invalid operand expansion");
5872
5873 ReplaceValueWith(From: SDValue(N, 0), To: Res);
5874 return false;
5875}
5876
5877/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
5878/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
5879void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
5880 SDValue &NewRHS,
5881 ISD::CondCode &CCCode,
5882 const SDLoc &dl) {
5883 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5884 GetExpandedInteger(Op: NewLHS, Lo&: LHSLo, Hi&: LHSHi);
5885 GetExpandedInteger(Op: NewRHS, Lo&: RHSLo, Hi&: RHSHi);
5886
5887 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
5888 if (RHSLo == RHSHi && isAllOnesConstant(V: RHSLo)) {
5889 // Equality comparison to -1.
5890 NewLHS = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: LHSHi);
5891 NewRHS = RHSLo;
5892 return;
5893 }
5894
5895 NewLHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: RHSLo);
5896 NewRHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSHi, N2: RHSHi);
5897 NewLHS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NewLHS.getValueType(), N1: NewLHS, N2: NewRHS);
5898 NewRHS = DAG.getConstant(Val: 0, DL: dl, VT: NewLHS.getValueType());
5899 return;
5900 }
5901
5902 // If this is a comparison of the sign bit, just look at the top part.
5903 // X > -1, x < 0
5904 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Val&: NewRHS))
5905 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0
5906 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1
5907 NewLHS = LHSHi;
5908 NewRHS = RHSHi;
5909 return;
5910 }
5911
5912 // FIXME: This generated code sucks.
5913 ISD::CondCode LowCC;
5914 switch (CCCode) {
5915 default: llvm_unreachable("Unknown integer setcc!");
5916 case ISD::SETLT:
5917 case ISD::SETULT: LowCC = ISD::SETULT; break;
5918 case ISD::SETGT:
5919 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5920 case ISD::SETLE:
5921 case ISD::SETULE: LowCC = ISD::SETULE; break;
5922 case ISD::SETGE:
5923 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5924 }
5925
5926 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
5927 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
5928 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
5929
5930 // NOTE: on targets without efficient SELECT of bools, we can always use
5931 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5932 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
5933 nullptr);
5934 SDValue LoCmp, HiCmp;
5935 if (TLI.isTypeLegal(VT: LHSLo.getValueType()))
5936 LoCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSLo.getValueType()), N0: LHSLo,
5937 N1: RHSLo, Cond: LowCC, foldBooleans: false, DCI&: DagCombineInfo, dl);
5938 if (!LoCmp.getNode())
5939 LoCmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LHSLo.getValueType()), LHS: LHSLo,
5940 RHS: RHSLo, Cond: LowCC);
5941 if (TLI.isTypeLegal(VT: LHSHi.getValueType()))
5942 HiCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSHi.getValueType()), N0: LHSHi,
5943 N1: RHSHi, Cond: CCCode, foldBooleans: false, DCI&: DagCombineInfo, dl);
5944 if (!HiCmp.getNode())
5945 HiCmp =
5946 DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: getSetCCResultType(VT: LHSHi.getValueType()),
5947 N1: LHSHi, N2: RHSHi, N3: DAG.getCondCode(Cond: CCCode));
5948
5949 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(Val: LoCmp.getNode());
5950 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(Val: HiCmp.getNode());
5951
5952 bool EqAllowed = ISD::isTrueWhenEqual(Cond: CCCode);
5953
5954 // FIXME: Is the HiCmpC->isOne() here correct for
5955 // ZeroOrNegativeOneBooleanContent.
5956 if ((EqAllowed && (HiCmpC && HiCmpC->isZero())) ||
5957 (!EqAllowed &&
5958 ((HiCmpC && HiCmpC->isOne()) || (LoCmpC && LoCmpC->isZero())))) {
5959 // For LE / GE, if high part is known false, ignore the low part.
5960 // For LT / GT: if low part is known false, return the high part.
5961 // if high part is known true, ignore the low part.
5962 NewLHS = HiCmp;
5963 NewRHS = SDValue();
5964 return;
5965 }
5966
5967 if (LHSHi == RHSHi) {
5968 // Comparing the low bits is enough.
5969 NewLHS = LoCmp;
5970 NewRHS = SDValue();
5971 return;
5972 }
5973
5974 // Lower with SETCCCARRY if the target supports it.
5975 EVT HiVT = LHSHi.getValueType();
5976 EVT ExpandVT = TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: HiVT);
5977 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(Op: ISD::SETCCCARRY, VT: ExpandVT);
5978
5979 // FIXME: Make all targets support this, then remove the other lowering.
5980 if (HasSETCCCARRY) {
5981 // SETCCCARRY can detect < and >= directly. For > and <=, flip
5982 // operands and condition code.
5983 bool FlipOperands = false;
5984 switch (CCCode) {
5985 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
5986 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
5987 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
5988 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
5989 default: break;
5990 }
5991 if (FlipOperands) {
5992 std::swap(a&: LHSLo, b&: RHSLo);
5993 std::swap(a&: LHSHi, b&: RHSHi);
5994 }
5995 // Perform a wide subtraction, feeding the carry from the low part into
5996 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
5997 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
5998 // zero or positive iff LHS >= RHS.
5999 EVT LoVT = LHSLo.getValueType();
6000 SDVTList VTList = DAG.getVTList(VT1: LoVT, VT2: getSetCCResultType(VT: LoVT));
6001 SDValue LowCmp = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: LHSLo, N2: RHSLo);
6002 SDValue Res = DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: getSetCCResultType(VT: HiVT),
6003 N1: LHSHi, N2: RHSHi, N3: LowCmp.getValue(R: 1),
6004 N4: DAG.getCondCode(Cond: CCCode));
6005 NewLHS = Res;
6006 NewRHS = SDValue();
6007 return;
6008 }
6009
6010 NewLHS = TLI.SimplifySetCC(VT: getSetCCResultType(VT: HiVT), N0: LHSHi, N1: RHSHi, Cond: ISD::SETEQ,
6011 foldBooleans: false, DCI&: DagCombineInfo, dl);
6012 if (!NewLHS.getNode())
6013 NewLHS =
6014 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: HiVT), LHS: LHSHi, RHS: RHSHi, Cond: ISD::SETEQ);
6015 NewLHS = DAG.getSelect(DL: dl, VT: LoCmp.getValueType(), Cond: NewLHS, LHS: LoCmp, RHS: HiCmp);
6016 NewRHS = SDValue();
6017}
6018
6019SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
6020 SDValue NewLHS = N->getOperand(Num: 2), NewRHS = N->getOperand(Num: 3);
6021 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get();
6022 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
6023
6024 // If ExpandSetCCOperands returned a scalar, we need to compare the result
6025 // against zero to select between true and false values.
6026 if (!NewRHS.getNode()) {
6027 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
6028 CCCode = ISD::SETNE;
6029 }
6030
6031 // Update N to have the operands specified.
6032 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
6033 Op2: DAG.getCondCode(Cond: CCCode), Op3: NewLHS, Op4: NewRHS,
6034 Op5: N->getOperand(Num: 4)), 0);
6035}
6036
6037SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
6038 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
6039 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
6040 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
6041
6042 // If ExpandSetCCOperands returned a scalar, we need to compare the result
6043 // against zero to select between true and false values.
6044 if (!NewRHS.getNode()) {
6045 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
6046 CCCode = ISD::SETNE;
6047 }
6048
6049 // Update N to have the operands specified.
6050 return SDValue(DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS,
6051 Op3: N->getOperand(Num: 2), Op4: N->getOperand(Num: 3),
6052 Op5: DAG.getCondCode(Cond: CCCode)), 0);
6053}
6054
6055SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
6056 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
6057 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
6058 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
6059
6060 // If ExpandSetCCOperands returned a scalar, use it.
6061 if (!NewRHS.getNode()) {
6062 assert(NewLHS.getValueType() == N->getValueType(0) &&
6063 "Unexpected setcc expansion!");
6064 return NewLHS;
6065 }
6066
6067 // Otherwise, update N to have the operands specified.
6068 return SDValue(
6069 DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS, Op3: DAG.getCondCode(Cond: CCCode)), 0);
6070}
6071
6072SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
6073 SDValue LHS = N->getOperand(Num: 0);
6074 SDValue RHS = N->getOperand(Num: 1);
6075 SDValue Carry = N->getOperand(Num: 2);
6076 SDValue Cond = N->getOperand(Num: 3);
6077 SDLoc dl = SDLoc(N);
6078
6079 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
6080 GetExpandedInteger(Op: LHS, Lo&: LHSLo, Hi&: LHSHi);
6081 GetExpandedInteger(Op: RHS, Lo&: RHSLo, Hi&: RHSHi);
6082
6083 // Expand to a USUBO_CARRY for the low part and a SETCCCARRY for the high.
6084 SDVTList VTList = DAG.getVTList(VT1: LHSLo.getValueType(), VT2: Carry.getValueType());
6085 SDValue LowCmp =
6086 DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: LHSLo, N2: RHSLo, N3: Carry);
6087 return DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: N->getValueType(ResNo: 0), N1: LHSHi, N2: RHSHi,
6088 N3: LowCmp.getValue(R: 1), N4: Cond);
6089}
6090
6091SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
6092 // Split the operand and replace with SPLAT_VECTOR_PARTS.
6093 SDValue Lo, Hi;
6094 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
6095 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Lo,
6096 N2: Hi);
6097}
6098
6099SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
6100 // The value being shifted is legal, but the shift amount is too big.
6101 // It follows that either the result of the shift is undefined, or the
6102 // upper half of the shift amount is zero. Just use the lower half.
6103 SDValue Lo, Hi;
6104 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo, Hi);
6105 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Lo), 0);
6106}
6107
6108SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
6109 return TLI.expandCMP(Node: N, DAG);
6110}
6111
6112SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
6113 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
6114 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
6115 // constant to valid type.
6116 SDValue Lo, Hi;
6117 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
6118 return SDValue(DAG.UpdateNodeOperands(N, Op: Lo), 0);
6119}
6120
6121SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) {
6122 bool IsStrict = N->isStrictFPOpcode();
6123 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
6124 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
6125 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
6126 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
6127 EVT DstVT = N->getValueType(ResNo: 0);
6128 RTLIB::Libcall LC = IsSigned ? RTLIB::getSINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT)
6129 : RTLIB::getUINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT);
6130 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
6131 "Don't know how to expand this XINT_TO_FP!");
6132 TargetLowering::MakeLibCallOptions CallOptions;
6133 CallOptions.setIsSigned(true);
6134 std::pair<SDValue, SDValue> Tmp =
6135 TLI.makeLibCall(DAG, LC, RetVT: DstVT, Ops: Op, CallOptions, dl: SDLoc(N), Chain);
6136
6137 if (!IsStrict)
6138 return Tmp.first;
6139
6140 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
6141 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
6142 return SDValue();
6143}
6144
6145SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
6146 assert(!N->isAtomic() && "Should have been a ATOMIC_STORE?");
6147
6148 if (ISD::isNormalStore(N))
6149 return ExpandOp_NormalStore(N, OpNo);
6150
6151 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
6152 assert(OpNo == 1 && "Can only expand the stored value so far");
6153
6154 EVT VT = N->getOperand(Num: 1).getValueType();
6155 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6156 SDValue Ch = N->getChain();
6157 SDValue Ptr = N->getBasePtr();
6158 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
6159 AAMDNodes AAInfo = N->getAAInfo();
6160 SDLoc dl(N);
6161 SDValue Lo, Hi;
6162
6163 assert(NVT.isByteSized() && "Expanded type not byte sized!");
6164
6165 if (N->getMemoryVT().bitsLE(VT: NVT)) {
6166 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6167 return DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(),
6168 SVT: N->getMemoryVT(), Alignment: N->getBaseAlign(), MMOFlags,
6169 AAInfo);
6170 }
6171
6172 if (DAG.getDataLayout().isLittleEndian()) {
6173 // Little-endian - low bits are at low addresses.
6174 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6175
6176 Lo = DAG.getStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
6177 MMOFlags, AAInfo);
6178
6179 unsigned ExcessBits =
6180 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
6181 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
6182
6183 // Increment the pointer to the other half.
6184 unsigned IncrementSize = NVT.getSizeInBits()/8;
6185 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6186 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr,
6187 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6188 SVT: NEVT, Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
6189 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6190 }
6191
6192 // Big-endian - high bits are at low addresses. Favor aligned stores at
6193 // the cost of some bit-fiddling.
6194 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6195
6196 EVT ExtVT = N->getMemoryVT();
6197 unsigned EBytes = ExtVT.getStoreSize();
6198 unsigned IncrementSize = NVT.getSizeInBits()/8;
6199 unsigned ExcessBits = (EBytes - IncrementSize)*8;
6200 EVT HiVT = EVT::getIntegerVT(Context&: *DAG.getContext(),
6201 BitWidth: ExtVT.getSizeInBits() - ExcessBits);
6202
6203 if (ExcessBits < NVT.getSizeInBits()) {
6204 // Transfer high bits from the top of Lo to the bottom of Hi.
6205 Hi = DAG.getNode(
6206 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
6207 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
6208 Hi = DAG.getNode(
6209 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Hi,
6210 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Lo,
6211 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
6212 }
6213
6214 // Store both the high bits and maybe some of the low bits.
6215 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr, PtrInfo: N->getPointerInfo(), SVT: HiVT,
6216 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
6217
6218 // Increment the pointer to the other half.
6219 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6220 // Store the lowest ExcessBits bits in the second half.
6221 Lo = DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr,
6222 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6223 SVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
6224 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
6225 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6226}
6227
6228SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
6229 SDValue InL, InH;
6230 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
6231 // Just truncate the low part of the source.
6232 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: InL);
6233}
6234
6235SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
6236 SDLoc dl(N);
6237 SDValue Swap =
6238 DAG.getAtomic(Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(),
6239 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 2), Val: N->getOperand(Num: 1),
6240 MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
6241 return Swap.getValue(R: 1);
6242}
6243
6244SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
6245 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
6246 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
6247
6248 SDValue Hi; // The upper half is dropped out.
6249 SmallVector<SDValue, 8> NewOps(N->ops());
6250 GetExpandedInteger(Op: NewOps[OpNo], Lo&: NewOps[OpNo], Hi);
6251
6252 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
6253}
6254
6255SDValue DAGTypeLegalizer::ExpandIntOp_WRITE_REGISTER(SDNode *N, unsigned OpNo) {
6256 const Function &Fn = DAG.getMachineFunction().getFunction();
6257 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6258 "cannot use llvm.write_register with illegal type", Fn,
6259 N->getDebugLoc()));
6260
6261 return N->getOperand(Num: 0);
6262}
6263
6264SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
6265 SDLoc dl(N);
6266
6267 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6268 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6269 EVT OutVT = V0.getValueType();
6270
6271 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: OutVT, N1: V0, N2: V1, N3: N->getOperand(Num: 2));
6272}
6273
6274SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(SDNode *N) {
6275 SDLoc DL(N);
6276 unsigned Factor = N->getNumOperands();
6277
6278 SmallVector<SDValue, 8> Ops(Factor);
6279 for (unsigned i = 0; i != Factor; i++)
6280 Ops[i] = GetPromotedInteger(Op: N->getOperand(Num: i));
6281
6282 SmallVector<EVT, 8> ResVTs(Factor, Ops[0].getValueType());
6283 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VTs: ResVTs), Ops);
6284
6285 for (unsigned i = 0; i != Factor; i++)
6286 SetPromotedInteger(Op: SDValue(N, i), Result: Res.getValue(R: i));
6287
6288 return SDValue();
6289}
6290
6291SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
6292
6293 EVT OutVT = N->getValueType(ResNo: 0);
6294 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6295 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6296 EVT NOutVTElem = NOutVT.getVectorElementType();
6297
6298 SDLoc dl(N);
6299 SDValue BaseIdx = N->getOperand(Num: 1);
6300
6301 // TODO: We may be able to use this for types other than scalable
6302 // vectors and fix those tests that expect BUILD_VECTOR to be used
6303 if (OutVT.isScalableVector()) {
6304 SDValue InOp0 = N->getOperand(Num: 0);
6305 EVT InVT = InOp0.getValueType();
6306
6307 // Try and extract from a smaller type so that it eventually falls
6308 // into the promotion code below.
6309 if (getTypeAction(VT: InVT) == TargetLowering::TypeSplitVector ||
6310 getTypeAction(VT: InVT) == TargetLowering::TypeLegal) {
6311 EVT NInVT = InVT.getHalfNumVectorElementsVT(Context&: *DAG.getContext());
6312 unsigned NElts = NInVT.getVectorMinNumElements();
6313 uint64_t IdxVal = BaseIdx->getAsZExtVal();
6314
6315 SDValue Step1 = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NInVT, N1: InOp0,
6316 N2: DAG.getConstant(Val: alignDown(Value: IdxVal, Align: NElts), DL: dl,
6317 VT: BaseIdx.getValueType()));
6318 SDValue Step2 = DAG.getNode(
6319 Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Step1,
6320 N2: DAG.getConstant(Val: IdxVal % NElts, DL: dl, VT: BaseIdx.getValueType()));
6321 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Step2);
6322 }
6323
6324 // Try and extract from a widened type.
6325 if (getTypeAction(VT: InVT) == TargetLowering::TypeWidenVector) {
6326 SDValue Ops[] = {GetWidenedVector(Op: InOp0), BaseIdx};
6327 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: OutVT, Ops);
6328 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6329 }
6330
6331 // Promote operands and see if this is handled by target lowering,
6332 // Otherwise, use the BUILD_VECTOR approach below
6333 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
6334 // Collect the (promoted) operands
6335 SDValue Ops[] = { GetPromotedInteger(Op: InOp0), BaseIdx };
6336
6337 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
6338 assert(PromEltVT.bitsLE(NOutVTElem) &&
6339 "Promoted operand has an element type greater than result");
6340
6341 EVT ExtVT = NOutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: PromEltVT);
6342 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: ExtVT, Ops);
6343 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6344 }
6345 }
6346
6347 if (OutVT.isScalableVector())
6348 report_fatal_error(reason: "Unable to promote scalable types using BUILD_VECTOR");
6349
6350 SDValue InOp0 = N->getOperand(Num: 0);
6351 if (getTypeAction(VT: InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
6352 InOp0 = GetPromotedInteger(Op: InOp0);
6353
6354 EVT InVT = InOp0.getValueType();
6355 EVT InSVT = InVT.getVectorElementType();
6356
6357 unsigned OutNumElems = OutVT.getVectorNumElements();
6358 SmallVector<SDValue, 8> Ops;
6359 Ops.reserve(N: OutNumElems);
6360 for (unsigned i = 0; i != OutNumElems; ++i) {
6361 // Extract the element from the original vector.
6362 SDValue Index = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: BaseIdx.getValueType(), N1: BaseIdx,
6363 N2: DAG.getConstant(Val: i, DL: dl, VT: BaseIdx.getValueType()));
6364 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: InSVT,
6365 N1: N->getOperand(Num: 0), N2: Index);
6366 SDValue Op = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NOutVTElem);
6367 // Insert the converted element to the new vector.
6368 Ops.push_back(Elt: Op);
6369 }
6370
6371 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6372}
6373
6374SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
6375 EVT OutVT = N->getValueType(ResNo: 0);
6376 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6377 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6378
6379 SDLoc dl(N);
6380 SDValue Vec = N->getOperand(Num: 0);
6381 SDValue SubVec = N->getOperand(Num: 1);
6382 SDValue Idx = N->getOperand(Num: 2);
6383
6384 EVT SubVecVT = SubVec.getValueType();
6385 EVT NSubVT =
6386 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NOutVT.getVectorElementType(),
6387 EC: SubVecVT.getVectorElementCount());
6388
6389 Vec = GetPromotedInteger(Op: Vec);
6390 SubVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NSubVT, Operand: SubVec);
6391
6392 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: NOutVT, N1: Vec, N2: SubVec, N3: Idx);
6393}
6394
6395SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
6396 SDLoc dl(N);
6397
6398 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6399 EVT OutVT = V0.getValueType();
6400
6401 return DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL: dl, VT: OutVT, Operand: V0);
6402}
6403
6404SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
6405 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(Val: N);
6406 EVT VT = N->getValueType(ResNo: 0);
6407 SDLoc dl(N);
6408
6409 ArrayRef<int> NewMask = SV->getMask().slice(N: 0, M: VT.getVectorNumElements());
6410
6411 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6412 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6413 EVT OutVT = V0.getValueType();
6414
6415 return DAG.getVectorShuffle(VT: OutVT, dl, N1: V0, N2: V1, Mask: NewMask);
6416}
6417
6418SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
6419 EVT OutVT = N->getValueType(ResNo: 0);
6420 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6421 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6422 unsigned NumElems = N->getNumOperands();
6423 EVT NOutVTElem = NOutVT.getVectorElementType();
6424 TargetLoweringBase::BooleanContent NOutBoolType = TLI.getBooleanContents(Type: NOutVT);
6425 unsigned NOutExtOpc = TargetLowering::getExtendForContent(Content: NOutBoolType);
6426 SDLoc dl(N);
6427
6428 SmallVector<SDValue, 8> Ops;
6429 Ops.reserve(N: NumElems);
6430 for (unsigned i = 0; i != NumElems; ++i) {
6431 SDValue Op = N->getOperand(Num: i);
6432 EVT OpVT = Op.getValueType();
6433 // BUILD_VECTOR integer operand types are allowed to be larger than the
6434 // result's element type. This may still be true after the promotion. For
6435 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
6436 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
6437 if (OpVT.bitsLT(VT: NOutVTElem)) {
6438 unsigned ExtOpc = ISD::ANY_EXTEND;
6439 // Attempt to extend constant bool vectors to match target's BooleanContent.
6440 // While not necessary, this improves chances of the constant correctly
6441 // folding with compare results (e.g. for NOT patterns).
6442 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant)
6443 ExtOpc = NOutExtOpc;
6444 Op = DAG.getNode(Opcode: ExtOpc, DL: dl, VT: NOutVTElem, Operand: Op);
6445 }
6446 Ops.push_back(Elt: Op);
6447 }
6448
6449 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6450}
6451
6452SDValue DAGTypeLegalizer::PromoteIntRes_ScalarOp(SDNode *N) {
6453
6454 SDLoc dl(N);
6455
6456 assert(!N->getOperand(0).getValueType().isVector() &&
6457 "Input must be a scalar");
6458
6459 EVT OutVT = N->getValueType(ResNo: 0);
6460 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6461 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6462 EVT NOutElemVT = NOutVT.getVectorElementType();
6463
6464 SDValue Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutElemVT, Operand: N->getOperand(Num: 0));
6465 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NOutVT, Operand: Op);
6466}
6467
6468SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
6469 SDLoc dl(N);
6470 EVT OutVT = N->getValueType(ResNo: 0);
6471 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6472 assert(NOutVT.isScalableVector() &&
6473 "Type must be promoted to a scalable vector type");
6474 const APInt &StepVal = N->getConstantOperandAPInt(Num: 0);
6475 return DAG.getStepVector(DL: dl, ResVT: NOutVT,
6476 StepVal: StepVal.sext(width: NOutVT.getScalarSizeInBits()));
6477}
6478
6479SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
6480 SDLoc dl(N);
6481
6482 EVT OutVT = N->getValueType(ResNo: 0);
6483 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6484 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6485
6486 unsigned NumOperands = N->getNumOperands();
6487 unsigned NumOutElem = NOutVT.getVectorMinNumElements();
6488 EVT OutElemTy = NOutVT.getVectorElementType();
6489 if (OutVT.isScalableVector()) {
6490 // Find the largest promoted element type for each of the operands.
6491 SDUse *MaxSizedValue = std::max_element(
6492 first: N->op_begin(), last: N->op_end(), comp: [](const SDValue &A, const SDValue &B) {
6493 EVT AVT = A.getValueType().getVectorElementType();
6494 EVT BVT = B.getValueType().getVectorElementType();
6495 return AVT.getScalarSizeInBits() < BVT.getScalarSizeInBits();
6496 });
6497 EVT MaxElementVT = MaxSizedValue->getValueType().getVectorElementType();
6498
6499 // Then promote all vectors to the largest element type.
6500 SmallVector<SDValue, 8> Ops;
6501 for (unsigned I = 0; I < NumOperands; ++I) {
6502 SDValue Op = N->getOperand(Num: I);
6503 EVT OpVT = Op.getValueType();
6504 if (getTypeAction(VT: OpVT) == TargetLowering::TypePromoteInteger)
6505 Op = GetPromotedInteger(Op);
6506 else
6507 assert(getTypeAction(OpVT) == TargetLowering::TypeLegal &&
6508 "Unhandled legalization type");
6509
6510 if (OpVT.getVectorElementType().getScalarSizeInBits() <
6511 MaxElementVT.getScalarSizeInBits())
6512 Op = DAG.getAnyExtOrTrunc(
6513 Op, DL: dl,
6514 VT: OpVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT));
6515 Ops.push_back(Elt: Op);
6516 }
6517
6518 // Do the CONCAT on the promoted type and finally truncate to (the promoted)
6519 // NOutVT.
6520 return DAG.getAnyExtOrTrunc(
6521 Op: DAG.getNode(
6522 Opcode: ISD::CONCAT_VECTORS, DL: dl,
6523 VT: OutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT),
6524 Ops),
6525 DL: dl, VT: NOutVT);
6526 }
6527
6528 unsigned NumElem = N->getOperand(Num: 0).getValueType().getVectorNumElements();
6529 assert(NumElem * NumOperands == NumOutElem &&
6530 "Unexpected number of elements");
6531
6532 // Take the elements from the first vector.
6533 SmallVector<SDValue, 8> Ops(NumOutElem);
6534 for (unsigned i = 0; i < NumOperands; ++i) {
6535 SDValue Op = N->getOperand(Num: i);
6536 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypePromoteInteger)
6537 Op = GetPromotedInteger(Op);
6538 EVT SclrTy = Op.getValueType().getVectorElementType();
6539 assert(NumElem == Op.getValueType().getVectorNumElements() &&
6540 "Unexpected number of elements");
6541
6542 for (unsigned j = 0; j < NumElem; ++j) {
6543 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Op,
6544 N2: DAG.getVectorIdxConstant(Val: j, DL: dl));
6545 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: OutElemTy);
6546 }
6547 }
6548
6549 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6550}
6551
6552SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
6553 EVT VT = N->getValueType(ResNo: 0);
6554 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6555 assert(NVT.isVector() && "This type must be promoted to a vector type");
6556
6557 SDLoc dl(N);
6558
6559 // For operands whose TypeAction is to promote, extend the promoted node
6560 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
6561 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
6562 // type..
6563 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
6564 == TargetLowering::TypePromoteInteger) {
6565 SDValue Promoted;
6566
6567 switch(N->getOpcode()) {
6568 case ISD::SIGN_EXTEND_VECTOR_INREG:
6569 Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
6570 break;
6571 case ISD::ZERO_EXTEND_VECTOR_INREG:
6572 Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
6573 break;
6574 case ISD::ANY_EXTEND_VECTOR_INREG:
6575 Promoted = GetPromotedInteger(Op: N->getOperand(Num: 0));
6576 break;
6577 default:
6578 llvm_unreachable("Node has unexpected Opcode");
6579 }
6580 unsigned NewSize = NVT.getSizeInBits();
6581 if (Promoted.getValueType().getSizeInBits() > NewSize) {
6582 EVT ExtractVT = EVT::getVectorVT(
6583 Context&: *DAG.getContext(), VT: Promoted.getValueType().getVectorElementType(),
6584 NumElements: NewSize / Promoted.getScalarValueSizeInBits());
6585
6586 Promoted = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: ExtractVT, N1: Promoted,
6587 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
6588 }
6589 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Promoted);
6590 }
6591
6592 // Directly extend to the appropriate transform-to type.
6593 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
6594}
6595
6596SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(SDNode *N) {
6597 EVT VT = N->getValueType(ResNo: 0);
6598 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6599 return DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6600}
6601
6602SDValue DAGTypeLegalizer::PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
6603 EVT VT = N->getValueType(ResNo: 0);
6604 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6605 return DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6606}
6607
6608SDValue DAGTypeLegalizer::PromoteIntRes_PARTIAL_REDUCE_MLA(SDNode *N) {
6609 SDLoc DL(N);
6610 EVT VT = N->getValueType(ResNo: 0);
6611 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6612 SDValue ExtAcc = GetPromotedInteger(Op: N->getOperand(Num: 0));
6613 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: ExtAcc, N2: N->getOperand(Num: 1),
6614 N3: N->getOperand(Num: 2));
6615}
6616
6617SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
6618 EVT OutVT = N->getValueType(ResNo: 0);
6619 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6620 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6621
6622 EVT NOutVTElem = NOutVT.getVectorElementType();
6623
6624 SDLoc dl(N);
6625 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6626
6627 SDValue ConvElem = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6628 VT: NOutVTElem, Operand: N->getOperand(Num: 1));
6629 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NOutVT,
6630 N1: V0, N2: ConvElem, N3: N->getOperand(Num: 2));
6631}
6632
6633SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
6634 // The VECREDUCE result size may be larger than the element size, so
6635 // we can simply change the result type.
6636 SDLoc dl(N);
6637 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6638 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Ops: N->ops());
6639}
6640
6641SDValue DAGTypeLegalizer::PromoteIntRes_VP_REDUCE(SDNode *N) {
6642 // The VP_REDUCE result size may be larger than the element size, so we can
6643 // simply change the result type. However the start value and result must be
6644 // the same.
6645 SDLoc DL(N);
6646 SDValue Start = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
6647 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: Start.getValueType(), N1: Start,
6648 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
6649}
6650
6651SDValue DAGTypeLegalizer::PromoteIntRes_PATCHPOINT(SDNode *N) {
6652 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6653 SDLoc dl(N);
6654
6655 assert(N->getNumValues() == 3 && "Expected 3 values for PATCHPOINT");
6656 SDVTList VTList = DAG.getVTList(VTs: {NVT, MVT::Other, MVT::Glue});
6657
6658 SmallVector<SDValue> Ops(N->ops());
6659 SDValue Res = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList, Ops);
6660
6661 // Replace chain and glue uses with the new patchpoint.
6662 SDValue From[] = {SDValue(N, 1), SDValue(N, 2)};
6663 SDValue To[] = {Res.getValue(R: 1), Res.getValue(R: 2)};
6664 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
6665
6666 return Res.getValue(R: 0);
6667}
6668
6669SDValue DAGTypeLegalizer::PromoteIntRes_READ_REGISTER(SDNode *N) {
6670 const Function &Fn = DAG.getMachineFunction().getFunction();
6671 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6672 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
6673
6674 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6675 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
6676 return DAG.getPOISON(VT: NVT);
6677}
6678
6679SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
6680 SDLoc dl(N);
6681 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6682 SDValue V1 = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl,
6683 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
6684 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl,
6685 VT: V0->getValueType(ResNo: 0).getScalarType(), N1: V0, N2: V1);
6686
6687 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
6688 // element types. If this is the case then we need to expand the outgoing
6689 // value and not truncate it.
6690 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6691}
6692
6693SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_SUBVECTOR(SDNode *N) {
6694 SDLoc dl(N);
6695 // The result type is equal to the first input operand's type, so the
6696 // type that needs promoting must be the second source vector.
6697 SDValue V0 = N->getOperand(Num: 0);
6698 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6699 SDValue Idx = N->getOperand(Num: 2);
6700 EVT PromVT = EVT::getVectorVT(Context&: *DAG.getContext(),
6701 VT: V1.getValueType().getVectorElementType(),
6702 EC: V0.getValueType().getVectorElementCount());
6703 V0 = DAG.getAnyExtOrTrunc(Op: V0, DL: dl, VT: PromVT);
6704 SDValue Ext = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: PromVT, N1: V0, N2: V1, N3: Idx);
6705 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6706}
6707
6708// FIXME: We wouldn't need this if clang could promote short integers
6709// that are arguments to FAKE_USE.
6710SDValue DAGTypeLegalizer::PromoteIntOp_FAKE_USE(SDNode *N) {
6711 SDLoc dl(N);
6712 SDValue V0 = N->getOperand(Num: 0);
6713 SDValue V1 = N->getOperand(Num: 1);
6714 EVT InVT1 = V1.getValueType();
6715 SDValue VPromoted =
6716 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6717 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT1), Operand: V1);
6718 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: N->getValueType(ResNo: 0), N1: V0, N2: VPromoted);
6719}
6720
6721SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
6722 SDLoc dl(N);
6723 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6724 MVT InVT = V0.getValueType().getSimpleVT();
6725 MVT OutVT = MVT::getVectorVT(VT: InVT.getVectorElementType(),
6726 NumElements: N->getValueType(ResNo: 0).getVectorNumElements());
6727 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: V0, N2: N->getOperand(Num: 1));
6728 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Ext);
6729}
6730
6731SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
6732 SDLoc dl(N);
6733
6734 EVT ResVT = N->getValueType(ResNo: 0);
6735 unsigned NumElems = N->getNumOperands();
6736
6737 if (ResVT.isScalableVector()) {
6738 SDValue ResVec = DAG.getUNDEF(VT: ResVT);
6739
6740 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
6741 SDValue Op = N->getOperand(Num: OpIdx);
6742 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
6743 ResVec = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: ResVT, N1: ResVec, N2: Op,
6744 N3: DAG.getIntPtrConstant(Val: OpIdx * OpNumElts, DL: dl));
6745 }
6746
6747 return ResVec;
6748 }
6749
6750 EVT RetSclrTy = N->getValueType(ResNo: 0).getVectorElementType();
6751
6752 SmallVector<SDValue, 8> NewOps;
6753 NewOps.reserve(N: NumElems);
6754
6755 // For each incoming vector
6756 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
6757 SDValue Incoming = GetPromotedInteger(Op: N->getOperand(Num: VecIdx));
6758 EVT SclrTy = Incoming->getValueType(ResNo: 0).getVectorElementType();
6759 unsigned NumElem = Incoming->getValueType(ResNo: 0).getVectorNumElements();
6760
6761 for (unsigned i=0; i<NumElem; ++i) {
6762 // Extract element from incoming vector
6763 SDValue Ex = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Incoming,
6764 N2: DAG.getVectorIdxConstant(Val: i, DL: dl));
6765 SDValue Tr = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RetSclrTy, Operand: Ex);
6766 NewOps.push_back(Elt: Tr);
6767 }
6768 }
6769
6770 return DAG.getBuildVector(VT: N->getValueType(ResNo: 0), DL: dl, Ops: NewOps);
6771}
6772
6773SDValue DAGTypeLegalizer::ExpandIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
6774 assert(OpNo > 1);
6775 SDValue Op = N->getOperand(Num: OpNo);
6776
6777 // FIXME: Non-constant operands are not yet handled:
6778 // - https://github.com/llvm/llvm-project/issues/26431
6779 // - https://github.com/llvm/llvm-project/issues/55957
6780 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6781 if (!CN)
6782 return SDValue();
6783
6784 // Copy operands before the one being expanded.
6785 SmallVector<SDValue> NewOps;
6786 for (unsigned I = 0; I < OpNo; I++)
6787 NewOps.push_back(Elt: N->getOperand(Num: I));
6788
6789 EVT Ty = Op.getValueType();
6790 SDLoc DL = SDLoc(N);
6791 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6792 NewOps.push_back(
6793 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6794 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6795 } else {
6796 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6797 return SDValue();
6798 }
6799
6800 // Copy remaining operands.
6801 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6802 NewOps.push_back(Elt: N->getOperand(Num: I));
6803
6804 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6805
6806 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6807 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6808
6809 return SDValue(); // Signal that we have replaced the node already.
6810}
6811
6812SDValue DAGTypeLegalizer::ExpandIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
6813 assert(OpNo >= 7);
6814 SDValue Op = N->getOperand(Num: OpNo);
6815
6816 // FIXME: Non-constant operands are not yet handled:
6817 // - https://github.com/llvm/llvm-project/issues/26431
6818 // - https://github.com/llvm/llvm-project/issues/55957
6819 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6820 if (!CN)
6821 return SDValue();
6822
6823 // Copy operands before the one being expanded.
6824 SmallVector<SDValue> NewOps;
6825 for (unsigned I = 0; I < OpNo; I++)
6826 NewOps.push_back(Elt: N->getOperand(Num: I));
6827
6828 EVT Ty = Op.getValueType();
6829 SDLoc DL = SDLoc(N);
6830 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6831 NewOps.push_back(
6832 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6833 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6834 } else {
6835 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6836 return SDValue();
6837 }
6838
6839 // Copy remaining operands.
6840 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6841 NewOps.push_back(Elt: N->getOperand(Num: I));
6842
6843 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6844
6845 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6846 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6847
6848 return SDValue(); // Signal that we have replaced the node already.
6849}
6850