1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetLowering.h"
24#include "llvm/IR/DerivedTypes.h"
25#include "llvm/IR/DiagnosticInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/KnownBits.h"
28#include "llvm/Support/raw_ostream.h"
29#include <algorithm>
30using namespace llvm;
31
32#define DEBUG_TYPE "legalize-types"
33
34//===----------------------------------------------------------------------===//
35// Integer Result Promotion
36//===----------------------------------------------------------------------===//
37
38/// PromoteIntegerResult - This method is called when a result of a node is
39/// found to be in need of promotion to a larger type. At this point, the node
40/// may also have invalid operands or may have other results that need
41/// expansion, we just know that (at least) one result needs promotion.
42void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
43 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG));
44 SDValue Res = SDValue();
45
46 // See if the target wants to custom expand this node.
47 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true)) {
48 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
49 return;
50 }
51
52 switch (N->getOpcode()) {
53 default:
54#ifndef NDEBUG
55 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
56 N->dump(&DAG); dbgs() << "\n";
57#endif
58 report_fatal_error(reason: "Do not know how to promote this operator!");
59 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
60 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
61 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
62 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
63 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
64 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
65 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
66 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
67 case ISD::CTLZ_ZERO_POISON:
68 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
69 case ISD::CTLS: Res = PromoteIntRes_CTLS(N); break;
70 case ISD::PARITY:
71 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
72 case ISD::CTTZ_ZERO_POISON:
73 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
74 case ISD::CTTZ_ELTS_ZERO_POISON:
75 case ISD::CTTZ_ELTS:
76 case ISD::VP_CTTZ_ELTS_ZERO_POISON:
77 case ISD::VP_CTTZ_ELTS:
78 Res = PromoteIntRes_VP_CttzElements(N);
79 break;
80 case ISD::EXTRACT_VECTOR_ELT:
81 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
82 case ISD::LOAD: Res = PromoteIntRes_LOAD(N: cast<LoadSDNode>(Val: N)); break;
83 case ISD::VP_LOAD:
84 Res = PromoteIntRes_VP_LOAD(N: cast<VPLoadSDNode>(Val: N));
85 break;
86 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(N: cast<MaskedLoadSDNode>(Val: N));
87 break;
88 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(N: cast<MaskedGatherSDNode>(Val: N));
89 break;
90 case ISD::VECTOR_COMPRESS:
91 Res = PromoteIntRes_VECTOR_COMPRESS(N);
92 break;
93 case ISD::SELECT:
94 case ISD::VSELECT:
95 case ISD::VP_MERGE:
96 Res = PromoteIntRes_Select(N);
97 break;
98 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
99 case ISD::STRICT_FSETCC:
100 case ISD::STRICT_FSETCCS:
101 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
102
103 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
104 case ISD::SIGN_EXTEND_INREG:
105 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
106 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
107 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
108 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
109 case ISD::POISON:
110 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
111 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
112 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
113
114 case ISD::EXTRACT_SUBVECTOR:
115 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
116 case ISD::INSERT_SUBVECTOR:
117 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
118 case ISD::VECTOR_REVERSE:
119 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
120 case ISD::VECTOR_SHUFFLE:
121 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
122 case ISD::VECTOR_SPLICE_LEFT:
123 case ISD::VECTOR_SPLICE_RIGHT:
124 Res = PromoteIntRes_VECTOR_SPLICE(N);
125 break;
126 case ISD::VECTOR_REPEAT:
127 Res = PromoteIntRes_VECTOR_REPEAT(N);
128 break;
129 case ISD::VECTOR_INTERLEAVE:
130 case ISD::VECTOR_DEINTERLEAVE:
131 Res = PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(N);
132 return;
133 case ISD::INSERT_VECTOR_ELT:
134 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
135 case ISD::BUILD_VECTOR:
136 Res = PromoteIntRes_BUILD_VECTOR(N);
137 break;
138 case ISD::SPLAT_VECTOR:
139 case ISD::SCALAR_TO_VECTOR:
140 Res = PromoteIntRes_ScalarOp(N);
141 break;
142 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
143 case ISD::CONCAT_VECTORS:
144 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
145
146 case ISD::ANY_EXTEND_VECTOR_INREG:
147 case ISD::SIGN_EXTEND_VECTOR_INREG:
148 case ISD::ZERO_EXTEND_VECTOR_INREG:
149 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
150
151 case ISD::VECTOR_FIND_LAST_ACTIVE:
152 Res = PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(N);
153 break;
154
155 case ISD::GET_ACTIVE_LANE_MASK:
156 Res = PromoteIntRes_GET_ACTIVE_LANE_MASK(N);
157 break;
158 case ISD::MASK_BEFOREFIRST:
159 Res = PromoteIntRes_MASK_BEFOREFIRST(N);
160 break;
161 case ISD::VECTOR_MATCH:
162 Res = PromoteIntRes_VECTOR_MATCH(N);
163 break;
164
165 case ISD::PARTIAL_REDUCE_UMLA:
166 case ISD::PARTIAL_REDUCE_SMLA:
167 case ISD::PARTIAL_REDUCE_SUMLA:
168 Res = PromoteIntRes_PARTIAL_REDUCE_MLA(N);
169 break;
170
171 case ISD::SIGN_EXTEND:
172 case ISD::ZERO_EXTEND:
173 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
174
175 case ISD::STRICT_FP_TO_SINT:
176 case ISD::STRICT_FP_TO_UINT:
177 case ISD::FP_TO_SINT:
178 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
179
180 case ISD::FP_TO_SINT_SAT:
181 case ISD::FP_TO_UINT_SAT:
182 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
183
184 case ISD::FP_TO_BF16:
185 case ISD::FP_TO_FP16:
186 Res = PromoteIntRes_FP_TO_FP16_BF16(N);
187 break;
188 case ISD::CONVERT_TO_ARBITRARY_FP:
189 Res = PromoteIntRes_CONVERT_TO_ARBITRARY_FP(N);
190 break;
191 case ISD::STRICT_FP_TO_BF16:
192 case ISD::STRICT_FP_TO_FP16:
193 Res = PromoteIntRes_STRICT_FP_TO_FP16_BF16(N);
194 break;
195 case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break;
196
197 case ISD::AND:
198 case ISD::OR:
199 case ISD::XOR:
200 case ISD::ADD:
201 case ISD::SUB:
202 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
203
204 case ISD::SMIN:
205 case ISD::SMAX:
206 case ISD::ABDS:
207 case ISD::AVGCEILS:
208 case ISD::AVGFLOORS:
209 case ISD::SDIV:
210 case ISD::SREM:
211 case ISD::VP_SDIV:
212 case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
213
214 case ISD::AVGCEILU:
215 case ISD::AVGFLOORU:
216 case ISD::UDIV:
217 case ISD::UREM:
218 case ISD::VP_UDIV:
219 case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
220
221 case ISD::UMIN:
222 case ISD::UMAX:
223 case ISD::ABDU: Res = PromoteIntRes_SExtOrZExtIntBinOp(N); break;
224
225 case ISD::MASKED_UDIV:
226 case ISD::MASKED_UREM:
227 Res = PromoteIntRes_ZExtMaskedIntBinOp(N);
228 break;
229 case ISD::MASKED_SDIV:
230 case ISD::MASKED_SREM:
231 Res = PromoteIntRes_SExtMaskedIntBinOp(N);
232 break;
233
234 case ISD::SADDO:
235 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
236 case ISD::UADDO:
237 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
238 case ISD::SMULO:
239 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
240
241 case ISD::ADDE:
242 case ISD::SUBE:
243 case ISD::UADDO_CARRY:
244 case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break;
245
246 case ISD::SADDO_CARRY:
247 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
248
249 case ISD::SADDSAT:
250 case ISD::UADDSAT:
251 case ISD::SSUBSAT:
252 case ISD::USUBSAT:
253 case ISD::SSHLSAT:
254 case ISD::USHLSAT:
255 Res = PromoteIntRes_ADDSUBSHLSAT(N);
256 break;
257
258 case ISD::SCMP:
259 case ISD::UCMP:
260 Res = PromoteIntRes_CMP(N);
261 break;
262
263 case ISD::SMULFIX:
264 case ISD::SMULFIXSAT:
265 case ISD::UMULFIX:
266 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
267
268 case ISD::SDIVFIX:
269 case ISD::SDIVFIXSAT:
270 case ISD::UDIVFIX:
271 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
272
273 case ISD::ABS:
274 case ISD::ABS_MIN_POISON:
275 Res = PromoteIntRes_ABS(N);
276 break;
277
278 case ISD::ATOMIC_LOAD:
279 Res = PromoteIntRes_Atomic0(N: cast<AtomicSDNode>(Val: N)); break;
280
281 case ISD::ATOMIC_LOAD_ADD:
282 case ISD::ATOMIC_LOAD_SUB:
283 case ISD::ATOMIC_LOAD_AND:
284 case ISD::ATOMIC_LOAD_CLR:
285 case ISD::ATOMIC_LOAD_OR:
286 case ISD::ATOMIC_LOAD_XOR:
287 case ISD::ATOMIC_LOAD_NAND:
288 case ISD::ATOMIC_LOAD_MIN:
289 case ISD::ATOMIC_LOAD_MAX:
290 case ISD::ATOMIC_LOAD_UMIN:
291 case ISD::ATOMIC_LOAD_UMAX:
292 case ISD::ATOMIC_SWAP:
293 Res = PromoteIntRes_Atomic1(N: cast<AtomicSDNode>(Val: N)); break;
294
295 case ISD::ATOMIC_CMP_SWAP:
296 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
297 Res = PromoteIntRes_AtomicCmpSwap(N: cast<AtomicSDNode>(Val: N), ResNo);
298 break;
299
300 case ISD::VECREDUCE_ADD:
301 case ISD::VECREDUCE_MUL:
302 case ISD::VECREDUCE_AND:
303 case ISD::VECREDUCE_OR:
304 case ISD::VECREDUCE_XOR:
305 case ISD::VECREDUCE_SMAX:
306 case ISD::VECREDUCE_SMIN:
307 case ISD::VECREDUCE_UMAX:
308 case ISD::VECREDUCE_UMIN:
309 Res = PromoteIntRes_VECREDUCE(N);
310 break;
311
312 case ISD::VP_REDUCE_ADD:
313 case ISD::VP_REDUCE_MUL:
314 case ISD::VP_REDUCE_AND:
315 case ISD::VP_REDUCE_OR:
316 case ISD::VP_REDUCE_XOR:
317 case ISD::VP_REDUCE_SMAX:
318 case ISD::VP_REDUCE_SMIN:
319 case ISD::VP_REDUCE_UMAX:
320 case ISD::VP_REDUCE_UMIN:
321 Res = PromoteIntRes_VP_REDUCE(N);
322 break;
323
324 case ISD::LOOP_DEPENDENCE_WAR_MASK:
325 case ISD::LOOP_DEPENDENCE_RAW_MASK:
326 Res = PromoteIntRes_LOOP_DEPENDENCE_MASK(N);
327 break;
328
329 case ISD::FREEZE:
330 Res = PromoteIntRes_FREEZE(N);
331 break;
332
333 case ISD::ROTL:
334 case ISD::ROTR:
335 Res = PromoteIntRes_Rotate(N);
336 break;
337
338 case ISD::FSHL:
339 case ISD::FSHR:
340 Res = PromoteIntRes_FunnelShift(N);
341 break;
342
343 case ISD::CLMUL:
344 case ISD::CLMULH:
345 case ISD::CLMULR:
346 Res = PromoteIntRes_CLMUL(N);
347 break;
348
349 case ISD::PEXT:
350 Res = PromoteIntRes_PEXT(N);
351 break;
352
353 case ISD::PDEP:
354 Res = PromoteIntRes_PDEP(N);
355 break;
356
357 case ISD::MULHS:
358 case ISD::MULHU:
359 Res = PromoteIntRes_MULH(N);
360 break;
361
362 case ISD::IS_FPCLASS:
363 Res = PromoteIntRes_IS_FPCLASS(N);
364 break;
365 case ISD::FFREXP:
366 Res = PromoteIntRes_FFREXP(N);
367 break;
368
369 case ISD::LRINT:
370 case ISD::LLRINT:
371 Res = PromoteIntRes_XRINT(N);
372 break;
373
374 case ISD::PATCHPOINT:
375 Res = PromoteIntRes_PATCHPOINT(N);
376 break;
377 case ISD::READ_REGISTER:
378 Res = PromoteIntRes_READ_REGISTER(N);
379 break;
380 }
381
382 // If the result is null then the sub-method took care of registering it.
383 if (Res.getNode())
384 SetPromotedInteger(Op: SDValue(N, ResNo), Result: Res);
385}
386
387SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
388 unsigned ResNo) {
389 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
390 return GetPromotedInteger(Op);
391}
392
393SDValue DAGTypeLegalizer::PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
394 EVT VT = N->getValueType(ResNo: 0);
395 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
396 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: NewVT, Ops: N->ops());
397}
398
399SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
400 // Sign-extend the new bits, and continue the assertion.
401 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
402 return DAG.getNode(Opcode: ISD::AssertSext, DL: SDLoc(N),
403 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
404}
405
406SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
407 // Zero the new bits, and continue the assertion.
408 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
409 return DAG.getNode(Opcode: ISD::AssertZext, DL: SDLoc(N),
410 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
411}
412
413SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
414 EVT ResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
415 ISD::LoadExtType ExtType = N->getExtensionType();
416 if (ExtType == ISD::NON_EXTLOAD) {
417 switch (TLI.getExtendForAtomicOps()) {
418 case ISD::SIGN_EXTEND:
419 ExtType = ISD::SEXTLOAD;
420 break;
421 case ISD::ZERO_EXTEND:
422 ExtType = ISD::ZEXTLOAD;
423 break;
424 case ISD::ANY_EXTEND:
425 ExtType = ISD::EXTLOAD;
426 break;
427 default:
428 llvm_unreachable("Invalid atomic op extension");
429 }
430 }
431
432 SDValue Res =
433 DAG.getAtomicLoad(ExtType, dl: SDLoc(N), MemVT: N->getMemoryVT(), VT: ResVT,
434 Chain: N->getChain(), Ptr: N->getBasePtr(), MMO: N->getMemOperand());
435
436 // Legalize the chain result - switch anything that used the old chain to
437 // use the new one.
438 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
439 return Res;
440}
441
442SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
443 SDValue Op2 = N->getOperand(Num: 2);
444 switch (TLI.getExtendForAtomicRMWArg(Op: N->getOpcode())) {
445 case ISD::SIGN_EXTEND:
446 Op2 = SExtPromotedInteger(Op: Op2);
447 break;
448 case ISD::ZERO_EXTEND:
449 Op2 = ZExtPromotedInteger(Op: Op2);
450 break;
451 case ISD::ANY_EXTEND:
452 Op2 = GetPromotedInteger(Op: Op2);
453 break;
454 default:
455 llvm_unreachable("Invalid atomic op extension");
456 }
457 SDValue Res = DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N),
458 MemVT: N->getMemoryVT(),
459 Chain: N->getChain(), Ptr: N->getBasePtr(),
460 Val: Op2, MMO: N->getMemOperand());
461 // Legalize the chain result - switch anything that used the old chain to
462 // use the new one.
463 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
464 return Res;
465}
466
467SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
468 unsigned ResNo) {
469 if (ResNo == 1) {
470 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
471 EVT SVT = getSetCCResultType(VT: N->getOperand(Num: 2).getValueType());
472 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
473
474 // Only use the result of getSetCCResultType if it is legal,
475 // otherwise just use the promoted result type (NVT).
476 if (!TLI.isTypeLegal(VT: SVT))
477 SVT = NVT;
478
479 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: SVT, VT3: MVT::Other);
480 SDValue Res = DAG.getAtomicCmpSwap(
481 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs,
482 Chain: N->getChain(), Ptr: N->getBasePtr(), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
483 MMO: N->getMemOperand());
484 ReplaceValueWith(From: SDValue(N, 0), To: Res.getValue(R: 0));
485 ReplaceValueWith(From: SDValue(N, 2), To: Res.getValue(R: 2));
486 return DAG.getSExtOrTrunc(Op: Res.getValue(R: 1), DL: SDLoc(N), VT: NVT);
487 }
488
489 // Op2 is used for the comparison and thus must be extended according to the
490 // target's atomic operations. Op3 is merely stored and so can be left alone.
491 SDValue Op2 = N->getOperand(Num: 2);
492 SDValue Op3 = GetPromotedInteger(Op: N->getOperand(Num: 3));
493 switch (TLI.getExtendForAtomicCmpSwapArg()) {
494 case ISD::SIGN_EXTEND:
495 Op2 = SExtPromotedInteger(Op: Op2);
496 break;
497 case ISD::ZERO_EXTEND:
498 Op2 = ZExtPromotedInteger(Op: Op2);
499 break;
500 case ISD::ANY_EXTEND:
501 Op2 = GetPromotedInteger(Op: Op2);
502 break;
503 default:
504 llvm_unreachable("Invalid atomic op extension");
505 }
506
507 SDVTList VTs =
508 DAG.getVTList(VT1: Op2.getValueType(), VT2: N->getValueType(ResNo: 1), VT3: MVT::Other);
509 SDValue Res = DAG.getAtomicCmpSwap(
510 Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs, Chain: N->getChain(),
511 Ptr: N->getBasePtr(), Cmp: Op2, Swp: Op3, MMO: N->getMemOperand());
512 // Update the use to N with the newly created Res.
513 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
514 ReplaceValueWith(From: SDValue(N, i), To: Res.getValue(R: i));
515 return Res;
516}
517
518SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
519 SDValue InOp = N->getOperand(Num: 0);
520 EVT InVT = InOp.getValueType();
521 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
522 EVT OutVT = N->getValueType(ResNo: 0);
523 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
524 SDLoc dl(N);
525
526 switch (getTypeAction(VT: InVT)) {
527 case TargetLowering::TypeLegal:
528 break;
529 case TargetLowering::TypePromoteInteger:
530 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector() && !NInVT.isVector())
531 // The input promotes to the same size. Convert the promoted value.
532 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetPromotedInteger(Op: InOp));
533 break;
534 case TargetLowering::TypeSoftenFloat:
535 // Promote the integer operand by hand.
536 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftenedFloat(Op: InOp));
537 case TargetLowering::TypeSoftPromoteHalf:
538 // Promote the integer operand by hand.
539 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftPromotedHalf(Op: InOp));
540 case TargetLowering::TypeExpandInteger:
541 case TargetLowering::TypeExpandFloat:
542 break;
543 case TargetLowering::TypeScalarizeVector:
544 // Convert the element to an integer and promote it by hand.
545 if (!NOutVT.isVector())
546 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
547 Operand: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)));
548 break;
549 case TargetLowering::TypeScalarizeScalableVector:
550 report_fatal_error(reason: "scalarization of scalable vectors is not supported");
551 case TargetLowering::TypeSplitVector: {
552 if (!NOutVT.isVector()) {
553 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
554 // pieces of the input into integers and reassemble in the final type.
555 SDValue Lo, Hi;
556 GetSplitVector(Op: N->getOperand(Num: 0), Lo, Hi);
557 Lo = BitConvertToInteger(Op: Lo);
558 Hi = BitConvertToInteger(Op: Hi);
559
560 if (DAG.getDataLayout().isBigEndian())
561 std::swap(a&: Lo, b&: Hi);
562
563 InOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
564 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
565 BitWidth: NOutVT.getSizeInBits()),
566 Operand: JoinIntegers(Lo, Hi));
567 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: InOp);
568 }
569 break;
570 }
571 case TargetLowering::TypeWidenVector:
572 // The input is widened to the same size. Convert to the widened value.
573 // Make sure that the outgoing value is not a vector, because this would
574 // make us bitcast between two vectors which are legalized in different ways.
575 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector()) {
576 SDValue Res =
577 DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetWidenedVector(Op: InOp));
578
579 // For big endian targets we need to shift the casted value or the
580 // interesting bits will end up at the wrong place.
581 if (DAG.getDataLayout().isBigEndian()) {
582 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
583 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
584 Res = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NOutVT, N1: Res,
585 N2: DAG.getShiftAmountConstant(Val: ShiftAmt, VT: NOutVT, DL: dl));
586 }
587 return Res;
588 }
589 // If the output type is also a vector and widening it to the same size
590 // as the widened input type would be a legal type, we can widen the bitcast
591 // and handle the promotion after.
592 if (NOutVT.isVector()) {
593 TypeSize WidenInSize = NInVT.getSizeInBits();
594 TypeSize OutSize = OutVT.getSizeInBits();
595 if (WidenInSize.hasKnownScalarFactor(RHS: OutSize)) {
596 unsigned Scale = WidenInSize.getKnownScalarFactor(RHS: OutSize);
597 EVT WideOutVT =
598 EVT::getVectorVT(Context&: *DAG.getContext(), VT: OutVT.getVectorElementType(),
599 EC: OutVT.getVectorElementCount() * Scale);
600 if (isTypeLegal(VT: WideOutVT)) {
601 InOp = DAG.getBitcast(VT: WideOutVT, V: GetWidenedVector(Op: InOp));
602 InOp = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: InOp,
603 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
604 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: InOp);
605 }
606 }
607 }
608 }
609
610 // TODO: Handle big endian
611 if (!NOutVT.isVector() && InOp.getValueType().isVector() &&
612 DAG.getDataLayout().isLittleEndian()) {
613 // Pad the vector operand with undef and cast to a wider integer.
614 EVT EltVT = InOp.getValueType().getVectorElementType();
615 TypeSize EltSize = EltVT.getSizeInBits();
616 TypeSize OutSize = NOutVT.getSizeInBits();
617
618 if (OutSize.hasKnownScalarFactor(RHS: EltSize)) {
619 unsigned NumEltsWithPadding = OutSize.getKnownScalarFactor(RHS: EltSize);
620 EVT WideVecVT =
621 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
622
623 if (isTypeLegal(VT: WideVecVT)) {
624 SDValue Inserted = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: WideVecVT,
625 N1: DAG.getUNDEF(VT: WideVecVT), N2: InOp,
626 N3: DAG.getVectorIdxConstant(Val: 0, DL: dl));
627
628 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Inserted);
629 }
630 }
631 }
632
633 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
634 Operand: CreateStackStoreLoad(Op: InOp, DestVT: OutVT));
635}
636
637SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
638 SDValue V = GetPromotedInteger(Op: N->getOperand(Num: 0));
639 return DAG.getNode(Opcode: ISD::FREEZE, DL: SDLoc(N),
640 VT: V.getValueType(), Operand: V);
641}
642
643SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
644 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
645 EVT OVT = N->getValueType(ResNo: 0);
646 EVT NVT = Op.getValueType();
647 SDLoc dl(N);
648
649 // If the larger BSWAP isn't supported by the target, try to expand now.
650 // If we expand later we'll end up with more operations since we lost the
651 // original type. We only do this for scalars since we have a shuffle
652 // based lowering for vectors in LegalizeVectorOps.
653 if (!OVT.isVector() &&
654 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BSWAP, VT: NVT)) {
655 if (SDValue Res = TLI.expandBSWAP(N, DAG))
656 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
657 }
658
659 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
660 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
661 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: NVT, Operand: Op),
662 N2: ShAmt);
663}
664
665SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
666 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
667 EVT OVT = N->getValueType(ResNo: 0);
668 EVT NVT = Op.getValueType();
669 SDLoc dl(N);
670
671 // If the larger BITREVERSE isn't supported by the target, try to expand now.
672 // If we expand later we'll end up with more operations since we lost the
673 // original type. We only do this for scalars since we have a shuffle
674 // based lowering for vectors in LegalizeVectorOps.
675 if (!OVT.isVector() && OVT.isSimple() &&
676 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BITREVERSE, VT: NVT)) {
677 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
678 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
679 }
680
681 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
682 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
683 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT,
684 N1: DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: NVT, Operand: Op), N2: ShAmt);
685}
686
687SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
688 // The pair element type may be legal, or may not promote to the same type as
689 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
690 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N),
691 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
692 VT: N->getValueType(ResNo: 0)), Operand: JoinIntegers(Lo: N->getOperand(Num: 0),
693 Hi: N->getOperand(Num: 1)));
694}
695
696SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
697 EVT VT = N->getValueType(ResNo: 0);
698 // FIXME there is no actual debug info here
699 SDLoc dl(N);
700 // Zero extend things like i1, sign extend everything else. It shouldn't
701 // matter in theory which one we pick, but this tends to give better code?
702 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
703 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl,
704 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT),
705 Operand: SDValue(N, 0));
706 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
707 return Result;
708}
709
710SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
711 EVT OVT = N->getValueType(ResNo: 0);
712 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
713 SDLoc dl(N);
714
715 // If the larger CTLZ isn't supported by the target, try to expand now.
716 // If we expand later we'll end up with more operations since we lost the
717 // original type.
718 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
719 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ, VT: NVT) &&
720 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ_ZERO_POISON, VT: NVT)) {
721 if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
722 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
723 return Result;
724 }
725 }
726
727 unsigned CtlzOpcode = N->getOpcode();
728 if (CtlzOpcode == ISD::CTLZ) {
729 // Subtract off the extra leading bits in the bigger type.
730 SDValue ExtractLeadingBits = DAG.getConstant(
731 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
732 // Zero extend to the promoted type and do the count there.
733 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
734
735 // At this stage SUB is guaranteed to be positive no-wrap,
736 // that to be used in further KnownBits optimizations.
737 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT,
738 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Op),
739 N2: ExtractLeadingBits, Flags: SDNodeFlags::NoUnsignedWrap);
740 }
741 if (CtlzOpcode == ISD::CTLZ_ZERO_POISON) {
742 // Any Extend the argument
743 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
744 // Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
745 unsigned SHLAmount = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
746 auto ShiftConst =
747 DAG.getShiftAmountConstant(Val: SHLAmount, VT: Op.getValueType(), DL: dl);
748 Op = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst);
749 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, Operand: Op);
750 }
751 llvm_unreachable("Invalid CTLZ Opcode");
752}
753
754SDValue DAGTypeLegalizer::PromoteIntRes_CTLS(SDNode *N) {
755 EVT OVT = N->getValueType(ResNo: 0);
756 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
757 SDLoc dl(N);
758
759 SDValue ExtractLeadingBits = DAG.getConstant(
760 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
761
762 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
763 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Op),
764 N2: ExtractLeadingBits);
765}
766
767SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
768 EVT OVT = N->getValueType(ResNo: 0);
769 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
770
771 // If the larger CTPOP isn't supported by the target, try to expand now.
772 // If we expand later we'll end up with more operations since we lost the
773 // original type.
774 // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
775 // TargetLowering.
776 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
777 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTPOP, VT: NVT)) {
778 if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
779 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Result);
780 return Result;
781 }
782 }
783
784 // Zero extend to the promoted type and do the count or parity there.
785 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
786 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), Operand: Op);
787}
788
789SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
790 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
791 EVT OVT = N->getValueType(ResNo: 0);
792 EVT NVT = Op.getValueType();
793 SDLoc dl(N);
794
795 // If the larger CTTZ isn't supported by the target, try to expand now.
796 // If we expand later we'll end up with more operations since we lost the
797 // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
798 // larger type.
799 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
800 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ, VT: NVT) &&
801 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ_ZERO_POISON, VT: NVT) &&
802 !TLI.isOperationLegal(Op: ISD::CTPOP, VT: NVT) &&
803 !TLI.isOperationLegal(Op: ISD::CTLZ, VT: NVT)) {
804 if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
805 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
806 return Result;
807 }
808 }
809
810 unsigned NewOpc = N->getOpcode();
811 if (NewOpc == ISD::CTTZ) {
812 // The count is the same in the promoted type except if the original
813 // value was zero. This can be handled by setting the bit just off
814 // the top of the original type.
815 auto TopBit = APInt::getOneBitSet(numBits: NVT.getScalarSizeInBits(),
816 BitNo: OVT.getScalarSizeInBits());
817 Op = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
818 NewOpc = ISD::CTTZ_ZERO_POISON;
819 }
820 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Op);
821}
822
823SDValue DAGTypeLegalizer::PromoteIntRes_VP_CttzElements(SDNode *N) {
824 SDLoc DL(N);
825 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
826 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NewVT, Ops: N->ops());
827}
828
829SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
830 SDLoc dl(N);
831 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
832
833 SDValue Op0 = N->getOperand(Num: 0);
834 SDValue Op1 = N->getOperand(Num: 1);
835
836 // If the input also needs to be promoted, do that first so we can get a
837 // get a good idea for the output type.
838 if (TLI.getTypeAction(Context&: *DAG.getContext(), VT: Op0.getValueType())
839 == TargetLowering::TypePromoteInteger) {
840 SDValue In = GetPromotedInteger(Op: Op0);
841
842 // If the new type is larger than NVT, use it. We probably won't need to
843 // promote it again.
844 EVT SVT = In.getValueType().getScalarType();
845 if (SVT.bitsGE(VT: NVT)) {
846 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SVT, N1: In, N2: Op1);
847 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NVT);
848 }
849 }
850
851 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NVT, N1: Op0, N2: Op1);
852}
853
854SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
855 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
856 unsigned NewOpc =
857 TLI.getPreferredFPToIntOpcode(Op: N->getOpcode(), FromVT: N->getValueType(ResNo: 0), ToVT: NVT);
858 SDLoc dl(N);
859
860 SDValue Res;
861 if (N->isStrictFPOpcode()) {
862 Res = DAG.getNode(Opcode: NewOpc, DL: dl, ResultTys: {NVT, MVT::Other},
863 Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1)});
864 // Legalize the chain result - switch anything that used the old chain to
865 // use the new one.
866 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
867 } else {
868 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
869 }
870
871 // Assert that the converted value fits in the original type. If it doesn't
872 // (eg: because the value being converted is too big), then the result of the
873 // original operation was undefined anyway, so the assert is still correct.
874 //
875 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
876 // before legalization: fp-to-uint16, 65534. -> 0xfffe
877 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
878 return DAG.getNode(Opcode: (N->getOpcode() == ISD::FP_TO_UINT ||
879 N->getOpcode() == ISD::STRICT_FP_TO_UINT)
880 ? ISD::AssertZext
881 : ISD::AssertSext,
882 DL: dl, VT: NVT, N1: Res,
883 N2: DAG.getValueType(N->getValueType(ResNo: 0).getScalarType()));
884}
885
886SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
887 // Promote the result type, while keeping the original width in Op1.
888 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
889 SDLoc dl(N);
890 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
891 N2: N->getOperand(Num: 1));
892}
893
894SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16_BF16(SDNode *N) {
895 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
896 SDLoc dl(N);
897
898 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
899}
900
901// TODO: CONVERT_TO_ARBITRARY_FP also needs an ExpandIntegerResult handler for
902// wider arbitrary FP formats whose integer result requires expansion.
903SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_TO_ARBITRARY_FP(SDNode *N) {
904 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
905 SDLoc dl(N);
906
907 return DAG.getNode(Opcode: ISD::CONVERT_TO_ARBITRARY_FP, DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
908 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
909}
910
911SDValue DAGTypeLegalizer::PromoteIntRes_STRICT_FP_TO_FP16_BF16(SDNode *N) {
912 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
913 SDLoc dl(N);
914
915 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
916 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
917 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
918 return Res;
919}
920
921SDValue DAGTypeLegalizer::PromoteIntRes_XRINT(SDNode *N) {
922 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
923 SDLoc dl(N);
924 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
925}
926
927SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) {
928 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
929 SDLoc dl(N);
930
931 SDValue Res =
932 DAG.getNode(Opcode: N->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
933
934 // Legalize the chain result - switch anything that used the old chain to
935 // use the new one.
936 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
937 return Res;
938}
939
940SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
941 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
942 SDLoc dl(N);
943
944 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
945 == TargetLowering::TypePromoteInteger) {
946 SDValue Res = GetPromotedInteger(Op: N->getOperand(Num: 0));
947 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
948
949 // If the result and operand types are the same after promotion, simplify
950 // to an in-register extension. Unless this is a VP_*_EXTEND.
951 if (NVT == Res.getValueType() && N->getNumOperands() == 1) {
952 // The high bits are not guaranteed to be anything. Insert an extend.
953 if (N->getOpcode() == ISD::SIGN_EXTEND)
954 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
955 N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
956 if (N->getOpcode() == ISD::ZERO_EXTEND)
957 return DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: N->getOperand(Num: 0).getValueType());
958 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
959 return Res;
960 }
961 }
962
963 // Otherwise, just extend the original operand all the way to the larger type.
964 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
965}
966
967SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
968 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
969 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
970 ISD::LoadExtType ExtType =
971 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
972 SDLoc dl(N);
973 SDValue Res = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
974 MemVT: N->getMemoryVT(), MMO: N->getMemOperand());
975
976 // Legalize the chain result - switch anything that used the old chain to
977 // use the new one.
978 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
979 return Res;
980}
981
982SDValue DAGTypeLegalizer::PromoteIntRes_VP_LOAD(VPLoadSDNode *N) {
983 assert(!N->isIndexed() && "Indexed vp_load during type legalization!");
984 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
985 ISD::LoadExtType ExtType = (N->getExtensionType() == ISD::NON_EXTLOAD)
986 ? ISD::EXTLOAD
987 : N->getExtensionType();
988 SDLoc dl(N);
989 SDValue Res =
990 DAG.getExtLoadVP(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
991 Mask: N->getMask(), EVL: N->getVectorLength(), MemVT: N->getMemoryVT(),
992 MMO: N->getMemOperand(), IsExpanding: N->isExpandingLoad());
993 // Legalize the chain result - switch anything that used the old chain to
994 // use the new one.
995 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
996 return Res;
997}
998
999SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
1000 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1001 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1002
1003 ISD::LoadExtType ExtType = N->getExtensionType();
1004 if (ExtType == ISD::NON_EXTLOAD)
1005 ExtType = ISD::EXTLOAD;
1006
1007 SDLoc dl(N);
1008 SDValue Res = DAG.getMaskedLoad(VT: NVT, dl, Chain: N->getChain(), Base: N->getBasePtr(),
1009 Offset: N->getOffset(), Mask: N->getMask(), Src0: ExtPassThru,
1010 MemVT: N->getMemoryVT(), MMO: N->getMemOperand(),
1011 AM: N->getAddressingMode(), ExtType,
1012 IsExpanding: N->isExpandingLoad());
1013 // Legalize the chain result - switch anything that used the old chain to
1014 // use the new one.
1015 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1016 return Res;
1017}
1018
1019SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
1020 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1021 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1022 assert(NVT == ExtPassThru.getValueType() &&
1023 "Gather result type and the passThru argument type should be the same");
1024
1025 ISD::LoadExtType ExtType = N->getExtensionType();
1026 if (ExtType == ISD::NON_EXTLOAD)
1027 ExtType = ISD::EXTLOAD;
1028
1029 SDLoc dl(N);
1030 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
1031 N->getIndex(), N->getScale() };
1032 SDValue Res = DAG.getMaskedGather(VTs: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
1033 MemVT: N->getMemoryVT(), dl, Ops,
1034 MMO: N->getMemOperand(), IndexType: N->getIndexType(),
1035 ExtTy: ExtType);
1036 // Legalize the chain result - switch anything that used the old chain to
1037 // use the new one.
1038 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1039 return Res;
1040}
1041
1042SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_COMPRESS(SDNode *N) {
1043 SDValue Vec = GetPromotedInteger(Op: N->getOperand(Num: 0));
1044 SDValue Passthru = GetPromotedInteger(Op: N->getOperand(Num: 2));
1045 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT: Vec.getValueType(), N1: Vec,
1046 N2: N->getOperand(Num: 1), N3: Passthru);
1047}
1048
1049/// Promote the overflow flag of an overflowing arithmetic node.
1050SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
1051 // Change the return type of the boolean result while obeying
1052 // getSetCCResultType.
1053 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1054 EVT VT = N->getValueType(ResNo: 0);
1055 EVT SVT = getSetCCResultType(VT);
1056 SDValue Ops[3] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
1057 unsigned NumOps = N->getNumOperands();
1058 assert(NumOps <= 3 && "Too many operands");
1059 if (NumOps == 3)
1060 Ops[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: VT);
1061
1062 SDLoc dl(N);
1063 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: SVT),
1064 Ops: ArrayRef(Ops, NumOps));
1065
1066 // Modified the sum result - switch anything that used the old sum to use
1067 // the new one.
1068 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1069
1070 // Convert to the expected type.
1071 return DAG.getBoolExtOrTrunc(Op: Res.getValue(R: 1), SL: dl, VT: NVT, OpVT: VT);
1072}
1073
1074SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
1075 // If the promoted type is legal, we can convert this to:
1076 // 1. ANY_EXTEND iN to iM
1077 // 2. SHL by M-N
1078 // 3. [US][ADD|SUB|SHL]SAT
1079 // 4. L/ASHR by M-N
1080 // Else it is more efficient to convert this to a min and a max
1081 // operation in the higher precision arithmetic.
1082 SDLoc dl(N);
1083 SDValue Op1 = N->getOperand(Num: 0);
1084 SDValue Op2 = N->getOperand(Num: 1);
1085
1086 unsigned Opcode = N->getOpcode();
1087 unsigned OldBits = Op1.getScalarValueSizeInBits();
1088
1089 // USUBSAT can always be promoted as long as we have zero/sign-extended the
1090 // args.
1091 if (Opcode == ISD::USUBSAT) {
1092 SExtOrZExtPromotedOperands(LHS&: Op1, RHS&: Op2);
1093 return DAG.getNode(Opcode: ISD::USUBSAT, DL: dl, VT: Op1.getValueType(), N1: Op1, N2: Op2);
1094 }
1095
1096 if (Opcode == ISD::UADDSAT) {
1097 EVT OVT = Op1.getValueType();
1098 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1099 // We can promote if we use sign-extend. Do this if the target prefers.
1100 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT)) {
1101 Op1 = SExtPromotedInteger(Op: Op1);
1102 Op2 = SExtPromotedInteger(Op: Op2);
1103 return DAG.getNode(Opcode: ISD::UADDSAT, DL: dl, VT: NVT, N1: Op1, N2: Op2);
1104 }
1105
1106 Op1 = ZExtPromotedInteger(Op: Op1);
1107 Op2 = ZExtPromotedInteger(Op: Op2);
1108 unsigned NewBits = NVT.getScalarSizeInBits();
1109 APInt MaxVal = APInt::getLowBitsSet(numBits: NewBits, loBitsSet: OldBits);
1110 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: NVT);
1111 SDValue Add = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Op1, N2: Op2);
1112 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT: NVT, N1: Add, N2: SatMax);
1113 }
1114
1115 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
1116
1117 // FIXME: We need vp-aware PromotedInteger functions.
1118 if (IsShift) {
1119 Op1 = GetPromotedInteger(Op: Op1);
1120 if (getTypeAction(VT: Op2.getValueType()) == TargetLowering::TypePromoteInteger)
1121 Op2 = ZExtPromotedInteger(Op: Op2);
1122 } else {
1123 Op1 = SExtPromotedInteger(Op: Op1);
1124 Op2 = SExtPromotedInteger(Op: Op2);
1125 }
1126 EVT PromotedType = Op1.getValueType();
1127 unsigned NewBits = PromotedType.getScalarSizeInBits();
1128
1129 // Shift cannot use a min/max expansion, we can't detect overflow if all of
1130 // the bits have been shifted out.
1131 if (IsShift || TLI.isOperationLegal(Op: Opcode, VT: PromotedType)) {
1132 unsigned ShiftOp;
1133 switch (Opcode) {
1134 case ISD::SADDSAT:
1135 case ISD::SSUBSAT:
1136 case ISD::SSHLSAT:
1137 ShiftOp = ISD::SRA;
1138 break;
1139 case ISD::USHLSAT:
1140 ShiftOp = ISD::SRL;
1141 break;
1142 default:
1143 llvm_unreachable("Expected opcode to be signed or unsigned saturation "
1144 "addition, subtraction or left shift");
1145 }
1146
1147 unsigned SHLAmount = NewBits - OldBits;
1148 SDValue ShiftAmount =
1149 DAG.getShiftAmountConstant(Val: SHLAmount, VT: PromotedType, DL: dl);
1150 Op1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1, N2: ShiftAmount);
1151 if (!IsShift)
1152 Op2 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op2, N2: ShiftAmount);
1153
1154 SDValue Result = DAG.getNode(Opcode, DL: dl, VT: PromotedType, N1: Op1, N2: Op2);
1155 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result, N2: ShiftAmount);
1156 }
1157
1158 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
1159 APInt MinVal = APInt::getSignedMinValue(numBits: OldBits).sext(width: NewBits);
1160 APInt MaxVal = APInt::getSignedMaxValue(numBits: OldBits).sext(width: NewBits);
1161 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT: PromotedType);
1162 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: PromotedType);
1163 SDValue Result = DAG.getNode(Opcode: AddOp, DL: dl, VT: PromotedType, N1: Op1, N2: Op2);
1164 Result = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT: PromotedType, N1: Result, N2: SatMax);
1165 Result = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT: PromotedType, N1: Result, N2: SatMin);
1166 return Result;
1167}
1168
1169SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
1170 // Can just promote the operands then continue with operation.
1171 SDLoc dl(N);
1172 SDValue Op1Promoted, Op2Promoted;
1173 bool Signed =
1174 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
1175 bool Saturating =
1176 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
1177 if (Signed) {
1178 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1179 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1180 } else {
1181 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1182 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1183 }
1184 EVT OldType = N->getOperand(Num: 0).getValueType();
1185 EVT PromotedType = Op1Promoted.getValueType();
1186 unsigned DiffSize =
1187 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
1188
1189 if (Saturating) {
1190 // Promoting the operand and result values changes the saturation width,
1191 // which is extends the values that we clamp to on saturation. This could be
1192 // resolved by shifting one of the operands the same amount, which would
1193 // also shift the result we compare against, then shifting back.
1194 Op1Promoted =
1195 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1196 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1197 SDValue Result = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1198 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1199 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1200 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result,
1201 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1202 }
1203 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted, N2: Op2Promoted,
1204 N3: N->getOperand(Num: 2));
1205}
1206
1207static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
1208 unsigned SatW, bool Signed,
1209 const TargetLowering &TLI,
1210 SelectionDAG &DAG) {
1211 EVT VT = V.getValueType();
1212 unsigned VTW = VT.getScalarSizeInBits();
1213
1214 if (!Signed) {
1215 // Saturate to the unsigned maximum by getting the minimum of V and the
1216 // maximum.
1217 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT, N1: V,
1218 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW),
1219 DL: dl, VT));
1220 }
1221
1222 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
1223 // signed minimum of it and V.
1224 V = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT, N1: V,
1225 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW - 1),
1226 DL: dl, VT));
1227 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
1228 // signed maximum of it and V.
1229 V = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT, N1: V,
1230 N2: DAG.getConstant(Val: APInt::getHighBitsSet(numBits: VTW, hiBitsSet: VTW - SatW + 1),
1231 DL: dl, VT));
1232 return V;
1233}
1234
1235static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
1236 unsigned Scale, const TargetLowering &TLI,
1237 SelectionDAG &DAG, unsigned SatW = 0) {
1238 EVT VT = LHS.getValueType();
1239 unsigned VTSize = VT.getScalarSizeInBits();
1240 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1241 N->getOpcode() == ISD::SDIVFIXSAT;
1242 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1243 N->getOpcode() == ISD::UDIVFIXSAT;
1244
1245 SDLoc dl(N);
1246 // Widen the types by a factor of two. This is guaranteed to expand, since it
1247 // will always have enough high bits in the LHS to shift into.
1248 EVT WideVT = VT.changeElementType(
1249 Context&: *DAG.getContext(), EltVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: VTSize * 2));
1250 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL: dl, VT: WideVT);
1251 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL: dl, VT: WideVT);
1252 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS, RHS, Scale,
1253 DAG);
1254 assert(Res && "Expanding DIVFIX with wide type failed?");
1255 if (Saturating) {
1256 // If the caller has told us to saturate at something less, use that width
1257 // instead of the type before doubling. However, it cannot be more than
1258 // what we just widened!
1259 assert(SatW <= VTSize &&
1260 "Tried to saturate to more than the original type?");
1261 Res = SaturateWidenedDIVFIX(V: Res, dl, SatW: SatW == 0 ? VTSize : SatW, Signed,
1262 TLI, DAG);
1263 }
1264 return DAG.getZExtOrTrunc(Op: Res, DL: dl, VT);
1265}
1266
1267SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1268 SDLoc dl(N);
1269 SDValue Op1Promoted, Op2Promoted;
1270 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1271 N->getOpcode() == ISD::SDIVFIXSAT;
1272 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1273 N->getOpcode() == ISD::UDIVFIXSAT;
1274 if (Signed) {
1275 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1276 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1277 } else {
1278 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1279 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1280 }
1281 EVT PromotedType = Op1Promoted.getValueType();
1282 unsigned Scale = N->getConstantOperandVal(Num: 2);
1283
1284 // If the type is already legal and the operation is legal in that type, we
1285 // should not early expand.
1286 if (TLI.isTypeLegal(VT: PromotedType)) {
1287 TargetLowering::LegalizeAction Action =
1288 TLI.getFixedPointOperationAction(Op: N->getOpcode(), VT: PromotedType, Scale);
1289 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1290 unsigned Diff = PromotedType.getScalarSizeInBits() -
1291 N->getValueType(ResNo: 0).getScalarSizeInBits();
1292 if (Saturating)
1293 Op1Promoted =
1294 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1295 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1296 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1297 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1298 if (Saturating)
1299 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL: dl, VT: PromotedType, N1: Res,
1300 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1301 return Res;
1302 }
1303 }
1304
1305 // See if we can perform the division in this type without expanding.
1306 if (SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: Op1Promoted,
1307 RHS: Op2Promoted, Scale, DAG)) {
1308 if (Saturating)
1309 Res = SaturateWidenedDIVFIX(V: Res, dl,
1310 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits(),
1311 Signed, TLI, DAG);
1312 return Res;
1313 }
1314 // If we cannot, expand it to twice the type width. If we are saturating, give
1315 // it the original width as a saturating width so we don't need to emit
1316 // two saturations.
1317 return earlyExpandDIVFIX(N, LHS: Op1Promoted, RHS: Op2Promoted, Scale, TLI, DAG,
1318 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits());
1319}
1320
1321SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1322 if (ResNo == 1)
1323 return PromoteIntRes_Overflow(N);
1324
1325 // The operation overflowed iff the result in the larger type is not the
1326 // sign extension of its truncation to the original type.
1327 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1328 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1329 EVT OVT = N->getOperand(Num: 0).getValueType();
1330 EVT NVT = LHS.getValueType();
1331 SDLoc dl(N);
1332
1333 // Do the arithmetic in the larger type.
1334 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1335 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1336
1337 // Calculate the overflow flag: sign extend the arithmetic result from
1338 // the original type.
1339 SDValue Ofl = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1340 N2: DAG.getValueType(OVT));
1341 // Overflowed if and only if this is not equal to Res.
1342 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1343
1344 // Use the calculated overflow everywhere.
1345 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1346
1347 return Res;
1348}
1349
1350SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
1351 EVT PromotedResultTy =
1352 TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1353 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: PromotedResultTy,
1354 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
1355}
1356
1357SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1358 SDValue Mask = N->getOperand(Num: 0);
1359
1360 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1361 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1362
1363 unsigned Opcode = N->getOpcode();
1364 if (Opcode == ISD::VP_MERGE)
1365 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS,
1366 N4: N->getOperand(Num: 3));
1367 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS);
1368}
1369
1370SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1371 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1372 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 3));
1373 return DAG.getNode(Opcode: ISD::SELECT_CC, DL: SDLoc(N),
1374 VT: LHS.getValueType(), N1: N->getOperand(Num: 0),
1375 N2: N->getOperand(Num: 1), N3: LHS, N4: RHS, N5: N->getOperand(Num: 4));
1376}
1377
1378SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1379 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1380 EVT InVT = N->getOperand(Num: OpNo).getValueType();
1381 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1382
1383 EVT SVT = getSetCCResultType(VT: InVT);
1384
1385 // If we got back a type that needs to be promoted, this likely means the
1386 // the input type also needs to be promoted. So get the promoted type for
1387 // the input and try the query again.
1388 if (getTypeAction(VT: SVT) == TargetLowering::TypePromoteInteger) {
1389 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
1390 InVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
1391 SVT = getSetCCResultType(VT: InVT);
1392 } else {
1393 // Input type isn't promoted, just use the default promoted type.
1394 SVT = NVT;
1395 }
1396 }
1397
1398 SDLoc dl(N);
1399 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1400 "Vector compare must return a vector result!");
1401
1402 // Get the SETCC result using the canonical SETCC type.
1403 SDValue SetCC;
1404 if (N->isStrictFPOpcode()) {
1405 SDVTList VTs = DAG.getVTList(VTs: {SVT, MVT::Other});
1406 SDValue Opers[] = {N->getOperand(Num: 0), N->getOperand(Num: 1),
1407 N->getOperand(Num: 2), N->getOperand(Num: 3)};
1408 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: VTs, Ops: Opers, Flags: N->getFlags());
1409 // Legalize the chain result - switch anything that used the old chain to
1410 // use the new one.
1411 ReplaceValueWith(From: SDValue(N, 1), To: SetCC.getValue(R: 1));
1412 } else
1413 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: SVT, N1: N->getOperand(Num: 0),
1414 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), Flags: N->getFlags());
1415
1416 // Convert to the expected type.
1417 return DAG.getSExtOrTrunc(Op: SetCC, DL: dl, VT: NVT);
1418}
1419
1420SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
1421 SDLoc DL(N);
1422 SDValue Arg = N->getOperand(Num: 0);
1423 SDValue Test = N->getOperand(Num: 1);
1424 EVT NResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1425 return DAG.getNode(Opcode: ISD::IS_FPCLASS, DL, VT: NResVT, N1: Arg, N2: Test);
1426}
1427
1428SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
1429 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1430 EVT VT = N->getValueType(ResNo: 0);
1431
1432 SDLoc dl(N);
1433 SDValue Res =
1434 DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: NVT), N: N->getOperand(Num: 0));
1435
1436 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1437 return Res.getValue(R: 1);
1438}
1439
1440SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1441 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1442 SDValue RHS = N->getOperand(Num: 1);
1443 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1444 RHS = ZExtPromotedInteger(Op: RHS);
1445 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1446}
1447
1448SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1449 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
1450 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: SDLoc(N),
1451 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
1452}
1453
1454SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1455 // The input may have strange things in the top bits of the registers, but
1456 // these operations don't care. They may have weird bits going out, but
1457 // that too is okay if they are integer operations.
1458 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1459 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1460 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1461}
1462
1463SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1464 // Sign extend the input.
1465 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1466 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1467 if (N->getNumOperands() == 2)
1468 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1469 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1470 assert((N->getOpcode() == ISD::VP_SDIV || N->getOpcode() == ISD::VP_SREM) &&
1471 "Expected VP opcode");
1472 SDValue Mask = N->getOperand(Num: 2);
1473 SDValue EVL = N->getOperand(Num: 3);
1474 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1475 N3: Mask, N4: EVL);
1476}
1477
1478SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1479 // Zero extend the input.
1480 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1481 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1482 if (N->getNumOperands() == 2)
1483 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1484 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1485 assert((N->getOpcode() == ISD::VP_UDIV || N->getOpcode() == ISD::VP_UREM) &&
1486 "Expected VP opcode");
1487 // Zero extend the input.
1488 SDValue Mask = N->getOperand(Num: 2);
1489 SDValue EVL = N->getOperand(Num: 3);
1490 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1491 N3: Mask, N4: EVL);
1492}
1493
1494SDValue DAGTypeLegalizer::PromoteIntRes_ZExtMaskedIntBinOp(SDNode *N) {
1495 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1496 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1497 SDValue Mask = N->getOperand(Num: 2);
1498 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1499 N3: Mask);
1500}
1501
1502SDValue DAGTypeLegalizer::PromoteIntRes_SExtMaskedIntBinOp(SDNode *N) {
1503 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1504 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1505 SDValue Mask = N->getOperand(Num: 2);
1506 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1507 N3: Mask);
1508}
1509
1510SDValue DAGTypeLegalizer::PromoteIntRes_SExtOrZExtIntBinOp(SDNode *N) {
1511 SDValue LHS = N->getOperand(Num: 0);
1512 SDValue RHS = N->getOperand(Num: 1);
1513
1514 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1515 // whatever is best for the target and the promoted operands.
1516 SExtOrZExtPromotedOperands(LHS, RHS);
1517
1518 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N),
1519 VT: LHS.getValueType(), N1: LHS, N2: RHS);
1520}
1521
1522SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1523 // The input value must be properly sign extended.
1524 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1525 SDValue RHS = N->getOperand(Num: 1);
1526 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1527 RHS = ZExtPromotedInteger(Op: RHS);
1528 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1529}
1530
1531SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1532 SDValue RHS = N->getOperand(Num: 1);
1533 // The input value must be properly zero extended.
1534 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1535 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1536 RHS = ZExtPromotedInteger(Op: RHS);
1537 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1538}
1539
1540SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1541 EVT OldVT = N->getValueType(ResNo: 0);
1542 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1543 SDValue Amt = N->getOperand(Num: 1);
1544 unsigned Opcode = N->getOpcode();
1545 unsigned OldBits = OldVT.getScalarSizeInBits();
1546 unsigned NewBits = VT.getScalarSizeInBits();
1547
1548 // If the promoted type is twice the size (or more), then we can concatenate
1549 // the value with itself and treat this similar to a funnel shift. This isn't
1550 // necessary if the rotate amount is constant or if shl/srl of the original
1551 // type are custom lowered.
1552 // rotl(x,amt) -> (((aext(x) << bw) | zext(x)) << (amt % bw)) >> bw.
1553 // rotr(x,amt) -> (((aext(x) << bw) | zext(x)) >> (amt % bw)).
1554 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1555 !TLI.isOperationLegalOrCustom(Op: Opcode, VT) &&
1556 TLI.getOperationAction(Op: ISD::SHL, VT: OldVT) != TargetLowering::Custom &&
1557 TLI.getOperationAction(Op: ISD::SRL, VT: OldVT) != TargetLowering::Custom) {
1558 SDValue Op0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
1559 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1560 Amt = ZExtPromotedInteger(Op: Amt);
1561 EVT AmtVT = Amt.getValueType();
1562
1563 SDLoc DL(N);
1564 // Amount has to be interpreted modulo the old bit width.
1565 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1566 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1567 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1568 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Op0, N2: HiShift);
1569 SDValue Lo = DAG.getZeroExtendInReg(Op: Op0, DL, VT: OldVT);
1570 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1571 bool IsROTR = N->getOpcode() == ISD::ROTR;
1572 Res = DAG.getNode(Opcode: IsROTR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1573 // FIXME: We can avoid this by using ROTL when the promoted type is exactly
1574 // twice the size.
1575 if (!IsROTR)
1576 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1577 return Res;
1578 }
1579
1580 // Lower the rotate to shifts and ORs which can be promoted.
1581 SDValue Res = TLI.expandROT(N, AllowVectorOps: true /*AllowVectorOps*/, DAG);
1582 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1583 return SDValue();
1584}
1585
1586SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1587 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1588 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1589 SDValue Amt = N->getOperand(Num: 2);
1590 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1591 Amt = ZExtPromotedInteger(Op: Amt);
1592 EVT AmtVT = Amt.getValueType();
1593
1594 SDLoc DL(N);
1595 EVT OldVT = N->getOperand(Num: 0).getValueType();
1596 EVT VT = Lo.getValueType();
1597 unsigned Opcode = N->getOpcode();
1598 bool IsFSHR = Opcode == ISD::FSHR;
1599 unsigned OldBits = OldVT.getScalarSizeInBits();
1600 unsigned NewBits = VT.getScalarSizeInBits();
1601
1602 // Amount has to be interpreted modulo the old bit width.
1603 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1604 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1605
1606 // If the promoted type is twice the size (or more), then we use the
1607 // traditional funnel 'double' shift codegen. This isn't necessary if the
1608 // shift amount is constant.
1609 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1610 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1611 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1612 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1613 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1614 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: HiShift);
1615 Lo = DAG.getZeroExtendInReg(Op: Lo, DL, VT: OldVT);
1616 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1617 Res = DAG.getNode(Opcode: IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1618 if (!IsFSHR)
1619 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1620 return Res;
1621 }
1622
1623 // Shift Lo up to occupy the upper bits of the promoted type.
1624 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Lo,
1625 N2: DAG.getShiftAmountConstant(Val: NewBits - OldBits, VT, DL));
1626
1627 // Increase Amount to shift the result into the lower bits of the promoted
1628 // type.
1629 if (IsFSHR)
1630 Amt = DAG.getNode(Opcode: ISD::ADD, DL, VT: AmtVT, N1: Amt,
1631 N2: DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT));
1632
1633 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt);
1634}
1635
1636SDValue DAGTypeLegalizer::PromoteIntRes_CLMUL(SDNode *N) {
1637 unsigned Opcode = N->getOpcode();
1638
1639 SDLoc DL(N);
1640 EVT OldVT = N->getOperand(Num: 0).getValueType();
1641 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1642
1643 if (Opcode == ISD::CLMUL) {
1644 // Avoid the generic expansion if the cross-product expansion in
1645 // ExpandIntRes_CLMUL would produce a better result.
1646 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CLMUL, VT) &&
1647 !(getTypeAction(VT) == TargetLowering::TypeExpandInteger &&
1648 TLI.isOperationLegalOrCustom(
1649 Op: ISD::CLMUL, VT: TLI.getRegisterType(Context&: *DAG.getContext(), VT)))) {
1650 if (SDValue Res = TLI.expandCLMUL(N, DAG))
1651 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1652 }
1653 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1654 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1655 return DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1656 }
1657
1658 SDValue X = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1659 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1660
1661 unsigned OldBits = OldVT.getScalarSizeInBits();
1662 unsigned NewBits = VT.getScalarSizeInBits();
1663 if (NewBits < 2 * OldBits) {
1664 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1665 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1666 SDValue Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1667 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1668 SDValue Clmulh = DAG.getNode(Opcode: ISD::CLMULH, DL, VT, N1: X, N2: Y);
1669 ShAmt = Opcode == ISD::CLMULH ? NewBits - OldBits : NewBits - OldBits + 1;
1670 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Clmulh,
1671 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1672 return DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Lo, N2: Hi);
1673 }
1674
1675 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1676 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1677 return DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1678 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1679}
1680
1681SDValue DAGTypeLegalizer::PromoteIntRes_PEXT(SDNode *N) {
1682 SDLoc DL(N);
1683 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1684 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::PEXT, VT)) {
1685 if (SDValue Res = TLI.expandPEXT(N, DAG))
1686 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1687 }
1688 // Only the mask operand needs zero-extension because the implicit AND from
1689 // masking clears the corresponding bits in X anyway.
1690 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1691 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1692 return DAG.getNode(Opcode: ISD::PEXT, DL, VT, N1: X, N2: Y);
1693}
1694
1695SDValue DAGTypeLegalizer::PromoteIntRes_PDEP(SDNode *N) {
1696 SDLoc DL(N);
1697 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1698 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::PDEP, VT)) {
1699 if (SDValue Res = TLI.expandPDEP(N, DAG))
1700 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1701 }
1702 // Neither operand needs zero-extension because the upper operand bits could
1703 // only result in depositing result bits that will be discarded.
1704 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1705 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1706 return DAG.getNode(Opcode: ISD::PDEP, DL, VT, N1: X, N2: Y);
1707}
1708
1709SDValue DAGTypeLegalizer::PromoteIntRes_MULH(SDNode *N) {
1710 SDLoc dl(N);
1711 EVT VT = N->getValueType(ResNo: 0);
1712 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
1713 bool IsSigned = N->getOpcode() == ISD::MULHS;
1714 unsigned BW = VT.getScalarSizeInBits();
1715 unsigned NBW = NVT.getScalarSizeInBits();
1716
1717 SDValue LHS, RHS;
1718 if (IsSigned) {
1719 LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1720 RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1721 } else {
1722 LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1723 RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1724 }
1725
1726 // If the promoted type is already wide enough, emit a MUL.
1727 if (NBW >= 2 * BW)
1728 return DAG.getNode(Opcode: IsSigned ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
1729 N1: DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: NVT, N1: LHS, N2: RHS),
1730 N2: DAG.getShiftAmountConstant(Val: BW, VT: NVT, DL: dl));
1731
1732 // Otherwise, align an operand with a left-shift and emit a MULH.
1733 LHS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: LHS,
1734 N2: DAG.getShiftAmountConstant(Val: NBW - BW, VT: NVT, DL: dl));
1735 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: LHS, N2: RHS);
1736}
1737
1738SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1739 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1740 SDValue Res;
1741 SDValue InOp = N->getOperand(Num: 0);
1742 SDLoc dl(N);
1743
1744 switch (getTypeAction(VT: InOp.getValueType())) {
1745 default: llvm_unreachable("Unknown type action!");
1746 case TargetLowering::TypeLegal:
1747 case TargetLowering::TypeExpandInteger:
1748 Res = InOp;
1749 break;
1750 case TargetLowering::TypePromoteInteger:
1751 Res = GetPromotedInteger(Op: InOp);
1752 break;
1753 case TargetLowering::TypeSplitVector: {
1754 EVT InVT = InOp.getValueType();
1755 assert(InVT.isVector() && "Cannot split scalar types");
1756 ElementCount NumElts = InVT.getVectorElementCount();
1757 assert(NumElts == NVT.getVectorElementCount() &&
1758 "Dst and Src must have the same number of elements");
1759 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1760 "Promoted vector type must be a power of two");
1761
1762 SDValue EOp1, EOp2;
1763 GetSplitVector(Op: InOp, Lo&: EOp1, Hi&: EOp2);
1764
1765 EVT HalfNVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getScalarType(),
1766 EC: NumElts.divideCoefficientBy(RHS: 2));
1767 EOp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp1);
1768 EOp2 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp2);
1769 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl, VT: NVT, N1: EOp1, N2: EOp2);
1770 }
1771 case TargetLowering::TypeWidenVector: {
1772 SDValue WideInOp = GetWidenedVector(Op: InOp);
1773
1774 // Truncate widened InOp.
1775 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1776 EVT TruncVT = EVT::getVectorVT(Context&: *DAG.getContext(),
1777 VT: N->getValueType(ResNo: 0).getScalarType(), NumElements: NumElem);
1778 SDValue WideTrunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: TruncVT, Operand: WideInOp);
1779
1780 // Zero extend so that the elements are of same type as those of NVT
1781 EVT ExtVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getVectorElementType(),
1782 NumElements: NumElem);
1783 SDValue WideExt = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: ExtVT, Operand: WideTrunc);
1784
1785 // Extract the low NVT subvector.
1786 SDValue ZeroIdx = DAG.getVectorIdxConstant(Val: 0, DL: dl);
1787 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NVT, N1: WideExt, N2: ZeroIdx);
1788 }
1789 }
1790
1791 // Truncate to NVT instead of VT
1792 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Res);
1793}
1794
1795SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1796 if (ResNo == 1)
1797 return PromoteIntRes_Overflow(N);
1798
1799 // The operation overflowed iff the result in the larger type is not the
1800 // zero extension of its truncation to the original type.
1801 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1802 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1803 EVT OVT = N->getOperand(Num: 0).getValueType();
1804 EVT NVT = LHS.getValueType();
1805 SDLoc dl(N);
1806
1807 // Do the arithmetic in the larger type.
1808 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1809 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1810
1811 // Calculate the overflow flag: zero extend the arithmetic result from
1812 // the original type.
1813 SDValue Ofl = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: OVT);
1814 // Overflowed if and only if this is not equal to Res.
1815 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1816
1817 // Use the calculated overflow everywhere.
1818 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1819
1820 return Res;
1821}
1822
1823// Handle promotion for the ADDE/SUBE/UADDO_CARRY/USUBO_CARRY nodes. Notice that
1824// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1825// the UADDO_CARRY/USUBO_CARRY nodes in that the third operand is carry Boolean.
1826SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO_CARRY(SDNode *N,
1827 unsigned ResNo) {
1828 if (ResNo == 1)
1829 return PromoteIntRes_Overflow(N);
1830
1831 // We need to sign-extend the operands so the carry value computed by the
1832 // wide operation will be equivalent to the carry value computed by the
1833 // narrow operation.
1834 // An UADDO_CARRY can generate carry only if any of the operands has its
1835 // most significant bit set. Sign extension propagates the most significant
1836 // bit into the higher bits which means the extra bit that the narrow
1837 // addition would need (i.e. the carry) will be propagated through the higher
1838 // bits of the wide addition.
1839 // A USUBO_CARRY can generate borrow only if LHS < RHS and this property will
1840 // be preserved by sign extension.
1841 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1842 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1843
1844 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(ResNo: 1)};
1845
1846 // Do the arithmetic in the wide type.
1847 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VTList: DAG.getVTList(VTs: ValueVTs),
1848 N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
1849
1850 // Update the users of the original carry/borrow value.
1851 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1852
1853 return SDValue(Res.getNode(), 0);
1854}
1855
1856SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1857 unsigned ResNo) {
1858 assert(ResNo == 1 && "Don't know how to promote other results yet.");
1859 return PromoteIntRes_Overflow(N);
1860}
1861
1862SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1863 EVT OVT = N->getValueType(ResNo: 0);
1864 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1865
1866 // If a larger ABS or SMAX isn't supported by the target, try to expand now.
1867 // If we expand later we'll end up sign extending more than just the sra input
1868 // in sra+xor+sub expansion.
1869 if (!OVT.isVector() &&
1870 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS, VT: NVT) &&
1871 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS_MIN_POISON, VT: NVT) &&
1872 !TLI.isOperationLegal(Op: ISD::SMAX, VT: NVT)) {
1873 if (SDValue Res = TLI.expandABS(N, DAG))
1874 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Res);
1875 }
1876
1877 SDValue Op0 = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1878 return DAG.getNode(Opcode: ISD::ABS_MIN_POISON, DL: SDLoc(N), VT: Op0.getValueType(), Operand: Op0);
1879}
1880
1881SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1882 // Promote the overflow bit trivially.
1883 if (ResNo == 1)
1884 return PromoteIntRes_Overflow(N);
1885
1886 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
1887 SDLoc DL(N);
1888 EVT SmallVT = LHS.getValueType();
1889
1890 // To determine if the result overflowed in a larger type, we extend the
1891 // input to the larger type, do the multiply (checking if it overflows),
1892 // then also check the high bits of the result to see if overflow happened
1893 // there.
1894 if (N->getOpcode() == ISD::SMULO) {
1895 LHS = SExtPromotedInteger(Op: LHS);
1896 RHS = SExtPromotedInteger(Op: RHS);
1897 } else {
1898 LHS = ZExtPromotedInteger(Op: LHS);
1899 RHS = ZExtPromotedInteger(Op: RHS);
1900 }
1901 SDVTList VTs = DAG.getVTList(VT1: LHS.getValueType(), VT2: N->getValueType(ResNo: 1));
1902 SDValue Mul = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N1: LHS, N2: RHS);
1903
1904 // Overflow occurred if it occurred in the larger type, or if the high part
1905 // of the result does not zero/sign-extend the low part. Check this second
1906 // possibility first.
1907 SDValue Overflow;
1908 if (N->getOpcode() == ISD::UMULO) {
1909 // Unsigned overflow occurred if the high part is non-zero.
1910 unsigned Shift = SmallVT.getScalarSizeInBits();
1911 SDValue Hi =
1912 DAG.getNode(Opcode: ISD::SRL, DL, VT: Mul.getValueType(), N1: Mul,
1913 N2: DAG.getShiftAmountConstant(Val: Shift, VT: Mul.getValueType(), DL));
1914 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: Hi,
1915 RHS: DAG.getConstant(Val: 0, DL, VT: Hi.getValueType()),
1916 Cond: ISD::SETNE);
1917 } else {
1918 // Signed overflow occurred if the high part does not sign extend the low.
1919 SDValue SExt = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: Mul.getValueType(),
1920 N1: Mul, N2: DAG.getValueType(SmallVT));
1921 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: SExt, RHS: Mul, Cond: ISD::SETNE);
1922 }
1923
1924 // The only other way for overflow to occur is if the multiplication in the
1925 // larger type itself overflowed.
1926 Overflow = DAG.getNode(Opcode: ISD::OR, DL, VT: N->getValueType(ResNo: 1), N1: Overflow,
1927 N2: SDValue(Mul.getNode(), 1));
1928
1929 // Use the calculated overflow everywhere.
1930 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
1931 return Mul;
1932}
1933
1934SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1935 return DAG.getUNDEF(VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
1936 VT: N->getValueType(ResNo: 0)));
1937}
1938
1939SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1940 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1941
1942 const APInt &MulImm = N->getConstantOperandAPInt(Num: 0);
1943 return DAG.getVScale(DL: SDLoc(N), VT, MulImm: MulImm.sext(width: VT.getSizeInBits()));
1944}
1945
1946SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1947 SDValue Chain = N->getOperand(Num: 0); // Get the chain.
1948 SDValue Ptr = N->getOperand(Num: 1); // Get the pointer.
1949 EVT VT = N->getValueType(ResNo: 0);
1950 SDLoc dl(N);
1951
1952 MVT RegVT = TLI.getRegisterType(Context&: *DAG.getContext(), VT);
1953 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
1954 // The argument is passed as NumRegs registers of type RegVT.
1955
1956 SmallVector<SDValue, 8> Parts(NumRegs);
1957 for (unsigned i = 0; i < NumRegs; ++i) {
1958 Parts[i] = DAG.getVAArg(VT: RegVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2),
1959 Align: N->getConstantOperandVal(Num: 3));
1960 Chain = Parts[i].getValue(R: 1);
1961 }
1962
1963 // Handle endianness of the load.
1964 if (DAG.getDataLayout().isBigEndian())
1965 std::reverse(first: Parts.begin(), last: Parts.end());
1966
1967 // Assemble the parts in the promoted type.
1968 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1969 SDValue Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[0]);
1970 for (unsigned i = 1; i < NumRegs; ++i) {
1971 SDValue Part = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[i]);
1972 // Shift it to the right position and "or" it in.
1973 Part = DAG.getNode(
1974 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Part,
1975 N2: DAG.getShiftAmountConstant(Val: i * RegVT.getSizeInBits(), VT: NVT, DL: dl));
1976 Res = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Res, N2: Part);
1977 }
1978
1979 // Modified the chain result - switch anything that used the old chain to
1980 // use the new one.
1981 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
1982
1983 return Res;
1984}
1985
1986//===----------------------------------------------------------------------===//
1987// Integer Operand Promotion
1988//===----------------------------------------------------------------------===//
1989
1990/// PromoteIntegerOperand - This method is called when the specified operand of
1991/// the specified node is found to need promotion. At this point, all of the
1992/// result types of the node are known to be legal, but other operands of the
1993/// node may need promotion or expansion as well as the specified one.
1994bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1995 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG));
1996 SDValue Res = SDValue();
1997 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false)) {
1998 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
1999 return false;
2000 }
2001
2002 switch (N->getOpcode()) {
2003 default:
2004 #ifndef NDEBUG
2005 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
2006 N->dump(&DAG); dbgs() << "\n";
2007 #endif
2008 report_fatal_error(reason: "Do not know how to promote this operator's operand!");
2009
2010 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
2011 case ISD::ANY_EXTEND_VECTOR_INREG:
2012 Res = PromoteIntOp_ANY_EXTEND_VECTOR_INREG(N);
2013 break;
2014 case ISD::ATOMIC_STORE:
2015 Res = PromoteIntOp_ATOMIC_STORE(N: cast<AtomicSDNode>(Val: N));
2016 break;
2017 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
2018 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
2019 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
2020 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
2021 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
2022 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
2023 case ISD::COND_LOOP:
2024 Res = PromoteIntOp_COND_LOOP(N, OpNo);
2025 break;
2026 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
2027 case ISD::FAKE_USE:
2028 Res = PromoteIntOp_FAKE_USE(N);
2029 break;
2030 case ISD::INSERT_VECTOR_ELT:
2031 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
2032 break;
2033 case ISD::SPLAT_VECTOR:
2034 case ISD::SCALAR_TO_VECTOR:
2035 Res = PromoteIntOp_ScalarOp(N);
2036 break;
2037 case ISD::VSELECT:
2038 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
2039 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
2040 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
2041 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
2042 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
2043 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
2044 case ISD::STORE: Res = PromoteIntOp_STORE(N: cast<StoreSDNode>(Val: N),
2045 OpNo); break;
2046 case ISD::VP_STORE:
2047 Res = PromoteIntOp_VP_STORE(N: cast<VPStoreSDNode>(Val: N), OpNo);
2048 break;
2049 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(N: cast<MaskedStoreSDNode>(Val: N),
2050 OpNo); break;
2051 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(N: cast<MaskedLoadSDNode>(Val: N),
2052 OpNo); break;
2053 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(N: cast<MaskedGatherSDNode>(Val: N),
2054 OpNo); break;
2055 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(N: cast<MaskedScatterSDNode>(Val: N),
2056 OpNo); break;
2057 case ISD::VECTOR_COMPRESS:
2058 Res = PromoteIntOp_VECTOR_COMPRESS(N, OpNo);
2059 break;
2060 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
2061 case ISD::BF16_TO_FP:
2062 case ISD::FP16_TO_FP:
2063 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
2064 case ISD::CONVERT_FROM_ARBITRARY_FP:
2065 Res = PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(N);
2066 break;
2067 case ISD::STRICT_FP16_TO_FP:
2068 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
2069 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
2070 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
2071 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
2072
2073 case ISD::SHL:
2074 case ISD::SRA:
2075 case ISD::SRL:
2076 case ISD::ROTL:
2077 case ISD::ROTR:
2078 case ISD::SSHLSAT:
2079 case ISD::USHLSAT:
2080 Res = PromoteIntOp_Shift(N);
2081 break;
2082
2083 case ISD::SCMP:
2084 case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
2085
2086 case ISD::FSHL:
2087 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
2088
2089 case ISD::FRAMEADDR:
2090 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
2091
2092 case ISD::SMULFIX:
2093 case ISD::SMULFIXSAT:
2094 case ISD::UMULFIX:
2095 case ISD::UMULFIXSAT:
2096 case ISD::SDIVFIX:
2097 case ISD::SDIVFIXSAT:
2098 case ISD::UDIVFIX:
2099 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
2100 case ISD::FPOWI:
2101 case ISD::STRICT_FPOWI:
2102 case ISD::FLDEXP:
2103 case ISD::STRICT_FLDEXP: Res = PromoteIntOp_ExpOp(N); break;
2104 case ISD::VECREDUCE_ADD:
2105 case ISD::VECREDUCE_MUL:
2106 case ISD::VECREDUCE_AND:
2107 case ISD::VECREDUCE_OR:
2108 case ISD::VECREDUCE_XOR:
2109 case ISD::VECREDUCE_SMAX:
2110 case ISD::VECREDUCE_SMIN:
2111 case ISD::VECREDUCE_UMAX:
2112 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
2113 case ISD::VP_REDUCE_ADD:
2114 case ISD::VP_REDUCE_MUL:
2115 case ISD::VP_REDUCE_AND:
2116 case ISD::VP_REDUCE_OR:
2117 case ISD::VP_REDUCE_XOR:
2118 case ISD::VP_REDUCE_SMAX:
2119 case ISD::VP_REDUCE_SMIN:
2120 case ISD::VP_REDUCE_UMAX:
2121 case ISD::VP_REDUCE_UMIN:
2122 Res = PromoteIntOp_VP_REDUCE(N, OpNo);
2123 break;
2124
2125 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
2126 case ISD::STACKMAP:
2127 Res = PromoteIntOp_STACKMAP(N, OpNo);
2128 break;
2129 case ISD::PATCHPOINT:
2130 Res = PromoteIntOp_PATCHPOINT(N, OpNo);
2131 break;
2132 case ISD::WRITE_REGISTER:
2133 Res = PromoteIntOp_WRITE_REGISTER(N, OpNo);
2134 break;
2135 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
2136 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
2137 Res = PromoteIntOp_VP_STRIDED(N, OpNo);
2138 break;
2139 case ISD::EXPERIMENTAL_VP_SPLICE:
2140 Res = PromoteIntOp_VP_SPLICE(N, OpNo);
2141 break;
2142 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
2143 Res = PromoteIntOp_VECTOR_HISTOGRAM(N, OpNo);
2144 break;
2145 case ISD::VECTOR_FIND_LAST_ACTIVE:
2146 case ISD::CTTZ_ELTS:
2147 case ISD::CTTZ_ELTS_ZERO_POISON:
2148 Res = PromoteIntOp_UnaryBooleanVectorOp(N, OpNo);
2149 break;
2150 case ISD::GET_ACTIVE_LANE_MASK:
2151 Res = PromoteIntOp_GET_ACTIVE_LANE_MASK(N);
2152 break;
2153 case ISD::VECTOR_MATCH:
2154 Res = PromoteIntOp_VECTOR_MATCH(N, OpNo);
2155 break;
2156 case ISD::MASKED_UDIV:
2157 case ISD::MASKED_SDIV:
2158 case ISD::MASKED_UREM:
2159 case ISD::MASKED_SREM:
2160 Res = PromoteIntOp_MaskedBinOp(N, OpNo);
2161 break;
2162 case ISD::PARTIAL_REDUCE_UMLA:
2163 case ISD::PARTIAL_REDUCE_SMLA:
2164 case ISD::PARTIAL_REDUCE_SUMLA:
2165 Res = PromoteIntOp_PARTIAL_REDUCE_MLA(N);
2166 break;
2167 case ISD::VECTOR_REPEAT:
2168 Res = PromoteIntOp_VECTOR_REPEAT(N);
2169 break;
2170 case ISD::LOOP_DEPENDENCE_RAW_MASK:
2171 case ISD::LOOP_DEPENDENCE_WAR_MASK:
2172 Res = PromoteIntOp_LOOP_DEPENDENCE_MASK(N);
2173 break;
2174 }
2175
2176 // If the result is null, the sub-method took care of registering results etc.
2177 if (!Res.getNode()) return false;
2178
2179 // If the result is N, the sub-method updated N in place. Tell the legalizer
2180 // core about this.
2181 if (Res.getNode() == N)
2182 return true;
2183
2184 const bool IsStrictFp = N->isStrictFPOpcode();
2185 assert(Res.getValueType() == N->getValueType(0) &&
2186 N->getNumValues() == (IsStrictFp ? 2 : 1) &&
2187 "Invalid operand expansion");
2188 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
2189 Res.dump());
2190
2191 ReplaceValueWith(From: SDValue(N, 0), To: Res);
2192 if (IsStrictFp)
2193 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res.getNode(), 1));
2194
2195 return false;
2196}
2197
2198// These operands can be either sign extended or zero extended as long as we
2199// treat them the same. If an extension is free, choose that. Otherwise, follow
2200// target preference.
2201void DAGTypeLegalizer::SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS) {
2202 SDValue OpL = GetPromotedInteger(Op: LHS);
2203 SDValue OpR = GetPromotedInteger(Op: RHS);
2204
2205 if (TLI.isSExtCheaperThanZExt(FromTy: LHS.getValueType(), ToTy: OpL.getValueType())) {
2206 // The target would prefer to promote the comparison operand with sign
2207 // extension. Honor that unless the promoted values are already zero
2208 // extended.
2209 unsigned OpLEffectiveBits =
2210 DAG.computeKnownBits(Op: OpL).countMaxActiveBits();
2211 unsigned OpREffectiveBits =
2212 DAG.computeKnownBits(Op: OpR).countMaxActiveBits();
2213 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2214 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2215 LHS = OpL;
2216 RHS = OpR;
2217 return;
2218 }
2219
2220 // The promoted values aren't zero extended, use a sext_inreg.
2221 LHS = SExtPromotedInteger(Op: LHS);
2222 RHS = SExtPromotedInteger(Op: RHS);
2223 return;
2224 }
2225
2226 // Prefer to promote the comparison operand with zero extension.
2227
2228 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
2229 // than the width of LHS/RHS, we can avoid inserting a zext_inreg operation
2230 // that we might not be able to remove.
2231 unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpL);
2232 unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpR);
2233 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2234 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2235 LHS = OpL;
2236 RHS = OpR;
2237 return;
2238 }
2239
2240 // Otherwise, use zext_inreg.
2241 LHS = ZExtPromotedInteger(Op: LHS);
2242 RHS = ZExtPromotedInteger(Op: RHS);
2243}
2244
2245/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
2246/// shared among BR_CC, SELECT_CC, and SETCC handlers.
2247void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
2248 ISD::CondCode CCCode) {
2249 // We have to insert explicit sign or zero extends. Note that we could
2250 // insert sign extends for ALL conditions. For those operations where either
2251 // zero or sign extension would be valid, we ask the target which extension
2252 // it would prefer.
2253
2254 // Signed comparisons always require sign extension.
2255 if (ISD::isSignedIntSetCC(Code: CCCode)) {
2256 LHS = SExtPromotedInteger(Op: LHS);
2257 RHS = SExtPromotedInteger(Op: RHS);
2258 return;
2259 }
2260
2261 assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
2262 "Unknown integer comparison!");
2263
2264 SExtOrZExtPromotedOperands(LHS, RHS);
2265}
2266
2267SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
2268 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2269 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2270}
2271
2272SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND_VECTOR_INREG(SDNode *N) {
2273 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2274 EVT ResVT = N->getValueType(ResNo: 0);
2275 EVT OpVT = Op.getValueType();
2276 EVT NewVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: OpVT.getScalarType(),
2277 NumElements: ResVT.getVectorNumElements());
2278 Op = DAG.getExtractSubvector(DL: SDLoc(Op), VT: NewVT, Vec: Op, Idx: 0);
2279 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: ResVT, Operand: Op);
2280}
2281
2282SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
2283 SDValue Op1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
2284 return DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(),
2285 Chain: N->getChain(), Ptr: Op1, Val: N->getBasePtr(), MMO: N->getMemOperand());
2286}
2287
2288SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
2289 EVT OutVT = N->getValueType(ResNo: 0);
2290 SDValue InOp = N->getOperand(Num: 0);
2291 EVT InVT = InOp.getValueType();
2292 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
2293 SDLoc dl(N);
2294
2295 switch (getTypeAction(VT: InVT)) {
2296 case TargetLowering::TypePromoteInteger: {
2297 // TODO: Handle big endian & vector input type.
2298 if (OutVT.isVector() && !InVT.isVector() &&
2299 DAG.getDataLayout().isLittleEndian()) {
2300 EVT EltVT = OutVT.getVectorElementType();
2301 TypeSize EltSize = EltVT.getSizeInBits();
2302 TypeSize NInSize = NInVT.getSizeInBits();
2303
2304 if (NInSize.hasKnownScalarFactor(RHS: EltSize)) {
2305 unsigned NumEltsWithPadding = NInSize.getKnownScalarFactor(RHS: EltSize);
2306 EVT WideVecVT =
2307 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
2308
2309 if (isTypeLegal(VT: WideVecVT)) {
2310 SDValue Promoted = GetPromotedInteger(Op: InOp);
2311 SDValue Cast = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: WideVecVT, Operand: Promoted);
2312 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Cast,
2313 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
2314 }
2315 }
2316 }
2317
2318 break;
2319 }
2320 default:
2321 break;
2322 }
2323
2324 // This should only occur in unusual situations like bitcasting to an
2325 // x86_fp80, so just turn it into a store+load
2326 return CreateStackStoreLoad(Op: InOp, DestVT: OutVT);
2327}
2328
2329SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
2330 assert(OpNo == 2 && "Don't know how to promote this operand!");
2331
2332 SDValue LHS = N->getOperand(Num: 2);
2333 SDValue RHS = N->getOperand(Num: 3);
2334 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get());
2335
2336 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
2337 // legal types.
2338 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2339 Op2: N->getOperand(Num: 1), Op3: LHS, Op4: RHS, Op5: N->getOperand(Num: 4)),
2340 0);
2341}
2342
2343SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
2344 assert(OpNo == 1 && "only know how to promote condition");
2345
2346 // Promote all the way up to the canonical SetCC type.
2347 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2348
2349 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
2350 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond,
2351 Op3: N->getOperand(Num: 2)), 0);
2352}
2353
2354SDValue DAGTypeLegalizer::PromoteIntOp_COND_LOOP(SDNode *N, unsigned OpNo) {
2355 assert(OpNo == 1 && "only know how to promote condition");
2356
2357 // Promote all the way up to the canonical SetCC type.
2358 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2359
2360 // The chain (Op#0) is always a legal type.
2361 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond), 0);
2362}
2363
2364SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
2365 // Since the result type is legal, the operands must promote to it.
2366 EVT OVT = N->getOperand(Num: 0).getValueType();
2367 SDValue Lo = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2368 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 1));
2369 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
2370 SDLoc dl(N);
2371
2372 Hi = DAG.getNode(
2373 Opcode: ISD::SHL, DL: dl, VT: N->getValueType(ResNo: 0), N1: Hi,
2374 N2: DAG.getShiftAmountConstant(Val: OVT.getSizeInBits(), VT: N->getValueType(ResNo: 0), DL: dl));
2375 return DAG.getNode(Opcode: ISD::OR, DL: dl, VT: N->getValueType(ResNo: 0), N1: Lo, N2: Hi);
2376}
2377
2378SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
2379 // The vector type is legal but the element type is not. This implies
2380 // that the vector is a power-of-two in length and that the element
2381 // type does not have a strange size (eg: it is not i1).
2382 EVT VecVT = N->getValueType(ResNo: 0);
2383 unsigned NumElts = VecVT.getVectorNumElements();
2384 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
2385 "Legal vector of one illegal element?");
2386
2387 // Promote the inserted value. The type does not need to match the
2388 // vector element type. Check that any extra bits introduced will be
2389 // truncated away.
2390 assert(N->getOperand(0).getValueSizeInBits() >=
2391 N->getValueType(0).getScalarSizeInBits() &&
2392 "Type of inserted value narrower than vector element type!");
2393
2394 SmallVector<SDValue, 16> NewOps;
2395 for (unsigned i = 0; i < NumElts; ++i)
2396 NewOps.push_back(Elt: GetPromotedInteger(Op: N->getOperand(Num: i)));
2397
2398 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2399}
2400
2401SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
2402 unsigned OpNo) {
2403 if (OpNo == 1) {
2404 // Promote the inserted value. This is valid because the type does not
2405 // have to match the vector element type.
2406
2407 // Check that any extra bits introduced will be truncated away.
2408 assert(N->getOperand(1).getValueSizeInBits() >=
2409 N->getValueType(0).getScalarSizeInBits() &&
2410 "Type of inserted value narrower than vector element type!");
2411 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2412 Op2: GetPromotedInteger(Op: N->getOperand(Num: 1)),
2413 Op3: N->getOperand(Num: 2)),
2414 0);
2415 }
2416
2417 assert(OpNo == 2 && "Different operand and result vector types?");
2418
2419 // Promote the index.
2420 SDValue Idx = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 2), DL: SDLoc(N),
2421 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
2422 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2423 Op2: N->getOperand(Num: 1), Op3: Idx), 0);
2424}
2425
2426SDValue DAGTypeLegalizer::PromoteIntOp_ScalarOp(SDNode *N) {
2427 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2428
2429 // Integer SPLAT_VECTOR/SCALAR_TO_VECTOR operands are implicitly truncated,
2430 // so just promote the operand in place.
2431 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2432}
2433
2434SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
2435 assert(OpNo == 0 && "Only know how to promote the condition!");
2436 SDValue Cond = N->getOperand(Num: 0);
2437 EVT OpTy = N->getOperand(Num: 1).getValueType();
2438
2439 if (N->getOpcode() == ISD::VSELECT)
2440 if (SDValue Res = WidenVSELECTMask(N))
2441 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
2442 N1: Res, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2443
2444 // Promote all the way up to the canonical SetCC type.
2445 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
2446 Cond = PromoteTargetBoolean(Bool: Cond, ValVT: OpVT);
2447
2448 return SDValue(DAG.UpdateNodeOperands(N, Op1: Cond, Op2: N->getOperand(Num: 1),
2449 Op3: N->getOperand(Num: 2)), 0);
2450}
2451
2452SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
2453 assert(OpNo == 0 && "Don't know how to promote this operand!");
2454
2455 SDValue LHS = N->getOperand(Num: 0);
2456 SDValue RHS = N->getOperand(Num: 1);
2457 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get());
2458
2459 // The CC (#4) and the possible return values (#2 and #3) have legal types.
2460 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2461 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)), 0);
2462}
2463
2464SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
2465 assert(OpNo == 0 && "Don't know how to promote this operand!");
2466
2467 SDValue LHS = N->getOperand(Num: 0);
2468 SDValue RHS = N->getOperand(Num: 1);
2469 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get());
2470
2471 // The CC (#2) is always legal.
2472 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2)), 0);
2473}
2474
2475SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
2476 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2477 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2478}
2479
2480SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
2481 SDValue LHS = N->getOperand(Num: 0);
2482 SDValue RHS = N->getOperand(Num: 1);
2483
2484 if (N->getOpcode() == ISD::SCMP) {
2485 LHS = SExtPromotedInteger(Op: LHS);
2486 RHS = SExtPromotedInteger(Op: RHS);
2487 } else {
2488 SExtOrZExtPromotedOperands(LHS, RHS);
2489 }
2490
2491 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS), 0);
2492}
2493
2494SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
2495 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
2496 Op3: ZExtPromotedInteger(Op: N->getOperand(Num: 2))), 0);
2497}
2498
2499SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
2500 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2501 SDLoc dl(N);
2502 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Op);
2503 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Op.getValueType(),
2504 N1: Op, N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
2505}
2506
2507SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
2508 return SDValue(DAG.UpdateNodeOperands(N,
2509 Op: SExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2510}
2511
2512SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
2513 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2514 Op2: SExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2515}
2516
2517SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
2518 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2519 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
2520 SDLoc dl(N);
2521
2522 SDValue Val = GetPromotedInteger(Op: N->getValue()); // Get promoted value.
2523
2524 // Truncate the value and store the result.
2525 return DAG.getTruncStore(Chain: Ch, dl, Val, Ptr,
2526 SVT: N->getMemoryVT(), MMO: N->getMemOperand());
2527}
2528
2529SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
2530 unsigned OpNo) {
2531
2532 assert(OpNo == 1 && "Unexpected operand for promotion");
2533 assert(!N->isIndexed() && "expecting unindexed vp_store!");
2534
2535 SDValue DataOp = GetPromotedInteger(Op: N->getValue());
2536 return DAG.getTruncStoreVP(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Ptr: N->getBasePtr(),
2537 Mask: N->getMask(), EVL: N->getVectorLength(),
2538 SVT: N->getMemoryVT(), MMO: N->getMemOperand(),
2539 IsCompressing: N->isCompressingStore());
2540}
2541
2542SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
2543 unsigned OpNo) {
2544 SDValue DataOp = N->getValue();
2545 SDValue Mask = N->getMask();
2546
2547 if (OpNo == 4) {
2548 // The Mask. Update in place.
2549 EVT DataVT = DataOp.getValueType();
2550 Mask = PromoteTargetBoolean(Bool: Mask, ValVT: DataVT);
2551 SmallVector<SDValue, 4> NewOps(N->ops());
2552 NewOps[4] = Mask;
2553 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2554 }
2555
2556 assert(OpNo == 1 && "Unexpected operand for promotion");
2557 DataOp = GetPromotedInteger(Op: DataOp);
2558
2559 return DAG.getMaskedStore(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Base: N->getBasePtr(),
2560 Offset: N->getOffset(), Mask, MemVT: N->getMemoryVT(),
2561 MMO: N->getMemOperand(), AM: N->getAddressingMode(),
2562 /*IsTruncating*/ true, IsCompressing: N->isCompressingStore());
2563}
2564
2565SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
2566 unsigned OpNo) {
2567 assert(OpNo == 3 && "Only know how to promote the mask!");
2568 EVT DataVT = N->getValueType(ResNo: 0);
2569 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2570 SmallVector<SDValue, 4> NewOps(N->ops());
2571 NewOps[OpNo] = Mask;
2572 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2573 if (Res == N)
2574 return SDValue(Res, 0);
2575
2576 // Update triggered CSE, do our own replacement since caller can't.
2577 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2578 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2579 return SDValue();
2580}
2581
2582SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
2583 unsigned OpNo) {
2584 SmallVector<SDValue, 5> NewOps(N->ops());
2585
2586 if (OpNo == 2) {
2587 // The Mask
2588 EVT DataVT = N->getValueType(ResNo: 0);
2589 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2590 } else if (OpNo == 4) {
2591 // The Index
2592 if (N->isIndexSigned())
2593 // Need to sign extend the index since the bits will likely be used.
2594 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2595 else
2596 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2597 } else
2598 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2599
2600 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2601 if (Res == N)
2602 return SDValue(Res, 0);
2603
2604 // Update triggered CSE, do our own replacement since caller can't.
2605 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2606 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2607 return SDValue();
2608}
2609
2610SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2611 unsigned OpNo) {
2612 bool TruncateStore = N->isTruncatingStore();
2613 SmallVector<SDValue, 5> NewOps(N->ops());
2614
2615 if (OpNo == 2) {
2616 // The Mask
2617 EVT DataVT = N->getValue().getValueType();
2618 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2619 } else if (OpNo == 4) {
2620 // The Index
2621 if (N->isIndexSigned())
2622 // Need to sign extend the index since the bits will likely be used.
2623 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2624 else
2625 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2626 } else {
2627 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2628 TruncateStore = true;
2629 }
2630
2631 return DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: N->getMemoryVT(),
2632 dl: SDLoc(N), Ops: NewOps, MMO: N->getMemOperand(),
2633 IndexType: N->getIndexType(), IsTruncating: TruncateStore);
2634}
2635
2636SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_COMPRESS(SDNode *N,
2637 unsigned OpNo) {
2638 assert(OpNo == 1 && "Can only promote VECTOR_COMPRESS mask.");
2639 SDValue Vec = N->getOperand(Num: 0);
2640 EVT VT = Vec.getValueType();
2641 SDValue Passthru = N->getOperand(Num: 2);
2642 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: VT);
2643 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT, N1: Vec, N2: Mask, N3: Passthru);
2644}
2645
2646SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2647 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2648 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2649}
2650
2651SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2652 return SDValue(DAG.UpdateNodeOperands(N,
2653 Op: ZExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2654}
2655
2656SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(SDNode *N) {
2657 return SDValue(DAG.UpdateNodeOperands(N, Op1: GetPromotedInteger(Op: N->getOperand(Num: 0)),
2658 Op2: N->getOperand(Num: 1)),
2659 0);
2660}
2661
2662SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2663 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2664 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2665}
2666
2667SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2668 SDLoc dl(N);
2669 SDValue Src = N->getOperand(Num: 0);
2670 SDValue Op = GetPromotedInteger(Op: Src);
2671 EVT VT = N->getValueType(ResNo: 0);
2672
2673 // If this zext has the nneg flag and the target prefers sext, see if the
2674 // promoted input is already sign extended.
2675 // TODO: Should we have some way to set nneg on ISD::AND instead?
2676 if (N->getFlags().hasNonNeg() && Op.getValueType() == VT &&
2677 TLI.isSExtCheaperThanZExt(FromTy: Src.getValueType(), ToTy: VT)) {
2678 unsigned OpEffectiveBits = DAG.ComputeMaxSignificantBits(Op);
2679 if (OpEffectiveBits <= Src.getScalarValueSizeInBits())
2680 return Op;
2681 }
2682
2683 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Op);
2684 return DAG.getZeroExtendInReg(Op, DL: dl, VT: Src.getValueType());
2685}
2686
2687SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2688 SDValue Op2 = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2689 return SDValue(
2690 DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1), Op3: Op2), 0);
2691}
2692
2693SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2694 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2695 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2696 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2697}
2698
2699SDValue DAGTypeLegalizer::PromoteIntOp_ExpOp(SDNode *N) {
2700 bool IsStrict = N->isStrictFPOpcode();
2701 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
2702
2703 bool IsPowI =
2704 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI;
2705 unsigned OpOffset = IsStrict ? 1 : 0;
2706
2707 // The integer operand is the last operand in FPOWI (or FLDEXP) (so the result
2708 // and floating point operand is already type legalized).
2709 RTLIB::Libcall LC = IsPowI ? RTLIB::getPOWI(VT: N->getValueType(ResNo: 0))
2710 : RTLIB::getLDEXP(VT: N->getValueType(ResNo: 0));
2711
2712 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
2713 if (LCImpl == RTLIB::Unsupported) {
2714 // Scalarize vector FPOWI instead of promoting the type. This allows the
2715 // scalar FPOWIs to be visited and converted to libcalls before promoting
2716 // the type.
2717 // FIXME: This should be done in LegalizeVectorOps/LegalizeDAG, but call
2718 // lowering needs the unpromoted EVT.
2719 if (IsPowI && N->getValueType(ResNo: 0).isVector())
2720 return DAG.UnrollVectorOp(N);
2721 SmallVector<SDValue, 3> NewOps(N->ops());
2722 NewOps[1 + OpOffset] = SExtPromotedInteger(Op: N->getOperand(Num: 1 + OpOffset));
2723 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2724 }
2725
2726 // We can't just promote the exponent type in FPOWI, since we want to lower
2727 // the node to a libcall and we if we promote to a type larger than
2728 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2729 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2730 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2731
2732 // A wider-than-int exponent can't be passed in an int (there's no wider
2733 // libcall), so bail like the soften/expand paths. A narrower one is
2734 // sign-extended to int by the makeLibCall below.
2735 if (N->getOperand(Num: 1 + OpOffset).getScalarValueSizeInBits() >
2736 DAG.getLibInfo().getIntSize()) {
2737 const Function &Fn = DAG.getMachineFunction().getFunction();
2738 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
2739 Twine(IsPowI ? "powi" : "ldexp") +
2740 " exponent does not match sizeof(int)",
2741 Fn, N->getDebugLoc()));
2742 if (IsStrict)
2743 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
2744 ReplaceValueWith(From: SDValue(N, 0), To: DAG.getPOISON(VT: N->getValueType(ResNo: 0)));
2745 return SDValue();
2746 }
2747
2748 TargetLowering::MakeLibCallOptions CallOptions;
2749 CallOptions.setIsSigned(true);
2750 SDValue Ops[2] = {N->getOperand(Num: 0 + OpOffset), N->getOperand(Num: 1 + OpOffset)};
2751 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2752 DAG, LibcallImpl: LCImpl, RetVT: N->getValueType(ResNo: 0), Ops, CallOptions, dl: SDLoc(N), Chain);
2753 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
2754 if (IsStrict)
2755 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
2756 return SDValue();
2757}
2758
2759static unsigned getExtendForIntVecReduction(SDNode *N) {
2760 switch (N->getOpcode()) {
2761 default:
2762 llvm_unreachable("Expected integer vector reduction");
2763 case ISD::VECREDUCE_ADD:
2764 case ISD::VECREDUCE_MUL:
2765 case ISD::VECREDUCE_AND:
2766 case ISD::VECREDUCE_OR:
2767 case ISD::VECREDUCE_XOR:
2768 case ISD::VP_REDUCE_ADD:
2769 case ISD::VP_REDUCE_MUL:
2770 case ISD::VP_REDUCE_AND:
2771 case ISD::VP_REDUCE_OR:
2772 case ISD::VP_REDUCE_XOR:
2773 return ISD::ANY_EXTEND;
2774 case ISD::VECREDUCE_SMAX:
2775 case ISD::VECREDUCE_SMIN:
2776 case ISD::VP_REDUCE_SMAX:
2777 case ISD::VP_REDUCE_SMIN:
2778 return ISD::SIGN_EXTEND;
2779 case ISD::VECREDUCE_UMAX:
2780 case ISD::VECREDUCE_UMIN:
2781 case ISD::VP_REDUCE_UMAX:
2782 case ISD::VP_REDUCE_UMIN:
2783 return ISD::ZERO_EXTEND;
2784 }
2785}
2786
2787SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2788 switch (getExtendForIntVecReduction(N)) {
2789 default:
2790 llvm_unreachable("Impossible extension kind for integer reduction");
2791 case ISD::ANY_EXTEND:
2792 return GetPromotedInteger(Op: V);
2793 case ISD::SIGN_EXTEND:
2794 return SExtPromotedInteger(Op: V);
2795 case ISD::ZERO_EXTEND:
2796 return ZExtPromotedInteger(Op: V);
2797 }
2798}
2799
2800SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2801 SDLoc dl(N);
2802 SDValue Op = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
2803
2804 EVT OrigEltVT = N->getOperand(Num: 0).getValueType().getVectorElementType();
2805 EVT InVT = Op.getValueType();
2806 EVT EltVT = InVT.getVectorElementType();
2807 EVT ResVT = N->getValueType(ResNo: 0);
2808 unsigned Opcode = N->getOpcode();
2809
2810 // An i1 vecreduce_xor is equivalent to vecreduce_add, use that instead if
2811 // vecreduce_xor is not legal
2812 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 &&
2813 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_XOR, VT: InVT) &&
2814 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_ADD, VT: InVT))
2815 Opcode = ISD::VECREDUCE_ADD;
2816
2817 // An i1 vecreduce_or is equivalent to vecreduce_umax, use that instead if
2818 // vecreduce_or is not legal
2819 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 &&
2820 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_OR, VT: InVT) &&
2821 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMAX, VT: InVT)) {
2822 Opcode = ISD::VECREDUCE_UMAX;
2823 // Can't use promoteTargetBoolean here because we still need
2824 // to either sign_ext or zero_ext in the undefined case.
2825 switch (TLI.getBooleanContents(Type: InVT)) {
2826 case TargetLoweringBase::UndefinedBooleanContent:
2827 case TargetLoweringBase::ZeroOrOneBooleanContent:
2828 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2829 break;
2830 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2831 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2832 break;
2833 }
2834 }
2835
2836 // An i1 vecreduce_and is equivalent to vecreduce_umin, use that instead if
2837 // vecreduce_and is not legal
2838 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 &&
2839 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_AND, VT: InVT) &&
2840 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMIN, VT: InVT)) {
2841 Opcode = ISD::VECREDUCE_UMIN;
2842 // Can't use promoteTargetBoolean here because we still need
2843 // to either sign_ext or zero_ext in the undefined case.
2844 switch (TLI.getBooleanContents(Type: InVT)) {
2845 case TargetLoweringBase::UndefinedBooleanContent:
2846 case TargetLoweringBase::ZeroOrOneBooleanContent:
2847 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2848 break;
2849 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2850 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2851 break;
2852 }
2853 }
2854
2855 if (ResVT.bitsGE(VT: EltVT))
2856 return DAG.getNode(Opcode, DL: SDLoc(N), VT: ResVT, Operand: Op);
2857
2858 // Result size must be >= element size. If this is not the case after
2859 // promotion, also promote the result type and then truncate.
2860 SDValue Reduce = DAG.getNode(Opcode, DL: dl, VT: EltVT, Operand: Op);
2861 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: ResVT, Operand: Reduce);
2862}
2863
2864SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
2865 SDLoc DL(N);
2866 SDValue Op = N->getOperand(Num: OpNo);
2867 SmallVector<SDValue, 4> NewOps(N->ops());
2868
2869 if (OpNo == 2) { // Mask
2870 // Update in place.
2871 NewOps[2] = PromoteTargetBoolean(Bool: Op, ValVT: N->getOperand(Num: 1).getValueType());
2872 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2873 }
2874
2875 assert(OpNo == 1 && "Unexpected operand for promotion");
2876
2877 Op = PromoteIntOpVectorReduction(N, V: Op);
2878
2879 NewOps[OpNo] = Op;
2880
2881 EVT VT = N->getValueType(ResNo: 0);
2882 EVT EltVT = Op.getValueType().getScalarType();
2883
2884 if (VT.bitsGE(VT: EltVT))
2885 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT, Ops: NewOps);
2886
2887 // Result size must be >= element/start-value size. If this is not the case
2888 // after promotion, also promote both the start value and result type and
2889 // then truncate.
2890 NewOps[0] =
2891 DAG.getNode(Opcode: getExtendForIntVecReduction(N), DL, VT: EltVT, Operand: N->getOperand(Num: 0));
2892 SDValue Reduce = DAG.getNode(Opcode: N->getOpcode(), DL, VT: EltVT, Ops: NewOps);
2893 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT, Operand: Reduce);
2894}
2895
2896SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2897 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2898 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Op), 0);
2899}
2900
2901SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
2902 assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
2903 SmallVector<SDValue> NewOps(N->ops());
2904 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
2905 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2906}
2907
2908SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
2909 assert(OpNo >= 7);
2910 SmallVector<SDValue> NewOps(N->ops());
2911 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
2912 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2913}
2914
2915SDValue DAGTypeLegalizer::PromoteIntOp_WRITE_REGISTER(SDNode *N,
2916 unsigned OpNo) {
2917 const Function &Fn = DAG.getMachineFunction().getFunction();
2918 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
2919 "cannot use llvm.write_register with illegal type", Fn,
2920 N->getDebugLoc()));
2921 return N->getOperand(Num: 0);
2922}
2923
2924SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
2925 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
2926 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
2927
2928 SmallVector<SDValue, 8> NewOps(N->ops());
2929 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2930 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2931 if (Res == N)
2932 return SDValue(Res, 0);
2933
2934 // Update triggered CSE, do our own replacement since caller can't.
2935 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2936 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2937 return SDValue();
2938}
2939
2940SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
2941 SmallVector<SDValue, 6> NewOps(N->ops());
2942
2943 if (OpNo == 2) { // Offset operand
2944 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2945 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2946 }
2947
2948 assert((OpNo == 4 || OpNo == 5) && "Unexpected operand for promotion");
2949
2950 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2951 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2952}
2953
2954SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_HISTOGRAM(SDNode *N,
2955 unsigned OpNo) {
2956 assert(OpNo == 1 && "Unexpected operand for promotion");
2957 SmallVector<SDValue, 7> NewOps(N->ops());
2958 NewOps[1] = GetPromotedInteger(Op: N->getOperand(Num: 1));
2959 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2960}
2961
2962SDValue DAGTypeLegalizer::PromoteIntOp_UnaryBooleanVectorOp(SDNode *N,
2963 unsigned OpNo) {
2964 assert(OpNo == 0 && "Unexpected operand for promotion");
2965 SDValue Op = N->getOperand(Num: 0);
2966
2967 SDValue NewOp;
2968 if (TLI.getBooleanContents(Type: Op.getValueType()) ==
2969 TargetLowering::ZeroOrNegativeOneBooleanContent)
2970 NewOp = SExtPromotedInteger(Op);
2971 else
2972 NewOp = ZExtPromotedInteger(Op);
2973
2974 return SDValue(DAG.UpdateNodeOperands(N, Op: NewOp), 0);
2975}
2976
2977SDValue DAGTypeLegalizer::PromoteIntOp_GET_ACTIVE_LANE_MASK(SDNode *N) {
2978 SmallVector<SDValue, 1> NewOps(N->ops());
2979 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2980 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2981 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2982}
2983
2984SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_MATCH(SDNode *N, unsigned OpNo) {
2985 assert(OpNo < 3 && "Unexpected operand for promotion");
2986 if (OpNo != 2)
2987 return TLI.expandVectorMatch(N, DAG);
2988
2989 SmallVector<SDValue, 3> NewOps(N->ops());
2990 NewOps[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: N->getValueType(ResNo: 0));
2991 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2992}
2993
2994SDValue DAGTypeLegalizer::PromoteIntOp_MaskedBinOp(SDNode *N, unsigned OpNo) {
2995 assert(OpNo == 2);
2996 SmallVector<SDValue, 3> NewOps(N->ops());
2997 NewOps[2] = PromoteTargetBoolean(Bool: NewOps[2], ValVT: N->getValueType(ResNo: 0));
2998 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2999}
3000
3001SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
3002 SmallVector<SDValue, 1> NewOps(N->ops());
3003 switch (N->getOpcode()) {
3004 case ISD::PARTIAL_REDUCE_SMLA:
3005 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3006 NewOps[2] = SExtPromotedInteger(Op: N->getOperand(Num: 2));
3007 break;
3008 case ISD::PARTIAL_REDUCE_UMLA:
3009 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3010 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3011 break;
3012 case ISD::PARTIAL_REDUCE_SUMLA:
3013 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3014 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3015 break;
3016 default:
3017 llvm_unreachable("unexpected opcode");
3018 }
3019 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3020}
3021
3022SDValue DAGTypeLegalizer::PromoteIntOp_LOOP_DEPENDENCE_MASK(SDNode *N) {
3023 SDValue NewOps[4];
3024 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3025 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3026 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3027 NewOps[3] = N->getOperand(Num: 3);
3028 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3029}
3030
3031SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_REPEAT(SDNode *N) {
3032 SDLoc DL(N);
3033 SDValue Src = GetPromotedInteger(Op: N->getOperand(Num: 0));
3034 EVT SrcVT = Src.getValueType();
3035 EVT OrigVT = N->getValueType(ResNo: 0);
3036 EVT NewVT = OrigVT.changeVectorElementType(Context&: *DAG.getContext(),
3037 EltVT: SrcVT.getVectorElementType());
3038 SDValue Res = DAG.getNode(Opcode: ISD::VECTOR_REPEAT, DL, VT: NewVT, Operand: Src);
3039 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: OrigVT, Operand: Res);
3040}
3041
3042//===----------------------------------------------------------------------===//
3043// Integer Result Expansion
3044//===----------------------------------------------------------------------===//
3045
3046/// ExpandIntegerResult - This method is called when the specified result of the
3047/// specified node is found to need expansion. At this point, the node may also
3048/// have invalid operands or may have other results that need promotion, we just
3049/// know that (at least) one result needs expansion.
3050void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
3051 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG));
3052 SDValue Lo, Hi;
3053 Lo = Hi = SDValue();
3054
3055 // See if the target wants to custom expand this node.
3056 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true))
3057 return;
3058
3059 switch (N->getOpcode()) {
3060 default:
3061#ifndef NDEBUG
3062 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
3063 N->dump(&DAG); dbgs() << "\n";
3064#endif
3065 report_fatal_error(reason: "do not know how to expand the result of this "
3066 "operator!");
3067
3068 case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
3069 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
3070 case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
3071 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
3072 case ISD::POISON:
3073 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
3074 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
3075 case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;
3076
3077 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
3078 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
3079 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
3080 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
3081 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
3082
3083 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
3084 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
3085 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
3086 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
3087 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
3088 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
3089 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
3090 case ISD::ABS:
3091 case ISD::ABS_MIN_POISON:
3092 ExpandIntRes_ABS(N, Lo, Hi);
3093 break;
3094 case ISD::ABDS:
3095 case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
3096 case ISD::CTLZ_ZERO_POISON:
3097 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
3098 case ISD::CTLS: ExpandIntRes_CTLS(N, Lo, Hi); break;
3099 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
3100 case ISD::CTTZ_ZERO_POISON:
3101 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
3102 case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
3103 case ISD::STRICT_FP_TO_SINT:
3104 case ISD::FP_TO_SINT:
3105 case ISD::STRICT_FP_TO_UINT:
3106 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_XINT(N, Lo, Hi); break;
3107 case ISD::FP_TO_SINT_SAT:
3108 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
3109 case ISD::STRICT_LROUND:
3110 case ISD::STRICT_LRINT:
3111 case ISD::LROUND:
3112 case ISD::LRINT:
3113 case ISD::STRICT_LLROUND:
3114 case ISD::STRICT_LLRINT:
3115 case ISD::LLROUND:
3116 case ISD::LLRINT: ExpandIntRes_XROUND_XRINT(N, Lo, Hi); break;
3117 case ISD::LOAD: ExpandIntRes_LOAD(N: cast<LoadSDNode>(Val: N), Lo, Hi); break;
3118 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
3119 case ISD::READCYCLECOUNTER:
3120 case ISD::READSTEADYCOUNTER: ExpandIntRes_READCOUNTER(N, Lo, Hi); break;
3121 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
3122 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
3123 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
3124 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
3125 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
3126 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
3127 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
3128 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
3129 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
3130
3131 case ISD::ATOMIC_LOAD_ADD:
3132 case ISD::ATOMIC_LOAD_SUB:
3133 case ISD::ATOMIC_LOAD_AND:
3134 case ISD::ATOMIC_LOAD_CLR:
3135 case ISD::ATOMIC_LOAD_OR:
3136 case ISD::ATOMIC_LOAD_XOR:
3137 case ISD::ATOMIC_LOAD_NAND:
3138 case ISD::ATOMIC_LOAD_MIN:
3139 case ISD::ATOMIC_LOAD_MAX:
3140 case ISD::ATOMIC_LOAD_UMIN:
3141 case ISD::ATOMIC_LOAD_UMAX:
3142 case ISD::ATOMIC_SWAP:
3143 case ISD::ATOMIC_CMP_SWAP: {
3144 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node: N);
3145 SplitInteger(Op: Tmp.first, Lo, Hi);
3146 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
3147 break;
3148 }
3149 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3150 AtomicSDNode *AN = cast<AtomicSDNode>(Val: N);
3151 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: MVT::Other);
3152 SDValue Tmp = DAG.getAtomicCmpSwap(
3153 Opcode: ISD::ATOMIC_CMP_SWAP, dl: SDLoc(N), MemVT: AN->getMemoryVT(), VTs,
3154 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 1), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
3155 MMO: AN->getMemOperand());
3156
3157 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
3158 // success simply by comparing the loaded value against the ingoing
3159 // comparison.
3160 SDValue Success = DAG.getSetCC(DL: SDLoc(N), VT: N->getValueType(ResNo: 1), LHS: Tmp,
3161 RHS: N->getOperand(Num: 2), Cond: ISD::SETEQ);
3162
3163 SplitInteger(Op: Tmp, Lo, Hi);
3164 ReplaceValueWith(From: SDValue(N, 1), To: Success);
3165 ReplaceValueWith(From: SDValue(N, 2), To: Tmp.getValue(R: 1));
3166 break;
3167 }
3168
3169 case ISD::AND:
3170 case ISD::OR:
3171 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
3172
3173 case ISD::UMAX:
3174 case ISD::SMAX:
3175 case ISD::UMIN:
3176 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
3177
3178 case ISD::SCMP:
3179 case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
3180
3181 case ISD::ADD:
3182 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
3183
3184 case ISD::ADDC:
3185 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
3186
3187 case ISD::ADDE:
3188 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
3189
3190 case ISD::UADDO_CARRY:
3191 case ISD::USUBO_CARRY: ExpandIntRes_UADDSUBO_CARRY(N, Lo, Hi); break;
3192
3193 case ISD::SADDO_CARRY:
3194 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
3195
3196 case ISD::SHL:
3197 case ISD::SRA:
3198 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
3199
3200 case ISD::SADDO:
3201 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
3202 case ISD::UADDO:
3203 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
3204 case ISD::UMULO:
3205 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3206
3207 case ISD::SADDSAT:
3208 case ISD::UADDSAT:
3209 case ISD::SSUBSAT:
3210 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
3211
3212 case ISD::SSHLSAT:
3213 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
3214
3215 case ISD::AVGCEILS:
3216 case ISD::AVGCEILU:
3217 case ISD::AVGFLOORS:
3218 case ISD::AVGFLOORU: ExpandIntRes_AVG(N, Lo, Hi); break;
3219
3220 case ISD::SMULFIX:
3221 case ISD::SMULFIXSAT:
3222 case ISD::UMULFIX:
3223 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
3224
3225 case ISD::SDIVFIX:
3226 case ISD::SDIVFIXSAT:
3227 case ISD::UDIVFIX:
3228 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
3229
3230 case ISD::VECREDUCE_ADD:
3231 case ISD::VECREDUCE_MUL:
3232 case ISD::VECREDUCE_AND:
3233 case ISD::VECREDUCE_OR:
3234 case ISD::VECREDUCE_XOR:
3235 case ISD::VECREDUCE_SMAX:
3236 case ISD::VECREDUCE_SMIN:
3237 case ISD::VECREDUCE_UMAX:
3238 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
3239
3240 case ISD::ROTL:
3241 case ISD::ROTR:
3242 ExpandIntRes_Rotate(N, Lo, Hi);
3243 break;
3244
3245 case ISD::FSHL:
3246 case ISD::FSHR:
3247 ExpandIntRes_FunnelShift(N, Lo, Hi);
3248 break;
3249
3250 case ISD::CLMUL:
3251 case ISD::CLMULR:
3252 case ISD::CLMULH:
3253 ExpandIntRes_CLMUL(N, Lo, Hi);
3254 break;
3255
3256 case ISD::PEXT:
3257 ExpandIntRes_PEXT(N, Lo, Hi);
3258 break;
3259
3260 case ISD::PDEP:
3261 ExpandIntRes_PDEP(N, Lo, Hi);
3262 break;
3263
3264 case ISD::MULHS:
3265 case ISD::MULHU:
3266 ExpandIntRes_MULH(N, Lo, Hi);
3267 break;
3268
3269 case ISD::VSCALE:
3270 ExpandIntRes_VSCALE(N, Lo, Hi);
3271 break;
3272
3273 case ISD::READ_REGISTER:
3274 ExpandIntRes_READ_REGISTER(N, Lo, Hi);
3275 break;
3276
3277 case ISD::CTTZ_ELTS:
3278 case ISD::CTTZ_ELTS_ZERO_POISON:
3279 ExpandIntRes_CTTZ_ELTS(N, Lo, Hi);
3280 break;
3281 }
3282
3283 // If Lo/Hi is null, the sub-method took care of registering results etc.
3284 if (Lo.getNode())
3285 SetExpandedInteger(Op: SDValue(N, ResNo), Lo, Hi);
3286}
3287
3288/// Lower an atomic node to the appropriate builtin call.
3289std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
3290 unsigned Opc = Node->getOpcode();
3291 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
3292 AtomicOrdering order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
3293 // Lower to outline atomic libcall if outline atomics enabled,
3294 // or to sync libcall otherwise
3295 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order: order, VT);
3296 EVT RetVT = Node->getValueType(ResNo: 0);
3297 TargetLowering::MakeLibCallOptions CallOptions;
3298 SmallVector<SDValue, 4> Ops;
3299
3300 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3301 if (LCImpl != RTLIB::Unsupported) {
3302 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
3303 Ops.push_back(Elt: Node->getOperand(Num: 1));
3304 } else {
3305 LC = RTLIB::getSYNC(Opc, VT);
3306 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3307 "Unexpected atomic op or value type!");
3308 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
3309 LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3310 }
3311 return TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT, Ops, CallOptions, dl: SDLoc(Node),
3312 Chain: Node->getOperand(Num: 0));
3313}
3314
3315/// N is a shift by a value that needs to be expanded,
3316/// and the shift amount is a constant 'Amt'. Expand the operation.
3317void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
3318 SDValue &Lo, SDValue &Hi) {
3319 SDLoc DL(N);
3320 // Expand the incoming operand to be shifted, so that we have its parts
3321 SDValue InL, InH;
3322 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3323
3324 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
3325 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
3326 if (!Amt) {
3327 Lo = InL;
3328 Hi = InH;
3329 return;
3330 }
3331
3332 EVT NVT = InL.getValueType();
3333 unsigned VTBits = N->getValueType(ResNo: 0).getSizeInBits();
3334 unsigned NVTBits = NVT.getSizeInBits();
3335
3336 if (N->getOpcode() == ISD::SHL) {
3337 if (Amt.uge(RHS: VTBits)) {
3338 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3339 } else if (Amt.ugt(RHS: NVTBits)) {
3340 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3341 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3342 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3343 } else if (Amt == NVTBits) {
3344 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3345 Hi = InL;
3346 } else {
3347 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3348 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3349 // Use FSHL if legal so we don't need to combine it later.
3350 if (TLI.isOperationLegal(Op: ISD::FSHL, VT: NVT)) {
3351 Hi = DAG.getNode(Opcode: ISD::FSHL, DL, VT: NVT, N1: InH, N2: InL,
3352 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3353 } else {
3354 Hi = DAG.getNode(
3355 Opcode: ISD::OR, DL, VT: NVT,
3356 N1: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3357 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3358 N2: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3359 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3360 }
3361 }
3362 return;
3363 }
3364
3365 if (N->getOpcode() == ISD::SRL) {
3366 if (Amt.uge(RHS: VTBits)) {
3367 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3368 } else if (Amt.ugt(RHS: NVTBits)) {
3369 Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3370 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3371 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3372 } else if (Amt == NVTBits) {
3373 Lo = InH;
3374 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3375 } else {
3376 // Use FSHR if legal so we don't need to combine it later.
3377 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3378 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3379 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3380 } else {
3381 Lo = DAG.getNode(
3382 Opcode: ISD::OR, DL, VT: NVT,
3383 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3384 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3385 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3386 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3387 }
3388 Hi = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3389 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3390 }
3391 return;
3392 }
3393
3394 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3395 if (Amt.uge(RHS: VTBits)) {
3396 Hi = Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3397 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3398 } else if (Amt.ugt(RHS: NVTBits)) {
3399 Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3400 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3401 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3402 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3403 } else if (Amt == NVTBits) {
3404 Lo = InH;
3405 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3406 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3407 } else {
3408 // Use FSHR if legal so we don't need to combine it later.
3409 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3410 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3411 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3412 } else {
3413 Lo = DAG.getNode(
3414 Opcode: ISD::OR, DL, VT: NVT,
3415 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3416 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3417 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3418 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3419 }
3420 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3421 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3422 }
3423}
3424
3425/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
3426/// this shift based on knowledge of the high bit of the shift amount. If we
3427/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
3428/// shift amount.
3429bool DAGTypeLegalizer::
3430ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3431 unsigned Opc = N->getOpcode();
3432 SDValue In = N->getOperand(Num: 0);
3433 SDValue Amt = N->getOperand(Num: 1);
3434 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3435 EVT ShTy = Amt.getValueType();
3436 unsigned ShBits = ShTy.getScalarSizeInBits();
3437 unsigned NVTBits = NVT.getScalarSizeInBits();
3438 assert(isPowerOf2_32(NVTBits) &&
3439 "Expanded integer type size not a power of two!");
3440 SDLoc dl(N);
3441
3442 APInt HighBitMask = APInt::getHighBitsSet(numBits: ShBits, hiBitsSet: ShBits - Log2_32(Value: NVTBits));
3443 KnownBits Known = DAG.computeKnownBits(Op: Amt);
3444
3445 // If we don't know anything about the high bits, exit.
3446 if (((Known.Zero | Known.One) & HighBitMask) == 0)
3447 return false;
3448
3449 // Get the incoming operand to be shifted.
3450 SDValue InL, InH;
3451 GetExpandedInteger(Op: In, Lo&: InL, Hi&: InH);
3452
3453 // If we know that any of the high bits of the shift amount are one, then we
3454 // can do this as a couple of simple shifts.
3455 if (Known.One.intersects(RHS: HighBitMask)) {
3456 // Mask out the high bit, which we know is set.
3457 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShTy, N1: Amt,
3458 N2: DAG.getConstant(Val: ~HighBitMask, DL: dl, VT: ShTy));
3459
3460 switch (Opc) {
3461 default: llvm_unreachable("Unknown shift");
3462 case ISD::SHL:
3463 Lo = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Low part is zero.
3464 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt); // High part from Lo part.
3465 return true;
3466 case ISD::SRL:
3467 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3468 Lo = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3469 return true;
3470 case ISD::SRA:
3471 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign extend high part.
3472 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3473 Lo = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3474 return true;
3475 }
3476 }
3477
3478 // If we know that all of the high bits of the shift amount are zero, then we
3479 // can do this as a couple of simple shifts.
3480 if (HighBitMask.isSubsetOf(RHS: Known.Zero)) {
3481 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
3482 // shift if x is zero. We can use XOR here because x is known to be smaller
3483 // than 32.
3484 SDValue Amt2 = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: ShTy, N1: Amt,
3485 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3486
3487 unsigned Op1, Op2;
3488 switch (Opc) {
3489 default: llvm_unreachable("Unknown shift");
3490 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
3491 case ISD::SRL:
3492 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
3493 }
3494
3495 // When shifting right the arithmetic for Lo and Hi is swapped.
3496 if (Opc != ISD::SHL)
3497 std::swap(a&: InL, b&: InH);
3498
3499 // Use a little trick to get the bits that move from Lo to Hi. First
3500 // shift by one bit.
3501 SDValue Sh1 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: InL, N2: DAG.getConstant(Val: 1, DL: dl, VT: ShTy));
3502 // Then compute the remaining shift with amount-1.
3503 SDValue Sh2 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: Sh1, N2: Amt2);
3504
3505 Lo = DAG.getNode(Opcode: Opc, DL: dl, VT: NVT, N1: InL, N2: Amt);
3506 Hi = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: Op1, DL: dl, VT: NVT, N1: InH, N2: Amt),N2: Sh2);
3507
3508 if (Opc != ISD::SHL)
3509 std::swap(a&: Hi, b&: Lo);
3510 return true;
3511 }
3512
3513 return false;
3514}
3515
3516/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
3517/// of any size.
3518bool DAGTypeLegalizer::
3519ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3520 SDValue Amt = N->getOperand(Num: 1);
3521 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3522 EVT ShTy = Amt.getValueType();
3523 unsigned NVTBits = NVT.getSizeInBits();
3524 assert(isPowerOf2_32(NVTBits) &&
3525 "Expanded integer type size not a power of two!");
3526 SDLoc dl(N);
3527
3528 // Get the incoming operand to be shifted.
3529 SDValue InL, InH;
3530 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3531
3532 SDValue NVBitsNode = DAG.getConstant(Val: NVTBits, DL: dl, VT: ShTy);
3533 SDValue AmtExcess = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: Amt, N2: NVBitsNode);
3534 SDValue AmtLack = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: NVBitsNode, N2: Amt);
3535 SDValue isShort = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3536 LHS: Amt, RHS: NVBitsNode, Cond: ISD::SETULT);
3537 SDValue isZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3538 LHS: Amt, RHS: DAG.getConstant(Val: 0, DL: dl, VT: ShTy),
3539 Cond: ISD::SETEQ);
3540
3541 SDValue LoS, HiS, LoL, HiL;
3542 switch (N->getOpcode()) {
3543 default: llvm_unreachable("Unknown shift");
3544 case ISD::SHL:
3545 // Short: ShAmt < NVTBits
3546 LoS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt);
3547 HiS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3548 N1: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: Amt),
3549 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: AmtLack));
3550
3551 // Long: ShAmt >= NVTBits
3552 LoL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Lo part is zero.
3553 HiL = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: AmtExcess); // Hi from Lo part.
3554
3555 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL);
3556 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InH,
3557 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL));
3558 return true;
3559 case ISD::SRL:
3560 // Short: ShAmt < NVTBits
3561 HiS = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt);
3562 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3563 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3564 // FIXME: If Amt is zero, the following shift generates an undefined result
3565 // on some architectures.
3566 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3567
3568 // Long: ShAmt >= NVTBits
3569 HiL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3570 LoL = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3571
3572 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3573 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3574 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3575 return true;
3576 case ISD::SRA:
3577 // Short: ShAmt < NVTBits
3578 HiS = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt);
3579 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3580 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3581 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3582
3583 // Long: ShAmt >= NVTBits
3584 HiL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign of Hi part.
3585 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3586 LoL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3587
3588 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3589 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3590 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3591 return true;
3592 }
3593}
3594
3595static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
3596
3597 switch (Op) {
3598 default: llvm_unreachable("invalid min/max opcode");
3599 case ISD::SMAX:
3600 return std::make_pair(x: ISD::SETGT, y: ISD::UMAX);
3601 case ISD::UMAX:
3602 return std::make_pair(x: ISD::SETUGT, y: ISD::UMAX);
3603 case ISD::SMIN:
3604 return std::make_pair(x: ISD::SETLT, y: ISD::UMIN);
3605 case ISD::UMIN:
3606 return std::make_pair(x: ISD::SETULT, y: ISD::UMIN);
3607 }
3608}
3609
3610void DAGTypeLegalizer::ExpandIntRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
3611 SDLoc DL(N);
3612
3613 SDValue LHS = N->getOperand(Num: 0);
3614 SDValue RHS = N->getOperand(Num: 1);
3615 EVT NewVT = getSetCCResultType(VT: LHS.getValueType());
3616
3617 // Taking the same approach as ScalarizeVecRes_SETCC
3618 SDValue Res = DAG.getNode(Opcode: ISD::SETCC, DL, VT: NewVT, N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
3619
3620 Res = DAG.getBoolExtOrTrunc(Op: Res, SL: DL, VT: N->getValueType(ResNo: 0), OpVT: NewVT);
3621 SplitInteger(Op: Res, Lo, Hi);
3622}
3623
3624void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
3625 SDValue &Lo, SDValue &Hi) {
3626 SDLoc DL(N);
3627
3628 SDValue LHS = N->getOperand(Num: 0);
3629 SDValue RHS = N->getOperand(Num: 1);
3630
3631 // If the upper halves are all sign bits, then we can perform the MINMAX on
3632 // the lower half and sign-extend the result to the upper half.
3633 unsigned NumBits = N->getValueType(ResNo: 0).getScalarSizeInBits();
3634 unsigned NumHalfBits = NumBits / 2;
3635 if (DAG.ComputeNumSignBits(Op: LHS) > NumHalfBits &&
3636 DAG.ComputeNumSignBits(Op: RHS) > NumHalfBits) {
3637 SDValue LHSL, LHSH, RHSL, RHSH;
3638 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3639 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3640 EVT NVT = LHSL.getValueType();
3641
3642 Lo = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: LHSL, N2: RHSL);
3643 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: Lo,
3644 N2: DAG.getShiftAmountConstant(Val: NumHalfBits - 1, VT: NVT, DL));
3645 return;
3646 }
3647
3648 // The Lo of smin(X, -1) is LHSL if X is negative. Otherwise it's -1.
3649 // The Lo of smax(X, 0) is 0 if X is negative. Otherwise it's LHSL.
3650 if ((N->getOpcode() == ISD::SMAX && isNullConstant(V: RHS)) ||
3651 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(V: RHS))) {
3652 SDValue LHSL, LHSH, RHSL, RHSH;
3653 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3654 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3655 EVT NVT = LHSL.getValueType();
3656 EVT CCT = getSetCCResultType(VT: NVT);
3657
3658 SDValue HiNeg =
3659 DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: DAG.getConstant(Val: 0, DL, VT: NVT), Cond: ISD::SETLT);
3660 if (N->getOpcode() == ISD::SMIN) {
3661 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: LHSL, RHS: DAG.getAllOnesConstant(DL, VT: NVT));
3662 } else {
3663 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: DAG.getConstant(Val: 0, DL, VT: NVT), RHS: LHSL);
3664 }
3665 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3666 return;
3667 }
3668
3669 const APInt *RHSVal = nullptr;
3670 if (auto *RHSConst = dyn_cast<ConstantSDNode>(Val&: RHS))
3671 RHSVal = &RHSConst->getAPIntValue();
3672
3673 // The high half of MIN/MAX is always just the the MIN/MAX of the
3674 // high halves of the operands. Expand this way if it appears profitable.
3675 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) &&
3676 (RHSVal->countLeadingOnes() >= NumHalfBits ||
3677 RHSVal->countLeadingZeros() >= NumHalfBits)) {
3678 SDValue LHSL, LHSH, RHSL, RHSH;
3679 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3680 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3681 EVT NVT = LHSL.getValueType();
3682 EVT CCT = getSetCCResultType(VT: NVT);
3683
3684 ISD::NodeType LoOpc;
3685 ISD::CondCode CondC;
3686 std::tie(args&: CondC, args&: LoOpc) = getExpandedMinMaxOps(Op: N->getOpcode());
3687
3688 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3689 // We need to know whether to select Lo part that corresponds to 'winning'
3690 // Hi part or if Hi parts are equal.
3691 SDValue IsHiLeft = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: CondC);
3692 SDValue IsHiEq = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: ISD::SETEQ);
3693
3694 // Lo part corresponding to the 'winning' Hi part
3695 SDValue LoCmp = DAG.getSelect(DL, VT: NVT, Cond: IsHiLeft, LHS: LHSL, RHS: RHSL);
3696
3697 // Recursed Lo part if Hi parts are equal, this uses unsigned version
3698 SDValue LoMinMax = DAG.getNode(Opcode: LoOpc, DL, VT: NVT, Ops: {LHSL, RHSL});
3699
3700 Lo = DAG.getSelect(DL, VT: NVT, Cond: IsHiEq, LHS: LoMinMax, RHS: LoCmp);
3701 return;
3702 }
3703
3704 // Expand to "a < b ? a : b" etc. Prefer ge/le if that simplifies
3705 // the compare.
3706 ISD::CondCode Pred;
3707 switch (N->getOpcode()) {
3708 default: llvm_unreachable("How did we get here?");
3709 case ISD::SMAX:
3710 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3711 Pred = ISD::SETGE;
3712 else
3713 Pred = ISD::SETGT;
3714 break;
3715 case ISD::SMIN:
3716 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3717 Pred = ISD::SETLE;
3718 else
3719 Pred = ISD::SETLT;
3720 break;
3721 case ISD::UMAX:
3722 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3723 Pred = ISD::SETUGE;
3724 else
3725 Pred = ISD::SETUGT;
3726 break;
3727 case ISD::UMIN:
3728 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3729 Pred = ISD::SETULE;
3730 else
3731 Pred = ISD::SETULT;
3732 break;
3733 }
3734 EVT VT = N->getValueType(ResNo: 0);
3735 EVT CCT = getSetCCResultType(VT);
3736 SDValue Cond = DAG.getSetCC(DL, VT: CCT, LHS, RHS, Cond: Pred);
3737 SDValue Result = DAG.getSelect(DL, VT, Cond, LHS, RHS);
3738 SplitInteger(Op: Result, Lo, Hi);
3739}
3740
3741void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
3742 SDValue ExpandedCMP = TLI.expandCMP(Node: N, DAG);
3743 SplitInteger(Op: ExpandedCMP, Lo, Hi);
3744}
3745
3746void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
3747 SDValue &Lo, SDValue &Hi) {
3748 SDLoc dl(N);
3749 // Expand the subcomponents.
3750 SDValue LHSL, LHSH, RHSL, RHSH;
3751 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3752 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3753
3754 EVT NVT = LHSL.getValueType();
3755 SDValue LoOps[2] = { LHSL, RHSL };
3756 SDValue HiOps[3] = { LHSH, RHSH };
3757
3758 bool HasOpCarry = TLI.isOperationLegalOrCustom(
3759 Op: N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
3760 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3761 if (HasOpCarry) {
3762 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
3763 if (N->getOpcode() == ISD::ADD) {
3764 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3765 HiOps[2] = Lo.getValue(R: 1);
3766 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3767 ? DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3768 : DAG.getNode(Opcode: ISD::UADDO_CARRY, DL: dl, VTList, Ops: HiOps);
3769 } else {
3770 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3771 HiOps[2] = Lo.getValue(R: 1);
3772 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3773 ? DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3774 : DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, Ops: HiOps);
3775 }
3776 return;
3777 }
3778
3779 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
3780 // them. TODO: Teach operation legalization how to expand unsupported
3781 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
3782 // a carry of type MVT::Glue, but there doesn't seem to be any way to
3783 // generate a value of this type in the expanded code sequence.
3784 bool hasCarry =
3785 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3786 ISD::ADDC : ISD::SUBC,
3787 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3788
3789 if (hasCarry) {
3790 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: MVT::Glue);
3791 if (N->getOpcode() == ISD::ADD) {
3792 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3793 HiOps[2] = Lo.getValue(R: 1);
3794 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3795 } else {
3796 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3797 HiOps[2] = Lo.getValue(R: 1);
3798 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3799 }
3800 return;
3801 }
3802
3803 bool hasOVF =
3804 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3805 ISD::UADDO : ISD::USUBO,
3806 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3807 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(Type: NVT);
3808
3809 if (hasOVF) {
3810 EVT OvfVT = getSetCCResultType(VT: NVT);
3811 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: OvfVT);
3812 int RevOpc;
3813 if (N->getOpcode() == ISD::ADD) {
3814 RevOpc = ISD::SUB;
3815 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3816 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3817 } else {
3818 RevOpc = ISD::ADD;
3819 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3820 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3821 }
3822 SDValue OVF = Lo.getValue(R: 1);
3823
3824 switch (BoolType) {
3825 case TargetLoweringBase::UndefinedBooleanContent:
3826 OVF = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: OvfVT, N1: DAG.getConstant(Val: 1, DL: dl, VT: OvfVT), N2: OVF);
3827 [[fallthrough]];
3828 case TargetLoweringBase::ZeroOrOneBooleanContent:
3829 OVF = DAG.getZExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3830 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Hi, N2: OVF);
3831 break;
3832 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3833 OVF = DAG.getSExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3834 Hi = DAG.getNode(Opcode: RevOpc, DL: dl, VT: NVT, N1: Hi, N2: OVF);
3835 }
3836 return;
3837 }
3838
3839 if (N->getOpcode() == ISD::ADD) {
3840 Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: LoOps);
3841 SDValue Cmp;
3842 // Special case: X+1 has a carry out if X+1==0. This may reduce the live
3843 // range of X. We assume comparing with 0 is cheap.
3844 if (isOneConstant(V: LoOps[1]))
3845 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
3846 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3847 else if (isAllOnesConstant(V: LoOps[1])) {
3848 if (isAllOnesConstant(V: HiOps[1]))
3849 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3850 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3851 else
3852 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3853 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
3854 } else
3855 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo, RHS: LoOps[0],
3856 Cond: ISD::SETULT);
3857
3858 SDValue Carry;
3859 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3860 Carry = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3861 else
3862 Carry = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3863 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3864
3865 if (isAllOnesConstant(V: LoOps[1]) && isAllOnesConstant(V: HiOps[1])) {
3866 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: HiOps[0], N2: Carry);
3867 } else {
3868 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3869 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Hi, N2: Carry);
3870 }
3871 } else {
3872 Lo = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: LoOps);
3873 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3874 SDValue Cmp =
3875 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LoOps[0].getValueType()),
3876 LHS: LoOps[0], RHS: LoOps[1], Cond: ISD::SETULT);
3877
3878 SDValue Borrow;
3879 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3880 Borrow = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3881 else
3882 Borrow = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3883 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3884
3885 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Hi, N2: Borrow);
3886 }
3887}
3888
3889void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
3890 SDValue &Lo, SDValue &Hi) {
3891 // Expand the subcomponents.
3892 SDValue LHSL, LHSH, RHSL, RHSH;
3893 SDLoc dl(N);
3894 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3895 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3896 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3897 SDValue LoOps[2] = { LHSL, RHSL };
3898 SDValue HiOps[3] = { LHSH, RHSH };
3899
3900 if (N->getOpcode() == ISD::ADDC) {
3901 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3902 HiOps[2] = Lo.getValue(R: 1);
3903 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3904 } else {
3905 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3906 HiOps[2] = Lo.getValue(R: 1);
3907 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3908 }
3909
3910 // Legalized the flag result - switch anything that used the old flag to
3911 // use the new one.
3912 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3913}
3914
3915void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
3916 SDValue &Lo, SDValue &Hi) {
3917 // Expand the subcomponents.
3918 SDValue LHSL, LHSH, RHSL, RHSH;
3919 SDLoc dl(N);
3920 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3921 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3922 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3923 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3924 SDValue HiOps[3] = { LHSH, RHSH };
3925
3926 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3927 HiOps[2] = Lo.getValue(R: 1);
3928 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
3929
3930 // Legalized the flag result - switch anything that used the old flag to
3931 // use the new one.
3932 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3933}
3934
3935void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
3936 SDValue &Lo, SDValue &Hi) {
3937 SDValue LHS = N->getOperand(Num: 0);
3938 SDValue RHS = N->getOperand(Num: 1);
3939 SDLoc dl(N);
3940
3941 SDValue Ovf;
3942
3943 unsigned CarryOp, NoCarryOp;
3944 ISD::CondCode Cond;
3945 switch(N->getOpcode()) {
3946 case ISD::UADDO:
3947 CarryOp = ISD::UADDO_CARRY;
3948 NoCarryOp = ISD::ADD;
3949 Cond = ISD::SETULT;
3950 break;
3951 case ISD::USUBO:
3952 CarryOp = ISD::USUBO_CARRY;
3953 NoCarryOp = ISD::SUB;
3954 Cond = ISD::SETUGT;
3955 break;
3956 default:
3957 llvm_unreachable("Node has unexpected Opcode");
3958 }
3959
3960 bool HasCarryOp = TLI.isOperationLegalOrCustom(
3961 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
3962
3963 if (HasCarryOp) {
3964 // Expand the subcomponents.
3965 SDValue LHSL, LHSH, RHSL, RHSH;
3966 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3967 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3968 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3969 SDValue LoOps[2] = { LHSL, RHSL };
3970 SDValue HiOps[3] = { LHSH, RHSH };
3971
3972 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3973 HiOps[2] = Lo.getValue(R: 1);
3974 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: HiOps);
3975
3976 Ovf = Hi.getValue(R: 1);
3977 } else {
3978 // Expand the result by simply replacing it with the equivalent
3979 // non-overflow-checking operation.
3980 SDValue Sum = DAG.getNode(Opcode: NoCarryOp, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS);
3981 SplitInteger(Op: Sum, Lo, Hi);
3982
3983 if (N->getOpcode() == ISD::UADDO && isOneConstant(V: RHS)) {
3984 // Special case: uaddo X, 1 overflowed if X+1 == 0. We can detect this
3985 // with (Lo | Hi) == 0.
3986 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Lo.getValueType(), N1: Lo, N2: Hi);
3987 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Or,
3988 RHS: DAG.getConstant(Val: 0, DL: dl, VT: Lo.getValueType()), Cond: ISD::SETEQ);
3989 } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(V: RHS)) {
3990 // Special case: uaddo X, -1 overflows if X == 0.
3991 Ovf =
3992 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS,
3993 RHS: DAG.getConstant(Val: 0, DL: dl, VT: LHS.getValueType()), Cond: ISD::SETNE);
3994 } else {
3995 // Calculate the overflow: addition overflows iff a + b < a, and
3996 // subtraction overflows iff a - b > a.
3997 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Sum, RHS: LHS, Cond);
3998 }
3999 }
4000
4001 // Legalized the flag result - switch anything that used the old flag to
4002 // use the new one.
4003 ReplaceValueWith(From: SDValue(N, 1), To: Ovf);
4004}
4005
4006void DAGTypeLegalizer::ExpandIntRes_UADDSUBO_CARRY(SDNode *N, SDValue &Lo,
4007 SDValue &Hi) {
4008 // Expand the subcomponents.
4009 SDValue LHSL, LHSH, RHSL, RHSH;
4010 SDLoc dl(N);
4011 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4012 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4013 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4014 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
4015 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
4016
4017 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
4018 HiOps[2] = Lo.getValue(R: 1);
4019 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
4020
4021 // Legalized the flag result - switch anything that used the old flag to
4022 // use the new one.
4023 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4024}
4025
4026void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
4027 SDValue &Lo, SDValue &Hi) {
4028 // Expand the subcomponents.
4029 SDValue LHSL, LHSH, RHSL, RHSH;
4030 SDLoc dl(N);
4031 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4032 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4033 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4034
4035 // We need to use an unsigned carry op for the lo part.
4036 unsigned CarryOp =
4037 N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
4038 Lo = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSL, RHSL, N->getOperand(Num: 2) });
4039 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4040
4041 // Legalized the flag result - switch anything that used the old flag to
4042 // use the new one.
4043 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4044}
4045
4046void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
4047 SDValue &Lo, SDValue &Hi) {
4048 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4049 SDLoc dl(N);
4050 SDValue Op = N->getOperand(Num: 0);
4051 if (Op.getValueType().bitsLE(VT: NVT)) {
4052 // The low part is any extension of the input (which degenerates to a copy).
4053 Lo = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Op);
4054 Hi = DAG.getUNDEF(VT: NVT); // The high part is undefined.
4055 } else {
4056 // For example, extension of an i48 to an i64. The operand type necessarily
4057 // promotes to the result type, so will end up being expanded too.
4058 assert(getTypeAction(Op.getValueType()) ==
4059 TargetLowering::TypePromoteInteger &&
4060 "Only know how to promote this result!");
4061 SDValue Res = GetPromotedInteger(Op);
4062 assert(Res.getValueType() == N->getValueType(0) &&
4063 "Operand over promoted?");
4064 // Split the promoted operand. This will simplify when it is expanded.
4065 SplitInteger(Op: Res, Lo, Hi);
4066 }
4067}
4068
4069void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
4070 SDValue &Lo, SDValue &Hi) {
4071 SDLoc dl(N);
4072 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4073 EVT NVT = Lo.getValueType();
4074 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4075 unsigned NVTBits = NVT.getSizeInBits();
4076 unsigned EVTBits = EVT.getSizeInBits();
4077
4078 if (NVTBits < EVTBits) {
4079 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Hi,
4080 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4081 BitWidth: EVTBits - NVTBits)));
4082 } else {
4083 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4084 // The high part replicates the sign bit of Lo, make it explicit.
4085 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4086 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL: dl));
4087 }
4088}
4089
4090void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
4091 SDValue &Lo, SDValue &Hi) {
4092 SDLoc dl(N);
4093 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4094 EVT NVT = Lo.getValueType();
4095 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4096 unsigned NVTBits = NVT.getSizeInBits();
4097 unsigned EVTBits = EVT.getSizeInBits();
4098
4099 if (NVTBits < EVTBits) {
4100 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Hi,
4101 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4102 BitWidth: EVTBits - NVTBits)));
4103 } else {
4104 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4105 // The high part must be zero, make it explicit.
4106 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4107 }
4108}
4109
4110void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
4111 SDValue &Lo, SDValue &Hi) {
4112 SDLoc dl(N);
4113 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4114 Lo = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4115 Hi = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4116}
4117
4118void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
4119 SDValue &Lo, SDValue &Hi) {
4120 SDLoc dl(N);
4121 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4122 Lo = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4123 Hi = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4124}
4125
4126void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
4127 SDValue &Hi) {
4128 SDLoc dl(N);
4129 // parity(HiLo) -> parity(Lo^Hi)
4130 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4131 EVT NVT = Lo.getValueType();
4132 Lo =
4133 DAG.getNode(Opcode: ISD::PARITY, DL: dl, VT: NVT, Operand: DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Hi));
4134 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4135}
4136
4137void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
4138 SDValue &Lo, SDValue &Hi) {
4139 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4140 unsigned NBitWidth = NVT.getSizeInBits();
4141 auto Constant = cast<ConstantSDNode>(Val: N);
4142 const APInt &Cst = Constant->getAPIntValue();
4143 bool IsTarget = Constant->isTargetOpcode();
4144 bool IsOpaque = Constant->isOpaque();
4145 SDLoc dl(N);
4146 Lo = DAG.getConstant(Val: Cst.trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget, isOpaque: IsOpaque);
4147 Hi = DAG.getConstant(Val: Cst.lshr(shiftAmt: NBitWidth).trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget,
4148 isOpaque: IsOpaque);
4149}
4150
4151void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4152 SDLoc dl(N);
4153
4154 SDValue N0 = N->getOperand(Num: 0);
4155 GetExpandedInteger(Op: N0, Lo, Hi);
4156 EVT NVT = Lo.getValueType();
4157
4158 // If the upper half is all sign bits, then we can perform the ABS on the
4159 // lower half and zero-extend. We could use ISD::ABS_MIN_POISON here if
4160 // DAG.ComputeNumSignBits(N0) is larger than NVT.getScalarSizeInBits() + 1.
4161 unsigned NumSignBits = DAG.ComputeNumSignBits(Op: N0);
4162 if (NumSignBits > NVT.getScalarSizeInBits()) {
4163 unsigned AbsOpc = NumSignBits > NVT.getScalarSizeInBits() + 1
4164 ? ISD::ABS_MIN_POISON
4165 : ISD::ABS;
4166 Lo = DAG.getNode(Opcode: AbsOpc, DL: dl, VT: NVT, Operand: Lo);
4167 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4168 return;
4169 }
4170
4171 // If we have USUBO_CARRY, use the expanded form of the sra+xor+sub sequence
4172 // we use in LegalizeDAG. The SUB part of the expansion is based on
4173 // ExpandIntRes_ADDSUB which also uses USUBO_CARRY/USUBO after checking that
4174 // USUBO_CARRY is LegalOrCustom. Each of the pieces here can be further
4175 // expanded if needed. Shift expansion has a special case for filling with
4176 // sign bits so that we will only end up with one SRA.
4177 bool HasSubCarry = TLI.isOperationLegalOrCustom(
4178 Op: ISD::USUBO_CARRY, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
4179 if (HasSubCarry) {
4180 SDValue Sign = DAG.getNode(
4181 Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Hi,
4182 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - 1, VT: NVT, DL: dl));
4183 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
4184 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Sign);
4185 Hi = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Hi, N2: Sign);
4186 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: Lo, N2: Sign);
4187 Hi = DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: Hi, N2: Sign, N3: Lo.getValue(R: 1));
4188 return;
4189 }
4190
4191 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
4192 EVT VT = N->getValueType(ResNo: 0);
4193 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT,
4194 N1: DAG.getConstant(Val: 0, DL: dl, VT), N2: N0);
4195 SDValue NegLo, NegHi;
4196 SplitInteger(Op: Neg, Lo&: NegLo, Hi&: NegHi);
4197
4198 SDValue HiIsNeg = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4199 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETLT);
4200 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegLo, RHS: Lo);
4201 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegHi, RHS: Hi);
4202}
4203
4204void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
4205 SDValue &Lo, SDValue &Hi) {
4206 SDLoc dl(N);
4207 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
4208 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4209 EVT NVT = Lo.getValueType();
4210
4211 SDValue HiNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4212 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4213
4214 SDValue LoLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Lo);
4215 SDValue HiLZ = DAG.getNode(Opcode: ISD::CTLZ_ZERO_POISON, DL: dl, VT: NVT, Operand: Hi);
4216
4217 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiNotZero, LHS: HiLZ,
4218 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoLZ,
4219 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4220 VT: NVT)));
4221 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4222}
4223
4224void DAGTypeLegalizer::ExpandIntRes_CTLS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4225 SDLoc dl(N);
4226 // ctls(HiLo) -> if (IsAllSignBits = (ctls(Hi) == BW-1)) then
4227 // BW-1 + clz(IsNegative = (Hi < 0) ? ~Lo : Lo)
4228 // else ctls(Hi)
4229 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4230 EVT NVT = Lo.getValueType();
4231 unsigned NVTBits = NVT.getScalarSizeInBits();
4232
4233 SDValue Constant0 = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4234 SDValue ConstantBWM1 = DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: NVT);
4235
4236 SDValue HiCTLS = DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Hi);
4237 SDValue IsAllSignBits = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: HiCTLS,
4238 RHS: ConstantBWM1, Cond: ISD::SETEQ);
4239 SDValue IsNegative =
4240 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi, RHS: Constant0, Cond: ISD::SETLT);
4241 SDValue AdjustedLo =
4242 DAG.getSelect(DL: dl, VT: NVT, Cond: IsNegative, LHS: DAG.getNOT(DL: dl, Val: Lo, VT: NVT), RHS: Lo);
4243 SDValue LoCLZ = DAG.getNode(Opcode: ISD::CTLZ, DL: dl, VT: NVT, Operand: AdjustedLo);
4244 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: IsAllSignBits,
4245 LHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoCLZ, N2: ConstantBWM1),
4246 RHS: HiCTLS);
4247 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4248}
4249
4250void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
4251 SDValue Result = TLI.expandABD(N, DAG);
4252 SplitInteger(Op: Result, Lo, Hi);
4253}
4254
4255void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
4256 SDValue Op = N->getOperand(Num: 0);
4257 EVT VT = N->getValueType(ResNo: 0);
4258 SDLoc DL(N);
4259
4260 if (TLI.getOperationAction(Op: ISD::CTPOP, VT) == TargetLoweringBase::LibCall) {
4261 RTLIB::Libcall LC = RTLIB::getCTPOP(VT);
4262 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
4263 "LibCall explicitly requested, but not available");
4264
4265 if (RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
4266 TargetLowering::MakeLibCallOptions CallOptions;
4267 EVT IntVT =
4268 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
4269 SDValue Res =
4270 TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: IntVT, Ops: Op, CallOptions, dl: DL).first;
4271 SplitInteger(Op: DAG.getSExtOrTrunc(Op: Res, DL, VT), Lo, Hi);
4272 return;
4273 }
4274
4275 // If the function is not available, fall back on the expansion.
4276 }
4277
4278 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
4279 GetExpandedInteger(Op, Lo, Hi);
4280 EVT NVT = Lo.getValueType();
4281 Lo = DAG.getNode(Opcode: ISD::ADD, DL, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Lo),
4282 N2: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Hi));
4283 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
4284}
4285
4286void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
4287 SDValue &Lo, SDValue &Hi) {
4288 SDLoc dl(N);
4289 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
4290 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4291 EVT NVT = Lo.getValueType();
4292
4293 SDValue LoNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
4294 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4295
4296 SDValue LoLZ = DAG.getNode(Opcode: ISD::CTTZ_ZERO_POISON, DL: dl, VT: NVT, Operand: Lo);
4297 SDValue HiLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Hi);
4298
4299 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: LoNotZero, LHS: LoLZ,
4300 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: HiLZ,
4301 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4302 VT: NVT)));
4303 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4304}
4305
4306void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo,
4307 SDValue &Hi) {
4308 SDLoc dl(N);
4309 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4310 unsigned NBitWidth = NVT.getSizeInBits();
4311
4312 Lo = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
4313 SDValue Chain = Lo.getValue(R: 1);
4314 // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING
4315 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4316 N2: DAG.getShiftAmountConstant(Val: NBitWidth - 1, VT: NVT, DL: dl));
4317
4318 // Legalize the chain result - switch anything that used the old chain to
4319 // use the new one.
4320 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
4321}
4322
4323// Helper for producing an FP_EXTEND/STRICT_FP_EXTEND of Op.
4324static SDValue fpExtendHelper(SDValue Op, SDValue &Chain, bool IsStrict, EVT VT,
4325 SDLoc DL, SelectionDAG &DAG) {
4326 if (IsStrict) {
4327 Op = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL, ResultTys: {VT, MVT::Other}, Ops: {Chain, Op});
4328 Chain = Op.getValue(R: 1);
4329 return Op;
4330 }
4331 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT, Operand: Op);
4332}
4333
4334void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
4335 SDValue &Hi) {
4336 SDLoc dl(N);
4337 EVT VT = N->getValueType(ResNo: 0);
4338
4339 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
4340 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
4341 bool IsStrict = N->isStrictFPOpcode();
4342 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4343 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4344
4345 // If the input is bf16 or needs to be soft promoted, extend to f32.
4346 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf ||
4347 Op.getValueType() == MVT::bf16) {
4348 Op = fpExtendHelper(Op, Chain, IsStrict, VT: MVT::f32, DL: dl, DAG);
4349 }
4350
4351 // NOTE: We need a variable that lives across makeLibCall so
4352 // CallOptions.setTypeListBeforeSoften can save a reference to it.
4353 EVT OpVT = Op.getValueType();
4354
4355 RTLIB::Libcall LC =
4356 IsSigned ? RTLIB::getFPTOSINT(OpVT, RetVT: VT) : RTLIB::getFPTOUINT(OpVT, RetVT: VT);
4357 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
4358 TargetLowering::MakeLibCallOptions CallOptions;
4359 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftenFloat)
4360 CallOptions.setTypeListBeforeSoften(OpsVT: OpVT, RetVT: VT);
4361 else
4362 CallOptions.setIsSigned(true); // FIXME: Is this needed?
4363 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op,
4364 CallOptions, dl, Chain);
4365 SplitInteger(Op: Tmp.first, Lo, Hi);
4366
4367 if (IsStrict)
4368 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4369}
4370
4371void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
4372 SDValue &Hi) {
4373 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
4374 SplitInteger(Op: Res, Lo, Hi);
4375}
4376
4377void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo,
4378 SDValue &Hi) {
4379 SDLoc dl(N);
4380 bool IsStrict = N->isStrictFPOpcode();
4381 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4382 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4383
4384 EVT VT = Op.getValueType();
4385
4386 if (VT == MVT::f16) {
4387 // Extend to f32.
4388 VT = MVT::f32;
4389 Op = fpExtendHelper(Op, Chain, IsStrict, VT, DL: dl, DAG);
4390 }
4391
4392 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4393 if (N->getOpcode() == ISD::LROUND ||
4394 N->getOpcode() == ISD::STRICT_LROUND) {
4395 LC = RTLIB::getLROUND(VT);
4396 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lround input type!");
4397 } else if (N->getOpcode() == ISD::LRINT ||
4398 N->getOpcode() == ISD::STRICT_LRINT) {
4399 LC = RTLIB::getLRINT(VT);
4400 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lrint input type!");
4401 } else if (N->getOpcode() == ISD::LLROUND ||
4402 N->getOpcode() == ISD::STRICT_LLROUND) {
4403 LC = RTLIB::getLLROUND(VT);
4404 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
4405 } else if (N->getOpcode() == ISD::LLRINT ||
4406 N->getOpcode() == ISD::STRICT_LLRINT) {
4407 LC = RTLIB::getLLRINT(VT);
4408 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
4409 } else
4410 llvm_unreachable("Unexpected opcode!");
4411
4412 EVT RetVT = N->getValueType(ResNo: 0);
4413
4414 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
4415 if (LCImpl == RTLIB::Unsupported) {
4416 DAG.getContext()->emitError(ErrorStr: Twine("no libcall available for ") +
4417 N->getOperationName(G: &DAG));
4418 SDValue Poison = DAG.getPOISON(VT: N->getValueType(ResNo: 0));
4419 SplitInteger(Op: Poison, Lo, Hi);
4420 if (N->isStrictFPOpcode())
4421 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
4422 return;
4423 }
4424
4425 TargetLowering::MakeLibCallOptions CallOptions;
4426 CallOptions.setIsSigned(true);
4427 std::pair<SDValue, SDValue> Tmp =
4428 TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT, Ops: Op, CallOptions, dl, Chain);
4429 SplitInteger(Op: Tmp.first, Lo, Hi);
4430
4431 if (N->isStrictFPOpcode())
4432 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4433}
4434
4435void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
4436 SDValue &Lo, SDValue &Hi) {
4437 assert(!N->isAtomic() && "Should have been a ATOMIC_LOAD?");
4438
4439 if (ISD::isNormalLoad(N)) {
4440 ExpandRes_NormalLoad(N, Lo, Hi);
4441 return;
4442 }
4443
4444 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
4445
4446 EVT VT = N->getValueType(ResNo: 0);
4447 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4448 SDValue Ch = N->getChain();
4449 SDValue Ptr = N->getBasePtr();
4450 ISD::LoadExtType ExtType = N->getExtensionType();
4451 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4452 MMOMetadata Metadata = N->getMMOMetadataForSubAccess();
4453 SDLoc dl(N);
4454
4455 assert(NVT.isByteSized() && "Expanded type not byte sized!");
4456
4457 if (N->getMemoryVT().bitsLE(VT: NVT)) {
4458 EVT MemVT = N->getMemoryVT();
4459
4460 Lo = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), MemVT,
4461 Alignment: N->getBaseAlign(), MMOFlags, Metadata);
4462
4463 // Remember the chain.
4464 Ch = Lo.getValue(R: 1);
4465
4466 if (ExtType == ISD::SEXTLOAD) {
4467 // The high part is obtained by SRA'ing all but one of the bits of the
4468 // lo part.
4469 unsigned LoSize = Lo.getValueSizeInBits();
4470 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4471 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
4472 } else if (ExtType == ISD::ZEXTLOAD) {
4473 // The high part is just a zero.
4474 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4475 } else {
4476 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
4477 // The high part is undefined.
4478 Hi = DAG.getUNDEF(VT: NVT);
4479 }
4480 } else if (DAG.getDataLayout().isLittleEndian()) {
4481 // Little-endian - low bits are at low addresses.
4482 Lo = DAG.getLoad(VT: NVT, dl, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
4483 MMOFlags, Metadata);
4484
4485 unsigned ExcessBits =
4486 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4487 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
4488
4489 // Increment the pointer to the other half.
4490 unsigned IncrementSize = NVT.getSizeInBits()/8;
4491 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4492 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr,
4493 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize), MemVT: NEVT,
4494 Alignment: N->getBaseAlign(), MMOFlags, Metadata);
4495
4496 // Build a factor node to remember that this load is independent of the
4497 // other one.
4498 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4499 N2: Hi.getValue(R: 1));
4500 } else {
4501 // Big-endian - high bits are at low addresses. Favor aligned loads at
4502 // the cost of some bit-fiddling.
4503 EVT MemVT = N->getMemoryVT();
4504 unsigned EBytes = MemVT.getStoreSize();
4505 unsigned IncrementSize = NVT.getSizeInBits()/8;
4506 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4507
4508 // Load both the high bits and maybe some of the low bits.
4509 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(),
4510 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(),
4511 BitWidth: MemVT.getSizeInBits() - ExcessBits),
4512 Alignment: N->getBaseAlign(), MMOFlags, Metadata);
4513
4514 // Increment the pointer to the other half.
4515 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4516 // Load the rest of the low bits.
4517 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: NVT, Chain: Ch, Ptr,
4518 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
4519 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
4520 Alignment: N->getBaseAlign(), MMOFlags, Metadata);
4521
4522 // Build a factor node to remember that this load is independent of the
4523 // other one.
4524 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4525 N2: Hi.getValue(R: 1));
4526
4527 if (ExcessBits < NVT.getSizeInBits()) {
4528 // Transfer low bits from the bottom of Hi to the top of Lo.
4529 Lo = DAG.getNode(
4530 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Lo,
4531 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
4532 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
4533 // Move high bits to the right position in Hi.
4534 Hi = DAG.getNode(Opcode: ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
4535 N1: Hi,
4536 N2: DAG.getShiftAmountConstant(
4537 Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
4538 }
4539 }
4540
4541 // Legalize the chain result - switch anything that used the old chain to
4542 // use the new one.
4543 ReplaceValueWith(From: SDValue(N, 1), To: Ch);
4544}
4545
4546void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
4547 SDValue &Lo, SDValue &Hi) {
4548 SDLoc dl(N);
4549 SDValue LL, LH, RL, RH;
4550 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4551 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4552
4553 SDNodeFlags Flags;
4554 if (N->getOpcode() == ISD::OR)
4555 Flags.setDisjoint(N->getFlags().hasDisjoint());
4556
4557 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LL, N2: RL, Flags);
4558 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LH, N2: RH, Flags);
4559}
4560
4561void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
4562 SDValue &Lo, SDValue &Hi) {
4563 EVT VT = N->getValueType(ResNo: 0);
4564 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4565 SDLoc dl(N);
4566
4567 SDValue LL, LH, RL, RH;
4568 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4569 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4570
4571 if (TLI.expandMUL(N, Lo, Hi, HiLoVT: NVT, DAG,
4572 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4573 LL, LH, RL, RH))
4574 return;
4575
4576 // If nothing else, we can make a libcall.
4577 RTLIB::Libcall LC = RTLIB::getMUL(VT);
4578 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
4579 if (LCImpl == RTLIB::Unsupported) {
4580 // Perform a wide multiplication where the wide type is the original VT and
4581 // the 4 parts are the split arguments.
4582 TLI.forceExpandMultiply(DAG, dl, /*Signed=*/false, Lo, Hi, LHS: LL, RHS: RL, HiLHS: LH, HiRHS: RH);
4583 return;
4584 }
4585
4586 // Note that we don't need to do a wide MUL here since we don't care about the
4587 // upper half of the result if it exceeds VT.
4588 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4589 TargetLowering::MakeLibCallOptions CallOptions;
4590 CallOptions.setIsSigned(true);
4591 SplitInteger(Op: TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
4592 Hi);
4593}
4594
4595void DAGTypeLegalizer::ExpandIntRes_READCOUNTER(SDNode *N, SDValue &Lo,
4596 SDValue &Hi) {
4597 SDLoc DL(N);
4598 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4599 SDVTList VTs = DAG.getVTList(VT1: NVT, VT2: NVT, VT3: MVT::Other);
4600 SDValue R = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N: N->getOperand(Num: 0));
4601 Lo = R.getValue(R: 0);
4602 Hi = R.getValue(R: 1);
4603 ReplaceValueWith(From: SDValue(N, 1), To: R.getValue(R: 2));
4604}
4605
4606void DAGTypeLegalizer::ExpandIntRes_AVG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4607 SDValue Result = TLI.expandAVG(N, DAG);
4608 SplitInteger(Op: Result, Lo, Hi);
4609}
4610
4611void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
4612 SDValue &Hi) {
4613 SDValue Result = TLI.expandAddSubSat(Node: N, DAG);
4614 SplitInteger(Op: Result, Lo, Hi);
4615}
4616
4617void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
4618 SDValue &Hi) {
4619 SDValue Result = TLI.expandShlSat(Node: N, DAG);
4620 SplitInteger(Op: Result, Lo, Hi);
4621}
4622
4623/// This performs an expansion of the integer result for a fixed point
4624/// multiplication. The default expansion performs rounding down towards
4625/// negative infinity, though targets that do care about rounding should specify
4626/// a target hook for rounding and provide their own expansion or lowering of
4627/// fixed point multiplication to be consistent with rounding.
4628void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
4629 SDValue &Hi) {
4630 SDLoc dl(N);
4631 EVT VT = N->getValueType(ResNo: 0);
4632 unsigned VTSize = VT.getScalarSizeInBits();
4633 SDValue LHS = N->getOperand(Num: 0);
4634 SDValue RHS = N->getOperand(Num: 1);
4635 uint64_t Scale = N->getConstantOperandVal(Num: 2);
4636 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
4637 N->getOpcode() == ISD::UMULFIXSAT);
4638 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
4639 N->getOpcode() == ISD::SMULFIXSAT);
4640
4641 // Handle special case when scale is equal to zero.
4642 if (!Scale) {
4643 SDValue Result;
4644 if (!Saturating) {
4645 Result = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS);
4646 } else {
4647 EVT BoolVT = getSetCCResultType(VT);
4648 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
4649 Result = DAG.getNode(Opcode: MulOp, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: BoolVT), N1: LHS, N2: RHS);
4650 SDValue Product = Result.getValue(R: 0);
4651 SDValue Overflow = Result.getValue(R: 1);
4652 if (Signed) {
4653 APInt MinVal = APInt::getSignedMinValue(numBits: VTSize);
4654 APInt MaxVal = APInt::getSignedMaxValue(numBits: VTSize);
4655 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT);
4656 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4657 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
4658 // Xor the inputs, if resulting sign bit is 0 the product will be
4659 // positive, else negative.
4660 SDValue Xor = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4661 SDValue ProdNeg = DAG.getSetCC(DL: dl, VT: BoolVT, LHS: Xor, RHS: Zero, Cond: ISD::SETLT);
4662 Result = DAG.getSelect(DL: dl, VT, Cond: ProdNeg, LHS: SatMin, RHS: SatMax);
4663 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: Result, RHS: Product);
4664 } else {
4665 // For unsigned multiplication, we only need to check the max since we
4666 // can't really overflow towards zero.
4667 APInt MaxVal = APInt::getMaxValue(numBits: VTSize);
4668 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4669 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: SatMax, RHS: Product);
4670 }
4671 }
4672 SplitInteger(Op: Result, Lo, Hi);
4673 return;
4674 }
4675
4676 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
4677 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
4678 assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
4679
4680 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4681 SDValue LL, LH, RL, RH;
4682 GetExpandedInteger(Op: LHS, Lo&: LL, Hi&: LH);
4683 GetExpandedInteger(Op: RHS, Lo&: RL, Hi&: RH);
4684 SmallVector<SDValue, 4> Result;
4685
4686 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
4687 if (!TLI.expandMUL_LOHI(Opcode: LoHiOp, VT, dl, LHS, RHS, Result, HiLoVT: NVT, DAG,
4688 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4689 LL, LH, RL, RH)) {
4690 Result.clear();
4691 Result.resize(N: 4);
4692
4693 SDValue LoTmp, HiTmp;
4694 TLI.forceExpandWideMUL(DAG, dl, Signed, LHS, RHS, Lo&: LoTmp, Hi&: HiTmp);
4695 SplitInteger(Op: LoTmp, Lo&: Result[0], Hi&: Result[1]);
4696 SplitInteger(Op: HiTmp, Lo&: Result[2], Hi&: Result[3]);
4697 }
4698 assert(Result.size() == 4 && "Unexpected number of partlets in the result");
4699
4700 unsigned NVTSize = NVT.getScalarSizeInBits();
4701 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
4702 "the size of the current value type");
4703
4704 // After getting the multiplication result in 4 parts, we need to perform a
4705 // shift right by the amount of the scale to get the result in that scale.
4706 //
4707 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
4708 // 128 bits that are cut into 4 32-bit parts:
4709 //
4710 // HH HL LH LL
4711 // |---32---|---32---|---32---|---32---|
4712 // 128 96 64 32 0
4713 //
4714 // |------VTSize-----|
4715 //
4716 // |NVTSize-|
4717 //
4718 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
4719 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
4720 // amount and get Lo and Hi using two funnel shifts. Or for the special case
4721 // when Scale is a multiple of NVTSize we can just pick the result without
4722 // shifting.
4723 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
4724 if (Scale % NVTSize) {
4725 SDValue ShiftAmount = DAG.getShiftAmountConstant(Val: Scale % NVTSize, VT: NVT, DL: dl);
4726 Lo = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 1], N2: Result[Part0],
4727 N3: ShiftAmount);
4728 Hi = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 2], N2: Result[Part0 + 1],
4729 N3: ShiftAmount);
4730 } else {
4731 Lo = Result[Part0];
4732 Hi = Result[Part0 + 1];
4733 }
4734
4735 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
4736 if (!Saturating)
4737 return;
4738
4739 // Can not overflow when there is no integer part.
4740 if (Scale == VTSize)
4741 return;
4742
4743 // To handle saturation we must check for overflow in the multiplication.
4744 //
4745 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
4746 // aren't all zeroes.
4747 //
4748 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
4749 // aren't all ones or all zeroes.
4750 //
4751 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
4752 // highest bit of HH determines saturation direction in the event of signed
4753 // saturation.
4754
4755 SDValue ResultHL = Result[2];
4756 SDValue ResultHH = Result[3];
4757
4758 SDValue SatMax, SatMin;
4759 SDValue NVTZero = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4760 SDValue NVTNeg1 = DAG.getAllOnesConstant(DL: dl, VT: NVT);
4761 EVT BoolNVT = getSetCCResultType(VT: NVT);
4762
4763 if (!Signed) {
4764 if (Scale < NVTSize) {
4765 // Overflow happened if ((HH | (HL >> Scale)) != 0).
4766 SDValue HLAdjusted =
4767 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4768 N2: DAG.getShiftAmountConstant(Val: Scale, VT: NVT, DL: dl));
4769 SDValue Tmp = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: HLAdjusted, N2: ResultHH);
4770 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: Tmp, RHS: NVTZero, Cond: ISD::SETNE);
4771 } else if (Scale == NVTSize) {
4772 // Overflow happened if (HH != 0).
4773 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETNE);
4774 } else if (Scale < VTSize) {
4775 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
4776 SDValue HHAdjusted =
4777 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHH,
4778 N2: DAG.getShiftAmountConstant(Val: Scale - NVTSize, VT: NVT, DL: dl));
4779 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: HHAdjusted, RHS: NVTZero, Cond: ISD::SETNE);
4780 } else
4781 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
4782 "(and saturation can't happen with Scale==VTSize).");
4783
4784 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Hi);
4785 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Lo);
4786 return;
4787 }
4788
4789 if (Scale < NVTSize) {
4790 // The number of overflow bits we can check are VTSize - Scale + 1 (we
4791 // include the sign bit). If these top bits are > 0, then we overflowed past
4792 // the max value. If these top bits are < -1, then we overflowed past the
4793 // min value. Otherwise, we did not overflow.
4794 unsigned OverflowBits = VTSize - Scale + 1;
4795 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
4796 "Extent of overflow bits must start within HL");
4797 SDValue HLHiMask = DAG.getConstant(
4798 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits - NVTSize), DL: dl, VT: NVT);
4799 SDValue HLLoMask = DAG.getConstant(
4800 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: VTSize - OverflowBits), DL: dl, VT: NVT);
4801 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
4802 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4803 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4804 SDValue HLUGT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLLoMask, Cond: ISD::SETUGT);
4805 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4806 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLUGT));
4807 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
4808 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4809 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4810 SDValue HLULT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLHiMask, Cond: ISD::SETULT);
4811 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4812 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLULT));
4813 } else if (Scale == NVTSize) {
4814 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
4815 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4816 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4817 SDValue HLNeg = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETLT);
4818 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4819 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLNeg));
4820 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
4821 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4822 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4823 SDValue HLPos = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETGE);
4824 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4825 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLPos));
4826 } else if (Scale < VTSize) {
4827 // This is similar to the case when we saturate if Scale < NVTSize, but we
4828 // only need to check HH.
4829 unsigned OverflowBits = VTSize - Scale + 1;
4830 SDValue HHHiMask = DAG.getConstant(
4831 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits), DL: dl, VT: NVT);
4832 SDValue HHLoMask = DAG.getConstant(
4833 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: NVTSize - OverflowBits), DL: dl, VT: NVT);
4834 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHLoMask, Cond: ISD::SETGT);
4835 SatMin = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHHiMask, Cond: ISD::SETLT);
4836 } else
4837 llvm_unreachable("Illegal scale for signed fixed point mul.");
4838
4839 // Saturate to signed maximum.
4840 APInt MaxHi = APInt::getSignedMaxValue(numBits: NVTSize);
4841 APInt MaxLo = APInt::getAllOnes(numBits: NVTSize);
4842 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxHi, DL: dl, VT: NVT), RHS: Hi);
4843 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxLo, DL: dl, VT: NVT), RHS: Lo);
4844 // Saturate to signed minimum.
4845 APInt MinHi = APInt::getSignedMinValue(numBits: NVTSize);
4846 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: DAG.getConstant(Val: MinHi, DL: dl, VT: NVT), RHS: Hi);
4847 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: NVTZero, RHS: Lo);
4848}
4849
4850void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
4851 SDValue &Hi) {
4852 SDLoc dl(N);
4853 // Try expanding in the existing type first.
4854 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: N->getOperand(Num: 0),
4855 RHS: N->getOperand(Num: 1),
4856 Scale: N->getConstantOperandVal(Num: 2), DAG);
4857
4858 if (!Res)
4859 Res = earlyExpandDIVFIX(N, LHS: N->getOperand(Num: 0), RHS: N->getOperand(Num: 1),
4860 Scale: N->getConstantOperandVal(Num: 2), TLI, DAG);
4861 SplitInteger(Op: Res, Lo, Hi);
4862}
4863
4864void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
4865 SDValue &Lo, SDValue &Hi) {
4866 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
4867 "Node has unexpected Opcode");
4868 SDValue LHS = Node->getOperand(Num: 0);
4869 SDValue RHS = Node->getOperand(Num: 1);
4870 SDLoc dl(Node);
4871
4872 SDValue Ovf;
4873
4874 bool IsAdd = Node->getOpcode() == ISD::SADDO;
4875 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
4876
4877 bool HasCarryOp = TLI.isOperationLegalOrCustom(
4878 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
4879
4880 if (HasCarryOp) {
4881 // Expand the subcomponents.
4882 SDValue LHSL, LHSH, RHSL, RHSH;
4883 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
4884 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
4885 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: Node->getValueType(ResNo: 1));
4886
4887 Lo = DAG.getNode(Opcode: IsAdd ? ISD::UADDO : ISD::USUBO, DL: dl, VTList, Ops: {LHSL, RHSL});
4888 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4889
4890 Ovf = Hi.getValue(R: 1);
4891 } else {
4892 // Expand the result by simply replacing it with the equivalent
4893 // non-overflow-checking operation.
4894 SDValue Sum = DAG.getNode(Opcode: Node->getOpcode() == ISD::SADDO ?
4895 ISD::ADD : ISD::SUB, DL: dl, VT: LHS.getValueType(),
4896 N1: LHS, N2: RHS);
4897 SplitInteger(Op: Sum, Lo, Hi);
4898
4899 // Compute the overflow.
4900 //
4901 // LHSSign -> LHS < 0
4902 // RHSSign -> RHS < 0
4903 // SumSign -> Sum < 0
4904 //
4905 // Add:
4906 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4907 // Sub:
4908 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4909 //
4910 // To get better codegen we can rewrite this by doing bitwise math on
4911 // the integers and extract the final sign bit at the end. So the
4912 // above becomes:
4913 //
4914 // Add:
4915 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
4916 // Sub:
4917 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
4918 //
4919 // NOTE: This is different than the expansion we do in expandSADDSUBO
4920 // because it is more costly to implement the same overflow predicate with
4921 // SETCC nodes when the integers are split.
4922 EVT VT = LHS.getValueType();
4923 SDValue SignsMatch = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4924 if (IsAdd)
4925 SignsMatch = DAG.getNOT(DL: dl, Val: SignsMatch, VT);
4926
4927 SDValue SumSignNE = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: Sum);
4928 Ovf = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: SignsMatch, N2: SumSignNE);
4929 EVT OType = Node->getValueType(ResNo: 1);
4930 Ovf = DAG.getSetCC(DL: dl, VT: OType, LHS: Ovf, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETLT);
4931 }
4932
4933 // Use the calculated overflow everywhere.
4934 ReplaceValueWith(From: SDValue(Node, 1), To: Ovf);
4935}
4936
4937void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
4938 SDValue &Lo, SDValue &Hi) {
4939 EVT VT = N->getValueType(ResNo: 0);
4940 SDLoc dl(N);
4941 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4942
4943 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
4944 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
4945 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
4946 return;
4947 }
4948
4949 RTLIB::Libcall LC = RTLIB::getSDIV(VT);
4950 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
4951
4952 TargetLowering::MakeLibCallOptions CallOptions;
4953 CallOptions.setIsSigned(true);
4954 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
4955}
4956
4957void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
4958 SDValue &Hi) {
4959 SDLoc dl(N);
4960 SDValue Shiftee = N->getOperand(Num: 0);
4961 EVT VT = Shiftee.getValueType();
4962 SDValue ShAmt = N->getOperand(Num: 1);
4963 EVT ShAmtVT = ShAmt.getValueType();
4964
4965 EVT LoadVT = VT;
4966 do {
4967 LoadVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: LoadVT);
4968 } while (!TLI.isTypeLegal(VT: LoadVT));
4969
4970 const unsigned ShiftUnitInBits = LoadVT.getStoreSizeInBits();
4971 assert(ShiftUnitInBits <= VT.getScalarSizeInBits());
4972 assert(isPowerOf2_32(ShiftUnitInBits) &&
4973 "Shifting unit is not a a power of two!");
4974
4975 const bool IsOneStepShift =
4976 DAG.computeKnownBits(Op: ShAmt).countMinTrailingZeros() >=
4977 Log2_32(Value: ShiftUnitInBits);
4978
4979 // If we can't do it as one step, we'll have two uses of shift amount,
4980 // and thus must freeze it.
4981 if (!IsOneStepShift)
4982 ShAmt = DAG.getFreeze(V: ShAmt);
4983
4984 unsigned VTBitWidth = VT.getScalarSizeInBits();
4985 assert(VTBitWidth % 8 == 0 && "Shifting a not byte multiple value?");
4986 unsigned VTByteWidth = VTBitWidth / 8;
4987 assert(isPowerOf2_32(VTByteWidth) &&
4988 "Shiftee type size is not a power of two!");
4989 unsigned StackSlotByteWidth = 2 * VTByteWidth;
4990 unsigned StackSlotBitWidth = 8 * StackSlotByteWidth;
4991 EVT StackSlotVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StackSlotBitWidth);
4992
4993 // Get a temporary stack slot 2x the width of our VT.
4994 // FIXME: reuse stack slots?
4995 Align StackAlign = DAG.getReducedAlign(VT: StackSlotVT, /*UseABI=*/false);
4996 SDValue StackPtr =
4997 DAG.CreateStackTemporary(Bytes: StackSlotVT.getStoreSize(), Alignment: StackAlign);
4998 EVT PtrTy = StackPtr.getValueType();
4999 SDValue Ch = DAG.getEntryNode();
5000
5001 MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
5002 MF&: DAG.getMachineFunction(),
5003 FI: cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex());
5004
5005 // Extend the value, that is being shifted, to the entire stack slot's width.
5006 SDValue Init;
5007 if (N->getOpcode() != ISD::SHL) {
5008 unsigned WideningOpc =
5009 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5010 Init = DAG.getNode(Opcode: WideningOpc, DL: dl, VT: StackSlotVT, Operand: Shiftee);
5011 } else {
5012 // For left-shifts, pad the Shiftee's LSB with zeros to twice it's width.
5013 SDValue AllZeros = DAG.getConstant(Val: 0, DL: dl, VT);
5014 Init = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: StackSlotVT, N1: AllZeros, N2: Shiftee);
5015 }
5016 // And spill it into the stack slot.
5017 Ch = DAG.getStore(Chain: Ch, dl, Val: Init, Ptr: StackPtr, PtrInfo: StackPtrInfo, Alignment: StackAlign);
5018
5019 // Now, compute the full-byte offset into stack slot from where we can load.
5020 // We have shift amount, which is in bits. Offset should point to an aligned
5021 // address.
5022 SDNodeFlags Flags;
5023 Flags.setExact(IsOneStepShift);
5024 SDValue SrlTmp = DAG.getNode(
5025 Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: ShAmt,
5026 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT), Flags);
5027 SDValue BitOffset =
5028 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: ShAmtVT, N1: SrlTmp,
5029 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT));
5030
5031 SDValue ByteOffset =
5032 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: BitOffset,
5033 N2: DAG.getConstant(Val: 3, DL: dl, VT: ShAmtVT), Flags: SDNodeFlags::Exact);
5034 // And clamp it, because OOB load is an immediate UB,
5035 // while shift overflow would have *just* been poison.
5036 ByteOffset = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ByteOffset,
5037 N2: DAG.getConstant(Val: VTByteWidth - 1, DL: dl, VT: ShAmtVT));
5038 // We have exactly two strategies on indexing into stack slot here:
5039 // 1. upwards starting from the beginning of the slot
5040 // 2. downwards starting from the middle of the slot
5041 // On little-endian machine, we pick 1. for right shifts and 2. for left-shift
5042 // and vice versa on big-endian machine.
5043 bool WillIndexUpwards = N->getOpcode() != ISD::SHL;
5044 if (DAG.getDataLayout().isBigEndian())
5045 WillIndexUpwards = !WillIndexUpwards;
5046
5047 SDValue AdjStackPtr;
5048 if (WillIndexUpwards) {
5049 AdjStackPtr = StackPtr;
5050 } else {
5051 AdjStackPtr = DAG.getMemBasePlusOffset(
5052 Base: StackPtr, Offset: DAG.getConstant(Val: VTByteWidth, DL: dl, VT: PtrTy), DL: dl);
5053 ByteOffset = DAG.getNegative(Val: ByteOffset, DL: dl, VT: ShAmtVT);
5054 }
5055
5056 // Get the pointer somewhere into the stack slot from which we need to load.
5057 ByteOffset = DAG.getSExtOrTrunc(Op: ByteOffset, DL: dl, VT: PtrTy);
5058 AdjStackPtr = DAG.getMemBasePlusOffset(Base: AdjStackPtr, Offset: ByteOffset, DL: dl);
5059
5060 // And load it! While the load is not legal, legalizing it is obvious.
5061 SDValue Res =
5062 DAG.getLoad(VT, dl, Chain: Ch, Ptr: AdjStackPtr,
5063 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
5064 Alignment: commonAlignment(A: StackAlign, Offset: LoadVT.getStoreSize()));
5065
5066 // If we may still have a remaining bits to shift by, do so now.
5067 if (!IsOneStepShift) {
5068 SDValue ShAmtRem =
5069 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ShAmt,
5070 N2: DAG.getConstant(Val: ShiftUnitInBits - 1, DL: dl, VT: ShAmtVT));
5071 Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT, N1: Res, N2: ShAmtRem);
5072 }
5073
5074 // Finally, split the computed value.
5075 SplitInteger(Op: Res, Lo, Hi);
5076}
5077
5078void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
5079 SDValue &Lo, SDValue &Hi) {
5080 EVT VT = N->getValueType(ResNo: 0);
5081 unsigned Opc = N->getOpcode();
5082 SDLoc dl(N);
5083
5084 // If we can emit an efficient shift operation, do so now. Check to see if
5085 // the RHS is a constant.
5086 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1)))
5087 return ExpandShiftByConstant(N, Amt: CN->getAPIntValue(), Lo, Hi);
5088
5089 // If we can determine that the high bit of the shift is zero or one, even if
5090 // the low bits are variable, emit this shift in an optimized form.
5091 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
5092 return;
5093
5094 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
5095 unsigned PartsOpc;
5096 if (Opc == ISD::SHL) {
5097 PartsOpc = ISD::SHL_PARTS;
5098 } else if (Opc == ISD::SRL) {
5099 PartsOpc = ISD::SRL_PARTS;
5100 } else {
5101 assert(Opc == ISD::SRA && "Unknown shift!");
5102 PartsOpc = ISD::SRA_PARTS;
5103 }
5104
5105 // Next check to see if the target supports this SHL_PARTS operation or if it
5106 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
5107 // size, but create a libcall instead.
5108 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5109 TargetLowering::LegalizeAction Action = TLI.getOperationAction(Op: PartsOpc, VT: NVT);
5110 const bool LegalOrCustom =
5111 (Action == TargetLowering::Legal && TLI.isTypeLegal(VT: NVT)) ||
5112 Action == TargetLowering::Custom;
5113
5114 unsigned ExpansionFactor = 1;
5115 // That VT->NVT expansion is one step. But will we re-expand NVT?
5116 for (EVT TmpVT = NVT;;) {
5117 EVT NewTMPVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: TmpVT);
5118 if (NewTMPVT == TmpVT)
5119 break;
5120 TmpVT = NewTMPVT;
5121 ++ExpansionFactor;
5122 }
5123
5124 TargetLowering::ShiftLegalizationStrategy S =
5125 TLI.preferredShiftLegalizationStrategy(DAG, N, ExpansionFactor);
5126
5127 if (S == TargetLowering::ShiftLegalizationStrategy::ExpandThroughStack)
5128 return ExpandIntRes_ShiftThroughStack(N, Lo, Hi);
5129
5130 if (LegalOrCustom &&
5131 S != TargetLowering::ShiftLegalizationStrategy::LowerToLibcall) {
5132 // Expand the subcomponents.
5133 SDValue LHSL, LHSH;
5134 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
5135 EVT VT = LHSL.getValueType();
5136
5137 // If the shift amount operand is coming from a vector legalization it may
5138 // have an illegal type. Fix that first by casting the operand, otherwise
5139 // the new SHL_PARTS operation would need further legalization.
5140 SDValue ShiftOp = N->getOperand(Num: 1);
5141 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
5142 if (ShiftOp.getValueType() != ShiftTy)
5143 ShiftOp = DAG.getZExtOrTrunc(Op: ShiftOp, DL: dl, VT: ShiftTy);
5144
5145 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
5146 Lo = DAG.getNode(Opcode: PartsOpc, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5147 Hi = Lo.getValue(R: 1);
5148 return;
5149 }
5150
5151 // Otherwise, emit a libcall.
5152 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5153 bool isSigned;
5154 if (Opc == ISD::SHL) {
5155 isSigned = false; /*sign irrelevant*/
5156 LC = RTLIB::getSHL(VT);
5157 } else if (Opc == ISD::SRL) {
5158 isSigned = false;
5159 LC = RTLIB::getSRL(VT);
5160 } else {
5161 assert(Opc == ISD::SRA && "Unknown shift!");
5162 isSigned = true;
5163 LC = RTLIB::getSRA(VT);
5164 }
5165
5166 if (RTLIB::LibcallImpl LibcallImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
5167 EVT ShAmtTy =
5168 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
5169 SDValue ShAmt = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl, VT: ShAmtTy);
5170 SDValue Ops[2] = {N->getOperand(Num: 0), ShAmt};
5171 TargetLowering::MakeLibCallOptions CallOptions;
5172 CallOptions.setIsSigned(isSigned);
5173 SplitInteger(
5174 Op: TLI.makeLibCall(DAG, LibcallImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
5175 Hi);
5176 return;
5177 }
5178
5179 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
5180 llvm_unreachable("Unsupported shift!");
5181}
5182
5183void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
5184 SDValue &Lo, SDValue &Hi) {
5185 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5186 SDLoc dl(N);
5187 SDValue Op = N->getOperand(Num: 0);
5188 if (Op.getValueType().bitsLE(VT: NVT)) {
5189 // The low part is sign extension of the input (degenerates to a copy).
5190 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5191 // The high part is obtained by SRA'ing all but one of the bits of low part.
5192 unsigned LoSize = NVT.getSizeInBits();
5193 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
5194 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
5195 } else {
5196 // For example, extension of an i48 to an i64. The operand type necessarily
5197 // promotes to the result type, so will end up being expanded too.
5198 assert(getTypeAction(Op.getValueType()) ==
5199 TargetLowering::TypePromoteInteger &&
5200 "Only know how to promote this result!");
5201 SDValue Res = GetPromotedInteger(Op);
5202 assert(Res.getValueType() == N->getValueType(0) &&
5203 "Operand over promoted?");
5204 // Split the promoted operand. This will simplify when it is expanded.
5205 SplitInteger(Op: Res, Lo, Hi);
5206 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5207 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5208 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5209 BitWidth: ExcessBits)));
5210 }
5211}
5212
5213void DAGTypeLegalizer::
5214ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
5215 SDLoc dl(N);
5216 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5217 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
5218
5219 if (EVT.bitsLE(VT: Lo.getValueType())) {
5220 // sext_inreg the low part if needed.
5221 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Lo.getValueType(), N1: Lo,
5222 N2: N->getOperand(Num: 1));
5223
5224 // The high part gets the sign extension from the lo-part. This handles
5225 // things like sextinreg V:i64 from i8.
5226 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: Hi.getValueType(), N1: Lo,
5227 N2: DAG.getShiftAmountConstant(Val: Hi.getValueSizeInBits() - 1,
5228 VT: Hi.getValueType(), DL: dl));
5229 } else {
5230 // For example, extension of an i48 to an i64. Leave the low part alone,
5231 // sext_inreg the high part.
5232 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
5233 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5234 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5235 BitWidth: ExcessBits)));
5236 }
5237}
5238
5239void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
5240 SDValue &Lo, SDValue &Hi) {
5241 EVT VT = N->getValueType(ResNo: 0);
5242 SDLoc dl(N);
5243 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5244
5245 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5246 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5247 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5248 return;
5249 }
5250
5251 RTLIB::Libcall LC = RTLIB::getSREM(VT);
5252 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
5253
5254 TargetLowering::MakeLibCallOptions CallOptions;
5255 CallOptions.setIsSigned(true);
5256 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5257}
5258
5259void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
5260 SDValue &Lo, SDValue &Hi) {
5261 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5262 SDValue InOp = N->getOperand(Num: 0);
5263 EVT InVT = InOp.getValueType();
5264 SDLoc dl(N);
5265 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: InOp);
5266 Hi = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: InVT, N1: InOp,
5267 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits(), VT: InVT, DL: dl));
5268 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Hi);
5269}
5270
5271void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
5272 SDValue &Lo, SDValue &Hi) {
5273 EVT VT = N->getValueType(ResNo: 0);
5274 SDLoc dl(N);
5275
5276 if (N->getOpcode() == ISD::UMULO) {
5277 // This section expands the operation into the following sequence of
5278 // instructions. `iNh` here refers to a type which has half the bit width of
5279 // the type the original operation operated on.
5280 //
5281 // %0 = %LHS.HI != 0 && %RHS.HI != 0
5282 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
5283 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
5284 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
5285 // %4 = add iNh %1.0, %2.0 as iN
5286 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
5287 //
5288 // %lo = %3.LO
5289 // %hi = %5.0
5290 // %ovf = %0 || %1.1 || %2.1 || %5.1
5291 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
5292 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
5293 GetExpandedInteger(Op: LHS, Lo&: LHSLow, Hi&: LHSHigh);
5294 GetExpandedInteger(Op: RHS, Lo&: RHSLow, Hi&: RHSHigh);
5295 EVT HalfVT = LHSLow.getValueType();
5296 EVT BitVT = N->getValueType(ResNo: 1);
5297 SDVTList VTHalfWithO = DAG.getVTList(VT1: HalfVT, VT2: BitVT);
5298
5299 SDValue HalfZero = DAG.getConstant(Val: 0, DL: dl, VT: HalfVT);
5300 SDValue Overflow = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BitVT,
5301 N1: DAG.getSetCC(DL: dl, VT: BitVT, LHS: LHSHigh, RHS: HalfZero, Cond: ISD::SETNE),
5302 N2: DAG.getSetCC(DL: dl, VT: BitVT, LHS: RHSHigh, RHS: HalfZero, Cond: ISD::SETNE));
5303
5304 SDValue One = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: LHSHigh, N2: RHSLow);
5305 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: One.getValue(R: 1));
5306
5307 SDValue Two = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: RHSHigh, N2: LHSLow);
5308 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Two.getValue(R: 1));
5309
5310 SDValue HighSum = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: HalfVT, N1: One, N2: Two);
5311
5312 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
5313 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
5314 // operation recursively legalized?).
5315 //
5316 // Many backends understand this pattern and will convert into LOHI
5317 // themselves, if applicable.
5318 SDValue Three = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT,
5319 N1: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: LHSLow),
5320 N2: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: RHSLow));
5321 SplitInteger(Op: Three, Lo, Hi);
5322
5323 Hi = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList: VTHalfWithO, N1: Hi, N2: HighSum);
5324 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Hi.getValue(R: 1));
5325 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5326 return;
5327 }
5328
5329 Type *RetTy = VT.getTypeForEVT(Context&: *DAG.getContext());
5330 EVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
5331 Type *PtrTy = PtrVT.getTypeForEVT(Context&: *DAG.getContext());
5332
5333 // Replace this with a libcall that will check overflow.
5334 RTLIB::Libcall LC = RTLIB::getMULO(VT);
5335 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
5336
5337 // If we don't have the libcall or if the function we are compiling is the
5338 // implementation of the expected libcall (avoid inf-loop), expand inline.
5339 if (LCImpl == RTLIB::Unsupported ||
5340 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LCImpl) ==
5341 DAG.getMachineFunction().getName()) {
5342 // FIXME: This is not an optimal expansion, but better than crashing.
5343 SDValue MulLo, MulHi;
5344 TLI.forceExpandWideMUL(DAG, dl, /*Signed=*/true, LHS: N->getOperand(Num: 0),
5345 RHS: N->getOperand(Num: 1), Lo&: MulLo, Hi&: MulHi);
5346 SDValue SRA = DAG.getNode(
5347 Opcode: ISD::SRA, DL: dl, VT, N1: MulLo,
5348 N2: DAG.getShiftAmountConstant(Val: VT.getScalarSizeInBits() - 1, VT, DL: dl));
5349 SDValue Overflow =
5350 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: MulHi, RHS: SRA, Cond: ISD::SETNE);
5351 SplitInteger(Op: MulLo, Lo, Hi);
5352 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5353 return;
5354 }
5355
5356 SDValue Temp = DAG.CreateStackTemporary(VT: PtrVT);
5357 // Temporary for the overflow value, default it to zero.
5358 SDValue Chain =
5359 DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT), Ptr: Temp,
5360 PtrInfo: MachinePointerInfo());
5361
5362 TargetLowering::ArgListTy Args;
5363 for (const SDValue &Op : N->op_values()) {
5364 EVT ArgVT = Op.getValueType();
5365 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
5366 TargetLowering::ArgListEntry Entry(Op, ArgTy);
5367 Entry.IsSExt = true;
5368 Entry.IsZExt = false;
5369 Args.push_back(x: Entry);
5370 }
5371
5372 // Also pass the address of the overflow check.
5373 TargetLowering::ArgListEntry Entry(
5374 Temp, PointerType::getUnqual(C&: PtrTy->getContext()));
5375 Entry.IsSExt = true;
5376 Entry.IsZExt = false;
5377 Args.push_back(x: Entry);
5378
5379 SDValue Func = DAG.getExternalSymbol(LCImpl, VT: PtrVT);
5380
5381 TargetLowering::CallLoweringInfo CLI(DAG);
5382 CLI.setDebugLoc(dl)
5383 .setChain(Chain)
5384 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
5385 Target: Func, ArgsList: std::move(Args))
5386 .setSExtResult();
5387
5388 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
5389
5390 SplitInteger(Op: CallInfo.first, Lo, Hi);
5391 SDValue Temp2 =
5392 DAG.getLoad(VT: PtrVT, dl, Chain: CallInfo.second, Ptr: Temp, PtrInfo: MachinePointerInfo());
5393 SDValue Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Temp2,
5394 RHS: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT),
5395 Cond: ISD::SETNE);
5396 // Use the overflow from the libcall everywhere.
5397 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
5398}
5399
5400void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
5401 SDValue &Lo, SDValue &Hi) {
5402 EVT VT = N->getValueType(ResNo: 0);
5403 SDLoc dl(N);
5404 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5405
5406 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5407 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5408 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5409 return;
5410 }
5411
5412 // Try to expand UDIV by constant.
5413 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5414 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5415 // Only if the new type is legal.
5416 if (isTypeLegal(VT: NVT)) {
5417 SDValue InL, InH;
5418 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5419 SmallVector<SDValue> Result;
5420 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5421 Lo = Result[0];
5422 Hi = Result[1];
5423 return;
5424 }
5425 }
5426 }
5427
5428 RTLIB::Libcall LC = RTLIB::getUDIV(VT);
5429 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
5430
5431 TargetLowering::MakeLibCallOptions CallOptions;
5432 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5433}
5434
5435void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
5436 SDValue &Lo, SDValue &Hi) {
5437 EVT VT = N->getValueType(ResNo: 0);
5438 SDLoc dl(N);
5439 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5440
5441 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5442 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5443 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5444 return;
5445 }
5446
5447 // Try to expand UREM by constant.
5448 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5449 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5450 // Only if the new type is legal.
5451 if (isTypeLegal(VT: NVT)) {
5452 SDValue InL, InH;
5453 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5454 SmallVector<SDValue> Result;
5455 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5456 Lo = Result[0];
5457 Hi = Result[1];
5458 return;
5459 }
5460 }
5461 }
5462
5463 RTLIB::Libcall LC = RTLIB::getUREM(VT);
5464 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
5465
5466 TargetLowering::MakeLibCallOptions CallOptions;
5467 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5468}
5469
5470void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
5471 SDValue &Lo, SDValue &Hi) {
5472 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5473 SDLoc dl(N);
5474 SDValue Op = N->getOperand(Num: 0);
5475 if (Op.getValueType().bitsLE(VT: NVT)) {
5476 // The low part is zero extension of the input (degenerates to a copy).
5477 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5478 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // The high part is just a zero.
5479 } else {
5480 // For example, extension of an i48 to an i64. The operand type necessarily
5481 // promotes to the result type, so will end up being expanded too.
5482 assert(getTypeAction(Op.getValueType()) ==
5483 TargetLowering::TypePromoteInteger &&
5484 "Only know how to promote this result!");
5485 SDValue Res = GetPromotedInteger(Op);
5486 assert(Res.getValueType() == N->getValueType(0) &&
5487 "Operand over promoted?");
5488 // Split the promoted operand. This will simplify when it is expanded.
5489 SplitInteger(Op: Res, Lo, Hi);
5490 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5491 Hi = DAG.getZeroExtendInReg(Op: Hi, DL: dl,
5492 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
5493 BitWidth: ExcessBits));
5494 }
5495}
5496
5497void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
5498 SDValue &Lo, SDValue &Hi) {
5499 SDLoc dl(N);
5500 EVT VT = cast<AtomicSDNode>(Val: N)->getMemoryVT();
5501 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::i1, VT3: MVT::Other);
5502 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
5503 SDValue Swap = DAG.getAtomicCmpSwap(
5504 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
5505 MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(), VTs, Chain: N->getOperand(Num: 0),
5506 Ptr: N->getOperand(Num: 1), Cmp: Zero, Swp: Zero, MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5507
5508 ReplaceValueWith(From: SDValue(N, 0), To: Swap.getValue(R: 0));
5509 ReplaceValueWith(From: SDValue(N, 1), To: Swap.getValue(R: 2));
5510}
5511
5512void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
5513 SDValue &Lo, SDValue &Hi) {
5514 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
5515 // both halves independently.
5516 SDValue Res = TLI.expandVecReduce(Node: N, DAG);
5517 SplitInteger(Op: Res, Lo, Hi);
5518}
5519
5520void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
5521 SDValue &Lo, SDValue &Hi) {
5522 // Delegate to funnel-shift expansion.
5523 SDLoc DL(N);
5524 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR;
5525 SDValue Res = DAG.getNode(Opcode, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
5526 N2: N->getOperand(Num: 0), N3: N->getOperand(Num: 1));
5527 SplitInteger(Op: Res, Lo, Hi);
5528}
5529
5530void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
5531 SDValue &Hi) {
5532 // Values numbered from least significant to most significant.
5533 SDValue In1, In2, In3, In4;
5534 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: In3, Hi&: In4);
5535 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: In1, Hi&: In2);
5536 EVT HalfVT = In1.getValueType();
5537
5538 SDLoc DL(N);
5539 unsigned Opc = N->getOpcode();
5540 SDValue ShAmt = N->getOperand(Num: 2);
5541 EVT ShAmtVT = ShAmt.getValueType();
5542 EVT ShAmtCCVT = getSetCCResultType(VT: ShAmtVT);
5543
5544 // If the shift amount is at least half the bitwidth, swap the inputs.
5545 unsigned HalfVTBits = HalfVT.getScalarSizeInBits();
5546 SDValue AndNode = DAG.getNode(Opcode: ISD::AND, DL, VT: ShAmtVT, N1: ShAmt,
5547 N2: DAG.getConstant(Val: HalfVTBits, DL, VT: ShAmtVT));
5548 SDValue Cond =
5549 DAG.getSetCC(DL, VT: ShAmtCCVT, LHS: AndNode, RHS: DAG.getConstant(Val: 0, DL, VT: ShAmtVT),
5550 Cond: Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ);
5551
5552 // Expand to a pair of funnel shifts.
5553 EVT NewShAmtVT = TLI.getShiftAmountTy(LHSTy: HalfVT, DL: DAG.getDataLayout());
5554 SDValue NewShAmt = DAG.getAnyExtOrTrunc(Op: ShAmt, DL, VT: NewShAmtVT);
5555
5556 SDValue Select1 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In1, N3: In2);
5557 SDValue Select2 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In2, N3: In3);
5558 SDValue Select3 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In3, N3: In4);
5559 Lo = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select2, N2: Select1, N3: NewShAmt);
5560 Hi = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select3, N2: Select2, N3: NewShAmt);
5561}
5562
5563void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo, SDValue &Hi) {
5564 if (N->getOpcode() != ISD::CLMUL) {
5565 SDValue Res = TLI.expandCLMUL(N, DAG);
5566 return SplitInteger(Op: Res, Lo, Hi);
5567 }
5568
5569 SDValue LL, LH, RL, RH;
5570 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
5571 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
5572 EVT HalfVT = LL.getValueType();
5573 SDLoc DL(N);
5574
5575 // The low bits are a direct CLMUL of the the low bits.
5576 Lo = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RL);
5577
5578 // We compute two Hi-Lo cross-products, XOR them, and XOR it with the overflow
5579 // of the CLMUL of the low bits (given by CLMULH of the low bits) to yield the
5580 // final high bits.
5581 SDValue LoH = DAG.getNode(Opcode: ISD::CLMULH, DL, VT: HalfVT, N1: LL, N2: RL);
5582 SDValue HiLoCross1 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RH);
5583 SDValue HiLoCross2 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LH, N2: RL);
5584 SDValue HiLoCross = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: HiLoCross1, N2: HiLoCross2);
5585 Hi = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: LoH, N2: HiLoCross);
5586}
5587
5588void DAGTypeLegalizer::ExpandIntRes_PEXT(SDNode *N, SDValue &Lo, SDValue &Hi) {
5589 SDValue Res = TLI.expandPEXT(N, DAG);
5590 SplitInteger(Op: Res, Lo, Hi);
5591}
5592
5593void DAGTypeLegalizer::ExpandIntRes_PDEP(SDNode *N, SDValue &Lo, SDValue &Hi) {
5594 SDValue Res = TLI.expandPDEP(N, DAG);
5595 SplitInteger(Op: Res, Lo, Hi);
5596}
5597
5598void DAGTypeLegalizer::ExpandIntRes_MULH(SDNode *N, SDValue &Lo, SDValue &Hi) {
5599 SDValue Res = TLI.expandMULH(Node: N, DAG);
5600 SplitInteger(Op: Res, Lo, Hi);
5601}
5602
5603void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
5604 SDValue &Hi) {
5605 EVT VT = N->getValueType(ResNo: 0);
5606 EVT HalfVT =
5607 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: N->getValueSizeInBits(ResNo: 0) / 2);
5608 SDLoc dl(N);
5609
5610 // We assume VSCALE(1) fits into a legal integer.
5611 APInt One(HalfVT.getSizeInBits(), 1);
5612 SDValue VScaleBase = DAG.getVScale(DL: dl, VT: HalfVT, MulImm: One);
5613 VScaleBase = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: VScaleBase);
5614 SDValue Res = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: VScaleBase, N2: N->getOperand(Num: 0));
5615 SplitInteger(Op: Res, Lo, Hi);
5616}
5617
5618void DAGTypeLegalizer::ExpandIntRes_READ_REGISTER(SDNode *N, SDValue &Lo,
5619 SDValue &Hi) {
5620 const Function &Fn = DAG.getMachineFunction().getFunction();
5621 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
5622 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
5623 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
5624 EVT LoVT, HiVT;
5625 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: N->getValueType(ResNo: 0));
5626 Lo = DAG.getPOISON(VT: LoVT);
5627 Hi = DAG.getPOISON(VT: HiVT);
5628}
5629
5630void DAGTypeLegalizer::ExpandIntRes_CTTZ_ELTS(SDNode *N, SDValue &Lo,
5631 SDValue &Hi) {
5632 // Assume that the maximum number of vector elements fits in getVectorIdxTy
5633 // and expand to that.
5634 EVT VT = N->getSimpleValueType(ResNo: 0);
5635 EVT IdxVT = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
5636 assert(IdxVT.bitsLT(VT) &&
5637 "VectorIdxTy should be smaller than type to be expanded?");
5638
5639 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: IdxVT, Operand: N->getOperand(Num: 0));
5640 Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: SDLoc(N), VT, Operand: Res);
5641 SplitInteger(Op: Res, Lo, Hi);
5642}
5643
5644//===----------------------------------------------------------------------===//
5645// Integer Operand Expansion
5646//===----------------------------------------------------------------------===//
5647
5648/// ExpandIntegerOperand - This method is called when the specified operand of
5649/// the specified node is found to need expansion. At this point, all of the
5650/// result types of the node are known to be legal, but other operands of the
5651/// node may need promotion or expansion as well as the specified one.
5652bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
5653 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG));
5654 SDValue Res = SDValue();
5655
5656 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false))
5657 return false;
5658
5659 switch (N->getOpcode()) {
5660 default:
5661 #ifndef NDEBUG
5662 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
5663 N->dump(&DAG); dbgs() << "\n";
5664 #endif
5665 report_fatal_error(reason: "do not know how to expand this operator's operand!");
5666
5667 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
5668 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
5669 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
5670 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
5671 case ISD::FAKE_USE:
5672 Res = ExpandOp_FAKE_USE(N);
5673 break;
5674 case ISD::LOOP_DEPENDENCE_RAW_MASK:
5675 case ISD::LOOP_DEPENDENCE_WAR_MASK:
5676 Res = TLI.expandLoopDependenceMask(N, DAG);
5677 break;
5678 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
5679 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
5680 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
5681 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
5682 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
5683 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
5684 case ISD::STRICT_SINT_TO_FP:
5685 case ISD::SINT_TO_FP:
5686 case ISD::STRICT_UINT_TO_FP:
5687 case ISD::UINT_TO_FP: Res = ExpandIntOp_XINT_TO_FP(N); break;
5688 case ISD::STORE: Res = ExpandIntOp_STORE(N: cast<StoreSDNode>(Val: N), OpNo); break;
5689 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
5690
5691 case ISD::SHL:
5692 case ISD::SRA:
5693 case ISD::SRL:
5694 case ISD::ROTL:
5695 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
5696 case ISD::RETURNADDR:
5697 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
5698
5699 case ISD::SCMP:
5700 case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
5701
5702 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
5703 case ISD::STACKMAP:
5704 Res = ExpandIntOp_STACKMAP(N, OpNo);
5705 break;
5706 case ISD::PATCHPOINT:
5707 Res = ExpandIntOp_PATCHPOINT(N, OpNo);
5708 break;
5709 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
5710 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
5711 Res = ExpandIntOp_VP_STRIDED(N, OpNo);
5712 break;
5713 case ISD::WRITE_REGISTER:
5714 Res = ExpandIntOp_WRITE_REGISTER(N, OpNo);
5715 break;
5716 }
5717
5718 // If the result is null, the sub-method took care of registering results etc.
5719 if (!Res.getNode()) return false;
5720
5721 // If the result is N, the sub-method updated N in place. Tell the legalizer
5722 // core about this.
5723 if (Res.getNode() == N)
5724 return true;
5725
5726 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
5727 "Invalid operand expansion");
5728
5729 ReplaceValueWith(From: SDValue(N, 0), To: Res);
5730 return false;
5731}
5732
5733/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
5734/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
5735void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
5736 SDValue &NewRHS,
5737 ISD::CondCode &CCCode,
5738 const SDLoc &dl) {
5739 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5740 GetExpandedInteger(Op: NewLHS, Lo&: LHSLo, Hi&: LHSHi);
5741 GetExpandedInteger(Op: NewRHS, Lo&: RHSLo, Hi&: RHSHi);
5742
5743 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
5744 if (RHSLo == RHSHi && isAllOnesConstant(V: RHSLo)) {
5745 // Equality comparison to -1.
5746 NewLHS = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: LHSHi);
5747 NewRHS = RHSLo;
5748 return;
5749 }
5750
5751 NewLHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: RHSLo);
5752 NewRHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSHi, N2: RHSHi);
5753 NewLHS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NewLHS.getValueType(), N1: NewLHS, N2: NewRHS);
5754 NewRHS = DAG.getConstant(Val: 0, DL: dl, VT: NewLHS.getValueType());
5755 return;
5756 }
5757
5758 // If this is a comparison of the sign bit, just look at the top part.
5759 // X > -1, x < 0
5760 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Val&: NewRHS))
5761 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0
5762 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1
5763 NewLHS = LHSHi;
5764 NewRHS = RHSHi;
5765 return;
5766 }
5767
5768 // FIXME: This generated code sucks.
5769 ISD::CondCode LowCC;
5770 switch (CCCode) {
5771 default: llvm_unreachable("Unknown integer setcc!");
5772 case ISD::SETLT:
5773 case ISD::SETULT: LowCC = ISD::SETULT; break;
5774 case ISD::SETGT:
5775 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5776 case ISD::SETLE:
5777 case ISD::SETULE: LowCC = ISD::SETULE; break;
5778 case ISD::SETGE:
5779 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5780 }
5781
5782 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
5783 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
5784 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
5785
5786 // NOTE: on targets without efficient SELECT of bools, we can always use
5787 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5788 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
5789 nullptr);
5790 SDValue LoCmp, HiCmp;
5791 if (TLI.isTypeLegal(VT: LHSLo.getValueType()))
5792 LoCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSLo.getValueType()), N0: LHSLo,
5793 N1: RHSLo, Cond: LowCC, foldBooleans: false, DCI&: DagCombineInfo, dl);
5794 if (!LoCmp.getNode())
5795 LoCmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LHSLo.getValueType()), LHS: LHSLo,
5796 RHS: RHSLo, Cond: LowCC);
5797 if (TLI.isTypeLegal(VT: LHSHi.getValueType()))
5798 HiCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSHi.getValueType()), N0: LHSHi,
5799 N1: RHSHi, Cond: CCCode, foldBooleans: false, DCI&: DagCombineInfo, dl);
5800 if (!HiCmp.getNode())
5801 HiCmp =
5802 DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: getSetCCResultType(VT: LHSHi.getValueType()),
5803 N1: LHSHi, N2: RHSHi, N3: DAG.getCondCode(Cond: CCCode));
5804
5805 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(Val: LoCmp.getNode());
5806 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(Val: HiCmp.getNode());
5807
5808 bool EqAllowed = ISD::isTrueWhenEqual(Cond: CCCode);
5809
5810 // FIXME: Is the HiCmpC->isOne() here correct for
5811 // ZeroOrNegativeOneBooleanContent.
5812 if ((EqAllowed && (HiCmpC && HiCmpC->isZero())) ||
5813 (!EqAllowed &&
5814 ((HiCmpC && HiCmpC->isOne()) || (LoCmpC && LoCmpC->isZero())))) {
5815 // For LE / GE, if high part is known false, ignore the low part.
5816 // For LT / GT: if low part is known false, return the high part.
5817 // if high part is known true, ignore the low part.
5818 NewLHS = HiCmp;
5819 NewRHS = SDValue();
5820 return;
5821 }
5822
5823 if (LHSHi == RHSHi) {
5824 // Comparing the low bits is enough.
5825 NewLHS = LoCmp;
5826 NewRHS = SDValue();
5827 return;
5828 }
5829
5830 // Lower with SETCCCARRY if the target supports it.
5831 EVT HiVT = LHSHi.getValueType();
5832 EVT ExpandVT = TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: HiVT);
5833 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(Op: ISD::SETCCCARRY, VT: ExpandVT);
5834
5835 // FIXME: Make all targets support this, then remove the other lowering.
5836 if (HasSETCCCARRY) {
5837 // SETCCCARRY can detect < and >= directly. For > and <=, flip
5838 // operands and condition code.
5839 bool FlipOperands = false;
5840 switch (CCCode) {
5841 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
5842 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
5843 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
5844 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
5845 default: break;
5846 }
5847 if (FlipOperands) {
5848 std::swap(a&: LHSLo, b&: RHSLo);
5849 std::swap(a&: LHSHi, b&: RHSHi);
5850 }
5851 // Perform a wide subtraction, feeding the carry from the low part into
5852 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
5853 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
5854 // zero or positive iff LHS >= RHS.
5855 EVT LoVT = LHSLo.getValueType();
5856 SDVTList VTList = DAG.getVTList(VT1: LoVT, VT2: getSetCCResultType(VT: LoVT));
5857 SDValue LowCmp = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: LHSLo, N2: RHSLo);
5858 SDValue Res = DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: getSetCCResultType(VT: HiVT),
5859 N1: LHSHi, N2: RHSHi, N3: LowCmp.getValue(R: 1),
5860 N4: DAG.getCondCode(Cond: CCCode));
5861 NewLHS = Res;
5862 NewRHS = SDValue();
5863 return;
5864 }
5865
5866 NewLHS = TLI.SimplifySetCC(VT: getSetCCResultType(VT: HiVT), N0: LHSHi, N1: RHSHi, Cond: ISD::SETEQ,
5867 foldBooleans: false, DCI&: DagCombineInfo, dl);
5868 if (!NewLHS.getNode())
5869 NewLHS =
5870 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: HiVT), LHS: LHSHi, RHS: RHSHi, Cond: ISD::SETEQ);
5871 NewLHS = DAG.getSelect(DL: dl, VT: LoCmp.getValueType(), Cond: NewLHS, LHS: LoCmp, RHS: HiCmp);
5872 NewRHS = SDValue();
5873}
5874
5875SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
5876 SDValue NewLHS = N->getOperand(Num: 2), NewRHS = N->getOperand(Num: 3);
5877 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get();
5878 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5879
5880 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5881 // against zero to select between true and false values.
5882 if (!NewRHS.getNode()) {
5883 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5884 CCCode = ISD::SETNE;
5885 }
5886
5887 // Update N to have the operands specified.
5888 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
5889 Op2: DAG.getCondCode(Cond: CCCode), Op3: NewLHS, Op4: NewRHS,
5890 Op5: N->getOperand(Num: 4)), 0);
5891}
5892
5893SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
5894 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5895 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
5896 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5897
5898 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5899 // against zero to select between true and false values.
5900 if (!NewRHS.getNode()) {
5901 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5902 CCCode = ISD::SETNE;
5903 }
5904
5905 // Update N to have the operands specified.
5906 return SDValue(DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS,
5907 Op3: N->getOperand(Num: 2), Op4: N->getOperand(Num: 3),
5908 Op5: DAG.getCondCode(Cond: CCCode)), 0);
5909}
5910
5911SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
5912 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5913 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
5914 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5915
5916 // If ExpandSetCCOperands returned a scalar, use it.
5917 if (!NewRHS.getNode()) {
5918 assert(NewLHS.getValueType() == N->getValueType(0) &&
5919 "Unexpected setcc expansion!");
5920 return NewLHS;
5921 }
5922
5923 // Otherwise, update N to have the operands specified.
5924 return SDValue(
5925 DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS, Op3: DAG.getCondCode(Cond: CCCode)), 0);
5926}
5927
5928SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
5929 SDValue LHS = N->getOperand(Num: 0);
5930 SDValue RHS = N->getOperand(Num: 1);
5931 SDValue Carry = N->getOperand(Num: 2);
5932 SDValue Cond = N->getOperand(Num: 3);
5933 SDLoc dl = SDLoc(N);
5934
5935 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5936 GetExpandedInteger(Op: LHS, Lo&: LHSLo, Hi&: LHSHi);
5937 GetExpandedInteger(Op: RHS, Lo&: RHSLo, Hi&: RHSHi);
5938
5939 // Expand to a USUBO_CARRY for the low part and a SETCCCARRY for the high.
5940 SDVTList VTList = DAG.getVTList(VT1: LHSLo.getValueType(), VT2: Carry.getValueType());
5941 SDValue LowCmp =
5942 DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: LHSLo, N2: RHSLo, N3: Carry);
5943 return DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: N->getValueType(ResNo: 0), N1: LHSHi, N2: RHSHi,
5944 N3: LowCmp.getValue(R: 1), N4: Cond);
5945}
5946
5947SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
5948 // Split the operand and replace with SPLAT_VECTOR_PARTS.
5949 SDValue Lo, Hi;
5950 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5951 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Lo,
5952 N2: Hi);
5953}
5954
5955SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
5956 // The value being shifted is legal, but the shift amount is too big.
5957 // It follows that either the result of the shift is undefined, or the
5958 // upper half of the shift amount is zero. Just use the lower half.
5959 SDValue Lo, Hi;
5960 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo, Hi);
5961 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Lo), 0);
5962}
5963
5964SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
5965 return TLI.expandCMP(Node: N, DAG);
5966}
5967
5968SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
5969 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
5970 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
5971 // constant to valid type.
5972 SDValue Lo, Hi;
5973 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5974 return SDValue(DAG.UpdateNodeOperands(N, Op: Lo), 0);
5975}
5976
5977SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) {
5978 bool IsStrict = N->isStrictFPOpcode();
5979 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
5980 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
5981 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
5982 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
5983 EVT DstVT = N->getValueType(ResNo: 0);
5984 RTLIB::Libcall LC = IsSigned ? RTLIB::getSINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT)
5985 : RTLIB::getUINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT);
5986 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
5987 "Don't know how to expand this XINT_TO_FP!");
5988 TargetLowering::MakeLibCallOptions CallOptions;
5989 CallOptions.setIsSigned(true);
5990 std::pair<SDValue, SDValue> Tmp =
5991 TLI.makeLibCall(DAG, LC, RetVT: DstVT, Ops: Op, CallOptions, dl: SDLoc(N), Chain);
5992
5993 if (!IsStrict)
5994 return Tmp.first;
5995
5996 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
5997 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
5998 return SDValue();
5999}
6000
6001SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
6002 assert(!N->isAtomic() && "Should have been a ATOMIC_STORE?");
6003
6004 if (ISD::isNormalStore(N))
6005 return ExpandOp_NormalStore(N, OpNo);
6006
6007 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
6008 assert(OpNo == 1 && "Can only expand the stored value so far");
6009
6010 EVT VT = N->getOperand(Num: 1).getValueType();
6011 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6012 SDValue Ch = N->getChain();
6013 SDValue Ptr = N->getBasePtr();
6014 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
6015 MMOMetadata Metadata = N->getMMOMetadataForSubAccess();
6016 SDLoc dl(N);
6017 SDValue Lo, Hi;
6018
6019 assert(NVT.isByteSized() && "Expanded type not byte sized!");
6020
6021 if (N->getMemoryVT().bitsLE(VT: NVT)) {
6022 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6023 return DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(),
6024 SVT: N->getMemoryVT(), Alignment: N->getBaseAlign(), MMOFlags,
6025 Metadata);
6026 }
6027
6028 if (DAG.getDataLayout().isLittleEndian()) {
6029 // Little-endian - low bits are at low addresses.
6030 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6031
6032 Lo = DAG.getStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
6033 MMOFlags, Metadata);
6034
6035 unsigned ExcessBits =
6036 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
6037 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
6038
6039 // Increment the pointer to the other half.
6040 unsigned IncrementSize = NVT.getSizeInBits()/8;
6041 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6042 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr,
6043 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6044 SVT: NEVT, Alignment: N->getBaseAlign(), MMOFlags, Metadata);
6045 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6046 }
6047
6048 // Big-endian - high bits are at low addresses. Favor aligned stores at
6049 // the cost of some bit-fiddling.
6050 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6051
6052 EVT ExtVT = N->getMemoryVT();
6053 unsigned EBytes = ExtVT.getStoreSize();
6054 unsigned IncrementSize = NVT.getSizeInBits()/8;
6055 unsigned ExcessBits = (EBytes - IncrementSize)*8;
6056 EVT HiVT = EVT::getIntegerVT(Context&: *DAG.getContext(),
6057 BitWidth: ExtVT.getSizeInBits() - ExcessBits);
6058
6059 if (ExcessBits < NVT.getSizeInBits()) {
6060 // Transfer high bits from the top of Lo to the bottom of Hi.
6061 Hi = DAG.getNode(
6062 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
6063 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
6064 Hi = DAG.getNode(
6065 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Hi,
6066 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Lo,
6067 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
6068 }
6069
6070 // Store both the high bits and maybe some of the low bits.
6071 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr, PtrInfo: N->getPointerInfo(), SVT: HiVT,
6072 Alignment: N->getBaseAlign(), MMOFlags, Metadata);
6073
6074 // Increment the pointer to the other half.
6075 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6076 // Store the lowest ExcessBits bits in the second half.
6077 Lo = DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr,
6078 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6079 SVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
6080 Alignment: N->getBaseAlign(), MMOFlags, Metadata);
6081 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6082}
6083
6084SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
6085 SDValue InL, InH;
6086 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
6087 // Just truncate the low part of the source.
6088 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: InL);
6089}
6090
6091SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
6092 SDLoc dl(N);
6093 SDValue Swap =
6094 DAG.getAtomic(Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(),
6095 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 2), Val: N->getOperand(Num: 1),
6096 MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
6097 return Swap.getValue(R: 1);
6098}
6099
6100SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
6101 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
6102 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
6103
6104 SDValue Hi; // The upper half is dropped out.
6105 SmallVector<SDValue, 8> NewOps(N->ops());
6106 GetExpandedInteger(Op: NewOps[OpNo], Lo&: NewOps[OpNo], Hi);
6107
6108 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
6109}
6110
6111SDValue DAGTypeLegalizer::ExpandIntOp_WRITE_REGISTER(SDNode *N, unsigned OpNo) {
6112 const Function &Fn = DAG.getMachineFunction().getFunction();
6113 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6114 "cannot use llvm.write_register with illegal type", Fn,
6115 N->getDebugLoc()));
6116
6117 return N->getOperand(Num: 0);
6118}
6119
6120SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
6121 SDLoc dl(N);
6122
6123 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6124 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6125 EVT OutVT = V0.getValueType();
6126
6127 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: OutVT, N1: V0, N2: V1, N3: N->getOperand(Num: 2));
6128}
6129
6130SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REPEAT(SDNode *N) {
6131 SDLoc DL(N);
6132
6133 EVT OutVT = N->getValueType(ResNo: 0);
6134 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6135 EVT NInVT = N->getOperand(Num: 0).getValueType().changeVectorElementType(
6136 Context&: *DAG.getContext(), EltVT: NOutVT.getVectorElementType());
6137
6138 SDValue Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: NInVT, Operand: N->getOperand(Num: 0));
6139 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NOutVT, Operand: Op);
6140}
6141
6142SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(SDNode *N) {
6143 SDLoc DL(N);
6144 unsigned Factor = N->getNumOperands();
6145
6146 SmallVector<SDValue, 8> Ops(Factor);
6147 for (unsigned i = 0; i != Factor; i++)
6148 Ops[i] = GetPromotedInteger(Op: N->getOperand(Num: i));
6149
6150 SmallVector<EVT, 8> ResVTs(Factor, Ops[0].getValueType());
6151 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VTs: ResVTs), Ops);
6152
6153 for (unsigned i = 0; i != Factor; i++)
6154 SetPromotedInteger(Op: SDValue(N, i), Result: Res.getValue(R: i));
6155
6156 return SDValue();
6157}
6158
6159SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
6160
6161 EVT OutVT = N->getValueType(ResNo: 0);
6162 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6163 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6164 EVT NOutVTElem = NOutVT.getVectorElementType();
6165
6166 SDLoc dl(N);
6167 SDValue BaseIdx = N->getOperand(Num: 1);
6168
6169 // TODO: We may be able to use this for types other than scalable
6170 // vectors and fix those tests that expect BUILD_VECTOR to be used
6171 if (OutVT.isScalableVector()) {
6172 SDValue InOp0 = N->getOperand(Num: 0);
6173 EVT InVT = InOp0.getValueType();
6174
6175 // Try and extract from a smaller type so that it eventually falls
6176 // into the promotion code below.
6177 if (getTypeAction(VT: InVT) == TargetLowering::TypeSplitVector ||
6178 getTypeAction(VT: InVT) == TargetLowering::TypeLegal) {
6179 EVT NInVT = InVT.getHalfNumVectorElementsVT(Context&: *DAG.getContext());
6180 unsigned NElts = NInVT.getVectorMinNumElements();
6181 uint64_t IdxVal = BaseIdx->getAsZExtVal();
6182
6183 SDValue Step1 = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NInVT, N1: InOp0,
6184 N2: DAG.getConstant(Val: alignDown(Value: IdxVal, Align: NElts), DL: dl,
6185 VT: BaseIdx.getValueType()));
6186 SDValue Step2 = DAG.getNode(
6187 Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Step1,
6188 N2: DAG.getConstant(Val: IdxVal % NElts, DL: dl, VT: BaseIdx.getValueType()));
6189 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Step2);
6190 }
6191
6192 // Try and extract from a widened type.
6193 if (getTypeAction(VT: InVT) == TargetLowering::TypeWidenVector) {
6194 SDValue Ops[] = {GetWidenedVector(Op: InOp0), BaseIdx};
6195 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: OutVT, Ops);
6196 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6197 }
6198
6199 // Promote operands and see if this is handled by target lowering,
6200 // Otherwise, use the BUILD_VECTOR approach below
6201 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
6202 // Collect the (promoted) operands
6203 SDValue Ops[] = { GetPromotedInteger(Op: InOp0), BaseIdx };
6204
6205 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
6206 assert(PromEltVT.bitsLE(NOutVTElem) &&
6207 "Promoted operand has an element type greater than result");
6208
6209 EVT ExtVT = NOutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: PromEltVT);
6210 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: ExtVT, Ops);
6211 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6212 }
6213 }
6214
6215 if (OutVT.isScalableVector())
6216 report_fatal_error(reason: "Unable to promote scalable types using BUILD_VECTOR");
6217
6218 SDValue InOp0 = N->getOperand(Num: 0);
6219 if (getTypeAction(VT: InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
6220 InOp0 = GetPromotedInteger(Op: InOp0);
6221
6222 EVT InVT = InOp0.getValueType();
6223 EVT InSVT = InVT.getVectorElementType();
6224
6225 unsigned OutNumElems = OutVT.getVectorNumElements();
6226 SmallVector<SDValue, 8> Ops;
6227 Ops.reserve(N: OutNumElems);
6228 for (unsigned i = 0; i != OutNumElems; ++i) {
6229 // Extract the element from the original vector.
6230 SDValue Index = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: BaseIdx.getValueType(), N1: BaseIdx,
6231 N2: DAG.getConstant(Val: i, DL: dl, VT: BaseIdx.getValueType()));
6232 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: InSVT,
6233 N1: N->getOperand(Num: 0), N2: Index);
6234 SDValue Op = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NOutVTElem);
6235 // Insert the converted element to the new vector.
6236 Ops.push_back(Elt: Op);
6237 }
6238
6239 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6240}
6241
6242SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
6243 EVT OutVT = N->getValueType(ResNo: 0);
6244 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6245 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6246
6247 SDLoc dl(N);
6248 SDValue Vec = N->getOperand(Num: 0);
6249 SDValue SubVec = N->getOperand(Num: 1);
6250 SDValue Idx = N->getOperand(Num: 2);
6251
6252 EVT SubVecVT = SubVec.getValueType();
6253 EVT NSubVT =
6254 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NOutVT.getVectorElementType(),
6255 EC: SubVecVT.getVectorElementCount());
6256
6257 Vec = GetPromotedInteger(Op: Vec);
6258 SubVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NSubVT, Operand: SubVec);
6259
6260 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: NOutVT, N1: Vec, N2: SubVec, N3: Idx);
6261}
6262
6263SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
6264 SDLoc dl(N);
6265
6266 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6267 EVT OutVT = V0.getValueType();
6268
6269 return DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL: dl, VT: OutVT, Operand: V0);
6270}
6271
6272SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
6273 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(Val: N);
6274 EVT VT = N->getValueType(ResNo: 0);
6275 SDLoc dl(N);
6276
6277 ArrayRef<int> NewMask = SV->getMask().slice(N: 0, M: VT.getVectorNumElements());
6278
6279 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6280 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6281 EVT OutVT = V0.getValueType();
6282
6283 return DAG.getVectorShuffle(VT: OutVT, dl, N1: V0, N2: V1, Mask: NewMask);
6284}
6285
6286SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
6287 EVT OutVT = N->getValueType(ResNo: 0);
6288 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6289 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6290 unsigned NumElems = N->getNumOperands();
6291 EVT NOutVTElem = NOutVT.getVectorElementType();
6292 TargetLoweringBase::BooleanContent NOutBoolType = TLI.getBooleanContents(Type: NOutVT);
6293 unsigned NOutExtOpc = TargetLowering::getExtendForContent(Content: NOutBoolType);
6294 SDLoc dl(N);
6295
6296 SmallVector<SDValue, 8> Ops;
6297 Ops.reserve(N: NumElems);
6298 for (unsigned i = 0; i != NumElems; ++i) {
6299 SDValue Op = N->getOperand(Num: i);
6300 EVT OpVT = Op.getValueType();
6301 // BUILD_VECTOR integer operand types are allowed to be larger than the
6302 // result's element type. This may still be true after the promotion. For
6303 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
6304 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
6305 if (OpVT.bitsLT(VT: NOutVTElem)) {
6306 unsigned ExtOpc = ISD::ANY_EXTEND;
6307 // Attempt to extend constant bool vectors to match target's BooleanContent.
6308 // While not necessary, this improves chances of the constant correctly
6309 // folding with compare results (e.g. for NOT patterns).
6310 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant)
6311 ExtOpc = NOutExtOpc;
6312 Op = DAG.getNode(Opcode: ExtOpc, DL: dl, VT: NOutVTElem, Operand: Op);
6313 }
6314 Ops.push_back(Elt: Op);
6315 }
6316
6317 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6318}
6319
6320SDValue DAGTypeLegalizer::PromoteIntRes_ScalarOp(SDNode *N) {
6321
6322 SDLoc dl(N);
6323
6324 assert(!N->getOperand(0).getValueType().isVector() &&
6325 "Input must be a scalar");
6326
6327 EVT OutVT = N->getValueType(ResNo: 0);
6328 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6329 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6330 EVT NOutElemVT = NOutVT.getVectorElementType();
6331
6332 SDValue Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutElemVT, Operand: N->getOperand(Num: 0));
6333 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NOutVT, Operand: Op);
6334}
6335
6336SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
6337 SDLoc dl(N);
6338 EVT OutVT = N->getValueType(ResNo: 0);
6339 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6340 assert(NOutVT.isScalableVector() &&
6341 "Type must be promoted to a scalable vector type");
6342 const APInt &StepVal = N->getConstantOperandAPInt(Num: 0);
6343 return DAG.getStepVector(DL: dl, ResVT: NOutVT,
6344 StepVal: StepVal.sext(width: NOutVT.getScalarSizeInBits()));
6345}
6346
6347SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
6348 SDLoc dl(N);
6349
6350 EVT OutVT = N->getValueType(ResNo: 0);
6351 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6352 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6353
6354 unsigned NumOperands = N->getNumOperands();
6355 unsigned NumOutElem = NOutVT.getVectorMinNumElements();
6356 EVT OutElemTy = NOutVT.getVectorElementType();
6357 if (OutVT.isScalableVector()) {
6358 EVT OpVT = N->getOperand(Num: 0).getValueType();
6359 TargetLowering::LegalizeTypeAction OpAction = getTypeAction(VT: OpVT);
6360 assert((OpAction == TargetLowering::TypeLegal ||
6361 OpAction == TargetLowering::TypePromoteInteger ||
6362 OpAction == TargetLowering::TypeWidenVector) &&
6363 "Unhandled legalization type");
6364
6365 EVT ExtendedOpVT =
6366 OpVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: OutElemTy);
6367
6368 SmallVector<SDValue, 8> Ops;
6369 for (unsigned I = 0; I < NumOperands; ++I) {
6370 SDValue Op = N->getOperand(Num: I);
6371 if (OpAction == TargetLowering::TypePromoteInteger)
6372 Op = GetPromotedInteger(Op);
6373 else if (OpAction == TargetLowering::TypeWidenVector)
6374 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: ExtendedOpVT, Operand: Op);
6375 Ops.push_back(Elt: Op);
6376 }
6377
6378 // Do the CONCAT on the legalized operands' element type, then extend
6379 // or truncate to the promoted result type.
6380 EVT ConcatVT = OutVT.changeVectorElementType(
6381 Context&: *DAG.getContext(), EltVT: Ops[0].getValueType().getVectorElementType());
6382 return DAG.getAnyExtOrTrunc(
6383 Op: DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl, VT: ConcatVT, Ops), DL: dl, VT: NOutVT);
6384 }
6385
6386 unsigned NumElem = N->getOperand(Num: 0).getValueType().getVectorNumElements();
6387 assert(NumElem * NumOperands == NumOutElem &&
6388 "Unexpected number of elements");
6389
6390 // Take the elements from the first vector.
6391 SmallVector<SDValue, 8> Ops(NumOutElem);
6392 for (unsigned i = 0; i < NumOperands; ++i) {
6393 SDValue Op = N->getOperand(Num: i);
6394 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypePromoteInteger)
6395 Op = GetPromotedInteger(Op);
6396 EVT SclrTy = Op.getValueType().getVectorElementType();
6397 assert(NumElem == Op.getValueType().getVectorNumElements() &&
6398 "Unexpected number of elements");
6399
6400 for (unsigned j = 0; j < NumElem; ++j) {
6401 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Op,
6402 N2: DAG.getVectorIdxConstant(Val: j, DL: dl));
6403 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: OutElemTy);
6404 }
6405 }
6406
6407 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6408}
6409
6410SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
6411 EVT VT = N->getValueType(ResNo: 0);
6412 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6413 assert(NVT.isVector() && "This type must be promoted to a vector type");
6414
6415 SDLoc dl(N);
6416
6417 // For operands whose TypeAction is to promote, extend the promoted node
6418 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
6419 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
6420 // type..
6421 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
6422 == TargetLowering::TypePromoteInteger) {
6423 SDValue Promoted;
6424
6425 switch(N->getOpcode()) {
6426 case ISD::SIGN_EXTEND_VECTOR_INREG:
6427 Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
6428 break;
6429 case ISD::ZERO_EXTEND_VECTOR_INREG:
6430 Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
6431 break;
6432 case ISD::ANY_EXTEND_VECTOR_INREG:
6433 Promoted = GetPromotedInteger(Op: N->getOperand(Num: 0));
6434 break;
6435 default:
6436 llvm_unreachable("Node has unexpected Opcode");
6437 }
6438 unsigned NewSize = NVT.getSizeInBits();
6439 if (Promoted.getValueType().getSizeInBits() > NewSize) {
6440 EVT ExtractVT = EVT::getVectorVT(
6441 Context&: *DAG.getContext(), VT: Promoted.getValueType().getVectorElementType(),
6442 NumElements: NewSize / Promoted.getScalarValueSizeInBits());
6443
6444 Promoted = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: ExtractVT, N1: Promoted,
6445 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
6446 }
6447 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Promoted);
6448 }
6449
6450 // Directly extend to the appropriate transform-to type.
6451 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
6452}
6453
6454SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(SDNode *N) {
6455 EVT VT = N->getValueType(ResNo: 0);
6456 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6457 return DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6458}
6459
6460SDValue DAGTypeLegalizer::PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
6461 EVT VT = N->getValueType(ResNo: 0);
6462 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6463 return DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6464}
6465
6466SDValue DAGTypeLegalizer::PromoteIntRes_MASK_BEFOREFIRST(SDNode *N) {
6467 EVT VT = N->getValueType(ResNo: 0);
6468 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6469 SDValue Op = PromoteTargetBoolean(Bool: N->getOperand(Num: 0), ValVT: NVT);
6470 return DAG.getNode(Opcode: ISD::MASK_BEFOREFIRST, DL: SDLoc(N), VT: NVT, Operand: Op);
6471}
6472
6473SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_MATCH(SDNode *N) {
6474 EVT VT = N->getValueType(ResNo: 0);
6475 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6476 SmallVector<SDValue, 3> NewOps(N->ops());
6477 NewOps[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: NVT);
6478 return DAG.getNode(Opcode: ISD::VECTOR_MATCH, DL: SDLoc(N), VT: NVT, Ops: NewOps, Flags: N->getFlags());
6479}
6480
6481SDValue DAGTypeLegalizer::PromoteIntRes_PARTIAL_REDUCE_MLA(SDNode *N) {
6482 SDLoc DL(N);
6483 EVT VT = N->getValueType(ResNo: 0);
6484 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6485 SDValue ExtAcc = GetPromotedInteger(Op: N->getOperand(Num: 0));
6486 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: ExtAcc, N2: N->getOperand(Num: 1),
6487 N3: N->getOperand(Num: 2));
6488}
6489
6490SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
6491 EVT OutVT = N->getValueType(ResNo: 0);
6492 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6493 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6494
6495 EVT NOutVTElem = NOutVT.getVectorElementType();
6496
6497 SDLoc dl(N);
6498 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6499
6500 SDValue ConvElem = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6501 VT: NOutVTElem, Operand: N->getOperand(Num: 1));
6502 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NOutVT,
6503 N1: V0, N2: ConvElem, N3: N->getOperand(Num: 2));
6504}
6505
6506SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
6507 // The VECREDUCE result size may be larger than the element size, so
6508 // we can simply change the result type.
6509 SDLoc dl(N);
6510 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6511 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Ops: N->ops());
6512}
6513
6514SDValue DAGTypeLegalizer::PromoteIntRes_VP_REDUCE(SDNode *N) {
6515 // The VP_REDUCE result size may be larger than the element size, so we can
6516 // simply change the result type. However the start value and result must be
6517 // the same.
6518 SDLoc DL(N);
6519 SDValue Start = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
6520 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: Start.getValueType(), N1: Start,
6521 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
6522}
6523
6524SDValue DAGTypeLegalizer::PromoteIntRes_PATCHPOINT(SDNode *N) {
6525 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6526 SDLoc dl(N);
6527
6528 assert(N->getNumValues() == 3 && "Expected 3 values for PATCHPOINT");
6529 SDVTList VTList = DAG.getVTList(VTs: {NVT, MVT::Other, MVT::Glue});
6530
6531 SmallVector<SDValue> Ops(N->ops());
6532 SDValue Res = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList, Ops);
6533
6534 // Replace chain and glue uses with the new patchpoint.
6535 SDValue From[] = {SDValue(N, 1), SDValue(N, 2)};
6536 SDValue To[] = {Res.getValue(R: 1), Res.getValue(R: 2)};
6537 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
6538
6539 return Res.getValue(R: 0);
6540}
6541
6542SDValue DAGTypeLegalizer::PromoteIntRes_READ_REGISTER(SDNode *N) {
6543 const Function &Fn = DAG.getMachineFunction().getFunction();
6544 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6545 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
6546
6547 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6548 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
6549 return DAG.getPOISON(VT: NVT);
6550}
6551
6552SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
6553 SDLoc dl(N);
6554 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6555 SDValue V1 = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl,
6556 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
6557 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl,
6558 VT: V0->getValueType(ResNo: 0).getScalarType(), N1: V0, N2: V1);
6559
6560 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
6561 // element types. If this is the case then we need to expand the outgoing
6562 // value and not truncate it.
6563 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6564}
6565
6566SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_SUBVECTOR(SDNode *N) {
6567 SDLoc dl(N);
6568 // The result type is equal to the first input operand's type, so the
6569 // type that needs promoting must be the second source vector.
6570 SDValue V0 = N->getOperand(Num: 0);
6571 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6572 SDValue Idx = N->getOperand(Num: 2);
6573 EVT PromVT = EVT::getVectorVT(Context&: *DAG.getContext(),
6574 VT: V1.getValueType().getVectorElementType(),
6575 EC: V0.getValueType().getVectorElementCount());
6576 V0 = DAG.getAnyExtOrTrunc(Op: V0, DL: dl, VT: PromVT);
6577 SDValue Ext = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: PromVT, N1: V0, N2: V1, N3: Idx);
6578 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6579}
6580
6581// FIXME: We wouldn't need this if clang could promote short integers
6582// that are arguments to FAKE_USE.
6583SDValue DAGTypeLegalizer::PromoteIntOp_FAKE_USE(SDNode *N) {
6584 SDLoc dl(N);
6585 SDValue V0 = N->getOperand(Num: 0);
6586 SDValue V1 = N->getOperand(Num: 1);
6587 EVT InVT1 = V1.getValueType();
6588 SDValue VPromoted =
6589 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6590 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT1), Operand: V1);
6591 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: N->getValueType(ResNo: 0), N1: V0, N2: VPromoted);
6592}
6593
6594SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
6595 SDLoc dl(N);
6596 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6597 MVT InVT = V0.getValueType().getSimpleVT();
6598 MVT OutVT = MVT::getVectorVT(VT: InVT.getVectorElementType(),
6599 NumElements: N->getValueType(ResNo: 0).getVectorNumElements());
6600 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: V0, N2: N->getOperand(Num: 1));
6601 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Ext);
6602}
6603
6604SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
6605 SDLoc dl(N);
6606
6607 EVT ResVT = N->getValueType(ResNo: 0);
6608 unsigned NumElems = N->getNumOperands();
6609
6610 if (ResVT.isScalableVector()) {
6611 SDValue ResVec = DAG.getPOISON(VT: ResVT);
6612
6613 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
6614 SDValue Op = N->getOperand(Num: OpIdx);
6615 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
6616 ResVec = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: ResVT, N1: ResVec, N2: Op,
6617 N3: DAG.getIntPtrConstant(Val: OpIdx * OpNumElts, DL: dl));
6618 }
6619
6620 return ResVec;
6621 }
6622
6623 EVT RetSclrTy = N->getValueType(ResNo: 0).getVectorElementType();
6624
6625 SmallVector<SDValue, 8> NewOps;
6626 NewOps.reserve(N: NumElems);
6627
6628 // For each incoming vector
6629 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
6630 SDValue Incoming = GetPromotedInteger(Op: N->getOperand(Num: VecIdx));
6631 EVT SclrTy = Incoming->getValueType(ResNo: 0).getVectorElementType();
6632 unsigned NumElem = Incoming->getValueType(ResNo: 0).getVectorNumElements();
6633
6634 for (unsigned i=0; i<NumElem; ++i) {
6635 // Extract element from incoming vector
6636 SDValue Ex = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Incoming,
6637 N2: DAG.getVectorIdxConstant(Val: i, DL: dl));
6638 SDValue Tr = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RetSclrTy, Operand: Ex);
6639 NewOps.push_back(Elt: Tr);
6640 }
6641 }
6642
6643 return DAG.getBuildVector(VT: N->getValueType(ResNo: 0), DL: dl, Ops: NewOps);
6644}
6645
6646SDValue DAGTypeLegalizer::ExpandIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
6647 assert(OpNo > 1);
6648 SDValue Op = N->getOperand(Num: OpNo);
6649
6650 // FIXME: Non-constant operands are not yet handled:
6651 // - https://github.com/llvm/llvm-project/issues/26431
6652 // - https://github.com/llvm/llvm-project/issues/55957
6653 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6654 if (!CN)
6655 return SDValue();
6656
6657 // Copy operands before the one being expanded.
6658 SmallVector<SDValue> NewOps;
6659 for (unsigned I = 0; I < OpNo; I++)
6660 NewOps.push_back(Elt: N->getOperand(Num: I));
6661
6662 EVT Ty = Op.getValueType();
6663 SDLoc DL = SDLoc(N);
6664 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6665 NewOps.push_back(
6666 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6667 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6668 } else {
6669 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6670 return SDValue();
6671 }
6672
6673 // Copy remaining operands.
6674 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6675 NewOps.push_back(Elt: N->getOperand(Num: I));
6676
6677 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6678
6679 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6680 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6681
6682 return SDValue(); // Signal that we have replaced the node already.
6683}
6684
6685SDValue DAGTypeLegalizer::ExpandIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
6686 assert(OpNo >= 7);
6687 SDValue Op = N->getOperand(Num: OpNo);
6688
6689 // FIXME: Non-constant operands are not yet handled:
6690 // - https://github.com/llvm/llvm-project/issues/26431
6691 // - https://github.com/llvm/llvm-project/issues/55957
6692 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6693 if (!CN)
6694 return SDValue();
6695
6696 // Copy operands before the one being expanded.
6697 SmallVector<SDValue> NewOps;
6698 for (unsigned I = 0; I < OpNo; I++)
6699 NewOps.push_back(Elt: N->getOperand(Num: I));
6700
6701 EVT Ty = Op.getValueType();
6702 SDLoc DL = SDLoc(N);
6703 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6704 NewOps.push_back(
6705 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6706 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6707 } else {
6708 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6709 return SDValue();
6710 }
6711
6712 // Copy remaining operands.
6713 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6714 NewOps.push_back(Elt: N->getOperand(Num: I));
6715
6716 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6717
6718 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6719 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6720
6721 return SDValue(); // Signal that we have replaced the node already.
6722}
6723