1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetLowering.h"
24#include "llvm/IR/DerivedTypes.h"
25#include "llvm/IR/DiagnosticInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/KnownBits.h"
28#include "llvm/Support/raw_ostream.h"
29#include <algorithm>
30using namespace llvm;
31
32#define DEBUG_TYPE "legalize-types"
33
34//===----------------------------------------------------------------------===//
35// Integer Result Promotion
36//===----------------------------------------------------------------------===//
37
38/// PromoteIntegerResult - This method is called when a result of a node is
39/// found to be in need of promotion to a larger type. At this point, the node
40/// may also have invalid operands or may have other results that need
41/// expansion, we just know that (at least) one result needs promotion.
42void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
43 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG));
44 SDValue Res = SDValue();
45
46 // See if the target wants to custom expand this node.
47 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true)) {
48 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
49 return;
50 }
51
52 switch (N->getOpcode()) {
53 default:
54#ifndef NDEBUG
55 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
56 N->dump(&DAG); dbgs() << "\n";
57#endif
58 report_fatal_error(reason: "Do not know how to promote this operator!");
59 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
60 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
61 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
62 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
63 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
64 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
65 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
66 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
67 case ISD::CTLZ_ZERO_POISON:
68 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
69 case ISD::CTLS: Res = PromoteIntRes_CTLS(N); break;
70 case ISD::PARITY:
71 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
72 case ISD::CTTZ_ZERO_POISON:
73 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
74 case ISD::CTTZ_ELTS_ZERO_POISON:
75 case ISD::CTTZ_ELTS:
76 case ISD::VP_CTTZ_ELTS_ZERO_POISON:
77 case ISD::VP_CTTZ_ELTS:
78 Res = PromoteIntRes_VP_CttzElements(N);
79 break;
80 case ISD::EXTRACT_VECTOR_ELT:
81 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
82 case ISD::LOAD: Res = PromoteIntRes_LOAD(N: cast<LoadSDNode>(Val: N)); break;
83 case ISD::VP_LOAD:
84 Res = PromoteIntRes_VP_LOAD(N: cast<VPLoadSDNode>(Val: N));
85 break;
86 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(N: cast<MaskedLoadSDNode>(Val: N));
87 break;
88 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(N: cast<MaskedGatherSDNode>(Val: N));
89 break;
90 case ISD::VECTOR_COMPRESS:
91 Res = PromoteIntRes_VECTOR_COMPRESS(N);
92 break;
93 case ISD::SELECT:
94 case ISD::VSELECT:
95 case ISD::VP_MERGE:
96 Res = PromoteIntRes_Select(N);
97 break;
98 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
99 case ISD::STRICT_FSETCC:
100 case ISD::STRICT_FSETCCS:
101 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
102 case ISD::SMIN:
103 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
104 case ISD::UMIN:
105 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
106
107 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
108 case ISD::SIGN_EXTEND_INREG:
109 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
110 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
111 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
112 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
113 case ISD::POISON:
114 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
115 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
116 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
117
118 case ISD::EXTRACT_SUBVECTOR:
119 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
120 case ISD::INSERT_SUBVECTOR:
121 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
122 case ISD::VECTOR_REVERSE:
123 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
124 case ISD::VECTOR_SHUFFLE:
125 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
126 case ISD::VECTOR_SPLICE_LEFT:
127 case ISD::VECTOR_SPLICE_RIGHT:
128 Res = PromoteIntRes_VECTOR_SPLICE(N);
129 break;
130 case ISD::VECTOR_INTERLEAVE:
131 case ISD::VECTOR_DEINTERLEAVE:
132 Res = PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(N);
133 return;
134 case ISD::INSERT_VECTOR_ELT:
135 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
136 case ISD::BUILD_VECTOR:
137 Res = PromoteIntRes_BUILD_VECTOR(N);
138 break;
139 case ISD::SPLAT_VECTOR:
140 case ISD::SCALAR_TO_VECTOR:
141 Res = PromoteIntRes_ScalarOp(N);
142 break;
143 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
144 case ISD::CONCAT_VECTORS:
145 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
146
147 case ISD::ANY_EXTEND_VECTOR_INREG:
148 case ISD::SIGN_EXTEND_VECTOR_INREG:
149 case ISD::ZERO_EXTEND_VECTOR_INREG:
150 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
151
152 case ISD::VECTOR_FIND_LAST_ACTIVE:
153 Res = PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(N);
154 break;
155
156 case ISD::GET_ACTIVE_LANE_MASK:
157 Res = PromoteIntRes_GET_ACTIVE_LANE_MASK(N);
158 break;
159 case ISD::VECTOR_MATCH:
160 Res = PromoteIntRes_VECTOR_MATCH(N);
161 break;
162
163 case ISD::PARTIAL_REDUCE_UMLA:
164 case ISD::PARTIAL_REDUCE_SMLA:
165 case ISD::PARTIAL_REDUCE_SUMLA:
166 Res = PromoteIntRes_PARTIAL_REDUCE_MLA(N);
167 break;
168
169 case ISD::SIGN_EXTEND:
170 case ISD::ZERO_EXTEND:
171 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
172
173 case ISD::STRICT_FP_TO_SINT:
174 case ISD::STRICT_FP_TO_UINT:
175 case ISD::FP_TO_SINT:
176 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
177
178 case ISD::FP_TO_SINT_SAT:
179 case ISD::FP_TO_UINT_SAT:
180 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
181
182 case ISD::FP_TO_BF16:
183 case ISD::FP_TO_FP16:
184 Res = PromoteIntRes_FP_TO_FP16_BF16(N);
185 break;
186 case ISD::CONVERT_TO_ARBITRARY_FP:
187 Res = PromoteIntRes_CONVERT_TO_ARBITRARY_FP(N);
188 break;
189 case ISD::STRICT_FP_TO_BF16:
190 case ISD::STRICT_FP_TO_FP16:
191 Res = PromoteIntRes_STRICT_FP_TO_FP16_BF16(N);
192 break;
193 case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break;
194
195 case ISD::AND:
196 case ISD::OR:
197 case ISD::XOR:
198 case ISD::ADD:
199 case ISD::SUB:
200 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
201
202 case ISD::ABDS:
203 case ISD::AVGCEILS:
204 case ISD::AVGFLOORS:
205 case ISD::SDIV:
206 case ISD::SREM:
207 case ISD::VP_SDIV:
208 case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
209
210 case ISD::ABDU:
211 case ISD::AVGCEILU:
212 case ISD::AVGFLOORU:
213 case ISD::UDIV:
214 case ISD::UREM:
215 case ISD::VP_UDIV:
216 case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
217
218 case ISD::MASKED_UDIV:
219 case ISD::MASKED_UREM:
220 Res = PromoteIntRes_ZExtMaskedIntBinOp(N);
221 break;
222 case ISD::MASKED_SDIV:
223 case ISD::MASKED_SREM:
224 Res = PromoteIntRes_SExtMaskedIntBinOp(N);
225 break;
226
227 case ISD::SADDO:
228 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
229 case ISD::UADDO:
230 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
231 case ISD::SMULO:
232 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
233
234 case ISD::ADDE:
235 case ISD::SUBE:
236 case ISD::UADDO_CARRY:
237 case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break;
238
239 case ISD::SADDO_CARRY:
240 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
241
242 case ISD::SADDSAT:
243 case ISD::UADDSAT:
244 case ISD::SSUBSAT:
245 case ISD::USUBSAT:
246 case ISD::SSHLSAT:
247 case ISD::USHLSAT:
248 Res = PromoteIntRes_ADDSUBSHLSAT(N);
249 break;
250
251 case ISD::SCMP:
252 case ISD::UCMP:
253 Res = PromoteIntRes_CMP(N);
254 break;
255
256 case ISD::SMULFIX:
257 case ISD::SMULFIXSAT:
258 case ISD::UMULFIX:
259 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
260
261 case ISD::SDIVFIX:
262 case ISD::SDIVFIXSAT:
263 case ISD::UDIVFIX:
264 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
265
266 case ISD::ABS:
267 case ISD::ABS_MIN_POISON:
268 Res = PromoteIntRes_ABS(N);
269 break;
270
271 case ISD::ATOMIC_LOAD:
272 Res = PromoteIntRes_Atomic0(N: cast<AtomicSDNode>(Val: N)); break;
273
274 case ISD::ATOMIC_LOAD_ADD:
275 case ISD::ATOMIC_LOAD_SUB:
276 case ISD::ATOMIC_LOAD_AND:
277 case ISD::ATOMIC_LOAD_CLR:
278 case ISD::ATOMIC_LOAD_OR:
279 case ISD::ATOMIC_LOAD_XOR:
280 case ISD::ATOMIC_LOAD_NAND:
281 case ISD::ATOMIC_LOAD_MIN:
282 case ISD::ATOMIC_LOAD_MAX:
283 case ISD::ATOMIC_LOAD_UMIN:
284 case ISD::ATOMIC_LOAD_UMAX:
285 case ISD::ATOMIC_SWAP:
286 Res = PromoteIntRes_Atomic1(N: cast<AtomicSDNode>(Val: N)); break;
287
288 case ISD::ATOMIC_CMP_SWAP:
289 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
290 Res = PromoteIntRes_AtomicCmpSwap(N: cast<AtomicSDNode>(Val: N), ResNo);
291 break;
292
293 case ISD::VECREDUCE_ADD:
294 case ISD::VECREDUCE_MUL:
295 case ISD::VECREDUCE_AND:
296 case ISD::VECREDUCE_OR:
297 case ISD::VECREDUCE_XOR:
298 case ISD::VECREDUCE_SMAX:
299 case ISD::VECREDUCE_SMIN:
300 case ISD::VECREDUCE_UMAX:
301 case ISD::VECREDUCE_UMIN:
302 Res = PromoteIntRes_VECREDUCE(N);
303 break;
304
305 case ISD::VP_REDUCE_ADD:
306 case ISD::VP_REDUCE_MUL:
307 case ISD::VP_REDUCE_AND:
308 case ISD::VP_REDUCE_OR:
309 case ISD::VP_REDUCE_XOR:
310 case ISD::VP_REDUCE_SMAX:
311 case ISD::VP_REDUCE_SMIN:
312 case ISD::VP_REDUCE_UMAX:
313 case ISD::VP_REDUCE_UMIN:
314 Res = PromoteIntRes_VP_REDUCE(N);
315 break;
316
317 case ISD::LOOP_DEPENDENCE_WAR_MASK:
318 case ISD::LOOP_DEPENDENCE_RAW_MASK:
319 Res = PromoteIntRes_LOOP_DEPENDENCE_MASK(N);
320 break;
321
322 case ISD::FREEZE:
323 Res = PromoteIntRes_FREEZE(N);
324 break;
325
326 case ISD::ROTL:
327 case ISD::ROTR:
328 Res = PromoteIntRes_Rotate(N);
329 break;
330
331 case ISD::FSHL:
332 case ISD::FSHR:
333 Res = PromoteIntRes_FunnelShift(N);
334 break;
335
336 case ISD::CLMUL:
337 case ISD::CLMULH:
338 case ISD::CLMULR:
339 Res = PromoteIntRes_CLMUL(N);
340 break;
341
342 case ISD::PEXT:
343 Res = PromoteIntRes_PEXT(N);
344 break;
345
346 case ISD::PDEP:
347 Res = PromoteIntRes_PDEP(N);
348 break;
349
350 case ISD::MULHS:
351 case ISD::MULHU:
352 Res = PromoteIntRes_MULH(N);
353 break;
354
355 case ISD::IS_FPCLASS:
356 Res = PromoteIntRes_IS_FPCLASS(N);
357 break;
358 case ISD::FFREXP:
359 Res = PromoteIntRes_FFREXP(N);
360 break;
361
362 case ISD::LRINT:
363 case ISD::LLRINT:
364 Res = PromoteIntRes_XRINT(N);
365 break;
366
367 case ISD::PATCHPOINT:
368 Res = PromoteIntRes_PATCHPOINT(N);
369 break;
370 case ISD::READ_REGISTER:
371 Res = PromoteIntRes_READ_REGISTER(N);
372 break;
373 }
374
375 // If the result is null then the sub-method took care of registering it.
376 if (Res.getNode())
377 SetPromotedInteger(Op: SDValue(N, ResNo), Result: Res);
378}
379
380SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
381 unsigned ResNo) {
382 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
383 return GetPromotedInteger(Op);
384}
385
386SDValue DAGTypeLegalizer::PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
387 EVT VT = N->getValueType(ResNo: 0);
388 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
389 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: NewVT, Ops: N->ops());
390}
391
392SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
393 // Sign-extend the new bits, and continue the assertion.
394 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
395 return DAG.getNode(Opcode: ISD::AssertSext, DL: SDLoc(N),
396 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
397}
398
399SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
400 // Zero the new bits, and continue the assertion.
401 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
402 return DAG.getNode(Opcode: ISD::AssertZext, DL: SDLoc(N),
403 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
404}
405
406SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
407 EVT ResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
408 ISD::LoadExtType ExtType = N->getExtensionType();
409 if (ExtType == ISD::NON_EXTLOAD) {
410 switch (TLI.getExtendForAtomicOps()) {
411 case ISD::SIGN_EXTEND:
412 ExtType = ISD::SEXTLOAD;
413 break;
414 case ISD::ZERO_EXTEND:
415 ExtType = ISD::ZEXTLOAD;
416 break;
417 case ISD::ANY_EXTEND:
418 ExtType = ISD::EXTLOAD;
419 break;
420 default:
421 llvm_unreachable("Invalid atomic op extension");
422 }
423 }
424
425 SDValue Res =
426 DAG.getAtomicLoad(ExtType, dl: SDLoc(N), MemVT: N->getMemoryVT(), VT: ResVT,
427 Chain: N->getChain(), Ptr: N->getBasePtr(), MMO: N->getMemOperand());
428
429 // Legalize the chain result - switch anything that used the old chain to
430 // use the new one.
431 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
432 return Res;
433}
434
435SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
436 SDValue Op2 = N->getOperand(Num: 2);
437 switch (TLI.getExtendForAtomicRMWArg(Op: N->getOpcode())) {
438 case ISD::SIGN_EXTEND:
439 Op2 = SExtPromotedInteger(Op: Op2);
440 break;
441 case ISD::ZERO_EXTEND:
442 Op2 = ZExtPromotedInteger(Op: Op2);
443 break;
444 case ISD::ANY_EXTEND:
445 Op2 = GetPromotedInteger(Op: Op2);
446 break;
447 default:
448 llvm_unreachable("Invalid atomic op extension");
449 }
450 SDValue Res = DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N),
451 MemVT: N->getMemoryVT(),
452 Chain: N->getChain(), Ptr: N->getBasePtr(),
453 Val: Op2, MMO: N->getMemOperand());
454 // Legalize the chain result - switch anything that used the old chain to
455 // use the new one.
456 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
457 return Res;
458}
459
460SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
461 unsigned ResNo) {
462 if (ResNo == 1) {
463 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
464 EVT SVT = getSetCCResultType(VT: N->getOperand(Num: 2).getValueType());
465 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
466
467 // Only use the result of getSetCCResultType if it is legal,
468 // otherwise just use the promoted result type (NVT).
469 if (!TLI.isTypeLegal(VT: SVT))
470 SVT = NVT;
471
472 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: SVT, VT3: MVT::Other);
473 SDValue Res = DAG.getAtomicCmpSwap(
474 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs,
475 Chain: N->getChain(), Ptr: N->getBasePtr(), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
476 MMO: N->getMemOperand());
477 ReplaceValueWith(From: SDValue(N, 0), To: Res.getValue(R: 0));
478 ReplaceValueWith(From: SDValue(N, 2), To: Res.getValue(R: 2));
479 return DAG.getSExtOrTrunc(Op: Res.getValue(R: 1), DL: SDLoc(N), VT: NVT);
480 }
481
482 // Op2 is used for the comparison and thus must be extended according to the
483 // target's atomic operations. Op3 is merely stored and so can be left alone.
484 SDValue Op2 = N->getOperand(Num: 2);
485 SDValue Op3 = GetPromotedInteger(Op: N->getOperand(Num: 3));
486 switch (TLI.getExtendForAtomicCmpSwapArg()) {
487 case ISD::SIGN_EXTEND:
488 Op2 = SExtPromotedInteger(Op: Op2);
489 break;
490 case ISD::ZERO_EXTEND:
491 Op2 = ZExtPromotedInteger(Op: Op2);
492 break;
493 case ISD::ANY_EXTEND:
494 Op2 = GetPromotedInteger(Op: Op2);
495 break;
496 default:
497 llvm_unreachable("Invalid atomic op extension");
498 }
499
500 SDVTList VTs =
501 DAG.getVTList(VT1: Op2.getValueType(), VT2: N->getValueType(ResNo: 1), VT3: MVT::Other);
502 SDValue Res = DAG.getAtomicCmpSwap(
503 Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs, Chain: N->getChain(),
504 Ptr: N->getBasePtr(), Cmp: Op2, Swp: Op3, MMO: N->getMemOperand());
505 // Update the use to N with the newly created Res.
506 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
507 ReplaceValueWith(From: SDValue(N, i), To: Res.getValue(R: i));
508 return Res;
509}
510
511SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
512 SDValue InOp = N->getOperand(Num: 0);
513 EVT InVT = InOp.getValueType();
514 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
515 EVT OutVT = N->getValueType(ResNo: 0);
516 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
517 SDLoc dl(N);
518
519 switch (getTypeAction(VT: InVT)) {
520 case TargetLowering::TypeLegal:
521 break;
522 case TargetLowering::TypePromoteInteger:
523 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector() && !NInVT.isVector())
524 // The input promotes to the same size. Convert the promoted value.
525 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetPromotedInteger(Op: InOp));
526 break;
527 case TargetLowering::TypeSoftenFloat:
528 // Promote the integer operand by hand.
529 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftenedFloat(Op: InOp));
530 case TargetLowering::TypeSoftPromoteHalf:
531 // Promote the integer operand by hand.
532 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftPromotedHalf(Op: InOp));
533 case TargetLowering::TypeExpandInteger:
534 case TargetLowering::TypeExpandFloat:
535 break;
536 case TargetLowering::TypeScalarizeVector:
537 // Convert the element to an integer and promote it by hand.
538 if (!NOutVT.isVector())
539 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
540 Operand: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)));
541 break;
542 case TargetLowering::TypeScalarizeScalableVector:
543 report_fatal_error(reason: "Scalarization of scalable vectors is not supported.");
544 case TargetLowering::TypeSplitVector: {
545 if (!NOutVT.isVector()) {
546 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
547 // pieces of the input into integers and reassemble in the final type.
548 SDValue Lo, Hi;
549 GetSplitVector(Op: N->getOperand(Num: 0), Lo, Hi);
550 Lo = BitConvertToInteger(Op: Lo);
551 Hi = BitConvertToInteger(Op: Hi);
552
553 if (DAG.getDataLayout().isBigEndian())
554 std::swap(a&: Lo, b&: Hi);
555
556 InOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
557 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
558 BitWidth: NOutVT.getSizeInBits()),
559 Operand: JoinIntegers(Lo, Hi));
560 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: InOp);
561 }
562 break;
563 }
564 case TargetLowering::TypeWidenVector:
565 // The input is widened to the same size. Convert to the widened value.
566 // Make sure that the outgoing value is not a vector, because this would
567 // make us bitcast between two vectors which are legalized in different ways.
568 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector()) {
569 SDValue Res =
570 DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetWidenedVector(Op: InOp));
571
572 // For big endian targets we need to shift the casted value or the
573 // interesting bits will end up at the wrong place.
574 if (DAG.getDataLayout().isBigEndian()) {
575 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
576 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
577 Res = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NOutVT, N1: Res,
578 N2: DAG.getShiftAmountConstant(Val: ShiftAmt, VT: NOutVT, DL: dl));
579 }
580 return Res;
581 }
582 // If the output type is also a vector and widening it to the same size
583 // as the widened input type would be a legal type, we can widen the bitcast
584 // and handle the promotion after.
585 if (NOutVT.isVector()) {
586 TypeSize WidenInSize = NInVT.getSizeInBits();
587 TypeSize OutSize = OutVT.getSizeInBits();
588 if (WidenInSize.hasKnownScalarFactor(RHS: OutSize)) {
589 unsigned Scale = WidenInSize.getKnownScalarFactor(RHS: OutSize);
590 EVT WideOutVT =
591 EVT::getVectorVT(Context&: *DAG.getContext(), VT: OutVT.getVectorElementType(),
592 EC: OutVT.getVectorElementCount() * Scale);
593 if (isTypeLegal(VT: WideOutVT)) {
594 InOp = DAG.getBitcast(VT: WideOutVT, V: GetWidenedVector(Op: InOp));
595 InOp = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: InOp,
596 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
597 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: InOp);
598 }
599 }
600 }
601 }
602
603 // TODO: Handle big endian
604 if (!NOutVT.isVector() && InOp.getValueType().isVector() &&
605 DAG.getDataLayout().isLittleEndian()) {
606 // Pad the vector operand with undef and cast to a wider integer.
607 EVT EltVT = InOp.getValueType().getVectorElementType();
608 TypeSize EltSize = EltVT.getSizeInBits();
609 TypeSize OutSize = NOutVT.getSizeInBits();
610
611 if (OutSize.hasKnownScalarFactor(RHS: EltSize)) {
612 unsigned NumEltsWithPadding = OutSize.getKnownScalarFactor(RHS: EltSize);
613 EVT WideVecVT =
614 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
615
616 if (isTypeLegal(VT: WideVecVT)) {
617 SDValue Inserted = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: WideVecVT,
618 N1: DAG.getUNDEF(VT: WideVecVT), N2: InOp,
619 N3: DAG.getVectorIdxConstant(Val: 0, DL: dl));
620
621 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Inserted);
622 }
623 }
624 }
625
626 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
627 Operand: CreateStackStoreLoad(Op: InOp, DestVT: OutVT));
628}
629
630SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
631 SDValue V = GetPromotedInteger(Op: N->getOperand(Num: 0));
632 return DAG.getNode(Opcode: ISD::FREEZE, DL: SDLoc(N),
633 VT: V.getValueType(), Operand: V);
634}
635
636SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
637 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
638 EVT OVT = N->getValueType(ResNo: 0);
639 EVT NVT = Op.getValueType();
640 SDLoc dl(N);
641
642 // If the larger BSWAP isn't supported by the target, try to expand now.
643 // If we expand later we'll end up with more operations since we lost the
644 // original type. We only do this for scalars since we have a shuffle
645 // based lowering for vectors in LegalizeVectorOps.
646 if (!OVT.isVector() &&
647 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BSWAP, VT: NVT)) {
648 if (SDValue Res = TLI.expandBSWAP(N, DAG))
649 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
650 }
651
652 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
653 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
654 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: NVT, Operand: Op),
655 N2: ShAmt);
656}
657
658SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
659 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
660 EVT OVT = N->getValueType(ResNo: 0);
661 EVT NVT = Op.getValueType();
662 SDLoc dl(N);
663
664 // If the larger BITREVERSE isn't supported by the target, try to expand now.
665 // If we expand later we'll end up with more operations since we lost the
666 // original type. We only do this for scalars since we have a shuffle
667 // based lowering for vectors in LegalizeVectorOps.
668 if (!OVT.isVector() && OVT.isSimple() &&
669 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BITREVERSE, VT: NVT)) {
670 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
671 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
672 }
673
674 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
675 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
676 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT,
677 N1: DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: NVT, Operand: Op), N2: ShAmt);
678}
679
680SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
681 // The pair element type may be legal, or may not promote to the same type as
682 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
683 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N),
684 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
685 VT: N->getValueType(ResNo: 0)), Operand: JoinIntegers(Lo: N->getOperand(Num: 0),
686 Hi: N->getOperand(Num: 1)));
687}
688
689SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
690 EVT VT = N->getValueType(ResNo: 0);
691 // FIXME there is no actual debug info here
692 SDLoc dl(N);
693 // Zero extend things like i1, sign extend everything else. It shouldn't
694 // matter in theory which one we pick, but this tends to give better code?
695 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
696 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl,
697 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT),
698 Operand: SDValue(N, 0));
699 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
700 return Result;
701}
702
703SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
704 EVT OVT = N->getValueType(ResNo: 0);
705 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
706 SDLoc dl(N);
707
708 // If the larger CTLZ isn't supported by the target, try to expand now.
709 // If we expand later we'll end up with more operations since we lost the
710 // original type.
711 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
712 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ, VT: NVT) &&
713 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ_ZERO_POISON, VT: NVT)) {
714 if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
715 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
716 return Result;
717 }
718 }
719
720 unsigned CtlzOpcode = N->getOpcode();
721 if (CtlzOpcode == ISD::CTLZ) {
722 // Subtract off the extra leading bits in the bigger type.
723 SDValue ExtractLeadingBits = DAG.getConstant(
724 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
725 // Zero extend to the promoted type and do the count there.
726 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
727
728 // At this stage SUB is guaranteed to be positive no-wrap,
729 // that to be used in further KnownBits optimizations.
730 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT,
731 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Op),
732 N2: ExtractLeadingBits, Flags: SDNodeFlags::NoUnsignedWrap);
733 }
734 if (CtlzOpcode == ISD::CTLZ_ZERO_POISON) {
735 // Any Extend the argument
736 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
737 // Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
738 unsigned SHLAmount = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
739 auto ShiftConst =
740 DAG.getShiftAmountConstant(Val: SHLAmount, VT: Op.getValueType(), DL: dl);
741 Op = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst);
742 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, Operand: Op);
743 }
744 llvm_unreachable("Invalid CTLZ Opcode");
745}
746
747SDValue DAGTypeLegalizer::PromoteIntRes_CTLS(SDNode *N) {
748 EVT OVT = N->getValueType(ResNo: 0);
749 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
750 SDLoc dl(N);
751
752 SDValue ExtractLeadingBits = DAG.getConstant(
753 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
754
755 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
756 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Op),
757 N2: ExtractLeadingBits);
758}
759
760SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
761 EVT OVT = N->getValueType(ResNo: 0);
762 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
763
764 // If the larger CTPOP isn't supported by the target, try to expand now.
765 // If we expand later we'll end up with more operations since we lost the
766 // original type.
767 // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
768 // TargetLowering.
769 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
770 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTPOP, VT: NVT)) {
771 if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
772 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Result);
773 return Result;
774 }
775 }
776
777 // Zero extend to the promoted type and do the count or parity there.
778 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
779 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), Operand: Op);
780}
781
782SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
783 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
784 EVT OVT = N->getValueType(ResNo: 0);
785 EVT NVT = Op.getValueType();
786 SDLoc dl(N);
787
788 // If the larger CTTZ isn't supported by the target, try to expand now.
789 // If we expand later we'll end up with more operations since we lost the
790 // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
791 // larger type.
792 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
793 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ, VT: NVT) &&
794 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ_ZERO_POISON, VT: NVT) &&
795 !TLI.isOperationLegal(Op: ISD::CTPOP, VT: NVT) &&
796 !TLI.isOperationLegal(Op: ISD::CTLZ, VT: NVT)) {
797 if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
798 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
799 return Result;
800 }
801 }
802
803 unsigned NewOpc = N->getOpcode();
804 if (NewOpc == ISD::CTTZ) {
805 // The count is the same in the promoted type except if the original
806 // value was zero. This can be handled by setting the bit just off
807 // the top of the original type.
808 auto TopBit = APInt::getOneBitSet(numBits: NVT.getScalarSizeInBits(),
809 BitNo: OVT.getScalarSizeInBits());
810 Op = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
811 NewOpc = ISD::CTTZ_ZERO_POISON;
812 }
813 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Op);
814}
815
816SDValue DAGTypeLegalizer::PromoteIntRes_VP_CttzElements(SDNode *N) {
817 SDLoc DL(N);
818 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
819 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NewVT, Ops: N->ops());
820}
821
822SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
823 SDLoc dl(N);
824 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
825
826 SDValue Op0 = N->getOperand(Num: 0);
827 SDValue Op1 = N->getOperand(Num: 1);
828
829 // If the input also needs to be promoted, do that first so we can get a
830 // get a good idea for the output type.
831 if (TLI.getTypeAction(Context&: *DAG.getContext(), VT: Op0.getValueType())
832 == TargetLowering::TypePromoteInteger) {
833 SDValue In = GetPromotedInteger(Op: Op0);
834
835 // If the new type is larger than NVT, use it. We probably won't need to
836 // promote it again.
837 EVT SVT = In.getValueType().getScalarType();
838 if (SVT.bitsGE(VT: NVT)) {
839 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SVT, N1: In, N2: Op1);
840 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NVT);
841 }
842 }
843
844 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NVT, N1: Op0, N2: Op1);
845}
846
847SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
848 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
849 unsigned NewOpc =
850 TLI.getPreferredFPToIntOpcode(Op: N->getOpcode(), FromVT: N->getValueType(ResNo: 0), ToVT: NVT);
851 SDLoc dl(N);
852
853 SDValue Res;
854 if (N->isStrictFPOpcode()) {
855 Res = DAG.getNode(Opcode: NewOpc, DL: dl, ResultTys: {NVT, MVT::Other},
856 Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1)});
857 // Legalize the chain result - switch anything that used the old chain to
858 // use the new one.
859 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
860 } else {
861 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
862 }
863
864 // Assert that the converted value fits in the original type. If it doesn't
865 // (eg: because the value being converted is too big), then the result of the
866 // original operation was undefined anyway, so the assert is still correct.
867 //
868 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
869 // before legalization: fp-to-uint16, 65534. -> 0xfffe
870 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
871 return DAG.getNode(Opcode: (N->getOpcode() == ISD::FP_TO_UINT ||
872 N->getOpcode() == ISD::STRICT_FP_TO_UINT)
873 ? ISD::AssertZext
874 : ISD::AssertSext,
875 DL: dl, VT: NVT, N1: Res,
876 N2: DAG.getValueType(N->getValueType(ResNo: 0).getScalarType()));
877}
878
879SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
880 // Promote the result type, while keeping the original width in Op1.
881 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
882 SDLoc dl(N);
883 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
884 N2: N->getOperand(Num: 1));
885}
886
887SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16_BF16(SDNode *N) {
888 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
889 SDLoc dl(N);
890
891 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
892}
893
894// TODO: CONVERT_TO_ARBITRARY_FP also needs an ExpandIntegerResult handler for
895// wider arbitrary FP formats whose integer result requires expansion.
896SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_TO_ARBITRARY_FP(SDNode *N) {
897 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
898 SDLoc dl(N);
899
900 return DAG.getNode(Opcode: ISD::CONVERT_TO_ARBITRARY_FP, DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
901 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
902}
903
904SDValue DAGTypeLegalizer::PromoteIntRes_STRICT_FP_TO_FP16_BF16(SDNode *N) {
905 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
906 SDLoc dl(N);
907
908 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
909 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
910 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
911 return Res;
912}
913
914SDValue DAGTypeLegalizer::PromoteIntRes_XRINT(SDNode *N) {
915 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
916 SDLoc dl(N);
917 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
918}
919
920SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) {
921 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
922 SDLoc dl(N);
923
924 SDValue Res =
925 DAG.getNode(Opcode: N->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
926
927 // Legalize the chain result - switch anything that used the old chain to
928 // use the new one.
929 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
930 return Res;
931}
932
933SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
934 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
935 SDLoc dl(N);
936
937 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
938 == TargetLowering::TypePromoteInteger) {
939 SDValue Res = GetPromotedInteger(Op: N->getOperand(Num: 0));
940 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
941
942 // If the result and operand types are the same after promotion, simplify
943 // to an in-register extension. Unless this is a VP_*_EXTEND.
944 if (NVT == Res.getValueType() && N->getNumOperands() == 1) {
945 // The high bits are not guaranteed to be anything. Insert an extend.
946 if (N->getOpcode() == ISD::SIGN_EXTEND)
947 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
948 N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
949 if (N->getOpcode() == ISD::ZERO_EXTEND)
950 return DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: N->getOperand(Num: 0).getValueType());
951 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
952 return Res;
953 }
954 }
955
956 // Otherwise, just extend the original operand all the way to the larger type.
957 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
958}
959
960SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
961 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
962 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
963 ISD::LoadExtType ExtType =
964 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
965 SDLoc dl(N);
966 SDValue Res = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
967 MemVT: N->getMemoryVT(), MMO: N->getMemOperand());
968
969 // Legalize the chain result - switch anything that used the old chain to
970 // use the new one.
971 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
972 return Res;
973}
974
975SDValue DAGTypeLegalizer::PromoteIntRes_VP_LOAD(VPLoadSDNode *N) {
976 assert(!N->isIndexed() && "Indexed vp_load during type legalization!");
977 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
978 ISD::LoadExtType ExtType = (N->getExtensionType() == ISD::NON_EXTLOAD)
979 ? ISD::EXTLOAD
980 : N->getExtensionType();
981 SDLoc dl(N);
982 SDValue Res =
983 DAG.getExtLoadVP(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
984 Mask: N->getMask(), EVL: N->getVectorLength(), MemVT: N->getMemoryVT(),
985 MMO: N->getMemOperand(), IsExpanding: N->isExpandingLoad());
986 // Legalize the chain result - switch anything that used the old chain to
987 // use the new one.
988 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
989 return Res;
990}
991
992SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
993 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
994 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
995
996 ISD::LoadExtType ExtType = N->getExtensionType();
997 if (ExtType == ISD::NON_EXTLOAD)
998 ExtType = ISD::EXTLOAD;
999
1000 SDLoc dl(N);
1001 SDValue Res = DAG.getMaskedLoad(VT: NVT, dl, Chain: N->getChain(), Base: N->getBasePtr(),
1002 Offset: N->getOffset(), Mask: N->getMask(), Src0: ExtPassThru,
1003 MemVT: N->getMemoryVT(), MMO: N->getMemOperand(),
1004 AM: N->getAddressingMode(), ExtType,
1005 IsExpanding: N->isExpandingLoad());
1006 // Legalize the chain result - switch anything that used the old chain to
1007 // use the new one.
1008 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1009 return Res;
1010}
1011
1012SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
1013 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1014 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1015 assert(NVT == ExtPassThru.getValueType() &&
1016 "Gather result type and the passThru argument type should be the same");
1017
1018 ISD::LoadExtType ExtType = N->getExtensionType();
1019 if (ExtType == ISD::NON_EXTLOAD)
1020 ExtType = ISD::EXTLOAD;
1021
1022 SDLoc dl(N);
1023 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
1024 N->getIndex(), N->getScale() };
1025 SDValue Res = DAG.getMaskedGather(VTs: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
1026 MemVT: N->getMemoryVT(), dl, Ops,
1027 MMO: N->getMemOperand(), IndexType: N->getIndexType(),
1028 ExtTy: ExtType);
1029 // Legalize the chain result - switch anything that used the old chain to
1030 // use the new one.
1031 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1032 return Res;
1033}
1034
1035SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_COMPRESS(SDNode *N) {
1036 SDValue Vec = GetPromotedInteger(Op: N->getOperand(Num: 0));
1037 SDValue Passthru = GetPromotedInteger(Op: N->getOperand(Num: 2));
1038 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT: Vec.getValueType(), N1: Vec,
1039 N2: N->getOperand(Num: 1), N3: Passthru);
1040}
1041
1042/// Promote the overflow flag of an overflowing arithmetic node.
1043SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
1044 // Change the return type of the boolean result while obeying
1045 // getSetCCResultType.
1046 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1047 EVT VT = N->getValueType(ResNo: 0);
1048 EVT SVT = getSetCCResultType(VT);
1049 SDValue Ops[3] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
1050 unsigned NumOps = N->getNumOperands();
1051 assert(NumOps <= 3 && "Too many operands");
1052 if (NumOps == 3)
1053 Ops[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: VT);
1054
1055 SDLoc dl(N);
1056 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: SVT),
1057 Ops: ArrayRef(Ops, NumOps));
1058
1059 // Modified the sum result - switch anything that used the old sum to use
1060 // the new one.
1061 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1062
1063 // Convert to the expected type.
1064 return DAG.getBoolExtOrTrunc(Op: Res.getValue(R: 1), SL: dl, VT: NVT, OpVT: VT);
1065}
1066
1067SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
1068 // If the promoted type is legal, we can convert this to:
1069 // 1. ANY_EXTEND iN to iM
1070 // 2. SHL by M-N
1071 // 3. [US][ADD|SUB|SHL]SAT
1072 // 4. L/ASHR by M-N
1073 // Else it is more efficient to convert this to a min and a max
1074 // operation in the higher precision arithmetic.
1075 SDLoc dl(N);
1076 SDValue Op1 = N->getOperand(Num: 0);
1077 SDValue Op2 = N->getOperand(Num: 1);
1078
1079 unsigned Opcode = N->getOpcode();
1080 unsigned OldBits = Op1.getScalarValueSizeInBits();
1081
1082 // USUBSAT can always be promoted as long as we have zero/sign-extended the
1083 // args.
1084 if (Opcode == ISD::USUBSAT) {
1085 SExtOrZExtPromotedOperands(LHS&: Op1, RHS&: Op2);
1086 return DAG.getNode(Opcode: ISD::USUBSAT, DL: dl, VT: Op1.getValueType(), N1: Op1, N2: Op2);
1087 }
1088
1089 if (Opcode == ISD::UADDSAT) {
1090 EVT OVT = Op1.getValueType();
1091 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1092 // We can promote if we use sign-extend. Do this if the target prefers.
1093 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT)) {
1094 Op1 = SExtPromotedInteger(Op: Op1);
1095 Op2 = SExtPromotedInteger(Op: Op2);
1096 return DAG.getNode(Opcode: ISD::UADDSAT, DL: dl, VT: NVT, N1: Op1, N2: Op2);
1097 }
1098
1099 Op1 = ZExtPromotedInteger(Op: Op1);
1100 Op2 = ZExtPromotedInteger(Op: Op2);
1101 unsigned NewBits = NVT.getScalarSizeInBits();
1102 APInt MaxVal = APInt::getLowBitsSet(numBits: NewBits, loBitsSet: OldBits);
1103 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: NVT);
1104 SDValue Add = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Op1, N2: Op2);
1105 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT: NVT, N1: Add, N2: SatMax);
1106 }
1107
1108 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
1109
1110 // FIXME: We need vp-aware PromotedInteger functions.
1111 if (IsShift) {
1112 Op1 = GetPromotedInteger(Op: Op1);
1113 if (getTypeAction(VT: Op2.getValueType()) == TargetLowering::TypePromoteInteger)
1114 Op2 = ZExtPromotedInteger(Op: Op2);
1115 } else {
1116 Op1 = SExtPromotedInteger(Op: Op1);
1117 Op2 = SExtPromotedInteger(Op: Op2);
1118 }
1119 EVT PromotedType = Op1.getValueType();
1120 unsigned NewBits = PromotedType.getScalarSizeInBits();
1121
1122 // Shift cannot use a min/max expansion, we can't detect overflow if all of
1123 // the bits have been shifted out.
1124 if (IsShift || TLI.isOperationLegal(Op: Opcode, VT: PromotedType)) {
1125 unsigned ShiftOp;
1126 switch (Opcode) {
1127 case ISD::SADDSAT:
1128 case ISD::SSUBSAT:
1129 case ISD::SSHLSAT:
1130 ShiftOp = ISD::SRA;
1131 break;
1132 case ISD::USHLSAT:
1133 ShiftOp = ISD::SRL;
1134 break;
1135 default:
1136 llvm_unreachable("Expected opcode to be signed or unsigned saturation "
1137 "addition, subtraction or left shift");
1138 }
1139
1140 unsigned SHLAmount = NewBits - OldBits;
1141 SDValue ShiftAmount =
1142 DAG.getShiftAmountConstant(Val: SHLAmount, VT: PromotedType, DL: dl);
1143 Op1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1, N2: ShiftAmount);
1144 if (!IsShift)
1145 Op2 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op2, N2: ShiftAmount);
1146
1147 SDValue Result = DAG.getNode(Opcode, DL: dl, VT: PromotedType, N1: Op1, N2: Op2);
1148 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result, N2: ShiftAmount);
1149 }
1150
1151 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
1152 APInt MinVal = APInt::getSignedMinValue(numBits: OldBits).sext(width: NewBits);
1153 APInt MaxVal = APInt::getSignedMaxValue(numBits: OldBits).sext(width: NewBits);
1154 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT: PromotedType);
1155 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: PromotedType);
1156 SDValue Result = DAG.getNode(Opcode: AddOp, DL: dl, VT: PromotedType, N1: Op1, N2: Op2);
1157 Result = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT: PromotedType, N1: Result, N2: SatMax);
1158 Result = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT: PromotedType, N1: Result, N2: SatMin);
1159 return Result;
1160}
1161
1162SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
1163 // Can just promote the operands then continue with operation.
1164 SDLoc dl(N);
1165 SDValue Op1Promoted, Op2Promoted;
1166 bool Signed =
1167 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
1168 bool Saturating =
1169 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
1170 if (Signed) {
1171 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1172 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1173 } else {
1174 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1175 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1176 }
1177 EVT OldType = N->getOperand(Num: 0).getValueType();
1178 EVT PromotedType = Op1Promoted.getValueType();
1179 unsigned DiffSize =
1180 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
1181
1182 if (Saturating) {
1183 // Promoting the operand and result values changes the saturation width,
1184 // which is extends the values that we clamp to on saturation. This could be
1185 // resolved by shifting one of the operands the same amount, which would
1186 // also shift the result we compare against, then shifting back.
1187 Op1Promoted =
1188 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1189 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1190 SDValue Result = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1191 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1192 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1193 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result,
1194 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1195 }
1196 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted, N2: Op2Promoted,
1197 N3: N->getOperand(Num: 2));
1198}
1199
1200static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
1201 unsigned SatW, bool Signed,
1202 const TargetLowering &TLI,
1203 SelectionDAG &DAG) {
1204 EVT VT = V.getValueType();
1205 unsigned VTW = VT.getScalarSizeInBits();
1206
1207 if (!Signed) {
1208 // Saturate to the unsigned maximum by getting the minimum of V and the
1209 // maximum.
1210 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT, N1: V,
1211 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW),
1212 DL: dl, VT));
1213 }
1214
1215 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
1216 // signed minimum of it and V.
1217 V = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT, N1: V,
1218 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW - 1),
1219 DL: dl, VT));
1220 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
1221 // signed maximum of it and V.
1222 V = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT, N1: V,
1223 N2: DAG.getConstant(Val: APInt::getHighBitsSet(numBits: VTW, hiBitsSet: VTW - SatW + 1),
1224 DL: dl, VT));
1225 return V;
1226}
1227
1228static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
1229 unsigned Scale, const TargetLowering &TLI,
1230 SelectionDAG &DAG, unsigned SatW = 0) {
1231 EVT VT = LHS.getValueType();
1232 unsigned VTSize = VT.getScalarSizeInBits();
1233 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1234 N->getOpcode() == ISD::SDIVFIXSAT;
1235 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1236 N->getOpcode() == ISD::UDIVFIXSAT;
1237
1238 SDLoc dl(N);
1239 // Widen the types by a factor of two. This is guaranteed to expand, since it
1240 // will always have enough high bits in the LHS to shift into.
1241 EVT WideVT = VT.changeElementType(
1242 Context&: *DAG.getContext(), EltVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: VTSize * 2));
1243 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL: dl, VT: WideVT);
1244 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL: dl, VT: WideVT);
1245 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS, RHS, Scale,
1246 DAG);
1247 assert(Res && "Expanding DIVFIX with wide type failed?");
1248 if (Saturating) {
1249 // If the caller has told us to saturate at something less, use that width
1250 // instead of the type before doubling. However, it cannot be more than
1251 // what we just widened!
1252 assert(SatW <= VTSize &&
1253 "Tried to saturate to more than the original type?");
1254 Res = SaturateWidenedDIVFIX(V: Res, dl, SatW: SatW == 0 ? VTSize : SatW, Signed,
1255 TLI, DAG);
1256 }
1257 return DAG.getZExtOrTrunc(Op: Res, DL: dl, VT);
1258}
1259
1260SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1261 SDLoc dl(N);
1262 SDValue Op1Promoted, Op2Promoted;
1263 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1264 N->getOpcode() == ISD::SDIVFIXSAT;
1265 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1266 N->getOpcode() == ISD::UDIVFIXSAT;
1267 if (Signed) {
1268 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1269 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1270 } else {
1271 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1272 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1273 }
1274 EVT PromotedType = Op1Promoted.getValueType();
1275 unsigned Scale = N->getConstantOperandVal(Num: 2);
1276
1277 // If the type is already legal and the operation is legal in that type, we
1278 // should not early expand.
1279 if (TLI.isTypeLegal(VT: PromotedType)) {
1280 TargetLowering::LegalizeAction Action =
1281 TLI.getFixedPointOperationAction(Op: N->getOpcode(), VT: PromotedType, Scale);
1282 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1283 unsigned Diff = PromotedType.getScalarSizeInBits() -
1284 N->getValueType(ResNo: 0).getScalarSizeInBits();
1285 if (Saturating)
1286 Op1Promoted =
1287 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1288 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1289 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1290 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1291 if (Saturating)
1292 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL: dl, VT: PromotedType, N1: Res,
1293 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1294 return Res;
1295 }
1296 }
1297
1298 // See if we can perform the division in this type without expanding.
1299 if (SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: Op1Promoted,
1300 RHS: Op2Promoted, Scale, DAG)) {
1301 if (Saturating)
1302 Res = SaturateWidenedDIVFIX(V: Res, dl,
1303 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits(),
1304 Signed, TLI, DAG);
1305 return Res;
1306 }
1307 // If we cannot, expand it to twice the type width. If we are saturating, give
1308 // it the original width as a saturating width so we don't need to emit
1309 // two saturations.
1310 return earlyExpandDIVFIX(N, LHS: Op1Promoted, RHS: Op2Promoted, Scale, TLI, DAG,
1311 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits());
1312}
1313
1314SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1315 if (ResNo == 1)
1316 return PromoteIntRes_Overflow(N);
1317
1318 // The operation overflowed iff the result in the larger type is not the
1319 // sign extension of its truncation to the original type.
1320 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1321 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1322 EVT OVT = N->getOperand(Num: 0).getValueType();
1323 EVT NVT = LHS.getValueType();
1324 SDLoc dl(N);
1325
1326 // Do the arithmetic in the larger type.
1327 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1328 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1329
1330 // Calculate the overflow flag: sign extend the arithmetic result from
1331 // the original type.
1332 SDValue Ofl = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1333 N2: DAG.getValueType(OVT));
1334 // Overflowed if and only if this is not equal to Res.
1335 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1336
1337 // Use the calculated overflow everywhere.
1338 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1339
1340 return Res;
1341}
1342
1343SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
1344 EVT PromotedResultTy =
1345 TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1346 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: PromotedResultTy,
1347 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
1348}
1349
1350SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1351 SDValue Mask = N->getOperand(Num: 0);
1352
1353 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1354 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1355
1356 unsigned Opcode = N->getOpcode();
1357 if (Opcode == ISD::VP_MERGE)
1358 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS,
1359 N4: N->getOperand(Num: 3));
1360 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS);
1361}
1362
1363SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1364 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1365 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 3));
1366 return DAG.getNode(Opcode: ISD::SELECT_CC, DL: SDLoc(N),
1367 VT: LHS.getValueType(), N1: N->getOperand(Num: 0),
1368 N2: N->getOperand(Num: 1), N3: LHS, N4: RHS, N5: N->getOperand(Num: 4));
1369}
1370
1371SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1372 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1373 EVT InVT = N->getOperand(Num: OpNo).getValueType();
1374 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1375
1376 EVT SVT = getSetCCResultType(VT: InVT);
1377
1378 // If we got back a type that needs to be promoted, this likely means the
1379 // the input type also needs to be promoted. So get the promoted type for
1380 // the input and try the query again.
1381 if (getTypeAction(VT: SVT) == TargetLowering::TypePromoteInteger) {
1382 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
1383 InVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
1384 SVT = getSetCCResultType(VT: InVT);
1385 } else {
1386 // Input type isn't promoted, just use the default promoted type.
1387 SVT = NVT;
1388 }
1389 }
1390
1391 SDLoc dl(N);
1392 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1393 "Vector compare must return a vector result!");
1394
1395 // Get the SETCC result using the canonical SETCC type.
1396 SDValue SetCC;
1397 if (N->isStrictFPOpcode()) {
1398 SDVTList VTs = DAG.getVTList(VTs: {SVT, MVT::Other});
1399 SDValue Opers[] = {N->getOperand(Num: 0), N->getOperand(Num: 1),
1400 N->getOperand(Num: 2), N->getOperand(Num: 3)};
1401 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: VTs, Ops: Opers, Flags: N->getFlags());
1402 // Legalize the chain result - switch anything that used the old chain to
1403 // use the new one.
1404 ReplaceValueWith(From: SDValue(N, 1), To: SetCC.getValue(R: 1));
1405 } else
1406 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: SVT, N1: N->getOperand(Num: 0),
1407 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), Flags: N->getFlags());
1408
1409 // Convert to the expected type.
1410 return DAG.getSExtOrTrunc(Op: SetCC, DL: dl, VT: NVT);
1411}
1412
1413SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
1414 SDLoc DL(N);
1415 SDValue Arg = N->getOperand(Num: 0);
1416 SDValue Test = N->getOperand(Num: 1);
1417 EVT NResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1418 return DAG.getNode(Opcode: ISD::IS_FPCLASS, DL, VT: NResVT, N1: Arg, N2: Test);
1419}
1420
1421SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
1422 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1423 EVT VT = N->getValueType(ResNo: 0);
1424
1425 SDLoc dl(N);
1426 SDValue Res =
1427 DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: NVT), N: N->getOperand(Num: 0));
1428
1429 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1430 return Res.getValue(R: 1);
1431}
1432
1433SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1434 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1435 SDValue RHS = N->getOperand(Num: 1);
1436 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1437 RHS = ZExtPromotedInteger(Op: RHS);
1438 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1439}
1440
1441SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1442 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
1443 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: SDLoc(N),
1444 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
1445}
1446
1447SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1448 // The input may have strange things in the top bits of the registers, but
1449 // these operations don't care. They may have weird bits going out, but
1450 // that too is okay if they are integer operations.
1451 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1452 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1453 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1454}
1455
1456SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1457 // Sign extend the input.
1458 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1459 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1460 if (N->getNumOperands() == 2)
1461 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1462 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1463 assert((N->getOpcode() == ISD::VP_SDIV || N->getOpcode() == ISD::VP_SREM) &&
1464 "Expected VP opcode");
1465 SDValue Mask = N->getOperand(Num: 2);
1466 SDValue EVL = N->getOperand(Num: 3);
1467 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1468 N3: Mask, N4: EVL);
1469}
1470
1471SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1472 // Zero extend the input.
1473 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1474 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1475 if (N->getNumOperands() == 2)
1476 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1477 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1478 assert((N->getOpcode() == ISD::VP_UDIV || N->getOpcode() == ISD::VP_UREM) &&
1479 "Expected VP opcode");
1480 // Zero extend the input.
1481 SDValue Mask = N->getOperand(Num: 2);
1482 SDValue EVL = N->getOperand(Num: 3);
1483 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1484 N3: Mask, N4: EVL);
1485}
1486
1487SDValue DAGTypeLegalizer::PromoteIntRes_ZExtMaskedIntBinOp(SDNode *N) {
1488 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1489 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1490 SDValue Mask = N->getOperand(Num: 2);
1491 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1492 N3: Mask);
1493}
1494
1495SDValue DAGTypeLegalizer::PromoteIntRes_SExtMaskedIntBinOp(SDNode *N) {
1496 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1497 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1498 SDValue Mask = N->getOperand(Num: 2);
1499 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1500 N3: Mask);
1501}
1502
1503SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1504 SDValue LHS = N->getOperand(Num: 0);
1505 SDValue RHS = N->getOperand(Num: 1);
1506
1507 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1508 // whatever is best for the target and the promoted operands.
1509 SExtOrZExtPromotedOperands(LHS, RHS);
1510
1511 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N),
1512 VT: LHS.getValueType(), N1: LHS, N2: RHS);
1513}
1514
1515SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1516 // The input value must be properly sign extended.
1517 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1518 SDValue RHS = N->getOperand(Num: 1);
1519 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1520 RHS = ZExtPromotedInteger(Op: RHS);
1521 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1522}
1523
1524SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1525 SDValue RHS = N->getOperand(Num: 1);
1526 // The input value must be properly zero extended.
1527 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1528 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1529 RHS = ZExtPromotedInteger(Op: RHS);
1530 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1531}
1532
1533SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1534 EVT OldVT = N->getValueType(ResNo: 0);
1535 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1536 SDValue Amt = N->getOperand(Num: 1);
1537 unsigned Opcode = N->getOpcode();
1538 unsigned OldBits = OldVT.getScalarSizeInBits();
1539 unsigned NewBits = VT.getScalarSizeInBits();
1540
1541 // If the promoted type is twice the size (or more), then we can concatenate
1542 // the value with itself and treat this similar to a funnel shift. This isn't
1543 // necessary if the rotate amount is constant or if shl/srl of the original
1544 // type are custom lowered.
1545 // rotl(x,amt) -> (((aext(x) << bw) | zext(x)) << (amt % bw)) >> bw.
1546 // rotr(x,amt) -> (((aext(x) << bw) | zext(x)) >> (amt % bw)).
1547 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1548 !TLI.isOperationLegalOrCustom(Op: Opcode, VT) &&
1549 TLI.getOperationAction(Op: ISD::SHL, VT: OldVT) != TargetLowering::Custom &&
1550 TLI.getOperationAction(Op: ISD::SRL, VT: OldVT) != TargetLowering::Custom) {
1551 SDValue Op0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
1552 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1553 Amt = ZExtPromotedInteger(Op: Amt);
1554 EVT AmtVT = Amt.getValueType();
1555
1556 SDLoc DL(N);
1557 // Amount has to be interpreted modulo the old bit width.
1558 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1559 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1560 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1561 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Op0, N2: HiShift);
1562 SDValue Lo = DAG.getZeroExtendInReg(Op: Op0, DL, VT: OldVT);
1563 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1564 bool IsROTR = N->getOpcode() == ISD::ROTR;
1565 Res = DAG.getNode(Opcode: IsROTR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1566 // FIXME: We can avoid this by using ROTL when the promoted type is exactly
1567 // twice the size.
1568 if (!IsROTR)
1569 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1570 return Res;
1571 }
1572
1573 // Lower the rotate to shifts and ORs which can be promoted.
1574 SDValue Res = TLI.expandROT(N, AllowVectorOps: true /*AllowVectorOps*/, DAG);
1575 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1576 return SDValue();
1577}
1578
1579SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1580 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1581 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1582 SDValue Amt = N->getOperand(Num: 2);
1583 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1584 Amt = ZExtPromotedInteger(Op: Amt);
1585 EVT AmtVT = Amt.getValueType();
1586
1587 SDLoc DL(N);
1588 EVT OldVT = N->getOperand(Num: 0).getValueType();
1589 EVT VT = Lo.getValueType();
1590 unsigned Opcode = N->getOpcode();
1591 bool IsFSHR = Opcode == ISD::FSHR;
1592 unsigned OldBits = OldVT.getScalarSizeInBits();
1593 unsigned NewBits = VT.getScalarSizeInBits();
1594
1595 // Amount has to be interpreted modulo the old bit width.
1596 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1597 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1598
1599 // If the promoted type is twice the size (or more), then we use the
1600 // traditional funnel 'double' shift codegen. This isn't necessary if the
1601 // shift amount is constant.
1602 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1603 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1604 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1605 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1606 SDValue HiShift = DAG.getShiftAmountConstant(Val: OldBits, VT, DL);
1607 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: HiShift);
1608 Lo = DAG.getZeroExtendInReg(Op: Lo, DL, VT: OldVT);
1609 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1610 Res = DAG.getNode(Opcode: IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1611 if (!IsFSHR)
1612 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1613 return Res;
1614 }
1615
1616 // Shift Lo up to occupy the upper bits of the promoted type.
1617 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Lo,
1618 N2: DAG.getShiftAmountConstant(Val: NewBits - OldBits, VT, DL));
1619
1620 // Increase Amount to shift the result into the lower bits of the promoted
1621 // type.
1622 if (IsFSHR)
1623 Amt = DAG.getNode(Opcode: ISD::ADD, DL, VT: AmtVT, N1: Amt,
1624 N2: DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT));
1625
1626 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt);
1627}
1628
1629SDValue DAGTypeLegalizer::PromoteIntRes_CLMUL(SDNode *N) {
1630 unsigned Opcode = N->getOpcode();
1631
1632 SDLoc DL(N);
1633 EVT OldVT = N->getOperand(Num: 0).getValueType();
1634 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
1635
1636 if (Opcode == ISD::CLMUL) {
1637 // Avoid the generic expansion if the cross-product expansion in
1638 // ExpandIntRes_CLMUL would produce a better result.
1639 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CLMUL, VT) &&
1640 !(getTypeAction(VT) == TargetLowering::TypeExpandInteger &&
1641 TLI.isOperationLegalOrCustom(
1642 Op: ISD::CLMUL, VT: TLI.getRegisterType(Context&: *DAG.getContext(), VT)))) {
1643 if (SDValue Res = TLI.expandCLMUL(N, DAG))
1644 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1645 }
1646 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1647 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1648 return DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1649 }
1650
1651 SDValue X = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1652 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1653
1654 unsigned OldBits = OldVT.getScalarSizeInBits();
1655 unsigned NewBits = VT.getScalarSizeInBits();
1656 if (NewBits < 2 * OldBits) {
1657 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1658 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1659 SDValue Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1660 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1661 SDValue Clmulh = DAG.getNode(Opcode: ISD::CLMULH, DL, VT, N1: X, N2: Y);
1662 ShAmt = Opcode == ISD::CLMULH ? NewBits - OldBits : NewBits - OldBits + 1;
1663 SDValue Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Clmulh,
1664 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1665 return DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Lo, N2: Hi);
1666 }
1667
1668 SDValue Clmul = DAG.getNode(Opcode: ISD::CLMUL, DL, VT, N1: X, N2: Y);
1669 unsigned ShAmt = Opcode == ISD::CLMULH ? OldBits : OldBits - 1;
1670 return DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Clmul,
1671 N2: DAG.getShiftAmountConstant(Val: ShAmt, VT, DL));
1672}
1673
1674SDValue DAGTypeLegalizer::PromoteIntRes_PEXT(SDNode *N) {
1675 SDLoc DL(N);
1676 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1677 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::PEXT, VT)) {
1678 if (SDValue Res = TLI.expandPEXT(N, DAG))
1679 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1680 }
1681 // Only the mask operand needs zero-extension because the implicit AND from
1682 // masking clears the corresponding bits in X anyway.
1683 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1684 SDValue Y = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1685 return DAG.getNode(Opcode: ISD::PEXT, DL, VT, N1: X, N2: Y);
1686}
1687
1688SDValue DAGTypeLegalizer::PromoteIntRes_PDEP(SDNode *N) {
1689 SDLoc DL(N);
1690 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1691 if (!TLI.isOperationLegalOrCustomOrPromote(Op: ISD::PDEP, VT)) {
1692 if (SDValue Res = TLI.expandPDEP(N, DAG))
1693 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT, Operand: Res);
1694 }
1695 // Neither operand needs zero-extension because the upper operand bits could
1696 // only result in depositing result bits that will be discarded.
1697 SDValue X = GetPromotedInteger(Op: N->getOperand(Num: 0));
1698 SDValue Y = GetPromotedInteger(Op: N->getOperand(Num: 1));
1699 return DAG.getNode(Opcode: ISD::PDEP, DL, VT, N1: X, N2: Y);
1700}
1701
1702SDValue DAGTypeLegalizer::PromoteIntRes_MULH(SDNode *N) {
1703 SDLoc dl(N);
1704 EVT VT = N->getValueType(ResNo: 0);
1705 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
1706 bool IsSigned = N->getOpcode() == ISD::MULHS;
1707 unsigned BW = VT.getScalarSizeInBits();
1708 unsigned NBW = NVT.getScalarSizeInBits();
1709
1710 SDValue LHS, RHS;
1711 if (IsSigned) {
1712 LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1713 RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1714 } else {
1715 LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1716 RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1717 }
1718
1719 // If the promoted type is already wide enough, emit a MUL.
1720 if (NBW >= 2 * BW)
1721 return DAG.getNode(Opcode: IsSigned ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
1722 N1: DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: NVT, N1: LHS, N2: RHS),
1723 N2: DAG.getShiftAmountConstant(Val: BW, VT: NVT, DL: dl));
1724
1725 // Otherwise, align an operand with a left-shift and emit a MULH.
1726 LHS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: LHS,
1727 N2: DAG.getShiftAmountConstant(Val: NBW - BW, VT: NVT, DL: dl));
1728 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: LHS, N2: RHS);
1729}
1730
1731SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1732 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1733 SDValue Res;
1734 SDValue InOp = N->getOperand(Num: 0);
1735 SDLoc dl(N);
1736
1737 switch (getTypeAction(VT: InOp.getValueType())) {
1738 default: llvm_unreachable("Unknown type action!");
1739 case TargetLowering::TypeLegal:
1740 case TargetLowering::TypeExpandInteger:
1741 Res = InOp;
1742 break;
1743 case TargetLowering::TypePromoteInteger:
1744 Res = GetPromotedInteger(Op: InOp);
1745 break;
1746 case TargetLowering::TypeSplitVector: {
1747 EVT InVT = InOp.getValueType();
1748 assert(InVT.isVector() && "Cannot split scalar types");
1749 ElementCount NumElts = InVT.getVectorElementCount();
1750 assert(NumElts == NVT.getVectorElementCount() &&
1751 "Dst and Src must have the same number of elements");
1752 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1753 "Promoted vector type must be a power of two");
1754
1755 SDValue EOp1, EOp2;
1756 GetSplitVector(Op: InOp, Lo&: EOp1, Hi&: EOp2);
1757
1758 EVT HalfNVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getScalarType(),
1759 EC: NumElts.divideCoefficientBy(RHS: 2));
1760 EOp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp1);
1761 EOp2 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp2);
1762 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl, VT: NVT, N1: EOp1, N2: EOp2);
1763 }
1764 case TargetLowering::TypeWidenVector: {
1765 SDValue WideInOp = GetWidenedVector(Op: InOp);
1766
1767 // Truncate widened InOp.
1768 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1769 EVT TruncVT = EVT::getVectorVT(Context&: *DAG.getContext(),
1770 VT: N->getValueType(ResNo: 0).getScalarType(), NumElements: NumElem);
1771 SDValue WideTrunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: TruncVT, Operand: WideInOp);
1772
1773 // Zero extend so that the elements are of same type as those of NVT
1774 EVT ExtVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getVectorElementType(),
1775 NumElements: NumElem);
1776 SDValue WideExt = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: ExtVT, Operand: WideTrunc);
1777
1778 // Extract the low NVT subvector.
1779 SDValue ZeroIdx = DAG.getVectorIdxConstant(Val: 0, DL: dl);
1780 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NVT, N1: WideExt, N2: ZeroIdx);
1781 }
1782 }
1783
1784 // Truncate to NVT instead of VT
1785 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Res);
1786}
1787
1788SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1789 if (ResNo == 1)
1790 return PromoteIntRes_Overflow(N);
1791
1792 // The operation overflowed iff the result in the larger type is not the
1793 // zero extension of its truncation to the original type.
1794 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1795 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1796 EVT OVT = N->getOperand(Num: 0).getValueType();
1797 EVT NVT = LHS.getValueType();
1798 SDLoc dl(N);
1799
1800 // Do the arithmetic in the larger type.
1801 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1802 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1803
1804 // Calculate the overflow flag: zero extend the arithmetic result from
1805 // the original type.
1806 SDValue Ofl = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: OVT);
1807 // Overflowed if and only if this is not equal to Res.
1808 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1809
1810 // Use the calculated overflow everywhere.
1811 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1812
1813 return Res;
1814}
1815
1816// Handle promotion for the ADDE/SUBE/UADDO_CARRY/USUBO_CARRY nodes. Notice that
1817// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1818// the UADDO_CARRY/USUBO_CARRY nodes in that the third operand is carry Boolean.
1819SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO_CARRY(SDNode *N,
1820 unsigned ResNo) {
1821 if (ResNo == 1)
1822 return PromoteIntRes_Overflow(N);
1823
1824 // We need to sign-extend the operands so the carry value computed by the
1825 // wide operation will be equivalent to the carry value computed by the
1826 // narrow operation.
1827 // An UADDO_CARRY can generate carry only if any of the operands has its
1828 // most significant bit set. Sign extension propagates the most significant
1829 // bit into the higher bits which means the extra bit that the narrow
1830 // addition would need (i.e. the carry) will be propagated through the higher
1831 // bits of the wide addition.
1832 // A USUBO_CARRY can generate borrow only if LHS < RHS and this property will
1833 // be preserved by sign extension.
1834 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1835 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1836
1837 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(ResNo: 1)};
1838
1839 // Do the arithmetic in the wide type.
1840 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VTList: DAG.getVTList(VTs: ValueVTs),
1841 N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
1842
1843 // Update the users of the original carry/borrow value.
1844 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1845
1846 return SDValue(Res.getNode(), 0);
1847}
1848
1849SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1850 unsigned ResNo) {
1851 assert(ResNo == 1 && "Don't know how to promote other results yet.");
1852 return PromoteIntRes_Overflow(N);
1853}
1854
1855SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1856 EVT OVT = N->getValueType(ResNo: 0);
1857 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1858
1859 // If a larger ABS or SMAX isn't supported by the target, try to expand now.
1860 // If we expand later we'll end up sign extending more than just the sra input
1861 // in sra+xor+sub expansion.
1862 if (!OVT.isVector() &&
1863 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS, VT: NVT) &&
1864 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS_MIN_POISON, VT: NVT) &&
1865 !TLI.isOperationLegal(Op: ISD::SMAX, VT: NVT)) {
1866 if (SDValue Res = TLI.expandABS(N, DAG))
1867 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Res);
1868 }
1869
1870 SDValue Op0 = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1871 return DAG.getNode(Opcode: ISD::ABS_MIN_POISON, DL: SDLoc(N), VT: Op0.getValueType(), Operand: Op0);
1872}
1873
1874SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1875 // Promote the overflow bit trivially.
1876 if (ResNo == 1)
1877 return PromoteIntRes_Overflow(N);
1878
1879 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
1880 SDLoc DL(N);
1881 EVT SmallVT = LHS.getValueType();
1882
1883 // To determine if the result overflowed in a larger type, we extend the
1884 // input to the larger type, do the multiply (checking if it overflows),
1885 // then also check the high bits of the result to see if overflow happened
1886 // there.
1887 if (N->getOpcode() == ISD::SMULO) {
1888 LHS = SExtPromotedInteger(Op: LHS);
1889 RHS = SExtPromotedInteger(Op: RHS);
1890 } else {
1891 LHS = ZExtPromotedInteger(Op: LHS);
1892 RHS = ZExtPromotedInteger(Op: RHS);
1893 }
1894 SDVTList VTs = DAG.getVTList(VT1: LHS.getValueType(), VT2: N->getValueType(ResNo: 1));
1895 SDValue Mul = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N1: LHS, N2: RHS);
1896
1897 // Overflow occurred if it occurred in the larger type, or if the high part
1898 // of the result does not zero/sign-extend the low part. Check this second
1899 // possibility first.
1900 SDValue Overflow;
1901 if (N->getOpcode() == ISD::UMULO) {
1902 // Unsigned overflow occurred if the high part is non-zero.
1903 unsigned Shift = SmallVT.getScalarSizeInBits();
1904 SDValue Hi =
1905 DAG.getNode(Opcode: ISD::SRL, DL, VT: Mul.getValueType(), N1: Mul,
1906 N2: DAG.getShiftAmountConstant(Val: Shift, VT: Mul.getValueType(), DL));
1907 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: Hi,
1908 RHS: DAG.getConstant(Val: 0, DL, VT: Hi.getValueType()),
1909 Cond: ISD::SETNE);
1910 } else {
1911 // Signed overflow occurred if the high part does not sign extend the low.
1912 SDValue SExt = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: Mul.getValueType(),
1913 N1: Mul, N2: DAG.getValueType(SmallVT));
1914 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: SExt, RHS: Mul, Cond: ISD::SETNE);
1915 }
1916
1917 // The only other way for overflow to occur is if the multiplication in the
1918 // larger type itself overflowed.
1919 Overflow = DAG.getNode(Opcode: ISD::OR, DL, VT: N->getValueType(ResNo: 1), N1: Overflow,
1920 N2: SDValue(Mul.getNode(), 1));
1921
1922 // Use the calculated overflow everywhere.
1923 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
1924 return Mul;
1925}
1926
1927SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1928 return DAG.getUNDEF(VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
1929 VT: N->getValueType(ResNo: 0)));
1930}
1931
1932SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1933 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1934
1935 const APInt &MulImm = N->getConstantOperandAPInt(Num: 0);
1936 return DAG.getVScale(DL: SDLoc(N), VT, MulImm: MulImm.sext(width: VT.getSizeInBits()));
1937}
1938
1939SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1940 SDValue Chain = N->getOperand(Num: 0); // Get the chain.
1941 SDValue Ptr = N->getOperand(Num: 1); // Get the pointer.
1942 EVT VT = N->getValueType(ResNo: 0);
1943 SDLoc dl(N);
1944
1945 MVT RegVT = TLI.getRegisterType(Context&: *DAG.getContext(), VT);
1946 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
1947 // The argument is passed as NumRegs registers of type RegVT.
1948
1949 SmallVector<SDValue, 8> Parts(NumRegs);
1950 for (unsigned i = 0; i < NumRegs; ++i) {
1951 Parts[i] = DAG.getVAArg(VT: RegVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2),
1952 Align: N->getConstantOperandVal(Num: 3));
1953 Chain = Parts[i].getValue(R: 1);
1954 }
1955
1956 // Handle endianness of the load.
1957 if (DAG.getDataLayout().isBigEndian())
1958 std::reverse(first: Parts.begin(), last: Parts.end());
1959
1960 // Assemble the parts in the promoted type.
1961 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1962 SDValue Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[0]);
1963 for (unsigned i = 1; i < NumRegs; ++i) {
1964 SDValue Part = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[i]);
1965 // Shift it to the right position and "or" it in.
1966 Part = DAG.getNode(
1967 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Part,
1968 N2: DAG.getShiftAmountConstant(Val: i * RegVT.getSizeInBits(), VT: NVT, DL: dl));
1969 Res = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Res, N2: Part);
1970 }
1971
1972 // Modified the chain result - switch anything that used the old chain to
1973 // use the new one.
1974 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
1975
1976 return Res;
1977}
1978
1979//===----------------------------------------------------------------------===//
1980// Integer Operand Promotion
1981//===----------------------------------------------------------------------===//
1982
1983/// PromoteIntegerOperand - This method is called when the specified operand of
1984/// the specified node is found to need promotion. At this point, all of the
1985/// result types of the node are known to be legal, but other operands of the
1986/// node may need promotion or expansion as well as the specified one.
1987bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1988 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG));
1989 SDValue Res = SDValue();
1990 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false)) {
1991 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
1992 return false;
1993 }
1994
1995 switch (N->getOpcode()) {
1996 default:
1997 #ifndef NDEBUG
1998 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1999 N->dump(&DAG); dbgs() << "\n";
2000 #endif
2001 report_fatal_error(reason: "Do not know how to promote this operator's operand!");
2002
2003 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
2004 case ISD::ANY_EXTEND_VECTOR_INREG:
2005 Res = PromoteIntOp_ANY_EXTEND_VECTOR_INREG(N);
2006 break;
2007 case ISD::ATOMIC_STORE:
2008 Res = PromoteIntOp_ATOMIC_STORE(N: cast<AtomicSDNode>(Val: N));
2009 break;
2010 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
2011 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
2012 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
2013 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
2014 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
2015 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
2016 case ISD::COND_LOOP:
2017 Res = PromoteIntOp_COND_LOOP(N, OpNo);
2018 break;
2019 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
2020 case ISD::FAKE_USE:
2021 Res = PromoteIntOp_FAKE_USE(N);
2022 break;
2023 case ISD::INSERT_VECTOR_ELT:
2024 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
2025 break;
2026 case ISD::SPLAT_VECTOR:
2027 case ISD::SCALAR_TO_VECTOR:
2028 Res = PromoteIntOp_ScalarOp(N);
2029 break;
2030 case ISD::VSELECT:
2031 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
2032 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
2033 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
2034 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
2035 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
2036 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
2037 case ISD::STORE: Res = PromoteIntOp_STORE(N: cast<StoreSDNode>(Val: N),
2038 OpNo); break;
2039 case ISD::VP_STORE:
2040 Res = PromoteIntOp_VP_STORE(N: cast<VPStoreSDNode>(Val: N), OpNo);
2041 break;
2042 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(N: cast<MaskedStoreSDNode>(Val: N),
2043 OpNo); break;
2044 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(N: cast<MaskedLoadSDNode>(Val: N),
2045 OpNo); break;
2046 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(N: cast<MaskedGatherSDNode>(Val: N),
2047 OpNo); break;
2048 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(N: cast<MaskedScatterSDNode>(Val: N),
2049 OpNo); break;
2050 case ISD::VECTOR_COMPRESS:
2051 Res = PromoteIntOp_VECTOR_COMPRESS(N, OpNo);
2052 break;
2053 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
2054 case ISD::BF16_TO_FP:
2055 case ISD::FP16_TO_FP:
2056 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
2057 case ISD::CONVERT_FROM_ARBITRARY_FP:
2058 Res = PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(N);
2059 break;
2060 case ISD::STRICT_FP16_TO_FP:
2061 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
2062 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
2063 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
2064 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
2065
2066 case ISD::SHL:
2067 case ISD::SRA:
2068 case ISD::SRL:
2069 case ISD::ROTL:
2070 case ISD::ROTR:
2071 case ISD::SSHLSAT:
2072 case ISD::USHLSAT:
2073 Res = PromoteIntOp_Shift(N);
2074 break;
2075
2076 case ISD::SCMP:
2077 case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
2078
2079 case ISD::FSHL:
2080 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
2081
2082 case ISD::FRAMEADDR:
2083 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
2084
2085 case ISD::SMULFIX:
2086 case ISD::SMULFIXSAT:
2087 case ISD::UMULFIX:
2088 case ISD::UMULFIXSAT:
2089 case ISD::SDIVFIX:
2090 case ISD::SDIVFIXSAT:
2091 case ISD::UDIVFIX:
2092 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
2093 case ISD::FPOWI:
2094 case ISD::STRICT_FPOWI:
2095 case ISD::FLDEXP:
2096 case ISD::STRICT_FLDEXP: Res = PromoteIntOp_ExpOp(N); break;
2097 case ISD::VECREDUCE_ADD:
2098 case ISD::VECREDUCE_MUL:
2099 case ISD::VECREDUCE_AND:
2100 case ISD::VECREDUCE_OR:
2101 case ISD::VECREDUCE_XOR:
2102 case ISD::VECREDUCE_SMAX:
2103 case ISD::VECREDUCE_SMIN:
2104 case ISD::VECREDUCE_UMAX:
2105 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
2106 case ISD::VP_REDUCE_ADD:
2107 case ISD::VP_REDUCE_MUL:
2108 case ISD::VP_REDUCE_AND:
2109 case ISD::VP_REDUCE_OR:
2110 case ISD::VP_REDUCE_XOR:
2111 case ISD::VP_REDUCE_SMAX:
2112 case ISD::VP_REDUCE_SMIN:
2113 case ISD::VP_REDUCE_UMAX:
2114 case ISD::VP_REDUCE_UMIN:
2115 Res = PromoteIntOp_VP_REDUCE(N, OpNo);
2116 break;
2117
2118 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
2119 case ISD::STACKMAP:
2120 Res = PromoteIntOp_STACKMAP(N, OpNo);
2121 break;
2122 case ISD::PATCHPOINT:
2123 Res = PromoteIntOp_PATCHPOINT(N, OpNo);
2124 break;
2125 case ISD::WRITE_REGISTER:
2126 Res = PromoteIntOp_WRITE_REGISTER(N, OpNo);
2127 break;
2128 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
2129 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
2130 Res = PromoteIntOp_VP_STRIDED(N, OpNo);
2131 break;
2132 case ISD::EXPERIMENTAL_VP_SPLICE:
2133 Res = PromoteIntOp_VP_SPLICE(N, OpNo);
2134 break;
2135 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
2136 Res = PromoteIntOp_VECTOR_HISTOGRAM(N, OpNo);
2137 break;
2138 case ISD::VECTOR_FIND_LAST_ACTIVE:
2139 case ISD::CTTZ_ELTS:
2140 case ISD::CTTZ_ELTS_ZERO_POISON:
2141 Res = PromoteIntOp_UnaryBooleanVectorOp(N, OpNo);
2142 break;
2143 case ISD::GET_ACTIVE_LANE_MASK:
2144 Res = PromoteIntOp_GET_ACTIVE_LANE_MASK(N);
2145 break;
2146 case ISD::VECTOR_MATCH:
2147 Res = PromoteIntOp_VECTOR_MATCH(N, OpNo);
2148 break;
2149 case ISD::MASKED_UDIV:
2150 case ISD::MASKED_SDIV:
2151 case ISD::MASKED_UREM:
2152 case ISD::MASKED_SREM:
2153 Res = PromoteIntOp_MaskedBinOp(N, OpNo);
2154 break;
2155 case ISD::PARTIAL_REDUCE_UMLA:
2156 case ISD::PARTIAL_REDUCE_SMLA:
2157 case ISD::PARTIAL_REDUCE_SUMLA:
2158 Res = PromoteIntOp_PARTIAL_REDUCE_MLA(N);
2159 break;
2160 case ISD::LOOP_DEPENDENCE_RAW_MASK:
2161 case ISD::LOOP_DEPENDENCE_WAR_MASK:
2162 Res = PromoteIntOp_LOOP_DEPENDENCE_MASK(N);
2163 break;
2164 }
2165
2166 // If the result is null, the sub-method took care of registering results etc.
2167 if (!Res.getNode()) return false;
2168
2169 // If the result is N, the sub-method updated N in place. Tell the legalizer
2170 // core about this.
2171 if (Res.getNode() == N)
2172 return true;
2173
2174 const bool IsStrictFp = N->isStrictFPOpcode();
2175 assert(Res.getValueType() == N->getValueType(0) &&
2176 N->getNumValues() == (IsStrictFp ? 2 : 1) &&
2177 "Invalid operand expansion");
2178 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
2179 Res.dump());
2180
2181 ReplaceValueWith(From: SDValue(N, 0), To: Res);
2182 if (IsStrictFp)
2183 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res.getNode(), 1));
2184
2185 return false;
2186}
2187
2188// These operands can be either sign extended or zero extended as long as we
2189// treat them the same. If an extension is free, choose that. Otherwise, follow
2190// target preference.
2191void DAGTypeLegalizer::SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS) {
2192 SDValue OpL = GetPromotedInteger(Op: LHS);
2193 SDValue OpR = GetPromotedInteger(Op: RHS);
2194
2195 if (TLI.isSExtCheaperThanZExt(FromTy: LHS.getValueType(), ToTy: OpL.getValueType())) {
2196 // The target would prefer to promote the comparison operand with sign
2197 // extension. Honor that unless the promoted values are already zero
2198 // extended.
2199 unsigned OpLEffectiveBits =
2200 DAG.computeKnownBits(Op: OpL).countMaxActiveBits();
2201 unsigned OpREffectiveBits =
2202 DAG.computeKnownBits(Op: OpR).countMaxActiveBits();
2203 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2204 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2205 LHS = OpL;
2206 RHS = OpR;
2207 return;
2208 }
2209
2210 // The promoted values aren't zero extended, use a sext_inreg.
2211 LHS = SExtPromotedInteger(Op: LHS);
2212 RHS = SExtPromotedInteger(Op: RHS);
2213 return;
2214 }
2215
2216 // Prefer to promote the comparison operand with zero extension.
2217
2218 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
2219 // than the width of LHS/RHS, we can avoid inserting a zext_inreg operation
2220 // that we might not be able to remove.
2221 unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpL);
2222 unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpR);
2223 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2224 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2225 LHS = OpL;
2226 RHS = OpR;
2227 return;
2228 }
2229
2230 // Otherwise, use zext_inreg.
2231 LHS = ZExtPromotedInteger(Op: LHS);
2232 RHS = ZExtPromotedInteger(Op: RHS);
2233}
2234
2235/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
2236/// shared among BR_CC, SELECT_CC, and SETCC handlers.
2237void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
2238 ISD::CondCode CCCode) {
2239 // We have to insert explicit sign or zero extends. Note that we could
2240 // insert sign extends for ALL conditions. For those operations where either
2241 // zero or sign extension would be valid, we ask the target which extension
2242 // it would prefer.
2243
2244 // Signed comparisons always require sign extension.
2245 if (ISD::isSignedIntSetCC(Code: CCCode)) {
2246 LHS = SExtPromotedInteger(Op: LHS);
2247 RHS = SExtPromotedInteger(Op: RHS);
2248 return;
2249 }
2250
2251 assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
2252 "Unknown integer comparison!");
2253
2254 SExtOrZExtPromotedOperands(LHS, RHS);
2255}
2256
2257SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
2258 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2259 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2260}
2261
2262SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND_VECTOR_INREG(SDNode *N) {
2263 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2264 EVT ResVT = N->getValueType(ResNo: 0);
2265 EVT OpVT = Op.getValueType();
2266 EVT NewVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: OpVT.getScalarType(),
2267 NumElements: ResVT.getVectorNumElements());
2268 Op = DAG.getExtractSubvector(DL: SDLoc(Op), VT: NewVT, Vec: Op, Idx: 0);
2269 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: ResVT, Operand: Op);
2270}
2271
2272SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
2273 SDValue Op1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
2274 return DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(),
2275 Chain: N->getChain(), Ptr: Op1, Val: N->getBasePtr(), MMO: N->getMemOperand());
2276}
2277
2278SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
2279 EVT OutVT = N->getValueType(ResNo: 0);
2280 SDValue InOp = N->getOperand(Num: 0);
2281 EVT InVT = InOp.getValueType();
2282 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
2283 SDLoc dl(N);
2284
2285 switch (getTypeAction(VT: InVT)) {
2286 case TargetLowering::TypePromoteInteger: {
2287 // TODO: Handle big endian & vector input type.
2288 if (OutVT.isVector() && !InVT.isVector() &&
2289 DAG.getDataLayout().isLittleEndian()) {
2290 EVT EltVT = OutVT.getVectorElementType();
2291 TypeSize EltSize = EltVT.getSizeInBits();
2292 TypeSize NInSize = NInVT.getSizeInBits();
2293
2294 if (NInSize.hasKnownScalarFactor(RHS: EltSize)) {
2295 unsigned NumEltsWithPadding = NInSize.getKnownScalarFactor(RHS: EltSize);
2296 EVT WideVecVT =
2297 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
2298
2299 if (isTypeLegal(VT: WideVecVT)) {
2300 SDValue Promoted = GetPromotedInteger(Op: InOp);
2301 SDValue Cast = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: WideVecVT, Operand: Promoted);
2302 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Cast,
2303 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
2304 }
2305 }
2306 }
2307
2308 break;
2309 }
2310 default:
2311 break;
2312 }
2313
2314 // This should only occur in unusual situations like bitcasting to an
2315 // x86_fp80, so just turn it into a store+load
2316 return CreateStackStoreLoad(Op: InOp, DestVT: OutVT);
2317}
2318
2319SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
2320 assert(OpNo == 2 && "Don't know how to promote this operand!");
2321
2322 SDValue LHS = N->getOperand(Num: 2);
2323 SDValue RHS = N->getOperand(Num: 3);
2324 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get());
2325
2326 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
2327 // legal types.
2328 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2329 Op2: N->getOperand(Num: 1), Op3: LHS, Op4: RHS, Op5: N->getOperand(Num: 4)),
2330 0);
2331}
2332
2333SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
2334 assert(OpNo == 1 && "only know how to promote condition");
2335
2336 // Promote all the way up to the canonical SetCC type.
2337 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2338
2339 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
2340 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond,
2341 Op3: N->getOperand(Num: 2)), 0);
2342}
2343
2344SDValue DAGTypeLegalizer::PromoteIntOp_COND_LOOP(SDNode *N, unsigned OpNo) {
2345 assert(OpNo == 1 && "only know how to promote condition");
2346
2347 // Promote all the way up to the canonical SetCC type.
2348 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2349
2350 // The chain (Op#0) is always a legal type.
2351 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond), 0);
2352}
2353
2354SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
2355 // Since the result type is legal, the operands must promote to it.
2356 EVT OVT = N->getOperand(Num: 0).getValueType();
2357 SDValue Lo = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2358 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 1));
2359 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
2360 SDLoc dl(N);
2361
2362 Hi = DAG.getNode(
2363 Opcode: ISD::SHL, DL: dl, VT: N->getValueType(ResNo: 0), N1: Hi,
2364 N2: DAG.getShiftAmountConstant(Val: OVT.getSizeInBits(), VT: N->getValueType(ResNo: 0), DL: dl));
2365 return DAG.getNode(Opcode: ISD::OR, DL: dl, VT: N->getValueType(ResNo: 0), N1: Lo, N2: Hi);
2366}
2367
2368SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
2369 // The vector type is legal but the element type is not. This implies
2370 // that the vector is a power-of-two in length and that the element
2371 // type does not have a strange size (eg: it is not i1).
2372 EVT VecVT = N->getValueType(ResNo: 0);
2373 unsigned NumElts = VecVT.getVectorNumElements();
2374 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
2375 "Legal vector of one illegal element?");
2376
2377 // Promote the inserted value. The type does not need to match the
2378 // vector element type. Check that any extra bits introduced will be
2379 // truncated away.
2380 assert(N->getOperand(0).getValueSizeInBits() >=
2381 N->getValueType(0).getScalarSizeInBits() &&
2382 "Type of inserted value narrower than vector element type!");
2383
2384 SmallVector<SDValue, 16> NewOps;
2385 for (unsigned i = 0; i < NumElts; ++i)
2386 NewOps.push_back(Elt: GetPromotedInteger(Op: N->getOperand(Num: i)));
2387
2388 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2389}
2390
2391SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
2392 unsigned OpNo) {
2393 if (OpNo == 1) {
2394 // Promote the inserted value. This is valid because the type does not
2395 // have to match the vector element type.
2396
2397 // Check that any extra bits introduced will be truncated away.
2398 assert(N->getOperand(1).getValueSizeInBits() >=
2399 N->getValueType(0).getScalarSizeInBits() &&
2400 "Type of inserted value narrower than vector element type!");
2401 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2402 Op2: GetPromotedInteger(Op: N->getOperand(Num: 1)),
2403 Op3: N->getOperand(Num: 2)),
2404 0);
2405 }
2406
2407 assert(OpNo == 2 && "Different operand and result vector types?");
2408
2409 // Promote the index.
2410 SDValue Idx = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 2), DL: SDLoc(N),
2411 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
2412 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2413 Op2: N->getOperand(Num: 1), Op3: Idx), 0);
2414}
2415
2416SDValue DAGTypeLegalizer::PromoteIntOp_ScalarOp(SDNode *N) {
2417 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2418
2419 // Integer SPLAT_VECTOR/SCALAR_TO_VECTOR operands are implicitly truncated,
2420 // so just promote the operand in place.
2421 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2422}
2423
2424SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
2425 assert(OpNo == 0 && "Only know how to promote the condition!");
2426 SDValue Cond = N->getOperand(Num: 0);
2427 EVT OpTy = N->getOperand(Num: 1).getValueType();
2428
2429 if (N->getOpcode() == ISD::VSELECT)
2430 if (SDValue Res = WidenVSELECTMask(N))
2431 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
2432 N1: Res, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2433
2434 // Promote all the way up to the canonical SetCC type.
2435 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
2436 Cond = PromoteTargetBoolean(Bool: Cond, ValVT: OpVT);
2437
2438 return SDValue(DAG.UpdateNodeOperands(N, Op1: Cond, Op2: N->getOperand(Num: 1),
2439 Op3: N->getOperand(Num: 2)), 0);
2440}
2441
2442SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
2443 assert(OpNo == 0 && "Don't know how to promote this operand!");
2444
2445 SDValue LHS = N->getOperand(Num: 0);
2446 SDValue RHS = N->getOperand(Num: 1);
2447 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get());
2448
2449 // The CC (#4) and the possible return values (#2 and #3) have legal types.
2450 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2451 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)), 0);
2452}
2453
2454SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
2455 assert(OpNo == 0 && "Don't know how to promote this operand!");
2456
2457 SDValue LHS = N->getOperand(Num: 0);
2458 SDValue RHS = N->getOperand(Num: 1);
2459 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get());
2460
2461 // The CC (#2) is always legal.
2462 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2)), 0);
2463}
2464
2465SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
2466 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2467 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2468}
2469
2470SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
2471 SDValue LHS = N->getOperand(Num: 0);
2472 SDValue RHS = N->getOperand(Num: 1);
2473
2474 if (N->getOpcode() == ISD::SCMP) {
2475 LHS = SExtPromotedInteger(Op: LHS);
2476 RHS = SExtPromotedInteger(Op: RHS);
2477 } else {
2478 SExtOrZExtPromotedOperands(LHS, RHS);
2479 }
2480
2481 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS), 0);
2482}
2483
2484SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
2485 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
2486 Op3: ZExtPromotedInteger(Op: N->getOperand(Num: 2))), 0);
2487}
2488
2489SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
2490 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2491 SDLoc dl(N);
2492 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Op);
2493 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Op.getValueType(),
2494 N1: Op, N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
2495}
2496
2497SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
2498 return SDValue(DAG.UpdateNodeOperands(N,
2499 Op: SExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2500}
2501
2502SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
2503 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2504 Op2: SExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2505}
2506
2507SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
2508 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2509 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
2510 SDLoc dl(N);
2511
2512 SDValue Val = GetPromotedInteger(Op: N->getValue()); // Get promoted value.
2513
2514 // Truncate the value and store the result.
2515 return DAG.getTruncStore(Chain: Ch, dl, Val, Ptr,
2516 SVT: N->getMemoryVT(), MMO: N->getMemOperand());
2517}
2518
2519SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
2520 unsigned OpNo) {
2521
2522 assert(OpNo == 1 && "Unexpected operand for promotion");
2523 assert(!N->isIndexed() && "expecting unindexed vp_store!");
2524
2525 SDValue DataOp = GetPromotedInteger(Op: N->getValue());
2526 return DAG.getTruncStoreVP(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Ptr: N->getBasePtr(),
2527 Mask: N->getMask(), EVL: N->getVectorLength(),
2528 SVT: N->getMemoryVT(), MMO: N->getMemOperand(),
2529 IsCompressing: N->isCompressingStore());
2530}
2531
2532SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
2533 unsigned OpNo) {
2534 SDValue DataOp = N->getValue();
2535 SDValue Mask = N->getMask();
2536
2537 if (OpNo == 4) {
2538 // The Mask. Update in place.
2539 EVT DataVT = DataOp.getValueType();
2540 Mask = PromoteTargetBoolean(Bool: Mask, ValVT: DataVT);
2541 SmallVector<SDValue, 4> NewOps(N->ops());
2542 NewOps[4] = Mask;
2543 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2544 }
2545
2546 assert(OpNo == 1 && "Unexpected operand for promotion");
2547 DataOp = GetPromotedInteger(Op: DataOp);
2548
2549 return DAG.getMaskedStore(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Base: N->getBasePtr(),
2550 Offset: N->getOffset(), Mask, MemVT: N->getMemoryVT(),
2551 MMO: N->getMemOperand(), AM: N->getAddressingMode(),
2552 /*IsTruncating*/ true, IsCompressing: N->isCompressingStore());
2553}
2554
2555SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
2556 unsigned OpNo) {
2557 assert(OpNo == 3 && "Only know how to promote the mask!");
2558 EVT DataVT = N->getValueType(ResNo: 0);
2559 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2560 SmallVector<SDValue, 4> NewOps(N->ops());
2561 NewOps[OpNo] = Mask;
2562 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2563 if (Res == N)
2564 return SDValue(Res, 0);
2565
2566 // Update triggered CSE, do our own replacement since caller can't.
2567 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2568 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2569 return SDValue();
2570}
2571
2572SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
2573 unsigned OpNo) {
2574 SmallVector<SDValue, 5> NewOps(N->ops());
2575
2576 if (OpNo == 2) {
2577 // The Mask
2578 EVT DataVT = N->getValueType(ResNo: 0);
2579 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2580 } else if (OpNo == 4) {
2581 // The Index
2582 if (N->isIndexSigned())
2583 // Need to sign extend the index since the bits will likely be used.
2584 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2585 else
2586 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2587 } else
2588 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2589
2590 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2591 if (Res == N)
2592 return SDValue(Res, 0);
2593
2594 // Update triggered CSE, do our own replacement since caller can't.
2595 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2596 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2597 return SDValue();
2598}
2599
2600SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2601 unsigned OpNo) {
2602 bool TruncateStore = N->isTruncatingStore();
2603 SmallVector<SDValue, 5> NewOps(N->ops());
2604
2605 if (OpNo == 2) {
2606 // The Mask
2607 EVT DataVT = N->getValue().getValueType();
2608 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2609 } else if (OpNo == 4) {
2610 // The Index
2611 if (N->isIndexSigned())
2612 // Need to sign extend the index since the bits will likely be used.
2613 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2614 else
2615 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2616 } else {
2617 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2618 TruncateStore = true;
2619 }
2620
2621 return DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: N->getMemoryVT(),
2622 dl: SDLoc(N), Ops: NewOps, MMO: N->getMemOperand(),
2623 IndexType: N->getIndexType(), IsTruncating: TruncateStore);
2624}
2625
2626SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_COMPRESS(SDNode *N,
2627 unsigned OpNo) {
2628 assert(OpNo == 1 && "Can only promote VECTOR_COMPRESS mask.");
2629 SDValue Vec = N->getOperand(Num: 0);
2630 EVT VT = Vec.getValueType();
2631 SDValue Passthru = N->getOperand(Num: 2);
2632 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: VT);
2633 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT, N1: Vec, N2: Mask, N3: Passthru);
2634}
2635
2636SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2637 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2638 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2639}
2640
2641SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2642 return SDValue(DAG.UpdateNodeOperands(N,
2643 Op: ZExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2644}
2645
2646SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(SDNode *N) {
2647 return SDValue(DAG.UpdateNodeOperands(N, Op1: GetPromotedInteger(Op: N->getOperand(Num: 0)),
2648 Op2: N->getOperand(Num: 1)),
2649 0);
2650}
2651
2652SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2653 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2654 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2655}
2656
2657SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2658 SDLoc dl(N);
2659 SDValue Src = N->getOperand(Num: 0);
2660 SDValue Op = GetPromotedInteger(Op: Src);
2661 EVT VT = N->getValueType(ResNo: 0);
2662
2663 // If this zext has the nneg flag and the target prefers sext, see if the
2664 // promoted input is already sign extended.
2665 // TODO: Should we have some way to set nneg on ISD::AND instead?
2666 if (N->getFlags().hasNonNeg() && Op.getValueType() == VT &&
2667 TLI.isSExtCheaperThanZExt(FromTy: Src.getValueType(), ToTy: VT)) {
2668 unsigned OpEffectiveBits = DAG.ComputeMaxSignificantBits(Op);
2669 if (OpEffectiveBits <= Src.getScalarValueSizeInBits())
2670 return Op;
2671 }
2672
2673 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Op);
2674 return DAG.getZeroExtendInReg(Op, DL: dl, VT: Src.getValueType());
2675}
2676
2677SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2678 SDValue Op2 = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2679 return SDValue(
2680 DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1), Op3: Op2), 0);
2681}
2682
2683SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2684 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2685 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2686 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2687}
2688
2689SDValue DAGTypeLegalizer::PromoteIntOp_ExpOp(SDNode *N) {
2690 bool IsStrict = N->isStrictFPOpcode();
2691 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
2692
2693 bool IsPowI =
2694 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI;
2695 unsigned OpOffset = IsStrict ? 1 : 0;
2696
2697 // The integer operand is the last operand in FPOWI (or FLDEXP) (so the result
2698 // and floating point operand is already type legalized).
2699 RTLIB::Libcall LC = IsPowI ? RTLIB::getPOWI(VT: N->getValueType(ResNo: 0))
2700 : RTLIB::getLDEXP(VT: N->getValueType(ResNo: 0));
2701
2702 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
2703 if (LCImpl == RTLIB::Unsupported) {
2704 // Scalarize vector FPOWI instead of promoting the type. This allows the
2705 // scalar FPOWIs to be visited and converted to libcalls before promoting
2706 // the type.
2707 // FIXME: This should be done in LegalizeVectorOps/LegalizeDAG, but call
2708 // lowering needs the unpromoted EVT.
2709 if (IsPowI && N->getValueType(ResNo: 0).isVector())
2710 return DAG.UnrollVectorOp(N);
2711 SmallVector<SDValue, 3> NewOps(N->ops());
2712 NewOps[1 + OpOffset] = SExtPromotedInteger(Op: N->getOperand(Num: 1 + OpOffset));
2713 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2714 }
2715
2716 // We can't just promote the exponent type in FPOWI, since we want to lower
2717 // the node to a libcall and we if we promote to a type larger than
2718 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2719 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2720 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2721
2722 // A wider-than-int exponent can't be passed in an int (there's no wider
2723 // libcall), so bail like the soften/expand paths. A narrower one is
2724 // sign-extended to int by the makeLibCall below.
2725 if (N->getOperand(Num: 1 + OpOffset).getScalarValueSizeInBits() >
2726 DAG.getLibInfo().getIntSize()) {
2727 const Function &Fn = DAG.getMachineFunction().getFunction();
2728 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
2729 Twine(IsPowI ? "powi" : "ldexp") +
2730 " exponent does not match sizeof(int)",
2731 Fn, N->getDebugLoc()));
2732 if (IsStrict)
2733 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
2734 ReplaceValueWith(From: SDValue(N, 0), To: DAG.getPOISON(VT: N->getValueType(ResNo: 0)));
2735 return SDValue();
2736 }
2737
2738 TargetLowering::MakeLibCallOptions CallOptions;
2739 CallOptions.setIsSigned(true);
2740 SDValue Ops[2] = {N->getOperand(Num: 0 + OpOffset), N->getOperand(Num: 1 + OpOffset)};
2741 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2742 DAG, LibcallImpl: LCImpl, RetVT: N->getValueType(ResNo: 0), Ops, CallOptions, dl: SDLoc(N), Chain);
2743 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
2744 if (IsStrict)
2745 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
2746 return SDValue();
2747}
2748
2749static unsigned getExtendForIntVecReduction(SDNode *N) {
2750 switch (N->getOpcode()) {
2751 default:
2752 llvm_unreachable("Expected integer vector reduction");
2753 case ISD::VECREDUCE_ADD:
2754 case ISD::VECREDUCE_MUL:
2755 case ISD::VECREDUCE_AND:
2756 case ISD::VECREDUCE_OR:
2757 case ISD::VECREDUCE_XOR:
2758 case ISD::VP_REDUCE_ADD:
2759 case ISD::VP_REDUCE_MUL:
2760 case ISD::VP_REDUCE_AND:
2761 case ISD::VP_REDUCE_OR:
2762 case ISD::VP_REDUCE_XOR:
2763 return ISD::ANY_EXTEND;
2764 case ISD::VECREDUCE_SMAX:
2765 case ISD::VECREDUCE_SMIN:
2766 case ISD::VP_REDUCE_SMAX:
2767 case ISD::VP_REDUCE_SMIN:
2768 return ISD::SIGN_EXTEND;
2769 case ISD::VECREDUCE_UMAX:
2770 case ISD::VECREDUCE_UMIN:
2771 case ISD::VP_REDUCE_UMAX:
2772 case ISD::VP_REDUCE_UMIN:
2773 return ISD::ZERO_EXTEND;
2774 }
2775}
2776
2777SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2778 switch (getExtendForIntVecReduction(N)) {
2779 default:
2780 llvm_unreachable("Impossible extension kind for integer reduction");
2781 case ISD::ANY_EXTEND:
2782 return GetPromotedInteger(Op: V);
2783 case ISD::SIGN_EXTEND:
2784 return SExtPromotedInteger(Op: V);
2785 case ISD::ZERO_EXTEND:
2786 return ZExtPromotedInteger(Op: V);
2787 }
2788}
2789
2790SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2791 SDLoc dl(N);
2792 SDValue Op = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
2793
2794 EVT OrigEltVT = N->getOperand(Num: 0).getValueType().getVectorElementType();
2795 EVT InVT = Op.getValueType();
2796 EVT EltVT = InVT.getVectorElementType();
2797 EVT ResVT = N->getValueType(ResNo: 0);
2798 unsigned Opcode = N->getOpcode();
2799
2800 // An i1 vecreduce_xor is equivalent to vecreduce_add, use that instead if
2801 // vecreduce_xor is not legal
2802 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 &&
2803 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_XOR, VT: InVT) &&
2804 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_ADD, VT: InVT))
2805 Opcode = ISD::VECREDUCE_ADD;
2806
2807 // An i1 vecreduce_or is equivalent to vecreduce_umax, use that instead if
2808 // vecreduce_or is not legal
2809 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 &&
2810 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_OR, VT: InVT) &&
2811 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMAX, VT: InVT)) {
2812 Opcode = ISD::VECREDUCE_UMAX;
2813 // Can't use promoteTargetBoolean here because we still need
2814 // to either sign_ext or zero_ext in the undefined case.
2815 switch (TLI.getBooleanContents(Type: InVT)) {
2816 case TargetLoweringBase::UndefinedBooleanContent:
2817 case TargetLoweringBase::ZeroOrOneBooleanContent:
2818 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2819 break;
2820 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2821 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2822 break;
2823 }
2824 }
2825
2826 // An i1 vecreduce_and is equivalent to vecreduce_umin, use that instead if
2827 // vecreduce_and is not legal
2828 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 &&
2829 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_AND, VT: InVT) &&
2830 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMIN, VT: InVT)) {
2831 Opcode = ISD::VECREDUCE_UMIN;
2832 // Can't use promoteTargetBoolean here because we still need
2833 // to either sign_ext or zero_ext in the undefined case.
2834 switch (TLI.getBooleanContents(Type: InVT)) {
2835 case TargetLoweringBase::UndefinedBooleanContent:
2836 case TargetLoweringBase::ZeroOrOneBooleanContent:
2837 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2838 break;
2839 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2840 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2841 break;
2842 }
2843 }
2844
2845 if (ResVT.bitsGE(VT: EltVT))
2846 return DAG.getNode(Opcode, DL: SDLoc(N), VT: ResVT, Operand: Op);
2847
2848 // Result size must be >= element size. If this is not the case after
2849 // promotion, also promote the result type and then truncate.
2850 SDValue Reduce = DAG.getNode(Opcode, DL: dl, VT: EltVT, Operand: Op);
2851 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: ResVT, Operand: Reduce);
2852}
2853
2854SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
2855 SDLoc DL(N);
2856 SDValue Op = N->getOperand(Num: OpNo);
2857 SmallVector<SDValue, 4> NewOps(N->ops());
2858
2859 if (OpNo == 2) { // Mask
2860 // Update in place.
2861 NewOps[2] = PromoteTargetBoolean(Bool: Op, ValVT: N->getOperand(Num: 1).getValueType());
2862 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2863 }
2864
2865 assert(OpNo == 1 && "Unexpected operand for promotion");
2866
2867 Op = PromoteIntOpVectorReduction(N, V: Op);
2868
2869 NewOps[OpNo] = Op;
2870
2871 EVT VT = N->getValueType(ResNo: 0);
2872 EVT EltVT = Op.getValueType().getScalarType();
2873
2874 if (VT.bitsGE(VT: EltVT))
2875 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT, Ops: NewOps);
2876
2877 // Result size must be >= element/start-value size. If this is not the case
2878 // after promotion, also promote both the start value and result type and
2879 // then truncate.
2880 NewOps[0] =
2881 DAG.getNode(Opcode: getExtendForIntVecReduction(N), DL, VT: EltVT, Operand: N->getOperand(Num: 0));
2882 SDValue Reduce = DAG.getNode(Opcode: N->getOpcode(), DL, VT: EltVT, Ops: NewOps);
2883 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT, Operand: Reduce);
2884}
2885
2886SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2887 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2888 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Op), 0);
2889}
2890
2891SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
2892 assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
2893 SmallVector<SDValue> NewOps(N->ops());
2894 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
2895 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2896}
2897
2898SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
2899 assert(OpNo >= 7);
2900 SmallVector<SDValue> NewOps(N->ops());
2901 NewOps[OpNo] = GetPromotedInteger(Op: NewOps[OpNo]);
2902 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2903}
2904
2905SDValue DAGTypeLegalizer::PromoteIntOp_WRITE_REGISTER(SDNode *N,
2906 unsigned OpNo) {
2907 const Function &Fn = DAG.getMachineFunction().getFunction();
2908 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
2909 "cannot use llvm.write_register with illegal type", Fn,
2910 N->getDebugLoc()));
2911 return N->getOperand(Num: 0);
2912}
2913
2914SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
2915 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
2916 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
2917
2918 SmallVector<SDValue, 8> NewOps(N->ops());
2919 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2920 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2921 if (Res == N)
2922 return SDValue(Res, 0);
2923
2924 // Update triggered CSE, do our own replacement since caller can't.
2925 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2926 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2927 return SDValue();
2928}
2929
2930SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
2931 SmallVector<SDValue, 6> NewOps(N->ops());
2932
2933 if (OpNo == 2) { // Offset operand
2934 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2935 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2936 }
2937
2938 assert((OpNo == 4 || OpNo == 5) && "Unexpected operand for promotion");
2939
2940 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2941 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2942}
2943
2944SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_HISTOGRAM(SDNode *N,
2945 unsigned OpNo) {
2946 assert(OpNo == 1 && "Unexpected operand for promotion");
2947 SmallVector<SDValue, 7> NewOps(N->ops());
2948 NewOps[1] = GetPromotedInteger(Op: N->getOperand(Num: 1));
2949 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2950}
2951
2952SDValue DAGTypeLegalizer::PromoteIntOp_UnaryBooleanVectorOp(SDNode *N,
2953 unsigned OpNo) {
2954 assert(OpNo == 0 && "Unexpected operand for promotion");
2955 SDValue Op = N->getOperand(Num: 0);
2956
2957 SDValue NewOp;
2958 if (TLI.getBooleanContents(Type: Op.getValueType()) ==
2959 TargetLowering::ZeroOrNegativeOneBooleanContent)
2960 NewOp = SExtPromotedInteger(Op);
2961 else
2962 NewOp = ZExtPromotedInteger(Op);
2963
2964 return SDValue(DAG.UpdateNodeOperands(N, Op: NewOp), 0);
2965}
2966
2967SDValue DAGTypeLegalizer::PromoteIntOp_GET_ACTIVE_LANE_MASK(SDNode *N) {
2968 SmallVector<SDValue, 1> NewOps(N->ops());
2969 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2970 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2971 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2972}
2973
2974SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_MATCH(SDNode *N, unsigned OpNo) {
2975 assert(OpNo < 3 && "Unexpected operand for promotion");
2976 if (OpNo != 2)
2977 return TLI.expandVectorMatch(N, DAG);
2978
2979 SmallVector<SDValue, 3> NewOps(N->ops());
2980 NewOps[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: N->getValueType(ResNo: 0));
2981 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2982}
2983
2984SDValue DAGTypeLegalizer::PromoteIntOp_MaskedBinOp(SDNode *N, unsigned OpNo) {
2985 assert(OpNo == 2);
2986 SmallVector<SDValue, 3> NewOps(N->ops());
2987 NewOps[2] = PromoteTargetBoolean(Bool: NewOps[2], ValVT: N->getValueType(ResNo: 0));
2988 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2989}
2990
2991SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
2992 SmallVector<SDValue, 1> NewOps(N->ops());
2993 switch (N->getOpcode()) {
2994 case ISD::PARTIAL_REDUCE_SMLA:
2995 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
2996 NewOps[2] = SExtPromotedInteger(Op: N->getOperand(Num: 2));
2997 break;
2998 case ISD::PARTIAL_REDUCE_UMLA:
2999 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3000 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3001 break;
3002 case ISD::PARTIAL_REDUCE_SUMLA:
3003 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
3004 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3005 break;
3006 default:
3007 llvm_unreachable("unexpected opcode");
3008 }
3009 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3010}
3011
3012SDValue DAGTypeLegalizer::PromoteIntOp_LOOP_DEPENDENCE_MASK(SDNode *N) {
3013 SDValue NewOps[4];
3014 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
3015 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
3016 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
3017 NewOps[3] = N->getOperand(Num: 3);
3018 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
3019}
3020
3021//===----------------------------------------------------------------------===//
3022// Integer Result Expansion
3023//===----------------------------------------------------------------------===//
3024
3025/// ExpandIntegerResult - This method is called when the specified result of the
3026/// specified node is found to need expansion. At this point, the node may also
3027/// have invalid operands or may have other results that need promotion, we just
3028/// know that (at least) one result needs expansion.
3029void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
3030 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG));
3031 SDValue Lo, Hi;
3032 Lo = Hi = SDValue();
3033
3034 // See if the target wants to custom expand this node.
3035 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true))
3036 return;
3037
3038 switch (N->getOpcode()) {
3039 default:
3040#ifndef NDEBUG
3041 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
3042 N->dump(&DAG); dbgs() << "\n";
3043#endif
3044 report_fatal_error(reason: "Do not know how to expand the result of this "
3045 "operator!");
3046
3047 case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
3048 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
3049 case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
3050 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
3051 case ISD::POISON:
3052 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
3053 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
3054 case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;
3055
3056 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
3057 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
3058 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
3059 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
3060 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
3061
3062 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
3063 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
3064 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
3065 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
3066 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
3067 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
3068 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
3069 case ISD::ABS:
3070 case ISD::ABS_MIN_POISON:
3071 ExpandIntRes_ABS(N, Lo, Hi);
3072 break;
3073 case ISD::ABDS:
3074 case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
3075 case ISD::CTLZ_ZERO_POISON:
3076 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
3077 case ISD::CTLS: ExpandIntRes_CTLS(N, Lo, Hi); break;
3078 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
3079 case ISD::CTTZ_ZERO_POISON:
3080 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
3081 case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
3082 case ISD::STRICT_FP_TO_SINT:
3083 case ISD::FP_TO_SINT:
3084 case ISD::STRICT_FP_TO_UINT:
3085 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_XINT(N, Lo, Hi); break;
3086 case ISD::FP_TO_SINT_SAT:
3087 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
3088 case ISD::STRICT_LROUND:
3089 case ISD::STRICT_LRINT:
3090 case ISD::LROUND:
3091 case ISD::LRINT:
3092 case ISD::STRICT_LLROUND:
3093 case ISD::STRICT_LLRINT:
3094 case ISD::LLROUND:
3095 case ISD::LLRINT: ExpandIntRes_XROUND_XRINT(N, Lo, Hi); break;
3096 case ISD::LOAD: ExpandIntRes_LOAD(N: cast<LoadSDNode>(Val: N), Lo, Hi); break;
3097 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
3098 case ISD::READCYCLECOUNTER:
3099 case ISD::READSTEADYCOUNTER: ExpandIntRes_READCOUNTER(N, Lo, Hi); break;
3100 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
3101 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
3102 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
3103 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
3104 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
3105 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
3106 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
3107 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
3108 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
3109
3110 case ISD::ATOMIC_LOAD_ADD:
3111 case ISD::ATOMIC_LOAD_SUB:
3112 case ISD::ATOMIC_LOAD_AND:
3113 case ISD::ATOMIC_LOAD_CLR:
3114 case ISD::ATOMIC_LOAD_OR:
3115 case ISD::ATOMIC_LOAD_XOR:
3116 case ISD::ATOMIC_LOAD_NAND:
3117 case ISD::ATOMIC_LOAD_MIN:
3118 case ISD::ATOMIC_LOAD_MAX:
3119 case ISD::ATOMIC_LOAD_UMIN:
3120 case ISD::ATOMIC_LOAD_UMAX:
3121 case ISD::ATOMIC_SWAP:
3122 case ISD::ATOMIC_CMP_SWAP: {
3123 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node: N);
3124 SplitInteger(Op: Tmp.first, Lo, Hi);
3125 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
3126 break;
3127 }
3128 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3129 AtomicSDNode *AN = cast<AtomicSDNode>(Val: N);
3130 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: MVT::Other);
3131 SDValue Tmp = DAG.getAtomicCmpSwap(
3132 Opcode: ISD::ATOMIC_CMP_SWAP, dl: SDLoc(N), MemVT: AN->getMemoryVT(), VTs,
3133 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 1), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
3134 MMO: AN->getMemOperand());
3135
3136 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
3137 // success simply by comparing the loaded value against the ingoing
3138 // comparison.
3139 SDValue Success = DAG.getSetCC(DL: SDLoc(N), VT: N->getValueType(ResNo: 1), LHS: Tmp,
3140 RHS: N->getOperand(Num: 2), Cond: ISD::SETEQ);
3141
3142 SplitInteger(Op: Tmp, Lo, Hi);
3143 ReplaceValueWith(From: SDValue(N, 1), To: Success);
3144 ReplaceValueWith(From: SDValue(N, 2), To: Tmp.getValue(R: 1));
3145 break;
3146 }
3147
3148 case ISD::AND:
3149 case ISD::OR:
3150 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
3151
3152 case ISD::UMAX:
3153 case ISD::SMAX:
3154 case ISD::UMIN:
3155 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
3156
3157 case ISD::SCMP:
3158 case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
3159
3160 case ISD::ADD:
3161 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
3162
3163 case ISD::ADDC:
3164 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
3165
3166 case ISD::ADDE:
3167 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
3168
3169 case ISD::UADDO_CARRY:
3170 case ISD::USUBO_CARRY: ExpandIntRes_UADDSUBO_CARRY(N, Lo, Hi); break;
3171
3172 case ISD::SADDO_CARRY:
3173 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
3174
3175 case ISD::SHL:
3176 case ISD::SRA:
3177 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
3178
3179 case ISD::SADDO:
3180 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
3181 case ISD::UADDO:
3182 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
3183 case ISD::UMULO:
3184 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3185
3186 case ISD::SADDSAT:
3187 case ISD::UADDSAT:
3188 case ISD::SSUBSAT:
3189 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
3190
3191 case ISD::SSHLSAT:
3192 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
3193
3194 case ISD::AVGCEILS:
3195 case ISD::AVGCEILU:
3196 case ISD::AVGFLOORS:
3197 case ISD::AVGFLOORU: ExpandIntRes_AVG(N, Lo, Hi); break;
3198
3199 case ISD::SMULFIX:
3200 case ISD::SMULFIXSAT:
3201 case ISD::UMULFIX:
3202 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
3203
3204 case ISD::SDIVFIX:
3205 case ISD::SDIVFIXSAT:
3206 case ISD::UDIVFIX:
3207 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
3208
3209 case ISD::VECREDUCE_ADD:
3210 case ISD::VECREDUCE_MUL:
3211 case ISD::VECREDUCE_AND:
3212 case ISD::VECREDUCE_OR:
3213 case ISD::VECREDUCE_XOR:
3214 case ISD::VECREDUCE_SMAX:
3215 case ISD::VECREDUCE_SMIN:
3216 case ISD::VECREDUCE_UMAX:
3217 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
3218
3219 case ISD::ROTL:
3220 case ISD::ROTR:
3221 ExpandIntRes_Rotate(N, Lo, Hi);
3222 break;
3223
3224 case ISD::FSHL:
3225 case ISD::FSHR:
3226 ExpandIntRes_FunnelShift(N, Lo, Hi);
3227 break;
3228
3229 case ISD::CLMUL:
3230 case ISD::CLMULR:
3231 case ISD::CLMULH:
3232 ExpandIntRes_CLMUL(N, Lo, Hi);
3233 break;
3234
3235 case ISD::PEXT:
3236 ExpandIntRes_PEXT(N, Lo, Hi);
3237 break;
3238
3239 case ISD::PDEP:
3240 ExpandIntRes_PDEP(N, Lo, Hi);
3241 break;
3242
3243 case ISD::MULHS:
3244 case ISD::MULHU:
3245 ExpandIntRes_MULH(N, Lo, Hi);
3246 break;
3247
3248 case ISD::VSCALE:
3249 ExpandIntRes_VSCALE(N, Lo, Hi);
3250 break;
3251
3252 case ISD::READ_REGISTER:
3253 ExpandIntRes_READ_REGISTER(N, Lo, Hi);
3254 break;
3255
3256 case ISD::CTTZ_ELTS:
3257 case ISD::CTTZ_ELTS_ZERO_POISON:
3258 ExpandIntRes_CTTZ_ELTS(N, Lo, Hi);
3259 break;
3260 }
3261
3262 // If Lo/Hi is null, the sub-method took care of registering results etc.
3263 if (Lo.getNode())
3264 SetExpandedInteger(Op: SDValue(N, ResNo), Lo, Hi);
3265}
3266
3267/// Lower an atomic node to the appropriate builtin call.
3268std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
3269 unsigned Opc = Node->getOpcode();
3270 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
3271 AtomicOrdering order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
3272 // Lower to outline atomic libcall if outline atomics enabled,
3273 // or to sync libcall otherwise
3274 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order: order, VT);
3275 EVT RetVT = Node->getValueType(ResNo: 0);
3276 TargetLowering::MakeLibCallOptions CallOptions;
3277 SmallVector<SDValue, 4> Ops;
3278
3279 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3280 if (LCImpl != RTLIB::Unsupported) {
3281 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
3282 Ops.push_back(Elt: Node->getOperand(Num: 1));
3283 } else {
3284 LC = RTLIB::getSYNC(Opc, VT);
3285 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3286 "Unexpected atomic op or value type!");
3287 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
3288 LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
3289 }
3290 return TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT, Ops, CallOptions, dl: SDLoc(Node),
3291 Chain: Node->getOperand(Num: 0));
3292}
3293
3294/// N is a shift by a value that needs to be expanded,
3295/// and the shift amount is a constant 'Amt'. Expand the operation.
3296void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
3297 SDValue &Lo, SDValue &Hi) {
3298 SDLoc DL(N);
3299 // Expand the incoming operand to be shifted, so that we have its parts
3300 SDValue InL, InH;
3301 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3302
3303 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
3304 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
3305 if (!Amt) {
3306 Lo = InL;
3307 Hi = InH;
3308 return;
3309 }
3310
3311 EVT NVT = InL.getValueType();
3312 unsigned VTBits = N->getValueType(ResNo: 0).getSizeInBits();
3313 unsigned NVTBits = NVT.getSizeInBits();
3314
3315 if (N->getOpcode() == ISD::SHL) {
3316 if (Amt.uge(RHS: VTBits)) {
3317 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3318 } else if (Amt.ugt(RHS: NVTBits)) {
3319 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3320 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3321 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3322 } else if (Amt == NVTBits) {
3323 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3324 Hi = InL;
3325 } else {
3326 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3327 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3328 // Use FSHL if legal so we don't need to combine it later.
3329 if (TLI.isOperationLegal(Op: ISD::FSHL, VT: NVT)) {
3330 Hi = DAG.getNode(Opcode: ISD::FSHL, DL, VT: NVT, N1: InH, N2: InL,
3331 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3332 } else {
3333 Hi = DAG.getNode(
3334 Opcode: ISD::OR, DL, VT: NVT,
3335 N1: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3336 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3337 N2: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3338 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3339 }
3340 }
3341 return;
3342 }
3343
3344 if (N->getOpcode() == ISD::SRL) {
3345 if (Amt.uge(RHS: VTBits)) {
3346 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3347 } else if (Amt.ugt(RHS: NVTBits)) {
3348 Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3349 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3350 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3351 } else if (Amt == NVTBits) {
3352 Lo = InH;
3353 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3354 } else {
3355 // Use FSHR if legal so we don't need to combine it later.
3356 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3357 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3358 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3359 } else {
3360 Lo = DAG.getNode(
3361 Opcode: ISD::OR, DL, VT: NVT,
3362 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3363 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3364 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3365 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3366 }
3367 Hi = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3368 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3369 }
3370 return;
3371 }
3372
3373 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3374 if (Amt.uge(RHS: VTBits)) {
3375 Hi = Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3376 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3377 } else if (Amt.ugt(RHS: NVTBits)) {
3378 Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3379 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3380 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3381 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3382 } else if (Amt == NVTBits) {
3383 Lo = InH;
3384 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3385 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3386 } else {
3387 // Use FSHR if legal so we don't need to combine it later.
3388 if (TLI.isOperationLegal(Op: ISD::FSHR, VT: NVT)) {
3389 Lo = DAG.getNode(Opcode: ISD::FSHR, DL, VT: NVT, N1: InH, N2: InL,
3390 N3: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3391 } else {
3392 Lo = DAG.getNode(
3393 Opcode: ISD::OR, DL, VT: NVT,
3394 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3395 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3396 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3397 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3398 }
3399 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3400 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3401 }
3402}
3403
3404/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
3405/// this shift based on knowledge of the high bit of the shift amount. If we
3406/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
3407/// shift amount.
3408bool DAGTypeLegalizer::
3409ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3410 unsigned Opc = N->getOpcode();
3411 SDValue In = N->getOperand(Num: 0);
3412 SDValue Amt = N->getOperand(Num: 1);
3413 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3414 EVT ShTy = Amt.getValueType();
3415 unsigned ShBits = ShTy.getScalarSizeInBits();
3416 unsigned NVTBits = NVT.getScalarSizeInBits();
3417 assert(isPowerOf2_32(NVTBits) &&
3418 "Expanded integer type size not a power of two!");
3419 SDLoc dl(N);
3420
3421 APInt HighBitMask = APInt::getHighBitsSet(numBits: ShBits, hiBitsSet: ShBits - Log2_32(Value: NVTBits));
3422 KnownBits Known = DAG.computeKnownBits(Op: Amt);
3423
3424 // If we don't know anything about the high bits, exit.
3425 if (((Known.Zero | Known.One) & HighBitMask) == 0)
3426 return false;
3427
3428 // Get the incoming operand to be shifted.
3429 SDValue InL, InH;
3430 GetExpandedInteger(Op: In, Lo&: InL, Hi&: InH);
3431
3432 // If we know that any of the high bits of the shift amount are one, then we
3433 // can do this as a couple of simple shifts.
3434 if (Known.One.intersects(RHS: HighBitMask)) {
3435 // Mask out the high bit, which we know is set.
3436 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShTy, N1: Amt,
3437 N2: DAG.getConstant(Val: ~HighBitMask, DL: dl, VT: ShTy));
3438
3439 switch (Opc) {
3440 default: llvm_unreachable("Unknown shift");
3441 case ISD::SHL:
3442 Lo = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Low part is zero.
3443 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt); // High part from Lo part.
3444 return true;
3445 case ISD::SRL:
3446 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3447 Lo = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3448 return true;
3449 case ISD::SRA:
3450 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign extend high part.
3451 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3452 Lo = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3453 return true;
3454 }
3455 }
3456
3457 // If we know that all of the high bits of the shift amount are zero, then we
3458 // can do this as a couple of simple shifts.
3459 if (HighBitMask.isSubsetOf(RHS: Known.Zero)) {
3460 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
3461 // shift if x is zero. We can use XOR here because x is known to be smaller
3462 // than 32.
3463 SDValue Amt2 = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: ShTy, N1: Amt,
3464 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3465
3466 unsigned Op1, Op2;
3467 switch (Opc) {
3468 default: llvm_unreachable("Unknown shift");
3469 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
3470 case ISD::SRL:
3471 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
3472 }
3473
3474 // When shifting right the arithmetic for Lo and Hi is swapped.
3475 if (Opc != ISD::SHL)
3476 std::swap(a&: InL, b&: InH);
3477
3478 // Use a little trick to get the bits that move from Lo to Hi. First
3479 // shift by one bit.
3480 SDValue Sh1 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: InL, N2: DAG.getConstant(Val: 1, DL: dl, VT: ShTy));
3481 // Then compute the remaining shift with amount-1.
3482 SDValue Sh2 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: Sh1, N2: Amt2);
3483
3484 Lo = DAG.getNode(Opcode: Opc, DL: dl, VT: NVT, N1: InL, N2: Amt);
3485 Hi = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: Op1, DL: dl, VT: NVT, N1: InH, N2: Amt),N2: Sh2);
3486
3487 if (Opc != ISD::SHL)
3488 std::swap(a&: Hi, b&: Lo);
3489 return true;
3490 }
3491
3492 return false;
3493}
3494
3495/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
3496/// of any size.
3497bool DAGTypeLegalizer::
3498ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3499 SDValue Amt = N->getOperand(Num: 1);
3500 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3501 EVT ShTy = Amt.getValueType();
3502 unsigned NVTBits = NVT.getSizeInBits();
3503 assert(isPowerOf2_32(NVTBits) &&
3504 "Expanded integer type size not a power of two!");
3505 SDLoc dl(N);
3506
3507 // Get the incoming operand to be shifted.
3508 SDValue InL, InH;
3509 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3510
3511 SDValue NVBitsNode = DAG.getConstant(Val: NVTBits, DL: dl, VT: ShTy);
3512 SDValue AmtExcess = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: Amt, N2: NVBitsNode);
3513 SDValue AmtLack = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: NVBitsNode, N2: Amt);
3514 SDValue isShort = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3515 LHS: Amt, RHS: NVBitsNode, Cond: ISD::SETULT);
3516 SDValue isZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3517 LHS: Amt, RHS: DAG.getConstant(Val: 0, DL: dl, VT: ShTy),
3518 Cond: ISD::SETEQ);
3519
3520 SDValue LoS, HiS, LoL, HiL;
3521 switch (N->getOpcode()) {
3522 default: llvm_unreachable("Unknown shift");
3523 case ISD::SHL:
3524 // Short: ShAmt < NVTBits
3525 LoS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt);
3526 HiS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3527 N1: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: Amt),
3528 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: AmtLack));
3529
3530 // Long: ShAmt >= NVTBits
3531 LoL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Lo part is zero.
3532 HiL = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: AmtExcess); // Hi from Lo part.
3533
3534 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL);
3535 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InH,
3536 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL));
3537 return true;
3538 case ISD::SRL:
3539 // Short: ShAmt < NVTBits
3540 HiS = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt);
3541 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3542 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3543 // FIXME: If Amt is zero, the following shift generates an undefined result
3544 // on some architectures.
3545 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3546
3547 // Long: ShAmt >= NVTBits
3548 HiL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3549 LoL = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3550
3551 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3552 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3553 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3554 return true;
3555 case ISD::SRA:
3556 // Short: ShAmt < NVTBits
3557 HiS = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt);
3558 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3559 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3560 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3561
3562 // Long: ShAmt >= NVTBits
3563 HiL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign of Hi part.
3564 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3565 LoL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3566
3567 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3568 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3569 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3570 return true;
3571 }
3572}
3573
3574static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
3575
3576 switch (Op) {
3577 default: llvm_unreachable("invalid min/max opcode");
3578 case ISD::SMAX:
3579 return std::make_pair(x: ISD::SETGT, y: ISD::UMAX);
3580 case ISD::UMAX:
3581 return std::make_pair(x: ISD::SETUGT, y: ISD::UMAX);
3582 case ISD::SMIN:
3583 return std::make_pair(x: ISD::SETLT, y: ISD::UMIN);
3584 case ISD::UMIN:
3585 return std::make_pair(x: ISD::SETULT, y: ISD::UMIN);
3586 }
3587}
3588
3589void DAGTypeLegalizer::ExpandIntRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
3590 SDLoc DL(N);
3591
3592 SDValue LHS = N->getOperand(Num: 0);
3593 SDValue RHS = N->getOperand(Num: 1);
3594 EVT NewVT = getSetCCResultType(VT: LHS.getValueType());
3595
3596 // Taking the same approach as ScalarizeVecRes_SETCC
3597 SDValue Res = DAG.getNode(Opcode: ISD::SETCC, DL, VT: NewVT, N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
3598
3599 Res = DAG.getBoolExtOrTrunc(Op: Res, SL: DL, VT: N->getValueType(ResNo: 0), OpVT: NewVT);
3600 SplitInteger(Op: Res, Lo, Hi);
3601}
3602
3603void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
3604 SDValue &Lo, SDValue &Hi) {
3605 SDLoc DL(N);
3606
3607 SDValue LHS = N->getOperand(Num: 0);
3608 SDValue RHS = N->getOperand(Num: 1);
3609
3610 // If the upper halves are all sign bits, then we can perform the MINMAX on
3611 // the lower half and sign-extend the result to the upper half.
3612 unsigned NumBits = N->getValueType(ResNo: 0).getScalarSizeInBits();
3613 unsigned NumHalfBits = NumBits / 2;
3614 if (DAG.ComputeNumSignBits(Op: LHS) > NumHalfBits &&
3615 DAG.ComputeNumSignBits(Op: RHS) > NumHalfBits) {
3616 SDValue LHSL, LHSH, RHSL, RHSH;
3617 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3618 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3619 EVT NVT = LHSL.getValueType();
3620
3621 Lo = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: LHSL, N2: RHSL);
3622 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: Lo,
3623 N2: DAG.getShiftAmountConstant(Val: NumHalfBits - 1, VT: NVT, DL));
3624 return;
3625 }
3626
3627 // The Lo of smin(X, -1) is LHSL if X is negative. Otherwise it's -1.
3628 // The Lo of smax(X, 0) is 0 if X is negative. Otherwise it's LHSL.
3629 if ((N->getOpcode() == ISD::SMAX && isNullConstant(V: RHS)) ||
3630 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(V: RHS))) {
3631 SDValue LHSL, LHSH, RHSL, RHSH;
3632 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3633 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3634 EVT NVT = LHSL.getValueType();
3635 EVT CCT = getSetCCResultType(VT: NVT);
3636
3637 SDValue HiNeg =
3638 DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: DAG.getConstant(Val: 0, DL, VT: NVT), Cond: ISD::SETLT);
3639 if (N->getOpcode() == ISD::SMIN) {
3640 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: LHSL, RHS: DAG.getAllOnesConstant(DL, VT: NVT));
3641 } else {
3642 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: DAG.getConstant(Val: 0, DL, VT: NVT), RHS: LHSL);
3643 }
3644 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3645 return;
3646 }
3647
3648 const APInt *RHSVal = nullptr;
3649 if (auto *RHSConst = dyn_cast<ConstantSDNode>(Val&: RHS))
3650 RHSVal = &RHSConst->getAPIntValue();
3651
3652 // The high half of MIN/MAX is always just the the MIN/MAX of the
3653 // high halves of the operands. Expand this way if it appears profitable.
3654 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) &&
3655 (RHSVal->countLeadingOnes() >= NumHalfBits ||
3656 RHSVal->countLeadingZeros() >= NumHalfBits)) {
3657 SDValue LHSL, LHSH, RHSL, RHSH;
3658 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3659 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3660 EVT NVT = LHSL.getValueType();
3661 EVT CCT = getSetCCResultType(VT: NVT);
3662
3663 ISD::NodeType LoOpc;
3664 ISD::CondCode CondC;
3665 std::tie(args&: CondC, args&: LoOpc) = getExpandedMinMaxOps(Op: N->getOpcode());
3666
3667 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3668 // We need to know whether to select Lo part that corresponds to 'winning'
3669 // Hi part or if Hi parts are equal.
3670 SDValue IsHiLeft = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: CondC);
3671 SDValue IsHiEq = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: ISD::SETEQ);
3672
3673 // Lo part corresponding to the 'winning' Hi part
3674 SDValue LoCmp = DAG.getSelect(DL, VT: NVT, Cond: IsHiLeft, LHS: LHSL, RHS: RHSL);
3675
3676 // Recursed Lo part if Hi parts are equal, this uses unsigned version
3677 SDValue LoMinMax = DAG.getNode(Opcode: LoOpc, DL, VT: NVT, Ops: {LHSL, RHSL});
3678
3679 Lo = DAG.getSelect(DL, VT: NVT, Cond: IsHiEq, LHS: LoMinMax, RHS: LoCmp);
3680 return;
3681 }
3682
3683 // Expand to "a < b ? a : b" etc. Prefer ge/le if that simplifies
3684 // the compare.
3685 ISD::CondCode Pred;
3686 switch (N->getOpcode()) {
3687 default: llvm_unreachable("How did we get here?");
3688 case ISD::SMAX:
3689 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3690 Pred = ISD::SETGE;
3691 else
3692 Pred = ISD::SETGT;
3693 break;
3694 case ISD::SMIN:
3695 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3696 Pred = ISD::SETLE;
3697 else
3698 Pred = ISD::SETLT;
3699 break;
3700 case ISD::UMAX:
3701 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3702 Pred = ISD::SETUGE;
3703 else
3704 Pred = ISD::SETUGT;
3705 break;
3706 case ISD::UMIN:
3707 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3708 Pred = ISD::SETULE;
3709 else
3710 Pred = ISD::SETULT;
3711 break;
3712 }
3713 EVT VT = N->getValueType(ResNo: 0);
3714 EVT CCT = getSetCCResultType(VT);
3715 SDValue Cond = DAG.getSetCC(DL, VT: CCT, LHS, RHS, Cond: Pred);
3716 SDValue Result = DAG.getSelect(DL, VT, Cond, LHS, RHS);
3717 SplitInteger(Op: Result, Lo, Hi);
3718}
3719
3720void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
3721 SDValue ExpandedCMP = TLI.expandCMP(Node: N, DAG);
3722 SplitInteger(Op: ExpandedCMP, Lo, Hi);
3723}
3724
3725void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
3726 SDValue &Lo, SDValue &Hi) {
3727 SDLoc dl(N);
3728 // Expand the subcomponents.
3729 SDValue LHSL, LHSH, RHSL, RHSH;
3730 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3731 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3732
3733 EVT NVT = LHSL.getValueType();
3734 SDValue LoOps[2] = { LHSL, RHSL };
3735 SDValue HiOps[3] = { LHSH, RHSH };
3736
3737 bool HasOpCarry = TLI.isOperationLegalOrCustom(
3738 Op: N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
3739 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3740 if (HasOpCarry) {
3741 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
3742 if (N->getOpcode() == ISD::ADD) {
3743 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3744 HiOps[2] = Lo.getValue(R: 1);
3745 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3746 ? DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3747 : DAG.getNode(Opcode: ISD::UADDO_CARRY, DL: dl, VTList, Ops: HiOps);
3748 } else {
3749 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3750 HiOps[2] = Lo.getValue(R: 1);
3751 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3752 ? DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3753 : DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, Ops: HiOps);
3754 }
3755 return;
3756 }
3757
3758 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
3759 // them. TODO: Teach operation legalization how to expand unsupported
3760 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
3761 // a carry of type MVT::Glue, but there doesn't seem to be any way to
3762 // generate a value of this type in the expanded code sequence.
3763 bool hasCarry =
3764 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3765 ISD::ADDC : ISD::SUBC,
3766 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3767
3768 if (hasCarry) {
3769 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: MVT::Glue);
3770 if (N->getOpcode() == ISD::ADD) {
3771 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3772 HiOps[2] = Lo.getValue(R: 1);
3773 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3774 } else {
3775 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3776 HiOps[2] = Lo.getValue(R: 1);
3777 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3778 }
3779 return;
3780 }
3781
3782 bool hasOVF =
3783 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3784 ISD::UADDO : ISD::USUBO,
3785 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3786 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(Type: NVT);
3787
3788 if (hasOVF) {
3789 EVT OvfVT = getSetCCResultType(VT: NVT);
3790 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: OvfVT);
3791 int RevOpc;
3792 if (N->getOpcode() == ISD::ADD) {
3793 RevOpc = ISD::SUB;
3794 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3795 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3796 } else {
3797 RevOpc = ISD::ADD;
3798 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3799 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3800 }
3801 SDValue OVF = Lo.getValue(R: 1);
3802
3803 switch (BoolType) {
3804 case TargetLoweringBase::UndefinedBooleanContent:
3805 OVF = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: OvfVT, N1: DAG.getConstant(Val: 1, DL: dl, VT: OvfVT), N2: OVF);
3806 [[fallthrough]];
3807 case TargetLoweringBase::ZeroOrOneBooleanContent:
3808 OVF = DAG.getZExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3809 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Hi, N2: OVF);
3810 break;
3811 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3812 OVF = DAG.getSExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3813 Hi = DAG.getNode(Opcode: RevOpc, DL: dl, VT: NVT, N1: Hi, N2: OVF);
3814 }
3815 return;
3816 }
3817
3818 if (N->getOpcode() == ISD::ADD) {
3819 Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: LoOps);
3820 SDValue Cmp;
3821 // Special case: X+1 has a carry out if X+1==0. This may reduce the live
3822 // range of X. We assume comparing with 0 is cheap.
3823 if (isOneConstant(V: LoOps[1]))
3824 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
3825 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3826 else if (isAllOnesConstant(V: LoOps[1])) {
3827 if (isAllOnesConstant(V: HiOps[1]))
3828 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3829 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3830 else
3831 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3832 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
3833 } else
3834 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo, RHS: LoOps[0],
3835 Cond: ISD::SETULT);
3836
3837 SDValue Carry;
3838 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3839 Carry = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3840 else
3841 Carry = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3842 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3843
3844 if (isAllOnesConstant(V: LoOps[1]) && isAllOnesConstant(V: HiOps[1])) {
3845 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: HiOps[0], N2: Carry);
3846 } else {
3847 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3848 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Hi, N2: Carry);
3849 }
3850 } else {
3851 Lo = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: LoOps);
3852 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3853 SDValue Cmp =
3854 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LoOps[0].getValueType()),
3855 LHS: LoOps[0], RHS: LoOps[1], Cond: ISD::SETULT);
3856
3857 SDValue Borrow;
3858 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3859 Borrow = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3860 else
3861 Borrow = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3862 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3863
3864 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Hi, N2: Borrow);
3865 }
3866}
3867
3868void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
3869 SDValue &Lo, SDValue &Hi) {
3870 // Expand the subcomponents.
3871 SDValue LHSL, LHSH, RHSL, RHSH;
3872 SDLoc dl(N);
3873 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3874 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3875 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3876 SDValue LoOps[2] = { LHSL, RHSL };
3877 SDValue HiOps[3] = { LHSH, RHSH };
3878
3879 if (N->getOpcode() == ISD::ADDC) {
3880 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3881 HiOps[2] = Lo.getValue(R: 1);
3882 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3883 } else {
3884 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3885 HiOps[2] = Lo.getValue(R: 1);
3886 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3887 }
3888
3889 // Legalized the flag result - switch anything that used the old flag to
3890 // use the new one.
3891 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3892}
3893
3894void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
3895 SDValue &Lo, SDValue &Hi) {
3896 // Expand the subcomponents.
3897 SDValue LHSL, LHSH, RHSL, RHSH;
3898 SDLoc dl(N);
3899 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3900 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3901 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3902 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3903 SDValue HiOps[3] = { LHSH, RHSH };
3904
3905 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3906 HiOps[2] = Lo.getValue(R: 1);
3907 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
3908
3909 // Legalized the flag result - switch anything that used the old flag to
3910 // use the new one.
3911 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3912}
3913
3914void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
3915 SDValue &Lo, SDValue &Hi) {
3916 SDValue LHS = N->getOperand(Num: 0);
3917 SDValue RHS = N->getOperand(Num: 1);
3918 SDLoc dl(N);
3919
3920 SDValue Ovf;
3921
3922 unsigned CarryOp, NoCarryOp;
3923 ISD::CondCode Cond;
3924 switch(N->getOpcode()) {
3925 case ISD::UADDO:
3926 CarryOp = ISD::UADDO_CARRY;
3927 NoCarryOp = ISD::ADD;
3928 Cond = ISD::SETULT;
3929 break;
3930 case ISD::USUBO:
3931 CarryOp = ISD::USUBO_CARRY;
3932 NoCarryOp = ISD::SUB;
3933 Cond = ISD::SETUGT;
3934 break;
3935 default:
3936 llvm_unreachable("Node has unexpected Opcode");
3937 }
3938
3939 bool HasCarryOp = TLI.isOperationLegalOrCustom(
3940 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
3941
3942 if (HasCarryOp) {
3943 // Expand the subcomponents.
3944 SDValue LHSL, LHSH, RHSL, RHSH;
3945 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3946 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3947 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3948 SDValue LoOps[2] = { LHSL, RHSL };
3949 SDValue HiOps[3] = { LHSH, RHSH };
3950
3951 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3952 HiOps[2] = Lo.getValue(R: 1);
3953 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: HiOps);
3954
3955 Ovf = Hi.getValue(R: 1);
3956 } else {
3957 // Expand the result by simply replacing it with the equivalent
3958 // non-overflow-checking operation.
3959 SDValue Sum = DAG.getNode(Opcode: NoCarryOp, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS);
3960 SplitInteger(Op: Sum, Lo, Hi);
3961
3962 if (N->getOpcode() == ISD::UADDO && isOneConstant(V: RHS)) {
3963 // Special case: uaddo X, 1 overflowed if X+1 == 0. We can detect this
3964 // with (Lo | Hi) == 0.
3965 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Lo.getValueType(), N1: Lo, N2: Hi);
3966 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Or,
3967 RHS: DAG.getConstant(Val: 0, DL: dl, VT: Lo.getValueType()), Cond: ISD::SETEQ);
3968 } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(V: RHS)) {
3969 // Special case: uaddo X, -1 overflows if X == 0.
3970 Ovf =
3971 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS,
3972 RHS: DAG.getConstant(Val: 0, DL: dl, VT: LHS.getValueType()), Cond: ISD::SETNE);
3973 } else {
3974 // Calculate the overflow: addition overflows iff a + b < a, and
3975 // subtraction overflows iff a - b > a.
3976 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Sum, RHS: LHS, Cond);
3977 }
3978 }
3979
3980 // Legalized the flag result - switch anything that used the old flag to
3981 // use the new one.
3982 ReplaceValueWith(From: SDValue(N, 1), To: Ovf);
3983}
3984
3985void DAGTypeLegalizer::ExpandIntRes_UADDSUBO_CARRY(SDNode *N, SDValue &Lo,
3986 SDValue &Hi) {
3987 // Expand the subcomponents.
3988 SDValue LHSL, LHSH, RHSL, RHSH;
3989 SDLoc dl(N);
3990 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3991 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3992 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3993 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3994 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
3995
3996 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3997 HiOps[2] = Lo.getValue(R: 1);
3998 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
3999
4000 // Legalized the flag result - switch anything that used the old flag to
4001 // use the new one.
4002 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4003}
4004
4005void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
4006 SDValue &Lo, SDValue &Hi) {
4007 // Expand the subcomponents.
4008 SDValue LHSL, LHSH, RHSL, RHSH;
4009 SDLoc dl(N);
4010 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4011 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
4012 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
4013
4014 // We need to use an unsigned carry op for the lo part.
4015 unsigned CarryOp =
4016 N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
4017 Lo = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSL, RHSL, N->getOperand(Num: 2) });
4018 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4019
4020 // Legalized the flag result - switch anything that used the old flag to
4021 // use the new one.
4022 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
4023}
4024
4025void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
4026 SDValue &Lo, SDValue &Hi) {
4027 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4028 SDLoc dl(N);
4029 SDValue Op = N->getOperand(Num: 0);
4030 if (Op.getValueType().bitsLE(VT: NVT)) {
4031 // The low part is any extension of the input (which degenerates to a copy).
4032 Lo = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Op);
4033 Hi = DAG.getUNDEF(VT: NVT); // The high part is undefined.
4034 } else {
4035 // For example, extension of an i48 to an i64. The operand type necessarily
4036 // promotes to the result type, so will end up being expanded too.
4037 assert(getTypeAction(Op.getValueType()) ==
4038 TargetLowering::TypePromoteInteger &&
4039 "Only know how to promote this result!");
4040 SDValue Res = GetPromotedInteger(Op);
4041 assert(Res.getValueType() == N->getValueType(0) &&
4042 "Operand over promoted?");
4043 // Split the promoted operand. This will simplify when it is expanded.
4044 SplitInteger(Op: Res, Lo, Hi);
4045 }
4046}
4047
4048void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
4049 SDValue &Lo, SDValue &Hi) {
4050 SDLoc dl(N);
4051 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4052 EVT NVT = Lo.getValueType();
4053 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4054 unsigned NVTBits = NVT.getSizeInBits();
4055 unsigned EVTBits = EVT.getSizeInBits();
4056
4057 if (NVTBits < EVTBits) {
4058 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Hi,
4059 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4060 BitWidth: EVTBits - NVTBits)));
4061 } else {
4062 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4063 // The high part replicates the sign bit of Lo, make it explicit.
4064 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4065 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL: dl));
4066 }
4067}
4068
4069void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
4070 SDValue &Lo, SDValue &Hi) {
4071 SDLoc dl(N);
4072 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4073 EVT NVT = Lo.getValueType();
4074 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
4075 unsigned NVTBits = NVT.getSizeInBits();
4076 unsigned EVTBits = EVT.getSizeInBits();
4077
4078 if (NVTBits < EVTBits) {
4079 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Hi,
4080 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
4081 BitWidth: EVTBits - NVTBits)));
4082 } else {
4083 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
4084 // The high part must be zero, make it explicit.
4085 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4086 }
4087}
4088
4089void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
4090 SDValue &Lo, SDValue &Hi) {
4091 SDLoc dl(N);
4092 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4093 Lo = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4094 Hi = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4095}
4096
4097void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
4098 SDValue &Lo, SDValue &Hi) {
4099 SDLoc dl(N);
4100 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
4101 Lo = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Lo.getValueType(), Operand: Lo);
4102 Hi = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Hi.getValueType(), Operand: Hi);
4103}
4104
4105void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
4106 SDValue &Hi) {
4107 SDLoc dl(N);
4108 // parity(HiLo) -> parity(Lo^Hi)
4109 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4110 EVT NVT = Lo.getValueType();
4111 Lo =
4112 DAG.getNode(Opcode: ISD::PARITY, DL: dl, VT: NVT, Operand: DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Hi));
4113 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4114}
4115
4116void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
4117 SDValue &Lo, SDValue &Hi) {
4118 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4119 unsigned NBitWidth = NVT.getSizeInBits();
4120 auto Constant = cast<ConstantSDNode>(Val: N);
4121 const APInt &Cst = Constant->getAPIntValue();
4122 bool IsTarget = Constant->isTargetOpcode();
4123 bool IsOpaque = Constant->isOpaque();
4124 SDLoc dl(N);
4125 Lo = DAG.getConstant(Val: Cst.trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget, isOpaque: IsOpaque);
4126 Hi = DAG.getConstant(Val: Cst.lshr(shiftAmt: NBitWidth).trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget,
4127 isOpaque: IsOpaque);
4128}
4129
4130void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4131 SDLoc dl(N);
4132
4133 SDValue N0 = N->getOperand(Num: 0);
4134 GetExpandedInteger(Op: N0, Lo, Hi);
4135 EVT NVT = Lo.getValueType();
4136
4137 // If the upper half is all sign bits, then we can perform the ABS on the
4138 // lower half and zero-extend. We could use ISD::ABS_MIN_POISON here if
4139 // DAG.ComputeNumSignBits(N0) is larger than NVT.getScalarSizeInBits() + 1.
4140 unsigned NumSignBits = DAG.ComputeNumSignBits(Op: N0);
4141 if (NumSignBits > NVT.getScalarSizeInBits()) {
4142 unsigned AbsOpc = NumSignBits > NVT.getScalarSizeInBits() + 1
4143 ? ISD::ABS_MIN_POISON
4144 : ISD::ABS;
4145 Lo = DAG.getNode(Opcode: AbsOpc, DL: dl, VT: NVT, Operand: Lo);
4146 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4147 return;
4148 }
4149
4150 // If we have USUBO_CARRY, use the expanded form of the sra+xor+sub sequence
4151 // we use in LegalizeDAG. The SUB part of the expansion is based on
4152 // ExpandIntRes_ADDSUB which also uses USUBO_CARRY/USUBO after checking that
4153 // USUBO_CARRY is LegalOrCustom. Each of the pieces here can be further
4154 // expanded if needed. Shift expansion has a special case for filling with
4155 // sign bits so that we will only end up with one SRA.
4156 bool HasSubCarry = TLI.isOperationLegalOrCustom(
4157 Op: ISD::USUBO_CARRY, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
4158 if (HasSubCarry) {
4159 SDValue Sign = DAG.getNode(
4160 Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Hi,
4161 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - 1, VT: NVT, DL: dl));
4162 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
4163 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Sign);
4164 Hi = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Hi, N2: Sign);
4165 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: Lo, N2: Sign);
4166 Hi = DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: Hi, N2: Sign, N3: Lo.getValue(R: 1));
4167 return;
4168 }
4169
4170 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
4171 EVT VT = N->getValueType(ResNo: 0);
4172 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT,
4173 N1: DAG.getConstant(Val: 0, DL: dl, VT), N2: N0);
4174 SDValue NegLo, NegHi;
4175 SplitInteger(Op: Neg, Lo&: NegLo, Hi&: NegHi);
4176
4177 SDValue HiIsNeg = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4178 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETLT);
4179 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegLo, RHS: Lo);
4180 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegHi, RHS: Hi);
4181}
4182
4183void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
4184 SDValue &Lo, SDValue &Hi) {
4185 SDLoc dl(N);
4186 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
4187 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4188 EVT NVT = Lo.getValueType();
4189
4190 SDValue HiNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4191 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4192
4193 SDValue LoLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Lo);
4194 SDValue HiLZ = DAG.getNode(Opcode: ISD::CTLZ_ZERO_POISON, DL: dl, VT: NVT, Operand: Hi);
4195
4196 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiNotZero, LHS: HiLZ,
4197 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoLZ,
4198 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4199 VT: NVT)));
4200 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4201}
4202
4203void DAGTypeLegalizer::ExpandIntRes_CTLS(SDNode *N, SDValue &Lo, SDValue &Hi) {
4204 SDLoc dl(N);
4205 // ctls(HiLo) -> if (IsAllSignBits = (ctls(Hi) == BW-1)) then
4206 // BW-1 + clz(IsNegative = (Hi < 0) ? ~Lo : Lo)
4207 // else ctls(Hi)
4208 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4209 EVT NVT = Lo.getValueType();
4210 unsigned NVTBits = NVT.getScalarSizeInBits();
4211
4212 SDValue Constant0 = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4213 SDValue ConstantBWM1 = DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: NVT);
4214
4215 SDValue HiCTLS = DAG.getNode(Opcode: ISD::CTLS, DL: dl, VT: NVT, Operand: Hi);
4216 SDValue IsAllSignBits = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: HiCTLS,
4217 RHS: ConstantBWM1, Cond: ISD::SETEQ);
4218 SDValue IsNegative =
4219 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi, RHS: Constant0, Cond: ISD::SETLT);
4220 SDValue AdjustedLo =
4221 DAG.getSelect(DL: dl, VT: NVT, Cond: IsNegative, LHS: DAG.getNOT(DL: dl, Val: Lo, VT: NVT), RHS: Lo);
4222 SDValue LoCLZ = DAG.getNode(Opcode: ISD::CTLZ, DL: dl, VT: NVT, Operand: AdjustedLo);
4223 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: IsAllSignBits,
4224 LHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoCLZ, N2: ConstantBWM1),
4225 RHS: HiCTLS);
4226 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4227}
4228
4229void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
4230 SDValue Result = TLI.expandABD(N, DAG);
4231 SplitInteger(Op: Result, Lo, Hi);
4232}
4233
4234void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
4235 SDValue Op = N->getOperand(Num: 0);
4236 EVT VT = N->getValueType(ResNo: 0);
4237 SDLoc DL(N);
4238
4239 if (TLI.getOperationAction(Op: ISD::CTPOP, VT) == TargetLoweringBase::LibCall) {
4240 RTLIB::Libcall LC = RTLIB::getCTPOP(VT);
4241 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
4242 "LibCall explicitly requested, but not available");
4243
4244 if (RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
4245 TargetLowering::MakeLibCallOptions CallOptions;
4246 EVT IntVT =
4247 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
4248 SDValue Res =
4249 TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: IntVT, Ops: Op, CallOptions, dl: DL).first;
4250 SplitInteger(Op: DAG.getSExtOrTrunc(Op: Res, DL, VT), Lo, Hi);
4251 return;
4252 }
4253
4254 // If the function is not available, fall back on the expansion.
4255 }
4256
4257 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
4258 GetExpandedInteger(Op, Lo, Hi);
4259 EVT NVT = Lo.getValueType();
4260 Lo = DAG.getNode(Opcode: ISD::ADD, DL, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Lo),
4261 N2: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Hi));
4262 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
4263}
4264
4265void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
4266 SDValue &Lo, SDValue &Hi) {
4267 SDLoc dl(N);
4268 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
4269 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4270 EVT NVT = Lo.getValueType();
4271
4272 SDValue LoNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
4273 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4274
4275 SDValue LoLZ = DAG.getNode(Opcode: ISD::CTTZ_ZERO_POISON, DL: dl, VT: NVT, Operand: Lo);
4276 SDValue HiLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Hi);
4277
4278 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: LoNotZero, LHS: LoLZ,
4279 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: HiLZ,
4280 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4281 VT: NVT)));
4282 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4283}
4284
4285void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo,
4286 SDValue &Hi) {
4287 SDLoc dl(N);
4288 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4289 unsigned NBitWidth = NVT.getSizeInBits();
4290
4291 Lo = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
4292 SDValue Chain = Lo.getValue(R: 1);
4293 // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING
4294 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4295 N2: DAG.getShiftAmountConstant(Val: NBitWidth - 1, VT: NVT, DL: dl));
4296
4297 // Legalize the chain result - switch anything that used the old chain to
4298 // use the new one.
4299 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
4300}
4301
4302// Helper for producing an FP_EXTEND/STRICT_FP_EXTEND of Op.
4303static SDValue fpExtendHelper(SDValue Op, SDValue &Chain, bool IsStrict, EVT VT,
4304 SDLoc DL, SelectionDAG &DAG) {
4305 if (IsStrict) {
4306 Op = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL, ResultTys: {VT, MVT::Other}, Ops: {Chain, Op});
4307 Chain = Op.getValue(R: 1);
4308 return Op;
4309 }
4310 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT, Operand: Op);
4311}
4312
4313void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
4314 SDValue &Hi) {
4315 SDLoc dl(N);
4316 EVT VT = N->getValueType(ResNo: 0);
4317
4318 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
4319 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
4320 bool IsStrict = N->isStrictFPOpcode();
4321 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4322 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4323
4324 // If the input is bf16 or needs to be soft promoted, extend to f32.
4325 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf ||
4326 Op.getValueType() == MVT::bf16) {
4327 Op = fpExtendHelper(Op, Chain, IsStrict, VT: MVT::f32, DL: dl, DAG);
4328 }
4329
4330 // NOTE: We need a variable that lives across makeLibCall so
4331 // CallOptions.setTypeListBeforeSoften can save a reference to it.
4332 EVT OpVT = Op.getValueType();
4333
4334 RTLIB::Libcall LC =
4335 IsSigned ? RTLIB::getFPTOSINT(OpVT, RetVT: VT) : RTLIB::getFPTOUINT(OpVT, RetVT: VT);
4336 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
4337 TargetLowering::MakeLibCallOptions CallOptions;
4338 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftenFloat)
4339 CallOptions.setTypeListBeforeSoften(OpsVT: OpVT, RetVT: VT);
4340 else
4341 CallOptions.setIsSigned(true); // FIXME: Is this needed?
4342 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op,
4343 CallOptions, dl, Chain);
4344 SplitInteger(Op: Tmp.first, Lo, Hi);
4345
4346 if (IsStrict)
4347 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4348}
4349
4350void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
4351 SDValue &Hi) {
4352 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
4353 SplitInteger(Op: Res, Lo, Hi);
4354}
4355
4356void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo,
4357 SDValue &Hi) {
4358 SDLoc dl(N);
4359 bool IsStrict = N->isStrictFPOpcode();
4360 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4361 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4362
4363 EVT VT = Op.getValueType();
4364
4365 if (VT == MVT::f16) {
4366 // Extend to f32.
4367 VT = MVT::f32;
4368 Op = fpExtendHelper(Op, Chain, IsStrict, VT, DL: dl, DAG);
4369 }
4370
4371 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4372 if (N->getOpcode() == ISD::LROUND ||
4373 N->getOpcode() == ISD::STRICT_LROUND) {
4374 LC = RTLIB::getLROUND(VT);
4375 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lround input type!");
4376 } else if (N->getOpcode() == ISD::LRINT ||
4377 N->getOpcode() == ISD::STRICT_LRINT) {
4378 LC = RTLIB::getLRINT(VT);
4379 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lrint input type!");
4380 } else if (N->getOpcode() == ISD::LLROUND ||
4381 N->getOpcode() == ISD::STRICT_LLROUND) {
4382 LC = RTLIB::getLLROUND(VT);
4383 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
4384 } else if (N->getOpcode() == ISD::LLRINT ||
4385 N->getOpcode() == ISD::STRICT_LLRINT) {
4386 LC = RTLIB::getLLRINT(VT);
4387 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
4388 } else
4389 llvm_unreachable("Unexpected opcode!");
4390
4391 EVT RetVT = N->getValueType(ResNo: 0);
4392
4393 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
4394 if (LCImpl == RTLIB::Unsupported) {
4395 DAG.getContext()->emitError(ErrorStr: Twine("no libcall available for ") +
4396 N->getOperationName(G: &DAG));
4397 SDValue Poison = DAG.getPOISON(VT: N->getValueType(ResNo: 0));
4398 SplitInteger(Op: Poison, Lo, Hi);
4399 if (N->isStrictFPOpcode())
4400 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
4401 return;
4402 }
4403
4404 TargetLowering::MakeLibCallOptions CallOptions;
4405 CallOptions.setIsSigned(true);
4406 std::pair<SDValue, SDValue> Tmp =
4407 TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT, Ops: Op, CallOptions, dl, Chain);
4408 SplitInteger(Op: Tmp.first, Lo, Hi);
4409
4410 if (N->isStrictFPOpcode())
4411 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4412}
4413
4414void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
4415 SDValue &Lo, SDValue &Hi) {
4416 assert(!N->isAtomic() && "Should have been a ATOMIC_LOAD?");
4417
4418 if (ISD::isNormalLoad(N)) {
4419 ExpandRes_NormalLoad(N, Lo, Hi);
4420 return;
4421 }
4422
4423 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
4424
4425 EVT VT = N->getValueType(ResNo: 0);
4426 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4427 SDValue Ch = N->getChain();
4428 SDValue Ptr = N->getBasePtr();
4429 ISD::LoadExtType ExtType = N->getExtensionType();
4430 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4431 AAMDNodes AAInfo = N->getAAInfo();
4432 SDLoc dl(N);
4433
4434 assert(NVT.isByteSized() && "Expanded type not byte sized!");
4435
4436 if (N->getMemoryVT().bitsLE(VT: NVT)) {
4437 EVT MemVT = N->getMemoryVT();
4438
4439 Lo = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), MemVT,
4440 Alignment: N->getBaseAlign(), MMOFlags, Metadata: AAInfo);
4441
4442 // Remember the chain.
4443 Ch = Lo.getValue(R: 1);
4444
4445 if (ExtType == ISD::SEXTLOAD) {
4446 // The high part is obtained by SRA'ing all but one of the bits of the
4447 // lo part.
4448 unsigned LoSize = Lo.getValueSizeInBits();
4449 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4450 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
4451 } else if (ExtType == ISD::ZEXTLOAD) {
4452 // The high part is just a zero.
4453 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4454 } else {
4455 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
4456 // The high part is undefined.
4457 Hi = DAG.getUNDEF(VT: NVT);
4458 }
4459 } else if (DAG.getDataLayout().isLittleEndian()) {
4460 // Little-endian - low bits are at low addresses.
4461 Lo = DAG.getLoad(VT: NVT, dl, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
4462 MMOFlags, Metadata: AAInfo);
4463
4464 unsigned ExcessBits =
4465 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4466 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
4467
4468 // Increment the pointer to the other half.
4469 unsigned IncrementSize = NVT.getSizeInBits()/8;
4470 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4471 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr,
4472 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize), MemVT: NEVT,
4473 Alignment: N->getBaseAlign(), MMOFlags, Metadata: AAInfo);
4474
4475 // Build a factor node to remember that this load is independent of the
4476 // other one.
4477 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4478 N2: Hi.getValue(R: 1));
4479 } else {
4480 // Big-endian - high bits are at low addresses. Favor aligned loads at
4481 // the cost of some bit-fiddling.
4482 EVT MemVT = N->getMemoryVT();
4483 unsigned EBytes = MemVT.getStoreSize();
4484 unsigned IncrementSize = NVT.getSizeInBits()/8;
4485 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4486
4487 // Load both the high bits and maybe some of the low bits.
4488 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(),
4489 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(),
4490 BitWidth: MemVT.getSizeInBits() - ExcessBits),
4491 Alignment: N->getBaseAlign(), MMOFlags, Metadata: AAInfo);
4492
4493 // Increment the pointer to the other half.
4494 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4495 // Load the rest of the low bits.
4496 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: NVT, Chain: Ch, Ptr,
4497 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
4498 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
4499 Alignment: N->getBaseAlign(), MMOFlags, Metadata: AAInfo);
4500
4501 // Build a factor node to remember that this load is independent of the
4502 // other one.
4503 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4504 N2: Hi.getValue(R: 1));
4505
4506 if (ExcessBits < NVT.getSizeInBits()) {
4507 // Transfer low bits from the bottom of Hi to the top of Lo.
4508 Lo = DAG.getNode(
4509 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Lo,
4510 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
4511 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
4512 // Move high bits to the right position in Hi.
4513 Hi = DAG.getNode(Opcode: ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
4514 N1: Hi,
4515 N2: DAG.getShiftAmountConstant(
4516 Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
4517 }
4518 }
4519
4520 // Legalize the chain result - switch anything that used the old chain to
4521 // use the new one.
4522 ReplaceValueWith(From: SDValue(N, 1), To: Ch);
4523}
4524
4525void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
4526 SDValue &Lo, SDValue &Hi) {
4527 SDLoc dl(N);
4528 SDValue LL, LH, RL, RH;
4529 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4530 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4531
4532 SDNodeFlags Flags;
4533 if (N->getOpcode() == ISD::OR)
4534 Flags.setDisjoint(N->getFlags().hasDisjoint());
4535
4536 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LL, N2: RL, Flags);
4537 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LH, N2: RH, Flags);
4538}
4539
4540void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
4541 SDValue &Lo, SDValue &Hi) {
4542 EVT VT = N->getValueType(ResNo: 0);
4543 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4544 SDLoc dl(N);
4545
4546 SDValue LL, LH, RL, RH;
4547 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4548 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4549
4550 if (TLI.expandMUL(N, Lo, Hi, HiLoVT: NVT, DAG,
4551 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4552 LL, LH, RL, RH))
4553 return;
4554
4555 // If nothing else, we can make a libcall.
4556 RTLIB::Libcall LC = RTLIB::getMUL(VT);
4557 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
4558 if (LCImpl == RTLIB::Unsupported) {
4559 // Perform a wide multiplication where the wide type is the original VT and
4560 // the 4 parts are the split arguments.
4561 TLI.forceExpandMultiply(DAG, dl, /*Signed=*/false, Lo, Hi, LHS: LL, RHS: RL, HiLHS: LH, HiRHS: RH);
4562 return;
4563 }
4564
4565 // Note that we don't need to do a wide MUL here since we don't care about the
4566 // upper half of the result if it exceeds VT.
4567 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4568 TargetLowering::MakeLibCallOptions CallOptions;
4569 CallOptions.setIsSigned(true);
4570 SplitInteger(Op: TLI.makeLibCall(DAG, LibcallImpl: LCImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
4571 Hi);
4572}
4573
4574void DAGTypeLegalizer::ExpandIntRes_READCOUNTER(SDNode *N, SDValue &Lo,
4575 SDValue &Hi) {
4576 SDLoc DL(N);
4577 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4578 SDVTList VTs = DAG.getVTList(VT1: NVT, VT2: NVT, VT3: MVT::Other);
4579 SDValue R = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N: N->getOperand(Num: 0));
4580 Lo = R.getValue(R: 0);
4581 Hi = R.getValue(R: 1);
4582 ReplaceValueWith(From: SDValue(N, 1), To: R.getValue(R: 2));
4583}
4584
4585void DAGTypeLegalizer::ExpandIntRes_AVG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4586 SDValue Result = TLI.expandAVG(N, DAG);
4587 SplitInteger(Op: Result, Lo, Hi);
4588}
4589
4590void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
4591 SDValue &Hi) {
4592 SDValue Result = TLI.expandAddSubSat(Node: N, DAG);
4593 SplitInteger(Op: Result, Lo, Hi);
4594}
4595
4596void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
4597 SDValue &Hi) {
4598 SDValue Result = TLI.expandShlSat(Node: N, DAG);
4599 SplitInteger(Op: Result, Lo, Hi);
4600}
4601
4602/// This performs an expansion of the integer result for a fixed point
4603/// multiplication. The default expansion performs rounding down towards
4604/// negative infinity, though targets that do care about rounding should specify
4605/// a target hook for rounding and provide their own expansion or lowering of
4606/// fixed point multiplication to be consistent with rounding.
4607void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
4608 SDValue &Hi) {
4609 SDLoc dl(N);
4610 EVT VT = N->getValueType(ResNo: 0);
4611 unsigned VTSize = VT.getScalarSizeInBits();
4612 SDValue LHS = N->getOperand(Num: 0);
4613 SDValue RHS = N->getOperand(Num: 1);
4614 uint64_t Scale = N->getConstantOperandVal(Num: 2);
4615 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
4616 N->getOpcode() == ISD::UMULFIXSAT);
4617 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
4618 N->getOpcode() == ISD::SMULFIXSAT);
4619
4620 // Handle special case when scale is equal to zero.
4621 if (!Scale) {
4622 SDValue Result;
4623 if (!Saturating) {
4624 Result = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS);
4625 } else {
4626 EVT BoolVT = getSetCCResultType(VT);
4627 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
4628 Result = DAG.getNode(Opcode: MulOp, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: BoolVT), N1: LHS, N2: RHS);
4629 SDValue Product = Result.getValue(R: 0);
4630 SDValue Overflow = Result.getValue(R: 1);
4631 if (Signed) {
4632 APInt MinVal = APInt::getSignedMinValue(numBits: VTSize);
4633 APInt MaxVal = APInt::getSignedMaxValue(numBits: VTSize);
4634 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT);
4635 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4636 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
4637 // Xor the inputs, if resulting sign bit is 0 the product will be
4638 // positive, else negative.
4639 SDValue Xor = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4640 SDValue ProdNeg = DAG.getSetCC(DL: dl, VT: BoolVT, LHS: Xor, RHS: Zero, Cond: ISD::SETLT);
4641 Result = DAG.getSelect(DL: dl, VT, Cond: ProdNeg, LHS: SatMin, RHS: SatMax);
4642 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: Result, RHS: Product);
4643 } else {
4644 // For unsigned multiplication, we only need to check the max since we
4645 // can't really overflow towards zero.
4646 APInt MaxVal = APInt::getMaxValue(numBits: VTSize);
4647 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4648 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: SatMax, RHS: Product);
4649 }
4650 }
4651 SplitInteger(Op: Result, Lo, Hi);
4652 return;
4653 }
4654
4655 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
4656 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
4657 assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
4658
4659 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4660 SDValue LL, LH, RL, RH;
4661 GetExpandedInteger(Op: LHS, Lo&: LL, Hi&: LH);
4662 GetExpandedInteger(Op: RHS, Lo&: RL, Hi&: RH);
4663 SmallVector<SDValue, 4> Result;
4664
4665 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
4666 if (!TLI.expandMUL_LOHI(Opcode: LoHiOp, VT, dl, LHS, RHS, Result, HiLoVT: NVT, DAG,
4667 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4668 LL, LH, RL, RH)) {
4669 Result.clear();
4670 Result.resize(N: 4);
4671
4672 SDValue LoTmp, HiTmp;
4673 TLI.forceExpandWideMUL(DAG, dl, Signed, LHS, RHS, Lo&: LoTmp, Hi&: HiTmp);
4674 SplitInteger(Op: LoTmp, Lo&: Result[0], Hi&: Result[1]);
4675 SplitInteger(Op: HiTmp, Lo&: Result[2], Hi&: Result[3]);
4676 }
4677 assert(Result.size() == 4 && "Unexpected number of partlets in the result");
4678
4679 unsigned NVTSize = NVT.getScalarSizeInBits();
4680 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
4681 "the size of the current value type");
4682
4683 // After getting the multiplication result in 4 parts, we need to perform a
4684 // shift right by the amount of the scale to get the result in that scale.
4685 //
4686 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
4687 // 128 bits that are cut into 4 32-bit parts:
4688 //
4689 // HH HL LH LL
4690 // |---32---|---32---|---32---|---32---|
4691 // 128 96 64 32 0
4692 //
4693 // |------VTSize-----|
4694 //
4695 // |NVTSize-|
4696 //
4697 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
4698 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
4699 // amount and get Lo and Hi using two funnel shifts. Or for the special case
4700 // when Scale is a multiple of NVTSize we can just pick the result without
4701 // shifting.
4702 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
4703 if (Scale % NVTSize) {
4704 SDValue ShiftAmount = DAG.getShiftAmountConstant(Val: Scale % NVTSize, VT: NVT, DL: dl);
4705 Lo = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 1], N2: Result[Part0],
4706 N3: ShiftAmount);
4707 Hi = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 2], N2: Result[Part0 + 1],
4708 N3: ShiftAmount);
4709 } else {
4710 Lo = Result[Part0];
4711 Hi = Result[Part0 + 1];
4712 }
4713
4714 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
4715 if (!Saturating)
4716 return;
4717
4718 // Can not overflow when there is no integer part.
4719 if (Scale == VTSize)
4720 return;
4721
4722 // To handle saturation we must check for overflow in the multiplication.
4723 //
4724 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
4725 // aren't all zeroes.
4726 //
4727 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
4728 // aren't all ones or all zeroes.
4729 //
4730 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
4731 // highest bit of HH determines saturation direction in the event of signed
4732 // saturation.
4733
4734 SDValue ResultHL = Result[2];
4735 SDValue ResultHH = Result[3];
4736
4737 SDValue SatMax, SatMin;
4738 SDValue NVTZero = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4739 SDValue NVTNeg1 = DAG.getAllOnesConstant(DL: dl, VT: NVT);
4740 EVT BoolNVT = getSetCCResultType(VT: NVT);
4741
4742 if (!Signed) {
4743 if (Scale < NVTSize) {
4744 // Overflow happened if ((HH | (HL >> Scale)) != 0).
4745 SDValue HLAdjusted =
4746 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4747 N2: DAG.getShiftAmountConstant(Val: Scale, VT: NVT, DL: dl));
4748 SDValue Tmp = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: HLAdjusted, N2: ResultHH);
4749 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: Tmp, RHS: NVTZero, Cond: ISD::SETNE);
4750 } else if (Scale == NVTSize) {
4751 // Overflow happened if (HH != 0).
4752 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETNE);
4753 } else if (Scale < VTSize) {
4754 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
4755 SDValue HLAdjusted =
4756 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4757 N2: DAG.getShiftAmountConstant(Val: Scale - NVTSize, VT: NVT, DL: dl));
4758 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: HLAdjusted, RHS: NVTZero, Cond: ISD::SETNE);
4759 } else
4760 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
4761 "(and saturation can't happen with Scale==VTSize).");
4762
4763 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Hi);
4764 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Lo);
4765 return;
4766 }
4767
4768 if (Scale < NVTSize) {
4769 // The number of overflow bits we can check are VTSize - Scale + 1 (we
4770 // include the sign bit). If these top bits are > 0, then we overflowed past
4771 // the max value. If these top bits are < -1, then we overflowed past the
4772 // min value. Otherwise, we did not overflow.
4773 unsigned OverflowBits = VTSize - Scale + 1;
4774 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
4775 "Extent of overflow bits must start within HL");
4776 SDValue HLHiMask = DAG.getConstant(
4777 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits - NVTSize), DL: dl, VT: NVT);
4778 SDValue HLLoMask = DAG.getConstant(
4779 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: VTSize - OverflowBits), DL: dl, VT: NVT);
4780 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
4781 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4782 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4783 SDValue HLUGT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLLoMask, Cond: ISD::SETUGT);
4784 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4785 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLUGT));
4786 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
4787 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4788 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4789 SDValue HLULT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLHiMask, Cond: ISD::SETULT);
4790 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4791 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLULT));
4792 } else if (Scale == NVTSize) {
4793 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
4794 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4795 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4796 SDValue HLNeg = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETLT);
4797 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4798 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLNeg));
4799 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
4800 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4801 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4802 SDValue HLPos = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETGE);
4803 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4804 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLPos));
4805 } else if (Scale < VTSize) {
4806 // This is similar to the case when we saturate if Scale < NVTSize, but we
4807 // only need to check HH.
4808 unsigned OverflowBits = VTSize - Scale + 1;
4809 SDValue HHHiMask = DAG.getConstant(
4810 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits), DL: dl, VT: NVT);
4811 SDValue HHLoMask = DAG.getConstant(
4812 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: NVTSize - OverflowBits), DL: dl, VT: NVT);
4813 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHLoMask, Cond: ISD::SETGT);
4814 SatMin = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHHiMask, Cond: ISD::SETLT);
4815 } else
4816 llvm_unreachable("Illegal scale for signed fixed point mul.");
4817
4818 // Saturate to signed maximum.
4819 APInt MaxHi = APInt::getSignedMaxValue(numBits: NVTSize);
4820 APInt MaxLo = APInt::getAllOnes(numBits: NVTSize);
4821 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxHi, DL: dl, VT: NVT), RHS: Hi);
4822 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxLo, DL: dl, VT: NVT), RHS: Lo);
4823 // Saturate to signed minimum.
4824 APInt MinHi = APInt::getSignedMinValue(numBits: NVTSize);
4825 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: DAG.getConstant(Val: MinHi, DL: dl, VT: NVT), RHS: Hi);
4826 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: NVTZero, RHS: Lo);
4827}
4828
4829void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
4830 SDValue &Hi) {
4831 SDLoc dl(N);
4832 // Try expanding in the existing type first.
4833 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: N->getOperand(Num: 0),
4834 RHS: N->getOperand(Num: 1),
4835 Scale: N->getConstantOperandVal(Num: 2), DAG);
4836
4837 if (!Res)
4838 Res = earlyExpandDIVFIX(N, LHS: N->getOperand(Num: 0), RHS: N->getOperand(Num: 1),
4839 Scale: N->getConstantOperandVal(Num: 2), TLI, DAG);
4840 SplitInteger(Op: Res, Lo, Hi);
4841}
4842
4843void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
4844 SDValue &Lo, SDValue &Hi) {
4845 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
4846 "Node has unexpected Opcode");
4847 SDValue LHS = Node->getOperand(Num: 0);
4848 SDValue RHS = Node->getOperand(Num: 1);
4849 SDLoc dl(Node);
4850
4851 SDValue Ovf;
4852
4853 bool IsAdd = Node->getOpcode() == ISD::SADDO;
4854 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
4855
4856 bool HasCarryOp = TLI.isOperationLegalOrCustom(
4857 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
4858
4859 if (HasCarryOp) {
4860 // Expand the subcomponents.
4861 SDValue LHSL, LHSH, RHSL, RHSH;
4862 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
4863 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
4864 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: Node->getValueType(ResNo: 1));
4865
4866 Lo = DAG.getNode(Opcode: IsAdd ? ISD::UADDO : ISD::USUBO, DL: dl, VTList, Ops: {LHSL, RHSL});
4867 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4868
4869 Ovf = Hi.getValue(R: 1);
4870 } else {
4871 // Expand the result by simply replacing it with the equivalent
4872 // non-overflow-checking operation.
4873 SDValue Sum = DAG.getNode(Opcode: Node->getOpcode() == ISD::SADDO ?
4874 ISD::ADD : ISD::SUB, DL: dl, VT: LHS.getValueType(),
4875 N1: LHS, N2: RHS);
4876 SplitInteger(Op: Sum, Lo, Hi);
4877
4878 // Compute the overflow.
4879 //
4880 // LHSSign -> LHS < 0
4881 // RHSSign -> RHS < 0
4882 // SumSign -> Sum < 0
4883 //
4884 // Add:
4885 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4886 // Sub:
4887 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4888 //
4889 // To get better codegen we can rewrite this by doing bitwise math on
4890 // the integers and extract the final sign bit at the end. So the
4891 // above becomes:
4892 //
4893 // Add:
4894 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
4895 // Sub:
4896 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
4897 //
4898 // NOTE: This is different than the expansion we do in expandSADDSUBO
4899 // because it is more costly to implement the same overflow predicate with
4900 // SETCC nodes when the integers are split.
4901 EVT VT = LHS.getValueType();
4902 SDValue SignsMatch = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4903 if (IsAdd)
4904 SignsMatch = DAG.getNOT(DL: dl, Val: SignsMatch, VT);
4905
4906 SDValue SumSignNE = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: Sum);
4907 Ovf = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: SignsMatch, N2: SumSignNE);
4908 EVT OType = Node->getValueType(ResNo: 1);
4909 Ovf = DAG.getSetCC(DL: dl, VT: OType, LHS: Ovf, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETLT);
4910 }
4911
4912 // Use the calculated overflow everywhere.
4913 ReplaceValueWith(From: SDValue(Node, 1), To: Ovf);
4914}
4915
4916void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
4917 SDValue &Lo, SDValue &Hi) {
4918 EVT VT = N->getValueType(ResNo: 0);
4919 SDLoc dl(N);
4920 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4921
4922 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
4923 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
4924 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
4925 return;
4926 }
4927
4928 RTLIB::Libcall LC = RTLIB::getSDIV(VT);
4929 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
4930
4931 TargetLowering::MakeLibCallOptions CallOptions;
4932 CallOptions.setIsSigned(true);
4933 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
4934}
4935
4936void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
4937 SDValue &Hi) {
4938 SDLoc dl(N);
4939 SDValue Shiftee = N->getOperand(Num: 0);
4940 EVT VT = Shiftee.getValueType();
4941 SDValue ShAmt = N->getOperand(Num: 1);
4942 EVT ShAmtVT = ShAmt.getValueType();
4943
4944 EVT LoadVT = VT;
4945 do {
4946 LoadVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: LoadVT);
4947 } while (!TLI.isTypeLegal(VT: LoadVT));
4948
4949 const unsigned ShiftUnitInBits = LoadVT.getStoreSizeInBits();
4950 assert(ShiftUnitInBits <= VT.getScalarSizeInBits());
4951 assert(isPowerOf2_32(ShiftUnitInBits) &&
4952 "Shifting unit is not a a power of two!");
4953
4954 const bool IsOneStepShift =
4955 DAG.computeKnownBits(Op: ShAmt).countMinTrailingZeros() >=
4956 Log2_32(Value: ShiftUnitInBits);
4957
4958 // If we can't do it as one step, we'll have two uses of shift amount,
4959 // and thus must freeze it.
4960 if (!IsOneStepShift)
4961 ShAmt = DAG.getFreeze(V: ShAmt);
4962
4963 unsigned VTBitWidth = VT.getScalarSizeInBits();
4964 assert(VTBitWidth % 8 == 0 && "Shifting a not byte multiple value?");
4965 unsigned VTByteWidth = VTBitWidth / 8;
4966 assert(isPowerOf2_32(VTByteWidth) &&
4967 "Shiftee type size is not a power of two!");
4968 unsigned StackSlotByteWidth = 2 * VTByteWidth;
4969 unsigned StackSlotBitWidth = 8 * StackSlotByteWidth;
4970 EVT StackSlotVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StackSlotBitWidth);
4971
4972 // Get a temporary stack slot 2x the width of our VT.
4973 // FIXME: reuse stack slots?
4974 Align StackAlign = DAG.getReducedAlign(VT: StackSlotVT, /*UseABI=*/false);
4975 SDValue StackPtr =
4976 DAG.CreateStackTemporary(Bytes: StackSlotVT.getStoreSize(), Alignment: StackAlign);
4977 EVT PtrTy = StackPtr.getValueType();
4978 SDValue Ch = DAG.getEntryNode();
4979
4980 MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
4981 MF&: DAG.getMachineFunction(),
4982 FI: cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex());
4983
4984 // Extend the value, that is being shifted, to the entire stack slot's width.
4985 SDValue Init;
4986 if (N->getOpcode() != ISD::SHL) {
4987 unsigned WideningOpc =
4988 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4989 Init = DAG.getNode(Opcode: WideningOpc, DL: dl, VT: StackSlotVT, Operand: Shiftee);
4990 } else {
4991 // For left-shifts, pad the Shiftee's LSB with zeros to twice it's width.
4992 SDValue AllZeros = DAG.getConstant(Val: 0, DL: dl, VT);
4993 Init = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: StackSlotVT, N1: AllZeros, N2: Shiftee);
4994 }
4995 // And spill it into the stack slot.
4996 Ch = DAG.getStore(Chain: Ch, dl, Val: Init, Ptr: StackPtr, PtrInfo: StackPtrInfo, Alignment: StackAlign);
4997
4998 // Now, compute the full-byte offset into stack slot from where we can load.
4999 // We have shift amount, which is in bits. Offset should point to an aligned
5000 // address.
5001 SDNodeFlags Flags;
5002 Flags.setExact(IsOneStepShift);
5003 SDValue SrlTmp = DAG.getNode(
5004 Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: ShAmt,
5005 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT), Flags);
5006 SDValue BitOffset =
5007 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: ShAmtVT, N1: SrlTmp,
5008 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT));
5009
5010 SDValue ByteOffset =
5011 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: BitOffset,
5012 N2: DAG.getConstant(Val: 3, DL: dl, VT: ShAmtVT), Flags: SDNodeFlags::Exact);
5013 // And clamp it, because OOB load is an immediate UB,
5014 // while shift overflow would have *just* been poison.
5015 ByteOffset = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ByteOffset,
5016 N2: DAG.getConstant(Val: VTByteWidth - 1, DL: dl, VT: ShAmtVT));
5017 // We have exactly two strategies on indexing into stack slot here:
5018 // 1. upwards starting from the beginning of the slot
5019 // 2. downwards starting from the middle of the slot
5020 // On little-endian machine, we pick 1. for right shifts and 2. for left-shift
5021 // and vice versa on big-endian machine.
5022 bool WillIndexUpwards = N->getOpcode() != ISD::SHL;
5023 if (DAG.getDataLayout().isBigEndian())
5024 WillIndexUpwards = !WillIndexUpwards;
5025
5026 SDValue AdjStackPtr;
5027 if (WillIndexUpwards) {
5028 AdjStackPtr = StackPtr;
5029 } else {
5030 AdjStackPtr = DAG.getMemBasePlusOffset(
5031 Base: StackPtr, Offset: DAG.getConstant(Val: VTByteWidth, DL: dl, VT: PtrTy), DL: dl);
5032 ByteOffset = DAG.getNegative(Val: ByteOffset, DL: dl, VT: ShAmtVT);
5033 }
5034
5035 // Get the pointer somewhere into the stack slot from which we need to load.
5036 ByteOffset = DAG.getSExtOrTrunc(Op: ByteOffset, DL: dl, VT: PtrTy);
5037 AdjStackPtr = DAG.getMemBasePlusOffset(Base: AdjStackPtr, Offset: ByteOffset, DL: dl);
5038
5039 // And load it! While the load is not legal, legalizing it is obvious.
5040 SDValue Res =
5041 DAG.getLoad(VT, dl, Chain: Ch, Ptr: AdjStackPtr,
5042 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
5043 Alignment: commonAlignment(A: StackAlign, Offset: LoadVT.getStoreSize()));
5044
5045 // If we may still have a remaining bits to shift by, do so now.
5046 if (!IsOneStepShift) {
5047 SDValue ShAmtRem =
5048 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ShAmt,
5049 N2: DAG.getConstant(Val: ShiftUnitInBits - 1, DL: dl, VT: ShAmtVT));
5050 Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT, N1: Res, N2: ShAmtRem);
5051 }
5052
5053 // Finally, split the computed value.
5054 SplitInteger(Op: Res, Lo, Hi);
5055}
5056
5057void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
5058 SDValue &Lo, SDValue &Hi) {
5059 EVT VT = N->getValueType(ResNo: 0);
5060 unsigned Opc = N->getOpcode();
5061 SDLoc dl(N);
5062
5063 // If we can emit an efficient shift operation, do so now. Check to see if
5064 // the RHS is a constant.
5065 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1)))
5066 return ExpandShiftByConstant(N, Amt: CN->getAPIntValue(), Lo, Hi);
5067
5068 // If we can determine that the high bit of the shift is zero or one, even if
5069 // the low bits are variable, emit this shift in an optimized form.
5070 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
5071 return;
5072
5073 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
5074 unsigned PartsOpc;
5075 if (Opc == ISD::SHL) {
5076 PartsOpc = ISD::SHL_PARTS;
5077 } else if (Opc == ISD::SRL) {
5078 PartsOpc = ISD::SRL_PARTS;
5079 } else {
5080 assert(Opc == ISD::SRA && "Unknown shift!");
5081 PartsOpc = ISD::SRA_PARTS;
5082 }
5083
5084 // Next check to see if the target supports this SHL_PARTS operation or if it
5085 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
5086 // size, but create a libcall instead.
5087 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5088 TargetLowering::LegalizeAction Action = TLI.getOperationAction(Op: PartsOpc, VT: NVT);
5089 const bool LegalOrCustom =
5090 (Action == TargetLowering::Legal && TLI.isTypeLegal(VT: NVT)) ||
5091 Action == TargetLowering::Custom;
5092
5093 unsigned ExpansionFactor = 1;
5094 // That VT->NVT expansion is one step. But will we re-expand NVT?
5095 for (EVT TmpVT = NVT;;) {
5096 EVT NewTMPVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: TmpVT);
5097 if (NewTMPVT == TmpVT)
5098 break;
5099 TmpVT = NewTMPVT;
5100 ++ExpansionFactor;
5101 }
5102
5103 TargetLowering::ShiftLegalizationStrategy S =
5104 TLI.preferredShiftLegalizationStrategy(DAG, N, ExpansionFactor);
5105
5106 if (S == TargetLowering::ShiftLegalizationStrategy::ExpandThroughStack)
5107 return ExpandIntRes_ShiftThroughStack(N, Lo, Hi);
5108
5109 if (LegalOrCustom &&
5110 S != TargetLowering::ShiftLegalizationStrategy::LowerToLibcall) {
5111 // Expand the subcomponents.
5112 SDValue LHSL, LHSH;
5113 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
5114 EVT VT = LHSL.getValueType();
5115
5116 // If the shift amount operand is coming from a vector legalization it may
5117 // have an illegal type. Fix that first by casting the operand, otherwise
5118 // the new SHL_PARTS operation would need further legalization.
5119 SDValue ShiftOp = N->getOperand(Num: 1);
5120 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
5121 if (ShiftOp.getValueType() != ShiftTy)
5122 ShiftOp = DAG.getZExtOrTrunc(Op: ShiftOp, DL: dl, VT: ShiftTy);
5123
5124 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
5125 Lo = DAG.getNode(Opcode: PartsOpc, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5126 Hi = Lo.getValue(R: 1);
5127 return;
5128 }
5129
5130 // Otherwise, emit a libcall.
5131 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5132 bool isSigned;
5133 if (Opc == ISD::SHL) {
5134 isSigned = false; /*sign irrelevant*/
5135 LC = RTLIB::getSHL(VT);
5136 } else if (Opc == ISD::SRL) {
5137 isSigned = false;
5138 LC = RTLIB::getSRL(VT);
5139 } else {
5140 assert(Opc == ISD::SRA && "Unknown shift!");
5141 isSigned = true;
5142 LC = RTLIB::getSRA(VT);
5143 }
5144
5145 if (RTLIB::LibcallImpl LibcallImpl = DAG.getLibcalls().getLibcallImpl(Call: LC)) {
5146 EVT ShAmtTy =
5147 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
5148 SDValue ShAmt = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl, VT: ShAmtTy);
5149 SDValue Ops[2] = {N->getOperand(Num: 0), ShAmt};
5150 TargetLowering::MakeLibCallOptions CallOptions;
5151 CallOptions.setIsSigned(isSigned);
5152 SplitInteger(
5153 Op: TLI.makeLibCall(DAG, LibcallImpl, RetVT: VT, Ops, CallOptions, dl).first, Lo,
5154 Hi);
5155 return;
5156 }
5157
5158 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
5159 llvm_unreachable("Unsupported shift!");
5160}
5161
5162void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
5163 SDValue &Lo, SDValue &Hi) {
5164 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5165 SDLoc dl(N);
5166 SDValue Op = N->getOperand(Num: 0);
5167 if (Op.getValueType().bitsLE(VT: NVT)) {
5168 // The low part is sign extension of the input (degenerates to a copy).
5169 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5170 // The high part is obtained by SRA'ing all but one of the bits of low part.
5171 unsigned LoSize = NVT.getSizeInBits();
5172 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
5173 N2: DAG.getShiftAmountConstant(Val: LoSize - 1, VT: NVT, DL: dl));
5174 } else {
5175 // For example, extension of an i48 to an i64. The operand type necessarily
5176 // promotes to the result type, so will end up being expanded too.
5177 assert(getTypeAction(Op.getValueType()) ==
5178 TargetLowering::TypePromoteInteger &&
5179 "Only know how to promote this result!");
5180 SDValue Res = GetPromotedInteger(Op);
5181 assert(Res.getValueType() == N->getValueType(0) &&
5182 "Operand over promoted?");
5183 // Split the promoted operand. This will simplify when it is expanded.
5184 SplitInteger(Op: Res, Lo, Hi);
5185 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5186 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5187 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5188 BitWidth: ExcessBits)));
5189 }
5190}
5191
5192void DAGTypeLegalizer::
5193ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
5194 SDLoc dl(N);
5195 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5196 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
5197
5198 if (EVT.bitsLE(VT: Lo.getValueType())) {
5199 // sext_inreg the low part if needed.
5200 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Lo.getValueType(), N1: Lo,
5201 N2: N->getOperand(Num: 1));
5202
5203 // The high part gets the sign extension from the lo-part. This handles
5204 // things like sextinreg V:i64 from i8.
5205 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: Hi.getValueType(), N1: Lo,
5206 N2: DAG.getShiftAmountConstant(Val: Hi.getValueSizeInBits() - 1,
5207 VT: Hi.getValueType(), DL: dl));
5208 } else {
5209 // For example, extension of an i48 to an i64. Leave the low part alone,
5210 // sext_inreg the high part.
5211 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
5212 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5213 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5214 BitWidth: ExcessBits)));
5215 }
5216}
5217
5218void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
5219 SDValue &Lo, SDValue &Hi) {
5220 EVT VT = N->getValueType(ResNo: 0);
5221 SDLoc dl(N);
5222 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5223
5224 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5225 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5226 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5227 return;
5228 }
5229
5230 RTLIB::Libcall LC = RTLIB::getSREM(VT);
5231 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
5232
5233 TargetLowering::MakeLibCallOptions CallOptions;
5234 CallOptions.setIsSigned(true);
5235 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5236}
5237
5238void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
5239 SDValue &Lo, SDValue &Hi) {
5240 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5241 SDValue InOp = N->getOperand(Num: 0);
5242 EVT InVT = InOp.getValueType();
5243 SDLoc dl(N);
5244 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: InOp);
5245 Hi = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: InVT, N1: InOp,
5246 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits(), VT: InVT, DL: dl));
5247 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Hi);
5248}
5249
5250void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
5251 SDValue &Lo, SDValue &Hi) {
5252 EVT VT = N->getValueType(ResNo: 0);
5253 SDLoc dl(N);
5254
5255 if (N->getOpcode() == ISD::UMULO) {
5256 // This section expands the operation into the following sequence of
5257 // instructions. `iNh` here refers to a type which has half the bit width of
5258 // the type the original operation operated on.
5259 //
5260 // %0 = %LHS.HI != 0 && %RHS.HI != 0
5261 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
5262 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
5263 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
5264 // %4 = add iNh %1.0, %2.0 as iN
5265 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
5266 //
5267 // %lo = %3.LO
5268 // %hi = %5.0
5269 // %ovf = %0 || %1.1 || %2.1 || %5.1
5270 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
5271 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
5272 GetExpandedInteger(Op: LHS, Lo&: LHSLow, Hi&: LHSHigh);
5273 GetExpandedInteger(Op: RHS, Lo&: RHSLow, Hi&: RHSHigh);
5274 EVT HalfVT = LHSLow.getValueType();
5275 EVT BitVT = N->getValueType(ResNo: 1);
5276 SDVTList VTHalfWithO = DAG.getVTList(VT1: HalfVT, VT2: BitVT);
5277
5278 SDValue HalfZero = DAG.getConstant(Val: 0, DL: dl, VT: HalfVT);
5279 SDValue Overflow = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BitVT,
5280 N1: DAG.getSetCC(DL: dl, VT: BitVT, LHS: LHSHigh, RHS: HalfZero, Cond: ISD::SETNE),
5281 N2: DAG.getSetCC(DL: dl, VT: BitVT, LHS: RHSHigh, RHS: HalfZero, Cond: ISD::SETNE));
5282
5283 SDValue One = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: LHSHigh, N2: RHSLow);
5284 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: One.getValue(R: 1));
5285
5286 SDValue Two = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: RHSHigh, N2: LHSLow);
5287 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Two.getValue(R: 1));
5288
5289 SDValue HighSum = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: HalfVT, N1: One, N2: Two);
5290
5291 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
5292 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
5293 // operation recursively legalized?).
5294 //
5295 // Many backends understand this pattern and will convert into LOHI
5296 // themselves, if applicable.
5297 SDValue Three = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT,
5298 N1: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: LHSLow),
5299 N2: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: RHSLow));
5300 SplitInteger(Op: Three, Lo, Hi);
5301
5302 Hi = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList: VTHalfWithO, N1: Hi, N2: HighSum);
5303 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Hi.getValue(R: 1));
5304 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5305 return;
5306 }
5307
5308 Type *RetTy = VT.getTypeForEVT(Context&: *DAG.getContext());
5309 EVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
5310 Type *PtrTy = PtrVT.getTypeForEVT(Context&: *DAG.getContext());
5311
5312 // Replace this with a libcall that will check overflow.
5313 RTLIB::Libcall LC = RTLIB::getMULO(VT);
5314 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
5315
5316 // If we don't have the libcall or if the function we are compiling is the
5317 // implementation of the expected libcall (avoid inf-loop), expand inline.
5318 if (LCImpl == RTLIB::Unsupported ||
5319 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LCImpl) ==
5320 DAG.getMachineFunction().getName()) {
5321 // FIXME: This is not an optimal expansion, but better than crashing.
5322 SDValue MulLo, MulHi;
5323 TLI.forceExpandWideMUL(DAG, dl, /*Signed=*/true, LHS: N->getOperand(Num: 0),
5324 RHS: N->getOperand(Num: 1), Lo&: MulLo, Hi&: MulHi);
5325 SDValue SRA = DAG.getNode(
5326 Opcode: ISD::SRA, DL: dl, VT, N1: MulLo,
5327 N2: DAG.getShiftAmountConstant(Val: VT.getScalarSizeInBits() - 1, VT, DL: dl));
5328 SDValue Overflow =
5329 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: MulHi, RHS: SRA, Cond: ISD::SETNE);
5330 SplitInteger(Op: MulLo, Lo, Hi);
5331 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5332 return;
5333 }
5334
5335 SDValue Temp = DAG.CreateStackTemporary(VT: PtrVT);
5336 // Temporary for the overflow value, default it to zero.
5337 SDValue Chain =
5338 DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT), Ptr: Temp,
5339 PtrInfo: MachinePointerInfo());
5340
5341 TargetLowering::ArgListTy Args;
5342 for (const SDValue &Op : N->op_values()) {
5343 EVT ArgVT = Op.getValueType();
5344 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
5345 TargetLowering::ArgListEntry Entry(Op, ArgTy);
5346 Entry.IsSExt = true;
5347 Entry.IsZExt = false;
5348 Args.push_back(x: Entry);
5349 }
5350
5351 // Also pass the address of the overflow check.
5352 TargetLowering::ArgListEntry Entry(
5353 Temp, PointerType::getUnqual(C&: PtrTy->getContext()));
5354 Entry.IsSExt = true;
5355 Entry.IsZExt = false;
5356 Args.push_back(x: Entry);
5357
5358 SDValue Func = DAG.getExternalSymbol(LCImpl, VT: PtrVT);
5359
5360 TargetLowering::CallLoweringInfo CLI(DAG);
5361 CLI.setDebugLoc(dl)
5362 .setChain(Chain)
5363 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
5364 Target: Func, ArgsList: std::move(Args))
5365 .setSExtResult();
5366
5367 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
5368
5369 SplitInteger(Op: CallInfo.first, Lo, Hi);
5370 SDValue Temp2 =
5371 DAG.getLoad(VT: PtrVT, dl, Chain: CallInfo.second, Ptr: Temp, PtrInfo: MachinePointerInfo());
5372 SDValue Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Temp2,
5373 RHS: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT),
5374 Cond: ISD::SETNE);
5375 // Use the overflow from the libcall everywhere.
5376 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
5377}
5378
5379void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
5380 SDValue &Lo, SDValue &Hi) {
5381 EVT VT = N->getValueType(ResNo: 0);
5382 SDLoc dl(N);
5383 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5384
5385 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5386 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5387 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5388 return;
5389 }
5390
5391 // Try to expand UDIV by constant.
5392 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5393 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5394 // Only if the new type is legal.
5395 if (isTypeLegal(VT: NVT)) {
5396 SDValue InL, InH;
5397 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5398 SmallVector<SDValue> Result;
5399 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5400 Lo = Result[0];
5401 Hi = Result[1];
5402 return;
5403 }
5404 }
5405 }
5406
5407 RTLIB::Libcall LC = RTLIB::getUDIV(VT);
5408 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
5409
5410 TargetLowering::MakeLibCallOptions CallOptions;
5411 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5412}
5413
5414void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
5415 SDValue &Lo, SDValue &Hi) {
5416 EVT VT = N->getValueType(ResNo: 0);
5417 SDLoc dl(N);
5418 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5419
5420 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5421 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5422 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5423 return;
5424 }
5425
5426 // Try to expand UREM by constant.
5427 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5428 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5429 // Only if the new type is legal.
5430 if (isTypeLegal(VT: NVT)) {
5431 SDValue InL, InH;
5432 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5433 SmallVector<SDValue> Result;
5434 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5435 Lo = Result[0];
5436 Hi = Result[1];
5437 return;
5438 }
5439 }
5440 }
5441
5442 RTLIB::Libcall LC = RTLIB::getUREM(VT);
5443 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
5444
5445 TargetLowering::MakeLibCallOptions CallOptions;
5446 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5447}
5448
5449void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
5450 SDValue &Lo, SDValue &Hi) {
5451 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5452 SDLoc dl(N);
5453 SDValue Op = N->getOperand(Num: 0);
5454 if (Op.getValueType().bitsLE(VT: NVT)) {
5455 // The low part is zero extension of the input (degenerates to a copy).
5456 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5457 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // The high part is just a zero.
5458 } else {
5459 // For example, extension of an i48 to an i64. The operand type necessarily
5460 // promotes to the result type, so will end up being expanded too.
5461 assert(getTypeAction(Op.getValueType()) ==
5462 TargetLowering::TypePromoteInteger &&
5463 "Only know how to promote this result!");
5464 SDValue Res = GetPromotedInteger(Op);
5465 assert(Res.getValueType() == N->getValueType(0) &&
5466 "Operand over promoted?");
5467 // Split the promoted operand. This will simplify when it is expanded.
5468 SplitInteger(Op: Res, Lo, Hi);
5469 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5470 Hi = DAG.getZeroExtendInReg(Op: Hi, DL: dl,
5471 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
5472 BitWidth: ExcessBits));
5473 }
5474}
5475
5476void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
5477 SDValue &Lo, SDValue &Hi) {
5478 SDLoc dl(N);
5479 EVT VT = cast<AtomicSDNode>(Val: N)->getMemoryVT();
5480 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::i1, VT3: MVT::Other);
5481 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
5482 SDValue Swap = DAG.getAtomicCmpSwap(
5483 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
5484 MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(), VTs, Chain: N->getOperand(Num: 0),
5485 Ptr: N->getOperand(Num: 1), Cmp: Zero, Swp: Zero, MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5486
5487 ReplaceValueWith(From: SDValue(N, 0), To: Swap.getValue(R: 0));
5488 ReplaceValueWith(From: SDValue(N, 1), To: Swap.getValue(R: 2));
5489}
5490
5491void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
5492 SDValue &Lo, SDValue &Hi) {
5493 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
5494 // both halves independently.
5495 SDValue Res = TLI.expandVecReduce(Node: N, DAG);
5496 SplitInteger(Op: Res, Lo, Hi);
5497}
5498
5499void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
5500 SDValue &Lo, SDValue &Hi) {
5501 // Delegate to funnel-shift expansion.
5502 SDLoc DL(N);
5503 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR;
5504 SDValue Res = DAG.getNode(Opcode, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
5505 N2: N->getOperand(Num: 0), N3: N->getOperand(Num: 1));
5506 SplitInteger(Op: Res, Lo, Hi);
5507}
5508
5509void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
5510 SDValue &Hi) {
5511 // Values numbered from least significant to most significant.
5512 SDValue In1, In2, In3, In4;
5513 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: In3, Hi&: In4);
5514 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: In1, Hi&: In2);
5515 EVT HalfVT = In1.getValueType();
5516
5517 SDLoc DL(N);
5518 unsigned Opc = N->getOpcode();
5519 SDValue ShAmt = N->getOperand(Num: 2);
5520 EVT ShAmtVT = ShAmt.getValueType();
5521 EVT ShAmtCCVT = getSetCCResultType(VT: ShAmtVT);
5522
5523 // If the shift amount is at least half the bitwidth, swap the inputs.
5524 unsigned HalfVTBits = HalfVT.getScalarSizeInBits();
5525 SDValue AndNode = DAG.getNode(Opcode: ISD::AND, DL, VT: ShAmtVT, N1: ShAmt,
5526 N2: DAG.getConstant(Val: HalfVTBits, DL, VT: ShAmtVT));
5527 SDValue Cond =
5528 DAG.getSetCC(DL, VT: ShAmtCCVT, LHS: AndNode, RHS: DAG.getConstant(Val: 0, DL, VT: ShAmtVT),
5529 Cond: Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ);
5530
5531 // Expand to a pair of funnel shifts.
5532 EVT NewShAmtVT = TLI.getShiftAmountTy(LHSTy: HalfVT, DL: DAG.getDataLayout());
5533 SDValue NewShAmt = DAG.getAnyExtOrTrunc(Op: ShAmt, DL, VT: NewShAmtVT);
5534
5535 SDValue Select1 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In1, N3: In2);
5536 SDValue Select2 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In2, N3: In3);
5537 SDValue Select3 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In3, N3: In4);
5538 Lo = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select2, N2: Select1, N3: NewShAmt);
5539 Hi = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select3, N2: Select2, N3: NewShAmt);
5540}
5541
5542void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo, SDValue &Hi) {
5543 if (N->getOpcode() != ISD::CLMUL) {
5544 SDValue Res = TLI.expandCLMUL(N, DAG);
5545 return SplitInteger(Op: Res, Lo, Hi);
5546 }
5547
5548 SDValue LL, LH, RL, RH;
5549 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
5550 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
5551 EVT HalfVT = LL.getValueType();
5552 SDLoc DL(N);
5553
5554 // The low bits are a direct CLMUL of the the low bits.
5555 Lo = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RL);
5556
5557 // We compute two Hi-Lo cross-products, XOR them, and XOR it with the overflow
5558 // of the CLMUL of the low bits (given by CLMULH of the low bits) to yield the
5559 // final high bits.
5560 SDValue LoH = DAG.getNode(Opcode: ISD::CLMULH, DL, VT: HalfVT, N1: LL, N2: RL);
5561 SDValue HiLoCross1 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LL, N2: RH);
5562 SDValue HiLoCross2 = DAG.getNode(Opcode: ISD::CLMUL, DL, VT: HalfVT, N1: LH, N2: RL);
5563 SDValue HiLoCross = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: HiLoCross1, N2: HiLoCross2);
5564 Hi = DAG.getNode(Opcode: ISD::XOR, DL, VT: HalfVT, N1: LoH, N2: HiLoCross);
5565}
5566
5567void DAGTypeLegalizer::ExpandIntRes_PEXT(SDNode *N, SDValue &Lo, SDValue &Hi) {
5568 SDValue Res = TLI.expandPEXT(N, DAG);
5569 SplitInteger(Op: Res, Lo, Hi);
5570}
5571
5572void DAGTypeLegalizer::ExpandIntRes_PDEP(SDNode *N, SDValue &Lo, SDValue &Hi) {
5573 SDValue Res = TLI.expandPDEP(N, DAG);
5574 SplitInteger(Op: Res, Lo, Hi);
5575}
5576
5577void DAGTypeLegalizer::ExpandIntRes_MULH(SDNode *N, SDValue &Lo, SDValue &Hi) {
5578 SDValue Res = TLI.expandMULH(Node: N, DAG);
5579 SplitInteger(Op: Res, Lo, Hi);
5580}
5581
5582void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
5583 SDValue &Hi) {
5584 EVT VT = N->getValueType(ResNo: 0);
5585 EVT HalfVT =
5586 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: N->getValueSizeInBits(ResNo: 0) / 2);
5587 SDLoc dl(N);
5588
5589 // We assume VSCALE(1) fits into a legal integer.
5590 APInt One(HalfVT.getSizeInBits(), 1);
5591 SDValue VScaleBase = DAG.getVScale(DL: dl, VT: HalfVT, MulImm: One);
5592 VScaleBase = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: VScaleBase);
5593 SDValue Res = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: VScaleBase, N2: N->getOperand(Num: 0));
5594 SplitInteger(Op: Res, Lo, Hi);
5595}
5596
5597void DAGTypeLegalizer::ExpandIntRes_READ_REGISTER(SDNode *N, SDValue &Lo,
5598 SDValue &Hi) {
5599 const Function &Fn = DAG.getMachineFunction().getFunction();
5600 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
5601 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
5602 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
5603 EVT LoVT, HiVT;
5604 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: N->getValueType(ResNo: 0));
5605 Lo = DAG.getPOISON(VT: LoVT);
5606 Hi = DAG.getPOISON(VT: HiVT);
5607}
5608
5609void DAGTypeLegalizer::ExpandIntRes_CTTZ_ELTS(SDNode *N, SDValue &Lo,
5610 SDValue &Hi) {
5611 // Assume that the maximum number of vector elements fits in getVectorIdxTy
5612 // and expand to that.
5613 EVT VT = N->getSimpleValueType(ResNo: 0);
5614 EVT IdxVT = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
5615 assert(IdxVT.bitsLT(VT) &&
5616 "VectorIdxTy should be smaller than type to be expanded?");
5617
5618 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: IdxVT, Operand: N->getOperand(Num: 0));
5619 Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: SDLoc(N), VT, Operand: Res);
5620 SplitInteger(Op: Res, Lo, Hi);
5621}
5622
5623//===----------------------------------------------------------------------===//
5624// Integer Operand Expansion
5625//===----------------------------------------------------------------------===//
5626
5627/// ExpandIntegerOperand - This method is called when the specified operand of
5628/// the specified node is found to need expansion. At this point, all of the
5629/// result types of the node are known to be legal, but other operands of the
5630/// node may need promotion or expansion as well as the specified one.
5631bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
5632 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG));
5633 SDValue Res = SDValue();
5634
5635 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false))
5636 return false;
5637
5638 switch (N->getOpcode()) {
5639 default:
5640 #ifndef NDEBUG
5641 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
5642 N->dump(&DAG); dbgs() << "\n";
5643 #endif
5644 report_fatal_error(reason: "Do not know how to expand this operator's operand!");
5645
5646 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
5647 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
5648 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
5649 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
5650 case ISD::FAKE_USE:
5651 Res = ExpandOp_FAKE_USE(N);
5652 break;
5653 case ISD::LOOP_DEPENDENCE_RAW_MASK:
5654 case ISD::LOOP_DEPENDENCE_WAR_MASK:
5655 Res = TLI.expandLoopDependenceMask(N, DAG);
5656 break;
5657 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
5658 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
5659 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
5660 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
5661 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
5662 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
5663 case ISD::STRICT_SINT_TO_FP:
5664 case ISD::SINT_TO_FP:
5665 case ISD::STRICT_UINT_TO_FP:
5666 case ISD::UINT_TO_FP: Res = ExpandIntOp_XINT_TO_FP(N); break;
5667 case ISD::STORE: Res = ExpandIntOp_STORE(N: cast<StoreSDNode>(Val: N), OpNo); break;
5668 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
5669
5670 case ISD::SHL:
5671 case ISD::SRA:
5672 case ISD::SRL:
5673 case ISD::ROTL:
5674 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
5675 case ISD::RETURNADDR:
5676 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
5677
5678 case ISD::SCMP:
5679 case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
5680
5681 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
5682 case ISD::STACKMAP:
5683 Res = ExpandIntOp_STACKMAP(N, OpNo);
5684 break;
5685 case ISD::PATCHPOINT:
5686 Res = ExpandIntOp_PATCHPOINT(N, OpNo);
5687 break;
5688 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
5689 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
5690 Res = ExpandIntOp_VP_STRIDED(N, OpNo);
5691 break;
5692 case ISD::WRITE_REGISTER:
5693 Res = ExpandIntOp_WRITE_REGISTER(N, OpNo);
5694 break;
5695 }
5696
5697 // If the result is null, the sub-method took care of registering results etc.
5698 if (!Res.getNode()) return false;
5699
5700 // If the result is N, the sub-method updated N in place. Tell the legalizer
5701 // core about this.
5702 if (Res.getNode() == N)
5703 return true;
5704
5705 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
5706 "Invalid operand expansion");
5707
5708 ReplaceValueWith(From: SDValue(N, 0), To: Res);
5709 return false;
5710}
5711
5712/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
5713/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
5714void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
5715 SDValue &NewRHS,
5716 ISD::CondCode &CCCode,
5717 const SDLoc &dl) {
5718 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5719 GetExpandedInteger(Op: NewLHS, Lo&: LHSLo, Hi&: LHSHi);
5720 GetExpandedInteger(Op: NewRHS, Lo&: RHSLo, Hi&: RHSHi);
5721
5722 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
5723 if (RHSLo == RHSHi && isAllOnesConstant(V: RHSLo)) {
5724 // Equality comparison to -1.
5725 NewLHS = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: LHSHi);
5726 NewRHS = RHSLo;
5727 return;
5728 }
5729
5730 NewLHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: RHSLo);
5731 NewRHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSHi, N2: RHSHi);
5732 NewLHS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NewLHS.getValueType(), N1: NewLHS, N2: NewRHS);
5733 NewRHS = DAG.getConstant(Val: 0, DL: dl, VT: NewLHS.getValueType());
5734 return;
5735 }
5736
5737 // If this is a comparison of the sign bit, just look at the top part.
5738 // X > -1, x < 0
5739 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Val&: NewRHS))
5740 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0
5741 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1
5742 NewLHS = LHSHi;
5743 NewRHS = RHSHi;
5744 return;
5745 }
5746
5747 // FIXME: This generated code sucks.
5748 ISD::CondCode LowCC;
5749 switch (CCCode) {
5750 default: llvm_unreachable("Unknown integer setcc!");
5751 case ISD::SETLT:
5752 case ISD::SETULT: LowCC = ISD::SETULT; break;
5753 case ISD::SETGT:
5754 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5755 case ISD::SETLE:
5756 case ISD::SETULE: LowCC = ISD::SETULE; break;
5757 case ISD::SETGE:
5758 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5759 }
5760
5761 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
5762 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
5763 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
5764
5765 // NOTE: on targets without efficient SELECT of bools, we can always use
5766 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5767 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
5768 nullptr);
5769 SDValue LoCmp, HiCmp;
5770 if (TLI.isTypeLegal(VT: LHSLo.getValueType()))
5771 LoCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSLo.getValueType()), N0: LHSLo,
5772 N1: RHSLo, Cond: LowCC, foldBooleans: false, DCI&: DagCombineInfo, dl);
5773 if (!LoCmp.getNode())
5774 LoCmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LHSLo.getValueType()), LHS: LHSLo,
5775 RHS: RHSLo, Cond: LowCC);
5776 if (TLI.isTypeLegal(VT: LHSHi.getValueType()))
5777 HiCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSHi.getValueType()), N0: LHSHi,
5778 N1: RHSHi, Cond: CCCode, foldBooleans: false, DCI&: DagCombineInfo, dl);
5779 if (!HiCmp.getNode())
5780 HiCmp =
5781 DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: getSetCCResultType(VT: LHSHi.getValueType()),
5782 N1: LHSHi, N2: RHSHi, N3: DAG.getCondCode(Cond: CCCode));
5783
5784 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(Val: LoCmp.getNode());
5785 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(Val: HiCmp.getNode());
5786
5787 bool EqAllowed = ISD::isTrueWhenEqual(Cond: CCCode);
5788
5789 // FIXME: Is the HiCmpC->isOne() here correct for
5790 // ZeroOrNegativeOneBooleanContent.
5791 if ((EqAllowed && (HiCmpC && HiCmpC->isZero())) ||
5792 (!EqAllowed &&
5793 ((HiCmpC && HiCmpC->isOne()) || (LoCmpC && LoCmpC->isZero())))) {
5794 // For LE / GE, if high part is known false, ignore the low part.
5795 // For LT / GT: if low part is known false, return the high part.
5796 // if high part is known true, ignore the low part.
5797 NewLHS = HiCmp;
5798 NewRHS = SDValue();
5799 return;
5800 }
5801
5802 if (LHSHi == RHSHi) {
5803 // Comparing the low bits is enough.
5804 NewLHS = LoCmp;
5805 NewRHS = SDValue();
5806 return;
5807 }
5808
5809 // Lower with SETCCCARRY if the target supports it.
5810 EVT HiVT = LHSHi.getValueType();
5811 EVT ExpandVT = TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: HiVT);
5812 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(Op: ISD::SETCCCARRY, VT: ExpandVT);
5813
5814 // FIXME: Make all targets support this, then remove the other lowering.
5815 if (HasSETCCCARRY) {
5816 // SETCCCARRY can detect < and >= directly. For > and <=, flip
5817 // operands and condition code.
5818 bool FlipOperands = false;
5819 switch (CCCode) {
5820 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
5821 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
5822 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
5823 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
5824 default: break;
5825 }
5826 if (FlipOperands) {
5827 std::swap(a&: LHSLo, b&: RHSLo);
5828 std::swap(a&: LHSHi, b&: RHSHi);
5829 }
5830 // Perform a wide subtraction, feeding the carry from the low part into
5831 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
5832 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
5833 // zero or positive iff LHS >= RHS.
5834 EVT LoVT = LHSLo.getValueType();
5835 SDVTList VTList = DAG.getVTList(VT1: LoVT, VT2: getSetCCResultType(VT: LoVT));
5836 SDValue LowCmp = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: LHSLo, N2: RHSLo);
5837 SDValue Res = DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: getSetCCResultType(VT: HiVT),
5838 N1: LHSHi, N2: RHSHi, N3: LowCmp.getValue(R: 1),
5839 N4: DAG.getCondCode(Cond: CCCode));
5840 NewLHS = Res;
5841 NewRHS = SDValue();
5842 return;
5843 }
5844
5845 NewLHS = TLI.SimplifySetCC(VT: getSetCCResultType(VT: HiVT), N0: LHSHi, N1: RHSHi, Cond: ISD::SETEQ,
5846 foldBooleans: false, DCI&: DagCombineInfo, dl);
5847 if (!NewLHS.getNode())
5848 NewLHS =
5849 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: HiVT), LHS: LHSHi, RHS: RHSHi, Cond: ISD::SETEQ);
5850 NewLHS = DAG.getSelect(DL: dl, VT: LoCmp.getValueType(), Cond: NewLHS, LHS: LoCmp, RHS: HiCmp);
5851 NewRHS = SDValue();
5852}
5853
5854SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
5855 SDValue NewLHS = N->getOperand(Num: 2), NewRHS = N->getOperand(Num: 3);
5856 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get();
5857 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5858
5859 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5860 // against zero to select between true and false values.
5861 if (!NewRHS.getNode()) {
5862 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5863 CCCode = ISD::SETNE;
5864 }
5865
5866 // Update N to have the operands specified.
5867 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
5868 Op2: DAG.getCondCode(Cond: CCCode), Op3: NewLHS, Op4: NewRHS,
5869 Op5: N->getOperand(Num: 4)), 0);
5870}
5871
5872SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
5873 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5874 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
5875 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5876
5877 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5878 // against zero to select between true and false values.
5879 if (!NewRHS.getNode()) {
5880 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5881 CCCode = ISD::SETNE;
5882 }
5883
5884 // Update N to have the operands specified.
5885 return SDValue(DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS,
5886 Op3: N->getOperand(Num: 2), Op4: N->getOperand(Num: 3),
5887 Op5: DAG.getCondCode(Cond: CCCode)), 0);
5888}
5889
5890SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
5891 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5892 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
5893 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5894
5895 // If ExpandSetCCOperands returned a scalar, use it.
5896 if (!NewRHS.getNode()) {
5897 assert(NewLHS.getValueType() == N->getValueType(0) &&
5898 "Unexpected setcc expansion!");
5899 return NewLHS;
5900 }
5901
5902 // Otherwise, update N to have the operands specified.
5903 return SDValue(
5904 DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS, Op3: DAG.getCondCode(Cond: CCCode)), 0);
5905}
5906
5907SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
5908 SDValue LHS = N->getOperand(Num: 0);
5909 SDValue RHS = N->getOperand(Num: 1);
5910 SDValue Carry = N->getOperand(Num: 2);
5911 SDValue Cond = N->getOperand(Num: 3);
5912 SDLoc dl = SDLoc(N);
5913
5914 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5915 GetExpandedInteger(Op: LHS, Lo&: LHSLo, Hi&: LHSHi);
5916 GetExpandedInteger(Op: RHS, Lo&: RHSLo, Hi&: RHSHi);
5917
5918 // Expand to a USUBO_CARRY for the low part and a SETCCCARRY for the high.
5919 SDVTList VTList = DAG.getVTList(VT1: LHSLo.getValueType(), VT2: Carry.getValueType());
5920 SDValue LowCmp =
5921 DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: LHSLo, N2: RHSLo, N3: Carry);
5922 return DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: N->getValueType(ResNo: 0), N1: LHSHi, N2: RHSHi,
5923 N3: LowCmp.getValue(R: 1), N4: Cond);
5924}
5925
5926SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
5927 // Split the operand and replace with SPLAT_VECTOR_PARTS.
5928 SDValue Lo, Hi;
5929 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5930 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Lo,
5931 N2: Hi);
5932}
5933
5934SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
5935 // The value being shifted is legal, but the shift amount is too big.
5936 // It follows that either the result of the shift is undefined, or the
5937 // upper half of the shift amount is zero. Just use the lower half.
5938 SDValue Lo, Hi;
5939 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo, Hi);
5940 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Lo), 0);
5941}
5942
5943SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
5944 return TLI.expandCMP(Node: N, DAG);
5945}
5946
5947SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
5948 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
5949 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
5950 // constant to valid type.
5951 SDValue Lo, Hi;
5952 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5953 return SDValue(DAG.UpdateNodeOperands(N, Op: Lo), 0);
5954}
5955
5956SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) {
5957 bool IsStrict = N->isStrictFPOpcode();
5958 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
5959 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
5960 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
5961 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
5962 EVT DstVT = N->getValueType(ResNo: 0);
5963 RTLIB::Libcall LC = IsSigned ? RTLIB::getSINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT)
5964 : RTLIB::getUINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT);
5965 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
5966 "Don't know how to expand this XINT_TO_FP!");
5967 TargetLowering::MakeLibCallOptions CallOptions;
5968 CallOptions.setIsSigned(true);
5969 std::pair<SDValue, SDValue> Tmp =
5970 TLI.makeLibCall(DAG, LC, RetVT: DstVT, Ops: Op, CallOptions, dl: SDLoc(N), Chain);
5971
5972 if (!IsStrict)
5973 return Tmp.first;
5974
5975 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
5976 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
5977 return SDValue();
5978}
5979
5980SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
5981 assert(!N->isAtomic() && "Should have been a ATOMIC_STORE?");
5982
5983 if (ISD::isNormalStore(N))
5984 return ExpandOp_NormalStore(N, OpNo);
5985
5986 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
5987 assert(OpNo == 1 && "Can only expand the stored value so far");
5988
5989 EVT VT = N->getOperand(Num: 1).getValueType();
5990 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5991 SDValue Ch = N->getChain();
5992 SDValue Ptr = N->getBasePtr();
5993 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
5994 AAMDNodes AAInfo = N->getAAInfo();
5995 SDLoc dl(N);
5996 SDValue Lo, Hi;
5997
5998 assert(NVT.isByteSized() && "Expanded type not byte sized!");
5999
6000 if (N->getMemoryVT().bitsLE(VT: NVT)) {
6001 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6002 return DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(),
6003 SVT: N->getMemoryVT(), Alignment: N->getBaseAlign(), MMOFlags,
6004 Metadata: AAInfo);
6005 }
6006
6007 if (DAG.getDataLayout().isLittleEndian()) {
6008 // Little-endian - low bits are at low addresses.
6009 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6010
6011 Lo = DAG.getStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
6012 MMOFlags, Metadata: AAInfo);
6013
6014 unsigned ExcessBits =
6015 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
6016 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
6017
6018 // Increment the pointer to the other half.
6019 unsigned IncrementSize = NVT.getSizeInBits()/8;
6020 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6021 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr,
6022 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6023 SVT: NEVT, Alignment: N->getBaseAlign(), MMOFlags, Metadata: AAInfo);
6024 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6025 }
6026
6027 // Big-endian - high bits are at low addresses. Favor aligned stores at
6028 // the cost of some bit-fiddling.
6029 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
6030
6031 EVT ExtVT = N->getMemoryVT();
6032 unsigned EBytes = ExtVT.getStoreSize();
6033 unsigned IncrementSize = NVT.getSizeInBits()/8;
6034 unsigned ExcessBits = (EBytes - IncrementSize)*8;
6035 EVT HiVT = EVT::getIntegerVT(Context&: *DAG.getContext(),
6036 BitWidth: ExtVT.getSizeInBits() - ExcessBits);
6037
6038 if (ExcessBits < NVT.getSizeInBits()) {
6039 // Transfer high bits from the top of Lo to the bottom of Hi.
6040 Hi = DAG.getNode(
6041 Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
6042 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - ExcessBits, VT: NVT, DL: dl));
6043 Hi = DAG.getNode(
6044 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Hi,
6045 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Lo,
6046 N2: DAG.getShiftAmountConstant(Val: ExcessBits, VT: NVT, DL: dl)));
6047 }
6048
6049 // Store both the high bits and maybe some of the low bits.
6050 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr, PtrInfo: N->getPointerInfo(), SVT: HiVT,
6051 Alignment: N->getBaseAlign(), MMOFlags, Metadata: AAInfo);
6052
6053 // Increment the pointer to the other half.
6054 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
6055 // Store the lowest ExcessBits bits in the second half.
6056 Lo = DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr,
6057 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
6058 SVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
6059 Alignment: N->getBaseAlign(), MMOFlags, Metadata: AAInfo);
6060 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
6061}
6062
6063SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
6064 SDValue InL, InH;
6065 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
6066 // Just truncate the low part of the source.
6067 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: InL);
6068}
6069
6070SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
6071 SDLoc dl(N);
6072 SDValue Swap =
6073 DAG.getAtomic(Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(),
6074 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 2), Val: N->getOperand(Num: 1),
6075 MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
6076 return Swap.getValue(R: 1);
6077}
6078
6079SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
6080 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
6081 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
6082
6083 SDValue Hi; // The upper half is dropped out.
6084 SmallVector<SDValue, 8> NewOps(N->ops());
6085 GetExpandedInteger(Op: NewOps[OpNo], Lo&: NewOps[OpNo], Hi);
6086
6087 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
6088}
6089
6090SDValue DAGTypeLegalizer::ExpandIntOp_WRITE_REGISTER(SDNode *N, unsigned OpNo) {
6091 const Function &Fn = DAG.getMachineFunction().getFunction();
6092 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6093 "cannot use llvm.write_register with illegal type", Fn,
6094 N->getDebugLoc()));
6095
6096 return N->getOperand(Num: 0);
6097}
6098
6099SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
6100 SDLoc dl(N);
6101
6102 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6103 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6104 EVT OutVT = V0.getValueType();
6105
6106 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: OutVT, N1: V0, N2: V1, N3: N->getOperand(Num: 2));
6107}
6108
6109SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(SDNode *N) {
6110 SDLoc DL(N);
6111 unsigned Factor = N->getNumOperands();
6112
6113 SmallVector<SDValue, 8> Ops(Factor);
6114 for (unsigned i = 0; i != Factor; i++)
6115 Ops[i] = GetPromotedInteger(Op: N->getOperand(Num: i));
6116
6117 SmallVector<EVT, 8> ResVTs(Factor, Ops[0].getValueType());
6118 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VTs: ResVTs), Ops);
6119
6120 for (unsigned i = 0; i != Factor; i++)
6121 SetPromotedInteger(Op: SDValue(N, i), Result: Res.getValue(R: i));
6122
6123 return SDValue();
6124}
6125
6126SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
6127
6128 EVT OutVT = N->getValueType(ResNo: 0);
6129 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6130 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6131 EVT NOutVTElem = NOutVT.getVectorElementType();
6132
6133 SDLoc dl(N);
6134 SDValue BaseIdx = N->getOperand(Num: 1);
6135
6136 // TODO: We may be able to use this for types other than scalable
6137 // vectors and fix those tests that expect BUILD_VECTOR to be used
6138 if (OutVT.isScalableVector()) {
6139 SDValue InOp0 = N->getOperand(Num: 0);
6140 EVT InVT = InOp0.getValueType();
6141
6142 // Try and extract from a smaller type so that it eventually falls
6143 // into the promotion code below.
6144 if (getTypeAction(VT: InVT) == TargetLowering::TypeSplitVector ||
6145 getTypeAction(VT: InVT) == TargetLowering::TypeLegal) {
6146 EVT NInVT = InVT.getHalfNumVectorElementsVT(Context&: *DAG.getContext());
6147 unsigned NElts = NInVT.getVectorMinNumElements();
6148 uint64_t IdxVal = BaseIdx->getAsZExtVal();
6149
6150 SDValue Step1 = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NInVT, N1: InOp0,
6151 N2: DAG.getConstant(Val: alignDown(Value: IdxVal, Align: NElts), DL: dl,
6152 VT: BaseIdx.getValueType()));
6153 SDValue Step2 = DAG.getNode(
6154 Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Step1,
6155 N2: DAG.getConstant(Val: IdxVal % NElts, DL: dl, VT: BaseIdx.getValueType()));
6156 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Step2);
6157 }
6158
6159 // Try and extract from a widened type.
6160 if (getTypeAction(VT: InVT) == TargetLowering::TypeWidenVector) {
6161 SDValue Ops[] = {GetWidenedVector(Op: InOp0), BaseIdx};
6162 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: OutVT, Ops);
6163 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6164 }
6165
6166 // Promote operands and see if this is handled by target lowering,
6167 // Otherwise, use the BUILD_VECTOR approach below
6168 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
6169 // Collect the (promoted) operands
6170 SDValue Ops[] = { GetPromotedInteger(Op: InOp0), BaseIdx };
6171
6172 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
6173 assert(PromEltVT.bitsLE(NOutVTElem) &&
6174 "Promoted operand has an element type greater than result");
6175
6176 EVT ExtVT = NOutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: PromEltVT);
6177 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: ExtVT, Ops);
6178 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6179 }
6180 }
6181
6182 if (OutVT.isScalableVector())
6183 report_fatal_error(reason: "Unable to promote scalable types using BUILD_VECTOR");
6184
6185 SDValue InOp0 = N->getOperand(Num: 0);
6186 if (getTypeAction(VT: InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
6187 InOp0 = GetPromotedInteger(Op: InOp0);
6188
6189 EVT InVT = InOp0.getValueType();
6190 EVT InSVT = InVT.getVectorElementType();
6191
6192 unsigned OutNumElems = OutVT.getVectorNumElements();
6193 SmallVector<SDValue, 8> Ops;
6194 Ops.reserve(N: OutNumElems);
6195 for (unsigned i = 0; i != OutNumElems; ++i) {
6196 // Extract the element from the original vector.
6197 SDValue Index = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: BaseIdx.getValueType(), N1: BaseIdx,
6198 N2: DAG.getConstant(Val: i, DL: dl, VT: BaseIdx.getValueType()));
6199 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: InSVT,
6200 N1: N->getOperand(Num: 0), N2: Index);
6201 SDValue Op = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NOutVTElem);
6202 // Insert the converted element to the new vector.
6203 Ops.push_back(Elt: Op);
6204 }
6205
6206 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6207}
6208
6209SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
6210 EVT OutVT = N->getValueType(ResNo: 0);
6211 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6212 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6213
6214 SDLoc dl(N);
6215 SDValue Vec = N->getOperand(Num: 0);
6216 SDValue SubVec = N->getOperand(Num: 1);
6217 SDValue Idx = N->getOperand(Num: 2);
6218
6219 EVT SubVecVT = SubVec.getValueType();
6220 EVT NSubVT =
6221 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NOutVT.getVectorElementType(),
6222 EC: SubVecVT.getVectorElementCount());
6223
6224 Vec = GetPromotedInteger(Op: Vec);
6225 SubVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NSubVT, Operand: SubVec);
6226
6227 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: NOutVT, N1: Vec, N2: SubVec, N3: Idx);
6228}
6229
6230SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
6231 SDLoc dl(N);
6232
6233 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6234 EVT OutVT = V0.getValueType();
6235
6236 return DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL: dl, VT: OutVT, Operand: V0);
6237}
6238
6239SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
6240 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(Val: N);
6241 EVT VT = N->getValueType(ResNo: 0);
6242 SDLoc dl(N);
6243
6244 ArrayRef<int> NewMask = SV->getMask().slice(N: 0, M: VT.getVectorNumElements());
6245
6246 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6247 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6248 EVT OutVT = V0.getValueType();
6249
6250 return DAG.getVectorShuffle(VT: OutVT, dl, N1: V0, N2: V1, Mask: NewMask);
6251}
6252
6253SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
6254 EVT OutVT = N->getValueType(ResNo: 0);
6255 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6256 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6257 unsigned NumElems = N->getNumOperands();
6258 EVT NOutVTElem = NOutVT.getVectorElementType();
6259 TargetLoweringBase::BooleanContent NOutBoolType = TLI.getBooleanContents(Type: NOutVT);
6260 unsigned NOutExtOpc = TargetLowering::getExtendForContent(Content: NOutBoolType);
6261 SDLoc dl(N);
6262
6263 SmallVector<SDValue, 8> Ops;
6264 Ops.reserve(N: NumElems);
6265 for (unsigned i = 0; i != NumElems; ++i) {
6266 SDValue Op = N->getOperand(Num: i);
6267 EVT OpVT = Op.getValueType();
6268 // BUILD_VECTOR integer operand types are allowed to be larger than the
6269 // result's element type. This may still be true after the promotion. For
6270 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
6271 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
6272 if (OpVT.bitsLT(VT: NOutVTElem)) {
6273 unsigned ExtOpc = ISD::ANY_EXTEND;
6274 // Attempt to extend constant bool vectors to match target's BooleanContent.
6275 // While not necessary, this improves chances of the constant correctly
6276 // folding with compare results (e.g. for NOT patterns).
6277 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant)
6278 ExtOpc = NOutExtOpc;
6279 Op = DAG.getNode(Opcode: ExtOpc, DL: dl, VT: NOutVTElem, Operand: Op);
6280 }
6281 Ops.push_back(Elt: Op);
6282 }
6283
6284 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6285}
6286
6287SDValue DAGTypeLegalizer::PromoteIntRes_ScalarOp(SDNode *N) {
6288
6289 SDLoc dl(N);
6290
6291 assert(!N->getOperand(0).getValueType().isVector() &&
6292 "Input must be a scalar");
6293
6294 EVT OutVT = N->getValueType(ResNo: 0);
6295 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6296 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6297 EVT NOutElemVT = NOutVT.getVectorElementType();
6298
6299 SDValue Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutElemVT, Operand: N->getOperand(Num: 0));
6300 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NOutVT, Operand: Op);
6301}
6302
6303SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
6304 SDLoc dl(N);
6305 EVT OutVT = N->getValueType(ResNo: 0);
6306 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6307 assert(NOutVT.isScalableVector() &&
6308 "Type must be promoted to a scalable vector type");
6309 const APInt &StepVal = N->getConstantOperandAPInt(Num: 0);
6310 return DAG.getStepVector(DL: dl, ResVT: NOutVT,
6311 StepVal: StepVal.sext(width: NOutVT.getScalarSizeInBits()));
6312}
6313
6314SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
6315 SDLoc dl(N);
6316
6317 EVT OutVT = N->getValueType(ResNo: 0);
6318 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6319 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6320
6321 unsigned NumOperands = N->getNumOperands();
6322 unsigned NumOutElem = NOutVT.getVectorMinNumElements();
6323 EVT OutElemTy = NOutVT.getVectorElementType();
6324 if (OutVT.isScalableVector()) {
6325 // Find the largest promoted element type for each of the operands.
6326 SDUse *MaxSizedValue = std::max_element(
6327 first: N->op_begin(), last: N->op_end(), comp: [](const SDValue &A, const SDValue &B) {
6328 EVT AVT = A.getValueType().getVectorElementType();
6329 EVT BVT = B.getValueType().getVectorElementType();
6330 return AVT.getScalarSizeInBits() < BVT.getScalarSizeInBits();
6331 });
6332 EVT MaxElementVT = MaxSizedValue->getValueType().getVectorElementType();
6333
6334 // Then promote all vectors to the largest element type.
6335 SmallVector<SDValue, 8> Ops;
6336 for (unsigned I = 0; I < NumOperands; ++I) {
6337 SDValue Op = N->getOperand(Num: I);
6338 EVT OpVT = Op.getValueType();
6339 if (getTypeAction(VT: OpVT) == TargetLowering::TypePromoteInteger)
6340 Op = GetPromotedInteger(Op);
6341 else
6342 assert(getTypeAction(OpVT) == TargetLowering::TypeLegal &&
6343 "Unhandled legalization type");
6344
6345 if (OpVT.getVectorElementType().getScalarSizeInBits() <
6346 MaxElementVT.getScalarSizeInBits())
6347 Op = DAG.getAnyExtOrTrunc(
6348 Op, DL: dl,
6349 VT: OpVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT));
6350 Ops.push_back(Elt: Op);
6351 }
6352
6353 // Do the CONCAT on the promoted type and finally truncate to (the promoted)
6354 // NOutVT.
6355 return DAG.getAnyExtOrTrunc(
6356 Op: DAG.getNode(
6357 Opcode: ISD::CONCAT_VECTORS, DL: dl,
6358 VT: OutVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MaxElementVT),
6359 Ops),
6360 DL: dl, VT: NOutVT);
6361 }
6362
6363 unsigned NumElem = N->getOperand(Num: 0).getValueType().getVectorNumElements();
6364 assert(NumElem * NumOperands == NumOutElem &&
6365 "Unexpected number of elements");
6366
6367 // Take the elements from the first vector.
6368 SmallVector<SDValue, 8> Ops(NumOutElem);
6369 for (unsigned i = 0; i < NumOperands; ++i) {
6370 SDValue Op = N->getOperand(Num: i);
6371 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypePromoteInteger)
6372 Op = GetPromotedInteger(Op);
6373 EVT SclrTy = Op.getValueType().getVectorElementType();
6374 assert(NumElem == Op.getValueType().getVectorNumElements() &&
6375 "Unexpected number of elements");
6376
6377 for (unsigned j = 0; j < NumElem; ++j) {
6378 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Op,
6379 N2: DAG.getVectorIdxConstant(Val: j, DL: dl));
6380 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: OutElemTy);
6381 }
6382 }
6383
6384 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6385}
6386
6387SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
6388 EVT VT = N->getValueType(ResNo: 0);
6389 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6390 assert(NVT.isVector() && "This type must be promoted to a vector type");
6391
6392 SDLoc dl(N);
6393
6394 // For operands whose TypeAction is to promote, extend the promoted node
6395 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
6396 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
6397 // type..
6398 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
6399 == TargetLowering::TypePromoteInteger) {
6400 SDValue Promoted;
6401
6402 switch(N->getOpcode()) {
6403 case ISD::SIGN_EXTEND_VECTOR_INREG:
6404 Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
6405 break;
6406 case ISD::ZERO_EXTEND_VECTOR_INREG:
6407 Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
6408 break;
6409 case ISD::ANY_EXTEND_VECTOR_INREG:
6410 Promoted = GetPromotedInteger(Op: N->getOperand(Num: 0));
6411 break;
6412 default:
6413 llvm_unreachable("Node has unexpected Opcode");
6414 }
6415 unsigned NewSize = NVT.getSizeInBits();
6416 if (Promoted.getValueType().getSizeInBits() > NewSize) {
6417 EVT ExtractVT = EVT::getVectorVT(
6418 Context&: *DAG.getContext(), VT: Promoted.getValueType().getVectorElementType(),
6419 NumElements: NewSize / Promoted.getScalarValueSizeInBits());
6420
6421 Promoted = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: ExtractVT, N1: Promoted,
6422 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
6423 }
6424 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Promoted);
6425 }
6426
6427 // Directly extend to the appropriate transform-to type.
6428 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
6429}
6430
6431SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(SDNode *N) {
6432 EVT VT = N->getValueType(ResNo: 0);
6433 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6434 return DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6435}
6436
6437SDValue DAGTypeLegalizer::PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
6438 EVT VT = N->getValueType(ResNo: 0);
6439 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6440 return DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6441}
6442
6443SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_MATCH(SDNode *N) {
6444 EVT VT = N->getValueType(ResNo: 0);
6445 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6446 SmallVector<SDValue, 3> NewOps(N->ops());
6447 NewOps[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: NVT);
6448 return DAG.getNode(Opcode: ISD::VECTOR_MATCH, DL: SDLoc(N), VT: NVT, Ops: NewOps, Flags: N->getFlags());
6449}
6450
6451SDValue DAGTypeLegalizer::PromoteIntRes_PARTIAL_REDUCE_MLA(SDNode *N) {
6452 SDLoc DL(N);
6453 EVT VT = N->getValueType(ResNo: 0);
6454 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6455 SDValue ExtAcc = GetPromotedInteger(Op: N->getOperand(Num: 0));
6456 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: ExtAcc, N2: N->getOperand(Num: 1),
6457 N3: N->getOperand(Num: 2));
6458}
6459
6460SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
6461 EVT OutVT = N->getValueType(ResNo: 0);
6462 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6463 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6464
6465 EVT NOutVTElem = NOutVT.getVectorElementType();
6466
6467 SDLoc dl(N);
6468 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6469
6470 SDValue ConvElem = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6471 VT: NOutVTElem, Operand: N->getOperand(Num: 1));
6472 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NOutVT,
6473 N1: V0, N2: ConvElem, N3: N->getOperand(Num: 2));
6474}
6475
6476SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
6477 // The VECREDUCE result size may be larger than the element size, so
6478 // we can simply change the result type.
6479 SDLoc dl(N);
6480 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6481 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Ops: N->ops());
6482}
6483
6484SDValue DAGTypeLegalizer::PromoteIntRes_VP_REDUCE(SDNode *N) {
6485 // The VP_REDUCE result size may be larger than the element size, so we can
6486 // simply change the result type. However the start value and result must be
6487 // the same.
6488 SDLoc DL(N);
6489 SDValue Start = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
6490 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: Start.getValueType(), N1: Start,
6491 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
6492}
6493
6494SDValue DAGTypeLegalizer::PromoteIntRes_PATCHPOINT(SDNode *N) {
6495 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6496 SDLoc dl(N);
6497
6498 assert(N->getNumValues() == 3 && "Expected 3 values for PATCHPOINT");
6499 SDVTList VTList = DAG.getVTList(VTs: {NVT, MVT::Other, MVT::Glue});
6500
6501 SmallVector<SDValue> Ops(N->ops());
6502 SDValue Res = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList, Ops);
6503
6504 // Replace chain and glue uses with the new patchpoint.
6505 SDValue From[] = {SDValue(N, 1), SDValue(N, 2)};
6506 SDValue To[] = {Res.getValue(R: 1), Res.getValue(R: 2)};
6507 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
6508
6509 return Res.getValue(R: 0);
6510}
6511
6512SDValue DAGTypeLegalizer::PromoteIntRes_READ_REGISTER(SDNode *N) {
6513 const Function &Fn = DAG.getMachineFunction().getFunction();
6514 Fn.getContext().diagnose(DI: DiagnosticInfoLegalizationFailure(
6515 "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
6516
6517 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6518 ReplaceValueWith(From: SDValue(N, 1), To: N->getOperand(Num: 0));
6519 return DAG.getPOISON(VT: NVT);
6520}
6521
6522SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
6523 SDLoc dl(N);
6524 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6525 SDValue V1 = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl,
6526 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
6527 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl,
6528 VT: V0->getValueType(ResNo: 0).getScalarType(), N1: V0, N2: V1);
6529
6530 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
6531 // element types. If this is the case then we need to expand the outgoing
6532 // value and not truncate it.
6533 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6534}
6535
6536SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_SUBVECTOR(SDNode *N) {
6537 SDLoc dl(N);
6538 // The result type is equal to the first input operand's type, so the
6539 // type that needs promoting must be the second source vector.
6540 SDValue V0 = N->getOperand(Num: 0);
6541 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6542 SDValue Idx = N->getOperand(Num: 2);
6543 EVT PromVT = EVT::getVectorVT(Context&: *DAG.getContext(),
6544 VT: V1.getValueType().getVectorElementType(),
6545 EC: V0.getValueType().getVectorElementCount());
6546 V0 = DAG.getAnyExtOrTrunc(Op: V0, DL: dl, VT: PromVT);
6547 SDValue Ext = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: PromVT, N1: V0, N2: V1, N3: Idx);
6548 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6549}
6550
6551// FIXME: We wouldn't need this if clang could promote short integers
6552// that are arguments to FAKE_USE.
6553SDValue DAGTypeLegalizer::PromoteIntOp_FAKE_USE(SDNode *N) {
6554 SDLoc dl(N);
6555 SDValue V0 = N->getOperand(Num: 0);
6556 SDValue V1 = N->getOperand(Num: 1);
6557 EVT InVT1 = V1.getValueType();
6558 SDValue VPromoted =
6559 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6560 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT1), Operand: V1);
6561 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: N->getValueType(ResNo: 0), N1: V0, N2: VPromoted);
6562}
6563
6564SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
6565 SDLoc dl(N);
6566 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6567 MVT InVT = V0.getValueType().getSimpleVT();
6568 MVT OutVT = MVT::getVectorVT(VT: InVT.getVectorElementType(),
6569 NumElements: N->getValueType(ResNo: 0).getVectorNumElements());
6570 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: V0, N2: N->getOperand(Num: 1));
6571 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Ext);
6572}
6573
6574SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
6575 SDLoc dl(N);
6576
6577 EVT ResVT = N->getValueType(ResNo: 0);
6578 unsigned NumElems = N->getNumOperands();
6579
6580 if (ResVT.isScalableVector()) {
6581 SDValue ResVec = DAG.getPOISON(VT: ResVT);
6582
6583 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
6584 SDValue Op = N->getOperand(Num: OpIdx);
6585 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
6586 ResVec = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: ResVT, N1: ResVec, N2: Op,
6587 N3: DAG.getIntPtrConstant(Val: OpIdx * OpNumElts, DL: dl));
6588 }
6589
6590 return ResVec;
6591 }
6592
6593 EVT RetSclrTy = N->getValueType(ResNo: 0).getVectorElementType();
6594
6595 SmallVector<SDValue, 8> NewOps;
6596 NewOps.reserve(N: NumElems);
6597
6598 // For each incoming vector
6599 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
6600 SDValue Incoming = GetPromotedInteger(Op: N->getOperand(Num: VecIdx));
6601 EVT SclrTy = Incoming->getValueType(ResNo: 0).getVectorElementType();
6602 unsigned NumElem = Incoming->getValueType(ResNo: 0).getVectorNumElements();
6603
6604 for (unsigned i=0; i<NumElem; ++i) {
6605 // Extract element from incoming vector
6606 SDValue Ex = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Incoming,
6607 N2: DAG.getVectorIdxConstant(Val: i, DL: dl));
6608 SDValue Tr = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RetSclrTy, Operand: Ex);
6609 NewOps.push_back(Elt: Tr);
6610 }
6611 }
6612
6613 return DAG.getBuildVector(VT: N->getValueType(ResNo: 0), DL: dl, Ops: NewOps);
6614}
6615
6616SDValue DAGTypeLegalizer::ExpandIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
6617 assert(OpNo > 1);
6618 SDValue Op = N->getOperand(Num: OpNo);
6619
6620 // FIXME: Non-constant operands are not yet handled:
6621 // - https://github.com/llvm/llvm-project/issues/26431
6622 // - https://github.com/llvm/llvm-project/issues/55957
6623 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6624 if (!CN)
6625 return SDValue();
6626
6627 // Copy operands before the one being expanded.
6628 SmallVector<SDValue> NewOps;
6629 for (unsigned I = 0; I < OpNo; I++)
6630 NewOps.push_back(Elt: N->getOperand(Num: I));
6631
6632 EVT Ty = Op.getValueType();
6633 SDLoc DL = SDLoc(N);
6634 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6635 NewOps.push_back(
6636 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6637 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6638 } else {
6639 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6640 return SDValue();
6641 }
6642
6643 // Copy remaining operands.
6644 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6645 NewOps.push_back(Elt: N->getOperand(Num: I));
6646
6647 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6648
6649 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6650 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6651
6652 return SDValue(); // Signal that we have replaced the node already.
6653}
6654
6655SDValue DAGTypeLegalizer::ExpandIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
6656 assert(OpNo >= 7);
6657 SDValue Op = N->getOperand(Num: OpNo);
6658
6659 // FIXME: Non-constant operands are not yet handled:
6660 // - https://github.com/llvm/llvm-project/issues/26431
6661 // - https://github.com/llvm/llvm-project/issues/55957
6662 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6663 if (!CN)
6664 return SDValue();
6665
6666 // Copy operands before the one being expanded.
6667 SmallVector<SDValue> NewOps;
6668 for (unsigned I = 0; I < OpNo; I++)
6669 NewOps.push_back(Elt: N->getOperand(Num: I));
6670
6671 EVT Ty = Op.getValueType();
6672 SDLoc DL = SDLoc(N);
6673 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6674 NewOps.push_back(
6675 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6676 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6677 } else {
6678 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6679 return SDValue();
6680 }
6681
6682 // Copy remaining operands.
6683 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6684 NewOps.push_back(Elt: N->getOperand(Num: I));
6685
6686 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6687
6688 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6689 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6690
6691 return SDValue(); // Signal that we have replaced the node already.
6692}
6693