1//===-------- LegalizeTypesGeneric.cpp - Generic type legalization --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements generic type expansion and splitting for LegalizeTypes.
10// The routines here perform legalization when the details of the type (such as
11// whether it is an integer or a float) do not matter.
12// Expansion is the act of changing a computation in an illegal type to be a
13// computation in two identical registers of a smaller type. The Lo/Hi part
14// is required to be stored first in memory on little/big-endian machines.
15// Splitting is the act of changing a computation in an illegal type to be a
16// computation in two not necessarily identical registers of a smaller type.
17// There are no requirements on how the type is represented in memory.
18//
19//===----------------------------------------------------------------------===//
20
21#include "LegalizeTypes.h"
22#include "llvm/IR/DataLayout.h"
23using namespace llvm;
24
25#define DEBUG_TYPE "legalize-types"
26
27//===----------------------------------------------------------------------===//
28// Generic Result Expansion.
29//===----------------------------------------------------------------------===//
30
31// These routines assume that the Lo/Hi part is stored first in memory on
32// little/big-endian machines, followed by the Hi/Lo part. This means that
33// they cannot be used as is on vectors, for which Lo is always stored first.
34void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
35 SDValue &Lo, SDValue &Hi) {
36 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
37 GetExpandedOp(Op, Lo, Hi);
38}
39
40void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
41 EVT OutVT = N->getValueType(ResNo: 0);
42 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
43 SDValue InOp = N->getOperand(Num: 0);
44 EVT InVT = InOp.getValueType();
45 SDLoc dl(N);
46
47 // Handle some special cases efficiently.
48 switch (getTypeAction(VT: InVT)) {
49 case TargetLowering::TypeLegal:
50 case TargetLowering::TypePromoteInteger:
51 break;
52 case TargetLowering::TypeSoftPromoteHalf:
53 llvm_unreachable("Bitcast of a promotion-needing float should never need"
54 "expansion");
55 case TargetLowering::TypeSoftenFloat:
56 SplitInteger(Op: GetSoftenedFloat(Op: InOp), Lo, Hi);
57 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
58 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
59 return;
60 case TargetLowering::TypeExpandInteger:
61 case TargetLowering::TypeExpandFloat: {
62 auto &DL = DAG.getDataLayout();
63 // Convert the expanded pieces of the input.
64 GetExpandedOp(Op: InOp, Lo, Hi);
65 if (TLI.hasBigEndianPartOrdering(VT: InVT, DL) !=
66 TLI.hasBigEndianPartOrdering(VT: OutVT, DL))
67 std::swap(a&: Lo, b&: Hi);
68 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
69 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
70 return;
71 }
72 case TargetLowering::TypeSplitVector:
73 GetSplitVector(Op: InOp, Lo, Hi);
74 if (TLI.hasBigEndianPartOrdering(VT: OutVT, DL: DAG.getDataLayout()))
75 std::swap(a&: Lo, b&: Hi);
76 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
77 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
78 return;
79 case TargetLowering::TypeScalarizeVector:
80 // Convert the element instead.
81 SplitInteger(Op: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)), Lo, Hi);
82 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
83 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
84 return;
85 case TargetLowering::TypeScalarizeScalableVector:
86 report_fatal_error(reason: "Scalarization of scalable vectors is not supported.");
87 case TargetLowering::TypeWidenVector: {
88 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
89 InOp = GetWidenedVector(Op: InOp);
90 EVT LoVT, HiVT;
91 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: InVT);
92 std::tie(args&: Lo, args&: Hi) = DAG.SplitVector(N: InOp, DL: dl, LoVT, HiVT);
93 if (TLI.hasBigEndianPartOrdering(VT: OutVT, DL: DAG.getDataLayout()))
94 std::swap(a&: Lo, b&: Hi);
95 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
96 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
97 return;
98 }
99 }
100
101 if (InVT.isVector() && OutVT.isInteger()) {
102 // Handle cases like i64 = BITCAST v1i64 on x86, where the operand
103 // is legal but the result is not.
104 unsigned NumElems = 2;
105 EVT ElemVT = NOutVT;
106 EVT NVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: ElemVT, NumElements: NumElems);
107
108 // If <ElemVT * N> is not a legal type, try <ElemVT/2 * (N*2)>.
109 while (!isTypeLegal(VT: NVT)) {
110 unsigned NewSizeInBits = ElemVT.getSizeInBits() / 2;
111 // If the element size is smaller than byte, bail.
112 if (NewSizeInBits < 8)
113 break;
114 NumElems *= 2;
115 ElemVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NewSizeInBits);
116 NVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: ElemVT, NumElements: NumElems);
117 }
118
119 if (isTypeLegal(VT: NVT)) {
120 SDValue CastInOp = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NVT, Operand: InOp);
121
122 SmallVector<SDValue, 8> Vals;
123 for (unsigned i = 0; i < NumElems; ++i)
124 Vals.push_back(Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: ElemVT,
125 N1: CastInOp, N2: DAG.getVectorIdxConstant(Val: i, DL: dl)));
126
127 // Build Lo, Hi pair by pairing extracted elements if needed.
128 unsigned Slot = 0;
129 for (unsigned e = Vals.size(); e - Slot > 2; Slot += 2, e += 1) {
130 // Each iteration will BUILD_PAIR two nodes and append the result until
131 // there are only two nodes left, i.e. Lo and Hi.
132 SDValue LHS = Vals[Slot];
133 SDValue RHS = Vals[Slot + 1];
134
135 if (DAG.getDataLayout().isBigEndian())
136 std::swap(a&: LHS, b&: RHS);
137
138 Vals.push_back(Elt: DAG.getNode(
139 Opcode: ISD::BUILD_PAIR, DL: dl,
140 VT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: LHS.getValueSizeInBits() << 1),
141 N1: LHS, N2: RHS));
142 }
143 Lo = Vals[Slot++];
144 Hi = Vals[Slot++];
145
146 if (DAG.getDataLayout().isBigEndian())
147 std::swap(a&: Lo, b&: Hi);
148
149 return;
150 }
151 }
152
153 // Lower the bit-convert to a store/load from the stack.
154 assert(NOutVT.isByteSized() && "Expanded type not byte sized!");
155
156 // Create the stack frame object. Make sure it is aligned for both
157 // the source and expanded destination types.
158
159 // In cases where the vector is illegal it will be broken down into parts
160 // and stored in parts - we should use the alignment for the smallest part.
161 Align InAlign = DAG.getReducedAlign(VT: InVT, /*UseABI=*/false);
162 Align NOutAlign = DAG.getReducedAlign(VT: NOutVT, /*UseABI=*/false);
163 Align Align = std::max(a: InAlign, b: NOutAlign);
164 SDValue StackPtr = DAG.CreateStackTemporary(Bytes: InVT.getStoreSize(), Alignment: Align);
165 int SPFI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
166 MachinePointerInfo PtrInfo =
167 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
168
169 // Emit a store to the stack slot.
170 SDValue Store = DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: InOp, Ptr: StackPtr, PtrInfo);
171
172 // Load the first half from the stack slot.
173 Lo = DAG.getLoad(VT: NOutVT, dl, Chain: Store, Ptr: StackPtr, PtrInfo, Alignment: NOutAlign);
174
175 // Increment the pointer to the other half.
176 unsigned IncrementSize = NOutVT.getSizeInBits() / 8;
177 StackPtr =
178 DAG.getMemBasePlusOffset(Base: StackPtr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
179
180 // Load the second half from the stack slot.
181 Hi = DAG.getLoad(VT: NOutVT, dl, Chain: Store, Ptr: StackPtr,
182 PtrInfo: PtrInfo.getWithOffset(O: IncrementSize), Alignment: NOutAlign);
183
184 // Handle endianness of the load.
185 if (TLI.hasBigEndianPartOrdering(VT: OutVT, DL: DAG.getDataLayout()))
186 std::swap(a&: Lo, b&: Hi);
187}
188
189void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
190 SDValue &Hi) {
191 // Return the operands.
192 Lo = N->getOperand(Num: 0);
193 Hi = N->getOperand(Num: 1);
194}
195
196void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
197 SDValue &Hi) {
198 GetExpandedOp(Op: N->getOperand(Num: 0), Lo, Hi);
199 SDValue Part = N->getConstantOperandVal(Num: 1) ? Hi : Lo;
200
201 assert(Part.getValueType() == N->getValueType(0) &&
202 "Type twice as big as expanded type not itself expanded!");
203
204 GetPairElements(Pair: Part, Lo, Hi);
205}
206
207void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
208 SDValue &Hi) {
209 SDValue OldVec = N->getOperand(Num: 0);
210 ElementCount OldEltCount = OldVec.getValueType().getVectorElementCount();
211 EVT OldEltVT = OldVec.getValueType().getVectorElementType();
212 SDLoc dl(N);
213
214 // Convert to a vector of the expanded element type, for example
215 // <3 x i64> -> <6 x i32>.
216 EVT OldVT = N->getValueType(ResNo: 0);
217 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
218
219 if (OldVT != OldEltVT) {
220 // The result of EXTRACT_VECTOR_ELT may be larger than the element type of
221 // the input vector. If so, extend the elements of the input vector to the
222 // same bitwidth as the result before expanding.
223 assert(OldEltVT.bitsLT(OldVT) && "Result type smaller then element type!");
224 EVT NVecVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: OldVT, EC: OldEltCount);
225 OldVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVecVT, Operand: N->getOperand(Num: 0));
226 }
227
228 SDValue NewVec = DAG.getNode(
229 Opcode: ISD::BITCAST, DL: dl,
230 VT: EVT::getVectorVT(Context&: *DAG.getContext(), VT: NewVT, EC: OldEltCount * 2), Operand: OldVec);
231
232 // Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
233 SDValue Idx = N->getOperand(Num: 1);
234
235 Idx = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: Idx.getValueType(), N1: Idx, N2: Idx);
236 Lo = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NewVT, N1: NewVec, N2: Idx);
237
238 Idx = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: Idx.getValueType(), N1: Idx,
239 N2: DAG.getConstant(Val: 1, DL: dl, VT: Idx.getValueType()));
240 Hi = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NewVT, N1: NewVec, N2: Idx);
241
242 if (DAG.getDataLayout().isBigEndian())
243 std::swap(a&: Lo, b&: Hi);
244}
245
246void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
247 SDValue &Hi) {
248 assert(ISD::isNormalLoad(N) && "This routine only for normal loads!");
249 SDLoc dl(N);
250
251 LoadSDNode *LD = cast<LoadSDNode>(Val: N);
252 assert(!LD->isAtomic() && "Atomics can not be split");
253 EVT ValueVT = LD->getValueType(ResNo: 0);
254 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: ValueVT);
255 SDValue Chain = LD->getChain();
256 SDValue Ptr = LD->getBasePtr();
257 AAMDNodes AAInfo = LD->getAAInfo();
258
259 assert(NVT.isByteSized() && "Expanded type not byte sized!");
260
261 Lo = DAG.getLoad(VT: NVT, dl, Chain, Ptr, PtrInfo: LD->getPointerInfo(),
262 Alignment: LD->getBaseAlign(), MMOFlags: LD->getMemOperand()->getFlags(), AAInfo);
263
264 // Increment the pointer to the other half.
265 unsigned IncrementSize = NVT.getSizeInBits() / 8;
266 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
267 Hi = DAG.getLoad(VT: NVT, dl, Chain, Ptr,
268 PtrInfo: LD->getPointerInfo().getWithOffset(O: IncrementSize),
269 Alignment: LD->getBaseAlign(), MMOFlags: LD->getMemOperand()->getFlags(), AAInfo);
270
271 // Build a factor node to remember that this load is independent of the
272 // other one.
273 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
274 N2: Hi.getValue(R: 1));
275
276 // Handle endianness of the load.
277 if (TLI.hasBigEndianPartOrdering(VT: ValueVT, DL: DAG.getDataLayout()))
278 std::swap(a&: Lo, b&: Hi);
279
280 // Modified the chain - switch anything that used the old chain to use
281 // the new one.
282 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
283}
284
285void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
286 EVT OVT = N->getValueType(ResNo: 0);
287 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
288 SDValue Chain = N->getOperand(Num: 0);
289 SDValue Ptr = N->getOperand(Num: 1);
290 SDLoc dl(N);
291 const unsigned Align = N->getConstantOperandVal(Num: 3);
292
293 Lo = DAG.getVAArg(VT: NVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2), Align);
294 Hi = DAG.getVAArg(VT: NVT, dl, Chain: Lo.getValue(R: 1), Ptr, SV: N->getOperand(Num: 2), Align: 0);
295 Chain = Hi.getValue(R: 1);
296
297 // Handle endianness of the load.
298 if (TLI.hasBigEndianPartOrdering(VT: OVT, DL: DAG.getDataLayout()))
299 std::swap(a&: Lo, b&: Hi);
300
301 // Modified the chain - switch anything that used the old chain to use
302 // the new one.
303 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
304}
305
306
307//===--------------------------------------------------------------------===//
308// Generic Operand Expansion.
309//===--------------------------------------------------------------------===//
310
311void DAGTypeLegalizer::IntegerToVector(SDValue Op, unsigned NumElements,
312 SmallVectorImpl<SDValue> &Ops,
313 EVT EltVT) {
314 assert(Op.getValueType().isInteger());
315 SDLoc DL(Op);
316 SDValue Parts[2];
317
318 if (NumElements > 1) {
319 NumElements >>= 1;
320 SplitInteger(Op, Lo&: Parts[0], Hi&: Parts[1]);
321 if (DAG.getDataLayout().isBigEndian())
322 std::swap(a&: Parts[0], b&: Parts[1]);
323 IntegerToVector(Op: Parts[0], NumElements, Ops, EltVT);
324 IntegerToVector(Op: Parts[1], NumElements, Ops, EltVT);
325 } else {
326 Ops.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL, VT: EltVT, Operand: Op));
327 }
328}
329
330SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
331 SDLoc dl(N);
332 if (N->getValueType(ResNo: 0).isVector() &&
333 N->getOperand(Num: 0).getValueType().isInteger()) {
334 // An illegal expanding type is being converted to a legal vector type.
335 // Make a two element vector out of the expanded parts and convert that
336 // instead, but only if the new vector type is legal (otherwise there
337 // is no point, and it might create expansion loops). For example, on
338 // x86 this turns v1i64 = BITCAST i64 into v1i64 = BITCAST v2i32.
339 //
340 // FIXME: I'm not sure why we are first trying to split the input into
341 // a 2 element vector, so I'm leaving it here to maintain the current
342 // behavior.
343 unsigned NumElts = 2;
344 EVT OVT = N->getOperand(Num: 0).getValueType();
345 EVT NVT = EVT::getVectorVT(Context&: *DAG.getContext(),
346 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT),
347 NumElements: NumElts);
348 if (!isTypeLegal(VT: NVT)) {
349 // If we can't find a legal type by splitting the integer in half,
350 // then we can use the node's value type.
351 NumElts = N->getValueType(ResNo: 0).getVectorNumElements();
352 NVT = N->getValueType(ResNo: 0);
353 }
354
355 SmallVector<SDValue, 8> Ops;
356 IntegerToVector(Op: N->getOperand(Num: 0), NumElements: NumElts, Ops, EltVT: NVT.getVectorElementType());
357
358 SDValue Vec = DAG.getBuildVector(VT: NVT, DL: dl, Ops: ArrayRef(Ops.data(), NumElts));
359 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Vec);
360 }
361
362 // Otherwise, store to a temporary and load out again as the new type.
363 return CreateStackStoreLoad(Op: N->getOperand(Num: 0), DestVT: N->getValueType(ResNo: 0));
364}
365
366SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
367 // The vector type is legal but the element type needs expansion.
368 EVT VecVT = N->getValueType(ResNo: 0);
369 unsigned NumElts = VecVT.getVectorNumElements();
370 EVT OldVT = N->getOperand(Num: 0).getValueType();
371 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
372 SDLoc dl(N);
373
374 assert(OldVT == VecVT.getVectorElementType() &&
375 "BUILD_VECTOR operand type doesn't match vector element type!");
376
377 if (VecVT.isInteger() && TLI.isOperationLegal(Op: ISD::SPLAT_VECTOR, VT: VecVT) &&
378 TLI.isOperationLegalOrCustom(Op: ISD::SPLAT_VECTOR_PARTS, VT: VecVT)) {
379 if (SDValue V = cast<BuildVectorSDNode>(Val: N)->getSplatValue()) {
380 SDValue Lo, Hi;
381 GetExpandedOp(Op: V, Lo, Hi);
382 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: dl, VT: VecVT, N1: Lo, N2: Hi);
383 }
384 }
385
386 // Build a vector of twice the length out of the expanded elements.
387 // For example <3 x i64> -> <6 x i32>.
388 SmallVector<SDValue, 16> NewElts;
389 NewElts.reserve(N: NumElts*2);
390
391 for (unsigned i = 0; i < NumElts; ++i) {
392 SDValue Lo, Hi;
393 GetExpandedOp(Op: N->getOperand(Num: i), Lo, Hi);
394 if (DAG.getDataLayout().isBigEndian())
395 std::swap(a&: Lo, b&: Hi);
396 NewElts.push_back(Elt: Lo);
397 NewElts.push_back(Elt: Hi);
398 }
399
400 EVT NewVecVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NewVT, NumElements: NewElts.size());
401 SDValue NewVec = DAG.getBuildVector(VT: NewVecVT, DL: dl, Ops: NewElts);
402
403 // Convert the new vector to the old vector type.
404 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VecVT, Operand: NewVec);
405}
406
407SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
408 SDValue Lo, Hi;
409 GetExpandedOp(Op: N->getOperand(Num: 0), Lo, Hi);
410 return N->getConstantOperandVal(Num: 1) ? Hi : Lo;
411}
412
413// Split the integer operand in two and create a second FAKE_USE node for
414// the other half. The original SDNode is updated in place.
415SDValue DAGTypeLegalizer::ExpandOp_FAKE_USE(SDNode *N) {
416 SDValue Lo, Hi;
417 SDValue Chain = N->getOperand(Num: 0);
418 GetExpandedOp(Op: N->getOperand(Num: 1), Lo, Hi);
419 SDValue LoUse = DAG.getNode(Opcode: ISD::FAKE_USE, DL: SDLoc(), VT: MVT::Other, N1: Chain, N2: Lo);
420 DAG.UpdateNodeOperands(N, Op1: LoUse, Op2: Hi);
421 return SDValue(N, 0);
422}
423
424SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
425 // The vector type is legal but the element type needs expansion.
426 EVT VecVT = N->getValueType(ResNo: 0);
427 unsigned NumElts = VecVT.getVectorNumElements();
428 SDLoc dl(N);
429
430 SDValue Val = N->getOperand(Num: 1);
431 EVT OldEVT = Val.getValueType();
432 EVT NewEVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldEVT);
433
434 assert(OldEVT == VecVT.getVectorElementType() &&
435 "Inserted element type doesn't match vector element type!");
436
437 // Bitconvert to a vector of twice the length with elements of the expanded
438 // type, insert the expanded vector elements, and then convert back.
439 EVT NewVecVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NewEVT, NumElements: NumElts*2);
440 SDValue NewVec = DAG.getNode(Opcode: ISD::BITCAST, DL: dl,
441 VT: NewVecVT, Operand: N->getOperand(Num: 0));
442
443 SDValue Lo, Hi;
444 GetExpandedOp(Op: Val, Lo, Hi);
445 if (DAG.getDataLayout().isBigEndian())
446 std::swap(a&: Lo, b&: Hi);
447
448 SDValue Idx = N->getOperand(Num: 2);
449 Idx = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: Idx.getValueType(), N1: Idx, N2: Idx);
450 NewVec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NewVecVT, N1: NewVec, N2: Lo, N3: Idx);
451 Idx = DAG.getNode(Opcode: ISD::ADD, DL: dl,
452 VT: Idx.getValueType(), N1: Idx,
453 N2: DAG.getConstant(Val: 1, DL: dl, VT: Idx.getValueType()));
454 NewVec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NewVecVT, N1: NewVec, N2: Hi, N3: Idx);
455
456 // Convert the new vector to the old vector type.
457 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VecVT, Operand: NewVec);
458}
459
460SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) {
461 SDLoc dl(N);
462 EVT VT = N->getValueType(ResNo: 0);
463 assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
464 "SCALAR_TO_VECTOR operand type doesn't match vector element type!");
465 unsigned NumElts = VT.getVectorNumElements();
466 SmallVector<SDValue, 16> Ops(NumElts);
467 Ops[0] = N->getOperand(Num: 0);
468 SDValue UndefVal = DAG.getUNDEF(VT: Ops[0].getValueType());
469 for (unsigned i = 1; i < NumElts; ++i)
470 Ops[i] = UndefVal;
471 return DAG.getBuildVector(VT, DL: dl, Ops);
472}
473
474SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
475 assert(ISD::isNormalStore(N) && "This routine only for normal stores!");
476 assert(OpNo == 1 && "Can only expand the stored value so far");
477 SDLoc dl(N);
478
479 StoreSDNode *St = cast<StoreSDNode>(Val: N);
480 assert(!St->isAtomic() && "Atomics can not be split");
481 EVT ValueVT = St->getValue().getValueType();
482 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: ValueVT);
483 SDValue Chain = St->getChain();
484 SDValue Ptr = St->getBasePtr();
485 AAMDNodes AAInfo = St->getAAInfo();
486
487 assert(NVT.isByteSized() && "Expanded type not byte sized!");
488 unsigned IncrementSize = NVT.getSizeInBits() / 8;
489
490 SDValue Lo, Hi;
491 GetExpandedOp(Op: St->getValue(), Lo, Hi);
492
493 if (TLI.hasBigEndianPartOrdering(VT: ValueVT, DL: DAG.getDataLayout()))
494 std::swap(a&: Lo, b&: Hi);
495
496 Lo =
497 DAG.getStore(Chain, dl, Val: Lo, Ptr, PtrInfo: St->getPointerInfo(), Alignment: St->getBaseAlign(),
498 MMOFlags: St->getMemOperand()->getFlags(), AAInfo);
499
500 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
501 Hi = DAG.getStore(
502 Chain, dl, Val: Hi, Ptr, PtrInfo: St->getPointerInfo().getWithOffset(O: IncrementSize),
503 Alignment: St->getBaseAlign(), MMOFlags: St->getMemOperand()->getFlags(), AAInfo);
504
505 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
506}
507
508
509//===--------------------------------------------------------------------===//
510// Generic Result Splitting.
511//===--------------------------------------------------------------------===//
512
513// Be careful to make no assumptions about which of Lo/Hi is stored first in
514// memory (for vectors it is always Lo first followed by Hi in the following
515// bytes; for integers and floats it is Lo first if and only if the machine is
516// little-endian).
517
518void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
519 SDValue &Lo, SDValue &Hi) {
520 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
521 GetSplitOp(Op, Lo, Hi);
522}
523
524void DAGTypeLegalizer::SplitRes_Select(SDNode *N, SDValue &Lo, SDValue &Hi) {
525 SDValue LL, LH, RL, RH, CL, CH;
526 SDLoc dl(N);
527 unsigned Opcode = N->getOpcode();
528 GetSplitOp(Op: N->getOperand(Num: 1), Lo&: LL, Hi&: LH);
529 GetSplitOp(Op: N->getOperand(Num: 2), Lo&: RL, Hi&: RH);
530
531 SDValue Cond = N->getOperand(Num: 0);
532 CL = CH = Cond;
533 if (Cond.getValueType().isVector()) {
534 if (SDValue Res = WidenVSELECTMask(N))
535 std::tie(args&: CL, args&: CH) = DAG.SplitVector(N: Res, DL: dl);
536 // Check if there are already splitted versions of the vector available and
537 // use those instead of splitting the mask operand again.
538 else if (getTypeAction(VT: Cond.getValueType()) ==
539 TargetLowering::TypeSplitVector)
540 GetSplitVector(Op: Cond, Lo&: CL, Hi&: CH);
541 // It seems to improve code to generate two narrow SETCCs as opposed to
542 // splitting a wide result vector.
543 else if (Cond.getOpcode() == ISD::SETCC) {
544 // If the condition is a vXi1 vector, and the LHS of the setcc is a legal
545 // type and the setcc result type is the same vXi1, then leave the setcc
546 // alone.
547 EVT CondLHSVT = Cond.getOperand(i: 0).getValueType();
548 if (Cond.getValueType().getVectorElementType() == MVT::i1 &&
549 isTypeLegal(VT: CondLHSVT) &&
550 getSetCCResultType(VT: CondLHSVT) == Cond.getValueType())
551 std::tie(args&: CL, args&: CH) = DAG.SplitVector(N: Cond, DL: dl);
552 else
553 SplitVecRes_SETCC(N: Cond.getNode(), Lo&: CL, Hi&: CH);
554 } else
555 std::tie(args&: CL, args&: CH) = DAG.SplitVector(N: Cond, DL: dl);
556 }
557
558 if (Opcode != ISD::VP_SELECT && Opcode != ISD::VP_MERGE) {
559 Lo = DAG.getNode(Opcode, DL: dl, VT: LL.getValueType(), N1: CL, N2: LL, N3: RL);
560 Hi = DAG.getNode(Opcode, DL: dl, VT: LH.getValueType(), N1: CH, N2: LH, N3: RH);
561 return;
562 }
563
564 SDValue EVLLo, EVLHi;
565 std::tie(args&: EVLLo, args&: EVLHi) =
566 DAG.SplitEVL(N: N->getOperand(Num: 3), VecVT: N->getValueType(ResNo: 0), DL: dl);
567
568 Lo = DAG.getNode(Opcode, DL: dl, VT: LL.getValueType(), N1: CL, N2: LL, N3: RL, N4: EVLLo);
569 Hi = DAG.getNode(Opcode, DL: dl, VT: LH.getValueType(), N1: CH, N2: LH, N3: RH, N4: EVLHi);
570}
571
572void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo,
573 SDValue &Hi) {
574 SDValue LL, LH, RL, RH;
575 SDLoc dl(N);
576 GetSplitOp(Op: N->getOperand(Num: 2), Lo&: LL, Hi&: LH);
577 GetSplitOp(Op: N->getOperand(Num: 3), Lo&: RL, Hi&: RH);
578
579 Lo = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: LL.getValueType(), N1: N->getOperand(Num: 0),
580 N2: N->getOperand(Num: 1), N3: LL, N4: RL, N5: N->getOperand(Num: 4));
581 Hi = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: LH.getValueType(), N1: N->getOperand(Num: 0),
582 N2: N->getOperand(Num: 1), N3: LH, N4: RH, N5: N->getOperand(Num: 4));
583}
584
585void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) {
586 EVT LoVT, HiVT;
587 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: N->getValueType(ResNo: 0));
588 Lo = DAG.getUNDEF(VT: LoVT);
589 Hi = DAG.getUNDEF(VT: HiVT);
590}
591
592void DAGTypeLegalizer::SplitVecRes_AssertZext(SDNode *N, SDValue &Lo,
593 SDValue &Hi) {
594 SDValue L, H;
595 SDLoc dl(N);
596 GetSplitOp(Op: N->getOperand(Num: 0), Lo&: L, Hi&: H);
597
598 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: L.getValueType(), N1: L, N2: N->getOperand(Num: 1));
599 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: H.getValueType(), N1: H, N2: N->getOperand(Num: 1));
600}
601
602void DAGTypeLegalizer::SplitVecRes_AssertSext(SDNode *N, SDValue &Lo,
603 SDValue &Hi) {
604 SDValue L, H;
605 SDLoc dl(N);
606 GetSplitOp(Op: N->getOperand(Num: 0), Lo&: L, Hi&: H);
607
608 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: L.getValueType(), N1: L, N2: N->getOperand(Num: 1));
609 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: H.getValueType(), N1: H, N2: N->getOperand(Num: 1));
610}
611
612void DAGTypeLegalizer::SplitRes_FREEZE(SDNode *N, SDValue &Lo, SDValue &Hi) {
613 SDValue L, H;
614 SDLoc dl(N);
615 GetSplitOp(Op: N->getOperand(Num: 0), Lo&: L, Hi&: H);
616
617 Lo = DAG.getNode(Opcode: ISD::FREEZE, DL: dl, VT: L.getValueType(), Operand: L);
618 Hi = DAG.getNode(Opcode: ISD::FREEZE, DL: dl, VT: H.getValueType(), Operand: H);
619}
620
621void DAGTypeLegalizer::SplitRes_ARITH_FENCE(SDNode *N, SDValue &Lo,
622 SDValue &Hi) {
623 SDValue L, H;
624 SDLoc DL(N);
625 GetSplitOp(Op: N->getOperand(Num: 0), Lo&: L, Hi&: H);
626
627 Lo = DAG.getNode(Opcode: ISD::ARITH_FENCE, DL, VT: L.getValueType(), Operand: L);
628 Hi = DAG.getNode(Opcode: ISD::ARITH_FENCE, DL, VT: H.getValueType(), Operand: H);
629}
630