1//===-------- LegalizeTypesGeneric.cpp - Generic type legalization --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements generic type expansion and splitting for LegalizeTypes.
10// The routines here perform legalization when the details of the type (such as
11// whether it is an integer or a float) do not matter.
12// Expansion is the act of changing a computation in an illegal type to be a
13// computation in two identical registers of a smaller type. The Lo/Hi part
14// is required to be stored first in memory on little/big-endian machines.
15// Splitting is the act of changing a computation in an illegal type to be a
16// computation in two not necessarily identical registers of a smaller type.
17// There are no requirements on how the type is represented in memory.
18//
19//===----------------------------------------------------------------------===//
20
21#include "LegalizeTypes.h"
22#include "llvm/IR/DataLayout.h"
23using namespace llvm;
24
25#define DEBUG_TYPE "legalize-types"
26
27//===----------------------------------------------------------------------===//
28// Generic Result Expansion.
29//===----------------------------------------------------------------------===//
30
31// These routines assume that the Lo/Hi part is stored first in memory on
32// little/big-endian machines, followed by the Hi/Lo part. This means that
33// they cannot be used as is on vectors, for which Lo is always stored first.
34void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
35 SDValue &Lo, SDValue &Hi) {
36 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
37 GetExpandedOp(Op, Lo, Hi);
38}
39
40void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
41 EVT OutVT = N->getValueType(ResNo: 0);
42 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
43 SDValue InOp = N->getOperand(Num: 0);
44 EVT InVT = InOp.getValueType();
45 SDLoc dl(N);
46
47 // Handle some special cases efficiently.
48 switch (getTypeAction(VT: InVT)) {
49 case TargetLowering::TypeLegal:
50 case TargetLowering::TypePromoteInteger:
51 break;
52 case TargetLowering::TypeSoftPromoteHalf:
53 llvm_unreachable("Bitcast of a promotion-needing float should never need"
54 "expansion");
55 case TargetLowering::TypeSoftenFloat:
56 SplitInteger(Op: GetSoftenedFloat(Op: InOp), Lo, Hi);
57 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
58 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
59 return;
60 case TargetLowering::TypeExpandInteger:
61 case TargetLowering::TypeExpandFloat: {
62 auto &DL = DAG.getDataLayout();
63 // Convert the expanded pieces of the input.
64 GetExpandedOp(Op: InOp, Lo, Hi);
65 if (TLI.hasBigEndianPartOrdering(VT: InVT, DL) !=
66 TLI.hasBigEndianPartOrdering(VT: OutVT, DL))
67 std::swap(a&: Lo, b&: Hi);
68 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
69 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
70 return;
71 }
72 case TargetLowering::TypeSplitVector:
73 GetSplitVector(Op: InOp, Lo, Hi);
74 if (TLI.hasBigEndianPartOrdering(VT: OutVT, DL: DAG.getDataLayout()))
75 std::swap(a&: Lo, b&: Hi);
76 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
77 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
78 return;
79 case TargetLowering::TypeScalarizeVector:
80 // Convert the element instead.
81 SplitInteger(Op: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)), Lo, Hi);
82 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
83 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
84 return;
85 case TargetLowering::TypeScalarizeScalableVector:
86 report_fatal_error(reason: "scalarization of scalable vectors is not supported");
87 case TargetLowering::TypeWidenVector: {
88 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
89 InOp = GetWidenedVector(Op: InOp);
90 EVT LoVT, HiVT;
91 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: InVT);
92 std::tie(args&: Lo, args&: Hi) = DAG.SplitVector(N: InOp, DL: dl, LoVT, HiVT);
93 if (TLI.hasBigEndianPartOrdering(VT: OutVT, DL: DAG.getDataLayout()))
94 std::swap(a&: Lo, b&: Hi);
95 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Lo);
96 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Hi);
97 return;
98 }
99 }
100
101 if (InVT.isVector() && OutVT.isInteger()) {
102 // Handle cases like i64 = BITCAST v1i64 on x86, where the operand
103 // is legal but the result is not.
104 unsigned NumElems = 2;
105 EVT ElemVT = NOutVT;
106 EVT NVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: ElemVT, NumElements: NumElems);
107
108 // If <ElemVT * N> is not a legal type, try <ElemVT/2 * (N*2)>.
109 while (!isTypeLegal(VT: NVT)) {
110 unsigned NewSizeInBits = ElemVT.getSizeInBits() / 2;
111 // If the element size is smaller than byte, bail.
112 if (NewSizeInBits < 8)
113 break;
114 NumElems *= 2;
115 ElemVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NewSizeInBits);
116 NVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: ElemVT, NumElements: NumElems);
117 }
118
119 if (isTypeLegal(VT: NVT)) {
120 SDValue CastInOp = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NVT, Operand: InOp);
121
122 SmallVector<SDValue, 8> Vals;
123 for (unsigned i = 0; i < NumElems; ++i)
124 Vals.push_back(Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: ElemVT,
125 N1: CastInOp, N2: DAG.getVectorIdxConstant(Val: i, DL: dl)));
126
127 // Build Lo, Hi pair by pairing extracted elements if needed.
128 unsigned Slot = 0;
129 for (unsigned e = Vals.size(); e - Slot > 2; Slot += 2, e += 1) {
130 // Each iteration will BUILD_PAIR two nodes and append the result until
131 // there are only two nodes left, i.e. Lo and Hi.
132 SDValue LHS = Vals[Slot];
133 SDValue RHS = Vals[Slot + 1];
134
135 if (DAG.getDataLayout().isBigEndian())
136 std::swap(a&: LHS, b&: RHS);
137
138 Vals.push_back(Elt: DAG.getNode(
139 Opcode: ISD::BUILD_PAIR, DL: dl,
140 VT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: LHS.getValueSizeInBits() << 1),
141 N1: LHS, N2: RHS));
142 }
143 Lo = Vals[Slot++];
144 Hi = Vals[Slot++];
145
146 if (DAG.getDataLayout().isBigEndian())
147 std::swap(a&: Lo, b&: Hi);
148
149 return;
150 }
151 }
152
153 // Lower the bit-convert to a store/load from the stack.
154 assert(NOutVT.isByteSized() && "Expanded type not byte sized!");
155
156 // Create the stack frame object. Make sure it is aligned for both
157 // the source and expanded destination types.
158
159 // In cases where the vector is illegal it will be broken down into parts
160 // and stored in parts - we should use the alignment for the smallest part.
161 Align InAlign = DAG.getReducedAlign(VT: InVT, /*UseABI=*/false);
162 Align NOutAlign = DAG.getReducedAlign(VT: NOutVT, /*UseABI=*/false);
163 Align Align = std::max(a: InAlign, b: NOutAlign);
164 SDValue StackPtr = DAG.CreateStackTemporary(Bytes: InVT.getStoreSize(), Alignment: Align);
165 int SPFI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
166 MachinePointerInfo PtrInfo =
167 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
168
169 // Emit a store to the stack slot.
170 SDValue Store = DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: InOp, Ptr: StackPtr, PtrInfo);
171
172 // Load the first half from the stack slot.
173 Lo = DAG.getLoad(VT: NOutVT, dl, Chain: Store, Ptr: StackPtr, PtrInfo, Alignment: NOutAlign);
174
175 // Increment the pointer to the other half.
176 unsigned IncrementSize = NOutVT.getSizeInBits() / 8;
177 StackPtr =
178 DAG.getMemBasePlusOffset(Base: StackPtr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
179
180 // Load the second half from the stack slot.
181 Hi = DAG.getLoad(VT: NOutVT, dl, Chain: Store, Ptr: StackPtr,
182 PtrInfo: PtrInfo.getWithOffset(O: IncrementSize), Alignment: NOutAlign);
183
184 // Handle endianness of the load.
185 if (TLI.hasBigEndianPartOrdering(VT: OutVT, DL: DAG.getDataLayout()))
186 std::swap(a&: Lo, b&: Hi);
187}
188
189void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
190 SDValue &Hi) {
191 // Return the operands.
192 Lo = N->getOperand(Num: 0);
193 Hi = N->getOperand(Num: 1);
194}
195
196void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
197 SDValue &Hi) {
198 GetExpandedOp(Op: N->getOperand(Num: 0), Lo, Hi);
199 SDValue Part = N->getConstantOperandVal(Num: 1) ? Hi : Lo;
200
201 assert(Part.getValueType() == N->getValueType(0) &&
202 "Type twice as big as expanded type not itself expanded!");
203
204 GetPairElements(Pair: Part, Lo, Hi);
205}
206
207void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
208 SDValue &Hi) {
209 SDValue OldVec = N->getOperand(Num: 0);
210 ElementCount OldEltCount = OldVec.getValueType().getVectorElementCount();
211 EVT OldEltVT = OldVec.getValueType().getVectorElementType();
212 SDLoc dl(N);
213
214 // Convert to a vector of the expanded element type, for example
215 // <3 x i64> -> <6 x i32>.
216 EVT OldVT = N->getValueType(ResNo: 0);
217 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
218
219 if (OldVT != OldEltVT) {
220 // The result of EXTRACT_VECTOR_ELT may be larger than the element type of
221 // the input vector. If so, extend the elements of the input vector to the
222 // same bitwidth as the result before expanding.
223 assert(OldEltVT.bitsLT(OldVT) && "Result type smaller then element type!");
224 EVT NVecVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: OldVT, EC: OldEltCount);
225 OldVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVecVT, Operand: N->getOperand(Num: 0));
226 }
227
228 SDValue NewVec = DAG.getNode(
229 Opcode: ISD::BITCAST, DL: dl,
230 VT: EVT::getVectorVT(Context&: *DAG.getContext(), VT: NewVT, EC: OldEltCount * 2), Operand: OldVec);
231
232 // Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
233 SDValue Idx = N->getOperand(Num: 1);
234 Idx = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: Idx.getValueType(), N1: Idx,
235 N2: DAG.getShiftAmountConstant(Val: 1, VT: Idx.getValueType(), DL: dl));
236 Lo = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NewVT, N1: NewVec, N2: Idx);
237
238 Idx = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: Idx.getValueType(), N1: Idx,
239 N2: DAG.getConstant(Val: 1, DL: dl, VT: Idx.getValueType()));
240 Hi = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NewVT, N1: NewVec, N2: Idx);
241
242 if (DAG.getDataLayout().isBigEndian())
243 std::swap(a&: Lo, b&: Hi);
244}
245
246void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
247 SDValue &Hi) {
248 assert(ISD::isNormalLoad(N) && "This routine only for normal loads!");
249 SDLoc dl(N);
250
251 LoadSDNode *LD = cast<LoadSDNode>(Val: N);
252 assert(!LD->isAtomic() && "Atomics can not be split");
253 EVT ValueVT = LD->getValueType(ResNo: 0);
254 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: ValueVT);
255 SDValue Chain = LD->getChain();
256 SDValue Ptr = LD->getBasePtr();
257 MMOMetadata Metadata = LD->getMMOMetadataForSubAccess();
258
259 assert(NVT.isByteSized() && "Expanded type not byte sized!");
260
261 Lo =
262 DAG.getLoad(VT: NVT, dl, Chain, Ptr, PtrInfo: LD->getPointerInfo(), Alignment: LD->getBaseAlign(),
263 MMOFlags: LD->getMemOperand()->getFlags(), Metadata);
264
265 // Increment the pointer to the other half.
266 unsigned IncrementSize = NVT.getSizeInBits() / 8;
267 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
268 Hi = DAG.getLoad(
269 VT: NVT, dl, Chain, Ptr, PtrInfo: LD->getPointerInfo().getWithOffset(O: IncrementSize),
270 Alignment: LD->getBaseAlign(), MMOFlags: LD->getMemOperand()->getFlags(), Metadata);
271
272 // Build a factor node to remember that this load is independent of the
273 // other one.
274 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
275 N2: Hi.getValue(R: 1));
276
277 // Handle endianness of the load.
278 if (TLI.hasBigEndianPartOrdering(VT: ValueVT, DL: DAG.getDataLayout()))
279 std::swap(a&: Lo, b&: Hi);
280
281 // Modified the chain - switch anything that used the old chain to use
282 // the new one.
283 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
284}
285
286void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
287 EVT OVT = N->getValueType(ResNo: 0);
288 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
289 SDValue Chain = N->getOperand(Num: 0);
290 SDValue Ptr = N->getOperand(Num: 1);
291 SDLoc dl(N);
292 const unsigned Align = N->getConstantOperandVal(Num: 3);
293
294 Lo = DAG.getVAArg(VT: NVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2), Align);
295 Hi = DAG.getVAArg(VT: NVT, dl, Chain: Lo.getValue(R: 1), Ptr, SV: N->getOperand(Num: 2), Align: 0);
296 Chain = Hi.getValue(R: 1);
297
298 // Handle endianness of the load.
299 if (TLI.hasBigEndianPartOrdering(VT: OVT, DL: DAG.getDataLayout()))
300 std::swap(a&: Lo, b&: Hi);
301
302 // Modified the chain - switch anything that used the old chain to use
303 // the new one.
304 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
305}
306
307
308//===--------------------------------------------------------------------===//
309// Generic Operand Expansion.
310//===--------------------------------------------------------------------===//
311
312void DAGTypeLegalizer::IntegerToVector(SDValue Op, unsigned NumElements,
313 SmallVectorImpl<SDValue> &Ops,
314 EVT EltVT) {
315 assert(Op.getValueType().isInteger());
316 SDLoc DL(Op);
317 SDValue Parts[2];
318
319 if (NumElements > 1) {
320 NumElements >>= 1;
321 SplitInteger(Op, Lo&: Parts[0], Hi&: Parts[1]);
322 if (DAG.getDataLayout().isBigEndian())
323 std::swap(a&: Parts[0], b&: Parts[1]);
324 IntegerToVector(Op: Parts[0], NumElements, Ops, EltVT);
325 IntegerToVector(Op: Parts[1], NumElements, Ops, EltVT);
326 } else {
327 Ops.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL, VT: EltVT, Operand: Op));
328 }
329}
330
331SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
332 SDLoc dl(N);
333 if (N->getValueType(ResNo: 0).isVector() &&
334 N->getOperand(Num: 0).getValueType().isInteger()) {
335 // An illegal expanding type is being converted to a legal vector type.
336 // Make a two element vector out of the expanded parts and convert that
337 // instead, but only if the new vector type is legal (otherwise there
338 // is no point, and it might create expansion loops). For example, on
339 // x86 this turns v1i64 = BITCAST i64 into v1i64 = BITCAST v2i32.
340 //
341 // FIXME: I'm not sure why we are first trying to split the input into
342 // a 2 element vector, so I'm leaving it here to maintain the current
343 // behavior.
344 unsigned NumElts = 2;
345 EVT OVT = N->getOperand(Num: 0).getValueType();
346 EVT NVT = EVT::getVectorVT(Context&: *DAG.getContext(),
347 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT),
348 NumElements: NumElts);
349 if (!isTypeLegal(VT: NVT)) {
350 // If we can't find a legal type by splitting the integer in half,
351 // then we can use the node's value type.
352 NumElts = N->getValueType(ResNo: 0).getVectorNumElements();
353 NVT = N->getValueType(ResNo: 0);
354 }
355
356 SmallVector<SDValue, 8> Ops;
357 IntegerToVector(Op: N->getOperand(Num: 0), NumElements: NumElts, Ops, EltVT: NVT.getVectorElementType());
358
359 SDValue Vec = DAG.getBuildVector(VT: NVT, DL: dl, Ops: ArrayRef(Ops.data(), NumElts));
360 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Vec);
361 }
362
363 // Otherwise, store to a temporary and load out again as the new type.
364 return CreateStackStoreLoad(Op: N->getOperand(Num: 0), DestVT: N->getValueType(ResNo: 0));
365}
366
367SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
368 // The vector type is legal but the element type needs expansion.
369 EVT VecVT = N->getValueType(ResNo: 0);
370 unsigned NumElts = VecVT.getVectorNumElements();
371 EVT OldVT = N->getOperand(Num: 0).getValueType();
372 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldVT);
373 SDLoc dl(N);
374
375 assert(OldVT == VecVT.getVectorElementType() &&
376 "BUILD_VECTOR operand type doesn't match vector element type!");
377
378 if (VecVT.isInteger() && TLI.isOperationLegal(Op: ISD::SPLAT_VECTOR, VT: VecVT) &&
379 TLI.isOperationLegalOrCustom(Op: ISD::SPLAT_VECTOR_PARTS, VT: VecVT)) {
380 if (SDValue V = cast<BuildVectorSDNode>(Val: N)->getSplatValue()) {
381 SDValue Lo, Hi;
382 GetExpandedOp(Op: V, Lo, Hi);
383 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: dl, VT: VecVT, N1: Lo, N2: Hi);
384 }
385 }
386
387 // Build a vector of twice the length out of the expanded elements.
388 // For example <3 x i64> -> <6 x i32>.
389 SmallVector<SDValue, 16> NewElts;
390 NewElts.reserve(N: NumElts*2);
391
392 for (unsigned i = 0; i < NumElts; ++i) {
393 SDValue Lo, Hi;
394 GetExpandedOp(Op: N->getOperand(Num: i), Lo, Hi);
395 if (DAG.getDataLayout().isBigEndian())
396 std::swap(a&: Lo, b&: Hi);
397 NewElts.push_back(Elt: Lo);
398 NewElts.push_back(Elt: Hi);
399 }
400
401 EVT NewVecVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NewVT, NumElements: NewElts.size());
402 SDValue NewVec = DAG.getBuildVector(VT: NewVecVT, DL: dl, Ops: NewElts);
403
404 // Convert the new vector to the old vector type.
405 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VecVT, Operand: NewVec);
406}
407
408SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
409 SDValue Lo, Hi;
410 GetExpandedOp(Op: N->getOperand(Num: 0), Lo, Hi);
411 return N->getConstantOperandVal(Num: 1) ? Hi : Lo;
412}
413
414// Split the integer operand in two and create a second FAKE_USE node for
415// the other half. The original SDNode is updated in place.
416SDValue DAGTypeLegalizer::ExpandOp_FAKE_USE(SDNode *N) {
417 SDValue Lo, Hi;
418 SDValue Chain = N->getOperand(Num: 0);
419 GetExpandedOp(Op: N->getOperand(Num: 1), Lo, Hi);
420 SDValue LoUse = DAG.getNode(Opcode: ISD::FAKE_USE, DL: SDLoc(), VT: MVT::Other, N1: Chain, N2: Lo);
421 DAG.UpdateNodeOperands(N, Op1: LoUse, Op2: Hi);
422 return SDValue(N, 0);
423}
424
425SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
426 // The vector type is legal but the element type needs expansion.
427 EVT VecVT = N->getValueType(ResNo: 0);
428 unsigned NumElts = VecVT.getVectorNumElements();
429 SDLoc dl(N);
430
431 SDValue Val = N->getOperand(Num: 1);
432 EVT OldEVT = Val.getValueType();
433 EVT NewEVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OldEVT);
434
435 assert(OldEVT == VecVT.getVectorElementType() &&
436 "Inserted element type doesn't match vector element type!");
437
438 // Bitconvert to a vector of twice the length with elements of the expanded
439 // type, insert the expanded vector elements, and then convert back.
440 EVT NewVecVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NewEVT, NumElements: NumElts*2);
441 SDValue NewVec = DAG.getNode(Opcode: ISD::BITCAST, DL: dl,
442 VT: NewVecVT, Operand: N->getOperand(Num: 0));
443
444 SDValue Lo, Hi;
445 GetExpandedOp(Op: Val, Lo, Hi);
446 if (DAG.getDataLayout().isBigEndian())
447 std::swap(a&: Lo, b&: Hi);
448
449 SDValue Idx = N->getOperand(Num: 2);
450 Idx = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: Idx.getValueType(), N1: Idx,
451 N2: DAG.getShiftAmountConstant(Val: 1, VT: Idx.getValueType(), DL: dl));
452 NewVec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NewVecVT, N1: NewVec, N2: Lo, N3: Idx);
453 Idx = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: Idx.getValueType(), N1: Idx,
454 N2: DAG.getConstant(Val: 1, DL: dl, VT: Idx.getValueType()));
455 NewVec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NewVecVT, N1: NewVec, N2: Hi, N3: Idx);
456
457 // Convert the new vector to the old vector type.
458 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VecVT, Operand: NewVec);
459}
460
461SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) {
462 SDLoc dl(N);
463 EVT VT = N->getValueType(ResNo: 0);
464 assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
465 "SCALAR_TO_VECTOR operand type doesn't match vector element type!");
466 unsigned NumElts = VT.getVectorNumElements();
467 SmallVector<SDValue, 16> Ops(NumElts);
468 Ops[0] = N->getOperand(Num: 0);
469 SDValue UndefVal = DAG.getUNDEF(VT: Ops[0].getValueType());
470 for (unsigned i = 1; i < NumElts; ++i)
471 Ops[i] = UndefVal;
472 return DAG.getBuildVector(VT, DL: dl, Ops);
473}
474
475SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
476 assert(ISD::isNormalStore(N) && "This routine only for normal stores!");
477 assert(OpNo == 1 && "Can only expand the stored value so far");
478 SDLoc dl(N);
479
480 StoreSDNode *St = cast<StoreSDNode>(Val: N);
481 assert(!St->isAtomic() && "Atomics can not be split");
482 EVT ValueVT = St->getValue().getValueType();
483 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: ValueVT);
484 SDValue Chain = St->getChain();
485 SDValue Ptr = St->getBasePtr();
486 MMOMetadata Metadata = St->getMMOMetadataForSubAccess();
487
488 assert(NVT.isByteSized() && "Expanded type not byte sized!");
489 unsigned IncrementSize = NVT.getSizeInBits() / 8;
490
491 SDValue Lo, Hi;
492 GetExpandedOp(Op: St->getValue(), Lo, Hi);
493
494 if (TLI.hasBigEndianPartOrdering(VT: ValueVT, DL: DAG.getDataLayout()))
495 std::swap(a&: Lo, b&: Hi);
496
497 Lo =
498 DAG.getStore(Chain, dl, Val: Lo, Ptr, PtrInfo: St->getPointerInfo(), Alignment: St->getBaseAlign(),
499 MMOFlags: St->getMemOperand()->getFlags(), Metadata);
500
501 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
502 Hi = DAG.getStore(
503 Chain, dl, Val: Hi, Ptr, PtrInfo: St->getPointerInfo().getWithOffset(O: IncrementSize),
504 Alignment: St->getBaseAlign(), MMOFlags: St->getMemOperand()->getFlags(), Metadata);
505
506 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
507}
508
509
510//===--------------------------------------------------------------------===//
511// Generic Result Splitting.
512//===--------------------------------------------------------------------===//
513
514// Be careful to make no assumptions about which of Lo/Hi is stored first in
515// memory (for vectors it is always Lo first followed by Hi in the following
516// bytes; for integers and floats it is Lo first if and only if the machine is
517// little-endian).
518
519void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
520 SDValue &Lo, SDValue &Hi) {
521 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
522 GetSplitOp(Op, Lo, Hi);
523}
524
525void DAGTypeLegalizer::SplitRes_Select(SDNode *N, SDValue &Lo, SDValue &Hi) {
526 SDValue LL, LH, RL, RH, CL, CH;
527 SDLoc dl(N);
528 unsigned Opcode = N->getOpcode();
529 GetSplitOp(Op: N->getOperand(Num: 1), Lo&: LL, Hi&: LH);
530 GetSplitOp(Op: N->getOperand(Num: 2), Lo&: RL, Hi&: RH);
531
532 SDValue Cond = N->getOperand(Num: 0);
533 CL = CH = Cond;
534 if (Cond.getValueType().isVector()) {
535 if (SDValue Res = WidenVSELECTMask(N))
536 std::tie(args&: CL, args&: CH) = DAG.SplitVector(N: Res, DL: dl);
537 // Check if there are already splitted versions of the vector available and
538 // use those instead of splitting the mask operand again.
539 else if (getTypeAction(VT: Cond.getValueType()) ==
540 TargetLowering::TypeSplitVector)
541 GetSplitVector(Op: Cond, Lo&: CL, Hi&: CH);
542 // It seems to improve code to generate two narrow SETCCs as opposed to
543 // splitting a wide result vector.
544 else if (Cond.getOpcode() == ISD::SETCC) {
545 // If the condition is a vXi1 vector, and the LHS of the setcc is a legal
546 // type and the setcc result type is the same vXi1, then leave the setcc
547 // alone.
548 EVT CondLHSVT = Cond.getOperand(i: 0).getValueType();
549 if (Cond.getValueType().getVectorElementType() == MVT::i1 &&
550 isTypeLegal(VT: CondLHSVT) &&
551 getSetCCResultType(VT: CondLHSVT) == Cond.getValueType())
552 std::tie(args&: CL, args&: CH) = DAG.SplitVector(N: Cond, DL: dl);
553 else
554 SplitVecRes_SETCC(N: Cond.getNode(), Lo&: CL, Hi&: CH);
555 } else
556 std::tie(args&: CL, args&: CH) = DAG.SplitVector(N: Cond, DL: dl);
557 }
558
559 if (Opcode != ISD::VP_MERGE) {
560 Lo = DAG.getNode(Opcode, DL: dl, VT: LL.getValueType(), N1: CL, N2: LL, N3: RL);
561 Hi = DAG.getNode(Opcode, DL: dl, VT: LH.getValueType(), N1: CH, N2: LH, N3: RH);
562 return;
563 }
564
565 SDValue EVLLo, EVLHi;
566 std::tie(args&: EVLLo, args&: EVLHi) =
567 DAG.SplitEVL(N: N->getOperand(Num: 3), VecVT: N->getValueType(ResNo: 0), DL: dl);
568
569 Lo = DAG.getNode(Opcode, DL: dl, VT: LL.getValueType(), N1: CL, N2: LL, N3: RL, N4: EVLLo);
570 Hi = DAG.getNode(Opcode, DL: dl, VT: LH.getValueType(), N1: CH, N2: LH, N3: RH, N4: EVLHi);
571}
572
573void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo,
574 SDValue &Hi) {
575 SDValue LL, LH, RL, RH;
576 SDLoc dl(N);
577 GetSplitOp(Op: N->getOperand(Num: 2), Lo&: LL, Hi&: LH);
578 GetSplitOp(Op: N->getOperand(Num: 3), Lo&: RL, Hi&: RH);
579
580 Lo = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: LL.getValueType(), N1: N->getOperand(Num: 0),
581 N2: N->getOperand(Num: 1), N3: LL, N4: RL, N5: N->getOperand(Num: 4));
582 Hi = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: LH.getValueType(), N1: N->getOperand(Num: 0),
583 N2: N->getOperand(Num: 1), N3: LH, N4: RH, N5: N->getOperand(Num: 4));
584}
585
586void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) {
587 EVT LoVT, HiVT;
588 std::tie(args&: LoVT, args&: HiVT) = DAG.GetSplitDestVTs(VT: N->getValueType(ResNo: 0));
589 Lo = DAG.getUNDEF(VT: LoVT);
590 Hi = DAG.getUNDEF(VT: HiVT);
591}
592
593void DAGTypeLegalizer::SplitVecRes_AssertZext(SDNode *N, SDValue &Lo,
594 SDValue &Hi) {
595 SDValue L, H;
596 SDLoc dl(N);
597 GetSplitOp(Op: N->getOperand(Num: 0), Lo&: L, Hi&: H);
598
599 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: L.getValueType(), N1: L, N2: N->getOperand(Num: 1));
600 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: H.getValueType(), N1: H, N2: N->getOperand(Num: 1));
601}
602
603void DAGTypeLegalizer::SplitVecRes_AssertSext(SDNode *N, SDValue &Lo,
604 SDValue &Hi) {
605 SDValue L, H;
606 SDLoc dl(N);
607 GetSplitOp(Op: N->getOperand(Num: 0), Lo&: L, Hi&: H);
608
609 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: L.getValueType(), N1: L, N2: N->getOperand(Num: 1));
610 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: H.getValueType(), N1: H, N2: N->getOperand(Num: 1));
611}
612
613void DAGTypeLegalizer::SplitRes_FREEZE(SDNode *N, SDValue &Lo, SDValue &Hi) {
614 SDValue L, H;
615 SDLoc dl(N);
616 GetSplitOp(Op: N->getOperand(Num: 0), Lo&: L, Hi&: H);
617
618 Lo = DAG.getNode(Opcode: ISD::FREEZE, DL: dl, VT: L.getValueType(), Operand: L);
619 Hi = DAG.getNode(Opcode: ISD::FREEZE, DL: dl, VT: H.getValueType(), Operand: H);
620}
621
622void DAGTypeLegalizer::SplitRes_ARITH_FENCE(SDNode *N, SDValue &Lo,
623 SDValue &Hi) {
624 SDValue L, H;
625 SDLoc DL(N);
626 GetSplitOp(Op: N->getOperand(Num: 0), Lo&: L, Hi&: H);
627
628 Lo = DAG.getNode(Opcode: ISD::ARITH_FENCE, DL, VT: L.getValueType(), Operand: L);
629 Hi = DAG.getNode(Opcode: ISD::ARITH_FENCE, DL, VT: H.getValueType(), Operand: H);
630}
631