1//===- SelectionDAGDumper.cpp - Implement SelectionDAG::dump() ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the SelectionDAG::dump method and friends.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SDNodeDbgValue.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/APInt.h"
16#include "llvm/ADT/SmallPtrSet.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/CodeGen/ISDOpcodes.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/MachineConstantPool.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/SelectionDAGNodes.h"
24#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetLowering.h"
27#include "llvm/CodeGen/TargetRegisterInfo.h"
28#include "llvm/CodeGen/TargetSubtargetInfo.h"
29#include "llvm/CodeGen/ValueTypes.h"
30#include "llvm/CodeGenTypes/MachineValueType.h"
31#include "llvm/Config/llvm-config.h"
32#include "llvm/IR/BasicBlock.h"
33#include "llvm/IR/Constants.h"
34#include "llvm/IR/DebugInfoMetadata.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Function.h"
37#include "llvm/IR/Intrinsics.h"
38#include "llvm/IR/ModuleSlotTracker.h"
39#include "llvm/IR/Value.h"
40#include "llvm/Support/Casting.h"
41#include "llvm/Support/CommandLine.h"
42#include "llvm/Support/Compiler.h"
43#include "llvm/Support/Debug.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/Printable.h"
46#include "llvm/Support/raw_ostream.h"
47#include "llvm/Target/TargetMachine.h"
48#include <cstdint>
49#include <iterator>
50
51using namespace llvm;
52
53static cl::opt<bool>
54VerboseDAGDumping("dag-dump-verbose", cl::Hidden,
55 cl::desc("Display more information when dumping selection "
56 "DAG nodes."));
57
58static cl::opt<bool>
59 PrintSDNodeAddrs("print-sdnode-addrs", cl::Hidden,
60 cl::desc("Print addresses of SDNodes when dumping"));
61
62std::string SDNode::getOperationName(const SelectionDAG *G) const {
63 switch (getOpcode()) {
64 default:
65 if (getOpcode() < ISD::BUILTIN_OP_END)
66 return "<<Unknown DAG Node>>";
67 if (isMachineOpcode()) {
68 if (G)
69 if (const TargetInstrInfo *TII = G->getSubtarget().getInstrInfo())
70 if (getMachineOpcode() < TII->getNumOpcodes())
71 return std::string(TII->getName(Opcode: getMachineOpcode()));
72 return "<<Unknown Machine Node #" + utostr(X: getOpcode()) + ">>";
73 }
74 if (G) {
75 const SelectionDAGTargetInfo &TSI = G->getSelectionDAGInfo();
76 if (const char *Name = TSI.getTargetNodeName(Opcode: getOpcode()))
77 return Name;
78 const TargetLowering &TLI = G->getTargetLoweringInfo();
79 const char *Name = TLI.getTargetNodeName(Opcode: getOpcode());
80 if (Name) return Name;
81 return "<<Unknown Target Node #" + utostr(X: getOpcode()) + ">>";
82 }
83 return "<<Unknown Node #" + utostr(X: getOpcode()) + ">>";
84
85 // clang-format off
86#ifndef NDEBUG
87 case ISD::DELETED_NODE: return "<<Deleted Node!>>";
88#endif
89 case ISD::PREFETCH: return "Prefetch";
90 case ISD::MEMBARRIER: return "MemBarrier";
91 case ISD::ATOMIC_FENCE: return "AtomicFence";
92 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
93 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess";
94 case ISD::ATOMIC_SWAP: return "AtomicSwap";
95 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
96 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
97 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
98 case ISD::ATOMIC_LOAD_CLR: return "AtomicLoadClr";
99 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr";
100 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor";
101 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand";
102 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin";
103 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax";
104 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin";
105 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax";
106 case ISD::ATOMIC_LOAD_FADD: return "AtomicLoadFAdd";
107 case ISD::ATOMIC_LOAD_FSUB: return "AtomicLoadFSub";
108 case ISD::ATOMIC_LOAD_FMIN: return "AtomicLoadFMin";
109 case ISD::ATOMIC_LOAD_FMAX: return "AtomicLoadFMax";
110 case ISD::ATOMIC_LOAD_FMINIMUM: return "AtomicLoadFMinimum";
111 case ISD::ATOMIC_LOAD_FMAXIMUM: return "AtomicLoadFMaximum";
112 case ISD::ATOMIC_LOAD_UINC_WRAP:
113 return "AtomicLoadUIncWrap";
114 case ISD::ATOMIC_LOAD_UDEC_WRAP:
115 return "AtomicLoadUDecWrap";
116 case ISD::ATOMIC_LOAD_USUB_COND:
117 return "AtomicLoadUSubCond";
118 case ISD::ATOMIC_LOAD_USUB_SAT:
119 return "AtomicLoadUSubSat";
120 case ISD::ATOMIC_LOAD: return "AtomicLoad";
121 case ISD::ATOMIC_STORE: return "AtomicStore";
122 case ISD::PCMARKER: return "PCMarker";
123 case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
124 case ISD::READSTEADYCOUNTER: return "ReadSteadyCounter";
125 case ISD::SRCVALUE: return "SrcValue";
126 case ISD::MDNODE_SDNODE: return "MDNode";
127 case ISD::EntryToken: return "EntryToken";
128 case ISD::TokenFactor: return "TokenFactor";
129 case ISD::AssertSext: return "AssertSext";
130 case ISD::AssertZext: return "AssertZext";
131 case ISD::AssertNoFPClass: return "AssertNoFPClass";
132 case ISD::AssertAlign: return "AssertAlign";
133
134 case ISD::BasicBlock: return "BasicBlock";
135 case ISD::VALUETYPE: return "ValueType";
136 case ISD::Register: return "Register";
137 case ISD::RegisterMask: return "RegisterMask";
138 case ISD::Constant:
139 if (cast<ConstantSDNode>(Val: this)->isOpaque())
140 return "OpaqueConstant";
141 return "Constant";
142 case ISD::ConstantFP: return "ConstantFP";
143 case ISD::GlobalAddress: return "GlobalAddress";
144 case ISD::GlobalTLSAddress: return "GlobalTLSAddress";
145 case ISD::PtrAuthGlobalAddress: return "PtrAuthGlobalAddress";
146 case ISD::FrameIndex: return "FrameIndex";
147 case ISD::JumpTable: return "JumpTable";
148 case ISD::JUMP_TABLE_DEBUG_INFO:
149 return "JUMP_TABLE_DEBUG_INFO";
150 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
151 case ISD::RETURNADDR: return "RETURNADDR";
152 case ISD::ADDROFRETURNADDR: return "ADDROFRETURNADDR";
153 case ISD::FRAMEADDR: return "FRAMEADDR";
154 case ISD::SPONENTRY: return "SPONENTRY";
155 case ISD::STACKADDRESS: return "STACKADDRESS";
156 case ISD::LOCAL_RECOVER: return "LOCAL_RECOVER";
157 case ISD::READ_REGISTER: return "READ_REGISTER";
158 case ISD::WRITE_REGISTER: return "WRITE_REGISTER";
159 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
160 case ISD::EH_DWARF_CFA: return "EH_DWARF_CFA";
161 case ISD::EH_RETURN: return "EH_RETURN";
162 case ISD::EH_SJLJ_SETJMP: return "EH_SJLJ_SETJMP";
163 case ISD::EH_SJLJ_LONGJMP: return "EH_SJLJ_LONGJMP";
164 case ISD::EH_SJLJ_SETUP_DISPATCH: return "EH_SJLJ_SETUP_DISPATCH";
165 case ISD::ConstantPool: return "ConstantPool";
166 case ISD::TargetIndex: return "TargetIndex";
167 case ISD::ExternalSymbol: return "ExternalSymbol";
168 case ISD::BlockAddress: return "BlockAddress";
169 case ISD::INTRINSIC_WO_CHAIN:
170 case ISD::INTRINSIC_VOID:
171 case ISD::INTRINSIC_W_CHAIN: {
172 unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
173 unsigned IID = getOperand(Num: OpNo)->getAsZExtVal();
174 if (IID < Intrinsic::num_intrinsics)
175 return Intrinsic::getBaseName(id: (Intrinsic::ID)IID).str();
176 if (!G)
177 return "Unknown intrinsic";
178 llvm_unreachable("Invalid intrinsic ID");
179 }
180
181 case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
182 case ISD::TargetConstant:
183 if (cast<ConstantSDNode>(Val: this)->isOpaque())
184 return "OpaqueTargetConstant";
185 return "TargetConstant";
186
187 case ISD::TargetConstantFP: return "TargetConstantFP";
188 case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
189 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress";
190 case ISD::TargetFrameIndex: return "TargetFrameIndex";
191 case ISD::TargetJumpTable: return "TargetJumpTable";
192 case ISD::TargetConstantPool: return "TargetConstantPool";
193 case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
194 case ISD::MCSymbol: return "MCSymbol";
195 case ISD::TargetBlockAddress: return "TargetBlockAddress";
196
197 case ISD::CopyToReg: return "CopyToReg";
198 case ISD::CopyFromReg: return "CopyFromReg";
199 case ISD::UNDEF: return "undef";
200 case ISD::POISON: return "poison";
201 case ISD::VSCALE: return "vscale";
202 case ISD::MERGE_VALUES: return "merge_values";
203 case ISD::INLINEASM: return "inlineasm";
204 case ISD::INLINEASM_BR: return "inlineasm_br";
205 case ISD::EH_LABEL: return "eh_label";
206 case ISD::ANNOTATION_LABEL: return "annotation_label";
207 case ISD::HANDLENODE: return "handlenode";
208
209 // Unary operators
210 case ISD::FABS: return "fabs";
211 case ISD::FMINNUM: return "fminnum";
212 case ISD::STRICT_FMINNUM: return "strict_fminnum";
213 case ISD::FMAXNUM: return "fmaxnum";
214 case ISD::STRICT_FMAXNUM: return "strict_fmaxnum";
215 case ISD::FMINNUM_IEEE: return "fminnum_ieee";
216 case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee";
217 case ISD::FMINIMUM: return "fminimum";
218 case ISD::STRICT_FMINIMUM: return "strict_fminimum";
219 case ISD::FMAXIMUM: return "fmaximum";
220 case ISD::STRICT_FMAXIMUM: return "strict_fmaximum";
221 case ISD::FMINIMUMNUM: return "fminimumnum";
222 case ISD::FMAXIMUMNUM: return "fmaximumnum";
223 case ISD::FNEG: return "fneg";
224 case ISD::FSQRT: return "fsqrt";
225 case ISD::STRICT_FSQRT: return "strict_fsqrt";
226 case ISD::FCBRT: return "fcbrt";
227 case ISD::FSIN: return "fsin";
228 case ISD::STRICT_FSIN: return "strict_fsin";
229 case ISD::FCOS: return "fcos";
230 case ISD::STRICT_FCOS: return "strict_fcos";
231 case ISD::FSINCOS: return "fsincos";
232 case ISD::FSINCOSPI: return "fsincospi";
233 case ISD::FMODF: return "fmodf";
234 case ISD::FTAN: return "ftan";
235 case ISD::STRICT_FTAN: return "strict_ftan";
236 case ISD::FASIN: return "fasin";
237 case ISD::STRICT_FASIN: return "strict_fasin";
238 case ISD::FACOS: return "facos";
239 case ISD::STRICT_FACOS: return "strict_facos";
240 case ISD::FATAN: return "fatan";
241 case ISD::STRICT_FATAN: return "strict_fatan";
242 case ISD::FATAN2: return "fatan2";
243 case ISD::STRICT_FATAN2: return "strict_fatan2";
244 case ISD::FSINH: return "fsinh";
245 case ISD::STRICT_FSINH: return "strict_fsinh";
246 case ISD::FCOSH: return "fcosh";
247 case ISD::STRICT_FCOSH: return "strict_fcosh";
248 case ISD::FTANH: return "ftanh";
249 case ISD::STRICT_FTANH: return "strict_ftanh";
250 case ISD::FTRUNC: return "ftrunc";
251 case ISD::STRICT_FTRUNC: return "strict_ftrunc";
252 case ISD::FFLOOR: return "ffloor";
253 case ISD::STRICT_FFLOOR: return "strict_ffloor";
254 case ISD::FCEIL: return "fceil";
255 case ISD::STRICT_FCEIL: return "strict_fceil";
256 case ISD::FRINT: return "frint";
257 case ISD::STRICT_FRINT: return "strict_frint";
258 case ISD::FNEARBYINT: return "fnearbyint";
259 case ISD::STRICT_FNEARBYINT: return "strict_fnearbyint";
260 case ISD::FROUND: return "fround";
261 case ISD::STRICT_FROUND: return "strict_fround";
262 case ISD::FROUNDEVEN: return "froundeven";
263 case ISD::STRICT_FROUNDEVEN: return "strict_froundeven";
264 case ISD::FEXP: return "fexp";
265 case ISD::STRICT_FEXP: return "strict_fexp";
266 case ISD::FEXP2: return "fexp2";
267 case ISD::STRICT_FEXP2: return "strict_fexp2";
268 case ISD::FEXP10: return "fexp10";
269 case ISD::FLOG: return "flog";
270 case ISD::STRICT_FLOG: return "strict_flog";
271 case ISD::FLOG2: return "flog2";
272 case ISD::STRICT_FLOG2: return "strict_flog2";
273 case ISD::FLOG10: return "flog10";
274 case ISD::STRICT_FLOG10: return "strict_flog10";
275
276 // Binary operators
277 case ISD::ADD: return "add";
278 case ISD::PTRADD: return "ptradd";
279 case ISD::SUB: return "sub";
280 case ISD::MUL: return "mul";
281 case ISD::MULHU: return "mulhu";
282 case ISD::MULHS: return "mulhs";
283 case ISD::AVGFLOORU: return "avgflooru";
284 case ISD::AVGFLOORS: return "avgfloors";
285 case ISD::AVGCEILU: return "avgceilu";
286 case ISD::AVGCEILS: return "avgceils";
287 case ISD::ABDS: return "abds";
288 case ISD::ABDU: return "abdu";
289 case ISD::SDIV: return "sdiv";
290 case ISD::UDIV: return "udiv";
291 case ISD::SREM: return "srem";
292 case ISD::UREM: return "urem";
293 case ISD::SMUL_LOHI: return "smul_lohi";
294 case ISD::UMUL_LOHI: return "umul_lohi";
295 case ISD::SDIVREM: return "sdivrem";
296 case ISD::UDIVREM: return "udivrem";
297 case ISD::AND: return "and";
298 case ISD::OR: return "or";
299 case ISD::XOR: return "xor";
300 case ISD::SHL: return "shl";
301 case ISD::SRA: return "sra";
302 case ISD::SRL: return "srl";
303 case ISD::ROTL: return "rotl";
304 case ISD::ROTR: return "rotr";
305 case ISD::FSHL: return "fshl";
306 case ISD::FSHR: return "fshr";
307 case ISD::CLMUL: return "clmul";
308 case ISD::CLMULR: return "clmulr";
309 case ISD::CLMULH: return "clmulh";
310 case ISD::PEXT: return "pext";
311 case ISD::PDEP: return "pdep";
312 case ISD::FADD: return "fadd";
313 case ISD::STRICT_FADD: return "strict_fadd";
314 case ISD::FSUB: return "fsub";
315 case ISD::STRICT_FSUB: return "strict_fsub";
316 case ISD::FMUL: return "fmul";
317 case ISD::STRICT_FMUL: return "strict_fmul";
318 case ISD::FDIV: return "fdiv";
319 case ISD::STRICT_FDIV: return "strict_fdiv";
320 case ISD::FMA: return "fma";
321 case ISD::STRICT_FMA: return "strict_fma";
322 case ISD::FMAD: return "fmad";
323 case ISD::FMULADD: return "fmuladd";
324 case ISD::FREM: return "frem";
325 case ISD::STRICT_FREM: return "strict_frem";
326 case ISD::FCOPYSIGN: return "fcopysign";
327 case ISD::FGETSIGN: return "fgetsign";
328 case ISD::FCANONICALIZE: return "fcanonicalize";
329 case ISD::IS_FPCLASS: return "is_fpclass";
330 case ISD::FPOW: return "fpow";
331 case ISD::STRICT_FPOW: return "strict_fpow";
332 case ISD::SMIN: return "smin";
333 case ISD::SMAX: return "smax";
334 case ISD::UMIN: return "umin";
335 case ISD::UMAX: return "umax";
336 case ISD::SCMP: return "scmp";
337 case ISD::UCMP: return "ucmp";
338
339 case ISD::FLDEXP: return "fldexp";
340 case ISD::STRICT_FLDEXP: return "strict_fldexp";
341 case ISD::FFREXP: return "ffrexp";
342 case ISD::FPOWI: return "fpowi";
343 case ISD::STRICT_FPOWI: return "strict_fpowi";
344 case ISD::SETCC: return "setcc";
345 case ISD::SETCCCARRY: return "setcccarry";
346 case ISD::STRICT_FSETCC: return "strict_fsetcc";
347 case ISD::STRICT_FSETCCS: return "strict_fsetccs";
348 case ISD::FPTRUNC_ROUND: return "fptrunc_round";
349 case ISD::SELECT: return "select";
350 case ISD::VSELECT: return "vselect";
351 case ISD::SELECT_CC: return "select_cc";
352 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
353 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
354 case ISD::CONCAT_VECTORS: return "concat_vectors";
355 case ISD::INSERT_SUBVECTOR: return "insert_subvector";
356 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
357 case ISD::VECTOR_DEINTERLEAVE: return "vector_deinterleave";
358 case ISD::VECTOR_INTERLEAVE: return "vector_interleave";
359 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
360 case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
361 case ISD::VECTOR_SPLICE_LEFT: return "vector_splice_left";
362 case ISD::VECTOR_SPLICE_RIGHT: return "vector_splice_right";
363 case ISD::SPLAT_VECTOR: return "splat_vector";
364 case ISD::SPLAT_VECTOR_PARTS: return "splat_vector_parts";
365 case ISD::VECTOR_REVERSE: return "vector_reverse";
366 case ISD::STEP_VECTOR: return "step_vector";
367 case ISD::CARRY_FALSE: return "carry_false";
368 case ISD::ADDC: return "addc";
369 case ISD::ADDE: return "adde";
370 case ISD::UADDO_CARRY: return "uaddo_carry";
371 case ISD::SADDO_CARRY: return "saddo_carry";
372 case ISD::SADDO: return "saddo";
373 case ISD::UADDO: return "uaddo";
374 case ISD::SSUBO: return "ssubo";
375 case ISD::USUBO: return "usubo";
376 case ISD::SMULO: return "smulo";
377 case ISD::UMULO: return "umulo";
378 case ISD::SUBC: return "subc";
379 case ISD::SUBE: return "sube";
380 case ISD::USUBO_CARRY: return "usubo_carry";
381 case ISD::SSUBO_CARRY: return "ssubo_carry";
382 case ISD::SHL_PARTS: return "shl_parts";
383 case ISD::SRA_PARTS: return "sra_parts";
384 case ISD::SRL_PARTS: return "srl_parts";
385
386 case ISD::SADDSAT: return "saddsat";
387 case ISD::UADDSAT: return "uaddsat";
388 case ISD::SSUBSAT: return "ssubsat";
389 case ISD::USUBSAT: return "usubsat";
390 case ISD::SSHLSAT: return "sshlsat";
391 case ISD::USHLSAT: return "ushlsat";
392
393 case ISD::SMULFIX: return "smulfix";
394 case ISD::SMULFIXSAT: return "smulfixsat";
395 case ISD::UMULFIX: return "umulfix";
396 case ISD::UMULFIXSAT: return "umulfixsat";
397
398 case ISD::SDIVFIX: return "sdivfix";
399 case ISD::SDIVFIXSAT: return "sdivfixsat";
400 case ISD::UDIVFIX: return "udivfix";
401 case ISD::UDIVFIXSAT: return "udivfixsat";
402
403 // Conversion operators.
404 case ISD::SIGN_EXTEND: return "sign_extend";
405 case ISD::ZERO_EXTEND: return "zero_extend";
406 case ISD::ANY_EXTEND: return "any_extend";
407 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
408 case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg";
409 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg";
410 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg";
411 case ISD::TRUNCATE: return "truncate";
412 case ISD::TRUNCATE_SSAT_S: return "truncate_ssat_s";
413 case ISD::TRUNCATE_SSAT_U: return "truncate_ssat_u";
414 case ISD::TRUNCATE_USAT_U: return "truncate_usat_u";
415 case ISD::FP_ROUND: return "fp_round";
416 case ISD::STRICT_FP_ROUND: return "strict_fp_round";
417 case ISD::FP_EXTEND: return "fp_extend";
418 case ISD::STRICT_FP_EXTEND: return "strict_fp_extend";
419
420 case ISD::SINT_TO_FP: return "sint_to_fp";
421 case ISD::STRICT_SINT_TO_FP: return "strict_sint_to_fp";
422 case ISD::UINT_TO_FP: return "uint_to_fp";
423 case ISD::STRICT_UINT_TO_FP: return "strict_uint_to_fp";
424 case ISD::FP_TO_SINT: return "fp_to_sint";
425 case ISD::STRICT_FP_TO_SINT: return "strict_fp_to_sint";
426 case ISD::FP_TO_UINT: return "fp_to_uint";
427 case ISD::STRICT_FP_TO_UINT: return "strict_fp_to_uint";
428 case ISD::FP_TO_SINT_SAT: return "fp_to_sint_sat";
429 case ISD::FP_TO_UINT_SAT: return "fp_to_uint_sat";
430 case ISD::BITCAST: return "bitcast";
431 case ISD::ADDRSPACECAST: return "addrspacecast";
432 case ISD::FP16_TO_FP: return "fp16_to_fp";
433 case ISD::STRICT_FP16_TO_FP: return "strict_fp16_to_fp";
434 case ISD::FP_TO_FP16: return "fp_to_fp16";
435 case ISD::STRICT_FP_TO_FP16: return "strict_fp_to_fp16";
436 case ISD::BF16_TO_FP: return "bf16_to_fp";
437 case ISD::STRICT_BF16_TO_FP: return "strict_bf16_to_fp";
438 case ISD::FP_TO_BF16: return "fp_to_bf16";
439 case ISD::STRICT_FP_TO_BF16: return "strict_fp_to_bf16";
440 case ISD::CONVERT_FROM_ARBITRARY_FP: return "convert_from_arbitrary_fp";
441 case ISD::CONVERT_TO_ARBITRARY_FP: return "convert_to_arbitrary_fp";
442 case ISD::LROUND: return "lround";
443 case ISD::STRICT_LROUND: return "strict_lround";
444 case ISD::LLROUND: return "llround";
445 case ISD::STRICT_LLROUND: return "strict_llround";
446 case ISD::LRINT: return "lrint";
447 case ISD::STRICT_LRINT: return "strict_lrint";
448 case ISD::LLRINT: return "llrint";
449 case ISD::STRICT_LLRINT: return "strict_llrint";
450
451 // Control flow instructions
452 case ISD::BR: return "br";
453 case ISD::BRIND: return "brind";
454 case ISD::BR_JT: return "br_jt";
455 case ISD::BRCOND: return "brcond";
456 case ISD::BR_CC: return "br_cc";
457 case ISD::CALLSEQ_START: return "callseq_start";
458 case ISD::CALLSEQ_END: return "callseq_end";
459
460 // EH instructions
461 case ISD::CATCHRET: return "catchret";
462 case ISD::CLEANUPRET: return "cleanupret";
463
464 // Other operators
465 case ISD::LOAD: return "load";
466 case ISD::STORE: return "store";
467 case ISD::MLOAD: return "masked_load";
468 case ISD::MSTORE: return "masked_store";
469 case ISD::MGATHER: return "masked_gather";
470 case ISD::MSCATTER: return "masked_scatter";
471 case ISD::VECTOR_COMPRESS: return "vector_compress";
472 case ISD::VAARG: return "vaarg";
473 case ISD::VACOPY: return "vacopy";
474 case ISD::VAEND: return "vaend";
475 case ISD::VASTART: return "vastart";
476 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc";
477 case ISD::EXTRACT_ELEMENT: return "extract_element";
478 case ISD::BUILD_PAIR: return "build_pair";
479 case ISD::STACKSAVE: return "stacksave";
480 case ISD::STACKRESTORE: return "stackrestore";
481 case ISD::TRAP: return "trap";
482 case ISD::DEBUGTRAP: return "debugtrap";
483 case ISD::UBSANTRAP: return "ubsantrap";
484 case ISD::LIFETIME_START: return "lifetime.start";
485 case ISD::LIFETIME_END: return "lifetime.end";
486 case ISD::FAKE_USE:
487 return "fake_use";
488 case ISD::RELOC_NONE:
489 return "reloc_none";
490 case ISD::COND_LOOP:
491 return "cond_loop";
492 case ISD::PSEUDO_PROBE:
493 return "pseudoprobe";
494 case ISD::GC_TRANSITION_START: return "gc_transition.start";
495 case ISD::GC_TRANSITION_END: return "gc_transition.end";
496 case ISD::GET_DYNAMIC_AREA_OFFSET: return "get.dynamic.area.offset";
497 case ISD::FREEZE: return "freeze";
498 case ISD::PREALLOCATED_SETUP:
499 return "call_setup";
500 case ISD::PREALLOCATED_ARG:
501 return "call_alloc";
502
503 // Floating point environment manipulation
504 case ISD::GET_ROUNDING: return "get_rounding";
505 case ISD::SET_ROUNDING: return "set_rounding";
506 case ISD::GET_FPENV: return "get_fpenv";
507 case ISD::SET_FPENV: return "set_fpenv";
508 case ISD::RESET_FPENV: return "reset_fpenv";
509 case ISD::GET_FPENV_MEM: return "get_fpenv_mem";
510 case ISD::SET_FPENV_MEM: return "set_fpenv_mem";
511 case ISD::GET_FPMODE: return "get_fpmode";
512 case ISD::SET_FPMODE: return "set_fpmode";
513 case ISD::RESET_FPMODE: return "reset_fpmode";
514
515 // Convergence control instructions
516 case ISD::CONVERGENCECTRL_ANCHOR: return "convergencectrl_anchor";
517 case ISD::CONVERGENCECTRL_ENTRY: return "convergencectrl_entry";
518 case ISD::CONVERGENCECTRL_LOOP: return "convergencectrl_loop";
519 case ISD::CONVERGENCECTRL_GLUE: return "convergencectrl_glue";
520
521 // Bit manipulation
522 case ISD::ABS: return "abs";
523 case ISD::ABS_MIN_POISON: return "abs_min_poison";
524 case ISD::BITREVERSE: return "bitreverse";
525 case ISD::BSWAP: return "bswap";
526 case ISD::CTPOP: return "ctpop";
527 case ISD::CTTZ: return "cttz";
528 case ISD::CTTZ_ZERO_POISON: return "cttz_zero_poison";
529 case ISD::CTLZ: return "ctlz";
530 case ISD::CTLZ_ZERO_POISON: return "ctlz_zero_poison";
531 case ISD::CTLS: return "ctls";
532 case ISD::PARITY: return "parity";
533
534 // Trampolines
535 case ISD::INIT_TRAMPOLINE: return "init_trampoline";
536 case ISD::ADJUST_TRAMPOLINE: return "adjust_trampoline";
537
538 // clang-format on
539
540 case ISD::CONDCODE:
541 switch (cast<CondCodeSDNode>(Val: this)->get()) {
542 default: llvm_unreachable("Unknown setcc condition!");
543 case ISD::SETOEQ: return "setoeq";
544 case ISD::SETOGT: return "setogt";
545 case ISD::SETOGE: return "setoge";
546 case ISD::SETOLT: return "setolt";
547 case ISD::SETOLE: return "setole";
548 case ISD::SETONE: return "setone";
549
550 case ISD::SETO: return "seto";
551 case ISD::SETUO: return "setuo";
552 case ISD::SETUEQ: return "setueq";
553 case ISD::SETUGT: return "setugt";
554 case ISD::SETUGE: return "setuge";
555 case ISD::SETULT: return "setult";
556 case ISD::SETULE: return "setule";
557 case ISD::SETUNE: return "setune";
558
559 case ISD::SETEQ: return "seteq";
560 case ISD::SETGT: return "setgt";
561 case ISD::SETGE: return "setge";
562 case ISD::SETLT: return "setlt";
563 case ISD::SETLE: return "setle";
564 case ISD::SETNE: return "setne";
565
566 case ISD::SETTRUE: return "settrue";
567 case ISD::SETTRUE2: return "settrue2";
568 case ISD::SETFALSE: return "setfalse";
569 case ISD::SETFALSE2: return "setfalse2";
570 }
571 case ISD::VECREDUCE_FADD: return "vecreduce_fadd";
572 case ISD::VECREDUCE_SEQ_FADD: return "vecreduce_seq_fadd";
573 case ISD::VECREDUCE_FMUL: return "vecreduce_fmul";
574 case ISD::VECREDUCE_SEQ_FMUL: return "vecreduce_seq_fmul";
575 case ISD::VECREDUCE_ADD: return "vecreduce_add";
576 case ISD::VECREDUCE_MUL: return "vecreduce_mul";
577 case ISD::VECREDUCE_AND: return "vecreduce_and";
578 case ISD::VECREDUCE_OR: return "vecreduce_or";
579 case ISD::VECREDUCE_XOR: return "vecreduce_xor";
580 case ISD::VECREDUCE_SMAX: return "vecreduce_smax";
581 case ISD::VECREDUCE_SMIN: return "vecreduce_smin";
582 case ISD::VECREDUCE_UMAX: return "vecreduce_umax";
583 case ISD::VECREDUCE_UMIN: return "vecreduce_umin";
584 case ISD::VECREDUCE_FMAX: return "vecreduce_fmax";
585 case ISD::VECREDUCE_FMIN: return "vecreduce_fmin";
586 case ISD::VECREDUCE_FMAXIMUM: return "vecreduce_fmaximum";
587 case ISD::VECREDUCE_FMINIMUM: return "vecreduce_fminimum";
588 case ISD::STACKMAP:
589 return "stackmap";
590 case ISD::PATCHPOINT:
591 return "patchpoint";
592 case ISD::CLEAR_CACHE:
593 return "clear_cache";
594
595 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
596 return "histogram";
597
598 case ISD::CTTZ_ELTS:
599 return "cttz_elts";
600 case ISD::CTTZ_ELTS_ZERO_POISON:
601 return "cttz_elts_zero_poison";
602
603 case ISD::VECTOR_FIND_LAST_ACTIVE:
604 return "find_last_active";
605
606 case ISD::GET_ACTIVE_LANE_MASK:
607 return "get_active_lane_mask";
608
609 case ISD::PARTIAL_REDUCE_UMLA:
610 return "partial_reduce_umla";
611 case ISD::PARTIAL_REDUCE_SMLA:
612 return "partial_reduce_smla";
613 case ISD::PARTIAL_REDUCE_SUMLA:
614 return "partial_reduce_sumla";
615 case ISD::PARTIAL_REDUCE_FMLA:
616 return "partial_reduce_fmla";
617 case ISD::LOOP_DEPENDENCE_WAR_MASK:
618 return "loop_dep_war";
619 case ISD::LOOP_DEPENDENCE_RAW_MASK:
620 return "loop_dep_raw";
621 case ISD::MASKED_UDIV:
622 return "masked_udiv";
623 case ISD::MASKED_SDIV:
624 return "masked_sdiv";
625 case ISD::MASKED_UREM:
626 return "masked_urem";
627 case ISD::MASKED_SREM:
628 return "masked_srem";
629
630 // Vector Predication
631#define BEGIN_REGISTER_VP_SDNODE(SDID, LEGALARG, NAME, ...) \
632 case ISD::SDID: \
633 return #NAME;
634#include "llvm/IR/VPIntrinsics.def"
635 }
636}
637
638const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
639 switch (AM) {
640 default: return "";
641 case ISD::PRE_INC: return "<pre-inc>";
642 case ISD::PRE_DEC: return "<pre-dec>";
643 case ISD::POST_INC: return "<post-inc>";
644 case ISD::POST_DEC: return "<post-dec>";
645 }
646}
647
648static Printable PrintNodeId(const SDNode &Node) {
649 return Printable([&Node](raw_ostream &OS) {
650#ifndef NDEBUG
651 static const raw_ostream::Colors Color[] = {
652 raw_ostream::BLACK, raw_ostream::RED, raw_ostream::GREEN,
653 raw_ostream::YELLOW, raw_ostream::BLUE, raw_ostream::MAGENTA,
654 raw_ostream::CYAN,
655 };
656 OS.changeColor(Color[Node.PersistentId % std::size(Color)]);
657 OS << 't' << Node.PersistentId;
658 OS.resetColor();
659#else
660 OS << (const void*)&Node;
661#endif
662 });
663}
664
665// Print the MMO with more information from the SelectionDAG.
666static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO,
667 const MachineFunction *MF, const Module *M,
668 const MachineFrameInfo *MFI,
669 const TargetInstrInfo *TII, LLVMContext &Ctx) {
670 ModuleSlotTracker MST(M);
671 if (MF)
672 MST.incorporateFunction(F: MF->getFunction());
673 SmallVector<StringRef, 0> SSNs;
674 MMO.print(OS, MST, SSNs, Context: Ctx, MFI, TII);
675}
676
677static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO,
678 const SelectionDAG *G) {
679 if (G) {
680 const MachineFunction *MF = &G->getMachineFunction();
681 return printMemOperand(OS, MMO, MF, M: MF->getFunction().getParent(),
682 MFI: &MF->getFrameInfo(),
683 TII: G->getSubtarget().getInstrInfo(), Ctx&: *G->getContext());
684 }
685
686 LLVMContext Ctx;
687 return printMemOperand(OS, MMO, /*MF=*/nullptr, /*M=*/nullptr,
688 /*MFI=*/nullptr, /*TII=*/nullptr, Ctx);
689}
690
691#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
692LLVM_DUMP_METHOD void SDNode::dump() const { dump(nullptr); }
693
694LLVM_DUMP_METHOD void SDNode::dump(const SelectionDAG *G) const {
695 print(dbgs(), G);
696 dbgs() << '\n';
697}
698#endif
699
700void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
701 for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
702 if (i) OS << ",";
703 if (getValueType(ResNo: i) == MVT::Other)
704 OS << "ch";
705 else
706 OS << getValueType(ResNo: i).getEVTString();
707 }
708}
709
710void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
711 if (getFlags().hasNoUnsignedWrap())
712 OS << " nuw";
713
714 if (getFlags().hasNoSignedWrap())
715 OS << " nsw";
716
717 if (getFlags().hasExact())
718 OS << " exact";
719
720 if (getFlags().hasDisjoint())
721 OS << " disjoint";
722
723 if (getFlags().hasSameSign())
724 OS << " samesign";
725
726 if (getFlags().hasInBounds())
727 OS << " inbounds";
728
729 if (getFlags().hasNonNeg())
730 OS << " nneg";
731
732 if (getFlags().hasNoNaNs())
733 OS << " nnan";
734
735 if (getFlags().hasNoInfs())
736 OS << " ninf";
737
738 if (getFlags().hasNoSignedZeros())
739 OS << " nsz";
740
741 if (getFlags().hasAllowReciprocal())
742 OS << " arcp";
743
744 if (getFlags().hasAllowContract())
745 OS << " contract";
746
747 if (getFlags().hasApproximateFuncs())
748 OS << " afn";
749
750 if (getFlags().hasAllowReassociation())
751 OS << " reassoc";
752
753 if (getFlags().hasNoFPExcept())
754 OS << " nofpexcept";
755
756 if (getFlags().hasNoConvergent())
757 OS << " noconvergent";
758
759 if (const MachineSDNode *MN = dyn_cast<MachineSDNode>(Val: this)) {
760 if (!MN->memoperands_empty()) {
761 OS << "<";
762 OS << "Mem:";
763 for (MachineSDNode::mmo_iterator i = MN->memoperands_begin(),
764 e = MN->memoperands_end(); i != e; ++i) {
765 printMemOperand(OS, MMO: **i, G);
766 if (std::next(x: i) != e)
767 OS << " ";
768 }
769 OS << ">";
770 }
771 } else if (const ShuffleVectorSDNode *SVN =
772 dyn_cast<ShuffleVectorSDNode>(Val: this)) {
773 OS << "<";
774 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
775 int Idx = SVN->getMaskElt(Idx: i);
776 if (i) OS << ",";
777 if (Idx < 0)
778 OS << "u";
779 else
780 OS << Idx;
781 }
782 OS << ">";
783 } else if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(Val: this)) {
784 OS << '<' << CSDN->getAPIntValue() << '>';
785 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(Val: this)) {
786 if (&CSDN->getValueAPF().getSemantics() == &APFloat::IEEEsingle())
787 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>';
788 else if (&CSDN->getValueAPF().getSemantics() == &APFloat::IEEEdouble())
789 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>';
790 else {
791 OS << "<APFloat(";
792 CSDN->getValueAPF().bitcastToAPInt().print(OS, isSigned: false);
793 OS << ")>";
794 }
795 } else if (const GlobalAddressSDNode *GADN =
796 dyn_cast<GlobalAddressSDNode>(Val: this)) {
797 int64_t offset = GADN->getOffset();
798 OS << '<';
799 GADN->getGlobal()->printAsOperand(O&: OS);
800 OS << '>';
801 if (offset > 0)
802 OS << " + " << offset;
803 else
804 OS << " " << offset;
805 if (unsigned int TF = GADN->getTargetFlags())
806 OS << " [TF=" << TF << ']';
807 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(Val: this)) {
808 OS << "<" << FIDN->getIndex() << ">";
809 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(Val: this)) {
810 OS << "<" << JTDN->getIndex() << ">";
811 if (unsigned int TF = JTDN->getTargetFlags())
812 OS << " [TF=" << TF << ']';
813 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val: this)){
814 int offset = CP->getOffset();
815 if (CP->isMachineConstantPoolEntry())
816 OS << "<" << *CP->getMachineCPVal() << ">";
817 else
818 OS << "<" << *CP->getConstVal() << ">";
819 if (offset > 0)
820 OS << " + " << offset;
821 else
822 OS << " " << offset;
823 if (unsigned int TF = CP->getTargetFlags())
824 OS << " [TF=" << TF << ']';
825 } else if (const TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Val: this)) {
826 OS << "<" << TI->getIndex() << '+' << TI->getOffset() << ">";
827 if (unsigned TF = TI->getTargetFlags())
828 OS << " [TF=" << TF << ']';
829 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(Val: this)) {
830 OS << "<";
831 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
832 if (LBB)
833 OS << LBB->getName() << " ";
834 OS << (const void*)BBDN->getBasicBlock() << ">";
835 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val: this)) {
836 OS << ' ' << printReg(Reg: R->getReg(),
837 TRI: G ? G->getSubtarget().getRegisterInfo() : nullptr);
838 } else if (const ExternalSymbolSDNode *ES =
839 dyn_cast<ExternalSymbolSDNode>(Val: this)) {
840 OS << "'" << ES->getSymbol() << "'";
841 if (unsigned int TF = ES->getTargetFlags())
842 OS << " [TF=" << TF << ']';
843 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(Val: this)) {
844 if (M->getValue())
845 OS << "<" << M->getValue() << ">";
846 else
847 OS << "<null>";
848 } else if (const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Val: this)) {
849 if (MD->getMD())
850 OS << "<" << MD->getMD() << ">";
851 else
852 OS << "<null>";
853 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(Val: this)) {
854 OS << ":" << N->getVT();
855 }
856 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: this)) {
857 OS << "<";
858
859 printMemOperand(OS, MMO: *LD->getMemOperand(), G);
860
861 bool doExt = true;
862 switch (LD->getExtensionType()) {
863 default: doExt = false; break;
864 case ISD::EXTLOAD: OS << ", anyext"; break;
865 case ISD::SEXTLOAD: OS << ", sext"; break;
866 case ISD::ZEXTLOAD: OS << ", zext"; break;
867 }
868 if (doExt)
869 OS << " from " << LD->getMemoryVT();
870
871 const char *AM = getIndexedModeName(AM: LD->getAddressingMode());
872 if (*AM)
873 OS << ", " << AM;
874
875 OS << ">";
876 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: this)) {
877 OS << "<";
878 printMemOperand(OS, MMO: *ST->getMemOperand(), G);
879
880 if (ST->isTruncatingStore())
881 OS << ", trunc to " << ST->getMemoryVT();
882
883 const char *AM = getIndexedModeName(AM: ST->getAddressingMode());
884 if (*AM)
885 OS << ", " << AM;
886
887 OS << ">";
888 } else if (const MaskedLoadSDNode *MLd = dyn_cast<MaskedLoadSDNode>(Val: this)) {
889 OS << "<";
890
891 printMemOperand(OS, MMO: *MLd->getMemOperand(), G);
892
893 bool doExt = true;
894 switch (MLd->getExtensionType()) {
895 default: doExt = false; break;
896 case ISD::EXTLOAD: OS << ", anyext"; break;
897 case ISD::SEXTLOAD: OS << ", sext"; break;
898 case ISD::ZEXTLOAD: OS << ", zext"; break;
899 }
900 if (doExt)
901 OS << " from " << MLd->getMemoryVT();
902
903 const char *AM = getIndexedModeName(AM: MLd->getAddressingMode());
904 if (*AM)
905 OS << ", " << AM;
906
907 if (MLd->isExpandingLoad())
908 OS << ", expanding";
909
910 OS << ">";
911 } else if (const MaskedStoreSDNode *MSt = dyn_cast<MaskedStoreSDNode>(Val: this)) {
912 OS << "<";
913 printMemOperand(OS, MMO: *MSt->getMemOperand(), G);
914
915 if (MSt->isTruncatingStore())
916 OS << ", trunc to " << MSt->getMemoryVT();
917
918 const char *AM = getIndexedModeName(AM: MSt->getAddressingMode());
919 if (*AM)
920 OS << ", " << AM;
921
922 if (MSt->isCompressingStore())
923 OS << ", compressing";
924
925 OS << ">";
926 } else if (const auto *MGather = dyn_cast<MaskedGatherSDNode>(Val: this)) {
927 OS << "<";
928 printMemOperand(OS, MMO: *MGather->getMemOperand(), G);
929
930 bool doExt = true;
931 switch (MGather->getExtensionType()) {
932 default: doExt = false; break;
933 case ISD::EXTLOAD: OS << ", anyext"; break;
934 case ISD::SEXTLOAD: OS << ", sext"; break;
935 case ISD::ZEXTLOAD: OS << ", zext"; break;
936 }
937 if (doExt)
938 OS << " from " << MGather->getMemoryVT();
939
940 auto Signed = MGather->isIndexSigned() ? "signed" : "unsigned";
941 auto Scaled = MGather->isIndexScaled() ? "scaled" : "unscaled";
942 OS << ", " << Signed << " " << Scaled << " offset";
943
944 OS << ">";
945 } else if (const auto *MScatter = dyn_cast<MaskedScatterSDNode>(Val: this)) {
946 OS << "<";
947 printMemOperand(OS, MMO: *MScatter->getMemOperand(), G);
948
949 if (MScatter->isTruncatingStore())
950 OS << ", trunc to " << MScatter->getMemoryVT();
951
952 auto Signed = MScatter->isIndexSigned() ? "signed" : "unsigned";
953 auto Scaled = MScatter->isIndexScaled() ? "scaled" : "unscaled";
954 OS << ", " << Signed << " " << Scaled << " offset";
955
956 OS << ">";
957 } else if (const MemSDNode *M = dyn_cast<MemSDNode>(Val: this)) {
958 OS << "<";
959 interleaveComma(c: M->memoperands(), os&: OS, each_fn: [&](const MachineMemOperand *MMO) {
960 printMemOperand(OS, MMO: *MMO, G);
961 });
962 if (auto *A = dyn_cast<AtomicSDNode>(Val: M))
963 if (A->getOpcode() == ISD::ATOMIC_LOAD) {
964 bool doExt = true;
965 switch (A->getExtensionType()) {
966 default: doExt = false; break;
967 case ISD::EXTLOAD: OS << ", anyext"; break;
968 case ISD::SEXTLOAD: OS << ", sext"; break;
969 case ISD::ZEXTLOAD: OS << ", zext"; break;
970 }
971 if (doExt)
972 OS << " from " << A->getMemoryVT();
973 }
974 OS << ">";
975 } else if (const BlockAddressSDNode *BA =
976 dyn_cast<BlockAddressSDNode>(Val: this)) {
977 int64_t offset = BA->getOffset();
978 OS << "<";
979 BA->getBlockAddress()->getFunction()->printAsOperand(O&: OS, PrintType: false);
980 OS << ", ";
981 BA->getBlockAddress()->getBasicBlock()->printAsOperand(O&: OS, PrintType: false);
982 OS << ">";
983 if (offset > 0)
984 OS << " + " << offset;
985 else
986 OS << " " << offset;
987 if (unsigned int TF = BA->getTargetFlags())
988 OS << " [TF=" << TF << ']';
989 } else if (const AddrSpaceCastSDNode *ASC =
990 dyn_cast<AddrSpaceCastSDNode>(Val: this)) {
991 OS << '['
992 << ASC->getSrcAddressSpace()
993 << " -> "
994 << ASC->getDestAddressSpace()
995 << ']';
996 } else if (const auto *AA = dyn_cast<AssertAlignSDNode>(Val: this)) {
997 OS << '<' << AA->getAlign().value() << '>';
998 }
999
1000 if (VerboseDAGDumping) {
1001 if (unsigned Order = getIROrder())
1002 OS << " [ORD=" << Order << ']';
1003
1004 if (getNodeId() != -1)
1005 OS << " [ID=" << getNodeId() << ']';
1006 if (!(isa<ConstantSDNode>(Val: this) || (isa<ConstantFPSDNode>(Val: this))))
1007 OS << " # D:" << isDivergent();
1008
1009 if (G && !G->GetDbgValues(SD: this).empty()) {
1010 OS << " [NoOfDbgValues=" << G->GetDbgValues(SD: this).size() << ']';
1011 for (SDDbgValue *Dbg : G->GetDbgValues(SD: this))
1012 if (!Dbg->isInvalidated())
1013 Dbg->print(OS);
1014 } else if (getHasDebugValue())
1015 OS << " [NoOfDbgValues>0]";
1016
1017 if (const auto *MD = G ? G->getPCSections(Node: this) : nullptr) {
1018 OS << " [pcsections ";
1019 MD->printAsOperand(OS, M: G->getMachineFunction().getFunction().getParent());
1020 OS << ']';
1021 }
1022
1023 if (MDNode *MMRA = G ? G->getMMRAMetadata(Node: this) : nullptr) {
1024 OS << " [mmra ";
1025 MMRA->printAsOperand(OS,
1026 M: G->getMachineFunction().getFunction().getParent());
1027 OS << ']';
1028 }
1029 }
1030}
1031
1032LLVM_DUMP_METHOD void SDDbgValue::print(raw_ostream &OS) const {
1033 OS << " DbgVal(Order=" << getOrder() << ')';
1034 if (isInvalidated())
1035 OS << "(Invalidated)";
1036 if (isEmitted())
1037 OS << "(Emitted)";
1038 OS << "(";
1039 bool Comma = false;
1040 for (const SDDbgOperand &Op : getLocationOps()) {
1041 if (Comma)
1042 OS << ", ";
1043 switch (Op.getKind()) {
1044 case SDDbgOperand::SDNODE:
1045 if (Op.getSDNode())
1046 OS << "SDNODE=" << PrintNodeId(Node: *Op.getSDNode()) << ':' << Op.getResNo();
1047 else
1048 OS << "SDNODE";
1049 break;
1050 case SDDbgOperand::CONST:
1051 OS << "CONST";
1052 break;
1053 case SDDbgOperand::FRAMEIX:
1054 OS << "FRAMEIX=" << Op.getFrameIx();
1055 break;
1056 case SDDbgOperand::VREG:
1057 OS << "VREG=" << printReg(Reg: Op.getVReg());
1058 break;
1059 }
1060 Comma = true;
1061 }
1062 OS << ")";
1063 if (isIndirect()) OS << "(Indirect)";
1064 if (isVariadic())
1065 OS << "(Variadic)";
1066 OS << ":\"" << Var->getName() << '"';
1067#ifndef NDEBUG
1068 if (Expr->getNumElements())
1069 Expr->dump();
1070#endif
1071}
1072
1073#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1074LLVM_DUMP_METHOD void SDDbgValue::dump() const {
1075 if (isInvalidated())
1076 return;
1077 print(dbgs());
1078 dbgs() << "\n";
1079}
1080#endif
1081
1082/// Return true if this node is so simple that we should just print it inline
1083/// if it appears as an operand.
1084static bool shouldPrintInline(const SDNode &Node, const SelectionDAG *G) {
1085 // Avoid lots of cluttering when inline printing nodes with associated
1086 // DbgValues in verbose mode.
1087 if (VerboseDAGDumping && G && !G->GetDbgValues(SD: &Node).empty())
1088 return false;
1089 if (Node.getOpcode() == ISD::EntryToken)
1090 return false;
1091 return Node.getNumOperands() == 0;
1092}
1093
1094#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1095static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
1096 for (const SDValue &Op : N->op_values()) {
1097 if (shouldPrintInline(*Op.getNode(), G))
1098 continue;
1099 if (Op.getNode()->hasOneUse())
1100 DumpNodes(Op.getNode(), indent+2, G);
1101 }
1102
1103 dbgs().indent(indent);
1104 N->dump(G);
1105}
1106
1107LLVM_DUMP_METHOD void SelectionDAG::dump() const { dump(false); }
1108
1109LLVM_DUMP_METHOD void SelectionDAG::dump(bool Sorted) const {
1110 dbgs() << "SelectionDAG has " << AllNodes.size() << " nodes:\n";
1111
1112 auto dumpEachNode = [this](const SDNode &N) {
1113 if (!N.hasOneUse() && &N != getRoot().getNode() &&
1114 (!shouldPrintInline(N, this) || N.use_empty()))
1115 DumpNodes(&N, 2, this);
1116 };
1117
1118 if (Sorted) {
1119 SmallVector<const SDNode *> SortedNodes;
1120 SortedNodes.reserve(AllNodes.size());
1121 getTopologicallyOrderedNodes(SortedNodes);
1122 for (const SDNode *N : SortedNodes)
1123 dumpEachNode(*N);
1124 } else {
1125 for (const SDNode &N : allnodes())
1126 dumpEachNode(N);
1127 }
1128
1129 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
1130 dbgs() << "\n";
1131
1132 if (VerboseDAGDumping) {
1133 if (DbgBegin() != DbgEnd())
1134 dbgs() << "SDDbgValues:\n";
1135 for (auto *Dbg : make_range(DbgBegin(), DbgEnd()))
1136 Dbg->dump();
1137 if (ByvalParmDbgBegin() != ByvalParmDbgEnd())
1138 dbgs() << "Byval SDDbgValues:\n";
1139 for (auto *Dbg : make_range(ByvalParmDbgBegin(), ByvalParmDbgEnd()))
1140 Dbg->dump();
1141 }
1142 dbgs() << "\n";
1143}
1144#endif
1145
1146void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
1147 OS << PrintNodeId(Node: *this) << ": ";
1148 print_types(OS, G);
1149 OS << " = " << getOperationName(G);
1150 print_details(OS, G);
1151}
1152
1153static bool printOperand(raw_ostream &OS, const SelectionDAG *G,
1154 const SDValue Value) {
1155 if (!Value.getNode()) {
1156 OS << "<null>";
1157 return false;
1158 }
1159
1160 if (shouldPrintInline(Node: *Value.getNode(), G)) {
1161 OS << Value->getOperationName(G) << ':';
1162 Value->print_types(OS, G);
1163 Value->print_details(OS, G);
1164 return true;
1165 }
1166
1167 OS << PrintNodeId(Node: *Value.getNode());
1168 if (unsigned RN = Value.getResNo())
1169 OS << ':' << RN;
1170 return false;
1171}
1172
1173#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1174using VisitedSDNodeSet = SmallPtrSet<const SDNode *, 32>;
1175
1176static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
1177 const SelectionDAG *G, VisitedSDNodeSet &once) {
1178 if (!once.insert(N).second) // If we've been here before, return now.
1179 return;
1180
1181 // Dump the current SDNode, but don't end the line yet.
1182 OS.indent(indent);
1183 N->printr(OS, G);
1184
1185 // Having printed this SDNode, walk the children:
1186 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1187 if (i) OS << ",";
1188 OS << " ";
1189
1190 const SDValue Op = N->getOperand(i);
1191 bool printedInline = printOperand(OS, G, Op);
1192 if (printedInline)
1193 once.insert(Op.getNode());
1194 }
1195
1196 OS << "\n";
1197
1198 // Dump children that have grandchildren on their own line(s).
1199 for (const SDValue &Op : N->op_values())
1200 DumpNodesr(OS, Op.getNode(), indent+2, G, once);
1201}
1202
1203LLVM_DUMP_METHOD void SDNode::dumpr() const {
1204 VisitedSDNodeSet once;
1205 DumpNodesr(dbgs(), this, 0, nullptr, once);
1206}
1207
1208LLVM_DUMP_METHOD void SDNode::dumpr(const SelectionDAG *G) const {
1209 VisitedSDNodeSet once;
1210 DumpNodesr(dbgs(), this, 0, G, once);
1211}
1212#endif
1213
1214static void printrWithDepthHelper(raw_ostream &OS, const SDNode *N,
1215 const SelectionDAG *G, unsigned depth,
1216 unsigned indent) {
1217 if (depth == 0)
1218 return;
1219
1220 OS.indent(NumSpaces: indent);
1221
1222 N->print(OS, G);
1223
1224 for (const SDValue &Op : N->op_values()) {
1225 // Don't follow chain operands.
1226 if (Op.getValueType() == MVT::Other)
1227 continue;
1228 // Don't print children that were fully rendered inline.
1229 if (shouldPrintInline(Node: *Op.getNode(), G))
1230 continue;
1231 OS << '\n';
1232 printrWithDepthHelper(OS, N: Op.getNode(), G, depth: depth - 1, indent: indent + 2);
1233 }
1234}
1235
1236void SDNode::printrWithDepth(raw_ostream &OS, const SelectionDAG *G,
1237 unsigned depth) const {
1238 printrWithDepthHelper(OS, N: this, G, depth, indent: 0);
1239}
1240
1241void SDNode::printrFull(raw_ostream &OS, const SelectionDAG *G) const {
1242 // Don't print impossibly deep things.
1243 printrWithDepth(OS, G, depth: 10);
1244}
1245
1246#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1247LLVM_DUMP_METHOD
1248void SDNode::dumprWithDepth(const SelectionDAG *G, unsigned depth) const {
1249 printrWithDepth(dbgs(), G, depth);
1250}
1251
1252LLVM_DUMP_METHOD void SDNode::dumprFull(const SelectionDAG *G) const {
1253 // Don't print impossibly deep things.
1254 dumprWithDepth(G, 10);
1255}
1256#endif
1257
1258void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
1259 printr(OS, G);
1260 // Under VerboseDAGDumping divergence will be printed always.
1261 if (isDivergent() && !VerboseDAGDumping)
1262 OS << " # D:1";
1263 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1264 if (i) OS << ", "; else OS << " ";
1265 printOperand(OS, G, Value: getOperand(Num: i));
1266 }
1267 if (DebugLoc DL = getDebugLoc()) {
1268 OS << ", ";
1269 DL.print(OS);
1270 }
1271 if (PrintSDNodeAddrs)
1272 OS << " ; " << this;
1273}
1274