1//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the TargetRegisterInfo interface.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/TargetRegisterInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallSet.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/BinaryFormat/Dwarf.h"
20#include "llvm/CodeGen/LiveInterval.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/TargetFrameLowering.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/CodeGen/VirtRegMap.h"
28#include "llvm/CodeGenTypes/MachineValueType.h"
29#include "llvm/Config/llvm-config.h"
30#include "llvm/IR/Attributes.h"
31#include "llvm/IR/DebugInfoMetadata.h"
32#include "llvm/IR/Function.h"
33#include "llvm/MC/MCRegisterInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Compiler.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/Printable.h"
38#include "llvm/Support/raw_ostream.h"
39#include <cassert>
40#include <utility>
41
42#define DEBUG_TYPE "target-reg-info"
43
44using namespace llvm;
45
46static cl::opt<unsigned>
47 HugeSizeForSplit("huge-size-for-split", cl::Hidden,
48 cl::desc("A threshold of live range size which may cause "
49 "high compile time cost in global splitting."),
50 cl::init(Val: 5000));
51
52TargetRegisterInfo::TargetRegisterInfo(
53 const TargetRegisterInfoDesc *ID, const char *SubRegIndexStrings,
54 ArrayRef<uint32_t> SubRegIndexNameOffsets,
55 const SubRegCoveredBits *SubRegIdxRanges,
56 const LaneBitmask *SubRegIndexLaneMasks, LaneBitmask CoveringLanes,
57 const RegClassInfo *const RCInfos,
58 const MVT::SimpleValueType *const RCVTLists, unsigned Mode)
59 : InfoDesc(ID), SubRegIndexStrings(SubRegIndexStrings),
60 SubRegIndexNameOffsets(SubRegIndexNameOffsets),
61 SubRegIdxRanges(SubRegIdxRanges),
62 SubRegIndexLaneMasks(SubRegIndexLaneMasks), CoveringLanes(CoveringLanes),
63 RCInfos(RCInfos), RCVTLists(RCVTLists), HwMode(Mode) {}
64
65TargetRegisterInfo::~TargetRegisterInfo() = default;
66
67bool TargetRegisterInfo::shouldRegionSplitForVirtReg(
68 const MachineFunction &MF, const LiveInterval &VirtReg) const {
69 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
70 const MachineRegisterInfo &MRI = MF.getRegInfo();
71 MachineInstr *MI = MRI.getUniqueVRegDef(Reg: VirtReg.reg());
72 if (MI && TII->isTriviallyReMaterializable(MI: *MI) &&
73 VirtReg.size() > HugeSizeForSplit)
74 return false;
75 return true;
76}
77
78void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,
79 MCRegister Reg) const {
80 for (MCPhysReg SR : superregs_inclusive(Reg))
81 RegisterSet.set(SR);
82}
83
84bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
85 ArrayRef<MCPhysReg> Exceptions) const {
86 // Check that all super registers of reserved regs are reserved as well.
87 BitVector Checked(getNumRegs());
88 for (unsigned Reg : RegisterSet.set_bits()) {
89 if (Checked[Reg])
90 continue;
91 for (MCPhysReg SR : superregs(Reg)) {
92 if (!RegisterSet[SR] && !is_contained(Range&: Exceptions, Element: Reg)) {
93 dbgs() << "Error: Super register " << printReg(Reg: SR, TRI: this)
94 << " of reserved register " << printReg(Reg, TRI: this)
95 << " is not reserved.\n";
96 return false;
97 }
98
99 // We transitively check superregs. So we can remember this for later
100 // to avoid compiletime explosion in deep register hierarchies.
101 Checked.set(SR);
102 }
103 }
104 return true;
105}
106
107Printable llvm::printReg(Register Reg, const TargetRegisterInfo *TRI,
108 unsigned SubIdx, const MachineRegisterInfo *MRI) {
109 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
110 if (!Reg)
111 OS << "$noreg";
112 else if (Reg.isStack())
113 OS << "SS#" << Reg.stackSlotIndex();
114 else if (Reg.isVirtual()) {
115 StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
116 if (Name != "") {
117 OS << '%' << Name;
118 } else {
119 OS << '%' << Reg.virtRegIndex();
120 }
121 } else if (!TRI)
122 OS << '$' << "physreg" << Reg.id();
123 else if (Reg < TRI->getNumRegs()) {
124 OS << '$';
125 printLowerCase(String: TRI->getName(RegNo: Reg), Out&: OS);
126 } else
127 llvm_unreachable("Register kind is unsupported.");
128
129 if (SubIdx) {
130 if (TRI)
131 OS << ':' << TRI->getSubRegIndexName(SubIdx);
132 else
133 OS << ":sub(" << SubIdx << ')';
134 }
135 });
136}
137
138Printable llvm::printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI) {
139 return Printable([Unit, TRI](raw_ostream &OS) {
140 // Generic printout when TRI is missing.
141 if (!TRI) {
142 OS << "Unit~" << static_cast<unsigned>(Unit);
143 return;
144 }
145
146 // Check for invalid register units.
147 if (static_cast<unsigned>(Unit) >= TRI->getNumRegUnits()) {
148 OS << "BadUnit~" << static_cast<unsigned>(Unit);
149 return;
150 }
151
152 // Normal units have at least one root.
153 MCRegUnitRootIterator Roots(Unit, TRI);
154 assert(Roots.isValid() && "Unit has no roots.");
155 OS << TRI->getName(RegNo: *Roots);
156 for (++Roots; Roots.isValid(); ++Roots)
157 OS << '~' << TRI->getName(RegNo: *Roots);
158 });
159}
160
161Printable llvm::printVRegOrUnit(VirtRegOrUnit VRegOrUnit,
162 const TargetRegisterInfo *TRI) {
163 return Printable([VRegOrUnit, TRI](raw_ostream &OS) {
164 if (VRegOrUnit.isVirtualReg()) {
165 OS << '%' << VRegOrUnit.asVirtualReg().virtRegIndex();
166 } else {
167 OS << printRegUnit(Unit: VRegOrUnit.asMCRegUnit(), TRI);
168 }
169 });
170}
171
172Printable llvm::printRegClassOrBank(Register Reg,
173 const MachineRegisterInfo &RegInfo,
174 const TargetRegisterInfo *TRI) {
175 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
176 if (RegInfo.getRegClassOrNull(Reg))
177 OS << StringRef(TRI->getRegClassName(Class: RegInfo.getRegClass(Reg))).lower();
178 else if (RegInfo.getRegBankOrNull(Reg))
179 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
180 else {
181 OS << "_";
182 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
183 "Generic registers must have a valid type");
184 }
185 });
186}
187
188/// getAllocatableClass - Return the maximal subclass of the given register
189/// class that is alloctable, or NULL.
190const TargetRegisterClass *
191TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
192 if (!RC || RC->isAllocatable())
193 return RC;
194
195 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
196 ++It) {
197 const TargetRegisterClass *SubRC = getRegClass(i: It.getID());
198 if (SubRC->isAllocatable())
199 return SubRC;
200 }
201 return nullptr;
202}
203
204static const TargetRegisterClass *
205getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1,
206 MCRegister Reg2) {
207 assert(Reg1.isPhysical() && Reg2.isPhysical() &&
208 "Reg1/Reg2 must be a physical register");
209
210 // Pick the most specific register class that contains both physregs.
211 const TargetRegisterClass *BestRC = nullptr;
212 for (const TargetRegisterClass &RC : TRI->regclasses()) {
213 if (RC.contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC: &RC)))
214 BestRC = &RC;
215 }
216
217 assert(BestRC && "Couldn't find the register class");
218 return BestRC;
219}
220
221const TargetRegisterClass *
222TargetRegisterInfo::getCommonMinimalPhysRegClass(MCRegister Reg1,
223 MCRegister Reg2) const {
224 return ::getCommonMinimalPhysRegClass(TRI: this, Reg1, Reg2);
225}
226
227/// getAllocatableSetForRC - Toggle the bits that represent allocatable
228/// registers for the specific register class.
229static void getAllocatableSetForRC(const MachineFunction &MF,
230 const TargetRegisterClass *RC, BitVector &R){
231 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
232 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
233 ArrayRef<MCPhysReg> Order = TRI.getRawAllocationOrder(RC: *RC, MF);
234 for (MCPhysReg PR : Order)
235 R.set(PR);
236}
237
238BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
239 const TargetRegisterClass *RC) const {
240 BitVector Allocatable(getNumRegs());
241 if (RC) {
242 // A register class with no allocatable subclass returns an empty set.
243 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
244 if (SubClass)
245 getAllocatableSetForRC(MF, RC: SubClass, R&: Allocatable);
246 } else {
247 for (const TargetRegisterClass &C : regclasses())
248 if (C.isAllocatable())
249 getAllocatableSetForRC(MF, RC: &C, R&: Allocatable);
250 }
251
252 // Mask out the reserved registers
253 const MachineRegisterInfo &MRI = MF.getRegInfo();
254 const BitVector &Reserved = MRI.getReservedRegs();
255 Allocatable.reset(RHS: Reserved);
256
257 return Allocatable;
258}
259
260static inline
261const TargetRegisterClass *firstCommonClass(const uint32_t *A,
262 const uint32_t *B,
263 const TargetRegisterInfo *TRI) {
264 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
265 if (unsigned Common = *A++ & *B++)
266 return TRI->getRegClass(i: I + llvm::countr_zero(Val: Common));
267 return nullptr;
268}
269
270const TargetRegisterClass *
271TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
272 const TargetRegisterClass *B) const {
273 // First take care of the trivial cases.
274 if (A == B)
275 return A;
276 if (!A || !B)
277 return nullptr;
278
279 // Register classes are ordered topologically, so the largest common
280 // sub-class it the common sub-class with the smallest ID.
281 return firstCommonClass(A: A->getSubClassMask(), B: B->getSubClassMask(), TRI: this);
282}
283
284const TargetRegisterClass *
285TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
286 const TargetRegisterClass *B,
287 unsigned Idx) const {
288 assert(A && B && "Missing register class");
289 assert(Idx && "Bad sub-register index");
290
291 // Find Idx in the list of super-register indices.
292 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
293 if (RCI.getSubReg() == Idx)
294 // The bit mask contains all register classes that are projected into B
295 // by Idx. Find a class that is also a sub-class of A.
296 return firstCommonClass(A: RCI.getMask(), B: A->getSubClassMask(), TRI: this);
297 return nullptr;
298}
299
300const TargetRegisterClass *TargetRegisterInfo::
301getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
302 const TargetRegisterClass *RCB, unsigned SubB,
303 unsigned &PreA, unsigned &PreB) const {
304 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
305
306 // Search all pairs of sub-register indices that project into RCA and RCB
307 // respectively. This is quadratic, but usually the sets are very small. On
308 // most targets like X86, there will only be a single sub-register index
309 // (e.g., sub_16bit projecting into GR16).
310 //
311 // The worst case is a register class like DPR on ARM.
312 // We have indices dsub_0..dsub_7 projecting into that class.
313 //
314 // It is very common that one register class is a sub-register of the other.
315 // Arrange for RCA to be the larger register so the answer will be found in
316 // the first iteration. This makes the search linear for the most common
317 // case.
318 const TargetRegisterClass *BestRC = nullptr;
319 unsigned *BestPreA = &PreA;
320 unsigned *BestPreB = &PreB;
321 if (getRegSizeInBits(RC: *RCA) < getRegSizeInBits(RC: *RCB)) {
322 std::swap(a&: RCA, b&: RCB);
323 std::swap(a&: SubA, b&: SubB);
324 std::swap(a&: BestPreA, b&: BestPreB);
325 }
326
327 // Also terminate the search one we have found a register class as small as
328 // RCA.
329 unsigned MinSize = getRegSizeInBits(RC: *RCA);
330
331 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
332 unsigned FinalA = composeSubRegIndices(a: IA.getSubReg(), b: SubA);
333 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
334 // Check if a common super-register class exists for this index pair.
335 const TargetRegisterClass *RC =
336 firstCommonClass(A: IA.getMask(), B: IB.getMask(), TRI: this);
337 if (!RC || getRegSizeInBits(RC: *RC) < MinSize)
338 continue;
339
340 // The indexes must compose identically: PreA+SubA == PreB+SubB.
341 unsigned FinalB = composeSubRegIndices(a: IB.getSubReg(), b: SubB);
342 if (FinalA != FinalB)
343 continue;
344
345 // Is RC a better candidate than BestRC?
346 if (BestRC && getRegSizeInBits(RC: *RC) >= getRegSizeInBits(RC: *BestRC))
347 continue;
348
349 // Yes, RC is the smallest super-register seen so far.
350 BestRC = RC;
351 *BestPreA = IA.getSubReg();
352 *BestPreB = IB.getSubReg();
353
354 // Bail early if we reached MinSize. We won't find a better candidate.
355 if (getRegSizeInBits(RC: *BestRC) == MinSize)
356 return BestRC;
357 }
358 }
359 return BestRC;
360}
361
362const TargetRegisterClass *TargetRegisterInfo::findCommonRegClass(
363 const TargetRegisterClass *DefRC, unsigned DefSubReg,
364 const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const {
365 // Same register class.
366 //
367 // When processing uncoalescable copies / bitcasts, it is possible we reach
368 // here with the same register class, but mismatched subregister indices.
369 if (DefRC == SrcRC && DefSubReg == SrcSubReg)
370 return DefRC;
371
372 // Both operands are sub registers. Check if they share a register class.
373 unsigned SrcIdx, DefIdx;
374 if (SrcSubReg && DefSubReg) {
375 return getCommonSuperRegClass(RCA: SrcRC, SubA: SrcSubReg, RCB: DefRC, SubB: DefSubReg, PreA&: SrcIdx,
376 PreB&: DefIdx);
377 }
378
379 // At most one of the register is a sub register, make it Src to avoid
380 // duplicating the test.
381 if (!SrcSubReg) {
382 std::swap(a&: DefSubReg, b&: SrcSubReg);
383 std::swap(a&: DefRC, b&: SrcRC);
384 }
385
386 // One of the register is a sub register, check if we can get a superclass.
387 if (SrcSubReg)
388 return getMatchingSuperRegClass(A: SrcRC, B: DefRC, Idx: SrcSubReg);
389
390 // Plain copy.
391 return getCommonSubClass(A: DefRC, B: SrcRC);
392}
393
394float TargetRegisterInfo::getSpillWeightScaleFactor(
395 const TargetRegisterClass *RC) const {
396 return 1.0;
397}
398
399// Compute target-independent register allocator hints to help eliminate copies.
400bool TargetRegisterInfo::getRegAllocationHints(
401 Register VirtReg, ArrayRef<MCPhysReg> Order,
402 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
403 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
404 const MachineRegisterInfo &MRI = MF.getRegInfo();
405 const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =
406 MRI.getRegAllocationHints(VReg: VirtReg);
407
408 if (!Hints_MRI)
409 return false;
410
411 SmallSet<Register, 32> HintedRegs;
412 // First hint may be a target hint.
413 bool Skip = (Hints_MRI->first != 0);
414 for (auto Reg : Hints_MRI->second) {
415 if (Skip) {
416 Skip = false;
417 continue;
418 }
419
420 // Target-independent hints are either a physical or a virtual register.
421 Register Phys = Reg;
422 if (VRM && Phys.isVirtual())
423 Phys = VRM->getPhys(virtReg: Phys);
424
425 // Don't add the same reg twice (Hints_MRI may contain multiple virtual
426 // registers allocated to the same physreg).
427 if (!HintedRegs.insert(V: Phys).second)
428 continue;
429 // Check that Phys is a valid hint in VirtReg's register class.
430 if (!Phys.isPhysical())
431 continue;
432 if (MRI.isReserved(PhysReg: Phys))
433 continue;
434 // Check that Phys is in the allocation order. We shouldn't heed hints
435 // from VirtReg's register class if they aren't in the allocation order. The
436 // target probably has a reason for removing the register.
437 if (!is_contained(Range&: Order, Element: Phys))
438 continue;
439
440 // All clear, tell the register allocator to prefer this register.
441 Hints.push_back(Elt: Phys.id());
442 }
443 return false;
444}
445
446bool TargetRegisterInfo::isCalleeSavedPhysReg(
447 MCRegister PhysReg, const MachineFunction &MF) const {
448 if (!PhysReg)
449 return false;
450 const uint32_t *callerPreservedRegs =
451 getCallPreservedMask(MF, MF.getFunction().getCallingConv());
452 if (callerPreservedRegs) {
453 assert(PhysReg.isPhysical() && "Expected physical register");
454 return (callerPreservedRegs[PhysReg.id() / 32] >> PhysReg.id() % 32) & 1;
455 }
456 return false;
457}
458
459bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
460 return MF.getFrameInfo().isStackRealignable();
461}
462
463bool TargetRegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
464 return MF.getFrameInfo().shouldRealignStack();
465}
466
467bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
468 const uint32_t *mask1) const {
469 unsigned N = (getNumRegs()+31) / 32;
470 for (unsigned I = 0; I < N; ++I)
471 if ((mask0[I] & mask1[I]) != mask0[I])
472 return false;
473 return true;
474}
475
476TypeSize
477TargetRegisterInfo::getRegSizeInBits(Register Reg,
478 const MachineRegisterInfo &MRI) const {
479 const TargetRegisterClass *RC{};
480 if (Reg.isPhysical()) {
481 // The size is not directly available for physical registers.
482 // Instead, we need to access a register class that contains Reg and
483 // get the size of that register class.
484 RC = getMinimalPhysRegClass(Reg);
485 assert(RC && "Unable to deduce the register class");
486 return getRegSizeInBits(RC: *RC);
487 }
488 LLT Ty = MRI.getType(Reg);
489 if (Ty.isValid())
490 return Ty.getSizeInBits();
491
492 // Since Reg is not a generic register, it may have a register class.
493 RC = MRI.getRegClass(Reg);
494 assert(RC && "Unable to deduce the register class");
495 return getRegSizeInBits(RC: *RC);
496}
497
498bool TargetRegisterInfo::getCoveringSubRegIndexes(
499 const TargetRegisterClass *RC, LaneBitmask LaneMask,
500 SmallVectorImpl<unsigned> &NeededIndexes) const {
501 SmallVector<unsigned, 8> PossibleIndexes;
502 unsigned BestIdx = 0;
503 unsigned BestCover = 0;
504
505 for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
506 // Is this index even compatible with the given class?
507 if (!isSubRegValidForRegClass(RC, Idx))
508 continue;
509 LaneBitmask SubRegMask = getSubRegIndexLaneMask(SubIdx: Idx);
510 // Early exit if we found a perfect match.
511 if (SubRegMask == LaneMask) {
512 BestIdx = Idx;
513 break;
514 }
515
516 // The index must not cover any lanes outside \p LaneMask.
517 if ((SubRegMask & ~LaneMask).any())
518 continue;
519
520 unsigned PopCount = SubRegMask.getNumLanes();
521 PossibleIndexes.push_back(Elt: Idx);
522 if (PopCount > BestCover) {
523 BestCover = PopCount;
524 BestIdx = Idx;
525 }
526 }
527
528 // Abort if we cannot possibly implement the COPY with the given indexes.
529 if (BestIdx == 0)
530 return false;
531
532 NeededIndexes.push_back(Elt: BestIdx);
533
534 // Greedy heuristic: Keep iterating keeping the best covering subreg index
535 // each time.
536 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(SubIdx: BestIdx);
537 while (LanesLeft.any()) {
538 unsigned BestIdx = 0;
539 int BestCover = std::numeric_limits<int>::min();
540 for (unsigned Idx : PossibleIndexes) {
541 LaneBitmask SubRegMask = getSubRegIndexLaneMask(SubIdx: Idx);
542 // Early exit if we found a perfect match.
543 if (SubRegMask == LanesLeft) {
544 BestIdx = Idx;
545 break;
546 }
547
548 // Do not cover already-covered lanes to avoid creating cycles
549 // in copy bundles (= bundle contains copies that write to the
550 // registers).
551 if ((SubRegMask & ~LanesLeft).any())
552 continue;
553
554 // Try to cover as many of the remaining lanes as possible.
555 const int Cover = (SubRegMask & LanesLeft).getNumLanes();
556 if (Cover > BestCover) {
557 BestCover = Cover;
558 BestIdx = Idx;
559 }
560 }
561
562 if (BestIdx == 0)
563 return false; // Impossible to handle
564
565 NeededIndexes.push_back(Elt: BestIdx);
566
567 LanesLeft &= ~getSubRegIndexLaneMask(SubIdx: BestIdx);
568 }
569
570 return BestIdx;
571}
572
573bool TargetRegisterInfo::checkSubRegInterference(Register RegA, unsigned SubA,
574 Register RegB,
575 unsigned SubB) const {
576 if (RegA == RegB && SubA == SubB)
577 return true;
578 if (RegA.isVirtual() && RegB.isVirtual()) {
579 if (RegA != RegB)
580 return false;
581 LaneBitmask LA = getSubRegIndexLaneMask(SubIdx: SubA);
582 LaneBitmask LB = getSubRegIndexLaneMask(SubIdx: SubB);
583 return (LA & LB).any();
584 }
585 if (RegA.isPhysical() && RegB.isPhysical()) {
586 MCRegister MCRegA = SubA ? getSubReg(Reg: RegA, Idx: SubA) : RegA.asMCReg();
587 MCRegister MCRegB = SubB ? getSubReg(Reg: RegB, Idx: SubB) : RegB.asMCReg();
588 assert(MCRegB.isValid() && MCRegA.isValid() && "invalid subregister");
589 return MCRegisterInfo::regsOverlap(RegA: MCRegA, RegB: MCRegB);
590 }
591 llvm_unreachable("mixed virtual and physical registers");
592}
593
594unsigned TargetRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
595 assert(Idx && Idx < getNumSubRegIndices() &&
596 "This is not a subregister index");
597 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Size;
598}
599
600unsigned TargetRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
601 assert(Idx && Idx < getNumSubRegIndices() &&
602 "This is not a subregister index");
603 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Offset;
604}
605
606Register
607TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
608 const MachineRegisterInfo *MRI) const {
609 while (true) {
610 const MachineInstr *MI = MRI->getVRegDef(Reg: SrcReg);
611 if (!MI->isCopyLike())
612 return SrcReg;
613
614 Register CopySrcReg;
615 if (MI->isCopy())
616 CopySrcReg = MI->getOperand(i: 1).getReg();
617 else {
618 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
619 CopySrcReg = MI->getOperand(i: 1).getReg();
620 }
621
622 if (!CopySrcReg.isVirtual())
623 return CopySrcReg;
624
625 SrcReg = CopySrcReg;
626 }
627}
628
629Register TargetRegisterInfo::lookThruSingleUseCopyChain(
630 Register SrcReg, const MachineRegisterInfo *MRI) const {
631 while (true) {
632 const MachineInstr *MI = MRI->getVRegDef(Reg: SrcReg);
633 // Found the real definition, return it if it has a single use.
634 if (!MI->isCopyLike())
635 return MRI->hasOneNonDBGUse(RegNo: SrcReg) ? SrcReg : Register();
636
637 Register CopySrcReg;
638 if (MI->isCopy())
639 CopySrcReg = MI->getOperand(i: 1).getReg();
640 else {
641 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
642 CopySrcReg = MI->getOperand(i: 1).getReg();
643 }
644
645 // Continue only if the next definition in the chain is for a virtual
646 // register that has a single use.
647 if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(RegNo: CopySrcReg))
648 return Register();
649
650 SrcReg = CopySrcReg;
651 }
652}
653
654void TargetRegisterInfo::getOffsetOpcodes(
655 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
656 assert(!Offset.getScalable() && "Scalable offsets are not handled");
657 DIExpression::appendOffset(Ops, Offset: Offset.getFixed());
658}
659
660DIExpression *
661TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,
662 unsigned PrependFlags,
663 const StackOffset &Offset) const {
664 assert((PrependFlags &
665 ~(DIExpression::DerefBefore | DIExpression::DerefAfter |
666 DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&
667 "Unsupported prepend flag");
668 SmallVector<uint64_t, 16> OffsetExpr;
669 if (PrependFlags & DIExpression::DerefBefore)
670 OffsetExpr.push_back(Elt: dwarf::DW_OP_deref);
671 getOffsetOpcodes(Offset, Ops&: OffsetExpr);
672 if (PrependFlags & DIExpression::DerefAfter)
673 OffsetExpr.push_back(Elt: dwarf::DW_OP_deref);
674 return DIExpression::prependOpcodes(Expr, Ops&: OffsetExpr,
675 StackValue: PrependFlags & DIExpression::StackValue,
676 EntryValue: PrependFlags & DIExpression::EntryValue);
677}
678
679#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
680LLVM_DUMP_METHOD
681void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
682 const TargetRegisterInfo *TRI) {
683 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
684}
685#endif
686