1//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the TargetRegisterInfo interface.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/TargetRegisterInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallSet.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/BinaryFormat/Dwarf.h"
20#include "llvm/CodeGen/LiveInterval.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/TargetFrameLowering.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/CodeGen/VirtRegMap.h"
28#include "llvm/CodeGenTypes/MachineValueType.h"
29#include "llvm/Config/llvm-config.h"
30#include "llvm/IR/Attributes.h"
31#include "llvm/IR/DebugInfoMetadata.h"
32#include "llvm/IR/Function.h"
33#include "llvm/MC/MCRegisterInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Compiler.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/Printable.h"
38#include "llvm/Support/raw_ostream.h"
39#include <cassert>
40#include <utility>
41
42#define DEBUG_TYPE "target-reg-info"
43
44using namespace llvm;
45
46static cl::opt<unsigned>
47 HugeSizeForSplit("huge-size-for-split", cl::Hidden,
48 cl::desc("A threshold of live range size which may cause "
49 "high compile time cost in global splitting."),
50 cl::init(Val: 5000));
51
52TargetRegisterInfo::TargetRegisterInfo(
53 const TargetRegisterInfoDesc *ID,
54 ArrayRef<const TargetRegisterClass *> RegisterClasses,
55 const char *SubRegIndexStrings, ArrayRef<uint32_t> SubRegIndexNameOffsets,
56 const SubRegCoveredBits *SubRegIdxRanges,
57 const LaneBitmask *SubRegIndexLaneMasks, LaneBitmask CoveringLanes,
58 const RegClassInfo *const RCInfos,
59 const MVT::SimpleValueType *const RCVTLists, unsigned Mode)
60 : InfoDesc(ID), SubRegIndexStrings(SubRegIndexStrings),
61 SubRegIndexNameOffsets(SubRegIndexNameOffsets),
62 SubRegIdxRanges(SubRegIdxRanges),
63 SubRegIndexLaneMasks(SubRegIndexLaneMasks),
64 RegClassBegin(RegisterClasses.begin()),
65 RegClassEnd(RegisterClasses.end()), CoveringLanes(CoveringLanes),
66 RCInfos(RCInfos), RCVTLists(RCVTLists), HwMode(Mode) {}
67
68TargetRegisterInfo::~TargetRegisterInfo() = default;
69
70bool TargetRegisterInfo::shouldRegionSplitForVirtReg(
71 const MachineFunction &MF, const LiveInterval &VirtReg) const {
72 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
73 const MachineRegisterInfo &MRI = MF.getRegInfo();
74 MachineInstr *MI = MRI.getUniqueVRegDef(Reg: VirtReg.reg());
75 if (MI && TII->isTriviallyReMaterializable(MI: *MI) &&
76 VirtReg.size() > HugeSizeForSplit)
77 return false;
78 return true;
79}
80
81void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,
82 MCRegister Reg) const {
83 for (MCPhysReg SR : superregs_inclusive(Reg))
84 RegisterSet.set(SR);
85}
86
87bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
88 ArrayRef<MCPhysReg> Exceptions) const {
89 // Check that all super registers of reserved regs are reserved as well.
90 BitVector Checked(getNumRegs());
91 for (unsigned Reg : RegisterSet.set_bits()) {
92 if (Checked[Reg])
93 continue;
94 for (MCPhysReg SR : superregs(Reg)) {
95 if (!RegisterSet[SR] && !is_contained(Range&: Exceptions, Element: Reg)) {
96 dbgs() << "Error: Super register " << printReg(Reg: SR, TRI: this)
97 << " of reserved register " << printReg(Reg, TRI: this)
98 << " is not reserved.\n";
99 return false;
100 }
101
102 // We transitively check superregs. So we can remember this for later
103 // to avoid compiletime explosion in deep register hierarchies.
104 Checked.set(SR);
105 }
106 }
107 return true;
108}
109
110Printable llvm::printReg(Register Reg, const TargetRegisterInfo *TRI,
111 unsigned SubIdx, const MachineRegisterInfo *MRI) {
112 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
113 if (!Reg)
114 OS << "$noreg";
115 else if (Reg.isStack())
116 OS << "SS#" << Reg.stackSlotIndex();
117 else if (Reg.isVirtual()) {
118 StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
119 if (Name != "") {
120 OS << '%' << Name;
121 } else {
122 OS << '%' << Reg.virtRegIndex();
123 }
124 } else if (!TRI)
125 OS << '$' << "physreg" << Reg.id();
126 else if (Reg < TRI->getNumRegs()) {
127 OS << '$';
128 printLowerCase(String: TRI->getName(RegNo: Reg), Out&: OS);
129 } else
130 llvm_unreachable("Register kind is unsupported.");
131
132 if (SubIdx) {
133 if (TRI)
134 OS << ':' << TRI->getSubRegIndexName(SubIdx);
135 else
136 OS << ":sub(" << SubIdx << ')';
137 }
138 });
139}
140
141Printable llvm::printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI) {
142 return Printable([Unit, TRI](raw_ostream &OS) {
143 // Generic printout when TRI is missing.
144 if (!TRI) {
145 OS << "Unit~" << static_cast<unsigned>(Unit);
146 return;
147 }
148
149 // Check for invalid register units.
150 if (static_cast<unsigned>(Unit) >= TRI->getNumRegUnits()) {
151 OS << "BadUnit~" << static_cast<unsigned>(Unit);
152 return;
153 }
154
155 // Normal units have at least one root.
156 MCRegUnitRootIterator Roots(Unit, TRI);
157 assert(Roots.isValid() && "Unit has no roots.");
158 OS << TRI->getName(RegNo: *Roots);
159 for (++Roots; Roots.isValid(); ++Roots)
160 OS << '~' << TRI->getName(RegNo: *Roots);
161 });
162}
163
164Printable llvm::printVRegOrUnit(VirtRegOrUnit VRegOrUnit,
165 const TargetRegisterInfo *TRI) {
166 return Printable([VRegOrUnit, TRI](raw_ostream &OS) {
167 if (VRegOrUnit.isVirtualReg()) {
168 OS << '%' << VRegOrUnit.asVirtualReg().virtRegIndex();
169 } else {
170 OS << printRegUnit(Unit: VRegOrUnit.asMCRegUnit(), TRI);
171 }
172 });
173}
174
175Printable llvm::printRegClassOrBank(Register Reg,
176 const MachineRegisterInfo &RegInfo,
177 const TargetRegisterInfo *TRI) {
178 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
179 if (RegInfo.getRegClassOrNull(Reg))
180 OS << StringRef(TRI->getRegClassName(Class: RegInfo.getRegClass(Reg))).lower();
181 else if (RegInfo.getRegBankOrNull(Reg))
182 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
183 else {
184 OS << "_";
185 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
186 "Generic registers must have a valid type");
187 }
188 });
189}
190
191/// getAllocatableClass - Return the maximal subclass of the given register
192/// class that is alloctable, or NULL.
193const TargetRegisterClass *
194TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
195 if (!RC || RC->isAllocatable())
196 return RC;
197
198 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
199 ++It) {
200 const TargetRegisterClass *SubRC = getRegClass(i: It.getID());
201 if (SubRC->isAllocatable())
202 return SubRC;
203 }
204 return nullptr;
205}
206
207static const TargetRegisterClass *
208getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1,
209 MCRegister Reg2) {
210 assert(Reg1.isPhysical() && Reg2.isPhysical() &&
211 "Reg1/Reg2 must be a physical register");
212
213 // Pick the most specific register class that contains both physregs.
214 const TargetRegisterClass *BestRC = nullptr;
215 for (const TargetRegisterClass *RC : TRI->regclasses()) {
216 if (RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC)))
217 BestRC = RC;
218 }
219
220 assert(BestRC && "Couldn't find the register class");
221 return BestRC;
222}
223
224const TargetRegisterClass *
225TargetRegisterInfo::getCommonMinimalPhysRegClass(MCRegister Reg1,
226 MCRegister Reg2) const {
227 return ::getCommonMinimalPhysRegClass(TRI: this, Reg1, Reg2);
228}
229
230/// getAllocatableSetForRC - Toggle the bits that represent allocatable
231/// registers for the specific register class.
232static void getAllocatableSetForRC(const MachineFunction &MF,
233 const TargetRegisterClass *RC, BitVector &R){
234 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
235 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
236 for (MCPhysReg PR : Order)
237 R.set(PR);
238}
239
240BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
241 const TargetRegisterClass *RC) const {
242 BitVector Allocatable(getNumRegs());
243 if (RC) {
244 // A register class with no allocatable subclass returns an empty set.
245 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
246 if (SubClass)
247 getAllocatableSetForRC(MF, RC: SubClass, R&: Allocatable);
248 } else {
249 for (const TargetRegisterClass *C : regclasses())
250 if (C->isAllocatable())
251 getAllocatableSetForRC(MF, RC: C, R&: Allocatable);
252 }
253
254 // Mask out the reserved registers
255 const MachineRegisterInfo &MRI = MF.getRegInfo();
256 const BitVector &Reserved = MRI.getReservedRegs();
257 Allocatable.reset(RHS: Reserved);
258
259 return Allocatable;
260}
261
262static inline
263const TargetRegisterClass *firstCommonClass(const uint32_t *A,
264 const uint32_t *B,
265 const TargetRegisterInfo *TRI) {
266 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
267 if (unsigned Common = *A++ & *B++)
268 return TRI->getRegClass(i: I + llvm::countr_zero(Val: Common));
269 return nullptr;
270}
271
272const TargetRegisterClass *
273TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
274 const TargetRegisterClass *B) const {
275 // First take care of the trivial cases.
276 if (A == B)
277 return A;
278 if (!A || !B)
279 return nullptr;
280
281 // Register classes are ordered topologically, so the largest common
282 // sub-class it the common sub-class with the smallest ID.
283 return firstCommonClass(A: A->getSubClassMask(), B: B->getSubClassMask(), TRI: this);
284}
285
286const TargetRegisterClass *
287TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
288 const TargetRegisterClass *B,
289 unsigned Idx) const {
290 assert(A && B && "Missing register class");
291 assert(Idx && "Bad sub-register index");
292
293 // Find Idx in the list of super-register indices.
294 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
295 if (RCI.getSubReg() == Idx)
296 // The bit mask contains all register classes that are projected into B
297 // by Idx. Find a class that is also a sub-class of A.
298 return firstCommonClass(A: RCI.getMask(), B: A->getSubClassMask(), TRI: this);
299 return nullptr;
300}
301
302const TargetRegisterClass *TargetRegisterInfo::
303getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
304 const TargetRegisterClass *RCB, unsigned SubB,
305 unsigned &PreA, unsigned &PreB) const {
306 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
307
308 // Search all pairs of sub-register indices that project into RCA and RCB
309 // respectively. This is quadratic, but usually the sets are very small. On
310 // most targets like X86, there will only be a single sub-register index
311 // (e.g., sub_16bit projecting into GR16).
312 //
313 // The worst case is a register class like DPR on ARM.
314 // We have indices dsub_0..dsub_7 projecting into that class.
315 //
316 // It is very common that one register class is a sub-register of the other.
317 // Arrange for RCA to be the larger register so the answer will be found in
318 // the first iteration. This makes the search linear for the most common
319 // case.
320 const TargetRegisterClass *BestRC = nullptr;
321 unsigned *BestPreA = &PreA;
322 unsigned *BestPreB = &PreB;
323 if (getRegSizeInBits(RC: *RCA) < getRegSizeInBits(RC: *RCB)) {
324 std::swap(a&: RCA, b&: RCB);
325 std::swap(a&: SubA, b&: SubB);
326 std::swap(a&: BestPreA, b&: BestPreB);
327 }
328
329 // Also terminate the search one we have found a register class as small as
330 // RCA.
331 unsigned MinSize = getRegSizeInBits(RC: *RCA);
332
333 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
334 unsigned FinalA = composeSubRegIndices(a: IA.getSubReg(), b: SubA);
335 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
336 // Check if a common super-register class exists for this index pair.
337 const TargetRegisterClass *RC =
338 firstCommonClass(A: IA.getMask(), B: IB.getMask(), TRI: this);
339 if (!RC || getRegSizeInBits(RC: *RC) < MinSize)
340 continue;
341
342 // The indexes must compose identically: PreA+SubA == PreB+SubB.
343 unsigned FinalB = composeSubRegIndices(a: IB.getSubReg(), b: SubB);
344 if (FinalA != FinalB)
345 continue;
346
347 // Is RC a better candidate than BestRC?
348 if (BestRC && getRegSizeInBits(RC: *RC) >= getRegSizeInBits(RC: *BestRC))
349 continue;
350
351 // Yes, RC is the smallest super-register seen so far.
352 BestRC = RC;
353 *BestPreA = IA.getSubReg();
354 *BestPreB = IB.getSubReg();
355
356 // Bail early if we reached MinSize. We won't find a better candidate.
357 if (getRegSizeInBits(RC: *BestRC) == MinSize)
358 return BestRC;
359 }
360 }
361 return BestRC;
362}
363
364const TargetRegisterClass *TargetRegisterInfo::findCommonRegClass(
365 const TargetRegisterClass *DefRC, unsigned DefSubReg,
366 const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const {
367 // Same register class.
368 //
369 // When processing uncoalescable copies / bitcasts, it is possible we reach
370 // here with the same register class, but mismatched subregister indices.
371 if (DefRC == SrcRC && DefSubReg == SrcSubReg)
372 return DefRC;
373
374 // Both operands are sub registers. Check if they share a register class.
375 unsigned SrcIdx, DefIdx;
376 if (SrcSubReg && DefSubReg) {
377 return getCommonSuperRegClass(RCA: SrcRC, SubA: SrcSubReg, RCB: DefRC, SubB: DefSubReg, PreA&: SrcIdx,
378 PreB&: DefIdx);
379 }
380
381 // At most one of the register is a sub register, make it Src to avoid
382 // duplicating the test.
383 if (!SrcSubReg) {
384 std::swap(a&: DefSubReg, b&: SrcSubReg);
385 std::swap(a&: DefRC, b&: SrcRC);
386 }
387
388 // One of the register is a sub register, check if we can get a superclass.
389 if (SrcSubReg)
390 return getMatchingSuperRegClass(A: SrcRC, B: DefRC, Idx: SrcSubReg);
391
392 // Plain copy.
393 return getCommonSubClass(A: DefRC, B: SrcRC);
394}
395
396float TargetRegisterInfo::getSpillWeightScaleFactor(
397 const TargetRegisterClass *RC) const {
398 return 1.0;
399}
400
401// Compute target-independent register allocator hints to help eliminate copies.
402bool TargetRegisterInfo::getRegAllocationHints(
403 Register VirtReg, ArrayRef<MCPhysReg> Order,
404 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
405 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
406 const MachineRegisterInfo &MRI = MF.getRegInfo();
407 const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =
408 MRI.getRegAllocationHints(VReg: VirtReg);
409
410 if (!Hints_MRI)
411 return false;
412
413 SmallSet<Register, 32> HintedRegs;
414 // First hint may be a target hint.
415 bool Skip = (Hints_MRI->first != 0);
416 for (auto Reg : Hints_MRI->second) {
417 if (Skip) {
418 Skip = false;
419 continue;
420 }
421
422 // Target-independent hints are either a physical or a virtual register.
423 Register Phys = Reg;
424 if (VRM && Phys.isVirtual())
425 Phys = VRM->getPhys(virtReg: Phys);
426
427 // Don't add the same reg twice (Hints_MRI may contain multiple virtual
428 // registers allocated to the same physreg).
429 if (!HintedRegs.insert(V: Phys).second)
430 continue;
431 // Check that Phys is a valid hint in VirtReg's register class.
432 if (!Phys.isPhysical())
433 continue;
434 if (MRI.isReserved(PhysReg: Phys))
435 continue;
436 // Check that Phys is in the allocation order. We shouldn't heed hints
437 // from VirtReg's register class if they aren't in the allocation order. The
438 // target probably has a reason for removing the register.
439 if (!is_contained(Range&: Order, Element: Phys))
440 continue;
441
442 // All clear, tell the register allocator to prefer this register.
443 Hints.push_back(Elt: Phys.id());
444 }
445 return false;
446}
447
448bool TargetRegisterInfo::isCalleeSavedPhysReg(
449 MCRegister PhysReg, const MachineFunction &MF) const {
450 if (!PhysReg)
451 return false;
452 const uint32_t *callerPreservedRegs =
453 getCallPreservedMask(MF, MF.getFunction().getCallingConv());
454 if (callerPreservedRegs) {
455 assert(PhysReg.isPhysical() && "Expected physical register");
456 return (callerPreservedRegs[PhysReg.id() / 32] >> PhysReg.id() % 32) & 1;
457 }
458 return false;
459}
460
461bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
462 return MF.getFrameInfo().isStackRealignable();
463}
464
465bool TargetRegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
466 return MF.getFrameInfo().shouldRealignStack();
467}
468
469bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
470 const uint32_t *mask1) const {
471 unsigned N = (getNumRegs()+31) / 32;
472 for (unsigned I = 0; I < N; ++I)
473 if ((mask0[I] & mask1[I]) != mask0[I])
474 return false;
475 return true;
476}
477
478TypeSize
479TargetRegisterInfo::getRegSizeInBits(Register Reg,
480 const MachineRegisterInfo &MRI) const {
481 const TargetRegisterClass *RC{};
482 if (Reg.isPhysical()) {
483 // The size is not directly available for physical registers.
484 // Instead, we need to access a register class that contains Reg and
485 // get the size of that register class.
486 RC = getMinimalPhysRegClass(Reg);
487 assert(RC && "Unable to deduce the register class");
488 return getRegSizeInBits(RC: *RC);
489 }
490 LLT Ty = MRI.getType(Reg);
491 if (Ty.isValid())
492 return Ty.getSizeInBits();
493
494 // Since Reg is not a generic register, it may have a register class.
495 RC = MRI.getRegClass(Reg);
496 assert(RC && "Unable to deduce the register class");
497 return getRegSizeInBits(RC: *RC);
498}
499
500bool TargetRegisterInfo::getCoveringSubRegIndexes(
501 const TargetRegisterClass *RC, LaneBitmask LaneMask,
502 SmallVectorImpl<unsigned> &NeededIndexes) const {
503 SmallVector<unsigned, 8> PossibleIndexes;
504 unsigned BestIdx = 0;
505 unsigned BestCover = 0;
506
507 for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
508 // Is this index even compatible with the given class?
509 if (!isSubRegValidForRegClass(RC, Idx))
510 continue;
511 LaneBitmask SubRegMask = getSubRegIndexLaneMask(SubIdx: Idx);
512 // Early exit if we found a perfect match.
513 if (SubRegMask == LaneMask) {
514 BestIdx = Idx;
515 break;
516 }
517
518 // The index must not cover any lanes outside \p LaneMask.
519 if ((SubRegMask & ~LaneMask).any())
520 continue;
521
522 unsigned PopCount = SubRegMask.getNumLanes();
523 PossibleIndexes.push_back(Elt: Idx);
524 if (PopCount > BestCover) {
525 BestCover = PopCount;
526 BestIdx = Idx;
527 }
528 }
529
530 // Abort if we cannot possibly implement the COPY with the given indexes.
531 if (BestIdx == 0)
532 return false;
533
534 NeededIndexes.push_back(Elt: BestIdx);
535
536 // Greedy heuristic: Keep iterating keeping the best covering subreg index
537 // each time.
538 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(SubIdx: BestIdx);
539 while (LanesLeft.any()) {
540 unsigned BestIdx = 0;
541 int BestCover = std::numeric_limits<int>::min();
542 for (unsigned Idx : PossibleIndexes) {
543 LaneBitmask SubRegMask = getSubRegIndexLaneMask(SubIdx: Idx);
544 // Early exit if we found a perfect match.
545 if (SubRegMask == LanesLeft) {
546 BestIdx = Idx;
547 break;
548 }
549
550 // Do not cover already-covered lanes to avoid creating cycles
551 // in copy bundles (= bundle contains copies that write to the
552 // registers).
553 if ((SubRegMask & ~LanesLeft).any())
554 continue;
555
556 // Try to cover as many of the remaining lanes as possible.
557 const int Cover = (SubRegMask & LanesLeft).getNumLanes();
558 if (Cover > BestCover) {
559 BestCover = Cover;
560 BestIdx = Idx;
561 }
562 }
563
564 if (BestIdx == 0)
565 return false; // Impossible to handle
566
567 NeededIndexes.push_back(Elt: BestIdx);
568
569 LanesLeft &= ~getSubRegIndexLaneMask(SubIdx: BestIdx);
570 }
571
572 return BestIdx;
573}
574
575bool TargetRegisterInfo::checkSubRegInterference(Register RegA, unsigned SubA,
576 Register RegB,
577 unsigned SubB) const {
578 if (RegA == RegB && SubA == SubB)
579 return true;
580 if (RegA.isVirtual() && RegB.isVirtual()) {
581 if (RegA != RegB)
582 return false;
583 LaneBitmask LA = getSubRegIndexLaneMask(SubIdx: SubA);
584 LaneBitmask LB = getSubRegIndexLaneMask(SubIdx: SubB);
585 return (LA & LB).any();
586 }
587 if (RegA.isPhysical() && RegB.isPhysical()) {
588 MCRegister MCRegA = SubA ? getSubReg(Reg: RegA, Idx: SubA) : RegA.asMCReg();
589 MCRegister MCRegB = SubB ? getSubReg(Reg: RegB, Idx: SubB) : RegB.asMCReg();
590 assert(MCRegB.isValid() && MCRegA.isValid() && "invalid subregister");
591 return MCRegisterInfo::regsOverlap(RegA: MCRegA, RegB: MCRegB);
592 }
593 llvm_unreachable("mixed virtual and physical registers");
594}
595
596unsigned TargetRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
597 assert(Idx && Idx < getNumSubRegIndices() &&
598 "This is not a subregister index");
599 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Size;
600}
601
602unsigned TargetRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
603 assert(Idx && Idx < getNumSubRegIndices() &&
604 "This is not a subregister index");
605 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Offset;
606}
607
608Register
609TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
610 const MachineRegisterInfo *MRI) const {
611 while (true) {
612 const MachineInstr *MI = MRI->getVRegDef(Reg: SrcReg);
613 if (!MI->isCopyLike())
614 return SrcReg;
615
616 Register CopySrcReg;
617 if (MI->isCopy())
618 CopySrcReg = MI->getOperand(i: 1).getReg();
619 else {
620 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
621 CopySrcReg = MI->getOperand(i: 1).getReg();
622 }
623
624 if (!CopySrcReg.isVirtual())
625 return CopySrcReg;
626
627 SrcReg = CopySrcReg;
628 }
629}
630
631Register TargetRegisterInfo::lookThruSingleUseCopyChain(
632 Register SrcReg, const MachineRegisterInfo *MRI) const {
633 while (true) {
634 const MachineInstr *MI = MRI->getVRegDef(Reg: SrcReg);
635 // Found the real definition, return it if it has a single use.
636 if (!MI->isCopyLike())
637 return MRI->hasOneNonDBGUse(RegNo: SrcReg) ? SrcReg : Register();
638
639 Register CopySrcReg;
640 if (MI->isCopy())
641 CopySrcReg = MI->getOperand(i: 1).getReg();
642 else {
643 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
644 CopySrcReg = MI->getOperand(i: 1).getReg();
645 }
646
647 // Continue only if the next definition in the chain is for a virtual
648 // register that has a single use.
649 if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(RegNo: CopySrcReg))
650 return Register();
651
652 SrcReg = CopySrcReg;
653 }
654}
655
656void TargetRegisterInfo::getOffsetOpcodes(
657 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
658 assert(!Offset.getScalable() && "Scalable offsets are not handled");
659 DIExpression::appendOffset(Ops, Offset: Offset.getFixed());
660}
661
662DIExpression *
663TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,
664 unsigned PrependFlags,
665 const StackOffset &Offset) const {
666 assert((PrependFlags &
667 ~(DIExpression::DerefBefore | DIExpression::DerefAfter |
668 DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&
669 "Unsupported prepend flag");
670 SmallVector<uint64_t, 16> OffsetExpr;
671 if (PrependFlags & DIExpression::DerefBefore)
672 OffsetExpr.push_back(Elt: dwarf::DW_OP_deref);
673 getOffsetOpcodes(Offset, Ops&: OffsetExpr);
674 if (PrependFlags & DIExpression::DerefAfter)
675 OffsetExpr.push_back(Elt: dwarf::DW_OP_deref);
676 return DIExpression::prependOpcodes(Expr, Ops&: OffsetExpr,
677 StackValue: PrependFlags & DIExpression::StackValue,
678 EntryValue: PrependFlags & DIExpression::EntryValue);
679}
680
681#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
682LLVM_DUMP_METHOD
683void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
684 const TargetRegisterInfo *TRI) {
685 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
686}
687#endif
688