1//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the TargetRegisterInfo interface.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/TargetRegisterInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/BinaryFormat/Dwarf.h"
19#include "llvm/CodeGen/LiveInterval.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/TargetFrameLowering.h"
24#include "llvm/CodeGen/TargetInstrInfo.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/CodeGen/VirtRegMap.h"
27#include "llvm/CodeGenTypes/MachineValueType.h"
28#include "llvm/Config/llvm-config.h"
29#include "llvm/IR/Attributes.h"
30#include "llvm/IR/DebugInfoMetadata.h"
31#include "llvm/IR/Function.h"
32#include "llvm/MC/MCRegisterInfo.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Compiler.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/Printable.h"
37#include "llvm/Support/raw_ostream.h"
38#include <cassert>
39#include <utility>
40
41#define DEBUG_TYPE "target-reg-info"
42
43using namespace llvm;
44
45static cl::opt<unsigned>
46 HugeSizeForSplit("huge-size-for-split", cl::Hidden,
47 cl::desc("A threshold of live range size which may cause "
48 "high compile time cost in global splitting."),
49 cl::init(Val: 5000));
50
51TargetRegisterInfo::TargetRegisterInfo(
52 const TargetRegisterInfoDesc *ID, const char *SubRegIndexStrings,
53 ArrayRef<uint32_t> SubRegIndexNameOffsets,
54 const SubRegCoveredBits *SubRegIdxRanges,
55 const LaneBitmask *SubRegIndexLaneMasks, LaneBitmask CoveringLanes,
56 const RegClassInfo *const RCInfos,
57 const MVT::SimpleValueType *const RCVTLists, unsigned Mode)
58 : InfoDesc(ID), SubRegIndexStrings(SubRegIndexStrings),
59 SubRegIndexNameOffsets(SubRegIndexNameOffsets),
60 SubRegIdxRanges(SubRegIdxRanges),
61 SubRegIndexLaneMasks(SubRegIndexLaneMasks), CoveringLanes(CoveringLanes),
62 RCInfos(RCInfos), RCVTLists(RCVTLists), HwMode(Mode) {}
63
64TargetRegisterInfo::~TargetRegisterInfo() = default;
65
66bool TargetRegisterInfo::shouldRegionSplitForVirtReg(
67 const MachineFunction &MF, const LiveInterval &VirtReg) const {
68 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
69 const MachineRegisterInfo &MRI = MF.getRegInfo();
70 MachineInstr *MI = MRI.getUniqueVRegDef(Reg: VirtReg.reg());
71 if (MI && TII->isTriviallyReMaterializable(MI: *MI) &&
72 VirtReg.size() > HugeSizeForSplit)
73 return false;
74 return true;
75}
76
77void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,
78 MCRegister Reg) const {
79 for (MCPhysReg SR : superregs_inclusive(Reg))
80 RegisterSet.set(SR);
81}
82
83bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
84 ArrayRef<MCPhysReg> Exceptions) const {
85 // Check that all super registers of reserved regs are reserved as well.
86 BitVector Checked(getNumRegs());
87 for (unsigned Reg : RegisterSet.set_bits()) {
88 if (Checked[Reg])
89 continue;
90 for (MCPhysReg SR : superregs(Reg)) {
91 if (!RegisterSet[SR] && !is_contained(Range&: Exceptions, Element: Reg)) {
92 dbgs() << "Error: Super register " << printReg(Reg: SR, TRI: this)
93 << " of reserved register " << printReg(Reg, TRI: this)
94 << " is not reserved.\n";
95 return false;
96 }
97
98 // We transitively check superregs. So we can remember this for later
99 // to avoid compiletime explosion in deep register hierarchies.
100 Checked.set(SR);
101 }
102 }
103 return true;
104}
105
106Printable llvm::printReg(Register Reg, const TargetRegisterInfo *TRI,
107 unsigned SubIdx, const MachineRegisterInfo *MRI) {
108 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
109 if (!Reg)
110 OS << "$noreg";
111 else if (Reg.isStack())
112 OS << "SS#" << Reg.stackSlotIndex();
113 else if (Reg.isVirtual()) {
114 StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
115 if (Name != "") {
116 OS << '%' << Name;
117 } else {
118 OS << '%' << Reg.virtRegIndex();
119 }
120 } else if (!TRI)
121 OS << '$' << "physreg" << Reg.id();
122 else if (Reg < TRI->getNumRegs()) {
123 OS << '$';
124 printLowerCase(String: TRI->getName(RegNo: Reg), Out&: OS);
125 } else
126 llvm_unreachable("Register kind is unsupported.");
127
128 if (SubIdx) {
129 if (TRI)
130 OS << ':' << TRI->getSubRegIndexName(SubIdx);
131 else
132 OS << ":sub(" << SubIdx << ')';
133 }
134 });
135}
136
137Printable llvm::printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI) {
138 return Printable([Unit, TRI](raw_ostream &OS) {
139 // Generic printout when TRI is missing.
140 if (!TRI) {
141 OS << "Unit~" << static_cast<unsigned>(Unit);
142 return;
143 }
144
145 // Check for invalid register units.
146 if (static_cast<unsigned>(Unit) >= TRI->getNumRegUnits()) {
147 OS << "BadUnit~" << static_cast<unsigned>(Unit);
148 return;
149 }
150
151 // Normal units have at least one root.
152 MCRegUnitRootIterator Roots(Unit, TRI);
153 assert(Roots.isValid() && "Unit has no roots.");
154 OS << TRI->getName(RegNo: *Roots);
155 for (++Roots; Roots.isValid(); ++Roots)
156 OS << '~' << TRI->getName(RegNo: *Roots);
157 });
158}
159
160Printable llvm::printVRegOrUnit(VirtRegOrUnit VRegOrUnit,
161 const TargetRegisterInfo *TRI) {
162 return Printable([VRegOrUnit, TRI](raw_ostream &OS) {
163 if (VRegOrUnit.isVirtualReg()) {
164 OS << '%' << VRegOrUnit.asVirtualReg().virtRegIndex();
165 } else {
166 OS << printRegUnit(Unit: VRegOrUnit.asMCRegUnit(), TRI);
167 }
168 });
169}
170
171Printable llvm::printRegClassOrBank(Register Reg,
172 const MachineRegisterInfo &RegInfo,
173 const TargetRegisterInfo *TRI) {
174 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
175 if (RegInfo.getRegClassOrNull(Reg))
176 OS << StringRef(TRI->getRegClassName(Class: RegInfo.getRegClass(Reg))).lower();
177 else if (RegInfo.getRegBankOrNull(Reg))
178 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
179 else {
180 OS << "_";
181 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
182 "Generic registers must have a valid type");
183 }
184 });
185}
186
187/// getAllocatableClass - Return the maximal subclass of the given register
188/// class that is alloctable, or NULL.
189const TargetRegisterClass *
190TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
191 if (!RC || RC->isAllocatable())
192 return RC;
193
194 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
195 ++It) {
196 const TargetRegisterClass *SubRC = getRegClass(i: It.getID());
197 if (SubRC->isAllocatable())
198 return SubRC;
199 }
200 return nullptr;
201}
202
203static const TargetRegisterClass *
204getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1,
205 MCRegister Reg2) {
206 assert(Reg1.isPhysical() && Reg2.isPhysical() &&
207 "Reg1/Reg2 must be a physical register");
208
209 // Pick the most specific register class that contains both physregs.
210 const TargetRegisterClass *BestRC = nullptr;
211 for (const TargetRegisterClass &RC : TRI->regclasses()) {
212 if (RC.contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC: &RC)))
213 BestRC = &RC;
214 }
215
216 assert(BestRC && "Couldn't find the register class");
217 return BestRC;
218}
219
220const TargetRegisterClass *
221TargetRegisterInfo::getCommonMinimalPhysRegClass(MCRegister Reg1,
222 MCRegister Reg2) const {
223 return ::getCommonMinimalPhysRegClass(TRI: this, Reg1, Reg2);
224}
225
226/// getAllocatableSetForRC - Toggle the bits that represent allocatable
227/// registers for the specific register class.
228static void getAllocatableSetForRC(const MachineFunction &MF,
229 const TargetRegisterClass *RC, BitVector &R){
230 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
231 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
232 ArrayRef<MCPhysReg> Order = TRI.getRawAllocationOrder(RC: *RC, MF);
233 for (MCPhysReg PR : Order)
234 R.set(PR);
235}
236
237BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
238 const TargetRegisterClass *RC) const {
239 BitVector Allocatable(getNumRegs());
240 if (RC) {
241 // A register class with no allocatable subclass returns an empty set.
242 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
243 if (SubClass)
244 getAllocatableSetForRC(MF, RC: SubClass, R&: Allocatable);
245 } else {
246 for (const TargetRegisterClass &C : regclasses())
247 if (C.isAllocatable())
248 getAllocatableSetForRC(MF, RC: &C, R&: Allocatable);
249 }
250
251 // Mask out the reserved registers
252 const MachineRegisterInfo &MRI = MF.getRegInfo();
253 const BitVector &Reserved = MRI.getReservedRegs();
254 Allocatable.reset(RHS: Reserved);
255
256 return Allocatable;
257}
258
259static inline
260const TargetRegisterClass *firstCommonClass(const uint32_t *A,
261 const uint32_t *B,
262 const TargetRegisterInfo *TRI) {
263 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
264 if (unsigned Common = *A++ & *B++)
265 return TRI->getRegClass(i: I + llvm::countr_zero(Val: Common));
266 return nullptr;
267}
268
269const TargetRegisterClass *
270TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
271 const TargetRegisterClass *B) const {
272 // First take care of the trivial cases.
273 if (A == B)
274 return A;
275 if (!A || !B)
276 return nullptr;
277
278 // Register classes are ordered topologically, so the largest common
279 // sub-class it the common sub-class with the smallest ID.
280 return firstCommonClass(A: A->getSubClassMask(), B: B->getSubClassMask(), TRI: this);
281}
282
283const TargetRegisterClass *
284TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
285 const TargetRegisterClass *B,
286 unsigned Idx) const {
287 assert(A && B && "Missing register class");
288 assert(Idx && "Bad sub-register index");
289
290 // Find Idx in the list of super-register indices.
291 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
292 if (RCI.getSubReg() == Idx)
293 // The bit mask contains all register classes that are projected into B
294 // by Idx. Find a class that is also a sub-class of A.
295 return firstCommonClass(A: RCI.getMask(), B: A->getSubClassMask(), TRI: this);
296 return nullptr;
297}
298
299const TargetRegisterClass *TargetRegisterInfo::
300getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
301 const TargetRegisterClass *RCB, unsigned SubB,
302 unsigned &PreA, unsigned &PreB) const {
303 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
304
305 // Search all pairs of sub-register indices that project into RCA and RCB
306 // respectively. This is quadratic, but usually the sets are very small. On
307 // most targets like X86, there will only be a single sub-register index
308 // (e.g., sub_16bit projecting into GR16).
309 //
310 // The worst case is a register class like DPR on ARM.
311 // We have indices dsub_0..dsub_7 projecting into that class.
312 //
313 // It is very common that one register class is a sub-register of the other.
314 // Arrange for RCA to be the larger register so the answer will be found in
315 // the first iteration. This makes the search linear for the most common
316 // case.
317 const TargetRegisterClass *BestRC = nullptr;
318 unsigned *BestPreA = &PreA;
319 unsigned *BestPreB = &PreB;
320 if (getRegSizeInBits(RC: *RCA) < getRegSizeInBits(RC: *RCB)) {
321 std::swap(a&: RCA, b&: RCB);
322 std::swap(a&: SubA, b&: SubB);
323 std::swap(a&: BestPreA, b&: BestPreB);
324 }
325
326 // Also terminate the search one we have found a register class as small as
327 // RCA.
328 unsigned MinSize = getRegSizeInBits(RC: *RCA);
329
330 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
331 unsigned FinalA = composeSubRegIndices(a: IA.getSubReg(), b: SubA);
332 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
333 // Check if a common super-register class exists for this index pair.
334 const TargetRegisterClass *RC =
335 firstCommonClass(A: IA.getMask(), B: IB.getMask(), TRI: this);
336 if (!RC || getRegSizeInBits(RC: *RC) < MinSize)
337 continue;
338
339 // The indexes must compose identically: PreA+SubA == PreB+SubB.
340 unsigned FinalB = composeSubRegIndices(a: IB.getSubReg(), b: SubB);
341 if (FinalA != FinalB)
342 continue;
343
344 // Is RC a better candidate than BestRC?
345 if (BestRC && getRegSizeInBits(RC: *RC) >= getRegSizeInBits(RC: *BestRC))
346 continue;
347
348 // Yes, RC is the smallest super-register seen so far.
349 BestRC = RC;
350 *BestPreA = IA.getSubReg();
351 *BestPreB = IB.getSubReg();
352
353 // Bail early if we reached MinSize. We won't find a better candidate.
354 if (getRegSizeInBits(RC: *BestRC) == MinSize)
355 return BestRC;
356 }
357 }
358 return BestRC;
359}
360
361const TargetRegisterClass *TargetRegisterInfo::findCommonRegClass(
362 const TargetRegisterClass *DefRC, unsigned DefSubReg,
363 const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const {
364 // Same register class.
365 //
366 // When processing uncoalescable copies / bitcasts, it is possible we reach
367 // here with the same register class, but mismatched subregister indices.
368 if (DefRC == SrcRC && DefSubReg == SrcSubReg)
369 return DefRC;
370
371 // Both operands are sub registers. Check if they share a register class.
372 unsigned SrcIdx, DefIdx;
373 if (SrcSubReg && DefSubReg) {
374 return getCommonSuperRegClass(RCA: SrcRC, SubA: SrcSubReg, RCB: DefRC, SubB: DefSubReg, PreA&: SrcIdx,
375 PreB&: DefIdx);
376 }
377
378 // At most one of the register is a sub register, make it Src to avoid
379 // duplicating the test.
380 if (!SrcSubReg) {
381 std::swap(a&: DefSubReg, b&: SrcSubReg);
382 std::swap(a&: DefRC, b&: SrcRC);
383 }
384
385 // One of the register is a sub register, check if we can get a superclass.
386 if (SrcSubReg)
387 return getMatchingSuperRegClass(A: SrcRC, B: DefRC, Idx: SrcSubReg);
388
389 // Plain copy.
390 return getCommonSubClass(A: DefRC, B: SrcRC);
391}
392
393float TargetRegisterInfo::getSpillWeightScaleFactor(
394 const TargetRegisterClass *RC) const {
395 return 1.0;
396}
397
398// Compute target-independent register allocator hints to help eliminate copies.
399bool TargetRegisterInfo::getRegAllocationHints(
400 Register VirtReg, ArrayRef<MCPhysReg> Order,
401 SmallSetVector<MCPhysReg, 16> &Hints, const MachineFunction &MF,
402 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
403 const MachineRegisterInfo &MRI = MF.getRegInfo();
404 const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =
405 MRI.getRegAllocationHints(VReg: VirtReg);
406
407 if (!Hints_MRI)
408 return false;
409
410 // First hint may be a target hint.
411 bool Skip = (Hints_MRI->first != 0);
412 for (auto Reg : Hints_MRI->second) {
413 if (Skip) {
414 Skip = false;
415 continue;
416 }
417
418 // Target-independent hints are either a physical or a virtual register.
419 Register Phys = Reg;
420 if (VRM && Phys.isVirtual())
421 Phys = VRM->getPhys(virtReg: Phys);
422
423 // Check that Phys is a valid hint in VirtReg's register class.
424 if (!Phys.isPhysical())
425 continue;
426 if (MRI.isReserved(PhysReg: Phys))
427 continue;
428 // Check that Phys is in the allocation order. We shouldn't heed hints
429 // from VirtReg's register class if they aren't in the allocation order. The
430 // target probably has a reason for removing the register.
431 if (!is_contained(Range&: Order, Element: Phys))
432 continue;
433
434 // All clear, tell the register allocator to prefer this register.
435 Hints.insert(X: Phys);
436 }
437 return false;
438}
439
440bool TargetRegisterInfo::isAntiHintedReg(
441 MCPhysReg Reg, const BitVector &AntiHintedRegUnits) const {
442 return llvm::any_of(Range: regunits(Reg), P: [&](MCRegUnit Unit) {
443 return AntiHintedRegUnits.test(Idx: static_cast<unsigned>(Unit));
444 });
445}
446
447void TargetRegisterInfo::applyRegAllocationAntiHints(
448 Register VirtReg, ArrayRef<MCPhysReg> Order,
449 SmallVectorImpl<MCPhysReg> &HintsAndCustomOrder, unsigned NumHints,
450 const BitVector &AntiHintedRegUnits, const MachineFunction &MF,
451 const LiveRegMatrix *Matrix, const RegisterClassInfo *RegClassInfo) const {
452
453 if (AntiHintedRegUnits.none())
454 return;
455
456 assert(HintsAndCustomOrder.size() == NumHints &&
457 "HintsAndCustomOrder should only contain the hints here.");
458 HintsAndCustomOrder.append(in_start: Order.begin(), in_end: Order.end());
459
460 // Custom reordering of the allocation order.
461 filterAndSortForAntiHintedRegs(
462 VirtReg,
463 CustomOrder: MutableArrayRef<MCPhysReg>(HintsAndCustomOrder).drop_front(N: NumHints),
464 AntiHintedRegUnits, MF, Matrix, RegClassInfo);
465}
466
467void TargetRegisterInfo::filterAndSortForAntiHintedRegs(
468 Register VirtReg, MutableArrayRef<MCPhysReg> CustomOrder,
469 const BitVector &AntiHintedRegUnits, const MachineFunction &MF,
470 const LiveRegMatrix *Matrix, const RegisterClassInfo *RegClassInfo) const {
471
472 // Partition non-anti-hinted register go first.
473 [[maybe_unused]] auto *PartitionPoint = std::stable_partition(
474 first: CustomOrder.begin(), last: CustomOrder.end(),
475 pred: [&](MCPhysReg Reg) { return !isAntiHintedReg(Reg, AntiHintedRegUnits); });
476
477 LLVM_DEBUG({
478 size_t NonAntiHintedCount =
479 std::distance(CustomOrder.begin(), PartitionPoint);
480 size_t AntiHintedCount = std::distance(PartitionPoint, CustomOrder.end());
481 dbgs() << "Added " << NonAntiHintedCount
482 << " non-anti-hinted registers first\n"
483 << "Added " << AntiHintedCount
484 << " anti-hinted registers at the end\n";
485 });
486}
487
488bool TargetRegisterInfo::isCalleeSavedPhysReg(
489 MCRegister PhysReg, const MachineFunction &MF) const {
490 if (!PhysReg)
491 return false;
492 const uint32_t *callerPreservedRegs =
493 getCallPreservedMask(MF, MF.getFunction().getCallingConv());
494 if (callerPreservedRegs) {
495 assert(PhysReg.isPhysical() && "Expected physical register");
496 return (callerPreservedRegs[PhysReg.id() / 32] >> PhysReg.id() % 32) & 1;
497 }
498 return false;
499}
500
501bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
502 return MF.getFrameInfo().isStackRealignable();
503}
504
505bool TargetRegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
506 return MF.getFrameInfo().shouldRealignStack();
507}
508
509bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
510 const uint32_t *mask1) const {
511 unsigned N = (getNumRegs()+31) / 32;
512 for (unsigned I = 0; I < N; ++I)
513 if ((mask0[I] & mask1[I]) != mask0[I])
514 return false;
515 return true;
516}
517
518TypeSize
519TargetRegisterInfo::getRegSizeInBits(Register Reg,
520 const MachineRegisterInfo &MRI) const {
521 const TargetRegisterClass *RC{};
522 if (Reg.isPhysical()) {
523 // The size is not directly available for physical registers.
524 // Instead, we need to access a register class that contains Reg and
525 // get the size of that register class.
526 RC = getMinimalPhysRegClass(Reg);
527 assert(RC && "Unable to deduce the register class");
528 return getRegSizeInBits(RC: *RC);
529 }
530 LLT Ty = MRI.getType(Reg);
531 if (Ty.isValid())
532 return Ty.getSizeInBits();
533
534 // Since Reg is not a generic register, it may have a register class.
535 RC = MRI.getRegClass(Reg);
536 assert(RC && "Unable to deduce the register class");
537 return getRegSizeInBits(RC: *RC);
538}
539
540bool TargetRegisterInfo::getCoveringSubRegIndexes(
541 const TargetRegisterClass *RC, LaneBitmask LaneMask,
542 SmallVectorImpl<unsigned> &NeededIndexes) const {
543 SmallVector<unsigned, 8> PossibleIndexes;
544 unsigned BestIdx = 0;
545 unsigned BestCover = 0;
546
547 for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
548 // Is this index even compatible with the given class?
549 if (!isSubRegValidForRegClass(RC, Idx))
550 continue;
551 LaneBitmask SubRegMask = getSubRegIndexLaneMask(SubIdx: Idx);
552 // Early exit if we found a perfect match.
553 if (SubRegMask == LaneMask) {
554 BestIdx = Idx;
555 break;
556 }
557
558 // The index must not cover any lanes outside \p LaneMask.
559 if ((SubRegMask & ~LaneMask).any())
560 continue;
561
562 unsigned PopCount = SubRegMask.getNumLanes();
563 PossibleIndexes.push_back(Elt: Idx);
564 if (PopCount > BestCover) {
565 BestCover = PopCount;
566 BestIdx = Idx;
567 }
568 }
569
570 // Abort if we cannot possibly implement the COPY with the given indexes.
571 if (BestIdx == 0)
572 return false;
573
574 NeededIndexes.push_back(Elt: BestIdx);
575
576 // Greedy heuristic: Keep iterating keeping the best covering subreg index
577 // each time.
578 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(SubIdx: BestIdx);
579 while (LanesLeft.any()) {
580 unsigned BestIdx = 0;
581 int BestCover = std::numeric_limits<int>::min();
582 for (unsigned Idx : PossibleIndexes) {
583 LaneBitmask SubRegMask = getSubRegIndexLaneMask(SubIdx: Idx);
584 // Early exit if we found a perfect match.
585 if (SubRegMask == LanesLeft) {
586 BestIdx = Idx;
587 break;
588 }
589
590 // Do not cover already-covered lanes to avoid creating cycles
591 // in copy bundles (= bundle contains copies that write to the
592 // registers).
593 if ((SubRegMask & ~LanesLeft).any())
594 continue;
595
596 // Try to cover as many of the remaining lanes as possible.
597 const int Cover = (SubRegMask & LanesLeft).getNumLanes();
598 if (Cover > BestCover) {
599 BestCover = Cover;
600 BestIdx = Idx;
601 }
602 }
603
604 if (BestIdx == 0)
605 return false; // Impossible to handle
606
607 NeededIndexes.push_back(Elt: BestIdx);
608
609 LanesLeft &= ~getSubRegIndexLaneMask(SubIdx: BestIdx);
610 }
611
612 return BestIdx;
613}
614
615bool TargetRegisterInfo::checkSubRegInterference(Register RegA, unsigned SubA,
616 Register RegB,
617 unsigned SubB) const {
618 if (RegA == RegB && SubA == SubB)
619 return true;
620 if (RegA.isVirtual() && RegB.isVirtual()) {
621 if (RegA != RegB)
622 return false;
623 LaneBitmask LA = getSubRegIndexLaneMask(SubIdx: SubA);
624 LaneBitmask LB = getSubRegIndexLaneMask(SubIdx: SubB);
625 return (LA & LB).any();
626 }
627 if (RegA.isPhysical() && RegB.isPhysical()) {
628 MCRegister MCRegA = SubA ? getSubReg(Reg: RegA, Idx: SubA) : RegA.asMCReg();
629 MCRegister MCRegB = SubB ? getSubReg(Reg: RegB, Idx: SubB) : RegB.asMCReg();
630 assert(MCRegB.isValid() && MCRegA.isValid() && "invalid subregister");
631 return MCRegisterInfo::regsOverlap(RegA: MCRegA, RegB: MCRegB);
632 }
633 llvm_unreachable("mixed virtual and physical registers");
634}
635
636unsigned TargetRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
637 assert(Idx && Idx < getNumSubRegIndices() &&
638 "This is not a subregister index");
639 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Size;
640}
641
642unsigned TargetRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
643 assert(Idx && Idx < getNumSubRegIndices() &&
644 "This is not a subregister index");
645 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Offset;
646}
647
648Register
649TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
650 const MachineRegisterInfo *MRI) const {
651 while (true) {
652 const MachineInstr *MI = MRI->getVRegDef(Reg: SrcReg);
653 if (!MI || !MI->isCopyLike())
654 return SrcReg;
655
656 Register CopySrcReg;
657 if (MI->isCopy())
658 CopySrcReg = MI->getOperand(i: 1).getReg();
659 else {
660 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
661 CopySrcReg = MI->getOperand(i: 1).getReg();
662 }
663
664 if (!CopySrcReg.isVirtual())
665 return CopySrcReg;
666
667 SrcReg = CopySrcReg;
668 }
669}
670
671Register TargetRegisterInfo::lookThruSingleUseCopyChain(
672 Register SrcReg, const MachineRegisterInfo *MRI) const {
673 while (true) {
674 const MachineInstr *MI = MRI->getVRegDef(Reg: SrcReg);
675 // Found the real definition, return it if it has a single use.
676 if (!MI || !MI->isCopyLike())
677 return MRI->hasOneNonDBGUse(RegNo: SrcReg) ? SrcReg : Register();
678
679 Register CopySrcReg;
680 if (MI->isCopy())
681 CopySrcReg = MI->getOperand(i: 1).getReg();
682 else {
683 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
684 CopySrcReg = MI->getOperand(i: 1).getReg();
685 }
686
687 // Continue only if the next definition in the chain is for a virtual
688 // register that has a single use.
689 if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(RegNo: CopySrcReg))
690 return Register();
691
692 SrcReg = CopySrcReg;
693 }
694}
695
696void TargetRegisterInfo::getOffsetOpcodes(
697 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
698 assert(!Offset.getScalable() && "Scalable offsets are not handled");
699 DIExpression::appendOffset(Ops, Offset: Offset.getFixed());
700}
701
702DIExpression *
703TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,
704 unsigned PrependFlags,
705 const StackOffset &Offset) const {
706 assert((PrependFlags &
707 ~(DIExpression::DerefBefore | DIExpression::DerefAfter |
708 DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&
709 "Unsupported prepend flag");
710 SmallVector<uint64_t, 16> OffsetExpr;
711 if (PrependFlags & DIExpression::DerefBefore)
712 OffsetExpr.push_back(Elt: dwarf::DW_OP_deref);
713 getOffsetOpcodes(Offset, Ops&: OffsetExpr);
714 if (PrependFlags & DIExpression::DerefAfter)
715 OffsetExpr.push_back(Elt: dwarf::DW_OP_deref);
716 return DIExpression::prependOpcodes(Expr, Ops&: OffsetExpr,
717 StackValue: PrependFlags & DIExpression::StackValue,
718 EntryValue: PrependFlags & DIExpression::EntryValue);
719}
720
721#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
722LLVM_DUMP_METHOD
723void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
724 const TargetRegisterInfo *TRI) {
725 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
726}
727#endif
728