1//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file describes the general parts of a Subtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/TargetSubtargetInfo.h"
14#include "llvm/IR/Intrinsics.h"
15
16using namespace llvm;
17
18TargetSubtargetInfo::TargetSubtargetInfo(
19 const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
20 StringTable PN, ArrayRef<SubtargetFeatureKV> PF,
21 ArrayRef<SubtargetSubTypeKV> PD, const MCSchedModel *PSM,
22 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
23 const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
24 const unsigned *FP)
25 : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM, WPR, WL, RA, IS,
26 OC, FP) {}
27
28TargetSubtargetInfo::~TargetSubtargetInfo() = default;
29
30bool TargetSubtargetInfo::isIntrinsicSupported(unsigned IntrinsicID) const {
31 StringRef RequiredFeatures = Intrinsic::getRequiredTargetFeatures(
32 id: static_cast<Intrinsic::ID>(IntrinsicID));
33
34 if (RequiredFeatures.empty())
35 return true;
36
37 auto [It, Inserted] = IntrinsicSupportCache.try_emplace(Key: IntrinsicID);
38 if (Inserted)
39 It->second = checkFeatureExpression(FeatureExpr: RequiredFeatures);
40 return It->second;
41}
42
43bool TargetSubtargetInfo::enableAtomicExpand() const {
44 return true;
45}
46
47bool TargetSubtargetInfo::enableIndirectBrExpand() const {
48 return false;
49}
50
51bool TargetSubtargetInfo::enableMachineScheduler() const {
52 return false;
53}
54
55bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
56 return enableMachineScheduler();
57}
58
59bool TargetSubtargetInfo::enableRALocalReassignment(
60 CodeGenOptLevel OptLevel) const {
61 return true;
62}
63
64bool TargetSubtargetInfo::enablePostRAScheduler() const {
65 return getSchedModel().PostRAScheduler;
66}
67
68bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
69 return enableMachineScheduler() && enablePostRAScheduler();
70}
71
72bool TargetSubtargetInfo::useAA() const {
73 return false;
74}
75
76void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }
77