1//===-- DWARFExpression.cpp -----------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/DebugInfo/DWARF/DWARFExpressionPrinter.h"
10#include "llvm/ADT/SmallString.h"
11#include "llvm/DebugInfo/DWARF/DWARFUnit.h"
12#include "llvm/DebugInfo/DWARF/LowLevel/DWARFExpression.h"
13#include "llvm/Support/Format.h"
14#include "llvm/Support/FormatVariadic.h"
15#include <cassert>
16#include <cstdint>
17
18using namespace llvm;
19using namespace dwarf;
20
21namespace llvm {
22
23typedef DWARFExpression::Operation Op;
24typedef Op::Description Desc;
25
26static void prettyPrintBaseTypeRef(DWARFUnit *U, raw_ostream &OS,
27 DIDumpOptions DumpOpts,
28 ArrayRef<uint64_t> Operands,
29 unsigned Operand) {
30 assert(Operand < Operands.size() && "operand out of bounds");
31 if (!U) {
32 OS << format(Fmt: " <base_type ref: 0x%" PRIx64 ">", Vals: Operands[Operand]);
33 return;
34 }
35 auto Die = U->getDIEForOffset(Offset: U->getOffset() + Operands[Operand]);
36 if (Die && Die.getTag() == dwarf::DW_TAG_base_type) {
37 OS << " (";
38 if (DumpOpts.Verbose)
39 OS << format(Fmt: "0x%08" PRIx64 " -> ", Vals: Operands[Operand]);
40 OS << format(Fmt: "0x%08" PRIx64 ")", Vals: U->getOffset() + Operands[Operand]);
41 if (auto Name = dwarf::toString(V: Die.find(Attr: dwarf::DW_AT_name)))
42 OS << " \"" << *Name << "\"";
43 } else {
44 OS << format(Fmt: " <invalid base_type ref: 0x%" PRIx64 ">", Vals: Operands[Operand]);
45 }
46}
47
48static bool printOp(const DWARFExpression::Operation *Op, raw_ostream &OS,
49 DIDumpOptions DumpOpts, const DWARFExpression *Expr,
50 DWARFUnit *U) {
51 if (Op->isError()) {
52 if (!DumpOpts.PrintRegisterOnly)
53 OS << "<decoding error>";
54 return false;
55 }
56
57 std::optional<unsigned> SubOpcode = Op->getSubCode();
58
59 // In "register-only" mode, still show simple constant-valued locations.
60 // This lets clients print annotations like "i = 0" when the location is
61 // a constant (e.g. DW_OP_constu/consts ... DW_OP_stack_value).
62 // We continue to suppress all other non-register ops in this mode.
63 if (DumpOpts.PrintRegisterOnly) {
64 // First, try pretty-printing registers (existing behavior below also does
65 // this, but we need to short-circuit here to avoid printing opcode names).
66 if ((Op->getCode() >= DW_OP_breg0 && Op->getCode() <= DW_OP_breg31) ||
67 (Op->getCode() >= DW_OP_reg0 && Op->getCode() <= DW_OP_reg31) ||
68 Op->getCode() == DW_OP_bregx || Op->getCode() == DW_OP_regx ||
69 Op->getCode() == DW_OP_regval_type ||
70 SubOpcode == DW_OP_LLVM_call_frame_entry_reg ||
71 SubOpcode == DW_OP_LLVM_aspace_bregx) {
72 if (prettyPrintRegisterOp(U, OS, DumpOpts, Opcode: Op->getCode(),
73 Operands: Op->getRawOperands()))
74 return true;
75 // If we couldn't pretty-print, fall through and suppress.
76 }
77
78 // Show constants (decimal), suppress everything else.
79 if (Op->getCode() == DW_OP_constu) {
80 OS << (uint64_t)Op->getRawOperand(Idx: 0);
81 return true;
82 }
83 if (Op->getCode() == DW_OP_consts) {
84 OS << (int64_t)Op->getRawOperand(Idx: 0);
85 return true;
86 }
87 if (Op->getCode() >= DW_OP_lit0 && Op->getCode() <= DW_OP_lit31) {
88 OS << (unsigned)(Op->getCode() - DW_OP_lit0);
89 return true;
90 }
91 if (Op->getCode() == DW_OP_stack_value)
92 return true; // metadata; don't print a token
93
94 return true; // suppress other opcodes silently in register-only mode
95 }
96
97 if (!DumpOpts.PrintRegisterOnly) {
98 StringRef Name = OperationEncodingString(Encoding: Op->getCode());
99 assert(!Name.empty() && "DW_OP has no name!");
100 OS << Name;
101
102 if (SubOpcode) {
103 StringRef SubName = SubOperationEncodingString(OpEncoding: Op->getCode(), SubOpEncoding: *SubOpcode);
104 assert(!SubName.empty() && "DW_OP SubOp has no name!");
105 OS << ' ' << SubName;
106 }
107 }
108
109 if ((Op->getCode() >= DW_OP_breg0 && Op->getCode() <= DW_OP_breg31) ||
110 (Op->getCode() >= DW_OP_reg0 && Op->getCode() <= DW_OP_reg31) ||
111 Op->getCode() == DW_OP_bregx || Op->getCode() == DW_OP_regx ||
112 Op->getCode() == DW_OP_regval_type ||
113 SubOpcode == DW_OP_LLVM_call_frame_entry_reg ||
114 SubOpcode == DW_OP_LLVM_aspace_bregx)
115 if (prettyPrintRegisterOp(U, OS, DumpOpts, Opcode: Op->getCode(),
116 Operands: Op->getRawOperands()))
117 return true;
118
119 if (!DumpOpts.PrintRegisterOnly) {
120 for (unsigned Operand = 0; Operand < Op->getDescription().Op.size();
121 ++Operand) {
122 unsigned Size = Op->getDescription().Op[Operand];
123 unsigned Signed = Size & DWARFExpression::Operation::SignBit;
124
125 if (Size == DWARFExpression::Operation::SizeSubOpLEB) {
126 assert(Operand == 0 && "DW_OP SubOp must be the first operand");
127 assert(SubOpcode && "DW_OP SubOp description is inconsistent");
128 } else if (Size == DWARFExpression::Operation::BaseTypeRef && U) {
129 // For DW_OP_convert the operand may be 0 to indicate that conversion to
130 // the generic type should be done. The same holds for
131 // DW_OP_reinterpret, which is currently not supported.
132 if (Op->getCode() == DW_OP_convert && Op->getRawOperand(Idx: Operand) == 0)
133 OS << " 0x0";
134 else
135 prettyPrintBaseTypeRef(U, OS, DumpOpts, Operands: Op->getRawOperands(),
136 Operand);
137 } else if (Size == DWARFExpression::Operation::WasmLocationArg) {
138 assert(Operand == 1);
139 switch (Op->getRawOperand(Idx: 0)) {
140 case 0:
141 case 1:
142 case 2:
143 case 3: // global as uint32
144 case 4:
145 OS << format(Fmt: " 0x%" PRIx64, Vals: Op->getRawOperand(Idx: Operand));
146 break;
147 default:
148 assert(false);
149 }
150 } else if (Size == DWARFExpression::Operation::SizeBlock) {
151 uint64_t Offset = Op->getRawOperand(Idx: Operand);
152 for (unsigned i = 0; i < Op->getRawOperand(Idx: Operand - 1); ++i)
153 OS << format(Fmt: " 0x%02x",
154 Vals: static_cast<uint8_t>(Expr->getData()[Offset++]));
155 } else {
156 if (Signed)
157 OS << formatv(Fmt: " {0:+d}", Vals: (int64_t)Op->getRawOperand(Idx: Operand));
158 else if (Op->getCode() != DW_OP_entry_value &&
159 Op->getCode() != DW_OP_GNU_entry_value)
160 OS << format(Fmt: " 0x%" PRIx64, Vals: Op->getRawOperand(Idx: Operand));
161 }
162 }
163 }
164 return true;
165}
166
167void printDwarfExpression(const DWARFExpression *E, raw_ostream &OS,
168 DIDumpOptions DumpOpts, DWARFUnit *U, bool IsEH) {
169 uint32_t EntryValExprSize = 0;
170 uint64_t EntryValStartOffset = 0;
171 if (E->getData().empty())
172 OS << "<empty>";
173
174 for (auto &Op : *E) {
175 DumpOpts.IsEH = IsEH;
176 if (!printOp(Op: &Op, OS, DumpOpts, Expr: E, U) && !DumpOpts.PrintRegisterOnly) {
177 uint64_t FailOffset = Op.getEndOffset();
178 while (FailOffset < E->getData().size())
179 OS << format(Fmt: " %02x", Vals: static_cast<uint8_t>(E->getData()[FailOffset++]));
180 return;
181 }
182 if (!DumpOpts.PrintRegisterOnly) {
183 if (Op.getCode() == DW_OP_entry_value ||
184 Op.getCode() == DW_OP_GNU_entry_value) {
185 OS << "(";
186 EntryValExprSize = Op.getRawOperand(Idx: 0);
187 EntryValStartOffset = Op.getEndOffset();
188 continue;
189 }
190
191 if (EntryValExprSize) {
192 EntryValExprSize -= Op.getEndOffset() - EntryValStartOffset;
193 if (EntryValExprSize == 0)
194 OS << ")";
195 }
196
197 if (Op.getEndOffset() < E->getData().size())
198 OS << ", ";
199 }
200 }
201}
202
203/// A user-facing string representation of a DWARF expression. This might be an
204/// Address expression, in which case it will be implicitly dereferenced, or a
205/// Value expression.
206struct PrintedExpr {
207 enum ExprKind {
208 Address,
209 Value,
210 };
211 ExprKind Kind;
212 SmallString<16> String;
213
214 PrintedExpr(ExprKind K = Address) : Kind(K) {}
215};
216
217static bool printCompactDWARFExpr(
218 raw_ostream &OS, DWARFExpression::iterator I,
219 const DWARFExpression::iterator E,
220 std::function<StringRef(uint64_t RegNum, bool IsEH)> GetNameForDWARFReg =
221 nullptr) {
222 SmallVector<PrintedExpr, 4> Stack;
223
224 auto UnknownOpcode = [](raw_ostream &OS, uint8_t Opcode,
225 std::optional<unsigned> SubOpcode) -> bool {
226 // If we hit an unknown operand, we don't know its effect on the stack,
227 // so bail out on the whole expression.
228 OS << "<unknown op " << dwarf::OperationEncodingString(Encoding: Opcode) << " ("
229 << (int)Opcode;
230 if (SubOpcode)
231 OS << ") subop " << dwarf::SubOperationEncodingString(OpEncoding: Opcode, SubOpEncoding: *SubOpcode)
232 << " (" << *SubOpcode;
233 OS << ")>";
234 return false;
235 };
236
237 while (I != E) {
238 const DWARFExpression::Operation &Op = *I;
239 uint8_t Opcode = Op.getCode();
240 switch (Opcode) {
241 case dwarf::DW_OP_regx: {
242 // DW_OP_regx: A register, with the register num given as an operand.
243 // Printed as the plain register name.
244 uint64_t DwarfRegNum = Op.getRawOperand(Idx: 0);
245 auto RegName = GetNameForDWARFReg(DwarfRegNum, false);
246 if (RegName.empty())
247 return false;
248 raw_svector_ostream S(Stack.emplace_back(Args: PrintedExpr::Value).String);
249 S << RegName;
250 break;
251 }
252 case dwarf::DW_OP_bregx: {
253 int DwarfRegNum = Op.getRawOperand(Idx: 0);
254 int64_t Offset = Op.getRawOperand(Idx: 1);
255 auto RegName = GetNameForDWARFReg(DwarfRegNum, false);
256 if (RegName.empty())
257 return false;
258 raw_svector_ostream S(Stack.emplace_back().String);
259 S << RegName;
260 if (Offset)
261 S << formatv(Fmt: "{0:+d}", Vals&: Offset);
262 break;
263 }
264 case dwarf::DW_OP_entry_value:
265 case dwarf::DW_OP_GNU_entry_value: {
266 // DW_OP_entry_value contains a sub-expression which must be rendered
267 // separately.
268 uint64_t SubExprLength = Op.getRawOperand(Idx: 0);
269 DWARFExpression::iterator SubExprEnd = I.skipBytes(Add: SubExprLength);
270 ++I;
271 raw_svector_ostream S(Stack.emplace_back().String);
272 S << "entry(";
273 printCompactDWARFExpr(OS&: S, I, E: SubExprEnd, GetNameForDWARFReg);
274 S << ")";
275 I = SubExprEnd;
276 continue;
277 }
278 case dwarf::DW_OP_stack_value: {
279 // The top stack entry should be treated as the actual value of tne
280 // variable, rather than the address of the variable in memory.
281 assert(!Stack.empty());
282 Stack.back().Kind = PrintedExpr::Value;
283 break;
284 }
285 case dwarf::DW_OP_nop: {
286 break;
287 }
288 case dwarf::DW_OP_LLVM_user: {
289 std::optional<unsigned> SubOpcode = Op.getSubCode();
290 if (SubOpcode == dwarf::DW_OP_LLVM_nop)
291 break;
292 return UnknownOpcode(OS, Opcode, SubOpcode);
293 }
294 default:
295 if (Opcode >= dwarf::DW_OP_reg0 && Opcode <= dwarf::DW_OP_reg31) {
296 // DW_OP_reg<N>: A register, with the register num implied by the
297 // opcode. Printed as the plain register name.
298 uint64_t DwarfRegNum = Opcode - dwarf::DW_OP_reg0;
299 auto RegName = GetNameForDWARFReg(DwarfRegNum, false);
300 if (RegName.empty())
301 return false;
302 raw_svector_ostream S(Stack.emplace_back(Args: PrintedExpr::Value).String);
303 S << RegName;
304 } else if (Opcode >= dwarf::DW_OP_breg0 &&
305 Opcode <= dwarf::DW_OP_breg31) {
306 int DwarfRegNum = Opcode - dwarf::DW_OP_breg0;
307 int64_t Offset = Op.getRawOperand(Idx: 0);
308 auto RegName = GetNameForDWARFReg(DwarfRegNum, false);
309 if (RegName.empty())
310 return false;
311 raw_svector_ostream S(Stack.emplace_back().String);
312 S << RegName;
313 if (Offset)
314 S << formatv(Fmt: "{0:+d}", Vals&: Offset);
315 } else {
316 return UnknownOpcode(OS, Opcode, std::nullopt);
317 }
318 break;
319 }
320 ++I;
321 }
322
323 if (Stack.size() != 1) {
324 OS << "<stack of size " << Stack.size() << ", expected 1>";
325 return false;
326 }
327
328 if (Stack.front().Kind == PrintedExpr::Address)
329 OS << "[" << Stack.front().String << "]";
330 else
331 OS << Stack.front().String;
332
333 return true;
334}
335
336bool printDwarfExpressionCompact(
337 const DWARFExpression *E, raw_ostream &OS,
338 std::function<StringRef(uint64_t RegNum, bool IsEH)> GetNameForDWARFReg) {
339 return printCompactDWARFExpr(OS, I: E->begin(), E: E->end(), GetNameForDWARFReg);
340}
341
342bool prettyPrintRegisterOp(DWARFUnit *U, raw_ostream &OS,
343 DIDumpOptions DumpOpts, uint8_t Opcode,
344 ArrayRef<uint64_t> Operands) {
345 if (!DumpOpts.GetNameForDWARFReg)
346 return false;
347
348 uint64_t DwarfRegNum;
349 unsigned OpNum = 0;
350
351 std::optional<unsigned> SubOpcode;
352 if (Opcode == DW_OP_LLVM_user)
353 SubOpcode = Operands[OpNum++];
354
355 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx ||
356 Opcode == DW_OP_regval_type || SubOpcode == DW_OP_LLVM_aspace_bregx ||
357 SubOpcode == DW_OP_LLVM_call_frame_entry_reg)
358 DwarfRegNum = Operands[OpNum++];
359 else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx)
360 DwarfRegNum = Opcode - DW_OP_breg0;
361 else
362 DwarfRegNum = Opcode - DW_OP_reg0;
363
364 auto RegName = DumpOpts.GetNameForDWARFReg(DwarfRegNum, DumpOpts.IsEH);
365 if (!RegName.empty()) {
366 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) ||
367 Opcode == DW_OP_bregx || SubOpcode == DW_OP_LLVM_aspace_bregx)
368 OS << ' ' << RegName << formatv(Fmt: "{0:+d}", Vals: int64_t(Operands[OpNum]));
369 else
370 OS << ' ' << RegName.data();
371
372 if (Opcode == DW_OP_regval_type)
373 prettyPrintBaseTypeRef(U, OS, DumpOpts, Operands, Operand: 1);
374 return true;
375 }
376
377 return false;
378}
379
380} // namespace llvm
381