1//===-- DWARFExpression.cpp -----------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/DebugInfo/DWARF/LowLevel/DWARFExpression.h"
10#include <cassert>
11#include <cstdint>
12#include <vector>
13
14using namespace llvm;
15using namespace dwarf;
16
17namespace llvm {
18
19typedef DWARFExpression::Operation Op;
20typedef Op::Description Desc;
21
22static std::vector<Desc> getOpDescriptions() {
23 std::vector<Desc> Descriptions;
24 Descriptions.resize(new_size: 0xff);
25 Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr);
26 Descriptions[DW_OP_deref] = Desc(Op::Dwarf2);
27 Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1);
28 Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1);
29 Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2);
30 Descriptions[DW_OP_const2s] = Desc(Op::Dwarf2, Op::SignedSize2);
31 Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4);
32 Descriptions[DW_OP_const4s] = Desc(Op::Dwarf2, Op::SignedSize4);
33 Descriptions[DW_OP_const8u] = Desc(Op::Dwarf2, Op::Size8);
34 Descriptions[DW_OP_const8s] = Desc(Op::Dwarf2, Op::SignedSize8);
35 Descriptions[DW_OP_constu] = Desc(Op::Dwarf2, Op::SizeLEB);
36 Descriptions[DW_OP_consts] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
37 Descriptions[DW_OP_dup] = Desc(Op::Dwarf2);
38 Descriptions[DW_OP_drop] = Desc(Op::Dwarf2);
39 Descriptions[DW_OP_over] = Desc(Op::Dwarf2);
40 Descriptions[DW_OP_pick] = Desc(Op::Dwarf2, Op::Size1);
41 Descriptions[DW_OP_swap] = Desc(Op::Dwarf2);
42 Descriptions[DW_OP_rot] = Desc(Op::Dwarf2);
43 Descriptions[DW_OP_xderef] = Desc(Op::Dwarf2);
44 Descriptions[DW_OP_abs] = Desc(Op::Dwarf2);
45 Descriptions[DW_OP_and] = Desc(Op::Dwarf2);
46 Descriptions[DW_OP_div] = Desc(Op::Dwarf2);
47 Descriptions[DW_OP_minus] = Desc(Op::Dwarf2);
48 Descriptions[DW_OP_mod] = Desc(Op::Dwarf2);
49 Descriptions[DW_OP_mul] = Desc(Op::Dwarf2);
50 Descriptions[DW_OP_neg] = Desc(Op::Dwarf2);
51 Descriptions[DW_OP_not] = Desc(Op::Dwarf2);
52 Descriptions[DW_OP_or] = Desc(Op::Dwarf2);
53 Descriptions[DW_OP_plus] = Desc(Op::Dwarf2);
54 Descriptions[DW_OP_plus_uconst] = Desc(Op::Dwarf2, Op::SizeLEB);
55 Descriptions[DW_OP_shl] = Desc(Op::Dwarf2);
56 Descriptions[DW_OP_shr] = Desc(Op::Dwarf2);
57 Descriptions[DW_OP_shra] = Desc(Op::Dwarf2);
58 Descriptions[DW_OP_xor] = Desc(Op::Dwarf2);
59 Descriptions[DW_OP_bra] = Desc(Op::Dwarf2, Op::SignedSize2);
60 Descriptions[DW_OP_eq] = Desc(Op::Dwarf2);
61 Descriptions[DW_OP_ge] = Desc(Op::Dwarf2);
62 Descriptions[DW_OP_gt] = Desc(Op::Dwarf2);
63 Descriptions[DW_OP_le] = Desc(Op::Dwarf2);
64 Descriptions[DW_OP_lt] = Desc(Op::Dwarf2);
65 Descriptions[DW_OP_ne] = Desc(Op::Dwarf2);
66 Descriptions[DW_OP_skip] = Desc(Op::Dwarf2, Op::SignedSize2);
67 for (uint16_t LA = DW_OP_lit0; LA <= DW_OP_lit31; ++LA)
68 Descriptions[LA] = Desc(Op::Dwarf2);
69 for (uint16_t LA = DW_OP_reg0; LA <= DW_OP_reg31; ++LA)
70 Descriptions[LA] = Desc(Op::Dwarf2);
71 for (uint16_t LA = DW_OP_breg0; LA <= DW_OP_breg31; ++LA)
72 Descriptions[LA] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
73 Descriptions[DW_OP_regx] = Desc(Op::Dwarf2, Op::SizeLEB);
74 Descriptions[DW_OP_fbreg] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
75 Descriptions[DW_OP_bregx] = Desc(Op::Dwarf2, Op::SizeLEB, Op::SignedSizeLEB);
76 Descriptions[DW_OP_piece] = Desc(Op::Dwarf2, Op::SizeLEB);
77 Descriptions[DW_OP_deref_size] = Desc(Op::Dwarf2, Op::Size1);
78 Descriptions[DW_OP_xderef_size] = Desc(Op::Dwarf2, Op::Size1);
79 Descriptions[DW_OP_nop] = Desc(Op::Dwarf2);
80 Descriptions[DW_OP_push_object_address] = Desc(Op::Dwarf3);
81 Descriptions[DW_OP_call2] = Desc(Op::Dwarf3, Op::Size2);
82 Descriptions[DW_OP_call4] = Desc(Op::Dwarf3, Op::Size4);
83 Descriptions[DW_OP_call_ref] = Desc(Op::Dwarf3, Op::SizeRefAddr);
84 Descriptions[DW_OP_form_tls_address] = Desc(Op::Dwarf3);
85 Descriptions[DW_OP_call_frame_cfa] = Desc(Op::Dwarf3);
86 Descriptions[DW_OP_bit_piece] = Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeLEB);
87 Descriptions[DW_OP_implicit_value] =
88 Desc(Op::Dwarf4, Op::SizeLEB, Op::SizeBlock);
89 Descriptions[DW_OP_stack_value] = Desc(Op::Dwarf4);
90 Descriptions[DW_OP_implicit_pointer] =
91 Desc(Op::Dwarf5, Op::SizeRefAddr, Op::SignedSizeLEB);
92 Descriptions[DW_OP_addrx] = Desc(Op::Dwarf5, Op::SizeLEB);
93 Descriptions[DW_OP_constx] = Desc(Op::Dwarf5, Op::SizeLEB);
94 Descriptions[DW_OP_entry_value] = Desc(Op::Dwarf5, Op::SizeLEB);
95 Descriptions[DW_OP_convert] = Desc(Op::Dwarf5, Op::BaseTypeRef);
96 Descriptions[DW_OP_regval_type] =
97 Desc(Op::Dwarf5, Op::SizeLEB, Op::BaseTypeRef);
98 Descriptions[DW_OP_WASM_location] =
99 Desc(Op::Dwarf4, Op::SizeLEB, Op::WasmLocationArg);
100 Descriptions[DW_OP_GNU_push_tls_address] = Desc(Op::Dwarf3);
101 Descriptions[DW_OP_GNU_addr_index] = Desc(Op::Dwarf4, Op::SizeLEB);
102 Descriptions[DW_OP_GNU_const_index] = Desc(Op::Dwarf4, Op::SizeLEB);
103 Descriptions[DW_OP_GNU_entry_value] = Desc(Op::Dwarf4, Op::SizeLEB);
104 Descriptions[DW_OP_GNU_implicit_pointer] =
105 Desc(Op::Dwarf4, Op::SizeRefAddr, Op::SignedSizeLEB);
106 // This Description acts as a marker that getSubOpDesc must be called
107 // to fetch the final Description for the operation. Each such final
108 // Description must share the same first SizeSubOpLEB operand.
109 Descriptions[DW_OP_LLVM_user] = Desc(Op::Dwarf5, Op::SizeSubOpLEB);
110 return Descriptions;
111}
112
113static Desc getDescImpl(ArrayRef<Desc> Descriptions, unsigned Opcode) {
114 // Handle possible corrupted or unsupported operation.
115 if (Opcode >= Descriptions.size())
116 return {};
117 return Descriptions[Opcode];
118}
119
120static Desc getOpDesc(unsigned Opcode) {
121 static std::vector<Desc> Descriptions = getOpDescriptions();
122 return getDescImpl(Descriptions, Opcode);
123}
124
125static std::vector<Desc> getSubOpDescriptions() {
126 static constexpr unsigned LlvmUserDescriptionsSize = 1
127#define HANDLE_DW_OP_LLVM_USEROP(ID, NAME) +1
128#include "llvm/BinaryFormat/Dwarf.def"
129 ;
130 std::vector<Desc> Descriptions;
131 Descriptions.resize(new_size: LlvmUserDescriptionsSize);
132 Descriptions[DW_OP_LLVM_nop] = Desc(Op::Dwarf5, Op::SizeSubOpLEB);
133 Descriptions[DW_OP_LLVM_form_aspace_address] =
134 Desc(Op::Dwarf5, Op::SizeSubOpLEB);
135 Descriptions[DW_OP_LLVM_push_lane] = Desc(Op::Dwarf5, Op::SizeSubOpLEB);
136 Descriptions[DW_OP_LLVM_offset] = Desc(Op::Dwarf5, Op::SizeSubOpLEB);
137 Descriptions[DW_OP_LLVM_offset_uconst] =
138 Desc(Op::Dwarf5, Op::SizeSubOpLEB, Op::SizeLEB);
139 Descriptions[DW_OP_LLVM_bit_offset] = Desc(Op::Dwarf5, Op::SizeSubOpLEB);
140 Descriptions[DW_OP_LLVM_call_frame_entry_reg] =
141 Desc(Op::Dwarf5, Op::SizeSubOpLEB, Op::SizeLEB);
142 Descriptions[DW_OP_LLVM_undefined] = Desc(Op::Dwarf5, Op::SizeSubOpLEB);
143 Descriptions[DW_OP_LLVM_aspace_bregx] =
144 Desc(Op::Dwarf5, Op::SizeSubOpLEB, Op::SizeLEB, Op::SizeLEB);
145 Descriptions[DW_OP_LLVM_piece_end] = Desc(Op::Dwarf5, Op::SizeSubOpLEB);
146 Descriptions[DW_OP_LLVM_extend] =
147 Desc(Op::Dwarf5, Op::SizeSubOpLEB, Op::SizeLEB, Op::SizeLEB);
148 Descriptions[DW_OP_LLVM_select_bit_piece] =
149 Desc(Op::Dwarf5, Op::SizeSubOpLEB, Op::SizeLEB, Op::SizeLEB);
150 Descriptions[DW_OP_LLVM_NVIDIA_mux] =
151 Desc(Op::Dwarf5, Op::SizeSubOpLEB, Op::NvidiaMuxArg);
152 return Descriptions;
153}
154
155static Desc getSubOpDesc(unsigned Opcode, unsigned SubOpcode) {
156 assert(Opcode == DW_OP_LLVM_user);
157 static std::vector<Desc> Descriptions = getSubOpDescriptions();
158 return getDescImpl(Descriptions, Opcode: SubOpcode);
159}
160
161bool DWARFExpression::Operation::extract(DataExtractor Data,
162 uint8_t AddressSize, uint64_t Offset,
163 std::optional<DwarfFormat> Format) {
164 EndOffset = Offset;
165 Opcode = Data.getU8(offset_ptr: &Offset);
166
167 Desc = getOpDesc(Opcode);
168 if (Desc.Version == Operation::DwarfNA)
169 return false;
170
171 Operands.resize(N: Desc.Op.size());
172 OperandEndOffsets.resize(N: Desc.Op.size());
173 for (unsigned Operand = 0; Operand < Desc.Op.size(); ++Operand) {
174 unsigned Size = Desc.Op[Operand];
175 unsigned Signed = Size & Operation::SignBit;
176
177 switch (Size & ~Operation::SignBit) {
178 case Operation::SizeSubOpLEB:
179 assert(Operand == 0 && "SubOp operand must be the first operand");
180 Operands[Operand] = Data.getULEB128(offset_ptr: &Offset);
181 Desc = getSubOpDesc(Opcode, SubOpcode: Operands[Operand]);
182 if (Desc.Version == Operation::DwarfNA)
183 return false;
184 assert(Desc.Op[Operand] == Operation::SizeSubOpLEB &&
185 "SizeSubOpLEB Description must begin with SizeSubOpLEB operand");
186 Operands.resize(N: Desc.Op.size());
187 OperandEndOffsets.resize(N: Desc.Op.size());
188 break;
189 case Operation::Size1:
190 Operands[Operand] = Data.getU8(offset_ptr: &Offset);
191 if (Signed)
192 Operands[Operand] = (int8_t)Operands[Operand];
193 break;
194 case Operation::Size2:
195 Operands[Operand] = Data.getU16(offset_ptr: &Offset);
196 if (Signed)
197 Operands[Operand] = (int16_t)Operands[Operand];
198 break;
199 case Operation::Size4:
200 Operands[Operand] = Data.getU32(offset_ptr: &Offset);
201 if (Signed)
202 Operands[Operand] = (int32_t)Operands[Operand];
203 break;
204 case Operation::Size8:
205 Operands[Operand] = Data.getU64(offset_ptr: &Offset);
206 break;
207 case Operation::SizeAddr:
208 Operands[Operand] = Data.getUnsigned(offset_ptr: &Offset, byte_size: AddressSize);
209 break;
210 case Operation::SizeRefAddr:
211 if (!Format)
212 return false;
213 Operands[Operand] =
214 Data.getUnsigned(offset_ptr: &Offset, byte_size: dwarf::getDwarfOffsetByteSize(Format: *Format));
215 break;
216 case Operation::SizeLEB:
217 if (Signed)
218 Operands[Operand] = Data.getSLEB128(OffsetPtr: &Offset);
219 else
220 Operands[Operand] = Data.getULEB128(offset_ptr: &Offset);
221 break;
222 case Operation::BaseTypeRef:
223 Operands[Operand] = Data.getULEB128(offset_ptr: &Offset);
224 break;
225 case Operation::NvidiaMuxArg:
226 assert(Operand == 1);
227 Operands[Operand] = Data.getULEB128(offset_ptr: &Offset);
228 // The selector names an NVIDIA specific operation, and the number and
229 // type of the operands that follow it are implied by that operation.
230 // No NVIDIA operation is known here, so where this operation ends is
231 // unknown and anything after it would be parsed from the wrong offset.
232 // Refuse to decode rather than mis-parse the rest of the expression.
233 // A build that knows a selector can decode its operands here.
234 return false;
235 case Operation::WasmLocationArg:
236 assert(Operand == 1);
237 switch (Operands[0]) {
238 case 0:
239 case 1:
240 case 2:
241 case 4:
242 Operands[Operand] = Data.getULEB128(offset_ptr: &Offset);
243 break;
244 case 3: // global as uint32
245 Operands[Operand] = Data.getU32(offset_ptr: &Offset);
246 break;
247 default:
248 return false; // Unknown Wasm location
249 }
250 break;
251 case Operation::SizeBlock:
252 // We need a size, so this cannot be the first operand
253 if (Operand == 0)
254 return false;
255 // Store the offset of the block as the value.
256 Operands[Operand] = Offset;
257 Offset += Operands[Operand - 1];
258 break;
259 default:
260 llvm_unreachable("Unknown DWARFExpression Op size");
261 }
262
263 OperandEndOffsets[Operand] = Offset;
264 }
265
266 EndOffset = Offset;
267 return true;
268}
269
270std::optional<unsigned> DWARFExpression::Operation::getSubCode() const {
271 if (!Desc.Op.size() || Desc.Op[0] != Operation::SizeSubOpLEB)
272 return std::nullopt;
273 return Operands[0];
274}
275
276bool DWARFExpression::operator==(const DWARFExpression &RHS) const {
277 if (AddressSize != RHS.AddressSize || Format != RHS.Format)
278 return false;
279 return Data.getData() == RHS.Data.getData();
280}
281
282} // namespace llvm
283