1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the MCLFIRewriter class, a base class that
11/// encapsulates the rewriting logic for MCInsts.
12///
13//===----------------------------------------------------------------------===//
14
15#include "llvm/MC/MCLFIRewriter.h"
16#include "llvm/ADT/Twine.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrInfo.h"
20
21using namespace llvm;
22
23void MCLFIRewriter::error(const MCInst &Inst, const Twine &Msg) {
24 Ctx.reportError(L: Inst.getLoc(), Msg);
25}
26
27void MCLFIRewriter::warning(const MCInst &Inst, const Twine &Msg) {
28 Ctx.reportWarning(L: Inst.getLoc(), Msg);
29}
30
31bool MCLFIRewriter::isCall(const MCInst &Inst) const {
32 return InstInfo->get(Opcode: Inst.getOpcode()).isCall();
33}
34
35bool MCLFIRewriter::isBranch(const MCInst &Inst) const {
36 return InstInfo->get(Opcode: Inst.getOpcode()).isBranch();
37}
38
39bool MCLFIRewriter::isIndirectBranch(const MCInst &Inst) const {
40 return InstInfo->get(Opcode: Inst.getOpcode()).isIndirectBranch();
41}
42
43bool MCLFIRewriter::isReturn(const MCInst &Inst) const {
44 return InstInfo->get(Opcode: Inst.getOpcode()).isReturn();
45}
46
47bool MCLFIRewriter::mayLoad(const MCInst &Inst) const {
48 return InstInfo->get(Opcode: Inst.getOpcode()).mayLoad();
49}
50
51bool MCLFIRewriter::mayStore(const MCInst &Inst) const {
52 return InstInfo->get(Opcode: Inst.getOpcode()).mayStore();
53}
54
55bool MCLFIRewriter::mayModifyRegister(const MCInst &Inst,
56 MCRegister Reg) const {
57 return InstInfo->get(Opcode: Inst.getOpcode()).hasDefOfPhysReg(MI: Inst, Reg, RI: *RegInfo);
58}
59
60bool MCLFIRewriter::explicitlyModifiesRegister(const MCInst &Inst,
61 MCRegister Reg) const {
62 return InstInfo->get(Opcode: Inst.getOpcode())
63 .hasExplicitDefOfPhysReg(MI: Inst, Reg, RI: *RegInfo);
64}
65