1//===---------------------------- Context.cpp -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines a class for holding ownership of various simulated
11/// hardware units. A Context also provides a utility routine for constructing
12/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13/// stages.
14///
15//===----------------------------------------------------------------------===//
16
17#include "llvm/MCA/Context.h"
18#include "llvm/MCA/HardwareUnits/RegisterFile.h"
19#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
20#include "llvm/MCA/HardwareUnits/Scheduler.h"
21#include "llvm/MCA/Stages/DispatchStage.h"
22#include "llvm/MCA/Stages/EntryStage.h"
23#include "llvm/MCA/Stages/ExecuteStage.h"
24#include "llvm/MCA/Stages/InOrderIssueStage.h"
25#include "llvm/MCA/Stages/MicroOpQueueStage.h"
26#include "llvm/MCA/Stages/RetireStage.h"
27
28namespace llvm {
29namespace mca {
30
31std::unique_ptr<Pipeline>
32Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
33 CustomBehaviour &CB) {
34 const MCSchedModel &SM = STI.getSchedModel();
35
36 if (!SM.isOutOfOrder())
37 return createInOrderPipeline(Opts, SrcMgr, CB);
38
39 // Create the hardware units defining the backend.
40 auto RCU = std::make_unique<RetireControlUnit>(args: SM);
41 auto PRF = std::make_unique<RegisterFile>(args: SM, args: MRI, args: Opts.RegisterFileSize);
42 auto LSU = std::make_unique<LSUnit>(args: SM, args: Opts.LoadQueueSize,
43 args: Opts.StoreQueueSize, args: Opts.AssumeNoAlias);
44 auto HWS =
45 std::make_unique<Scheduler>(args: SM, args&: *LSU, args: Opts.ReservationStationScaleFactor);
46
47 // Create the pipeline stages.
48 auto Fetch = std::make_unique<EntryStage>(args&: SrcMgr);
49 auto Dispatch =
50 std::make_unique<DispatchStage>(args: STI, args: MRI, args: Opts.DispatchWidth, args&: *RCU, args&: *PRF);
51 auto Execute =
52 std::make_unique<ExecuteStage>(args&: *HWS, args: Opts.EnableBottleneckAnalysis);
53 auto Retire = std::make_unique<RetireStage>(args&: *RCU, args&: *PRF, args&: *LSU);
54
55 // Pass the ownership of all the hardware units to this Context.
56 addHardwareUnit(H: std::move(RCU));
57 addHardwareUnit(H: std::move(PRF));
58 addHardwareUnit(H: std::move(LSU));
59 addHardwareUnit(H: std::move(HWS));
60
61 // Build the pipeline.
62 auto StagePipeline = std::make_unique<Pipeline>();
63 StagePipeline->appendStage(S: std::move(Fetch));
64 if (Opts.MicroOpQueueSize)
65 StagePipeline->appendStage(S: std::make_unique<MicroOpQueueStage>(
66 args: Opts.MicroOpQueueSize, args: Opts.DecodersThroughput));
67 StagePipeline->appendStage(S: std::move(Dispatch));
68 StagePipeline->appendStage(S: std::move(Execute));
69 StagePipeline->appendStage(S: std::move(Retire));
70 return StagePipeline;
71}
72
73std::unique_ptr<Pipeline>
74Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
75 CustomBehaviour &CB) {
76 const MCSchedModel &SM = STI.getSchedModel();
77 auto PRF = std::make_unique<RegisterFile>(args: SM, args: MRI, args: Opts.RegisterFileSize);
78 auto LSU = std::make_unique<LSUnit>(args: SM, args: Opts.LoadQueueSize,
79 args: Opts.StoreQueueSize, args: Opts.AssumeNoAlias);
80
81 // Create the pipeline stages.
82 auto Entry = std::make_unique<EntryStage>(args&: SrcMgr);
83 auto InOrderIssue = std::make_unique<InOrderIssueStage>(
84 args: STI, args&: *PRF, args&: CB, args&: *LSU, args: Opts.ReservationStationScaleFactor);
85 auto StagePipeline = std::make_unique<Pipeline>();
86
87 // Pass the ownership of all the hardware units to this Context.
88 addHardwareUnit(H: std::move(PRF));
89 addHardwareUnit(H: std::move(LSU));
90
91 // Build the pipeline.
92 StagePipeline->appendStage(S: std::move(Entry));
93 StagePipeline->appendStage(S: std::move(InOrderIssue));
94 return StagePipeline;
95}
96
97} // namespace mca
98} // namespace llvm
99