1//===- ELFObjectFile.cpp - ELF object file implementation -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Part of the ELFObjectFile class implementation.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/Object/ELFObjectFile.h"
14#include "llvm/BinaryFormat/ELF.h"
15#include "llvm/MC/MCInstrAnalysis.h"
16#include "llvm/MC/TargetRegistry.h"
17#include "llvm/Object/ELF.h"
18#include "llvm/Object/ELFTypes.h"
19#include "llvm/Object/Error.h"
20#include "llvm/Support/ARMAttributeParser.h"
21#include "llvm/Support/ARMBuildAttributes.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/HexagonAttributeParser.h"
24#include "llvm/Support/RISCVAttributeParser.h"
25#include "llvm/Support/RISCVAttributes.h"
26#include "llvm/TargetParser/RISCVISAInfo.h"
27#include "llvm/TargetParser/SubtargetFeature.h"
28#include "llvm/TargetParser/Triple.h"
29#include <algorithm>
30#include <cstddef>
31#include <cstdint>
32#include <memory>
33#include <optional>
34#include <string>
35#include <utility>
36
37using namespace llvm;
38using namespace object;
39
40const EnumEntry<unsigned> llvm::object::ElfSymbolTypes[NumElfSymbolTypes] = {
41 {"None", "NOTYPE", ELF::STT_NOTYPE},
42 {"Object", "OBJECT", ELF::STT_OBJECT},
43 {"Function", "FUNC", ELF::STT_FUNC},
44 {"Section", "SECTION", ELF::STT_SECTION},
45 {"File", "FILE", ELF::STT_FILE},
46 {"Common", "COMMON", ELF::STT_COMMON},
47 {"TLS", "TLS", ELF::STT_TLS},
48 {"Unknown", "<unknown>: 7", 7},
49 {"Unknown", "<unknown>: 8", 8},
50 {"Unknown", "<unknown>: 9", 9},
51 {"GNU_IFunc", "IFUNC", ELF::STT_GNU_IFUNC},
52 {"OS Specific", "<OS specific>: 11", 11},
53 {"OS Specific", "<OS specific>: 12", 12},
54 {"Proc Specific", "<processor specific>: 13", 13},
55 {"Proc Specific", "<processor specific>: 14", 14},
56 {"Proc Specific", "<processor specific>: 15", 15}
57};
58
59ELFObjectFileBase::ELFObjectFileBase(unsigned int Type, MemoryBufferRef Source)
60 : ObjectFile(Type, Source) {}
61
62template <class ELFT>
63static Expected<std::unique_ptr<ELFObjectFile<ELFT>>>
64createPtr(MemoryBufferRef Object, bool InitContent) {
65 auto Ret = ELFObjectFile<ELFT>::create(Object, InitContent);
66 if (Error E = Ret.takeError())
67 return std::move(E);
68 return std::make_unique<ELFObjectFile<ELFT>>(std::move(*Ret));
69}
70
71Expected<std::unique_ptr<ObjectFile>>
72ObjectFile::createELFObjectFile(MemoryBufferRef Obj, bool InitContent) {
73 std::pair<unsigned char, unsigned char> Ident =
74 getElfArchType(Object: Obj.getBuffer());
75 std::size_t MaxAlignment =
76 1ULL << llvm::countr_zero(
77 Val: reinterpret_cast<uintptr_t>(Obj.getBufferStart()));
78
79 if (MaxAlignment < 2)
80 return createError(Err: "Insufficient alignment");
81
82 if (Ident.first == ELF::ELFCLASS32) {
83 if (Ident.second == ELF::ELFDATA2LSB)
84 return createPtr<ELF32LE>(Object: Obj, InitContent);
85 else if (Ident.second == ELF::ELFDATA2MSB)
86 return createPtr<ELF32BE>(Object: Obj, InitContent);
87 else
88 return createError(Err: "Invalid ELF data");
89 } else if (Ident.first == ELF::ELFCLASS64) {
90 if (Ident.second == ELF::ELFDATA2LSB)
91 return createPtr<ELF64LE>(Object: Obj, InitContent);
92 else if (Ident.second == ELF::ELFDATA2MSB)
93 return createPtr<ELF64BE>(Object: Obj, InitContent);
94 else
95 return createError(Err: "Invalid ELF data");
96 }
97 return createError(Err: "Invalid ELF class");
98}
99
100SubtargetFeatures ELFObjectFileBase::getMIPSFeatures() const {
101 SubtargetFeatures Features;
102 unsigned PlatformFlags = getPlatformFlags();
103
104 switch (PlatformFlags & ELF::EF_MIPS_ARCH) {
105 case ELF::EF_MIPS_ARCH_1:
106 break;
107 case ELF::EF_MIPS_ARCH_2:
108 Features.AddFeature(String: "mips2");
109 break;
110 case ELF::EF_MIPS_ARCH_3:
111 Features.AddFeature(String: "mips3");
112 break;
113 case ELF::EF_MIPS_ARCH_4:
114 Features.AddFeature(String: "mips4");
115 break;
116 case ELF::EF_MIPS_ARCH_5:
117 Features.AddFeature(String: "mips5");
118 break;
119 case ELF::EF_MIPS_ARCH_32:
120 Features.AddFeature(String: "mips32");
121 break;
122 case ELF::EF_MIPS_ARCH_64:
123 Features.AddFeature(String: "mips64");
124 break;
125 case ELF::EF_MIPS_ARCH_32R2:
126 Features.AddFeature(String: "mips32r2");
127 break;
128 case ELF::EF_MIPS_ARCH_64R2:
129 Features.AddFeature(String: "mips64r2");
130 break;
131 case ELF::EF_MIPS_ARCH_32R6:
132 Features.AddFeature(String: "mips32r6");
133 break;
134 case ELF::EF_MIPS_ARCH_64R6:
135 Features.AddFeature(String: "mips64r6");
136 break;
137 default:
138 llvm_unreachable("Unknown EF_MIPS_ARCH value");
139 }
140
141 switch (PlatformFlags & ELF::EF_MIPS_MACH) {
142 case ELF::EF_MIPS_MACH_NONE:
143 // No feature associated with this value.
144 break;
145 case ELF::EF_MIPS_MACH_OCTEON:
146 Features.AddFeature(String: "cnmips");
147 break;
148 default:
149 llvm_unreachable("Unknown EF_MIPS_ARCH value");
150 }
151
152 if (PlatformFlags & ELF::EF_MIPS_ARCH_ASE_M16)
153 Features.AddFeature(String: "mips16");
154 if (PlatformFlags & ELF::EF_MIPS_MICROMIPS)
155 Features.AddFeature(String: "micromips");
156
157 return Features;
158}
159
160SubtargetFeatures ELFObjectFileBase::getARMFeatures() const {
161 SubtargetFeatures Features;
162 ARMAttributeParser Attributes;
163 if (Error E = getBuildAttributes(Attributes)) {
164 consumeError(Err: std::move(E));
165 return SubtargetFeatures();
166 }
167
168 // both ARMv7-M and R have to support thumb hardware div
169 bool isV7 = false;
170 std::optional<unsigned> Attr =
171 Attributes.getAttributeValue(tag: ARMBuildAttrs::CPU_arch);
172 if (Attr)
173 isV7 = *Attr == ARMBuildAttrs::v7;
174
175 Attr = Attributes.getAttributeValue(tag: ARMBuildAttrs::CPU_arch_profile);
176 if (Attr) {
177 switch (*Attr) {
178 case ARMBuildAttrs::ApplicationProfile:
179 Features.AddFeature(String: "aclass");
180 break;
181 case ARMBuildAttrs::RealTimeProfile:
182 Features.AddFeature(String: "rclass");
183 if (isV7)
184 Features.AddFeature(String: "hwdiv");
185 break;
186 case ARMBuildAttrs::MicroControllerProfile:
187 Features.AddFeature(String: "mclass");
188 if (isV7)
189 Features.AddFeature(String: "hwdiv");
190 break;
191 }
192 }
193
194 Attr = Attributes.getAttributeValue(tag: ARMBuildAttrs::THUMB_ISA_use);
195 if (Attr) {
196 switch (*Attr) {
197 default:
198 break;
199 case ARMBuildAttrs::Not_Allowed:
200 Features.AddFeature(String: "thumb", Enable: false);
201 Features.AddFeature(String: "thumb2", Enable: false);
202 break;
203 case ARMBuildAttrs::AllowThumb32:
204 Features.AddFeature(String: "thumb2");
205 break;
206 }
207 }
208
209 Attr = Attributes.getAttributeValue(tag: ARMBuildAttrs::FP_arch);
210 if (Attr) {
211 switch (*Attr) {
212 default:
213 break;
214 case ARMBuildAttrs::Not_Allowed:
215 Features.AddFeature(String: "vfp2sp", Enable: false);
216 Features.AddFeature(String: "vfp3d16sp", Enable: false);
217 Features.AddFeature(String: "vfp4d16sp", Enable: false);
218 break;
219 case ARMBuildAttrs::AllowFPv2:
220 Features.AddFeature(String: "vfp2");
221 break;
222 case ARMBuildAttrs::AllowFPv3A:
223 case ARMBuildAttrs::AllowFPv3B:
224 Features.AddFeature(String: "vfp3");
225 break;
226 case ARMBuildAttrs::AllowFPv4A:
227 case ARMBuildAttrs::AllowFPv4B:
228 Features.AddFeature(String: "vfp4");
229 break;
230 }
231 }
232
233 Attr = Attributes.getAttributeValue(tag: ARMBuildAttrs::Advanced_SIMD_arch);
234 if (Attr) {
235 switch (*Attr) {
236 default:
237 break;
238 case ARMBuildAttrs::Not_Allowed:
239 Features.AddFeature(String: "neon", Enable: false);
240 Features.AddFeature(String: "fp16", Enable: false);
241 break;
242 case ARMBuildAttrs::AllowNeon:
243 Features.AddFeature(String: "neon");
244 break;
245 case ARMBuildAttrs::AllowNeon2:
246 Features.AddFeature(String: "neon");
247 Features.AddFeature(String: "fp16");
248 break;
249 }
250 }
251
252 Attr = Attributes.getAttributeValue(tag: ARMBuildAttrs::MVE_arch);
253 if (Attr) {
254 switch (*Attr) {
255 default:
256 break;
257 case ARMBuildAttrs::Not_Allowed:
258 Features.AddFeature(String: "mve", Enable: false);
259 Features.AddFeature(String: "mve.fp", Enable: false);
260 break;
261 case ARMBuildAttrs::AllowMVEInteger:
262 Features.AddFeature(String: "mve.fp", Enable: false);
263 Features.AddFeature(String: "mve");
264 break;
265 case ARMBuildAttrs::AllowMVEIntegerAndFloat:
266 Features.AddFeature(String: "mve.fp");
267 break;
268 }
269 }
270
271 Attr = Attributes.getAttributeValue(tag: ARMBuildAttrs::DIV_use);
272 if (Attr) {
273 switch (*Attr) {
274 default:
275 break;
276 case ARMBuildAttrs::DisallowDIV:
277 Features.AddFeature(String: "hwdiv", Enable: false);
278 Features.AddFeature(String: "hwdiv-arm", Enable: false);
279 break;
280 case ARMBuildAttrs::AllowDIVExt:
281 Features.AddFeature(String: "hwdiv");
282 Features.AddFeature(String: "hwdiv-arm");
283 break;
284 }
285 }
286
287 return Features;
288}
289
290static std::optional<std::string> hexagonAttrToFeatureString(unsigned Attr) {
291 switch (Attr) {
292 case 5:
293 return "v5";
294 case 55:
295 return "v55";
296 case 60:
297 return "v60";
298 case 62:
299 return "v62";
300 case 65:
301 return "v65";
302 case 67:
303 return "v67";
304 case 68:
305 return "v68";
306 case 69:
307 return "v69";
308 case 71:
309 return "v71";
310 case 73:
311 return "v73";
312 case 75:
313 return "v75";
314 case 79:
315 return "v79";
316 case 81:
317 return "v81";
318 default:
319 return {};
320 }
321}
322
323SubtargetFeatures ELFObjectFileBase::getHexagonFeatures() const {
324 SubtargetFeatures Features;
325 HexagonAttributeParser Parser;
326 if (Error E = getBuildAttributes(Attributes&: Parser)) {
327 // Return no attributes if none can be read.
328 // This behavior is important for backwards compatibility.
329 consumeError(Err: std::move(E));
330 return Features;
331 }
332 std::optional<unsigned> Attr;
333
334 if ((Attr = Parser.getAttributeValue(tag: HexagonAttrs::ARCH))) {
335 if (std::optional<std::string> FeatureString =
336 hexagonAttrToFeatureString(Attr: *Attr))
337 Features.AddFeature(String: *FeatureString);
338 }
339
340 if ((Attr = Parser.getAttributeValue(tag: HexagonAttrs::HVXARCH))) {
341 std::optional<std::string> FeatureString =
342 hexagonAttrToFeatureString(Attr: *Attr);
343 // There is no corresponding hvx arch for v5 and v55.
344 if (FeatureString && *Attr >= 60)
345 Features.AddFeature(String: "hvx" + *FeatureString);
346 }
347
348 if ((Attr = Parser.getAttributeValue(tag: HexagonAttrs::HVXIEEEFP)))
349 if (*Attr)
350 Features.AddFeature(String: "hvx-ieee-fp");
351
352 if ((Attr = Parser.getAttributeValue(tag: HexagonAttrs::HVXQFLOAT)))
353 if (*Attr)
354 Features.AddFeature(String: "hvx-qfloat");
355
356 if ((Attr = Parser.getAttributeValue(tag: HexagonAttrs::ZREG)))
357 if (*Attr)
358 Features.AddFeature(String: "zreg");
359
360 if ((Attr = Parser.getAttributeValue(tag: HexagonAttrs::AUDIO)))
361 if (*Attr)
362 Features.AddFeature(String: "audio");
363
364 if ((Attr = Parser.getAttributeValue(tag: HexagonAttrs::CABAC)))
365 if (*Attr)
366 Features.AddFeature(String: "cabac");
367
368 return Features;
369}
370
371Expected<SubtargetFeatures> ELFObjectFileBase::getRISCVFeatures() const {
372 SubtargetFeatures Features;
373 unsigned PlatformFlags = getPlatformFlags();
374
375 if (PlatformFlags & ELF::EF_RISCV_RVC) {
376 Features.AddFeature(String: "zca");
377 }
378
379 RISCVAttributeParser Attributes;
380 if (Error E = getBuildAttributes(Attributes)) {
381 return std::move(E);
382 }
383
384 std::optional<StringRef> Attr =
385 Attributes.getAttributeString(tag: RISCVAttrs::ARCH);
386 if (Attr) {
387 auto ParseResult = RISCVISAInfo::parseNormalizedArchString(Arch: *Attr);
388 if (!ParseResult)
389 return ParseResult.takeError();
390 auto &ISAInfo = *ParseResult;
391
392 if (ISAInfo->getXLen() == 32)
393 Features.AddFeature(String: "64bit", Enable: false);
394 else if (ISAInfo->getXLen() == 64)
395 Features.AddFeature(String: "64bit");
396 else
397 llvm_unreachable("XLEN should be 32 or 64.");
398
399 Features.addFeaturesVector(OtherFeatures: ISAInfo->toFeatures());
400 }
401
402 return Features;
403}
404
405SubtargetFeatures ELFObjectFileBase::getLoongArchFeatures() const {
406 SubtargetFeatures Features;
407
408 switch (getPlatformFlags() & ELF::EF_LOONGARCH_ABI_MODIFIER_MASK) {
409 case ELF::EF_LOONGARCH_ABI_SOFT_FLOAT:
410 break;
411 case ELF::EF_LOONGARCH_ABI_DOUBLE_FLOAT:
412 Features.AddFeature(String: "d");
413 // D implies F according to LoongArch ISA spec.
414 [[fallthrough]];
415 case ELF::EF_LOONGARCH_ABI_SINGLE_FLOAT:
416 Features.AddFeature(String: "f");
417 break;
418 }
419
420 return Features;
421}
422
423Expected<SubtargetFeatures> ELFObjectFileBase::getFeatures() const {
424 switch (getEMachine()) {
425 case ELF::EM_MIPS:
426 return getMIPSFeatures();
427 case ELF::EM_ARM:
428 return getARMFeatures();
429 case ELF::EM_RISCV:
430 return getRISCVFeatures();
431 case ELF::EM_LOONGARCH:
432 return getLoongArchFeatures();
433 case ELF::EM_HEXAGON:
434 return getHexagonFeatures();
435 default:
436 return SubtargetFeatures();
437 }
438}
439
440std::optional<StringRef> ELFObjectFileBase::tryGetCPUName() const {
441 switch (getEMachine()) {
442 case ELF::EM_AMDGPU:
443 return getAMDGPUCPUName();
444 case ELF::EM_CUDA:
445 return getNVPTXCPUName();
446 case ELF::EM_PPC:
447 case ELF::EM_PPC64:
448 return StringRef("future");
449 case ELF::EM_BPF:
450 return StringRef("v4");
451 default:
452 return std::nullopt;
453 }
454}
455
456StringRef ELFObjectFileBase::getAMDGPUCPUName() const {
457 assert(getEMachine() == ELF::EM_AMDGPU);
458 unsigned CPU = getPlatformFlags() & ELF::EF_AMDGPU_MACH;
459
460 switch (CPU) {
461 // Radeon HD 2000/3000 Series (R600).
462 case ELF::EF_AMDGPU_MACH_R600_R600:
463 return "r600";
464 case ELF::EF_AMDGPU_MACH_R600_R630:
465 return "r630";
466 case ELF::EF_AMDGPU_MACH_R600_RS880:
467 return "rs880";
468 case ELF::EF_AMDGPU_MACH_R600_RV670:
469 return "rv670";
470
471 // Radeon HD 4000 Series (R700).
472 case ELF::EF_AMDGPU_MACH_R600_RV710:
473 return "rv710";
474 case ELF::EF_AMDGPU_MACH_R600_RV730:
475 return "rv730";
476 case ELF::EF_AMDGPU_MACH_R600_RV770:
477 return "rv770";
478
479 // Radeon HD 5000 Series (Evergreen).
480 case ELF::EF_AMDGPU_MACH_R600_CEDAR:
481 return "cedar";
482 case ELF::EF_AMDGPU_MACH_R600_CYPRESS:
483 return "cypress";
484 case ELF::EF_AMDGPU_MACH_R600_JUNIPER:
485 return "juniper";
486 case ELF::EF_AMDGPU_MACH_R600_REDWOOD:
487 return "redwood";
488 case ELF::EF_AMDGPU_MACH_R600_SUMO:
489 return "sumo";
490
491 // Radeon HD 6000 Series (Northern Islands).
492 case ELF::EF_AMDGPU_MACH_R600_BARTS:
493 return "barts";
494 case ELF::EF_AMDGPU_MACH_R600_CAICOS:
495 return "caicos";
496 case ELF::EF_AMDGPU_MACH_R600_CAYMAN:
497 return "cayman";
498 case ELF::EF_AMDGPU_MACH_R600_TURKS:
499 return "turks";
500
501 // AMDGCN GFX6.
502 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600:
503 return "gfx600";
504 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601:
505 return "gfx601";
506 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602:
507 return "gfx602";
508
509 // AMDGCN GFX7.
510 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700:
511 return "gfx700";
512 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701:
513 return "gfx701";
514 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702:
515 return "gfx702";
516 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703:
517 return "gfx703";
518 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704:
519 return "gfx704";
520 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705:
521 return "gfx705";
522
523 // AMDGCN GFX8.
524 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801:
525 return "gfx801";
526 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802:
527 return "gfx802";
528 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803:
529 return "gfx803";
530 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805:
531 return "gfx805";
532 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810:
533 return "gfx810";
534
535 // AMDGCN GFX9.
536 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900:
537 return "gfx900";
538 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902:
539 return "gfx902";
540 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904:
541 return "gfx904";
542 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906:
543 return "gfx906";
544 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908:
545 return "gfx908";
546 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909:
547 return "gfx909";
548 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A:
549 return "gfx90a";
550 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C:
551 return "gfx90c";
552 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942:
553 return "gfx942";
554 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX950:
555 return "gfx950";
556
557 // AMDGCN GFX10.
558 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010:
559 return "gfx1010";
560 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011:
561 return "gfx1011";
562 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012:
563 return "gfx1012";
564 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013:
565 return "gfx1013";
566 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030:
567 return "gfx1030";
568 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031:
569 return "gfx1031";
570 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032:
571 return "gfx1032";
572 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033:
573 return "gfx1033";
574 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034:
575 return "gfx1034";
576 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035:
577 return "gfx1035";
578 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036:
579 return "gfx1036";
580
581 // AMDGCN GFX11.
582 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100:
583 return "gfx1100";
584 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101:
585 return "gfx1101";
586 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102:
587 return "gfx1102";
588 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103:
589 return "gfx1103";
590 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150:
591 return "gfx1150";
592 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151:
593 return "gfx1151";
594 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152:
595 return "gfx1152";
596 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153:
597 return "gfx1153";
598
599 // AMDGCN GFX12.
600 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200:
601 return "gfx1200";
602 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201:
603 return "gfx1201";
604 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250:
605 return "gfx1250";
606 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1251:
607 return "gfx1251";
608
609 // AMDGCN GFX13.
610 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1310:
611 return "gfx1310";
612
613 // Generic AMDGCN targets
614 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC:
615 return "gfx9-generic";
616 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC:
617 return "gfx9-4-generic";
618 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC:
619 return "gfx10-1-generic";
620 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC:
621 return "gfx10-3-generic";
622 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC:
623 return "gfx11-generic";
624 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC:
625 return "gfx12-generic";
626 default:
627 llvm_unreachable("Unknown EF_AMDGPU_MACH value");
628 }
629}
630
631StringRef ELFObjectFileBase::getNVPTXCPUName() const {
632 assert(getEMachine() == ELF::EM_CUDA);
633 unsigned SM = getEIdentABIVersion() == ELF::ELFABIVERSION_CUDA_V1
634 ? getPlatformFlags() & ELF::EF_CUDA_SM
635 : (getPlatformFlags() & ELF::EF_CUDA_SM_MASK) >>
636 ELF::EF_CUDA_SM_OFFSET;
637
638 switch (SM) {
639 // Fermi architecture.
640 case ELF::EF_CUDA_SM20:
641 return "sm_20";
642 case ELF::EF_CUDA_SM21:
643 return "sm_21";
644
645 // Kepler architecture.
646 case ELF::EF_CUDA_SM30:
647 return "sm_30";
648 case ELF::EF_CUDA_SM32:
649 return "sm_32";
650 case ELF::EF_CUDA_SM35:
651 return "sm_35";
652 case ELF::EF_CUDA_SM37:
653 return "sm_37";
654
655 // Maxwell architecture.
656 case ELF::EF_CUDA_SM50:
657 return "sm_50";
658 case ELF::EF_CUDA_SM52:
659 return "sm_52";
660 case ELF::EF_CUDA_SM53:
661 return "sm_53";
662
663 // Pascal architecture.
664 case ELF::EF_CUDA_SM60:
665 return "sm_60";
666 case ELF::EF_CUDA_SM61:
667 return "sm_61";
668 case ELF::EF_CUDA_SM62:
669 return "sm_62";
670
671 // Volta architecture.
672 case ELF::EF_CUDA_SM70:
673 return "sm_70";
674 case ELF::EF_CUDA_SM72:
675 return "sm_72";
676
677 // Turing architecture.
678 case ELF::EF_CUDA_SM75:
679 return "sm_75";
680
681 // Ampere architecture.
682 case ELF::EF_CUDA_SM80:
683 return "sm_80";
684 case ELF::EF_CUDA_SM86:
685 return "sm_86";
686 case ELF::EF_CUDA_SM87:
687 return "sm_87";
688 case ELF::EF_CUDA_SM88:
689 return "sm_88";
690
691 // Ada architecture.
692 case ELF::EF_CUDA_SM89:
693 return "sm_89";
694
695 // Hopper architecture.
696 case ELF::EF_CUDA_SM90:
697 return getPlatformFlags() & ELF::EF_CUDA_ACCELERATORS_V1 ? "sm_90a"
698 : "sm_90";
699
700 // Blackwell architecture.
701 case ELF::EF_CUDA_SM100:
702 return getPlatformFlags() & ELF::EF_CUDA_ACCELERATORS ? "sm_100a"
703 : "sm_100";
704 case ELF::EF_CUDA_SM101:
705 return getPlatformFlags() & ELF::EF_CUDA_ACCELERATORS ? "sm_101a"
706 : "sm_101";
707 case ELF::EF_CUDA_SM103:
708 return getPlatformFlags() & ELF::EF_CUDA_ACCELERATORS ? "sm_103a"
709 : "sm_103";
710 case ELF::EF_CUDA_SM110:
711 return getPlatformFlags() & ELF::EF_CUDA_ACCELERATORS ? "sm_110a"
712 : "sm_110";
713
714 // Rubin architecture.
715 case ELF::EF_CUDA_SM120:
716 return getPlatformFlags() & ELF::EF_CUDA_ACCELERATORS ? "sm_120a"
717 : "sm_120";
718 case ELF::EF_CUDA_SM121:
719 return getPlatformFlags() & ELF::EF_CUDA_ACCELERATORS ? "sm_121a"
720 : "sm_121";
721 default:
722 llvm_unreachable("Unknown EF_CUDA_SM value");
723 }
724}
725
726// FIXME Encode from a tablegen description or target parser.
727void ELFObjectFileBase::setARMSubArch(Triple &TheTriple) const {
728 if (TheTriple.getSubArch() != Triple::NoSubArch)
729 return;
730
731 ARMAttributeParser Attributes;
732 if (Error E = getBuildAttributes(Attributes)) {
733 // TODO Propagate Error.
734 consumeError(Err: std::move(E));
735 return;
736 }
737
738 std::string Triple;
739 // Default to ARM, but use the triple if it's been set.
740 if (TheTriple.isThumb())
741 Triple = "thumb";
742 else
743 Triple = "arm";
744
745 std::optional<unsigned> Attr =
746 Attributes.getAttributeValue(tag: ARMBuildAttrs::CPU_arch);
747 if (Attr) {
748 switch (*Attr) {
749 case ARMBuildAttrs::v4:
750 Triple += "v4";
751 break;
752 case ARMBuildAttrs::v4T:
753 Triple += "v4t";
754 break;
755 case ARMBuildAttrs::v5T:
756 Triple += "v5t";
757 break;
758 case ARMBuildAttrs::v5TE:
759 Triple += "v5te";
760 break;
761 case ARMBuildAttrs::v5TEJ:
762 Triple += "v5tej";
763 break;
764 case ARMBuildAttrs::v6:
765 Triple += "v6";
766 break;
767 case ARMBuildAttrs::v6KZ:
768 Triple += "v6kz";
769 break;
770 case ARMBuildAttrs::v6T2:
771 Triple += "v6t2";
772 break;
773 case ARMBuildAttrs::v6K:
774 Triple += "v6k";
775 break;
776 case ARMBuildAttrs::v7: {
777 std::optional<unsigned> ArchProfileAttr =
778 Attributes.getAttributeValue(tag: ARMBuildAttrs::CPU_arch_profile);
779 if (ArchProfileAttr == ARMBuildAttrs::MicroControllerProfile)
780 Triple += "v7m";
781 else
782 Triple += "v7";
783 break;
784 }
785 case ARMBuildAttrs::v6_M:
786 Triple += "v6m";
787 break;
788 case ARMBuildAttrs::v6S_M:
789 Triple += "v6sm";
790 break;
791 case ARMBuildAttrs::v7E_M:
792 Triple += "v7em";
793 break;
794 case ARMBuildAttrs::v8_A:
795 Triple += "v8a";
796 break;
797 case ARMBuildAttrs::v8_R:
798 Triple += "v8r";
799 break;
800 case ARMBuildAttrs::v8_M_Base:
801 Triple += "v8m.base";
802 break;
803 case ARMBuildAttrs::v8_M_Main:
804 Triple += "v8m.main";
805 break;
806 case ARMBuildAttrs::v8_1_M_Main:
807 Triple += "v8.1m.main";
808 break;
809 case ARMBuildAttrs::v9_A:
810 Triple += "v9a";
811 break;
812 }
813 }
814 if (!isLittleEndian())
815 Triple += "eb";
816
817 TheTriple.setArchName(Triple);
818}
819
820std::vector<ELFPltEntry>
821ELFObjectFileBase::getPltEntries(const MCSubtargetInfo &STI) const {
822 std::string Err;
823 const auto Triple = makeTriple();
824 const auto *T = TargetRegistry::lookupTarget(TheTriple: Triple, Error&: Err);
825 if (!T)
826 return {};
827 uint32_t JumpSlotReloc = 0, GlobDatReloc = 0;
828 switch (Triple.getArch()) {
829 case Triple::x86:
830 JumpSlotReloc = ELF::R_386_JUMP_SLOT;
831 GlobDatReloc = ELF::R_386_GLOB_DAT;
832 break;
833 case Triple::x86_64:
834 JumpSlotReloc = ELF::R_X86_64_JUMP_SLOT;
835 GlobDatReloc = ELF::R_X86_64_GLOB_DAT;
836 break;
837 case Triple::aarch64:
838 case Triple::aarch64_be:
839 JumpSlotReloc = ELF::R_AARCH64_JUMP_SLOT;
840 break;
841 case Triple::arm:
842 case Triple::armeb:
843 case Triple::thumb:
844 case Triple::thumbeb:
845 JumpSlotReloc = ELF::R_ARM_JUMP_SLOT;
846 break;
847 case Triple::hexagon:
848 JumpSlotReloc = ELF::R_HEX_JMP_SLOT;
849 GlobDatReloc = ELF::R_HEX_GLOB_DAT;
850 break;
851 case Triple::riscv32:
852 case Triple::riscv64:
853 JumpSlotReloc = ELF::R_RISCV_JUMP_SLOT;
854 break;
855 default:
856 return {};
857 }
858 std::unique_ptr<const MCInstrInfo> MII(T->createMCInstrInfo());
859 std::unique_ptr<const MCInstrAnalysis> MIA(
860 T->createMCInstrAnalysis(Info: MII.get()));
861 if (!MIA)
862 return {};
863 std::vector<std::pair<uint64_t, uint64_t>> PltEntries;
864 std::optional<SectionRef> RelaPlt, RelaDyn;
865 uint64_t GotBaseVA = 0;
866 for (const SectionRef &Section : sections()) {
867 Expected<StringRef> NameOrErr = Section.getName();
868 if (!NameOrErr) {
869 consumeError(Err: NameOrErr.takeError());
870 continue;
871 }
872 StringRef Name = *NameOrErr;
873
874 if (Name == ".rela.plt" || Name == ".rel.plt") {
875 RelaPlt = Section;
876 } else if (Name == ".rela.dyn" || Name == ".rel.dyn") {
877 RelaDyn = Section;
878 } else if (Name == ".got.plt") {
879 GotBaseVA = Section.getAddress();
880 } else if (Name == ".plt" || Name == ".plt.got") {
881 Expected<StringRef> PltContents = Section.getContents();
882 if (!PltContents) {
883 consumeError(Err: PltContents.takeError());
884 return {};
885 }
886 llvm::append_range(
887 C&: PltEntries,
888 R: MIA->findPltEntries(PltSectionVA: Section.getAddress(),
889 PltContents: arrayRefFromStringRef(Input: *PltContents), STI));
890 }
891 }
892
893 // Build a map from GOT entry virtual address to PLT entry virtual address.
894 DenseMap<uint64_t, uint64_t> GotToPlt;
895 for (auto [Plt, GotPlt] : PltEntries) {
896 uint64_t GotPltEntry = GotPlt;
897 // An x86-32 PIC PLT uses jmp DWORD PTR [ebx-offset]. Add
898 // _GLOBAL_OFFSET_TABLE_ (EBX) to get the .got.plt (or .got) entry address.
899 // See X86MCTargetDesc.cpp:findPltEntries for the 1 << 32 bit.
900 if (GotPltEntry & (uint64_t(1) << 32) && getEMachine() == ELF::EM_386)
901 GotPltEntry = static_cast<int32_t>(GotPltEntry) + GotBaseVA;
902 GotToPlt.insert(KV: std::make_pair(x&: GotPltEntry, y&: Plt));
903 }
904
905 // Find the relocations in the dynamic relocation table that point to
906 // locations in the GOT for which we know the corresponding PLT entry.
907 std::vector<ELFPltEntry> Result;
908 auto handleRels = [&](iterator_range<relocation_iterator> Rels,
909 uint32_t RelType, StringRef PltSec) {
910 for (const auto &R : Rels) {
911 if (R.getType() != RelType)
912 continue;
913 auto PltEntryIter = GotToPlt.find(Val: R.getOffset());
914 if (PltEntryIter != GotToPlt.end()) {
915 symbol_iterator Sym = R.getSymbol();
916 if (Sym == symbol_end())
917 Result.push_back(
918 x: ELFPltEntry{.Section: PltSec, .Symbol: std::nullopt, .Address: PltEntryIter->second});
919 else
920 Result.push_back(x: ELFPltEntry{.Section: PltSec, .Symbol: Sym->getRawDataRefImpl(),
921 .Address: PltEntryIter->second});
922 }
923 }
924 };
925
926 if (RelaPlt)
927 handleRels(RelaPlt->relocations(), JumpSlotReloc, ".plt");
928
929 // If a symbol needing a PLT entry also needs a GLOB_DAT relocation, GNU ld's
930 // x86 port places the PLT entry in the .plt.got section.
931 if (RelaDyn)
932 handleRels(RelaDyn->relocations(), GlobDatReloc, ".plt.got");
933
934 return Result;
935}
936
937template <class ELFT>
938Expected<std::vector<BBAddrMap>> static readBBAddrMapImpl(
939 const ELFFile<ELFT> &EF, std::optional<unsigned> TextSectionIndex,
940 std::vector<PGOAnalysisMap> *PGOAnalyses) {
941 using Elf_Shdr = typename ELFT::Shdr;
942 bool IsRelocatable = EF.getHeader().e_type == ELF::ET_REL;
943 std::vector<BBAddrMap> BBAddrMaps;
944 if (PGOAnalyses)
945 PGOAnalyses->clear();
946
947 const auto &Sections = cantFail(EF.sections());
948 auto IsMatch = [&](const Elf_Shdr &Sec) -> Expected<bool> {
949 if (Sec.sh_type != ELF::SHT_LLVM_BB_ADDR_MAP)
950 return false;
951 if (!TextSectionIndex)
952 return true;
953 Expected<const Elf_Shdr *> TextSecOrErr = EF.getSection(Sec.sh_link);
954 if (!TextSecOrErr)
955 return createError("unable to get the linked-to section for " +
956 describe(EF, Sec) + ": " +
957 toString(TextSecOrErr.takeError()));
958 assert(*TextSecOrErr >= Sections.begin() &&
959 "Text section pointer outside of bounds");
960 if (*TextSectionIndex !=
961 (unsigned)std::distance(Sections.begin(), *TextSecOrErr))
962 return false;
963 return true;
964 };
965
966 Expected<MapVector<const Elf_Shdr *, const Elf_Shdr *>> SectionRelocMapOrErr =
967 EF.getSectionAndRelocations(IsMatch);
968 if (!SectionRelocMapOrErr)
969 return SectionRelocMapOrErr.takeError();
970
971 for (auto const &[Sec, RelocSec] : *SectionRelocMapOrErr) {
972 if (IsRelocatable && !RelocSec)
973 return createError("unable to get relocation section for " +
974 describe(EF, *Sec));
975 Expected<std::vector<BBAddrMap>> BBAddrMapOrErr =
976 EF.decodeBBAddrMap(*Sec, RelocSec, PGOAnalyses);
977 if (!BBAddrMapOrErr) {
978 if (PGOAnalyses)
979 PGOAnalyses->clear();
980 return createError("unable to read " + describe(EF, *Sec) + ": " +
981 toString(E: BBAddrMapOrErr.takeError()));
982 }
983 std::move(first: BBAddrMapOrErr->begin(), last: BBAddrMapOrErr->end(),
984 result: std::back_inserter(x&: BBAddrMaps));
985 }
986 if (PGOAnalyses)
987 assert(PGOAnalyses->size() == BBAddrMaps.size() &&
988 "The same number of BBAddrMaps and PGOAnalysisMaps should be "
989 "returned when PGO information is requested");
990 return BBAddrMaps;
991}
992
993template <class ELFT>
994static Expected<std::vector<VersionEntry>>
995readDynsymVersionsImpl(const ELFFile<ELFT> &EF,
996 ELFObjectFileBase::elf_symbol_iterator_range Symbols) {
997 using Elf_Shdr = typename ELFT::Shdr;
998 const Elf_Shdr *VerSec = nullptr;
999 const Elf_Shdr *VerNeedSec = nullptr;
1000 const Elf_Shdr *VerDefSec = nullptr;
1001 // The user should ensure sections() can't fail here.
1002 for (const Elf_Shdr &Sec : cantFail(EF.sections())) {
1003 if (Sec.sh_type == ELF::SHT_GNU_versym)
1004 VerSec = &Sec;
1005 else if (Sec.sh_type == ELF::SHT_GNU_verdef)
1006 VerDefSec = &Sec;
1007 else if (Sec.sh_type == ELF::SHT_GNU_verneed)
1008 VerNeedSec = &Sec;
1009 }
1010 if (!VerSec)
1011 return std::vector<VersionEntry>();
1012
1013 Expected<SmallVector<std::optional<VersionEntry>, 0>> MapOrErr =
1014 EF.loadVersionMap(VerNeedSec, VerDefSec);
1015 if (!MapOrErr)
1016 return MapOrErr.takeError();
1017
1018 std::vector<VersionEntry> Ret;
1019 size_t I = 0;
1020 for (const ELFSymbolRef &Sym : Symbols) {
1021 ++I;
1022 Expected<const typename ELFT::Versym *> VerEntryOrErr =
1023 EF.template getEntry<typename ELFT::Versym>(*VerSec, I);
1024 if (!VerEntryOrErr)
1025 return createError("unable to read an entry with index " + Twine(I) +
1026 " from " + describe(EF, *VerSec) + ": " +
1027 toString(VerEntryOrErr.takeError()));
1028
1029 Expected<uint32_t> FlagsOrErr = Sym.getFlags();
1030 if (!FlagsOrErr)
1031 return createError(Err: "unable to read flags for symbol with index " +
1032 Twine(I) + ": " + toString(E: FlagsOrErr.takeError()));
1033
1034 bool IsDefault;
1035 Expected<StringRef> VerOrErr = EF.getSymbolVersionByIndex(
1036 (*VerEntryOrErr)->vs_index, IsDefault, *MapOrErr,
1037 (*FlagsOrErr) & SymbolRef::SF_Undefined);
1038 if (!VerOrErr)
1039 return createError("unable to get a version for entry " + Twine(I) +
1040 " of " + describe(EF, *VerSec) + ": " +
1041 toString(E: VerOrErr.takeError()));
1042
1043 Ret.push_back(x: {.Name: (*VerOrErr).str(), .IsVerDef: IsDefault});
1044 }
1045
1046 return Ret;
1047}
1048
1049Expected<std::vector<VersionEntry>>
1050ELFObjectFileBase::readDynsymVersions() const {
1051 elf_symbol_iterator_range Symbols = getDynamicSymbolIterators();
1052 if (const auto *Obj = dyn_cast<ELF32LEObjectFile>(Val: this))
1053 return readDynsymVersionsImpl(EF: Obj->getELFFile(), Symbols);
1054 if (const auto *Obj = dyn_cast<ELF32BEObjectFile>(Val: this))
1055 return readDynsymVersionsImpl(EF: Obj->getELFFile(), Symbols);
1056 if (const auto *Obj = dyn_cast<ELF64LEObjectFile>(Val: this))
1057 return readDynsymVersionsImpl(EF: Obj->getELFFile(), Symbols);
1058 return readDynsymVersionsImpl(EF: cast<ELF64BEObjectFile>(Val: this)->getELFFile(),
1059 Symbols);
1060}
1061
1062Expected<std::vector<BBAddrMap>> ELFObjectFileBase::readBBAddrMap(
1063 std::optional<unsigned> TextSectionIndex,
1064 std::vector<PGOAnalysisMap> *PGOAnalyses) const {
1065 if (const auto *Obj = dyn_cast<ELF32LEObjectFile>(Val: this))
1066 return readBBAddrMapImpl(EF: Obj->getELFFile(), TextSectionIndex, PGOAnalyses);
1067 if (const auto *Obj = dyn_cast<ELF64LEObjectFile>(Val: this))
1068 return readBBAddrMapImpl(EF: Obj->getELFFile(), TextSectionIndex, PGOAnalyses);
1069 if (const auto *Obj = dyn_cast<ELF32BEObjectFile>(Val: this))
1070 return readBBAddrMapImpl(EF: Obj->getELFFile(), TextSectionIndex, PGOAnalyses);
1071 return readBBAddrMapImpl(EF: cast<ELF64BEObjectFile>(Val: this)->getELFFile(),
1072 TextSectionIndex, PGOAnalyses);
1073}
1074
1075StringRef ELFObjectFileBase::getCrelDecodeProblem(SectionRef Sec) const {
1076 auto Data = Sec.getRawDataRefImpl();
1077 if (const auto *Obj = dyn_cast<ELF32LEObjectFile>(Val: this))
1078 return Obj->getCrelDecodeProblem(Sec: Data);
1079 if (const auto *Obj = dyn_cast<ELF32BEObjectFile>(Val: this))
1080 return Obj->getCrelDecodeProblem(Sec: Data);
1081 if (const auto *Obj = dyn_cast<ELF64LEObjectFile>(Val: this))
1082 return Obj->getCrelDecodeProblem(Sec: Data);
1083 return cast<ELF64BEObjectFile>(Val: this)->getCrelDecodeProblem(Sec: Data);
1084}
1085