1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/CodeGen/MachinePassManager.h"
14#include "llvm/IR/PassManager.h"
15#include "llvm/Pass.h"
16#include "llvm/Support/AMDGPUAddrSpace.h"
17#include "llvm/Support/CodeGen.h"
18
19namespace llvm {
20
21class AMDGPUTargetMachine;
22class GCNTargetMachine;
23class TargetMachine;
24
25// GlobalISel passes
26void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
27FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
28void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
29FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
30FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
31void initializeAMDGPURegBankCombinerPass(PassRegistry &);
32FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
33FunctionPass *createAMDGPURegBankSelectPass();
34FunctionPass *createAMDGPURegBankLegalizePass();
35
36// SI Passes
37FunctionPass *createGCNDPPCombinePass();
38FunctionPass *createSIAnnotateControlFlowLegacyPass();
39FunctionPass *createSIFoldOperandsLegacyPass();
40FunctionPass *createSIPeepholeSDWALegacyPass();
41FunctionPass *createSILowerI1CopiesLegacyPass();
42FunctionPass *createSIShrinkInstructionsLegacyPass();
43FunctionPass *createSILoadStoreOptimizerLegacyPass();
44FunctionPass *createSIWholeQuadModeLegacyPass();
45FunctionPass *createSIFixControlFlowLiveIntervalsPass();
46FunctionPass *createSIOptimizeExecMaskingPreRAPass();
47FunctionPass *createSIOptimizeVGPRLiveRangeLegacyPass();
48FunctionPass *createSIFixSGPRCopiesLegacyPass();
49FunctionPass *createLowerWWMCopiesPass();
50FunctionPass *createSIMemoryLegalizerPass();
51FunctionPass *createSIInsertWaitcntsPass();
52FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
53FunctionPass *createSIFormMemoryClausesLegacyPass();
54
55FunctionPass *createSIPostRABundlerPass();
56FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
57ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
58FunctionPass *createAMDGPUCodeGenPreparePass();
59FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
60FunctionPass *createAMDGPUReserveWWMRegsPass();
61FunctionPass *createAMDGPURewriteOutArgumentsPass();
62ModulePass *
63createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
64ModulePass *createAMDGPULowerBufferFatPointersPass();
65ModulePass *createAMDGPULowerIntrinsicsLegacyPass();
66FunctionPass *createSIModeRegisterPass();
67FunctionPass *createGCNPreRAOptimizationsLegacyPass();
68FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass();
69ModulePass *createAMDGPUPreloadKernelArgumentsLegacyPass(const TargetMachine *);
70
71struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
72 AMDGPUSimplifyLibCallsPass() = default;
73 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
74};
75
76struct AMDGPUImageIntrinsicOptimizerPass
77 : PassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
78 AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM) : TM(TM) {}
79 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
80
81private:
82 TargetMachine &TM;
83};
84
85struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
86 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
87};
88
89class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
90public:
91 SILowerI1CopiesPass() = default;
92 PreservedAnalyses run(MachineFunction &MF,
93 MachineFunctionAnalysisManager &MFAM);
94};
95
96void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
97
98void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
99
100void initializeAMDGPUAsmPrinterPass(PassRegistry &);
101
102// DPP/Iterative option enables the atomic optimizer with given strategy
103// whereas None disables the atomic optimizer.
104enum class ScanOptions { DPP, Iterative, None };
105FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
106void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
107extern char &AMDGPUAtomicOptimizerID;
108
109ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
110void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
111extern char &AMDGPUCtorDtorLoweringLegacyPassID;
112
113FunctionPass *createAMDGPULowerKernelArgumentsPass();
114void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
115extern char &AMDGPULowerKernelArgumentsID;
116
117FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
118void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
119extern char &AMDGPUPromoteKernelArgumentsID;
120
121struct AMDGPUPromoteKernelArgumentsPass
122 : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
123 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
124};
125
126ModulePass *createAMDGPULowerKernelAttributesPass();
127void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
128extern char &AMDGPULowerKernelAttributesID;
129
130struct AMDGPULowerKernelAttributesPass
131 : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
132 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
133};
134
135void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &);
136extern char &AMDGPULowerModuleLDSLegacyPassID;
137
138struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
139 const AMDGPUTargetMachine &TM;
140 AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
141
142 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
143};
144
145void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &);
146extern char &AMDGPULowerBufferFatPointersID;
147
148struct AMDGPULowerBufferFatPointersPass
149 : PassInfoMixin<AMDGPULowerBufferFatPointersPass> {
150 AMDGPULowerBufferFatPointersPass(const TargetMachine &TM) : TM(TM) {}
151 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
152
153private:
154 const TargetMachine &TM;
155};
156
157void initializeAMDGPULowerIntrinsicsLegacyPass(PassRegistry &);
158
159struct AMDGPULowerIntrinsicsPass : PassInfoMixin<AMDGPULowerIntrinsicsPass> {
160 AMDGPULowerIntrinsicsPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
161 PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM);
162
163private:
164 const AMDGPUTargetMachine &TM;
165};
166
167void initializeAMDGPUPrepareAGPRAllocLegacyPass(PassRegistry &);
168extern char &AMDGPUPrepareAGPRAllocLegacyID;
169
170void initializeAMDGPUReserveWWMRegsLegacyPass(PassRegistry &);
171extern char &AMDGPUReserveWWMRegsLegacyID;
172
173void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
174extern char &AMDGPURewriteOutArgumentsID;
175
176void initializeGCNDPPCombineLegacyPass(PassRegistry &);
177extern char &GCNDPPCombineLegacyID;
178
179void initializeSIFoldOperandsLegacyPass(PassRegistry &);
180extern char &SIFoldOperandsLegacyID;
181
182void initializeSIPeepholeSDWALegacyPass(PassRegistry &);
183extern char &SIPeepholeSDWALegacyID;
184
185void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
186extern char &SIShrinkInstructionsLegacyID;
187
188void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
189extern char &SIFixSGPRCopiesLegacyID;
190
191void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
192extern char &SIFixVGPRCopiesID;
193
194void initializeSILowerWWMCopiesLegacyPass(PassRegistry &);
195extern char &SILowerWWMCopiesLegacyID;
196
197void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
198extern char &SILowerI1CopiesLegacyID;
199
200void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
201extern char &AMDGPUGlobalISelDivergenceLoweringID;
202
203void initializeAMDGPURegBankSelectPass(PassRegistry &);
204extern char &AMDGPURegBankSelectID;
205
206void initializeAMDGPURegBankLegalizePass(PassRegistry &);
207extern char &AMDGPURegBankLegalizeID;
208
209void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
210extern char &AMDGPUMarkLastScratchLoadID;
211
212void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
213extern char &SILowerSGPRSpillsLegacyID;
214
215void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
216extern char &SILoadStoreOptimizerLegacyID;
217
218void initializeSIWholeQuadModeLegacyPass(PassRegistry &);
219extern char &SIWholeQuadModeID;
220
221void initializeSILowerControlFlowLegacyPass(PassRegistry &);
222extern char &SILowerControlFlowLegacyID;
223
224void initializeSIPreEmitPeepholeLegacyPass(PassRegistry &);
225extern char &SIPreEmitPeepholeID;
226
227void initializeSILateBranchLoweringLegacyPass(PassRegistry &);
228extern char &SILateBranchLoweringPassID;
229
230void initializeSIOptimizeExecMaskingLegacyPass(PassRegistry &);
231extern char &SIOptimizeExecMaskingLegacyID;
232
233void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
234extern char &SIPreAllocateWWMRegsLegacyID;
235
236void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
237extern char &AMDGPUImageIntrinsicOptimizerID;
238
239void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &);
240extern char &AMDGPUPerfHintAnalysisLegacyID;
241
242void initializeGCNRegPressurePrinterPass(PassRegistry &);
243extern char &GCNRegPressurePrinterID;
244
245void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &);
246extern char &AMDGPUPreloadKernArgPrologLegacyID;
247
248void initializeAMDGPUPreloadKernelArgumentsLegacyPass(PassRegistry &);
249extern char &AMDGPUPreloadKernelArgumentsLegacyID;
250
251// Passes common to R600 and SI
252FunctionPass *createAMDGPUPromoteAlloca();
253void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
254extern char &AMDGPUPromoteAllocaID;
255
256struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
257 AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
258 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
259
260private:
261 TargetMachine &TM;
262};
263
264struct AMDGPUPromoteAllocaToVectorPass
265 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
266 AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
267 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
268
269private:
270 TargetMachine &TM;
271};
272
273struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
274 AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
275 : TM(TM), ScanImpl(ScanImpl) {}
276 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
277
278private:
279 TargetMachine &TM;
280 ScanOptions ScanImpl;
281};
282
283struct AMDGPUInsertDelayAluPass
284 : public PassInfoMixin<AMDGPUInsertDelayAluPass> {
285 PreservedAnalyses run(MachineFunction &F,
286 MachineFunctionAnalysisManager &MFAM);
287};
288
289Pass *createAMDGPUStructurizeCFGPass();
290FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
291ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
292
293struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
294 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
295 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
296
297private:
298 bool GlobalOpt;
299};
300
301void initializeAMDGPULowerExecSyncLegacyPass(PassRegistry &);
302extern char &AMDGPULowerExecSyncLegacyPassID;
303ModulePass *createAMDGPULowerExecSyncLegacyPass();
304
305struct AMDGPULowerExecSyncPass : PassInfoMixin<AMDGPULowerExecSyncPass> {
306 AMDGPULowerExecSyncPass() {}
307 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
308};
309
310void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
311extern char &AMDGPUSwLowerLDSLegacyPassID;
312ModulePass *
313createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
314
315struct AMDGPUSwLowerLDSPass : PassInfoMixin<AMDGPUSwLowerLDSPass> {
316 const AMDGPUTargetMachine &TM;
317 AMDGPUSwLowerLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
318 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
319};
320
321class AMDGPUCodeGenPreparePass
322 : public PassInfoMixin<AMDGPUCodeGenPreparePass> {
323private:
324 TargetMachine &TM;
325
326public:
327 AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
328 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
329};
330
331class AMDGPULateCodeGenPreparePass
332 : public PassInfoMixin<AMDGPULateCodeGenPreparePass> {
333private:
334 const GCNTargetMachine &TM;
335
336public:
337 AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM) : TM(TM) {};
338 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
339};
340
341class AMDGPULowerKernelArgumentsPass
342 : public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
343private:
344 TargetMachine &TM;
345
346public:
347 AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
348 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
349};
350
351struct AMDGPUAttributorOptions {
352 bool IsClosedWorld = false;
353};
354
355class AMDGPUAttributorPass : public PassInfoMixin<AMDGPUAttributorPass> {
356private:
357 TargetMachine &TM;
358
359 AMDGPUAttributorOptions Options;
360
361 const ThinOrFullLTOPhase LTOPhase;
362
363public:
364 AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options,
365 ThinOrFullLTOPhase LTOPhase = ThinOrFullLTOPhase::None)
366 : TM(TM), Options(Options), LTOPhase(LTOPhase) {};
367 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
368};
369
370class AMDGPUPreloadKernelArgumentsPass
371 : public PassInfoMixin<AMDGPUPreloadKernelArgumentsPass> {
372 const TargetMachine &TM;
373
374public:
375 explicit AMDGPUPreloadKernelArgumentsPass(const TargetMachine &TM) : TM(TM) {}
376
377 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
378};
379
380class AMDGPUAnnotateUniformValuesPass
381 : public PassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
382public:
383 AMDGPUAnnotateUniformValuesPass() = default;
384 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
385};
386
387class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
388public:
389 SIModeRegisterPass() = default;
390 PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
391};
392
393class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
394public:
395 PreservedAnalyses run(MachineFunction &MF,
396 MachineFunctionAnalysisManager &MFAM);
397 static bool isRequired() { return true; }
398};
399
400class GCNCreateVOPDPass : public PassInfoMixin<GCNCreateVOPDPass> {
401public:
402 PreservedAnalyses run(MachineFunction &MF,
403 MachineFunctionAnalysisManager &AM);
404};
405
406class AMDGPUMarkLastScratchLoadPass
407 : public PassInfoMixin<AMDGPUMarkLastScratchLoadPass> {
408public:
409 PreservedAnalyses run(MachineFunction &MF,
410 MachineFunctionAnalysisManager &AM);
411};
412
413class SIInsertWaitcntsPass : public PassInfoMixin<SIInsertWaitcntsPass> {
414public:
415 PreservedAnalyses run(MachineFunction &MF,
416 MachineFunctionAnalysisManager &MFAM);
417 static bool isRequired() { return true; }
418};
419
420class SIInsertHardClausesPass : public PassInfoMixin<SIInsertHardClausesPass> {
421public:
422 PreservedAnalyses run(MachineFunction &MF,
423 MachineFunctionAnalysisManager &MFAM);
424};
425
426class SILateBranchLoweringPass
427 : public PassInfoMixin<SILateBranchLoweringPass> {
428public:
429 PreservedAnalyses run(MachineFunction &MF,
430 MachineFunctionAnalysisManager &MFAM);
431 static bool isRequired() { return true; }
432};
433
434class SIPreEmitPeepholePass : public PassInfoMixin<SIPreEmitPeepholePass> {
435public:
436 PreservedAnalyses run(MachineFunction &MF,
437 MachineFunctionAnalysisManager &MFAM);
438 static bool isRequired() { return true; }
439};
440
441class AMDGPUSetWavePriorityPass
442 : public PassInfoMixin<AMDGPUSetWavePriorityPass> {
443public:
444 PreservedAnalyses run(MachineFunction &MF,
445 MachineFunctionAnalysisManager &MFAM);
446};
447
448FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
449
450ModulePass *createAMDGPUPrintfRuntimeBinding();
451void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
452extern char &AMDGPUPrintfRuntimeBindingID;
453
454void initializeAMDGPUResourceUsageAnalysisWrapperPassPass(PassRegistry &);
455extern char &AMDGPUResourceUsageAnalysisID;
456
457struct AMDGPUPrintfRuntimeBindingPass
458 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
459 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
460};
461
462void initializeSIOptimizeExecMaskingPreRALegacyPass(PassRegistry &);
463extern char &SIOptimizeExecMaskingPreRAID;
464
465void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &);
466extern char &SIOptimizeVGPRLiveRangeLegacyID;
467
468void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
469extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
470
471void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
472extern char &AMDGPUCodeGenPrepareID;
473
474void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &);
475extern char &AMDGPURemoveIncompatibleFunctionsID;
476
477void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &);
478extern char &AMDGPULateCodeGenPrepareLegacyID;
479
480FunctionPass *createAMDGPURewriteUndefForPHILegacyPass();
481void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &);
482extern char &AMDGPURewriteUndefForPHILegacyPassID;
483
484class AMDGPURewriteUndefForPHIPass
485 : public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
486public:
487 AMDGPURewriteUndefForPHIPass() = default;
488 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
489};
490
491class SIAnnotateControlFlowPass
492 : public PassInfoMixin<SIAnnotateControlFlowPass> {
493private:
494 const AMDGPUTargetMachine &TM;
495
496public:
497 SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
498 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
499};
500
501void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
502extern char &SIAnnotateControlFlowLegacyPassID;
503
504void initializeSIMemoryLegalizerLegacyPass(PassRegistry &);
505extern char &SIMemoryLegalizerID;
506
507void initializeSIModeRegisterLegacyPass(PassRegistry &);
508extern char &SIModeRegisterID;
509
510void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
511extern char &AMDGPUInsertDelayAluID;
512
513void initializeAMDGPULowerVGPREncodingLegacyPass(PassRegistry &);
514extern char &AMDGPULowerVGPREncodingLegacyID;
515
516void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
517extern char &SIInsertHardClausesID;
518
519void initializeSIInsertWaitcntsLegacyPass(PassRegistry &);
520extern char &SIInsertWaitcntsID;
521
522void initializeSIFormMemoryClausesLegacyPass(PassRegistry &);
523extern char &SIFormMemoryClausesID;
524
525void initializeSIPostRABundlerLegacyPass(PassRegistry &);
526extern char &SIPostRABundlerLegacyID;
527
528void initializeGCNCreateVOPDLegacyPass(PassRegistry &);
529extern char &GCNCreateVOPDID;
530
531void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
532extern char &AMDGPUUnifyDivergentExitNodesID;
533
534ImmutablePass *createAMDGPUAAWrapperPass();
535void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
536ImmutablePass *createAMDGPUExternalAAWrapperPass();
537void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
538
539void initializeAMDGPUArgumentUsageInfoWrapperLegacyPass(PassRegistry &);
540
541ModulePass *createAMDGPUExportKernelRuntimeHandlesLegacyPass();
542void initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(PassRegistry &);
543extern char &AMDGPUExportKernelRuntimeHandlesLegacyID;
544
545void initializeGCNNSAReassignLegacyPass(PassRegistry &);
546extern char &GCNNSAReassignID;
547
548void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &);
549extern char &GCNPreRALongBranchRegID;
550
551void initializeGCNPreRAOptimizationsLegacyPass(PassRegistry &);
552extern char &GCNPreRAOptimizationsID;
553
554FunctionPass *createAMDGPUSetWavePriorityPass();
555void initializeAMDGPUSetWavePriorityLegacyPass(PassRegistry &);
556
557void initializeGCNRewritePartialRegUsesLegacyPass(llvm::PassRegistry &);
558extern char &GCNRewritePartialRegUsesID;
559
560void initializeAMDGPUWaitSGPRHazardsLegacyPass(PassRegistry &);
561extern char &AMDGPUWaitSGPRHazardsLegacyID;
562
563class AMDGPURewriteAGPRCopyMFMAPass
564 : public PassInfoMixin<AMDGPURewriteAGPRCopyMFMAPass> {
565public:
566 AMDGPURewriteAGPRCopyMFMAPass() = default;
567 PreservedAnalyses run(MachineFunction &MF,
568 MachineFunctionAnalysisManager &MFAM);
569};
570
571void initializeAMDGPURewriteAGPRCopyMFMALegacyPass(PassRegistry &);
572extern char &AMDGPURewriteAGPRCopyMFMALegacyID;
573
574void initializeAMDGPUUniformIntrinsicCombineLegacyPass(PassRegistry &);
575extern char &AMDGPUUniformIntrinsicCombineLegacyPassID;
576FunctionPass *createAMDGPUUniformIntrinsicCombineLegacyPass();
577
578struct AMDGPUUniformIntrinsicCombinePass
579 : public PassInfoMixin<AMDGPUUniformIntrinsicCombinePass> {
580 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
581};
582
583namespace AMDGPU {
584enum TargetIndex {
585 TI_CONSTDATA_START,
586 TI_SCRATCH_RSRC_DWORD0,
587 TI_SCRATCH_RSRC_DWORD1,
588 TI_SCRATCH_RSRC_DWORD2,
589 TI_SCRATCH_RSRC_DWORD3
590};
591
592static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
593 if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
594 return true;
595
596 // clang-format off
597 static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
598 /* Flat Global Region Local Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
599 /* Flat */ {true, true, false, true, true, true, true, true, true, true},
600 /* Global */ {true, true, false, false, true, false, true, true, true, true},
601 /* Region */ {false, false, true, false, false, false, false, false, false, false},
602 /* Local */ {true, false, false, true, false, false, false, false, false, false},
603 /* Constant */ {true, true, false, false, false, false, true, true, true, true},
604 /* Private */ {true, false, false, false, false, true, false, false, false, false},
605 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true, true},
606 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true, true},
607 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true, true},
608 /* Buffer Strided Ptr */ {true, true, false, false, true, false, true, true, true, true},
609 };
610 // clang-format on
611 static_assert(std::size(ASAliasRules) == AMDGPUAS::MAX_AMDGPU_ADDRESS + 1);
612
613 return ASAliasRules[AS1][AS2];
614}
615
616}
617
618} // End namespace llvm
619
620#endif
621