1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/Analysis/CGSCCPassManager.h"
14#include "llvm/CodeGen/MachinePassManager.h"
15#include "llvm/IR/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Support/AMDGPUAddrSpace.h"
18#include "llvm/Support/CodeGen.h"
19
20namespace llvm {
21
22class AMDGPUTargetMachine;
23class LazyCallGraph;
24class GCNTargetMachine;
25class TargetMachine;
26
27// GlobalISel passes
28void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
29FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
30void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
31FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
32FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
33void initializeAMDGPURegBankCombinerPass(PassRegistry &);
34FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
35
36class AMDGPUGlobalISelDivergenceLoweringPass
37 : public RequiredPassInfoMixin<AMDGPUGlobalISelDivergenceLoweringPass> {
38public:
39 PreservedAnalyses run(MachineFunction &MF,
40 MachineFunctionAnalysisManager &MFAM);
41};
42FunctionPass *createAMDGPURegBankSelectPass();
43FunctionPass *createAMDGPURegBankLegalizePass();
44
45// SI Passes
46FunctionPass *createGCNDPPCombinePass();
47FunctionPass *createSIAnnotateControlFlowLegacyPass();
48FunctionPass *createSIFoldOperandsLegacyPass();
49FunctionPass *createSIPeepholeSDWALegacyPass();
50FunctionPass *createSILowerI1CopiesLegacyPass();
51FunctionPass *createSIShrinkInstructionsLegacyPass();
52FunctionPass *createSILoadStoreOptimizerLegacyPass();
53FunctionPass *createSIWholeQuadModeLegacyPass();
54FunctionPass *createSIOptimizeExecMaskingPreRAPass();
55FunctionPass *createSIOptimizeVGPRLiveRangeLegacyPass();
56FunctionPass *createAMDGPUNextUseAnalysisLegacyPass();
57FunctionPass *createAMDGPUNextUseAnalysisPrinterLegacyPass();
58FunctionPass *createSIFixSGPRCopiesLegacyPass();
59FunctionPass *createLowerWWMCopiesPass();
60FunctionPass *createSIMemoryLegalizerPass();
61FunctionPass *createSIInsertWaitcntsPass();
62FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
63FunctionPass *createSIFormMemoryClausesLegacyPass();
64
65FunctionPass *createSIPostRABundlerPass();
66FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
67ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
68FunctionPass *createAMDGPUCodeGenPreparePass();
69FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
70FunctionPass *createAMDGPUReserveWWMRegsPass();
71FunctionPass *createAMDGPURewriteOutArgumentsPass();
72ModulePass *
73createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
74ModulePass *createAMDGPULowerBufferFatPointersPass();
75ModulePass *createAMDGPULowerIntrinsicsLegacyPass();
76FunctionPass *createSIModeRegisterPass();
77FunctionPass *createGCNPreRAOptimizationsLegacyPass();
78FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass();
79ModulePass *createAMDGPUPreloadKernelArgumentsLegacyPass(const TargetMachine *);
80
81struct AMDGPUSimplifyLibCallsPass
82 : OptionalPassInfoMixin<AMDGPUSimplifyLibCallsPass> {
83 AMDGPUSimplifyLibCallsPass() = default;
84 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
85};
86
87struct AMDGPUImageIntrinsicOptimizerPass
88 : OptionalPassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
89 AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM) : TM(TM) {}
90 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
91
92private:
93 TargetMachine &TM;
94};
95
96struct AMDGPUUseNativeCallsPass
97 : OptionalPassInfoMixin<AMDGPUUseNativeCallsPass> {
98 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
99};
100
101class SILowerI1CopiesPass : public RequiredPassInfoMixin<SILowerI1CopiesPass> {
102public:
103 SILowerI1CopiesPass() = default;
104 PreservedAnalyses run(MachineFunction &MF,
105 MachineFunctionAnalysisManager &MFAM);
106};
107
108void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
109
110void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
111
112void initializeAMDGPUAsmPrinterPass(PassRegistry &);
113
114// DPP/Iterative option enables the atomic optimizer with given strategy
115// whereas None disables the atomic optimizer.
116enum class ScanOptions { DPP, Iterative, None };
117FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
118void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
119extern char &AMDGPUAtomicOptimizerID;
120
121ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
122void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
123extern char &AMDGPUCtorDtorLoweringLegacyPassID;
124
125FunctionPass *createAMDGPULowerKernelArgumentsPass();
126void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
127extern char &AMDGPULowerKernelArgumentsID;
128
129FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
130void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
131extern char &AMDGPUPromoteKernelArgumentsID;
132
133struct AMDGPUPromoteKernelArgumentsPass
134 : OptionalPassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
135 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
136};
137
138ModulePass *createAMDGPULowerKernelAttributesPass();
139void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
140extern char &AMDGPULowerKernelAttributesID;
141
142struct AMDGPULowerKernelAttributesPass
143 : OptionalPassInfoMixin<AMDGPULowerKernelAttributesPass> {
144 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
145};
146
147void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &);
148extern char &AMDGPULowerModuleLDSLegacyPassID;
149
150struct AMDGPULowerModuleLDSPass
151 : OptionalPassInfoMixin<AMDGPULowerModuleLDSPass> {
152 const AMDGPUTargetMachine &TM;
153 AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
154
155 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
156};
157
158void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &);
159extern char &AMDGPULowerBufferFatPointersID;
160
161struct AMDGPULowerBufferFatPointersPass
162 : OptionalPassInfoMixin<AMDGPULowerBufferFatPointersPass> {
163 AMDGPULowerBufferFatPointersPass(const TargetMachine &TM) : TM(TM) {}
164 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
165
166private:
167 const TargetMachine &TM;
168};
169
170void initializeAMDGPULowerIntrinsicsLegacyPass(PassRegistry &);
171
172struct AMDGPULowerIntrinsicsPass
173 : OptionalPassInfoMixin<AMDGPULowerIntrinsicsPass> {
174 AMDGPULowerIntrinsicsPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
175 PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM);
176
177private:
178 const AMDGPUTargetMachine &TM;
179};
180
181void initializeAMDGPUPrepareAGPRAllocLegacyPass(PassRegistry &);
182extern char &AMDGPUPrepareAGPRAllocLegacyID;
183
184void initializeAMDGPUReserveWWMRegsLegacyPass(PassRegistry &);
185extern char &AMDGPUReserveWWMRegsLegacyID;
186
187void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
188extern char &AMDGPURewriteOutArgumentsID;
189
190void initializeGCNDPPCombineLegacyPass(PassRegistry &);
191extern char &GCNDPPCombineLegacyID;
192
193void initializeSIFoldOperandsLegacyPass(PassRegistry &);
194extern char &SIFoldOperandsLegacyID;
195
196void initializeSIPeepholeSDWALegacyPass(PassRegistry &);
197extern char &SIPeepholeSDWALegacyID;
198
199void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
200extern char &SIShrinkInstructionsLegacyID;
201
202void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
203extern char &SIFixSGPRCopiesLegacyID;
204
205void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
206extern char &SIFixVGPRCopiesID;
207
208void initializeAMDGPUNextUseAnalysisLegacyPassPass(PassRegistry &);
209extern char &AMDGPUNextUseAnalysisLegacyID;
210
211void initializeAMDGPUNextUseAnalysisPrinterLegacyPassPass(PassRegistry &);
212extern char &AMDGPUNextUseAnalysisPrinterLegacyID;
213
214void initializeSILowerWWMCopiesLegacyPass(PassRegistry &);
215extern char &SILowerWWMCopiesLegacyID;
216
217void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
218extern char &SILowerI1CopiesLegacyID;
219
220void initializeAMDGPUGlobalISelDivergenceLoweringLegacyPass(PassRegistry &);
221extern char &AMDGPUGlobalISelDivergenceLoweringLegacyID;
222
223void initializeAMDGPURegBankSelectPass(PassRegistry &);
224extern char &AMDGPURegBankSelectID;
225
226void initializeAMDGPURegBankLegalizePass(PassRegistry &);
227extern char &AMDGPURegBankLegalizeID;
228
229void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
230extern char &AMDGPUMarkLastScratchLoadID;
231
232void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
233extern char &SILowerSGPRSpillsLegacyID;
234
235void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
236extern char &SILoadStoreOptimizerLegacyID;
237
238void initializeSIWholeQuadModeLegacyPass(PassRegistry &);
239extern char &SIWholeQuadModeID;
240
241void initializeSILowerControlFlowLegacyPass(PassRegistry &);
242extern char &SILowerControlFlowLegacyID;
243
244void initializeSIPreEmitPeepholeLegacyPass(PassRegistry &);
245extern char &SIPreEmitPeepholeID;
246
247void initializeSILateBranchLoweringLegacyPass(PassRegistry &);
248extern char &SILateBranchLoweringPassID;
249
250void initializeSIOptimizeExecMaskingLegacyPass(PassRegistry &);
251extern char &SIOptimizeExecMaskingLegacyID;
252
253void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
254extern char &SIPreAllocateWWMRegsLegacyID;
255
256void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
257extern char &AMDGPUImageIntrinsicOptimizerID;
258
259void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &);
260extern char &AMDGPUPerfHintAnalysisLegacyID;
261
262void initializeGCNRegPressurePrinterPass(PassRegistry &);
263extern char &GCNRegPressurePrinterID;
264
265void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &);
266extern char &AMDGPUPreloadKernArgPrologLegacyID;
267
268void initializeAMDGPUPreloadKernelArgumentsLegacyPass(PassRegistry &);
269extern char &AMDGPUPreloadKernelArgumentsLegacyID;
270
271// Passes common to R600 and SI
272FunctionPass *createAMDGPUPromoteAlloca();
273void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
274extern char &AMDGPUPromoteAllocaID;
275
276struct AMDGPUPromoteAllocaPass
277 : OptionalPassInfoMixin<AMDGPUPromoteAllocaPass> {
278 AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
279 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
280
281private:
282 TargetMachine &TM;
283};
284
285struct AMDGPUPromoteAllocaToVectorPass
286 : OptionalPassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
287 AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
288 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
289
290private:
291 TargetMachine &TM;
292};
293
294struct AMDGPUAtomicOptimizerPass
295 : OptionalPassInfoMixin<AMDGPUAtomicOptimizerPass> {
296 AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
297 : TM(TM), ScanImpl(ScanImpl) {}
298 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
299
300private:
301 TargetMachine &TM;
302 ScanOptions ScanImpl;
303};
304
305struct AMDGPUInsertDelayAluPass
306 : public OptionalPassInfoMixin<AMDGPUInsertDelayAluPass> {
307 PreservedAnalyses run(MachineFunction &F,
308 MachineFunctionAnalysisManager &MFAM);
309};
310
311Pass *createAMDGPUStructurizeCFGPass();
312FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
313ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
314
315struct AMDGPUAlwaysInlinePass : OptionalPassInfoMixin<AMDGPUAlwaysInlinePass> {
316 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
317 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
318
319private:
320 bool GlobalOpt;
321};
322
323void initializeAMDGPULowerExecSyncLegacyPass(PassRegistry &);
324extern char &AMDGPULowerExecSyncLegacyPassID;
325ModulePass *createAMDGPULowerExecSyncLegacyPass();
326
327struct AMDGPULowerExecSyncPass
328 : OptionalPassInfoMixin<AMDGPULowerExecSyncPass> {
329 AMDGPULowerExecSyncPass() {}
330 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
331};
332
333void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
334extern char &AMDGPUSwLowerLDSLegacyPassID;
335ModulePass *createAMDGPUSwLowerLDSLegacyPass();
336
337struct AMDGPUSwLowerLDSPass : OptionalPassInfoMixin<AMDGPUSwLowerLDSPass> {
338 AMDGPUSwLowerLDSPass() = default;
339 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
340};
341
342class AMDGPUCodeGenPreparePass
343 : public OptionalPassInfoMixin<AMDGPUCodeGenPreparePass> {
344private:
345 TargetMachine &TM;
346
347public:
348 AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
349 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
350};
351
352class AMDGPULateCodeGenPreparePass
353 : public OptionalPassInfoMixin<AMDGPULateCodeGenPreparePass> {
354private:
355 const GCNTargetMachine &TM;
356
357public:
358 AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM) : TM(TM) {};
359 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
360};
361
362class AMDGPULowerKernelArgumentsPass
363 : public RequiredPassInfoMixin<AMDGPULowerKernelArgumentsPass> {
364private:
365 TargetMachine &TM;
366
367public:
368 AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
369 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
370};
371
372struct AMDGPUAttributorOptions {
373 bool IsClosedWorld = false;
374};
375
376class AMDGPUAttributorPass
377 : public OptionalPassInfoMixin<AMDGPUAttributorPass> {
378private:
379 TargetMachine &TM;
380
381 AMDGPUAttributorOptions Options;
382
383 const ThinOrFullLTOPhase LTOPhase;
384
385public:
386 AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options,
387 ThinOrFullLTOPhase LTOPhase = ThinOrFullLTOPhase::None)
388 : TM(TM), Options(Options), LTOPhase(LTOPhase) {};
389 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
390};
391
392class AMDGPUAttributorCGSCCPass
393 : public OptionalPassInfoMixin<AMDGPUAttributorCGSCCPass> {
394private:
395 GCNTargetMachine &TM;
396
397public:
398 AMDGPUAttributorCGSCCPass(GCNTargetMachine &TM) : TM(TM) {}
399 PreservedAnalyses run(LazyCallGraph::SCC &C, CGSCCAnalysisManager &AM,
400 LazyCallGraph &CG, CGSCCUpdateResult &UR);
401};
402
403class AMDGPUPreloadKernelArgumentsPass
404 : public OptionalPassInfoMixin<AMDGPUPreloadKernelArgumentsPass> {
405 const TargetMachine &TM;
406
407public:
408 explicit AMDGPUPreloadKernelArgumentsPass(const TargetMachine &TM) : TM(TM) {}
409
410 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
411};
412
413class AMDGPUAnnotateUniformValuesPass
414 : public OptionalPassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
415public:
416 AMDGPUAnnotateUniformValuesPass() = default;
417 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
418};
419
420class SIModeRegisterPass : public RequiredPassInfoMixin<SIModeRegisterPass> {
421public:
422 SIModeRegisterPass() = default;
423 PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
424};
425
426class SIMemoryLegalizerPass
427 : public RequiredPassInfoMixin<SIMemoryLegalizerPass> {
428public:
429 PreservedAnalyses run(MachineFunction &MF,
430 MachineFunctionAnalysisManager &MFAM);
431};
432
433class GCNCreateVOPDPass : public OptionalPassInfoMixin<GCNCreateVOPDPass> {
434public:
435 PreservedAnalyses run(MachineFunction &MF,
436 MachineFunctionAnalysisManager &AM);
437};
438
439class AMDGPUMarkLastScratchLoadPass
440 : public OptionalPassInfoMixin<AMDGPUMarkLastScratchLoadPass> {
441public:
442 PreservedAnalyses run(MachineFunction &MF,
443 MachineFunctionAnalysisManager &AM);
444};
445
446class SIInsertWaitcntsPass
447 : public RequiredPassInfoMixin<SIInsertWaitcntsPass> {
448public:
449 PreservedAnalyses run(MachineFunction &MF,
450 MachineFunctionAnalysisManager &MFAM);
451};
452
453class SIInsertHardClausesPass
454 : public OptionalPassInfoMixin<SIInsertHardClausesPass> {
455public:
456 PreservedAnalyses run(MachineFunction &MF,
457 MachineFunctionAnalysisManager &MFAM);
458};
459
460class SILateBranchLoweringPass
461 : public RequiredPassInfoMixin<SILateBranchLoweringPass> {
462public:
463 PreservedAnalyses run(MachineFunction &MF,
464 MachineFunctionAnalysisManager &MFAM);
465};
466
467class SIPreEmitPeepholePass
468 : public RequiredPassInfoMixin<SIPreEmitPeepholePass> {
469public:
470 PreservedAnalyses run(MachineFunction &MF,
471 MachineFunctionAnalysisManager &MFAM);
472};
473
474class AMDGPUSetWavePriorityPass
475 : public OptionalPassInfoMixin<AMDGPUSetWavePriorityPass> {
476public:
477 PreservedAnalyses run(MachineFunction &MF,
478 MachineFunctionAnalysisManager &MFAM);
479};
480
481FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
482
483ModulePass *createAMDGPUPrintfRuntimeBinding();
484void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
485extern char &AMDGPUPrintfRuntimeBindingID;
486
487void initializeAMDGPUResourceUsageAnalysisWrapperPassPass(PassRegistry &);
488extern char &AMDGPUResourceUsageAnalysisID;
489
490struct AMDGPUPrintfRuntimeBindingPass
491 : OptionalPassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
492 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
493};
494
495void initializeSIOptimizeExecMaskingPreRALegacyPass(PassRegistry &);
496extern char &SIOptimizeExecMaskingPreRAID;
497
498void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &);
499extern char &SIOptimizeVGPRLiveRangeLegacyID;
500
501void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
502extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
503
504void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
505extern char &AMDGPUCodeGenPrepareID;
506
507void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &);
508extern char &AMDGPURemoveIncompatibleFunctionsID;
509
510void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &);
511extern char &AMDGPULateCodeGenPrepareLegacyID;
512
513FunctionPass *createAMDGPURewriteUndefForPHILegacyPass();
514void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &);
515extern char &AMDGPURewriteUndefForPHILegacyPassID;
516
517class AMDGPURewriteUndefForPHIPass
518 : public OptionalPassInfoMixin<AMDGPURewriteUndefForPHIPass> {
519public:
520 AMDGPURewriteUndefForPHIPass() = default;
521 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
522};
523
524class SIAnnotateControlFlowPass
525 : public RequiredPassInfoMixin<SIAnnotateControlFlowPass> {
526private:
527 const AMDGPUTargetMachine &TM;
528
529public:
530 SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
531 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
532};
533
534void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
535extern char &SIAnnotateControlFlowLegacyPassID;
536
537void initializeSIMemoryLegalizerLegacyPass(PassRegistry &);
538extern char &SIMemoryLegalizerID;
539
540void initializeSIModeRegisterLegacyPass(PassRegistry &);
541extern char &SIModeRegisterID;
542
543void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
544extern char &AMDGPUInsertDelayAluID;
545
546void initializeAMDGPULowerVGPREncodingLegacyPass(PassRegistry &);
547extern char &AMDGPULowerVGPREncodingLegacyID;
548
549void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
550extern char &SIInsertHardClausesID;
551
552void initializeSIInsertWaitcntsLegacyPass(PassRegistry &);
553extern char &SIInsertWaitcntsID;
554
555void initializeSIFormMemoryClausesLegacyPass(PassRegistry &);
556extern char &SIFormMemoryClausesID;
557
558void initializeSIPostRABundlerLegacyPass(PassRegistry &);
559extern char &SIPostRABundlerLegacyID;
560
561void initializeGCNCreateVOPDLegacyPass(PassRegistry &);
562extern char &GCNCreateVOPDID;
563
564void initializeAMDGPUUnifyDivergentExitNodesLegacyPass(PassRegistry &);
565extern char &AMDGPUUnifyDivergentExitNodesID;
566
567ImmutablePass *createAMDGPUAAWrapperPass();
568void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
569ImmutablePass *createAMDGPUExternalAAWrapperPass();
570void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
571
572ModulePass *createAMDGPUExportKernelRuntimeHandlesLegacyPass();
573void initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(PassRegistry &);
574extern char &AMDGPUExportKernelRuntimeHandlesLegacyID;
575
576void initializeGCNNSAReassignLegacyPass(PassRegistry &);
577extern char &GCNNSAReassignID;
578
579void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &);
580extern char &GCNPreRALongBranchRegID;
581
582void initializeGCNPreRAOptimizationsLegacyPass(PassRegistry &);
583extern char &GCNPreRAOptimizationsID;
584
585FunctionPass *createAMDGPUSetWavePriorityPass();
586void initializeAMDGPUSetWavePriorityLegacyPass(PassRegistry &);
587
588void initializeGCNRewritePartialRegUsesLegacyPass(llvm::PassRegistry &);
589extern char &GCNRewritePartialRegUsesID;
590
591void initializeAMDGPUWaitSGPRHazardsLegacyPass(PassRegistry &);
592extern char &AMDGPUWaitSGPRHazardsLegacyID;
593
594class AMDGPURewriteAGPRCopyMFMAPass
595 : public OptionalPassInfoMixin<AMDGPURewriteAGPRCopyMFMAPass> {
596public:
597 AMDGPURewriteAGPRCopyMFMAPass() = default;
598 PreservedAnalyses run(MachineFunction &MF,
599 MachineFunctionAnalysisManager &MFAM);
600};
601
602void initializeAMDGPURewriteAGPRCopyMFMALegacyPass(PassRegistry &);
603extern char &AMDGPURewriteAGPRCopyMFMALegacyID;
604
605void initializeAMDGPUUniformIntrinsicCombineLegacyPass(PassRegistry &);
606extern char &AMDGPUUniformIntrinsicCombineLegacyPassID;
607FunctionPass *createAMDGPUUniformIntrinsicCombineLegacyPass();
608
609struct AMDGPUUniformIntrinsicCombinePass
610 : public OptionalPassInfoMixin<AMDGPUUniformIntrinsicCombinePass> {
611 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
612};
613
614namespace AMDGPU {
615enum TargetIndex {
616 TI_CONSTDATA_START,
617 TI_SCRATCH_RSRC_DWORD0,
618 TI_SCRATCH_RSRC_DWORD1,
619 TI_SCRATCH_RSRC_DWORD2,
620 TI_SCRATCH_RSRC_DWORD3
621};
622
623static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
624 if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
625 return true;
626
627 // clang-format off
628 static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
629 /* Flat Global Region Local Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
630 /* Flat */ {true, true, false, true, true, true, true, true, true, true},
631 /* Global */ {true, true, false, false, true, false, true, true, true, true},
632 /* Region */ {false, false, true, false, false, false, false, false, false, false},
633 /* Local */ {true, false, false, true, false, false, false, false, false, false},
634 /* Constant */ {true, true, false, false, false, false, true, true, true, true},
635 /* Private */ {true, false, false, false, false, true, false, false, false, false},
636 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true, true},
637 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true, true},
638 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true, true},
639 /* Buffer Strided Ptr */ {true, true, false, false, true, false, true, true, true, true},
640 };
641 // clang-format on
642 static_assert(std::size(ASAliasRules) == AMDGPUAS::MAX_AMDGPU_ADDRESS + 1);
643
644 return ASAliasRules[AS1][AS2];
645}
646
647}
648
649} // End namespace llvm
650
651#endif
652