1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/Analysis/CGSCCPassManager.h"
14#include "llvm/CodeGen/MachinePassManager.h"
15#include "llvm/IR/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Support/AMDGPUAddrSpace.h"
18#include "llvm/Support/CodeGen.h"
19
20namespace llvm {
21
22class AMDGPUTargetMachine;
23class LazyCallGraph;
24class GCNTargetMachine;
25class TargetMachine;
26
27// GlobalISel passes
28void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
29FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
30void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
31FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
32FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
33void initializeAMDGPURegBankCombinerPass(PassRegistry &);
34FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
35FunctionPass *createAMDGPURegBankSelectPass();
36FunctionPass *createAMDGPURegBankLegalizePass();
37
38// SI Passes
39FunctionPass *createGCNDPPCombinePass();
40FunctionPass *createSIAnnotateControlFlowLegacyPass();
41FunctionPass *createSIFoldOperandsLegacyPass();
42FunctionPass *createSIPeepholeSDWALegacyPass();
43FunctionPass *createSILowerI1CopiesLegacyPass();
44FunctionPass *createSIShrinkInstructionsLegacyPass();
45FunctionPass *createSILoadStoreOptimizerLegacyPass();
46FunctionPass *createSIWholeQuadModeLegacyPass();
47FunctionPass *createSIFixControlFlowLiveIntervalsPass();
48FunctionPass *createSIOptimizeExecMaskingPreRAPass();
49FunctionPass *createSIOptimizeVGPRLiveRangeLegacyPass();
50FunctionPass *createAMDGPUNextUseAnalysisLegacyPass();
51FunctionPass *createAMDGPUNextUseAnalysisPrinterLegacyPass();
52FunctionPass *createSIFixSGPRCopiesLegacyPass();
53FunctionPass *createLowerWWMCopiesPass();
54FunctionPass *createSIMemoryLegalizerPass();
55FunctionPass *createSIInsertWaitcntsPass();
56FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
57FunctionPass *createSIFormMemoryClausesLegacyPass();
58
59FunctionPass *createSIPostRABundlerPass();
60FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
61ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
62FunctionPass *createAMDGPUCodeGenPreparePass();
63FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
64FunctionPass *createAMDGPUReserveWWMRegsPass();
65FunctionPass *createAMDGPURewriteOutArgumentsPass();
66ModulePass *
67createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
68ModulePass *createAMDGPULowerBufferFatPointersPass();
69ModulePass *createAMDGPULowerIntrinsicsLegacyPass();
70FunctionPass *createSIModeRegisterPass();
71FunctionPass *createGCNPreRAOptimizationsLegacyPass();
72FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass();
73ModulePass *createAMDGPUPreloadKernelArgumentsLegacyPass(const TargetMachine *);
74
75struct AMDGPUSimplifyLibCallsPass
76 : OptionalPassInfoMixin<AMDGPUSimplifyLibCallsPass> {
77 AMDGPUSimplifyLibCallsPass() = default;
78 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
79};
80
81struct AMDGPUImageIntrinsicOptimizerPass
82 : OptionalPassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
83 AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM) : TM(TM) {}
84 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
85
86private:
87 TargetMachine &TM;
88};
89
90struct AMDGPUUseNativeCallsPass
91 : OptionalPassInfoMixin<AMDGPUUseNativeCallsPass> {
92 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
93};
94
95class SILowerI1CopiesPass : public OptionalPassInfoMixin<SILowerI1CopiesPass> {
96public:
97 SILowerI1CopiesPass() = default;
98 PreservedAnalyses run(MachineFunction &MF,
99 MachineFunctionAnalysisManager &MFAM);
100};
101
102void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
103
104void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
105
106void initializeAMDGPUAsmPrinterPass(PassRegistry &);
107
108// DPP/Iterative option enables the atomic optimizer with given strategy
109// whereas None disables the atomic optimizer.
110enum class ScanOptions { DPP, Iterative, None };
111FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
112void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
113extern char &AMDGPUAtomicOptimizerID;
114
115ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
116void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
117extern char &AMDGPUCtorDtorLoweringLegacyPassID;
118
119FunctionPass *createAMDGPULowerKernelArgumentsPass();
120void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
121extern char &AMDGPULowerKernelArgumentsID;
122
123FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
124void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
125extern char &AMDGPUPromoteKernelArgumentsID;
126
127struct AMDGPUPromoteKernelArgumentsPass
128 : OptionalPassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
129 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
130};
131
132ModulePass *createAMDGPULowerKernelAttributesPass();
133void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
134extern char &AMDGPULowerKernelAttributesID;
135
136struct AMDGPULowerKernelAttributesPass
137 : OptionalPassInfoMixin<AMDGPULowerKernelAttributesPass> {
138 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
139};
140
141void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &);
142extern char &AMDGPULowerModuleLDSLegacyPassID;
143
144struct AMDGPULowerModuleLDSPass
145 : OptionalPassInfoMixin<AMDGPULowerModuleLDSPass> {
146 const AMDGPUTargetMachine &TM;
147 AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
148
149 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
150};
151
152void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &);
153extern char &AMDGPULowerBufferFatPointersID;
154
155struct AMDGPULowerBufferFatPointersPass
156 : OptionalPassInfoMixin<AMDGPULowerBufferFatPointersPass> {
157 AMDGPULowerBufferFatPointersPass(const TargetMachine &TM) : TM(TM) {}
158 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
159
160private:
161 const TargetMachine &TM;
162};
163
164void initializeAMDGPULowerIntrinsicsLegacyPass(PassRegistry &);
165
166struct AMDGPULowerIntrinsicsPass
167 : OptionalPassInfoMixin<AMDGPULowerIntrinsicsPass> {
168 AMDGPULowerIntrinsicsPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
169 PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM);
170
171private:
172 const AMDGPUTargetMachine &TM;
173};
174
175void initializeAMDGPUPrepareAGPRAllocLegacyPass(PassRegistry &);
176extern char &AMDGPUPrepareAGPRAllocLegacyID;
177
178void initializeAMDGPUReserveWWMRegsLegacyPass(PassRegistry &);
179extern char &AMDGPUReserveWWMRegsLegacyID;
180
181void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
182extern char &AMDGPURewriteOutArgumentsID;
183
184void initializeGCNDPPCombineLegacyPass(PassRegistry &);
185extern char &GCNDPPCombineLegacyID;
186
187void initializeSIFoldOperandsLegacyPass(PassRegistry &);
188extern char &SIFoldOperandsLegacyID;
189
190void initializeSIPeepholeSDWALegacyPass(PassRegistry &);
191extern char &SIPeepholeSDWALegacyID;
192
193void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
194extern char &SIShrinkInstructionsLegacyID;
195
196void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
197extern char &SIFixSGPRCopiesLegacyID;
198
199void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
200extern char &SIFixVGPRCopiesID;
201
202void initializeAMDGPUNextUseAnalysisLegacyPassPass(PassRegistry &);
203extern char &AMDGPUNextUseAnalysisLegacyID;
204
205void initializeAMDGPUNextUseAnalysisPrinterLegacyPassPass(PassRegistry &);
206extern char &AMDGPUNextUseAnalysisPrinterLegacyID;
207
208void initializeSILowerWWMCopiesLegacyPass(PassRegistry &);
209extern char &SILowerWWMCopiesLegacyID;
210
211void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
212extern char &SILowerI1CopiesLegacyID;
213
214void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
215extern char &AMDGPUGlobalISelDivergenceLoweringID;
216
217void initializeAMDGPURegBankSelectPass(PassRegistry &);
218extern char &AMDGPURegBankSelectID;
219
220void initializeAMDGPURegBankLegalizePass(PassRegistry &);
221extern char &AMDGPURegBankLegalizeID;
222
223void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
224extern char &AMDGPUMarkLastScratchLoadID;
225
226void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
227extern char &SILowerSGPRSpillsLegacyID;
228
229void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
230extern char &SILoadStoreOptimizerLegacyID;
231
232void initializeSIWholeQuadModeLegacyPass(PassRegistry &);
233extern char &SIWholeQuadModeID;
234
235void initializeSILowerControlFlowLegacyPass(PassRegistry &);
236extern char &SILowerControlFlowLegacyID;
237
238void initializeSIPreEmitPeepholeLegacyPass(PassRegistry &);
239extern char &SIPreEmitPeepholeID;
240
241void initializeSILateBranchLoweringLegacyPass(PassRegistry &);
242extern char &SILateBranchLoweringPassID;
243
244void initializeSIOptimizeExecMaskingLegacyPass(PassRegistry &);
245extern char &SIOptimizeExecMaskingLegacyID;
246
247void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
248extern char &SIPreAllocateWWMRegsLegacyID;
249
250void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
251extern char &AMDGPUImageIntrinsicOptimizerID;
252
253void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &);
254extern char &AMDGPUPerfHintAnalysisLegacyID;
255
256void initializeGCNRegPressurePrinterPass(PassRegistry &);
257extern char &GCNRegPressurePrinterID;
258
259void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &);
260extern char &AMDGPUPreloadKernArgPrologLegacyID;
261
262void initializeAMDGPUPreloadKernelArgumentsLegacyPass(PassRegistry &);
263extern char &AMDGPUPreloadKernelArgumentsLegacyID;
264
265// Passes common to R600 and SI
266FunctionPass *createAMDGPUPromoteAlloca();
267void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
268extern char &AMDGPUPromoteAllocaID;
269
270struct AMDGPUPromoteAllocaPass
271 : OptionalPassInfoMixin<AMDGPUPromoteAllocaPass> {
272 AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
273 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
274
275private:
276 TargetMachine &TM;
277};
278
279struct AMDGPUPromoteAllocaToVectorPass
280 : OptionalPassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
281 AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
282 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
283
284private:
285 TargetMachine &TM;
286};
287
288struct AMDGPUAtomicOptimizerPass
289 : OptionalPassInfoMixin<AMDGPUAtomicOptimizerPass> {
290 AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
291 : TM(TM), ScanImpl(ScanImpl) {}
292 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
293
294private:
295 TargetMachine &TM;
296 ScanOptions ScanImpl;
297};
298
299struct AMDGPUInsertDelayAluPass
300 : public OptionalPassInfoMixin<AMDGPUInsertDelayAluPass> {
301 PreservedAnalyses run(MachineFunction &F,
302 MachineFunctionAnalysisManager &MFAM);
303};
304
305Pass *createAMDGPUStructurizeCFGPass();
306FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
307ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
308
309struct AMDGPUAlwaysInlinePass : OptionalPassInfoMixin<AMDGPUAlwaysInlinePass> {
310 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
311 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
312
313private:
314 bool GlobalOpt;
315};
316
317void initializeAMDGPULowerExecSyncLegacyPass(PassRegistry &);
318extern char &AMDGPULowerExecSyncLegacyPassID;
319ModulePass *createAMDGPULowerExecSyncLegacyPass();
320
321struct AMDGPULowerExecSyncPass
322 : OptionalPassInfoMixin<AMDGPULowerExecSyncPass> {
323 AMDGPULowerExecSyncPass() {}
324 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
325};
326
327void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
328extern char &AMDGPUSwLowerLDSLegacyPassID;
329ModulePass *createAMDGPUSwLowerLDSLegacyPass();
330
331struct AMDGPUSwLowerLDSPass : OptionalPassInfoMixin<AMDGPUSwLowerLDSPass> {
332 AMDGPUSwLowerLDSPass() = default;
333 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
334};
335
336class AMDGPUCodeGenPreparePass
337 : public OptionalPassInfoMixin<AMDGPUCodeGenPreparePass> {
338private:
339 TargetMachine &TM;
340
341public:
342 AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
343 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
344};
345
346class AMDGPULateCodeGenPreparePass
347 : public OptionalPassInfoMixin<AMDGPULateCodeGenPreparePass> {
348private:
349 const GCNTargetMachine &TM;
350
351public:
352 AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM) : TM(TM) {};
353 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
354};
355
356class AMDGPULowerKernelArgumentsPass
357 : public OptionalPassInfoMixin<AMDGPULowerKernelArgumentsPass> {
358private:
359 TargetMachine &TM;
360
361public:
362 AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
363 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
364};
365
366struct AMDGPUAttributorOptions {
367 bool IsClosedWorld = false;
368};
369
370class AMDGPUAttributorPass
371 : public OptionalPassInfoMixin<AMDGPUAttributorPass> {
372private:
373 TargetMachine &TM;
374
375 AMDGPUAttributorOptions Options;
376
377 const ThinOrFullLTOPhase LTOPhase;
378
379public:
380 AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options,
381 ThinOrFullLTOPhase LTOPhase = ThinOrFullLTOPhase::None)
382 : TM(TM), Options(Options), LTOPhase(LTOPhase) {};
383 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
384};
385
386class AMDGPUAttributorCGSCCPass
387 : public OptionalPassInfoMixin<AMDGPUAttributorCGSCCPass> {
388private:
389 GCNTargetMachine &TM;
390
391public:
392 AMDGPUAttributorCGSCCPass(GCNTargetMachine &TM) : TM(TM) {}
393 PreservedAnalyses run(LazyCallGraph::SCC &C, CGSCCAnalysisManager &AM,
394 LazyCallGraph &CG, CGSCCUpdateResult &UR);
395};
396
397class AMDGPUPreloadKernelArgumentsPass
398 : public OptionalPassInfoMixin<AMDGPUPreloadKernelArgumentsPass> {
399 const TargetMachine &TM;
400
401public:
402 explicit AMDGPUPreloadKernelArgumentsPass(const TargetMachine &TM) : TM(TM) {}
403
404 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
405};
406
407class AMDGPUAnnotateUniformValuesPass
408 : public OptionalPassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
409public:
410 AMDGPUAnnotateUniformValuesPass() = default;
411 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
412};
413
414class SIModeRegisterPass : public OptionalPassInfoMixin<SIModeRegisterPass> {
415public:
416 SIModeRegisterPass() = default;
417 PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
418};
419
420class SIMemoryLegalizerPass
421 : public RequiredPassInfoMixin<SIMemoryLegalizerPass> {
422public:
423 PreservedAnalyses run(MachineFunction &MF,
424 MachineFunctionAnalysisManager &MFAM);
425};
426
427class GCNCreateVOPDPass : public OptionalPassInfoMixin<GCNCreateVOPDPass> {
428public:
429 PreservedAnalyses run(MachineFunction &MF,
430 MachineFunctionAnalysisManager &AM);
431};
432
433class AMDGPUMarkLastScratchLoadPass
434 : public OptionalPassInfoMixin<AMDGPUMarkLastScratchLoadPass> {
435public:
436 PreservedAnalyses run(MachineFunction &MF,
437 MachineFunctionAnalysisManager &AM);
438};
439
440class SIInsertWaitcntsPass
441 : public RequiredPassInfoMixin<SIInsertWaitcntsPass> {
442public:
443 PreservedAnalyses run(MachineFunction &MF,
444 MachineFunctionAnalysisManager &MFAM);
445};
446
447class SIInsertHardClausesPass
448 : public OptionalPassInfoMixin<SIInsertHardClausesPass> {
449public:
450 PreservedAnalyses run(MachineFunction &MF,
451 MachineFunctionAnalysisManager &MFAM);
452};
453
454class SILateBranchLoweringPass
455 : public RequiredPassInfoMixin<SILateBranchLoweringPass> {
456public:
457 PreservedAnalyses run(MachineFunction &MF,
458 MachineFunctionAnalysisManager &MFAM);
459};
460
461class SIPreEmitPeepholePass
462 : public RequiredPassInfoMixin<SIPreEmitPeepholePass> {
463public:
464 PreservedAnalyses run(MachineFunction &MF,
465 MachineFunctionAnalysisManager &MFAM);
466};
467
468class AMDGPUSetWavePriorityPass
469 : public OptionalPassInfoMixin<AMDGPUSetWavePriorityPass> {
470public:
471 PreservedAnalyses run(MachineFunction &MF,
472 MachineFunctionAnalysisManager &MFAM);
473};
474
475FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
476
477ModulePass *createAMDGPUPrintfRuntimeBinding();
478void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
479extern char &AMDGPUPrintfRuntimeBindingID;
480
481void initializeAMDGPUResourceUsageAnalysisWrapperPassPass(PassRegistry &);
482extern char &AMDGPUResourceUsageAnalysisID;
483
484struct AMDGPUPrintfRuntimeBindingPass
485 : OptionalPassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
486 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
487};
488
489void initializeSIOptimizeExecMaskingPreRALegacyPass(PassRegistry &);
490extern char &SIOptimizeExecMaskingPreRAID;
491
492void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &);
493extern char &SIOptimizeVGPRLiveRangeLegacyID;
494
495void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
496extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
497
498void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
499extern char &AMDGPUCodeGenPrepareID;
500
501void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &);
502extern char &AMDGPURemoveIncompatibleFunctionsID;
503
504void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &);
505extern char &AMDGPULateCodeGenPrepareLegacyID;
506
507FunctionPass *createAMDGPURewriteUndefForPHILegacyPass();
508void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &);
509extern char &AMDGPURewriteUndefForPHILegacyPassID;
510
511class AMDGPURewriteUndefForPHIPass
512 : public OptionalPassInfoMixin<AMDGPURewriteUndefForPHIPass> {
513public:
514 AMDGPURewriteUndefForPHIPass() = default;
515 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
516};
517
518class SIAnnotateControlFlowPass
519 : public OptionalPassInfoMixin<SIAnnotateControlFlowPass> {
520private:
521 const AMDGPUTargetMachine &TM;
522
523public:
524 SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
525 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
526};
527
528void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
529extern char &SIAnnotateControlFlowLegacyPassID;
530
531void initializeSIMemoryLegalizerLegacyPass(PassRegistry &);
532extern char &SIMemoryLegalizerID;
533
534void initializeSIModeRegisterLegacyPass(PassRegistry &);
535extern char &SIModeRegisterID;
536
537void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
538extern char &AMDGPUInsertDelayAluID;
539
540void initializeAMDGPULowerVGPREncodingLegacyPass(PassRegistry &);
541extern char &AMDGPULowerVGPREncodingLegacyID;
542
543void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
544extern char &SIInsertHardClausesID;
545
546void initializeSIInsertWaitcntsLegacyPass(PassRegistry &);
547extern char &SIInsertWaitcntsID;
548
549void initializeSIFormMemoryClausesLegacyPass(PassRegistry &);
550extern char &SIFormMemoryClausesID;
551
552void initializeSIPostRABundlerLegacyPass(PassRegistry &);
553extern char &SIPostRABundlerLegacyID;
554
555void initializeGCNCreateVOPDLegacyPass(PassRegistry &);
556extern char &GCNCreateVOPDID;
557
558void initializeAMDGPUUnifyDivergentExitNodesLegacyPass(PassRegistry &);
559extern char &AMDGPUUnifyDivergentExitNodesID;
560
561ImmutablePass *createAMDGPUAAWrapperPass();
562void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
563ImmutablePass *createAMDGPUExternalAAWrapperPass();
564void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
565
566ModulePass *createAMDGPUExportKernelRuntimeHandlesLegacyPass();
567void initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(PassRegistry &);
568extern char &AMDGPUExportKernelRuntimeHandlesLegacyID;
569
570void initializeGCNNSAReassignLegacyPass(PassRegistry &);
571extern char &GCNNSAReassignID;
572
573void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &);
574extern char &GCNPreRALongBranchRegID;
575
576void initializeGCNPreRAOptimizationsLegacyPass(PassRegistry &);
577extern char &GCNPreRAOptimizationsID;
578
579FunctionPass *createAMDGPUSetWavePriorityPass();
580void initializeAMDGPUSetWavePriorityLegacyPass(PassRegistry &);
581
582void initializeGCNRewritePartialRegUsesLegacyPass(llvm::PassRegistry &);
583extern char &GCNRewritePartialRegUsesID;
584
585void initializeAMDGPUWaitSGPRHazardsLegacyPass(PassRegistry &);
586extern char &AMDGPUWaitSGPRHazardsLegacyID;
587
588class AMDGPURewriteAGPRCopyMFMAPass
589 : public OptionalPassInfoMixin<AMDGPURewriteAGPRCopyMFMAPass> {
590public:
591 AMDGPURewriteAGPRCopyMFMAPass() = default;
592 PreservedAnalyses run(MachineFunction &MF,
593 MachineFunctionAnalysisManager &MFAM);
594};
595
596void initializeAMDGPURewriteAGPRCopyMFMALegacyPass(PassRegistry &);
597extern char &AMDGPURewriteAGPRCopyMFMALegacyID;
598
599void initializeAMDGPUUniformIntrinsicCombineLegacyPass(PassRegistry &);
600extern char &AMDGPUUniformIntrinsicCombineLegacyPassID;
601FunctionPass *createAMDGPUUniformIntrinsicCombineLegacyPass();
602
603struct AMDGPUUniformIntrinsicCombinePass
604 : public OptionalPassInfoMixin<AMDGPUUniformIntrinsicCombinePass> {
605 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
606};
607
608namespace AMDGPU {
609enum TargetIndex {
610 TI_CONSTDATA_START,
611 TI_SCRATCH_RSRC_DWORD0,
612 TI_SCRATCH_RSRC_DWORD1,
613 TI_SCRATCH_RSRC_DWORD2,
614 TI_SCRATCH_RSRC_DWORD3
615};
616
617static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
618 if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
619 return true;
620
621 // clang-format off
622 static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
623 /* Flat Global Region Local Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
624 /* Flat */ {true, true, false, true, true, true, true, true, true, true},
625 /* Global */ {true, true, false, false, true, false, true, true, true, true},
626 /* Region */ {false, false, true, false, false, false, false, false, false, false},
627 /* Local */ {true, false, false, true, false, false, false, false, false, false},
628 /* Constant */ {true, true, false, false, false, false, true, true, true, true},
629 /* Private */ {true, false, false, false, false, true, false, false, false, false},
630 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true, true},
631 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true, true},
632 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true, true},
633 /* Buffer Strided Ptr */ {true, true, false, false, true, false, true, true, true, true},
634 };
635 // clang-format on
636 static_assert(std::size(ASAliasRules) == AMDGPUAS::MAX_AMDGPU_ADDRESS + 1);
637
638 return ASAliasRules[AS1][AS2];
639}
640
641}
642
643} // End namespace llvm
644
645#endif
646