1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/Analysis/CGSCCPassManager.h"
14#include "llvm/CodeGen/MachinePassManager.h"
15#include "llvm/IR/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Support/AMDGPUAddrSpace.h"
18#include "llvm/Support/CodeGen.h"
19
20namespace llvm {
21
22class AMDGPUTargetMachine;
23class LazyCallGraph;
24class GCNTargetMachine;
25class TargetMachine;
26
27// GlobalISel passes
28void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
29FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
30void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
31FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
32FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
33void initializeAMDGPURegBankCombinerPass(PassRegistry &);
34FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
35FunctionPass *createAMDGPURegBankSelectPass();
36FunctionPass *createAMDGPURegBankLegalizePass();
37
38// SI Passes
39FunctionPass *createGCNDPPCombinePass();
40FunctionPass *createSIAnnotateControlFlowLegacyPass();
41FunctionPass *createSIFoldOperandsLegacyPass();
42FunctionPass *createSIPeepholeSDWALegacyPass();
43FunctionPass *createSILowerI1CopiesLegacyPass();
44FunctionPass *createSIShrinkInstructionsLegacyPass();
45FunctionPass *createSILoadStoreOptimizerLegacyPass();
46FunctionPass *createSIWholeQuadModeLegacyPass();
47FunctionPass *createSIFixControlFlowLiveIntervalsPass();
48FunctionPass *createSIOptimizeExecMaskingPreRAPass();
49FunctionPass *createSIOptimizeVGPRLiveRangeLegacyPass();
50FunctionPass *createSIFixSGPRCopiesLegacyPass();
51FunctionPass *createLowerWWMCopiesPass();
52FunctionPass *createSIMemoryLegalizerPass();
53FunctionPass *createSIInsertWaitcntsPass();
54FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
55FunctionPass *createSIFormMemoryClausesLegacyPass();
56
57FunctionPass *createSIPostRABundlerPass();
58FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
59ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
60FunctionPass *createAMDGPUCodeGenPreparePass();
61FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
62FunctionPass *createAMDGPUReserveWWMRegsPass();
63FunctionPass *createAMDGPURewriteOutArgumentsPass();
64ModulePass *
65createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
66ModulePass *createAMDGPULowerBufferFatPointersPass();
67ModulePass *createAMDGPULowerIntrinsicsLegacyPass();
68FunctionPass *createSIModeRegisterPass();
69FunctionPass *createGCNPreRAOptimizationsLegacyPass();
70FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass();
71ModulePass *createAMDGPUPreloadKernelArgumentsLegacyPass(const TargetMachine *);
72
73struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
74 AMDGPUSimplifyLibCallsPass() = default;
75 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
76};
77
78struct AMDGPUImageIntrinsicOptimizerPass
79 : PassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
80 AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM) : TM(TM) {}
81 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
82
83private:
84 TargetMachine &TM;
85};
86
87struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
88 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
89};
90
91class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
92public:
93 SILowerI1CopiesPass() = default;
94 PreservedAnalyses run(MachineFunction &MF,
95 MachineFunctionAnalysisManager &MFAM);
96};
97
98void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
99
100void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
101
102void initializeAMDGPUAsmPrinterPass(PassRegistry &);
103
104// DPP/Iterative option enables the atomic optimizer with given strategy
105// whereas None disables the atomic optimizer.
106enum class ScanOptions { DPP, Iterative, None };
107FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
108void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
109extern char &AMDGPUAtomicOptimizerID;
110
111ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
112void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
113extern char &AMDGPUCtorDtorLoweringLegacyPassID;
114
115FunctionPass *createAMDGPULowerKernelArgumentsPass();
116void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
117extern char &AMDGPULowerKernelArgumentsID;
118
119FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
120void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
121extern char &AMDGPUPromoteKernelArgumentsID;
122
123struct AMDGPUPromoteKernelArgumentsPass
124 : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
125 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
126};
127
128ModulePass *createAMDGPULowerKernelAttributesPass();
129void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
130extern char &AMDGPULowerKernelAttributesID;
131
132struct AMDGPULowerKernelAttributesPass
133 : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
134 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
135};
136
137void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &);
138extern char &AMDGPULowerModuleLDSLegacyPassID;
139
140struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
141 const AMDGPUTargetMachine &TM;
142 AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
143
144 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
145};
146
147void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &);
148extern char &AMDGPULowerBufferFatPointersID;
149
150struct AMDGPULowerBufferFatPointersPass
151 : PassInfoMixin<AMDGPULowerBufferFatPointersPass> {
152 AMDGPULowerBufferFatPointersPass(const TargetMachine &TM) : TM(TM) {}
153 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
154
155private:
156 const TargetMachine &TM;
157};
158
159void initializeAMDGPULowerIntrinsicsLegacyPass(PassRegistry &);
160
161struct AMDGPULowerIntrinsicsPass : PassInfoMixin<AMDGPULowerIntrinsicsPass> {
162 AMDGPULowerIntrinsicsPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
163 PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM);
164
165private:
166 const AMDGPUTargetMachine &TM;
167};
168
169void initializeAMDGPUPrepareAGPRAllocLegacyPass(PassRegistry &);
170extern char &AMDGPUPrepareAGPRAllocLegacyID;
171
172void initializeAMDGPUReserveWWMRegsLegacyPass(PassRegistry &);
173extern char &AMDGPUReserveWWMRegsLegacyID;
174
175void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
176extern char &AMDGPURewriteOutArgumentsID;
177
178void initializeGCNDPPCombineLegacyPass(PassRegistry &);
179extern char &GCNDPPCombineLegacyID;
180
181void initializeSIFoldOperandsLegacyPass(PassRegistry &);
182extern char &SIFoldOperandsLegacyID;
183
184void initializeSIPeepholeSDWALegacyPass(PassRegistry &);
185extern char &SIPeepholeSDWALegacyID;
186
187void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
188extern char &SIShrinkInstructionsLegacyID;
189
190void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
191extern char &SIFixSGPRCopiesLegacyID;
192
193void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
194extern char &SIFixVGPRCopiesID;
195
196void initializeSILowerWWMCopiesLegacyPass(PassRegistry &);
197extern char &SILowerWWMCopiesLegacyID;
198
199void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
200extern char &SILowerI1CopiesLegacyID;
201
202void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
203extern char &AMDGPUGlobalISelDivergenceLoweringID;
204
205void initializeAMDGPURegBankSelectPass(PassRegistry &);
206extern char &AMDGPURegBankSelectID;
207
208void initializeAMDGPURegBankLegalizePass(PassRegistry &);
209extern char &AMDGPURegBankLegalizeID;
210
211void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
212extern char &AMDGPUMarkLastScratchLoadID;
213
214void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
215extern char &SILowerSGPRSpillsLegacyID;
216
217void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
218extern char &SILoadStoreOptimizerLegacyID;
219
220void initializeSIWholeQuadModeLegacyPass(PassRegistry &);
221extern char &SIWholeQuadModeID;
222
223void initializeSILowerControlFlowLegacyPass(PassRegistry &);
224extern char &SILowerControlFlowLegacyID;
225
226void initializeSIPreEmitPeepholeLegacyPass(PassRegistry &);
227extern char &SIPreEmitPeepholeID;
228
229void initializeSILateBranchLoweringLegacyPass(PassRegistry &);
230extern char &SILateBranchLoweringPassID;
231
232void initializeSIOptimizeExecMaskingLegacyPass(PassRegistry &);
233extern char &SIOptimizeExecMaskingLegacyID;
234
235void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
236extern char &SIPreAllocateWWMRegsLegacyID;
237
238void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
239extern char &AMDGPUImageIntrinsicOptimizerID;
240
241void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &);
242extern char &AMDGPUPerfHintAnalysisLegacyID;
243
244void initializeGCNRegPressurePrinterPass(PassRegistry &);
245extern char &GCNRegPressurePrinterID;
246
247void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &);
248extern char &AMDGPUPreloadKernArgPrologLegacyID;
249
250void initializeAMDGPUPreloadKernelArgumentsLegacyPass(PassRegistry &);
251extern char &AMDGPUPreloadKernelArgumentsLegacyID;
252
253// Passes common to R600 and SI
254FunctionPass *createAMDGPUPromoteAlloca();
255void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
256extern char &AMDGPUPromoteAllocaID;
257
258struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
259 AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
260 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
261
262private:
263 TargetMachine &TM;
264};
265
266struct AMDGPUPromoteAllocaToVectorPass
267 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
268 AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
269 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
270
271private:
272 TargetMachine &TM;
273};
274
275struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
276 AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
277 : TM(TM), ScanImpl(ScanImpl) {}
278 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
279
280private:
281 TargetMachine &TM;
282 ScanOptions ScanImpl;
283};
284
285struct AMDGPUInsertDelayAluPass
286 : public PassInfoMixin<AMDGPUInsertDelayAluPass> {
287 PreservedAnalyses run(MachineFunction &F,
288 MachineFunctionAnalysisManager &MFAM);
289};
290
291Pass *createAMDGPUStructurizeCFGPass();
292FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
293ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
294
295struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
296 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
297 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
298
299private:
300 bool GlobalOpt;
301};
302
303void initializeAMDGPULowerExecSyncLegacyPass(PassRegistry &);
304extern char &AMDGPULowerExecSyncLegacyPassID;
305ModulePass *createAMDGPULowerExecSyncLegacyPass();
306
307struct AMDGPULowerExecSyncPass : PassInfoMixin<AMDGPULowerExecSyncPass> {
308 AMDGPULowerExecSyncPass() {}
309 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
310};
311
312void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
313extern char &AMDGPUSwLowerLDSLegacyPassID;
314ModulePass *
315createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
316
317struct AMDGPUSwLowerLDSPass : PassInfoMixin<AMDGPUSwLowerLDSPass> {
318 const AMDGPUTargetMachine &TM;
319 AMDGPUSwLowerLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
320 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
321};
322
323class AMDGPUCodeGenPreparePass
324 : public PassInfoMixin<AMDGPUCodeGenPreparePass> {
325private:
326 TargetMachine &TM;
327
328public:
329 AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
330 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
331};
332
333class AMDGPULateCodeGenPreparePass
334 : public PassInfoMixin<AMDGPULateCodeGenPreparePass> {
335private:
336 const GCNTargetMachine &TM;
337
338public:
339 AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM) : TM(TM) {};
340 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
341};
342
343class AMDGPULowerKernelArgumentsPass
344 : public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
345private:
346 TargetMachine &TM;
347
348public:
349 AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
350 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
351};
352
353struct AMDGPUAttributorOptions {
354 bool IsClosedWorld = false;
355};
356
357class AMDGPUAttributorPass : public PassInfoMixin<AMDGPUAttributorPass> {
358private:
359 TargetMachine &TM;
360
361 AMDGPUAttributorOptions Options;
362
363 const ThinOrFullLTOPhase LTOPhase;
364
365public:
366 AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options,
367 ThinOrFullLTOPhase LTOPhase = ThinOrFullLTOPhase::None)
368 : TM(TM), Options(Options), LTOPhase(LTOPhase) {};
369 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
370};
371
372class AMDGPUAttributorCGSCCPass
373 : public PassInfoMixin<AMDGPUAttributorCGSCCPass> {
374private:
375 GCNTargetMachine &TM;
376
377public:
378 AMDGPUAttributorCGSCCPass(GCNTargetMachine &TM) : TM(TM) {}
379 PreservedAnalyses run(LazyCallGraph::SCC &C, CGSCCAnalysisManager &AM,
380 LazyCallGraph &CG, CGSCCUpdateResult &UR);
381};
382
383class AMDGPUPreloadKernelArgumentsPass
384 : public PassInfoMixin<AMDGPUPreloadKernelArgumentsPass> {
385 const TargetMachine &TM;
386
387public:
388 explicit AMDGPUPreloadKernelArgumentsPass(const TargetMachine &TM) : TM(TM) {}
389
390 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
391};
392
393class AMDGPUAnnotateUniformValuesPass
394 : public PassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
395public:
396 AMDGPUAnnotateUniformValuesPass() = default;
397 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
398};
399
400class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
401public:
402 SIModeRegisterPass() = default;
403 PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
404};
405
406class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
407public:
408 PreservedAnalyses run(MachineFunction &MF,
409 MachineFunctionAnalysisManager &MFAM);
410 static bool isRequired() { return true; }
411};
412
413class GCNCreateVOPDPass : public PassInfoMixin<GCNCreateVOPDPass> {
414public:
415 PreservedAnalyses run(MachineFunction &MF,
416 MachineFunctionAnalysisManager &AM);
417};
418
419class AMDGPUMarkLastScratchLoadPass
420 : public PassInfoMixin<AMDGPUMarkLastScratchLoadPass> {
421public:
422 PreservedAnalyses run(MachineFunction &MF,
423 MachineFunctionAnalysisManager &AM);
424};
425
426class SIInsertWaitcntsPass : public PassInfoMixin<SIInsertWaitcntsPass> {
427public:
428 PreservedAnalyses run(MachineFunction &MF,
429 MachineFunctionAnalysisManager &MFAM);
430 static bool isRequired() { return true; }
431};
432
433class SIInsertHardClausesPass : public PassInfoMixin<SIInsertHardClausesPass> {
434public:
435 PreservedAnalyses run(MachineFunction &MF,
436 MachineFunctionAnalysisManager &MFAM);
437};
438
439class SILateBranchLoweringPass
440 : public PassInfoMixin<SILateBranchLoweringPass> {
441public:
442 PreservedAnalyses run(MachineFunction &MF,
443 MachineFunctionAnalysisManager &MFAM);
444 static bool isRequired() { return true; }
445};
446
447class SIPreEmitPeepholePass : public PassInfoMixin<SIPreEmitPeepholePass> {
448public:
449 PreservedAnalyses run(MachineFunction &MF,
450 MachineFunctionAnalysisManager &MFAM);
451 static bool isRequired() { return true; }
452};
453
454class AMDGPUSetWavePriorityPass
455 : public PassInfoMixin<AMDGPUSetWavePriorityPass> {
456public:
457 PreservedAnalyses run(MachineFunction &MF,
458 MachineFunctionAnalysisManager &MFAM);
459};
460
461FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
462
463ModulePass *createAMDGPUPrintfRuntimeBinding();
464void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
465extern char &AMDGPUPrintfRuntimeBindingID;
466
467void initializeAMDGPUResourceUsageAnalysisWrapperPassPass(PassRegistry &);
468extern char &AMDGPUResourceUsageAnalysisID;
469
470struct AMDGPUPrintfRuntimeBindingPass
471 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
472 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
473};
474
475void initializeSIOptimizeExecMaskingPreRALegacyPass(PassRegistry &);
476extern char &SIOptimizeExecMaskingPreRAID;
477
478void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &);
479extern char &SIOptimizeVGPRLiveRangeLegacyID;
480
481void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
482extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
483
484void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
485extern char &AMDGPUCodeGenPrepareID;
486
487void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &);
488extern char &AMDGPURemoveIncompatibleFunctionsID;
489
490void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &);
491extern char &AMDGPULateCodeGenPrepareLegacyID;
492
493FunctionPass *createAMDGPURewriteUndefForPHILegacyPass();
494void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &);
495extern char &AMDGPURewriteUndefForPHILegacyPassID;
496
497class AMDGPURewriteUndefForPHIPass
498 : public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
499public:
500 AMDGPURewriteUndefForPHIPass() = default;
501 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
502};
503
504class SIAnnotateControlFlowPass
505 : public PassInfoMixin<SIAnnotateControlFlowPass> {
506private:
507 const AMDGPUTargetMachine &TM;
508
509public:
510 SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
511 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
512};
513
514void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
515extern char &SIAnnotateControlFlowLegacyPassID;
516
517void initializeSIMemoryLegalizerLegacyPass(PassRegistry &);
518extern char &SIMemoryLegalizerID;
519
520void initializeSIModeRegisterLegacyPass(PassRegistry &);
521extern char &SIModeRegisterID;
522
523void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
524extern char &AMDGPUInsertDelayAluID;
525
526void initializeAMDGPULowerVGPREncodingLegacyPass(PassRegistry &);
527extern char &AMDGPULowerVGPREncodingLegacyID;
528
529void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
530extern char &SIInsertHardClausesID;
531
532void initializeSIInsertWaitcntsLegacyPass(PassRegistry &);
533extern char &SIInsertWaitcntsID;
534
535void initializeSIFormMemoryClausesLegacyPass(PassRegistry &);
536extern char &SIFormMemoryClausesID;
537
538void initializeSIPostRABundlerLegacyPass(PassRegistry &);
539extern char &SIPostRABundlerLegacyID;
540
541void initializeGCNCreateVOPDLegacyPass(PassRegistry &);
542extern char &GCNCreateVOPDID;
543
544void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
545extern char &AMDGPUUnifyDivergentExitNodesID;
546
547ImmutablePass *createAMDGPUAAWrapperPass();
548void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
549ImmutablePass *createAMDGPUExternalAAWrapperPass();
550void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
551
552ModulePass *createAMDGPUExportKernelRuntimeHandlesLegacyPass();
553void initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(PassRegistry &);
554extern char &AMDGPUExportKernelRuntimeHandlesLegacyID;
555
556void initializeGCNNSAReassignLegacyPass(PassRegistry &);
557extern char &GCNNSAReassignID;
558
559void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &);
560extern char &GCNPreRALongBranchRegID;
561
562void initializeGCNPreRAOptimizationsLegacyPass(PassRegistry &);
563extern char &GCNPreRAOptimizationsID;
564
565FunctionPass *createAMDGPUSetWavePriorityPass();
566void initializeAMDGPUSetWavePriorityLegacyPass(PassRegistry &);
567
568void initializeGCNRewritePartialRegUsesLegacyPass(llvm::PassRegistry &);
569extern char &GCNRewritePartialRegUsesID;
570
571void initializeAMDGPUWaitSGPRHazardsLegacyPass(PassRegistry &);
572extern char &AMDGPUWaitSGPRHazardsLegacyID;
573
574class AMDGPURewriteAGPRCopyMFMAPass
575 : public PassInfoMixin<AMDGPURewriteAGPRCopyMFMAPass> {
576public:
577 AMDGPURewriteAGPRCopyMFMAPass() = default;
578 PreservedAnalyses run(MachineFunction &MF,
579 MachineFunctionAnalysisManager &MFAM);
580};
581
582void initializeAMDGPURewriteAGPRCopyMFMALegacyPass(PassRegistry &);
583extern char &AMDGPURewriteAGPRCopyMFMALegacyID;
584
585void initializeAMDGPUUniformIntrinsicCombineLegacyPass(PassRegistry &);
586extern char &AMDGPUUniformIntrinsicCombineLegacyPassID;
587FunctionPass *createAMDGPUUniformIntrinsicCombineLegacyPass();
588
589struct AMDGPUUniformIntrinsicCombinePass
590 : public PassInfoMixin<AMDGPUUniformIntrinsicCombinePass> {
591 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
592};
593
594namespace AMDGPU {
595enum TargetIndex {
596 TI_CONSTDATA_START,
597 TI_SCRATCH_RSRC_DWORD0,
598 TI_SCRATCH_RSRC_DWORD1,
599 TI_SCRATCH_RSRC_DWORD2,
600 TI_SCRATCH_RSRC_DWORD3
601};
602
603static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
604 if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
605 return true;
606
607 // clang-format off
608 static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
609 /* Flat Global Region Local Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
610 /* Flat */ {true, true, false, true, true, true, true, true, true, true},
611 /* Global */ {true, true, false, false, true, false, true, true, true, true},
612 /* Region */ {false, false, true, false, false, false, false, false, false, false},
613 /* Local */ {true, false, false, true, false, false, false, false, false, false},
614 /* Constant */ {true, true, false, false, false, false, true, true, true, true},
615 /* Private */ {true, false, false, false, false, true, false, false, false, false},
616 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true, true},
617 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true, true},
618 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true, true},
619 /* Buffer Strided Ptr */ {true, true, false, false, true, false, true, true, true, true},
620 };
621 // clang-format on
622 static_assert(std::size(ASAliasRules) == AMDGPUAS::MAX_AMDGPU_ADDRESS + 1);
623
624 return ASAliasRules[AS1][AS2];
625}
626
627}
628
629} // End namespace llvm
630
631#endif
632