1//===- AMDGPUMFMAIGroupLP.h - AMDGPU MFMA IGroupLP --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMFMAIGROUPLP_H
10#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMFMAIGROUPLP_H
11
12#include "llvm/ADT/BitmaskEnum.h"
13#include "llvm/CodeGen/ScheduleDAGMutation.h"
14#include <memory>
15
16namespace llvm {
17
18namespace AMDGPU {
19// The current phase of instruction scheduling
20enum class SchedulingPhase { Initial, PreRAReentry, PostRA };
21
22/// Operand 0 immediate for IGLP_OPT pseudo instructions.
23enum IGLPStrategyID : int {
24 MFMASmallGemmOptID = 0,
25 MFMASmallGemmSingleWaveOptID = 1,
26 MFMAExpInterleaveID = 2,
27 MFMAExpSimpleInterleaveID = 3,
28};
29
30// Components of the mask that determines which instruction types may be may be
31// classified into a SchedGroup.
32enum class SchedGroupMask {
33 NONE = 0u,
34 ALU = 1u << 0,
35 VALU = 1u << 1,
36 SALU = 1u << 2,
37 MFMA = 1u << 3,
38 VMEM = 1u << 4,
39 VMEM_READ = 1u << 5,
40 VMEM_WRITE = 1u << 6,
41 DS = 1u << 7,
42 DS_READ = 1u << 8,
43 DS_WRITE = 1u << 9,
44 TRANS = 1u << 10,
45 LDSDMA = 1u << 11,
46 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
47 DS_READ | DS_WRITE | TRANS | LDSDMA,
48 LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ ALL)
49};
50} // namespace AMDGPU
51
52std::unique_ptr<ScheduleDAGMutation>
53createIGroupLPDAGMutation(AMDGPU::SchedulingPhase Phase);
54
55} // namespace llvm
56
57#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUMFMAIGROUPLP_H
58