1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the TargetLowering class that is common
11/// to all AMD GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class AMDGPUSubtarget;
25struct ArgDescriptor;
26
27class AMDGPUTargetLowering : public TargetLowering {
28private:
29 const AMDGPUSubtarget *Subtarget;
30
31 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32 /// legalized from a smaller type VT. Need to match pre-legalized type because
33 /// the generic legalization inserts the add/sub between the select and
34 /// compare.
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36
37public:
38 /// \returns The minimum number of bits needed to store the value of \Op as an
39 /// unsigned integer. Truncating to this size and then zero-extending to the
40 /// original size will not change the value.
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
42
43 /// \returns The minimum number of bits needed to store the value of \Op as a
44 /// signed integer. Truncating to this size and then sign-extending to the
45 /// original size will not change the value.
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
47
48protected:
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
51 /// Split a vector store into multiple scalar stores.
52 /// \returns The resulting chain.
53
54 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
58
59 SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
62
63 static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags);
64 static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src,
65 SDNodeFlags Flags);
66 SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op,
67 SDNodeFlags Flags) const;
68 SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const;
69 std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
70 const SDLoc SL, SDValue Op,
71 SDNodeFlags Flags) const;
72
73 SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
74 SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const;
76 SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
77 bool IsLog10, SDNodeFlags Flags) const;
78 SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const;
79
80 SDValue lowerFEXPUnsafeImpl(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
81 SDNodeFlags Flags, bool IsExp10) const;
82
83 SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
84 SDNodeFlags Flags) const;
85 SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
86 SDNodeFlags Flags) const;
87 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
88 SDValue lowerFEXPF64(SDValue Op, SelectionDAG &DAG) const;
89
90 SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
91
92 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
93
94 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
95 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
96 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
98
99 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
100 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
103
104 SDValue LowerF64ToF16Safe(SDValue Src, const SDLoc &DL,
105 SelectionDAG &DAG) const;
106
107 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
108
109protected:
110 /// Check whether value Val can be supported by v_mov_b64, for the current
111 /// target.
112 bool isInt64ImmLegal(SDNode *Val, SelectionDAG &DAG) const;
113 bool shouldCombineMemoryType(EVT VT) const;
114 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
115 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
116 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
117 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
118
119 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
120 unsigned Opc, SDValue LHS,
121 uint32_t ValLo, uint32_t ValHi) const;
122 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
123 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
124 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
125 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
126 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
127 SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
128 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
129 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
130 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
131 SDValue RHS, DAGCombinerInfo &DCI) const;
132
133 SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
134 SDValue N) const;
135 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
136
137 TargetLowering::NegatibleCost
138 getConstantNegateCost(const ConstantFPSDNode *C) const;
139
140 bool isConstantCostlierToNegate(SDValue N) const;
141 bool isConstantCheaperToNegate(SDValue N) const;
142 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
143 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
144 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
145
146 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
147
148 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
149 SelectionDAG &DAG) const;
150
151 /// Return 64-bit value Op as two 32-bit integers.
152 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
153 SelectionDAG &DAG) const;
154 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
155 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
156
157 /// Split a vector type into two parts. The first part is a power of two
158 /// vector. The second part is whatever is left over, and is a scalar if it
159 /// would otherwise be a 1-vector.
160 std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
161
162 /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
163 /// scalar.
164 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
165 const EVT &LoVT, const EVT &HighVT,
166 SelectionDAG &DAG) const;
167
168 /// Split a vector load into 2 loads of half the vector.
169 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
170
171 /// Widen a suitably aligned v3 load. For all other cases, split the input
172 /// vector load.
173 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
174
175 /// Split a vector store into 2 stores of half the vector.
176 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
177
178 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
179 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
180 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
181 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
182 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
183 SmallVectorImpl<SDValue> &Results) const;
184
185 void analyzeFormalArgumentsCompute(
186 CCState &State,
187 const SmallVectorImpl<ISD::InputArg> &Ins) const;
188
189public:
190 AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
191 const AMDGPUSubtarget &AMDGPUSTI);
192
193 bool mayIgnoreSignedZero(SDValue Op) const;
194
195 static inline SDValue stripBitcast(SDValue Val) {
196 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(i: 0) : Val;
197 }
198
199 static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc);
200 static bool allUsesHaveSourceMods(const SDNode *N,
201 unsigned CostThreshold = 4);
202 bool isFAbsFree(EVT VT) const override;
203 bool isFNegFree(EVT VT) const override;
204 bool isTruncateFree(EVT Src, EVT Dest) const override;
205 bool isTruncateFree(Type *Src, Type *Dest) const override;
206
207 bool isZExtFree(Type *Src, Type *Dest) const override;
208 bool isZExtFree(EVT Src, EVT Dest) const override;
209
210 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
211 bool LegalOperations, bool ForCodeSize,
212 NegatibleCost &Cost,
213 unsigned Depth) const override;
214
215 bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
216
217 bool isDesirableToCommuteWithShift(const SDNode *N,
218 CombineLevel Level) const override;
219
220 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
221 ISD::NodeType ExtendKind) const override;
222
223 unsigned getVectorIdxWidth(const DataLayout &) const override;
224 bool isSelectSupported(SelectSupportKind) const override;
225
226 bool isFPImmLegal(const APFloat &Imm, EVT VT,
227 bool ForCodeSize) const override;
228 bool ShouldShrinkFPConstant(EVT VT) const override;
229 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT,
230 std::optional<unsigned> ByteOffset) const override;
231
232 bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
233 const MachineMemOperand &MMO) const final;
234
235 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
236 unsigned NumElem,
237 unsigned AS) const override;
238 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
239 bool isCheapToSpeculateCttz(Type *Ty) const override;
240 bool isCheapToSpeculateCtlz(Type *Ty) const override;
241
242 bool isSDNodeAlwaysUniform(const SDNode *N) const override;
243
244 // FIXME: This hook should not exist
245 AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override {
246 return AtomicExpansionKind::None;
247 }
248
249 AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override {
250 return AtomicExpansionKind::None;
251 }
252
253 AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *) const override {
254 return AtomicExpansionKind::None;
255 }
256
257 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
258 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
259
260 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
261 const SmallVectorImpl<ISD::OutputArg> &Outs,
262 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
263 SelectionDAG &DAG) const override;
264
265 SDValue addTokenForArgument(SDValue Chain,
266 SelectionDAG &DAG,
267 MachineFrameInfo &MFI,
268 int ClobberedFI) const;
269
270 SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
271 SmallVectorImpl<SDValue> &InVals,
272 StringRef Reason) const;
273 SDValue LowerCall(CallLoweringInfo &CLI,
274 SmallVectorImpl<SDValue> &InVals) const override;
275
276 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
277 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
278 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
279 void ReplaceNodeResults(SDNode * N,
280 SmallVectorImpl<SDValue> &Results,
281 SelectionDAG &DAG) const override;
282
283 SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS,
284 SDValue RHS, SDValue True, SDValue False,
285 SDValue CC, DAGCombinerInfo &DCI) const;
286
287 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
288 SDValue RHS, SDValue True, SDValue False,
289 SDValue CC, DAGCombinerInfo &DCI) const;
290
291 // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
292 // AMDGPU. Commit r319036,
293 // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
294 // turned on MergeConsecutiveStores() before Instruction Selection for all
295 // targets. Enough AMDGPU compiles go into an infinite loop (
296 // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
297 // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
298 // now.
299 bool mergeStoresAfterLegalization(EVT) const override { return false; }
300
301 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
302 return true;
303 }
304 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
305 int &RefinementSteps, bool &UseOneConstNR,
306 bool Reciprocal) const override;
307 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
308 int &RefinementSteps) const override;
309
310 virtual SDNode *PostISelFolding(MachineSDNode *N,
311 SelectionDAG &DAG) const = 0;
312
313 /// Determine which of the bits specified in \p Mask are known to be
314 /// either zero or one and return them in the \p KnownZero and \p KnownOne
315 /// bitsets.
316 void computeKnownBitsForTargetNode(const SDValue Op,
317 KnownBits &Known,
318 const APInt &DemandedElts,
319 const SelectionDAG &DAG,
320 unsigned Depth = 0) const override;
321
322 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
323 const SelectionDAG &DAG,
324 unsigned Depth = 0) const override;
325
326 unsigned computeNumSignBitsForTargetInstr(GISelValueTracking &Analysis,
327 Register R,
328 const APInt &DemandedElts,
329 const MachineRegisterInfo &MRI,
330 unsigned Depth = 0) const override;
331
332 bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
333 const APInt &DemandedElts,
334 const SelectionDAG &DAG,
335 bool PoisonOnly, bool ConsiderFlags,
336 unsigned Depth) const override;
337
338 bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
339 const SelectionDAG &DAG, bool SNaN = false,
340 unsigned Depth = 0) const override;
341
342 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
343 Register N1) const override;
344
345 /// Helper function that adds Reg to the LiveIn list of the DAG's
346 /// MachineFunction.
347 ///
348 /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
349 /// a copy from the register.
350 SDValue CreateLiveInRegister(SelectionDAG &DAG,
351 const TargetRegisterClass *RC,
352 Register Reg, EVT VT,
353 const SDLoc &SL,
354 bool RawReg = false) const;
355 SDValue CreateLiveInRegister(SelectionDAG &DAG,
356 const TargetRegisterClass *RC,
357 Register Reg, EVT VT) const {
358 return CreateLiveInRegister(DAG, RC, Reg, VT, SL: SDLoc(DAG.getEntryNode()));
359 }
360
361 // Returns the raw live in register rather than a copy from it.
362 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
363 const TargetRegisterClass *RC,
364 Register Reg, EVT VT) const {
365 return CreateLiveInRegister(DAG, RC, Reg, VT, SL: SDLoc(DAG.getEntryNode()), RawReg: true);
366 }
367
368 /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
369 /// slot rather than passed in a register.
370 SDValue loadStackInputValue(SelectionDAG &DAG,
371 EVT VT,
372 const SDLoc &SL,
373 int64_t Offset) const;
374
375 SDValue storeStackInputValue(SelectionDAG &DAG,
376 const SDLoc &SL,
377 SDValue Chain,
378 SDValue ArgVal,
379 int64_t Offset) const;
380
381 SDValue loadInputValue(SelectionDAG &DAG,
382 const TargetRegisterClass *RC,
383 EVT VT, const SDLoc &SL,
384 const ArgDescriptor &Arg) const;
385
386 enum ImplicitParameter {
387 FIRST_IMPLICIT,
388 PRIVATE_BASE,
389 SHARED_BASE,
390 QUEUE_PTR,
391 };
392
393 /// Helper function that returns the byte offset of the given
394 /// type of implicit parameter.
395 uint32_t getImplicitParameterOffset(const MachineFunction &MF,
396 const ImplicitParameter Param) const;
397 uint32_t getImplicitParameterOffset(const uint64_t ExplicitKernArgSize,
398 const ImplicitParameter Param) const;
399
400 MVT getFenceOperandTy(const DataLayout &DL) const override {
401 return MVT::i32;
402 }
403
404 bool hasMultipleConditionRegisters(EVT VT) const override {
405 // FIXME: This is only partially true. If we have to do vector compares, any
406 // SGPR pair can be a condition register. If we have a uniform condition, we
407 // are better off doing SALU operations, where there is only one SCC. For
408 // now, we don't have a way of knowing during instruction selection if a
409 // condition will be uniform and we always use vector compares. Assume we
410 // are using vector compares until that is fixed.
411 return true;
412 }
413};
414
415} // End namespace llvm
416
417#endif
418