1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the TargetLowering class that is common
11/// to all AMD GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunctionInfo;
24class AMDGPUSubtarget;
25struct ArgDescriptor;
26
27class AMDGPUTargetLowering : public TargetLowering {
28private:
29 const AMDGPUSubtarget *Subtarget;
30
31 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32 /// legalized from a smaller type VT. Need to match pre-legalized type because
33 /// the generic legalization inserts the add/sub between the select and
34 /// compare.
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36
37public:
38 /// \returns The minimum number of bits needed to store the value of \Op as an
39 /// unsigned integer. Truncating to this size and then zero-extending to the
40 /// original size will not change the value.
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
42
43 /// \returns The minimum number of bits needed to store the value of \Op as a
44 /// signed integer. Truncating to this size and then sign-extending to the
45 /// original size will not change the value.
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
47
48protected:
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
51 /// Split a vector store into multiple scalar stores.
52 /// \returns The resulting chain.
53
54 SDValue LowerCTLS(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
59
60 SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
63
64 static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags);
65 static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src,
66 SDNodeFlags Flags);
67 SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op,
68 SDNodeFlags Flags) const;
69 SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const;
70 std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
71 const SDLoc SL, SDValue Op,
72 SDNodeFlags Flags) const;
73
74 SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const;
76 SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const;
77 SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
78 bool IsLog10, SDNodeFlags Flags) const;
79 SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const;
80
81 SDValue lowerFEXPUnsafeImpl(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
82 SDNodeFlags Flags, bool IsExp10) const;
83
84 SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
85 SDNodeFlags Flags) const;
86 SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
87 SDNodeFlags Flags) const;
88 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
89 SDValue lowerFEXPF64(SDValue Op, SelectionDAG &DAG) const;
90
91 SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
92
93 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
94
95 SDValue LowerINT_TO_FP16(SDValue Op, SelectionDAG &DAG, EVT FP16Ty) const;
96 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
97 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
98 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
100
101 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
102 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
105
106 SDValue LowerF64ToF16Safe(SDValue Src, const SDLoc &DL,
107 SelectionDAG &DAG) const;
108
109 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
110
111protected:
112 /// Check whether value Val can be supported by v_mov_b64, for the current
113 /// target.
114 bool isInt64ImmLegal(SDNode *Val, SelectionDAG &DAG) const;
115 bool shouldCombineMemoryType(EVT VT) const;
116 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
117 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
118 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
119 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
120
121 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
122 unsigned Opc, SDValue LHS,
123 uint32_t ValLo, uint32_t ValHi) const;
124 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
125 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
126 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
127 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
128 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
129 SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
130 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
131 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
132 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
133 SDValue RHS, DAGCombinerInfo &DCI) const;
134
135 SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
136 SDValue N) const;
137 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
138
139 TargetLowering::NegatibleCost
140 getConstantNegateCost(const ConstantFPSDNode *C) const;
141
142 bool isConstantCostlierToNegate(SDValue N) const;
143 bool isConstantCheaperToNegate(SDValue N) const;
144 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
145 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
146 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
147
148 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
149
150 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI, SDValue Op,
151 SelectionDAG &DAG) const;
152
153 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
154
155 /// Return 64-bit value Op as two 32-bit integers.
156 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
157 SelectionDAG &DAG) const;
158 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
159 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
160
161 /// Split a vector type into two parts. The first part is a power of two
162 /// vector. The second part is whatever is left over, and is a scalar if it
163 /// would otherwise be a 1-vector.
164 std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
165
166 /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
167 /// scalar.
168 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
169 const EVT &LoVT, const EVT &HighVT,
170 SelectionDAG &DAG) const;
171
172 /// Split a vector load into 2 loads of half the vector.
173 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
174
175 /// Widen a suitably aligned v3 load. For all other cases, split the input
176 /// vector load.
177 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
178
179 /// Split a vector store into 2 stores of half the vector.
180 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
181
182 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
183 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
184 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
185 SDValue LowerDIVREMToFloat(SDValue Op, SelectionDAG &DAG, bool sign) const;
186 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
187 SmallVectorImpl<SDValue> &Results) const;
188
189 void analyzeFormalArgumentsCompute(
190 CCState &State,
191 const SmallVectorImpl<ISD::InputArg> &Ins) const;
192
193public:
194 AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
195 const AMDGPUSubtarget &AMDGPUSTI);
196
197 static inline SDValue stripBitcast(SDValue Val) {
198 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(i: 0) : Val;
199 }
200
201 static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc);
202 static bool allUsesHaveSourceMods(const SDNode *N,
203 unsigned CostThreshold = 4);
204 bool isFAbsFree(EVT VT) const override;
205 bool isFNegFree(EVT VT) const override;
206 bool isTruncateFree(EVT Src, EVT Dest) const override;
207 bool isTruncateFree(Type *Src, Type *Dest) const override;
208
209 bool isZExtFree(Type *Src, Type *Dest) const override;
210 bool isZExtFree(EVT Src, EVT Dest) const override;
211
212 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
213 bool LegalOperations, bool ForCodeSize,
214 NegatibleCost &Cost,
215 unsigned Depth) const override;
216
217 bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
218
219 bool isDesirableToCommuteWithShift(const SDNode *N,
220 CombineLevel Level) const override;
221
222 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
223 ISD::NodeType ExtendKind) const override;
224
225 unsigned getVectorIdxWidth(const DataLayout &) const override;
226 bool isSelectSupported(SelectSupportKind) const override;
227
228 bool isFPImmLegal(const APFloat &Imm, EVT VT,
229 bool ForCodeSize) const override;
230 bool ShouldShrinkFPConstant(EVT VT) const override;
231 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT,
232 std::optional<unsigned> ByteOffset) const override;
233
234 bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
235 const MachineMemOperand &MMO) const final;
236
237 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
238 unsigned NumElem,
239 unsigned AS) const override;
240 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
241 bool isCheapToSpeculateCttz(Type *Ty) const override;
242 bool isCheapToSpeculateCtlz(Type *Ty) const override;
243
244 bool isSDNodeAlwaysUniform(const SDNode *N) const override;
245
246 // FIXME: This hook should not exist
247 AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override {
248 return AtomicExpansionKind::None;
249 }
250
251 AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override {
252 return AtomicExpansionKind::None;
253 }
254
255 AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *) const override {
256 return AtomicExpansionKind::None;
257 }
258
259 bool shouldIssueAtomicLoadForAtomicEmulationLoop() const override {
260 return false;
261 }
262
263 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
264 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
265
266 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
267 const SmallVectorImpl<ISD::OutputArg> &Outs,
268 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
269 SelectionDAG &DAG) const override;
270
271 SDValue addTokenForArgument(SDValue Chain,
272 SelectionDAG &DAG,
273 MachineFrameInfo &MFI,
274 int ClobberedFI) const;
275
276 SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
277 SmallVectorImpl<SDValue> &InVals,
278 StringRef Reason) const;
279 SDValue LowerCall(CallLoweringInfo &CLI,
280 SmallVectorImpl<SDValue> &InVals) const override;
281
282 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
283 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
284 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
285
286 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
287 const APInt &OriginalDemandedBits,
288 const APInt &OriginalDemandedElts,
289 KnownBits &Known,
290 TargetLoweringOpt &TLO,
291 unsigned Depth) const override;
292
293 void ReplaceNodeResults(SDNode * N,
294 SmallVectorImpl<SDValue> &Results,
295 SelectionDAG &DAG) const override;
296
297 SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS,
298 SDValue RHS, SDValue True, SDValue False,
299 SDValue CC, DAGCombinerInfo &DCI) const;
300
301 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
302 SDValue RHS, SDValue True, SDValue False,
303 SDValue CC, DAGCombinerInfo &DCI) const;
304
305 // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
306 // AMDGPU. Commit r319036,
307 // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
308 // turned on MergeConsecutiveStores() before Instruction Selection for all
309 // targets. Enough AMDGPU compiles go into an infinite loop (
310 // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
311 // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
312 // now.
313 bool mergeStoresAfterLegalization(EVT) const override { return false; }
314
315 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
316 return true;
317 }
318 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
319 int &RefinementSteps, bool &UseOneConstNR,
320 bool Reciprocal) const override;
321 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
322 int &RefinementSteps) const override;
323
324 virtual SDNode *PostISelFolding(MachineSDNode *N,
325 SelectionDAG &DAG) const = 0;
326
327 /// Determine which of the bits specified in \p Mask are known to be
328 /// either zero or one and return them in the \p KnownZero and \p KnownOne
329 /// bitsets.
330 void computeKnownBitsForTargetNode(const SDValue Op,
331 KnownBits &Known,
332 const APInt &DemandedElts,
333 const SelectionDAG &DAG,
334 unsigned Depth = 0) const override;
335
336 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
337 const SelectionDAG &DAG,
338 unsigned Depth = 0) const override;
339
340 unsigned computeNumSignBitsForTargetInstr(GISelValueTracking &Analysis,
341 Register R,
342 const APInt &DemandedElts,
343 const MachineRegisterInfo &MRI,
344 unsigned Depth = 0) const override;
345
346 bool canCreateUndefOrPoisonForTargetNode(
347 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
348 UndefPoisonKind Kind, bool ConsiderFlags, unsigned Depth) const override;
349
350 bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
351 const SelectionDAG &DAG, bool SNaN = false,
352 unsigned Depth = 0) const override;
353
354 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
355 Register N1) const override;
356
357 /// Helper function that adds Reg to the LiveIn list of the DAG's
358 /// MachineFunction.
359 ///
360 /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
361 /// a copy from the register.
362 SDValue CreateLiveInRegister(SelectionDAG &DAG,
363 const TargetRegisterClass *RC,
364 Register Reg, EVT VT,
365 const SDLoc &SL,
366 bool RawReg = false) const;
367 SDValue CreateLiveInRegister(SelectionDAG &DAG,
368 const TargetRegisterClass *RC,
369 Register Reg, EVT VT) const {
370 return CreateLiveInRegister(DAG, RC, Reg, VT, SL: SDLoc(DAG.getEntryNode()));
371 }
372
373 // Returns the raw live in register rather than a copy from it.
374 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
375 const TargetRegisterClass *RC,
376 Register Reg, EVT VT) const {
377 return CreateLiveInRegister(DAG, RC, Reg, VT, SL: SDLoc(DAG.getEntryNode()), RawReg: true);
378 }
379
380 /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
381 /// slot rather than passed in a register.
382 SDValue loadStackInputValue(SelectionDAG &DAG,
383 EVT VT,
384 const SDLoc &SL,
385 int64_t Offset) const;
386
387 SDValue storeStackInputValue(SelectionDAG &DAG,
388 const SDLoc &SL,
389 SDValue Chain,
390 SDValue ArgVal,
391 int64_t Offset) const;
392
393 SDValue loadInputValue(SelectionDAG &DAG,
394 const TargetRegisterClass *RC,
395 EVT VT, const SDLoc &SL,
396 const ArgDescriptor &Arg) const;
397
398 enum ImplicitParameter {
399 FIRST_IMPLICIT,
400 PRIVATE_BASE,
401 SHARED_BASE,
402 QUEUE_PTR,
403 };
404
405 /// Helper function that returns the byte offset of the given
406 /// type of implicit parameter.
407 uint32_t getImplicitParameterOffset(const MachineFunction &MF,
408 const ImplicitParameter Param) const;
409 uint32_t getImplicitParameterOffset(const uint64_t ExplicitKernArgSize,
410 const ImplicitParameter Param) const;
411
412 MVT getFenceOperandTy(const DataLayout &DL) const override {
413 return MVT::i32;
414 }
415
416 bool hasMultipleConditionRegisters(EVT VT) const override {
417 // FIXME: This is only partially true. If we have to do vector compares, any
418 // SGPR pair can be a condition register. If we have a uniform condition, we
419 // are better off doing SALU operations, where there is only one SCC. For
420 // now, we don't have a way of knowing during instruction selection if a
421 // condition will be uniform and we always use vector compares. Assume we
422 // are using vector compares until that is fixed.
423 return true;
424 }
425};
426
427} // End namespace llvm
428
429#endif
430