1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the TargetLowering class that is common
11/// to all AMD GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunctionInfo;
24class AMDGPUSubtarget;
25struct ArgDescriptor;
26
27class AMDGPUTargetLowering : public TargetLowering {
28private:
29 const AMDGPUSubtarget *Subtarget;
30
31 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32 /// legalized from a smaller type VT. Need to match pre-legalized type because
33 /// the generic legalization inserts the add/sub between the select and
34 /// compare.
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36
37public:
38 /// \returns The minimum number of bits needed to store the value of \Op as an
39 /// unsigned integer. Truncating to this size and then zero-extending to the
40 /// original size will not change the value.
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
42
43 /// \returns The minimum number of bits needed to store the value of \Op as a
44 /// signed integer. Truncating to this size and then sign-extending to the
45 /// original size will not change the value.
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
47
48protected:
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
51 /// Split a vector store into multiple scalar stores.
52 /// \returns The resulting chain.
53
54 SDValue LowerCTLS(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
59
60 SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
63
64 static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags);
65 static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src,
66 SDNodeFlags Flags);
67 SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op,
68 SDNodeFlags Flags) const;
69 SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const;
70 std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
71 const SDLoc SL, SDValue Op,
72 SDNodeFlags Flags) const;
73
74 SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const;
76 SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const;
77 SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
78 bool IsLog10, SDNodeFlags Flags) const;
79 SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const;
80
81 SDValue lowerFEXPUnsafeImpl(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
82 SDNodeFlags Flags, bool IsExp10) const;
83
84 SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
85 SDNodeFlags Flags) const;
86 SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
87 SDNodeFlags Flags) const;
88 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
89 SDValue lowerFEXPF64(SDValue Op, SelectionDAG &DAG) const;
90
91 SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
92
93 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
94
95 SDValue LowerINT_TO_FP16(SDValue Op, SelectionDAG &DAG, EVT FP16Ty) const;
96 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
97 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
98 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
100
101 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
102 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
105
106 SDValue LowerF64ToF16Safe(SDValue Src, const SDLoc &DL,
107 SelectionDAG &DAG) const;
108
109 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
110
111protected:
112 /// Check whether value Val can be supported by v_mov_b64, for the current
113 /// target.
114 bool isInt64ImmLegal(SDNode *Val, SelectionDAG &DAG) const;
115 bool shouldCombineMemoryType(EVT VT) const;
116 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
117 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
118 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
119 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
120
121 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
122 unsigned Opc, SDValue LHS,
123 uint32_t ValLo, uint32_t ValHi) const;
124 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
125 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
126 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
127 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
128 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
129 SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
130 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
131 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
132 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
133 SDValue RHS, DAGCombinerInfo &DCI) const;
134
135 SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
136 SDValue N) const;
137 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
138
139 TargetLowering::NegatibleCost
140 getConstantNegateCost(const ConstantFPSDNode *C) const;
141
142 bool isConstantCostlierToNegate(SDValue N) const;
143 bool isConstantCheaperToNegate(SDValue N) const;
144 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
145 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
146 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
147
148 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
149
150 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI, SDValue Op,
151 SelectionDAG &DAG) const;
152
153 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
154
155 /// Return 64-bit value Op as two 32-bit integers.
156 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
157 SelectionDAG &DAG) const;
158 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
159 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
160
161 /// Split a vector type into two parts. The first part is a power of two
162 /// vector. The second part is whatever is left over, and is a scalar if it
163 /// would otherwise be a 1-vector.
164 std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
165
166 /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
167 /// scalar.
168 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
169 const EVT &LoVT, const EVT &HighVT,
170 SelectionDAG &DAG) const;
171
172 /// Split a vector load into 2 loads of half the vector.
173 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
174
175 /// Widen a suitably aligned v3 load. For all other cases, split the input
176 /// vector load.
177 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
178
179 /// Split a vector store into 2 stores of half the vector.
180 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
181
182 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
183 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
184 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
185 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
186 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
187 SmallVectorImpl<SDValue> &Results) const;
188
189 void analyzeFormalArgumentsCompute(
190 CCState &State,
191 const SmallVectorImpl<ISD::InputArg> &Ins) const;
192
193public:
194 AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
195 const AMDGPUSubtarget &AMDGPUSTI);
196
197 bool mayIgnoreSignedZero(SDValue Op) const;
198
199 static inline SDValue stripBitcast(SDValue Val) {
200 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(i: 0) : Val;
201 }
202
203 static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc);
204 static bool allUsesHaveSourceMods(const SDNode *N,
205 unsigned CostThreshold = 4);
206 bool isFAbsFree(EVT VT) const override;
207 bool isFNegFree(EVT VT) const override;
208 bool isTruncateFree(EVT Src, EVT Dest) const override;
209 bool isTruncateFree(Type *Src, Type *Dest) const override;
210
211 bool isZExtFree(Type *Src, Type *Dest) const override;
212 bool isZExtFree(EVT Src, EVT Dest) const override;
213
214 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
215 bool LegalOperations, bool ForCodeSize,
216 NegatibleCost &Cost,
217 unsigned Depth) const override;
218
219 bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
220
221 bool isDesirableToCommuteWithShift(const SDNode *N,
222 CombineLevel Level) const override;
223
224 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
225 ISD::NodeType ExtendKind) const override;
226
227 unsigned getVectorIdxWidth(const DataLayout &) const override;
228 bool isSelectSupported(SelectSupportKind) const override;
229
230 bool isFPImmLegal(const APFloat &Imm, EVT VT,
231 bool ForCodeSize) const override;
232 bool ShouldShrinkFPConstant(EVT VT) const override;
233 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT,
234 std::optional<unsigned> ByteOffset) const override;
235
236 bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
237 const MachineMemOperand &MMO) const final;
238
239 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
240 unsigned NumElem,
241 unsigned AS) const override;
242 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
243 bool isCheapToSpeculateCttz(Type *Ty) const override;
244 bool isCheapToSpeculateCtlz(Type *Ty) const override;
245
246 bool isSDNodeAlwaysUniform(const SDNode *N) const override;
247
248 // FIXME: This hook should not exist
249 AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override {
250 return AtomicExpansionKind::None;
251 }
252
253 AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override {
254 return AtomicExpansionKind::None;
255 }
256
257 AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *) const override {
258 return AtomicExpansionKind::None;
259 }
260
261 bool shouldIssueAtomicLoadForAtomicEmulationLoop() const override {
262 return false;
263 }
264
265 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
266 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
267
268 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
269 const SmallVectorImpl<ISD::OutputArg> &Outs,
270 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
271 SelectionDAG &DAG) const override;
272
273 SDValue addTokenForArgument(SDValue Chain,
274 SelectionDAG &DAG,
275 MachineFrameInfo &MFI,
276 int ClobberedFI) const;
277
278 SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
279 SmallVectorImpl<SDValue> &InVals,
280 StringRef Reason) const;
281 SDValue LowerCall(CallLoweringInfo &CLI,
282 SmallVectorImpl<SDValue> &InVals) const override;
283
284 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
285 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
286 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
287
288 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
289 const APInt &OriginalDemandedBits,
290 const APInt &OriginalDemandedElts,
291 KnownBits &Known,
292 TargetLoweringOpt &TLO,
293 unsigned Depth) const override;
294
295 void ReplaceNodeResults(SDNode * N,
296 SmallVectorImpl<SDValue> &Results,
297 SelectionDAG &DAG) const override;
298
299 SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS,
300 SDValue RHS, SDValue True, SDValue False,
301 SDValue CC, DAGCombinerInfo &DCI) const;
302
303 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
304 SDValue RHS, SDValue True, SDValue False,
305 SDValue CC, DAGCombinerInfo &DCI) const;
306
307 // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
308 // AMDGPU. Commit r319036,
309 // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
310 // turned on MergeConsecutiveStores() before Instruction Selection for all
311 // targets. Enough AMDGPU compiles go into an infinite loop (
312 // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
313 // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
314 // now.
315 bool mergeStoresAfterLegalization(EVT) const override { return false; }
316
317 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
318 return true;
319 }
320 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
321 int &RefinementSteps, bool &UseOneConstNR,
322 bool Reciprocal) const override;
323 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
324 int &RefinementSteps) const override;
325
326 virtual SDNode *PostISelFolding(MachineSDNode *N,
327 SelectionDAG &DAG) const = 0;
328
329 /// Determine which of the bits specified in \p Mask are known to be
330 /// either zero or one and return them in the \p KnownZero and \p KnownOne
331 /// bitsets.
332 void computeKnownBitsForTargetNode(const SDValue Op,
333 KnownBits &Known,
334 const APInt &DemandedElts,
335 const SelectionDAG &DAG,
336 unsigned Depth = 0) const override;
337
338 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
339 const SelectionDAG &DAG,
340 unsigned Depth = 0) const override;
341
342 unsigned computeNumSignBitsForTargetInstr(GISelValueTracking &Analysis,
343 Register R,
344 const APInt &DemandedElts,
345 const MachineRegisterInfo &MRI,
346 unsigned Depth = 0) const override;
347
348 bool canCreateUndefOrPoisonForTargetNode(
349 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
350 UndefPoisonKind Kind, bool ConsiderFlags, unsigned Depth) const override;
351
352 bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
353 const SelectionDAG &DAG, bool SNaN = false,
354 unsigned Depth = 0) const override;
355
356 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
357 Register N1) const override;
358
359 /// Helper function that adds Reg to the LiveIn list of the DAG's
360 /// MachineFunction.
361 ///
362 /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
363 /// a copy from the register.
364 SDValue CreateLiveInRegister(SelectionDAG &DAG,
365 const TargetRegisterClass *RC,
366 Register Reg, EVT VT,
367 const SDLoc &SL,
368 bool RawReg = false) const;
369 SDValue CreateLiveInRegister(SelectionDAG &DAG,
370 const TargetRegisterClass *RC,
371 Register Reg, EVT VT) const {
372 return CreateLiveInRegister(DAG, RC, Reg, VT, SL: SDLoc(DAG.getEntryNode()));
373 }
374
375 // Returns the raw live in register rather than a copy from it.
376 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
377 const TargetRegisterClass *RC,
378 Register Reg, EVT VT) const {
379 return CreateLiveInRegister(DAG, RC, Reg, VT, SL: SDLoc(DAG.getEntryNode()), RawReg: true);
380 }
381
382 /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
383 /// slot rather than passed in a register.
384 SDValue loadStackInputValue(SelectionDAG &DAG,
385 EVT VT,
386 const SDLoc &SL,
387 int64_t Offset) const;
388
389 SDValue storeStackInputValue(SelectionDAG &DAG,
390 const SDLoc &SL,
391 SDValue Chain,
392 SDValue ArgVal,
393 int64_t Offset) const;
394
395 SDValue loadInputValue(SelectionDAG &DAG,
396 const TargetRegisterClass *RC,
397 EVT VT, const SDLoc &SL,
398 const ArgDescriptor &Arg) const;
399
400 enum ImplicitParameter {
401 FIRST_IMPLICIT,
402 PRIVATE_BASE,
403 SHARED_BASE,
404 QUEUE_PTR,
405 };
406
407 /// Helper function that returns the byte offset of the given
408 /// type of implicit parameter.
409 uint32_t getImplicitParameterOffset(const MachineFunction &MF,
410 const ImplicitParameter Param) const;
411 uint32_t getImplicitParameterOffset(const uint64_t ExplicitKernArgSize,
412 const ImplicitParameter Param) const;
413
414 MVT getFenceOperandTy(const DataLayout &DL) const override {
415 return MVT::i32;
416 }
417
418 bool hasMultipleConditionRegisters(EVT VT) const override {
419 // FIXME: This is only partially true. If we have to do vector compares, any
420 // SGPR pair can be a condition register. If we have a uniform condition, we
421 // are better off doing SALU operations, where there is only one SCC. For
422 // now, we don't have a way of knowing during instruction selection if a
423 // condition will be uniform and we always use vector compares. Assume we
424 // are using vector compares until that is fixed.
425 return true;
426 }
427};
428
429} // End namespace llvm
430
431#endif
432