1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the TargetLowering class that is common
11/// to all AMD GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class AMDGPUSubtarget;
25struct ArgDescriptor;
26
27class AMDGPUTargetLowering : public TargetLowering {
28private:
29 const AMDGPUSubtarget *Subtarget;
30
31 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32 /// legalized from a smaller type VT. Need to match pre-legalized type because
33 /// the generic legalization inserts the add/sub between the select and
34 /// compare.
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36
37public:
38 /// \returns The minimum number of bits needed to store the value of \Op as an
39 /// unsigned integer. Truncating to this size and then zero-extending to the
40 /// original size will not change the value.
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
42
43 /// \returns The minimum number of bits needed to store the value of \Op as a
44 /// signed integer. Truncating to this size and then sign-extending to the
45 /// original size will not change the value.
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
47
48protected:
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
51 /// Split a vector store into multiple scalar stores.
52 /// \returns The resulting chain.
53
54 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
58
59 SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
62
63 static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags);
64 static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src,
65 SDNodeFlags Flags);
66 SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op,
67 SDNodeFlags Flags) const;
68 SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const;
69 std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
70 const SDLoc SL, SDValue Op,
71 SDNodeFlags Flags) const;
72
73 SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
74 SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const;
76 SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
77 bool IsLog10, SDNodeFlags Flags) const;
78 SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const;
79
80 SDValue lowerFEXPUnsafeImpl(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
81 SDNodeFlags Flags, bool IsExp10) const;
82
83 SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
84 SDNodeFlags Flags) const;
85 SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
86 SDNodeFlags Flags) const;
87 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
88
89 SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
90
91 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
92
93 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
94 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
95 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
97
98 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
99 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
102
103 SDValue LowerF64ToF16Safe(SDValue Src, const SDLoc &DL,
104 SelectionDAG &DAG) const;
105
106 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
107
108protected:
109 bool shouldCombineMemoryType(EVT VT) const;
110 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
111 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
112 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
113 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
114
115 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
116 unsigned Opc, SDValue LHS,
117 uint32_t ValLo, uint32_t ValHi) const;
118 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
119 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
120 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
121 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
122 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
123 SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
124 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
125 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
126 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
127 SDValue RHS, DAGCombinerInfo &DCI) const;
128
129 SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
130 SDValue N) const;
131 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
132
133 TargetLowering::NegatibleCost
134 getConstantNegateCost(const ConstantFPSDNode *C) const;
135
136 bool isConstantCostlierToNegate(SDValue N) const;
137 bool isConstantCheaperToNegate(SDValue N) const;
138 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
139 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
140 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
141
142 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
143
144 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
145 SelectionDAG &DAG) const;
146
147 /// Return 64-bit value Op as two 32-bit integers.
148 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
149 SelectionDAG &DAG) const;
150 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
151 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
152
153 /// Split a vector type into two parts. The first part is a power of two
154 /// vector. The second part is whatever is left over, and is a scalar if it
155 /// would otherwise be a 1-vector.
156 std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
157
158 /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
159 /// scalar.
160 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
161 const EVT &LoVT, const EVT &HighVT,
162 SelectionDAG &DAG) const;
163
164 /// Split a vector load into 2 loads of half the vector.
165 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
166
167 /// Widen a suitably aligned v3 load. For all other cases, split the input
168 /// vector load.
169 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
170
171 /// Split a vector store into 2 stores of half the vector.
172 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
173
174 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
175 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
176 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
177 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
178 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
179 SmallVectorImpl<SDValue> &Results) const;
180
181 void analyzeFormalArgumentsCompute(
182 CCState &State,
183 const SmallVectorImpl<ISD::InputArg> &Ins) const;
184
185public:
186 AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
187 const AMDGPUSubtarget &AMDGPUSTI);
188
189 bool mayIgnoreSignedZero(SDValue Op) const;
190
191 static inline SDValue stripBitcast(SDValue Val) {
192 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(i: 0) : Val;
193 }
194
195 static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc);
196 static bool allUsesHaveSourceMods(const SDNode *N,
197 unsigned CostThreshold = 4);
198 bool isFAbsFree(EVT VT) const override;
199 bool isFNegFree(EVT VT) const override;
200 bool isTruncateFree(EVT Src, EVT Dest) const override;
201 bool isTruncateFree(Type *Src, Type *Dest) const override;
202
203 bool isZExtFree(Type *Src, Type *Dest) const override;
204 bool isZExtFree(EVT Src, EVT Dest) const override;
205
206 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
207 bool LegalOperations, bool ForCodeSize,
208 NegatibleCost &Cost,
209 unsigned Depth) const override;
210
211 bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
212
213 bool isDesirableToCommuteWithShift(const SDNode *N,
214 CombineLevel Level) const override;
215
216 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
217 ISD::NodeType ExtendKind) const override;
218
219 unsigned getVectorIdxWidth(const DataLayout &) const override;
220 bool isSelectSupported(SelectSupportKind) const override;
221
222 bool isFPImmLegal(const APFloat &Imm, EVT VT,
223 bool ForCodeSize) const override;
224 bool ShouldShrinkFPConstant(EVT VT) const override;
225 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT,
226 std::optional<unsigned> ByteOffset) const override;
227
228 bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
229 const MachineMemOperand &MMO) const final;
230
231 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
232 unsigned NumElem,
233 unsigned AS) const override;
234 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
235 bool isCheapToSpeculateCttz(Type *Ty) const override;
236 bool isCheapToSpeculateCtlz(Type *Ty) const override;
237
238 bool isSDNodeAlwaysUniform(const SDNode *N) const override;
239
240 // FIXME: This hook should not exist
241 AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override {
242 return AtomicExpansionKind::None;
243 }
244
245 AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override {
246 return AtomicExpansionKind::None;
247 }
248
249 AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *) const override {
250 return AtomicExpansionKind::None;
251 }
252
253 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
254 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
255
256 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
257 const SmallVectorImpl<ISD::OutputArg> &Outs,
258 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
259 SelectionDAG &DAG) const override;
260
261 SDValue addTokenForArgument(SDValue Chain,
262 SelectionDAG &DAG,
263 MachineFrameInfo &MFI,
264 int ClobberedFI) const;
265
266 SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
267 SmallVectorImpl<SDValue> &InVals,
268 StringRef Reason) const;
269 SDValue LowerCall(CallLoweringInfo &CLI,
270 SmallVectorImpl<SDValue> &InVals) const override;
271
272 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
273 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
274 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
275 void ReplaceNodeResults(SDNode * N,
276 SmallVectorImpl<SDValue> &Results,
277 SelectionDAG &DAG) const override;
278
279 SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS,
280 SDValue RHS, SDValue True, SDValue False,
281 SDValue CC, DAGCombinerInfo &DCI) const;
282
283 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
284 SDValue RHS, SDValue True, SDValue False,
285 SDValue CC, DAGCombinerInfo &DCI) const;
286
287 // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
288 // AMDGPU. Commit r319036,
289 // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
290 // turned on MergeConsecutiveStores() before Instruction Selection for all
291 // targets. Enough AMDGPU compiles go into an infinite loop (
292 // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
293 // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
294 // now.
295 bool mergeStoresAfterLegalization(EVT) const override { return false; }
296
297 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
298 return true;
299 }
300 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
301 int &RefinementSteps, bool &UseOneConstNR,
302 bool Reciprocal) const override;
303 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
304 int &RefinementSteps) const override;
305
306 virtual SDNode *PostISelFolding(MachineSDNode *N,
307 SelectionDAG &DAG) const = 0;
308
309 /// Determine which of the bits specified in \p Mask are known to be
310 /// either zero or one and return them in the \p KnownZero and \p KnownOne
311 /// bitsets.
312 void computeKnownBitsForTargetNode(const SDValue Op,
313 KnownBits &Known,
314 const APInt &DemandedElts,
315 const SelectionDAG &DAG,
316 unsigned Depth = 0) const override;
317
318 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
319 const SelectionDAG &DAG,
320 unsigned Depth = 0) const override;
321
322 unsigned computeNumSignBitsForTargetInstr(GISelValueTracking &Analysis,
323 Register R,
324 const APInt &DemandedElts,
325 const MachineRegisterInfo &MRI,
326 unsigned Depth = 0) const override;
327
328 bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
329 const APInt &DemandedElts,
330 const SelectionDAG &DAG,
331 bool PoisonOnly, bool ConsiderFlags,
332 unsigned Depth) const override;
333
334 bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
335 const SelectionDAG &DAG, bool SNaN = false,
336 unsigned Depth = 0) const override;
337
338 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
339 Register N1) const override;
340
341 /// Helper function that adds Reg to the LiveIn list of the DAG's
342 /// MachineFunction.
343 ///
344 /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
345 /// a copy from the register.
346 SDValue CreateLiveInRegister(SelectionDAG &DAG,
347 const TargetRegisterClass *RC,
348 Register Reg, EVT VT,
349 const SDLoc &SL,
350 bool RawReg = false) const;
351 SDValue CreateLiveInRegister(SelectionDAG &DAG,
352 const TargetRegisterClass *RC,
353 Register Reg, EVT VT) const {
354 return CreateLiveInRegister(DAG, RC, Reg, VT, SL: SDLoc(DAG.getEntryNode()));
355 }
356
357 // Returns the raw live in register rather than a copy from it.
358 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
359 const TargetRegisterClass *RC,
360 Register Reg, EVT VT) const {
361 return CreateLiveInRegister(DAG, RC, Reg, VT, SL: SDLoc(DAG.getEntryNode()), RawReg: true);
362 }
363
364 /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
365 /// slot rather than passed in a register.
366 SDValue loadStackInputValue(SelectionDAG &DAG,
367 EVT VT,
368 const SDLoc &SL,
369 int64_t Offset) const;
370
371 SDValue storeStackInputValue(SelectionDAG &DAG,
372 const SDLoc &SL,
373 SDValue Chain,
374 SDValue ArgVal,
375 int64_t Offset) const;
376
377 SDValue loadInputValue(SelectionDAG &DAG,
378 const TargetRegisterClass *RC,
379 EVT VT, const SDLoc &SL,
380 const ArgDescriptor &Arg) const;
381
382 enum ImplicitParameter {
383 FIRST_IMPLICIT,
384 PRIVATE_BASE,
385 SHARED_BASE,
386 QUEUE_PTR,
387 };
388
389 /// Helper function that returns the byte offset of the given
390 /// type of implicit parameter.
391 uint32_t getImplicitParameterOffset(const MachineFunction &MF,
392 const ImplicitParameter Param) const;
393 uint32_t getImplicitParameterOffset(const uint64_t ExplicitKernArgSize,
394 const ImplicitParameter Param) const;
395
396 MVT getFenceOperandTy(const DataLayout &DL) const override {
397 return MVT::i32;
398 }
399
400 bool hasMultipleConditionRegisters(EVT VT) const override {
401 // FIXME: This is only partially true. If we have to do vector compares, any
402 // SGPR pair can be a condition register. If we have a uniform condition, we
403 // are better off doing SALU operations, where there is only one SCC. For
404 // now, we don't have a way of knowing during instruction selection if a
405 // condition will be uniform and we always use vector compares. Assume we
406 // are using vector compares until that is fixed.
407 return true;
408 }
409};
410
411} // End namespace llvm
412
413#endif
414