1//===--- AMDGPUMachineModuleInfo.h ------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// AMDGPU Machine Module Info.
11///
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEMODULEINFO_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEMODULEINFO_H
17
18#include "llvm/CodeGen/MachineModuleInfoImpls.h"
19#include "llvm/IR/LLVMContext.h"
20
21namespace llvm {
22
23class AMDGPUMachineModuleInfo final : public MachineModuleInfoELF {
24private:
25
26 // All supported memory/synchronization scopes can be found here:
27 // http://llvm.org/docs/AMDGPUUsage.html#memory-scopes
28
29 /// Agent synchronization scope ID (cross address space).
30 SyncScope::ID AgentSSID;
31 /// Workgroup synchronization scope ID (cross address space).
32 SyncScope::ID WorkgroupSSID;
33 /// Wavefront synchronization scope ID (cross address space).
34 SyncScope::ID WavefrontSSID;
35 /// Cluster synchronization scope ID (cross address space).
36 SyncScope::ID ClusterSSID;
37 /// System synchronization scope ID (single address space).
38 SyncScope::ID SystemOneAddressSpaceSSID;
39 /// Agent synchronization scope ID (single address space).
40 SyncScope::ID AgentOneAddressSpaceSSID;
41 /// Workgroup synchronization scope ID (single address space).
42 SyncScope::ID WorkgroupOneAddressSpaceSSID;
43 /// Wavefront synchronization scope ID (single address space).
44 SyncScope::ID WavefrontOneAddressSpaceSSID;
45 /// Single thread synchronization scope ID (single address space).
46 SyncScope::ID SingleThreadOneAddressSpaceSSID;
47 /// Cluster synchronization scope ID (single address space).
48 SyncScope::ID ClusterOneAddressSpaceSSID;
49
50 /// In AMDGPU target synchronization scopes are inclusive, meaning a
51 /// larger synchronization scope is inclusive of a smaller synchronization
52 /// scope.
53 ///
54 /// \returns \p SSID's inclusion ordering, or "std::nullopt" if \p SSID is not
55 /// supported by the AMDGPU target.
56 std::optional<uint8_t>
57 getSyncScopeInclusionOrdering(SyncScope::ID SSID) const {
58 if (SSID == SyncScope::SingleThread ||
59 SSID == getSingleThreadOneAddressSpaceSSID())
60 return 0;
61 else if (SSID == getWavefrontSSID() ||
62 SSID == getWavefrontOneAddressSpaceSSID())
63 return 1;
64 else if (SSID == getWorkgroupSSID() ||
65 SSID == getWorkgroupOneAddressSpaceSSID())
66 return 2;
67 else if (SSID == getClusterSSID() ||
68 SSID == getClusterOneAddressSpaceSSID())
69 return 3;
70 else if (SSID == getAgentSSID() ||
71 SSID == getAgentOneAddressSpaceSSID())
72 return 4;
73 else if (SSID == SyncScope::System ||
74 SSID == getSystemOneAddressSpaceSSID())
75 return 5;
76
77 return std::nullopt;
78 }
79
80 /// \returns True if \p SSID is restricted to single address space, false
81 /// otherwise
82 bool isOneAddressSpace(SyncScope::ID SSID) const {
83 return SSID == getClusterOneAddressSpaceSSID() ||
84 SSID == getSingleThreadOneAddressSpaceSSID() ||
85 SSID == getWavefrontOneAddressSpaceSSID() ||
86 SSID == getWorkgroupOneAddressSpaceSSID() ||
87 SSID == getAgentOneAddressSpaceSSID() ||
88 SSID == getSystemOneAddressSpaceSSID();
89 }
90
91public:
92 AMDGPUMachineModuleInfo(const MachineModuleInfo &MMI);
93
94 /// \returns Agent synchronization scope ID (cross address space).
95 SyncScope::ID getAgentSSID() const {
96 return AgentSSID;
97 }
98 /// \returns Workgroup synchronization scope ID (cross address space).
99 SyncScope::ID getWorkgroupSSID() const {
100 return WorkgroupSSID;
101 }
102 /// \returns Wavefront synchronization scope ID (cross address space).
103 SyncScope::ID getWavefrontSSID() const {
104 return WavefrontSSID;
105 }
106 /// \returns Cluster synchronization scope ID (cross address space).
107 SyncScope::ID getClusterSSID() const { return ClusterSSID; }
108 /// \returns System synchronization scope ID (single address space).
109 SyncScope::ID getSystemOneAddressSpaceSSID() const {
110 return SystemOneAddressSpaceSSID;
111 }
112 /// \returns Agent synchronization scope ID (single address space).
113 SyncScope::ID getAgentOneAddressSpaceSSID() const {
114 return AgentOneAddressSpaceSSID;
115 }
116 /// \returns Workgroup synchronization scope ID (single address space).
117 SyncScope::ID getWorkgroupOneAddressSpaceSSID() const {
118 return WorkgroupOneAddressSpaceSSID;
119 }
120 /// \returns Wavefront synchronization scope ID (single address space).
121 SyncScope::ID getWavefrontOneAddressSpaceSSID() const {
122 return WavefrontOneAddressSpaceSSID;
123 }
124 /// \returns Single thread synchronization scope ID (single address space).
125 SyncScope::ID getSingleThreadOneAddressSpaceSSID() const {
126 return SingleThreadOneAddressSpaceSSID;
127 }
128 /// \returns Single thread synchronization scope ID (single address space).
129 SyncScope::ID getClusterOneAddressSpaceSSID() const {
130 return ClusterOneAddressSpaceSSID;
131 }
132
133 /// In AMDGPU target synchronization scopes are inclusive, meaning a
134 /// larger synchronization scope is inclusive of a smaller synchronization
135 /// scope.
136 ///
137 /// \returns True if synchronization scope \p A is larger than or equal to
138 /// synchronization scope \p B, false if synchronization scope \p A is smaller
139 /// than synchronization scope \p B, or "std::nullopt" if either
140 /// synchronization scope \p A or \p B is not supported by the AMDGPU target.
141 std::optional<bool> isSyncScopeInclusion(SyncScope::ID A,
142 SyncScope::ID B) const {
143 const auto &AIO = getSyncScopeInclusionOrdering(SSID: A);
144 const auto &BIO = getSyncScopeInclusionOrdering(SSID: B);
145 if (!AIO || !BIO)
146 return std::nullopt;
147
148 bool IsAOneAddressSpace = isOneAddressSpace(SSID: A);
149 bool IsBOneAddressSpace = isOneAddressSpace(SSID: B);
150
151 return *AIO >= *BIO &&
152 (IsAOneAddressSpace == IsBOneAddressSpace || !IsAOneAddressSpace);
153 }
154};
155
156} // end namespace llvm
157
158#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEMODULEINFO_H
159