1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInstrDesc.h"
14
15namespace llvm {
16
17// This needs to be kept in sync with the field bits in SIRegisterClass.
18enum SIRCFlags : uint8_t {
19 RegTupleAlignUnitsWidth = 2,
20 HasVGPRBit = RegTupleAlignUnitsWidth,
21 HasAGPRBit,
22 HasSGPRbit,
23
24 HasVGPR = 1 << HasVGPRBit,
25 HasAGPR = 1 << HasAGPRBit,
26 HasSGPR = 1 << HasSGPRbit,
27
28 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
29 RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
30}; // enum SIRCFlagsr
31
32namespace SIEncodingFamily {
33// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
34// and the columns of the getMCOpcodeGen table.
35enum {
36 SI = 0,
37 VI = 1,
38 SDWA = 2,
39 SDWA9 = 3,
40 GFX80 = 4,
41 GFX9 = 5,
42 GFX10 = 6,
43 SDWA10 = 7,
44 GFX90A = 8,
45 GFX940 = 9,
46 GFX11 = 10,
47 GFX1170 = 11,
48 GFX12 = 12,
49 GFX1250 = 13,
50 GFX13 = 14,
51};
52}
53
54namespace SIInstrFlags {
55// This needs to be kept in sync with the field bits in InstSI.
56enum : uint64_t {
57 // Low bits - basic encoding information.
58 SALU = 1 << 0,
59 VALU = 1 << 1,
60
61 // SALU instruction formats.
62 SOP1 = 1 << 2,
63 SOP2 = 1 << 3,
64 SOPC = 1 << 4,
65 SOPK = 1 << 5,
66 SOPP = 1 << 6,
67
68 // VALU instruction formats.
69 VOP1 = 1 << 7,
70 VOP2 = 1 << 8,
71 VOPC = 1 << 9,
72
73 // TODO: Should this be spilt into VOP3 a and b?
74 VOP3 = 1 << 10,
75 VOP3P = 1 << 12,
76
77 VINTRP = 1 << 13,
78 SDWA = 1 << 14,
79 DPP = 1 << 15,
80 TRANS = 1 << 16,
81
82 // Memory instruction formats.
83 MUBUF = 1 << 17,
84 MTBUF = 1 << 18,
85 SMRD = 1 << 19,
86 MIMG = 1 << 20,
87 VIMAGE = 1 << 21,
88 VSAMPLE = 1 << 22,
89 EXP = 1 << 23,
90 FLAT = 1 << 24,
91 DS = 1 << 25,
92
93 // Combined SGPR/VGPR Spill bit
94 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill
95 Spill = 1 << 26,
96
97 // LDSDIR instruction format.
98 LDSDIR = 1 << 28,
99
100 // VINTERP instruction format.
101 VINTERP = 1 << 29,
102
103 VOPD3 = 1 << 30,
104
105 // High bits - other information.
106 VM_CNT = UINT64_C(1) << 32,
107 EXP_CNT = UINT64_C(1) << 33,
108 LGKM_CNT = UINT64_C(1) << 34,
109
110 WQM = UINT64_C(1) << 35,
111 DisableWQM = UINT64_C(1) << 36,
112 Gather4 = UINT64_C(1) << 37,
113
114 TENSOR_CNT = UINT64_C(1) << 38,
115
116 SCALAR_STORE = UINT64_C(1) << 39,
117 FIXED_SIZE = UINT64_C(1) << 40,
118
119 ASYNC_CNT = UINT64_C(1) << 41,
120
121 VOP3_OPSEL = UINT64_C(1) << 42,
122 maybeAtomic = UINT64_C(1) << 43,
123 renamedInGFX9 = UINT64_C(1) << 44,
124
125 // Is a clamp on FP type.
126 FPClamp = UINT64_C(1) << 45,
127
128 // Is an integer clamp
129 IntClamp = UINT64_C(1) << 46,
130
131 // Clamps lo component of register.
132 ClampLo = UINT64_C(1) << 47,
133
134 // Clamps hi component of register.
135 // ClampLo and ClampHi set for packed clamp.
136 ClampHi = UINT64_C(1) << 48,
137
138 // Is a packed VOP3P instruction.
139 IsPacked = UINT64_C(1) << 49,
140
141 // Is a D16 buffer instruction.
142 D16Buf = UINT64_C(1) << 50,
143
144 // FLAT instruction accesses FLAT_GLBL segment.
145 FlatGlobal = UINT64_C(1) << 51,
146
147 // Uses floating point double precision rounding mode
148 FPDPRounding = UINT64_C(1) << 52,
149
150 // Instruction is FP atomic.
151 FPAtomic = UINT64_C(1) << 53,
152
153 // Is a MFMA instruction.
154 IsMAI = UINT64_C(1) << 54,
155
156 // Is a DOT instruction.
157 IsDOT = UINT64_C(1) << 55,
158
159 // FLAT instruction accesses FLAT_SCRATCH segment.
160 FlatScratch = UINT64_C(1) << 56,
161
162 // Atomic without return.
163 IsAtomicNoRet = UINT64_C(1) << 57,
164
165 // Atomic with return.
166 IsAtomicRet = UINT64_C(1) << 58,
167
168 // Is a WMMA instruction.
169 IsWMMA = UINT64_C(1) << 59,
170
171 // Whether tied sources will be read.
172 TiedSourceNotRead = UINT64_C(1) << 60,
173
174 // Is never uniform.
175 IsNeverUniform = UINT64_C(1) << 61,
176
177 // ds_gws_* instructions.
178 GWS = UINT64_C(1) << 62,
179
180 // Is a SWMMAC instruction.
181 IsSWMMAC = UINT64_C(1) << 63,
182};
183
184// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
185// The result is true if any of these tests are true.
186enum ClassFlags : unsigned {
187 S_NAN = 1 << 0, // Signaling NaN
188 Q_NAN = 1 << 1, // Quiet NaN
189 N_INFINITY = 1 << 2, // Negative infinity
190 N_NORMAL = 1 << 3, // Negative normal
191 N_SUBNORMAL = 1 << 4, // Negative subnormal
192 N_ZERO = 1 << 5, // Negative zero
193 P_ZERO = 1 << 6, // Positive zero
194 P_SUBNORMAL = 1 << 7, // Positive subnormal
195 P_NORMAL = 1 << 8, // Positive normal
196 P_INFINITY = 1 << 9 // Positive infinity
197};
198}
199
200namespace AMDGPU {
201enum OperandType : unsigned {
202 /// Operands with register, 32-bit, or 64-bit immediate
203 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
204 OPERAND_REG_IMM_INT64,
205 OPERAND_REG_IMM_INT16,
206 OPERAND_REG_IMM_FP32,
207 OPERAND_REG_IMM_FP64,
208 OPERAND_REG_IMM_BF16,
209 OPERAND_REG_IMM_FP16,
210 OPERAND_REG_IMM_V2BF16,
211 OPERAND_REG_IMM_V2FP16,
212 OPERAND_REG_IMM_V2FP16_SPLAT,
213 OPERAND_REG_IMM_V2INT16,
214 OPERAND_REG_IMM_NOINLINE_V2FP16,
215 OPERAND_REG_IMM_V2INT32,
216 OPERAND_REG_IMM_V2FP32,
217
218 /// Operands with register or inline constant
219 OPERAND_REG_INLINE_C_INT16,
220 OPERAND_REG_INLINE_C_INT32,
221 OPERAND_REG_INLINE_C_INT64,
222 OPERAND_REG_INLINE_C_BF16,
223 OPERAND_REG_INLINE_C_FP16,
224 OPERAND_REG_INLINE_C_FP32,
225 OPERAND_REG_INLINE_C_FP64,
226 OPERAND_REG_INLINE_C_V2INT16,
227 OPERAND_REG_INLINE_C_V2BF16,
228 OPERAND_REG_INLINE_C_V2FP16,
229
230 // Operand for split barrier inline constant
231 OPERAND_INLINE_SPLIT_BARRIER_INT32,
232
233 /// Operand with 32-bit immediate that uses the constant bus.
234 OPERAND_KIMM32,
235 OPERAND_KIMM16,
236 OPERAND_KIMM64,
237
238 /// Operands with an AccVGPR register or inline constant
239 OPERAND_REG_INLINE_AC_INT32,
240 OPERAND_REG_INLINE_AC_FP32,
241 OPERAND_REG_INLINE_AC_FP64,
242
243 // Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline
244 // constants. Does not accept registers.
245 OPERAND_INLINE_C_AV64_PSEUDO,
246
247 // Operand for source modifiers for VOP instructions
248 OPERAND_INPUT_MODS,
249
250 // Operand for SDWA instructions
251 OPERAND_SDWA_VOPC_DST,
252
253 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
254 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
255
256 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
257 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,
258
259 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,
260 OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO,
261
262 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
263 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
264
265 OPERAND_KIMM_FIRST = OPERAND_KIMM32,
266 OPERAND_KIMM_LAST = OPERAND_KIMM64
267
268};
269}
270
271// Input operand modifiers bit-masks
272// NEG and SEXT share same bit-mask because they can't be set simultaneously.
273namespace SISrcMods {
274enum : unsigned {
275 NONE = 0,
276 NEG = 1 << 0, // Floating-point negate modifier
277 ABS = 1 << 1, // Floating-point absolute modifier
278 SEXT = 1 << 4, // Integer sign-extend modifier
279 NEG_HI = ABS, // Floating-point negate high packed component modifier.
280 OP_SEL_0 = 1 << 2,
281 OP_SEL_1 = 1 << 3,
282 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
283};
284}
285
286namespace SIOutMods {
287 enum : unsigned {
288 NONE = 0,
289 MUL2 = 1,
290 MUL4 = 2,
291 DIV2 = 3
292 };
293}
294
295namespace AMDGPU {
296namespace VGPRIndexMode {
297
298enum Id : unsigned { // id of symbolic names
299 ID_SRC0 = 0,
300 ID_SRC1,
301 ID_SRC2,
302 ID_DST,
303
304 ID_MIN = ID_SRC0,
305 ID_MAX = ID_DST
306};
307
308enum EncBits : unsigned {
309 OFF = 0,
310 SRC0_ENABLE = 1 << ID_SRC0,
311 SRC1_ENABLE = 1 << ID_SRC1,
312 SRC2_ENABLE = 1 << ID_SRC2,
313 DST_ENABLE = 1 << ID_DST,
314 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
315 UNDEF = 0xFFFF
316};
317
318} // namespace VGPRIndexMode
319} // namespace AMDGPU
320
321namespace AMDGPUAsmVariants {
322 enum : unsigned {
323 DEFAULT = 0,
324 VOP3 = 1,
325 SDWA = 2,
326 SDWA9 = 3,
327 DPP = 4,
328 VOP3_DPP = 5
329 };
330} // namespace AMDGPUAsmVariants
331
332namespace AMDGPU {
333namespace EncValues { // Encoding values of enum9/8/7 operands
334
335enum : unsigned {
336 SGPR_MIN = 0,
337 SGPR_MAX_SI = 101,
338 SGPR_MAX_GFX10 = 105,
339 TTMP_VI_MIN = 112,
340 TTMP_VI_MAX = 123,
341 TTMP_GFX9PLUS_MIN = 108,
342 TTMP_GFX9PLUS_MAX = 123,
343 INLINE_INTEGER_C_MIN = 128,
344 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
345 INLINE_INTEGER_C_MAX = 208,
346 INLINE_FLOATING_C_MIN = 240,
347 INLINE_FLOATING_C_MAX = 248,
348 LITERAL64_CONST = 254,
349 LITERAL_CONST = 255,
350 VGPR_MIN = 256,
351 VGPR_MAX = 511,
352 IS_VGPR = 256, // Indicates VGPR or AGPR
353};
354
355} // namespace EncValues
356
357// Register codes as defined in the TableGen's HWEncoding field.
358namespace HWEncoding {
359enum : unsigned {
360 REG_IDX_MASK = 0x3ff,
361 LO256_REG_IDX_MASK = 0xff,
362 IS_VGPR = 1 << 10,
363 IS_AGPR = 1 << 11,
364 IS_HI16 = 1 << 12,
365};
366} // namespace HWEncoding
367
368namespace CPol {
369
370enum CPol {
371 GLC = 1,
372 SLC = 2,
373 DLC = 4,
374 SCC = 16,
375 SC0 = GLC,
376 SC1 = SCC,
377 NT = SLC,
378 ALL_pregfx12 = GLC | SLC | DLC | SCC,
379 SWZ_pregfx12 = 8,
380
381 // Below are GFX12+ cache policy bits
382
383 // Temporal hint
384 TH = 0x7, // All TH bits
385 TH_RT = 0, // regular
386 TH_NT = 1, // non-temporal
387 TH_HT = 2, // high-temporal
388 TH_LU = 3, // last use
389 TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
390 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
391 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
392 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
393 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)
394 TH_BYPASS = 3, // only to be used with scope = 3
395
396 TH_RESERVED = 7, // unused value for load insts
397
398 // Bits of TH for atomics
399 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
400 TH_ATOMIC_NT = SLC, // Non-temporal vs regular
401 TH_ATOMIC_CASCADE = 4, // Cascading vs regular
402
403 // Scope
404 SCOPE_SHIFT = 3,
405 SCOPE_MASK = 0x3,
406 SCOPE = SCOPE_MASK << SCOPE_SHIFT, // All Scope bits
407 SCOPE_CU = 0 << SCOPE_SHIFT,
408 SCOPE_SE = 1 << SCOPE_SHIFT,
409 SCOPE_DEV = 2 << SCOPE_SHIFT,
410 SCOPE_SYS = 3 << SCOPE_SHIFT,
411
412 NV = 1 << 5, // Non-volatile bit
413
414 SWZ = 1 << 6, // Swizzle bit
415
416 SCAL = 1 << 11, // Scale offset bit
417
418 ALL = TH | SCOPE | NV,
419
420 // Helper bits
421 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy
422 TH_TYPE_STORE = 1 << 8, // TH_STORE policy
423 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy
424 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
425
426 // Volatile (used to preserve/signal operation volatility for buffer
427 // operations not a real instruction bit)
428 VOLATILE = 1 << 31,
429 // The set of "cache policy" bits used for compiler features that
430 // do not correspond to handware features.
431 VIRTUAL_BITS = VOLATILE,
432};
433
434} // namespace CPol
435
436namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
437
438enum Id { // Message ID, width(4) [3:0].
439 ID_INTERRUPT = 1,
440
441 ID_GS_PreGFX11 = 2, // replaced in GFX11
442 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
443
444 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
445 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
446
447 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
448 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12
449 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12
450 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
451 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
452 ID_GS_ALLOC_REQ = 9, // added in GFX9
453 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
454 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
455 ID_SYSMSG = 15,
456
457 ID_RTN_GET_DOORBELL = 128,
458 ID_RTN_GET_DDID = 129,
459 ID_RTN_GET_TMA = 130,
460 ID_RTN_GET_REALTIME = 131,
461 ID_RTN_SAVE_WAVE = 132,
462 ID_RTN_GET_TBA = 133,
463 ID_RTN_GET_TBA_TO_PC = 134,
464 ID_RTN_GET_SE_AID_ID = 135,
465
466 ID_RTN_GET_CLUSTER_BARRIER_STATE = 136, // added in GFX1250
467 ID_RTN_SAVE_WAVE_HAS_TDM = 152, // added in GFX1250
468
469 ID_MASK_PreGFX11_ = 0xF,
470 ID_MASK_GFX11Plus_ = 0xFF
471};
472
473enum Op { // Both GS and SYS operation IDs.
474 OP_SHIFT_ = 4,
475 OP_NONE_ = 0,
476 // Bits used for operation encoding
477 OP_WIDTH_ = 3,
478 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
479 // GS operations are encoded in bits 5:4
480 OP_GS_NOP = 0,
481 OP_GS_CUT = 1,
482 OP_GS_EMIT = 2,
483 OP_GS_EMIT_CUT = 3,
484 OP_GS_FIRST_ = OP_GS_NOP,
485 // SYS operations are encoded in bits 6:4
486 OP_SYS_ECC_ERR_INTERRUPT = 1,
487 OP_SYS_REG_RD = 2,
488 OP_SYS_HOST_TRAP_ACK = 3,
489 OP_SYS_TTRACE_PC = 4,
490 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
491};
492
493enum StreamId : unsigned { // Stream ID, (2) [9:8].
494 STREAM_ID_NONE_ = 0,
495 STREAM_ID_DEFAULT_ = 0,
496 STREAM_ID_LAST_ = 4,
497 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
498 STREAM_ID_SHIFT_ = 8,
499 STREAM_ID_WIDTH_= 2,
500 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
501};
502
503} // namespace SendMsg
504
505namespace WaitEvent { // Encoding of SIMM16 used in s_wait_event
506enum Id {
507 DONT_WAIT_EXPORT_READY = 1 << 0, // Only used in gfx11
508 EXPORT_READY = 1 << 1, // gfx12+
509};
510
511} // namespace WaitEvent
512
513namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
514
515enum Id { // HwRegCode, (6) [5:0]
516 ID_MODE = 1,
517 ID_STATUS = 2,
518 ID_TRAPSTS = 3,
519 ID_HW_ID = 4,
520 ID_GPR_ALLOC = 5,
521 ID_LDS_ALLOC = 6,
522 ID_IB_STS = 7,
523 ID_PERF_SNAPSHOT_DATA_gfx12 = 10,
524 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,
525 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,
526 ID_MEM_BASES = 15,
527 ID_TBA_LO = 16,
528 ID_TBA_HI = 17,
529 ID_TMA_LO = 18,
530 ID_TMA_HI = 19,
531 ID_FLAT_SCR_LO = 20,
532 ID_FLAT_SCR_HI = 21,
533 ID_XNACK_MASK = 22,
534 ID_HW_ID1 = 23,
535 ID_HW_ID2 = 24,
536 ID_POPS_PACKER = 25,
537 ID_SCHED_MODE = 26,
538 ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
539 ID_IB_STS2 = 28,
540 ID_SHADER_CYCLES = 29,
541 ID_SHADER_CYCLES_HI = 30,
542 ID_DVGPR_ALLOC_LO = 31,
543 ID_DVGPR_ALLOC_HI = 32,
544
545 // Register numbers reused in GFX11
546 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,
547 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,
548
549 // Register numbers reused in GFX12+
550 ID_STATE_PRIV = 4,
551 ID_PERF_SNAPSHOT_DATA1 = 15,
552 ID_PERF_SNAPSHOT_DATA2 = 16,
553 ID_EXCP_FLAG_PRIV = 17,
554 ID_EXCP_FLAG_USER = 18,
555 ID_TRAP_CTRL = 19,
556
557 // GFX94* specific registers
558 ID_XCC_ID = 20,
559 ID_SQ_PERF_SNAPSHOT_DATA = 21,
560 ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
561 ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
562 ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
563
564 // GFX1250
565 ID_XNACK_STATE_PRIV = 33,
566 ID_XNACK_MASK_gfx1250 = 34,
567};
568
569enum Offset : unsigned { // Offset, (5) [10:6]
570 OFFSET_MEM_VIOL = 8,
571 OFFSET_ME_ID = 8, // in HW_ID2
572};
573
574enum ModeRegisterMasks : uint32_t {
575 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
576 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
577 DX10_CLAMP_MASK = 1 << 8,
578 IEEE_MODE_MASK = 1 << 9,
579 LOD_CLAMP_MASK = 1 << 10,
580 DEBUG_MASK = 1 << 11,
581
582 // EXCP_EN fields.
583 EXCP_EN_INVALID_MASK = 1 << 12,
584 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
585 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
586 EXCP_EN_OVERFLOW_MASK = 1 << 15,
587 EXCP_EN_UNDERFLOW_MASK = 1 << 16,
588 EXCP_EN_INEXACT_MASK = 1 << 17,
589 EXCP_EN_INT_DIV0_MASK = 1 << 18,
590
591 GPR_IDX_EN_MASK = 1 << 27,
592 VSKIP_MASK = 1 << 28,
593 CSP_MASK = 0x7u << 29, // Bits 29..31
594
595 // GFX1250
596 DST_VGPR_MSB = 0x3 << 12,
597 SRC0_VGPR_MSB = 0x3 << 14,
598 SRC1_VGPR_MSB = 0x3 << 16,
599 SRC2_VGPR_MSB = 0x3 << 18,
600 VGPR_MSB_MASK = 0xff << 12, // Bits 12..19
601
602 REPLAY_MODE = 1 << 25,
603 FLAT_SCRATCH_IS_NV = 1 << 26,
604};
605
606} // namespace Hwreg
607
608namespace MTBUFFormat {
609
610enum DataFormat : int64_t {
611 DFMT_INVALID = 0,
612 DFMT_8,
613 DFMT_16,
614 DFMT_8_8,
615 DFMT_32,
616 DFMT_16_16,
617 DFMT_10_11_11,
618 DFMT_11_11_10,
619 DFMT_10_10_10_2,
620 DFMT_2_10_10_10,
621 DFMT_8_8_8_8,
622 DFMT_32_32,
623 DFMT_16_16_16_16,
624 DFMT_32_32_32,
625 DFMT_32_32_32_32,
626 DFMT_RESERVED_15,
627
628 DFMT_MIN = DFMT_INVALID,
629 DFMT_MAX = DFMT_RESERVED_15,
630
631 DFMT_UNDEF = -1,
632 DFMT_DEFAULT = DFMT_8,
633
634 DFMT_SHIFT = 0,
635 DFMT_MASK = 0xF
636};
637
638enum NumFormat : int64_t {
639 NFMT_UNORM = 0,
640 NFMT_SNORM,
641 NFMT_USCALED,
642 NFMT_SSCALED,
643 NFMT_UINT,
644 NFMT_SINT,
645 NFMT_RESERVED_6, // VI and GFX9
646 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
647 NFMT_FLOAT,
648
649 NFMT_MIN = NFMT_UNORM,
650 NFMT_MAX = NFMT_FLOAT,
651
652 NFMT_UNDEF = -1,
653 NFMT_DEFAULT = NFMT_UNORM,
654
655 NFMT_SHIFT = 4,
656 NFMT_MASK = 7
657};
658
659enum MergedFormat : int64_t {
660 DFMT_NFMT_UNDEF = -1,
661 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
662 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
663
664
665 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
666
667 DFMT_NFMT_MAX = DFMT_NFMT_MASK
668};
669
670enum UnifiedFormatCommon : int64_t {
671 UFMT_MAX = 127,
672 UFMT_UNDEF = -1,
673 UFMT_DEFAULT = 1
674};
675
676} // namespace MTBUFFormat
677
678namespace UfmtGFX10 {
679enum UnifiedFormat : int64_t {
680 UFMT_INVALID = 0,
681
682 UFMT_8_UNORM,
683 UFMT_8_SNORM,
684 UFMT_8_USCALED,
685 UFMT_8_SSCALED,
686 UFMT_8_UINT,
687 UFMT_8_SINT,
688
689 UFMT_16_UNORM,
690 UFMT_16_SNORM,
691 UFMT_16_USCALED,
692 UFMT_16_SSCALED,
693 UFMT_16_UINT,
694 UFMT_16_SINT,
695 UFMT_16_FLOAT,
696
697 UFMT_8_8_UNORM,
698 UFMT_8_8_SNORM,
699 UFMT_8_8_USCALED,
700 UFMT_8_8_SSCALED,
701 UFMT_8_8_UINT,
702 UFMT_8_8_SINT,
703
704 UFMT_32_UINT,
705 UFMT_32_SINT,
706 UFMT_32_FLOAT,
707
708 UFMT_16_16_UNORM,
709 UFMT_16_16_SNORM,
710 UFMT_16_16_USCALED,
711 UFMT_16_16_SSCALED,
712 UFMT_16_16_UINT,
713 UFMT_16_16_SINT,
714 UFMT_16_16_FLOAT,
715
716 UFMT_10_11_11_UNORM,
717 UFMT_10_11_11_SNORM,
718 UFMT_10_11_11_USCALED,
719 UFMT_10_11_11_SSCALED,
720 UFMT_10_11_11_UINT,
721 UFMT_10_11_11_SINT,
722 UFMT_10_11_11_FLOAT,
723
724 UFMT_11_11_10_UNORM,
725 UFMT_11_11_10_SNORM,
726 UFMT_11_11_10_USCALED,
727 UFMT_11_11_10_SSCALED,
728 UFMT_11_11_10_UINT,
729 UFMT_11_11_10_SINT,
730 UFMT_11_11_10_FLOAT,
731
732 UFMT_10_10_10_2_UNORM,
733 UFMT_10_10_10_2_SNORM,
734 UFMT_10_10_10_2_USCALED,
735 UFMT_10_10_10_2_SSCALED,
736 UFMT_10_10_10_2_UINT,
737 UFMT_10_10_10_2_SINT,
738
739 UFMT_2_10_10_10_UNORM,
740 UFMT_2_10_10_10_SNORM,
741 UFMT_2_10_10_10_USCALED,
742 UFMT_2_10_10_10_SSCALED,
743 UFMT_2_10_10_10_UINT,
744 UFMT_2_10_10_10_SINT,
745
746 UFMT_8_8_8_8_UNORM,
747 UFMT_8_8_8_8_SNORM,
748 UFMT_8_8_8_8_USCALED,
749 UFMT_8_8_8_8_SSCALED,
750 UFMT_8_8_8_8_UINT,
751 UFMT_8_8_8_8_SINT,
752
753 UFMT_32_32_UINT,
754 UFMT_32_32_SINT,
755 UFMT_32_32_FLOAT,
756
757 UFMT_16_16_16_16_UNORM,
758 UFMT_16_16_16_16_SNORM,
759 UFMT_16_16_16_16_USCALED,
760 UFMT_16_16_16_16_SSCALED,
761 UFMT_16_16_16_16_UINT,
762 UFMT_16_16_16_16_SINT,
763 UFMT_16_16_16_16_FLOAT,
764
765 UFMT_32_32_32_UINT,
766 UFMT_32_32_32_SINT,
767 UFMT_32_32_32_FLOAT,
768 UFMT_32_32_32_32_UINT,
769 UFMT_32_32_32_32_SINT,
770 UFMT_32_32_32_32_FLOAT,
771
772 UFMT_FIRST = UFMT_INVALID,
773 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
774};
775
776} // namespace UfmtGFX10
777
778namespace UfmtGFX11 {
779enum UnifiedFormat : int64_t {
780 UFMT_INVALID = 0,
781
782 UFMT_8_UNORM,
783 UFMT_8_SNORM,
784 UFMT_8_USCALED,
785 UFMT_8_SSCALED,
786 UFMT_8_UINT,
787 UFMT_8_SINT,
788
789 UFMT_16_UNORM,
790 UFMT_16_SNORM,
791 UFMT_16_USCALED,
792 UFMT_16_SSCALED,
793 UFMT_16_UINT,
794 UFMT_16_SINT,
795 UFMT_16_FLOAT,
796
797 UFMT_8_8_UNORM,
798 UFMT_8_8_SNORM,
799 UFMT_8_8_USCALED,
800 UFMT_8_8_SSCALED,
801 UFMT_8_8_UINT,
802 UFMT_8_8_SINT,
803
804 UFMT_32_UINT,
805 UFMT_32_SINT,
806 UFMT_32_FLOAT,
807
808 UFMT_16_16_UNORM,
809 UFMT_16_16_SNORM,
810 UFMT_16_16_USCALED,
811 UFMT_16_16_SSCALED,
812 UFMT_16_16_UINT,
813 UFMT_16_16_SINT,
814 UFMT_16_16_FLOAT,
815
816 UFMT_10_11_11_FLOAT,
817
818 UFMT_11_11_10_FLOAT,
819
820 UFMT_10_10_10_2_UNORM,
821 UFMT_10_10_10_2_SNORM,
822 UFMT_10_10_10_2_UINT,
823 UFMT_10_10_10_2_SINT,
824
825 UFMT_2_10_10_10_UNORM,
826 UFMT_2_10_10_10_SNORM,
827 UFMT_2_10_10_10_USCALED,
828 UFMT_2_10_10_10_SSCALED,
829 UFMT_2_10_10_10_UINT,
830 UFMT_2_10_10_10_SINT,
831
832 UFMT_8_8_8_8_UNORM,
833 UFMT_8_8_8_8_SNORM,
834 UFMT_8_8_8_8_USCALED,
835 UFMT_8_8_8_8_SSCALED,
836 UFMT_8_8_8_8_UINT,
837 UFMT_8_8_8_8_SINT,
838
839 UFMT_32_32_UINT,
840 UFMT_32_32_SINT,
841 UFMT_32_32_FLOAT,
842
843 UFMT_16_16_16_16_UNORM,
844 UFMT_16_16_16_16_SNORM,
845 UFMT_16_16_16_16_USCALED,
846 UFMT_16_16_16_16_SSCALED,
847 UFMT_16_16_16_16_UINT,
848 UFMT_16_16_16_16_SINT,
849 UFMT_16_16_16_16_FLOAT,
850
851 UFMT_32_32_32_UINT,
852 UFMT_32_32_32_SINT,
853 UFMT_32_32_32_FLOAT,
854 UFMT_32_32_32_32_UINT,
855 UFMT_32_32_32_32_SINT,
856 UFMT_32_32_32_32_FLOAT,
857
858 UFMT_FIRST = UFMT_INVALID,
859 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
860};
861
862} // namespace UfmtGFX11
863
864namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
865
866enum Id : unsigned { // id of symbolic names
867 ID_QUAD_PERM = 0,
868 ID_BITMASK_PERM,
869 ID_SWAP,
870 ID_REVERSE,
871 ID_BROADCAST,
872 ID_FFT,
873 ID_ROTATE
874};
875
876// clang-format off
877enum EncBits : unsigned {
878
879 // swizzle mode encodings
880
881 QUAD_PERM_ENC = 0x8000,
882 QUAD_PERM_ENC_MASK = 0xFF00,
883
884 BITMASK_PERM_ENC = 0x0000,
885 BITMASK_PERM_ENC_MASK = 0x8000,
886
887 FFT_MODE_ENC = 0xE000,
888
889 ROTATE_MODE_ENC = 0xC000,
890 FFT_ROTATE_MODE_MASK = 0xF000,
891
892 ROTATE_MODE_LO = 0xC000,
893 FFT_MODE_LO = 0xE000,
894
895 // QUAD_PERM encodings
896
897 LANE_MASK = 0x3,
898 LANE_MAX = LANE_MASK,
899 LANE_SHIFT = 2,
900 LANE_NUM = 4,
901
902 // BITMASK_PERM encodings
903
904 BITMASK_MASK = 0x1F,
905 BITMASK_MAX = BITMASK_MASK,
906 BITMASK_WIDTH = 5,
907
908 BITMASK_AND_SHIFT = 0,
909 BITMASK_OR_SHIFT = 5,
910 BITMASK_XOR_SHIFT = 10,
911
912 // FFT encodings
913
914 FFT_SWIZZLE_MASK = 0x1F,
915 FFT_SWIZZLE_MAX = 0x1F,
916
917 // ROTATE encodings
918 ROTATE_MAX_SIZE = 0x1F,
919 ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
920 ROTATE_DIR_MASK = 0x1,
921 ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
922 ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
923};
924// clang-format on
925
926} // namespace Swizzle
927
928namespace SDWA {
929
930enum SdwaSel : unsigned {
931 BYTE_0 = 0,
932 BYTE_1 = 1,
933 BYTE_2 = 2,
934 BYTE_3 = 3,
935 WORD_0 = 4,
936 WORD_1 = 5,
937 DWORD = 6,
938};
939
940enum DstUnused : unsigned {
941 UNUSED_PAD = 0,
942 UNUSED_SEXT = 1,
943 UNUSED_PRESERVE = 2,
944};
945
946enum SDWA9EncValues : unsigned {
947 SRC_SGPR_MASK = 0x100,
948 SRC_VGPR_MASK = 0xFF,
949 VOPC_DST_VCC_MASK = 0x80,
950 VOPC_DST_SGPR_MASK = 0x7F,
951
952 SRC_VGPR_MIN = 0,
953 SRC_VGPR_MAX = 255,
954 SRC_SGPR_MIN = 256,
955 SRC_SGPR_MAX_SI = 357,
956 SRC_SGPR_MAX_GFX10 = 361,
957 SRC_TTMP_MIN = 364,
958 SRC_TTMP_MAX = 379,
959};
960
961} // namespace SDWA
962
963namespace DPP {
964
965// clang-format off
966enum DppCtrl : unsigned {
967 QUAD_PERM_FIRST = 0,
968 QUAD_PERM_ID = 0xE4, // identity permutation
969 QUAD_PERM_LAST = 0xFF,
970 DPP_UNUSED1 = 0x100,
971 ROW_SHL0 = 0x100,
972 ROW_SHL_FIRST = 0x101,
973 ROW_SHL_LAST = 0x10F,
974 DPP_UNUSED2 = 0x110,
975 ROW_SHR0 = 0x110,
976 ROW_SHR_FIRST = 0x111,
977 ROW_SHR_LAST = 0x11F,
978 DPP_UNUSED3 = 0x120,
979 ROW_ROR0 = 0x120,
980 ROW_ROR_FIRST = 0x121,
981 ROW_ROR_LAST = 0x12F,
982 WAVE_SHL1 = 0x130,
983 DPP_UNUSED4_FIRST = 0x131,
984 DPP_UNUSED4_LAST = 0x133,
985 WAVE_ROL1 = 0x134,
986 DPP_UNUSED5_FIRST = 0x135,
987 DPP_UNUSED5_LAST = 0x137,
988 WAVE_SHR1 = 0x138,
989 DPP_UNUSED6_FIRST = 0x139,
990 DPP_UNUSED6_LAST = 0x13B,
991 WAVE_ROR1 = 0x13C,
992 DPP_UNUSED7_FIRST = 0x13D,
993 DPP_UNUSED7_LAST = 0x13F,
994 ROW_MIRROR = 0x140,
995 ROW_HALF_MIRROR = 0x141,
996 BCAST15 = 0x142,
997 BCAST31 = 0x143,
998 DPP_UNUSED8_FIRST = 0x144,
999 DPP_UNUSED8_LAST = 0x14F,
1000 ROW_NEWBCAST_FIRST= 0x150,
1001 ROW_NEWBCAST_LAST = 0x15F,
1002 ROW_SHARE0 = 0x150,
1003 ROW_SHARE_FIRST = 0x150,
1004 ROW_SHARE_LAST = 0x15F,
1005 ROW_XMASK0 = 0x160,
1006 ROW_XMASK_FIRST = 0x160,
1007 ROW_XMASK_LAST = 0x16F,
1008 DPP_LAST = ROW_XMASK_LAST
1009};
1010// clang-format on
1011
1012enum DppFiMode {
1013 DPP_FI_0 = 0,
1014 DPP_FI_1 = 1,
1015 DPP8_FI_0 = 0xE9,
1016 DPP8_FI_1 = 0xEA,
1017};
1018
1019} // namespace DPP
1020
1021namespace Exp {
1022
1023enum Target : unsigned {
1024 ET_MRT0 = 0,
1025 ET_MRT7 = 7,
1026 ET_MRTZ = 8,
1027 ET_NULL = 9, // Pre-GFX11
1028 ET_POS0 = 12,
1029 ET_POS3 = 15,
1030 ET_POS4 = 16, // GFX10+
1031 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
1032 ET_PRIM = 20, // GFX10+
1033 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
1034 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
1035 ET_PARAM0 = 32, // Pre-GFX11
1036 ET_PARAM31 = 63, // Pre-GFX11
1037
1038 ET_NULL_MAX_IDX = 0,
1039 ET_MRTZ_MAX_IDX = 0,
1040 ET_PRIM_MAX_IDX = 0,
1041 ET_MRT_MAX_IDX = 7,
1042 ET_POS_MAX_IDX = 4,
1043 ET_DUAL_SRC_BLEND_MAX_IDX = 1,
1044 ET_PARAM_MAX_IDX = 31,
1045
1046 ET_INVALID = 255,
1047};
1048
1049} // namespace Exp
1050
1051namespace WMMA {
1052enum MatrixFMT : unsigned {
1053 MATRIX_FMT_FP8 = 0,
1054 MATRIX_FMT_BF8 = 1,
1055 MATRIX_FMT_FP6 = 2,
1056 MATRIX_FMT_BF6 = 3,
1057 MATRIX_FMT_FP4 = 4
1058};
1059
1060enum MatrixScale : unsigned {
1061 MATRIX_SCALE_ROW0 = 0,
1062 MATRIX_SCALE_ROW1 = 1,
1063};
1064
1065enum MatrixScaleFmt : unsigned {
1066 MATRIX_SCALE_FMT_E8 = 0,
1067 MATRIX_SCALE_FMT_E5M3 = 1,
1068 MATRIX_SCALE_FMT_E4M3 = 2
1069};
1070} // namespace WMMA
1071
1072namespace VOP3PEncoding {
1073
1074enum OpSel : uint64_t {
1075 OP_SEL_HI_0 = UINT64_C(1) << 59,
1076 OP_SEL_HI_1 = UINT64_C(1) << 60,
1077 OP_SEL_HI_2 = UINT64_C(1) << 14,
1078};
1079
1080} // namespace VOP3PEncoding
1081
1082namespace ImplicitArg {
1083// Implicit kernel argument offset for code object version 5.
1084enum Offset_COV5 : unsigned {
1085 HOSTCALL_PTR_OFFSET = 80,
1086 MULTIGRID_SYNC_ARG_OFFSET = 88,
1087 HEAP_PTR_OFFSET = 96,
1088
1089 DEFAULT_QUEUE_OFFSET = 104,
1090 COMPLETION_ACTION_OFFSET = 112,
1091
1092 PRIVATE_BASE_OFFSET = 192,
1093 SHARED_BASE_OFFSET = 196,
1094 QUEUE_PTR_OFFSET = 200,
1095};
1096
1097} // namespace ImplicitArg
1098
1099namespace MFMAScaleFormats {
1100// Enum value used in cbsz/blgp for F8F6F4 MFMA operations to select the matrix
1101// format.
1102enum MFMAScaleFormats {
1103 FP8_E4M3 = 0,
1104 FP8_E5M2 = 1,
1105 FP6_E2M3 = 2,
1106 FP6_E3M2 = 3,
1107 FP4_E2M1 = 4
1108};
1109} // namespace MFMAScaleFormats
1110
1111namespace VirtRegFlag {
1112// Virtual register flags used for various target specific handlings during
1113// codegen.
1114enum Register_Flag : uint8_t {
1115 // Register operand in a whole-wave mode operation.
1116 WWM_REG = 1 << 0,
1117};
1118
1119} // namespace VirtRegFlag
1120
1121} // namespace AMDGPU
1122
1123namespace AMDGPU {
1124namespace Barrier {
1125
1126enum Type {
1127 CLUSTER_TRAP = -4,
1128 CLUSTER = -3,
1129 TRAP = -2,
1130 WORKGROUP = -1,
1131 NAMED_BARRIER_FIRST = 1,
1132 NAMED_BARRIER_LAST = 16,
1133};
1134
1135enum {
1136 BARRIER_SCOPE_WORKGROUP = 0,
1137};
1138
1139} // namespace Barrier
1140} // namespace AMDGPU
1141
1142// clang-format off
1143
1144#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1145#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1146#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1147#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1148#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1149#define C_00B028_MEM_ORDERED 0xFDFFFFFF
1150
1151#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1152#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1153#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1154#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1155#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1156#define C_00B128_MEM_ORDERED 0xF7FFFFFF
1157
1158#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1159#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1160#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1161#define C_00B228_WGP_MODE 0xF7FFFFFF
1162#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1163#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1164#define C_00B228_MEM_ORDERED 0xFDFFFFFF
1165
1166#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1167#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1168#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1169#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1170#define C_00B428_WGP_MODE 0xFBFFFFFF
1171#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1172#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1173#define C_00B428_MEM_ORDERED 0xFEFFFFFF
1174
1175#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1176
1177#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1178#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1179#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1180#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1181#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1182#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1183#define C_00B84C_USER_SGPR 0xFFFFFFC1
1184#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1185#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1186#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1187#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1188#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1189#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1190#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1191#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1192#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1193#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1194#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1195#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1196#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1197#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1198#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1199#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1200#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1201#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1202/* CIK */
1203#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1204#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1205#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1206/* */
1207#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1208#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1209#define C_00B84C_LDS_SIZE 0xFF007FFF
1210#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1211#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1212#define C_00B84C_EXCP_EN 0x80FFFFFF
1213
1214#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1215#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1216
1217#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1218#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1219#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1220#define C_00B848_VGPRS 0xFFFFFFC0
1221#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1222#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1223#define C_00B848_SGPRS 0xFFFFFC3F
1224#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1225#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1226#define C_00B848_PRIORITY 0xFFFFF3FF
1227#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1228#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1229#define C_00B848_FLOAT_MODE 0xFFF00FFF
1230#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1231#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1232#define C_00B848_PRIV 0xFFEFFFFF
1233#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1234#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1235#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1236#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1237#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1238#define C_00B848_RR_WG_MODE 0xFFDFFFFF
1239#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1240#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1241#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1242#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1243#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1244#define C_00B848_IEEE_MODE 0xFF7FFFFF
1245#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1246#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1247#define C_00B848_WGP_MODE 0xDFFFFFFF
1248#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1249#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1250#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1251#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1252#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1253#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1254
1255// Helpers for setting FLOAT_MODE
1256#define FP_ROUND_ROUND_TO_NEAREST 0
1257#define FP_ROUND_ROUND_TO_INF 1
1258#define FP_ROUND_ROUND_TO_NEGINF 2
1259#define FP_ROUND_ROUND_TO_ZERO 3
1260
1261// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1262// precision.
1263#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1264#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1265
1266#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1267#define FP_DENORM_FLUSH_OUT 1
1268#define FP_DENORM_FLUSH_IN 2
1269#define FP_DENORM_FLUSH_NONE 3
1270
1271
1272// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1273// precision.
1274#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1275#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1276
1277#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1278#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1279#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1280#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1281
1282#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1283#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1284#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1285#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1286
1287#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1288#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1289#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1290#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1291#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1292#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1293#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1294#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1295
1296#define R_SPILLED_SGPRS 0x4
1297#define R_SPILLED_VGPRS 0x8
1298
1299// clang-format on
1300
1301} // End namespace llvm
1302
1303#endif
1304