1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInstrDesc.h"
14
15namespace llvm {
16
17// This needs to be kept in sync with the field bits in SIRegisterClass.
18enum SIRCFlags : uint8_t {
19 RegTupleAlignUnitsWidth = 2,
20 HasVGPRBit = RegTupleAlignUnitsWidth,
21 HasAGPRBit,
22 HasSGPRbit,
23
24 HasVGPR = 1 << HasVGPRBit,
25 HasAGPR = 1 << HasAGPRBit,
26 HasSGPR = 1 << HasSGPRbit,
27
28 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
29 RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
30}; // enum SIRCFlagsr
31
32namespace SIEncodingFamily {
33// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
34// and the columns of the getMCOpcodeGen table.
35enum {
36 SI = 0,
37 VI = 1,
38 SDWA = 2,
39 SDWA9 = 3,
40 GFX80 = 4,
41 GFX9 = 5,
42 GFX10 = 6,
43 SDWA10 = 7,
44 GFX90A = 8,
45 GFX940 = 9,
46 GFX11 = 10,
47 GFX12 = 11,
48 GFX1250 = 12,
49 GFX13 = 13,
50};
51}
52
53namespace SIInstrFlags {
54// This needs to be kept in sync with the field bits in InstSI.
55enum : uint64_t {
56 // Low bits - basic encoding information.
57 SALU = 1 << 0,
58 VALU = 1 << 1,
59
60 // SALU instruction formats.
61 SOP1 = 1 << 2,
62 SOP2 = 1 << 3,
63 SOPC = 1 << 4,
64 SOPK = 1 << 5,
65 SOPP = 1 << 6,
66
67 // VALU instruction formats.
68 VOP1 = 1 << 7,
69 VOP2 = 1 << 8,
70 VOPC = 1 << 9,
71
72 // TODO: Should this be spilt into VOP3 a and b?
73 VOP3 = 1 << 10,
74 VOP3P = 1 << 12,
75
76 VINTRP = 1 << 13,
77 SDWA = 1 << 14,
78 DPP = 1 << 15,
79 TRANS = 1 << 16,
80
81 // Memory instruction formats.
82 MUBUF = 1 << 17,
83 MTBUF = 1 << 18,
84 SMRD = 1 << 19,
85 MIMG = 1 << 20,
86 VIMAGE = 1 << 21,
87 VSAMPLE = 1 << 22,
88 EXP = 1 << 23,
89 FLAT = 1 << 24,
90 DS = 1 << 25,
91
92 // Combined SGPR/VGPR Spill bit
93 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill
94 Spill = 1 << 26,
95
96 // LDSDIR instruction format.
97 LDSDIR = 1 << 28,
98
99 // VINTERP instruction format.
100 VINTERP = 1 << 29,
101
102 VOPD3 = 1 << 30,
103
104 // High bits - other information.
105 VM_CNT = UINT64_C(1) << 32,
106 EXP_CNT = UINT64_C(1) << 33,
107 LGKM_CNT = UINT64_C(1) << 34,
108
109 WQM = UINT64_C(1) << 35,
110 DisableWQM = UINT64_C(1) << 36,
111 Gather4 = UINT64_C(1) << 37,
112
113 TENSOR_CNT = UINT64_C(1) << 38,
114
115 SCALAR_STORE = UINT64_C(1) << 39,
116 FIXED_SIZE = UINT64_C(1) << 40,
117
118 ASYNC_CNT = UINT64_C(1) << 41,
119
120 VOP3_OPSEL = UINT64_C(1) << 42,
121 maybeAtomic = UINT64_C(1) << 43,
122 renamedInGFX9 = UINT64_C(1) << 44,
123
124 // Is a clamp on FP type.
125 FPClamp = UINT64_C(1) << 45,
126
127 // Is an integer clamp
128 IntClamp = UINT64_C(1) << 46,
129
130 // Clamps lo component of register.
131 ClampLo = UINT64_C(1) << 47,
132
133 // Clamps hi component of register.
134 // ClampLo and ClampHi set for packed clamp.
135 ClampHi = UINT64_C(1) << 48,
136
137 // Is a packed VOP3P instruction.
138 IsPacked = UINT64_C(1) << 49,
139
140 // Is a D16 buffer instruction.
141 D16Buf = UINT64_C(1) << 50,
142
143 // FLAT instruction accesses FLAT_GLBL segment.
144 FlatGlobal = UINT64_C(1) << 51,
145
146 // Uses floating point double precision rounding mode
147 FPDPRounding = UINT64_C(1) << 52,
148
149 // Instruction is FP atomic.
150 FPAtomic = UINT64_C(1) << 53,
151
152 // Is a MFMA instruction.
153 IsMAI = UINT64_C(1) << 54,
154
155 // Is a DOT instruction.
156 IsDOT = UINT64_C(1) << 55,
157
158 // FLAT instruction accesses FLAT_SCRATCH segment.
159 FlatScratch = UINT64_C(1) << 56,
160
161 // Atomic without return.
162 IsAtomicNoRet = UINT64_C(1) << 57,
163
164 // Atomic with return.
165 IsAtomicRet = UINT64_C(1) << 58,
166
167 // Is a WMMA instruction.
168 IsWMMA = UINT64_C(1) << 59,
169
170 // Whether tied sources will be read.
171 TiedSourceNotRead = UINT64_C(1) << 60,
172
173 // Is never uniform.
174 IsNeverUniform = UINT64_C(1) << 61,
175
176 // ds_gws_* instructions.
177 GWS = UINT64_C(1) << 62,
178
179 // Is a SWMMAC instruction.
180 IsSWMMAC = UINT64_C(1) << 63,
181};
182
183// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
184// The result is true if any of these tests are true.
185enum ClassFlags : unsigned {
186 S_NAN = 1 << 0, // Signaling NaN
187 Q_NAN = 1 << 1, // Quiet NaN
188 N_INFINITY = 1 << 2, // Negative infinity
189 N_NORMAL = 1 << 3, // Negative normal
190 N_SUBNORMAL = 1 << 4, // Negative subnormal
191 N_ZERO = 1 << 5, // Negative zero
192 P_ZERO = 1 << 6, // Positive zero
193 P_SUBNORMAL = 1 << 7, // Positive subnormal
194 P_NORMAL = 1 << 8, // Positive normal
195 P_INFINITY = 1 << 9 // Positive infinity
196};
197}
198
199namespace AMDGPU {
200enum OperandType : unsigned {
201 /// Operands with register, 32-bit, or 64-bit immediate
202 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
203 OPERAND_REG_IMM_INT64,
204 OPERAND_REG_IMM_INT16,
205 OPERAND_REG_IMM_FP32,
206 OPERAND_REG_IMM_FP64,
207 OPERAND_REG_IMM_BF16,
208 OPERAND_REG_IMM_FP16,
209 OPERAND_REG_IMM_V2BF16,
210 OPERAND_REG_IMM_V2FP16,
211 OPERAND_REG_IMM_V2FP16_SPLAT,
212 OPERAND_REG_IMM_V2INT16,
213 OPERAND_REG_IMM_NOINLINE_V2FP16,
214 OPERAND_REG_IMM_V2INT32,
215 OPERAND_REG_IMM_V2FP32,
216
217 /// Operands with register or inline constant
218 OPERAND_REG_INLINE_C_INT16,
219 OPERAND_REG_INLINE_C_INT32,
220 OPERAND_REG_INLINE_C_INT64,
221 OPERAND_REG_INLINE_C_BF16,
222 OPERAND_REG_INLINE_C_FP16,
223 OPERAND_REG_INLINE_C_FP32,
224 OPERAND_REG_INLINE_C_FP64,
225 OPERAND_REG_INLINE_C_V2INT16,
226 OPERAND_REG_INLINE_C_V2BF16,
227 OPERAND_REG_INLINE_C_V2FP16,
228
229 // Operand for split barrier inline constant
230 OPERAND_INLINE_SPLIT_BARRIER_INT32,
231
232 /// Operand with 32-bit immediate that uses the constant bus.
233 OPERAND_KIMM32,
234 OPERAND_KIMM16,
235 OPERAND_KIMM64,
236
237 /// Operands with an AccVGPR register or inline constant
238 OPERAND_REG_INLINE_AC_INT32,
239 OPERAND_REG_INLINE_AC_FP32,
240 OPERAND_REG_INLINE_AC_FP64,
241
242 // Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline
243 // constants. Does not accept registers.
244 OPERAND_INLINE_C_AV64_PSEUDO,
245
246 // Operand for source modifiers for VOP instructions
247 OPERAND_INPUT_MODS,
248
249 // Operand for SDWA instructions
250 OPERAND_SDWA_VOPC_DST,
251
252 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
253 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
254
255 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
256 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,
257
258 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,
259 OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO,
260
261 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
262 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
263
264 OPERAND_KIMM_FIRST = OPERAND_KIMM32,
265 OPERAND_KIMM_LAST = OPERAND_KIMM64
266
267};
268}
269
270// Input operand modifiers bit-masks
271// NEG and SEXT share same bit-mask because they can't be set simultaneously.
272namespace SISrcMods {
273enum : unsigned {
274 NONE = 0,
275 NEG = 1 << 0, // Floating-point negate modifier
276 ABS = 1 << 1, // Floating-point absolute modifier
277 SEXT = 1 << 4, // Integer sign-extend modifier
278 NEG_HI = ABS, // Floating-point negate high packed component modifier.
279 OP_SEL_0 = 1 << 2,
280 OP_SEL_1 = 1 << 3,
281 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
282};
283}
284
285namespace SIOutMods {
286 enum : unsigned {
287 NONE = 0,
288 MUL2 = 1,
289 MUL4 = 2,
290 DIV2 = 3
291 };
292}
293
294namespace AMDGPU {
295namespace VGPRIndexMode {
296
297enum Id : unsigned { // id of symbolic names
298 ID_SRC0 = 0,
299 ID_SRC1,
300 ID_SRC2,
301 ID_DST,
302
303 ID_MIN = ID_SRC0,
304 ID_MAX = ID_DST
305};
306
307enum EncBits : unsigned {
308 OFF = 0,
309 SRC0_ENABLE = 1 << ID_SRC0,
310 SRC1_ENABLE = 1 << ID_SRC1,
311 SRC2_ENABLE = 1 << ID_SRC2,
312 DST_ENABLE = 1 << ID_DST,
313 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
314 UNDEF = 0xFFFF
315};
316
317} // namespace VGPRIndexMode
318} // namespace AMDGPU
319
320namespace AMDGPUAsmVariants {
321 enum : unsigned {
322 DEFAULT = 0,
323 VOP3 = 1,
324 SDWA = 2,
325 SDWA9 = 3,
326 DPP = 4,
327 VOP3_DPP = 5
328 };
329} // namespace AMDGPUAsmVariants
330
331namespace AMDGPU {
332namespace EncValues { // Encoding values of enum9/8/7 operands
333
334enum : unsigned {
335 SGPR_MIN = 0,
336 SGPR_MAX_SI = 101,
337 SGPR_MAX_GFX10 = 105,
338 TTMP_VI_MIN = 112,
339 TTMP_VI_MAX = 123,
340 TTMP_GFX9PLUS_MIN = 108,
341 TTMP_GFX9PLUS_MAX = 123,
342 INLINE_INTEGER_C_MIN = 128,
343 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
344 INLINE_INTEGER_C_MAX = 208,
345 INLINE_FLOATING_C_MIN = 240,
346 INLINE_FLOATING_C_MAX = 248,
347 LITERAL64_CONST = 254,
348 LITERAL_CONST = 255,
349 VGPR_MIN = 256,
350 VGPR_MAX = 511,
351 IS_VGPR = 256, // Indicates VGPR or AGPR
352};
353
354} // namespace EncValues
355
356// Register codes as defined in the TableGen's HWEncoding field.
357namespace HWEncoding {
358enum : unsigned {
359 REG_IDX_MASK = 0x3ff,
360 LO256_REG_IDX_MASK = 0xff,
361 IS_VGPR = 1 << 10,
362 IS_AGPR = 1 << 11,
363 IS_HI16 = 1 << 12,
364};
365} // namespace HWEncoding
366
367namespace CPol {
368
369enum CPol {
370 GLC = 1,
371 SLC = 2,
372 DLC = 4,
373 SCC = 16,
374 SC0 = GLC,
375 SC1 = SCC,
376 NT = SLC,
377 ALL_pregfx12 = GLC | SLC | DLC | SCC,
378 SWZ_pregfx12 = 8,
379
380 // Below are GFX12+ cache policy bits
381
382 // Temporal hint
383 TH = 0x7, // All TH bits
384 TH_RT = 0, // regular
385 TH_NT = 1, // non-temporal
386 TH_HT = 2, // high-temporal
387 TH_LU = 3, // last use
388 TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
389 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
390 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
391 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
392 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)
393 TH_BYPASS = 3, // only to be used with scope = 3
394
395 TH_RESERVED = 7, // unused value for load insts
396
397 // Bits of TH for atomics
398 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
399 TH_ATOMIC_NT = SLC, // Non-temporal vs regular
400 TH_ATOMIC_CASCADE = 4, // Cascading vs regular
401
402 // Scope
403 SCOPE_SHIFT = 3,
404 SCOPE_MASK = 0x3,
405 SCOPE = SCOPE_MASK << SCOPE_SHIFT, // All Scope bits
406 SCOPE_CU = 0 << SCOPE_SHIFT,
407 SCOPE_SE = 1 << SCOPE_SHIFT,
408 SCOPE_DEV = 2 << SCOPE_SHIFT,
409 SCOPE_SYS = 3 << SCOPE_SHIFT,
410
411 NV = 1 << 5, // Non-volatile bit
412
413 SWZ = 1 << 6, // Swizzle bit
414
415 SCAL = 1 << 11, // Scale offset bit
416
417 ALL = TH | SCOPE | NV,
418
419 // Helper bits
420 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy
421 TH_TYPE_STORE = 1 << 8, // TH_STORE policy
422 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy
423 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
424
425 // Volatile (used to preserve/signal operation volatility for buffer
426 // operations not a real instruction bit)
427 VOLATILE = 1 << 31,
428 // The set of "cache policy" bits used for compiler features that
429 // do not correspond to handware features.
430 VIRTUAL_BITS = VOLATILE,
431};
432
433} // namespace CPol
434
435namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
436
437enum Id { // Message ID, width(4) [3:0].
438 ID_INTERRUPT = 1,
439
440 ID_GS_PreGFX11 = 2, // replaced in GFX11
441 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
442
443 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
444 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
445
446 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
447 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12
448 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12
449 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
450 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
451 ID_GS_ALLOC_REQ = 9, // added in GFX9
452 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
453 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
454 ID_SYSMSG = 15,
455
456 ID_RTN_GET_DOORBELL = 128,
457 ID_RTN_GET_DDID = 129,
458 ID_RTN_GET_TMA = 130,
459 ID_RTN_GET_REALTIME = 131,
460 ID_RTN_SAVE_WAVE = 132,
461 ID_RTN_GET_TBA = 133,
462 ID_RTN_GET_TBA_TO_PC = 134,
463 ID_RTN_GET_SE_AID_ID = 135,
464
465 ID_RTN_GET_CLUSTER_BARRIER_STATE = 136, // added in GFX1250
466 ID_RTN_SAVE_WAVE_HAS_TDM = 152, // added in GFX1250
467
468 ID_MASK_PreGFX11_ = 0xF,
469 ID_MASK_GFX11Plus_ = 0xFF
470};
471
472enum Op { // Both GS and SYS operation IDs.
473 OP_SHIFT_ = 4,
474 OP_NONE_ = 0,
475 // Bits used for operation encoding
476 OP_WIDTH_ = 3,
477 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
478 // GS operations are encoded in bits 5:4
479 OP_GS_NOP = 0,
480 OP_GS_CUT = 1,
481 OP_GS_EMIT = 2,
482 OP_GS_EMIT_CUT = 3,
483 OP_GS_FIRST_ = OP_GS_NOP,
484 // SYS operations are encoded in bits 6:4
485 OP_SYS_ECC_ERR_INTERRUPT = 1,
486 OP_SYS_REG_RD = 2,
487 OP_SYS_HOST_TRAP_ACK = 3,
488 OP_SYS_TTRACE_PC = 4,
489 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
490};
491
492enum StreamId : unsigned { // Stream ID, (2) [9:8].
493 STREAM_ID_NONE_ = 0,
494 STREAM_ID_DEFAULT_ = 0,
495 STREAM_ID_LAST_ = 4,
496 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
497 STREAM_ID_SHIFT_ = 8,
498 STREAM_ID_WIDTH_= 2,
499 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
500};
501
502} // namespace SendMsg
503
504namespace WaitEvent { // Encoding of SIMM16 used in s_wait_event
505enum Id {
506 DONT_WAIT_EXPORT_READY = 1 << 0, // Only used in gfx11
507 EXPORT_READY = 1 << 1, // gfx12+
508};
509
510} // namespace WaitEvent
511
512namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
513
514enum Id { // HwRegCode, (6) [5:0]
515 ID_MODE = 1,
516 ID_STATUS = 2,
517 ID_TRAPSTS = 3,
518 ID_HW_ID = 4,
519 ID_GPR_ALLOC = 5,
520 ID_LDS_ALLOC = 6,
521 ID_IB_STS = 7,
522 ID_PERF_SNAPSHOT_DATA_gfx12 = 10,
523 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,
524 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,
525 ID_MEM_BASES = 15,
526 ID_TBA_LO = 16,
527 ID_TBA_HI = 17,
528 ID_TMA_LO = 18,
529 ID_TMA_HI = 19,
530 ID_FLAT_SCR_LO = 20,
531 ID_FLAT_SCR_HI = 21,
532 ID_XNACK_MASK = 22,
533 ID_HW_ID1 = 23,
534 ID_HW_ID2 = 24,
535 ID_POPS_PACKER = 25,
536 ID_SCHED_MODE = 26,
537 ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
538 ID_IB_STS2 = 28,
539 ID_SHADER_CYCLES = 29,
540 ID_SHADER_CYCLES_HI = 30,
541 ID_DVGPR_ALLOC_LO = 31,
542 ID_DVGPR_ALLOC_HI = 32,
543
544 // Register numbers reused in GFX11
545 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,
546 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,
547
548 // Register numbers reused in GFX12+
549 ID_STATE_PRIV = 4,
550 ID_PERF_SNAPSHOT_DATA1 = 15,
551 ID_PERF_SNAPSHOT_DATA2 = 16,
552 ID_EXCP_FLAG_PRIV = 17,
553 ID_EXCP_FLAG_USER = 18,
554 ID_TRAP_CTRL = 19,
555
556 // GFX94* specific registers
557 ID_XCC_ID = 20,
558 ID_SQ_PERF_SNAPSHOT_DATA = 21,
559 ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
560 ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
561 ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
562
563 // GFX1250
564 ID_XNACK_STATE_PRIV = 33,
565 ID_XNACK_MASK_gfx1250 = 34,
566};
567
568enum Offset : unsigned { // Offset, (5) [10:6]
569 OFFSET_MEM_VIOL = 8,
570 OFFSET_ME_ID = 8, // in HW_ID2
571};
572
573enum ModeRegisterMasks : uint32_t {
574 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
575 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
576 DX10_CLAMP_MASK = 1 << 8,
577 IEEE_MODE_MASK = 1 << 9,
578 LOD_CLAMP_MASK = 1 << 10,
579 DEBUG_MASK = 1 << 11,
580
581 // EXCP_EN fields.
582 EXCP_EN_INVALID_MASK = 1 << 12,
583 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
584 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
585 EXCP_EN_OVERFLOW_MASK = 1 << 15,
586 EXCP_EN_UNDERFLOW_MASK = 1 << 16,
587 EXCP_EN_INEXACT_MASK = 1 << 17,
588 EXCP_EN_INT_DIV0_MASK = 1 << 18,
589
590 GPR_IDX_EN_MASK = 1 << 27,
591 VSKIP_MASK = 1 << 28,
592 CSP_MASK = 0x7u << 29, // Bits 29..31
593
594 // GFX1250
595 DST_VGPR_MSB = 0x3 << 12,
596 SRC0_VGPR_MSB = 0x3 << 14,
597 SRC1_VGPR_MSB = 0x3 << 16,
598 SRC2_VGPR_MSB = 0x3 << 18,
599 VGPR_MSB_MASK = 0xff << 12, // Bits 12..19
600
601 REPLAY_MODE = 1 << 25,
602 FLAT_SCRATCH_IS_NV = 1 << 26,
603};
604
605} // namespace Hwreg
606
607namespace MTBUFFormat {
608
609enum DataFormat : int64_t {
610 DFMT_INVALID = 0,
611 DFMT_8,
612 DFMT_16,
613 DFMT_8_8,
614 DFMT_32,
615 DFMT_16_16,
616 DFMT_10_11_11,
617 DFMT_11_11_10,
618 DFMT_10_10_10_2,
619 DFMT_2_10_10_10,
620 DFMT_8_8_8_8,
621 DFMT_32_32,
622 DFMT_16_16_16_16,
623 DFMT_32_32_32,
624 DFMT_32_32_32_32,
625 DFMT_RESERVED_15,
626
627 DFMT_MIN = DFMT_INVALID,
628 DFMT_MAX = DFMT_RESERVED_15,
629
630 DFMT_UNDEF = -1,
631 DFMT_DEFAULT = DFMT_8,
632
633 DFMT_SHIFT = 0,
634 DFMT_MASK = 0xF
635};
636
637enum NumFormat : int64_t {
638 NFMT_UNORM = 0,
639 NFMT_SNORM,
640 NFMT_USCALED,
641 NFMT_SSCALED,
642 NFMT_UINT,
643 NFMT_SINT,
644 NFMT_RESERVED_6, // VI and GFX9
645 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
646 NFMT_FLOAT,
647
648 NFMT_MIN = NFMT_UNORM,
649 NFMT_MAX = NFMT_FLOAT,
650
651 NFMT_UNDEF = -1,
652 NFMT_DEFAULT = NFMT_UNORM,
653
654 NFMT_SHIFT = 4,
655 NFMT_MASK = 7
656};
657
658enum MergedFormat : int64_t {
659 DFMT_NFMT_UNDEF = -1,
660 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
661 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
662
663
664 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
665
666 DFMT_NFMT_MAX = DFMT_NFMT_MASK
667};
668
669enum UnifiedFormatCommon : int64_t {
670 UFMT_MAX = 127,
671 UFMT_UNDEF = -1,
672 UFMT_DEFAULT = 1
673};
674
675} // namespace MTBUFFormat
676
677namespace UfmtGFX10 {
678enum UnifiedFormat : int64_t {
679 UFMT_INVALID = 0,
680
681 UFMT_8_UNORM,
682 UFMT_8_SNORM,
683 UFMT_8_USCALED,
684 UFMT_8_SSCALED,
685 UFMT_8_UINT,
686 UFMT_8_SINT,
687
688 UFMT_16_UNORM,
689 UFMT_16_SNORM,
690 UFMT_16_USCALED,
691 UFMT_16_SSCALED,
692 UFMT_16_UINT,
693 UFMT_16_SINT,
694 UFMT_16_FLOAT,
695
696 UFMT_8_8_UNORM,
697 UFMT_8_8_SNORM,
698 UFMT_8_8_USCALED,
699 UFMT_8_8_SSCALED,
700 UFMT_8_8_UINT,
701 UFMT_8_8_SINT,
702
703 UFMT_32_UINT,
704 UFMT_32_SINT,
705 UFMT_32_FLOAT,
706
707 UFMT_16_16_UNORM,
708 UFMT_16_16_SNORM,
709 UFMT_16_16_USCALED,
710 UFMT_16_16_SSCALED,
711 UFMT_16_16_UINT,
712 UFMT_16_16_SINT,
713 UFMT_16_16_FLOAT,
714
715 UFMT_10_11_11_UNORM,
716 UFMT_10_11_11_SNORM,
717 UFMT_10_11_11_USCALED,
718 UFMT_10_11_11_SSCALED,
719 UFMT_10_11_11_UINT,
720 UFMT_10_11_11_SINT,
721 UFMT_10_11_11_FLOAT,
722
723 UFMT_11_11_10_UNORM,
724 UFMT_11_11_10_SNORM,
725 UFMT_11_11_10_USCALED,
726 UFMT_11_11_10_SSCALED,
727 UFMT_11_11_10_UINT,
728 UFMT_11_11_10_SINT,
729 UFMT_11_11_10_FLOAT,
730
731 UFMT_10_10_10_2_UNORM,
732 UFMT_10_10_10_2_SNORM,
733 UFMT_10_10_10_2_USCALED,
734 UFMT_10_10_10_2_SSCALED,
735 UFMT_10_10_10_2_UINT,
736 UFMT_10_10_10_2_SINT,
737
738 UFMT_2_10_10_10_UNORM,
739 UFMT_2_10_10_10_SNORM,
740 UFMT_2_10_10_10_USCALED,
741 UFMT_2_10_10_10_SSCALED,
742 UFMT_2_10_10_10_UINT,
743 UFMT_2_10_10_10_SINT,
744
745 UFMT_8_8_8_8_UNORM,
746 UFMT_8_8_8_8_SNORM,
747 UFMT_8_8_8_8_USCALED,
748 UFMT_8_8_8_8_SSCALED,
749 UFMT_8_8_8_8_UINT,
750 UFMT_8_8_8_8_SINT,
751
752 UFMT_32_32_UINT,
753 UFMT_32_32_SINT,
754 UFMT_32_32_FLOAT,
755
756 UFMT_16_16_16_16_UNORM,
757 UFMT_16_16_16_16_SNORM,
758 UFMT_16_16_16_16_USCALED,
759 UFMT_16_16_16_16_SSCALED,
760 UFMT_16_16_16_16_UINT,
761 UFMT_16_16_16_16_SINT,
762 UFMT_16_16_16_16_FLOAT,
763
764 UFMT_32_32_32_UINT,
765 UFMT_32_32_32_SINT,
766 UFMT_32_32_32_FLOAT,
767 UFMT_32_32_32_32_UINT,
768 UFMT_32_32_32_32_SINT,
769 UFMT_32_32_32_32_FLOAT,
770
771 UFMT_FIRST = UFMT_INVALID,
772 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
773};
774
775} // namespace UfmtGFX10
776
777namespace UfmtGFX11 {
778enum UnifiedFormat : int64_t {
779 UFMT_INVALID = 0,
780
781 UFMT_8_UNORM,
782 UFMT_8_SNORM,
783 UFMT_8_USCALED,
784 UFMT_8_SSCALED,
785 UFMT_8_UINT,
786 UFMT_8_SINT,
787
788 UFMT_16_UNORM,
789 UFMT_16_SNORM,
790 UFMT_16_USCALED,
791 UFMT_16_SSCALED,
792 UFMT_16_UINT,
793 UFMT_16_SINT,
794 UFMT_16_FLOAT,
795
796 UFMT_8_8_UNORM,
797 UFMT_8_8_SNORM,
798 UFMT_8_8_USCALED,
799 UFMT_8_8_SSCALED,
800 UFMT_8_8_UINT,
801 UFMT_8_8_SINT,
802
803 UFMT_32_UINT,
804 UFMT_32_SINT,
805 UFMT_32_FLOAT,
806
807 UFMT_16_16_UNORM,
808 UFMT_16_16_SNORM,
809 UFMT_16_16_USCALED,
810 UFMT_16_16_SSCALED,
811 UFMT_16_16_UINT,
812 UFMT_16_16_SINT,
813 UFMT_16_16_FLOAT,
814
815 UFMT_10_11_11_FLOAT,
816
817 UFMT_11_11_10_FLOAT,
818
819 UFMT_10_10_10_2_UNORM,
820 UFMT_10_10_10_2_SNORM,
821 UFMT_10_10_10_2_UINT,
822 UFMT_10_10_10_2_SINT,
823
824 UFMT_2_10_10_10_UNORM,
825 UFMT_2_10_10_10_SNORM,
826 UFMT_2_10_10_10_USCALED,
827 UFMT_2_10_10_10_SSCALED,
828 UFMT_2_10_10_10_UINT,
829 UFMT_2_10_10_10_SINT,
830
831 UFMT_8_8_8_8_UNORM,
832 UFMT_8_8_8_8_SNORM,
833 UFMT_8_8_8_8_USCALED,
834 UFMT_8_8_8_8_SSCALED,
835 UFMT_8_8_8_8_UINT,
836 UFMT_8_8_8_8_SINT,
837
838 UFMT_32_32_UINT,
839 UFMT_32_32_SINT,
840 UFMT_32_32_FLOAT,
841
842 UFMT_16_16_16_16_UNORM,
843 UFMT_16_16_16_16_SNORM,
844 UFMT_16_16_16_16_USCALED,
845 UFMT_16_16_16_16_SSCALED,
846 UFMT_16_16_16_16_UINT,
847 UFMT_16_16_16_16_SINT,
848 UFMT_16_16_16_16_FLOAT,
849
850 UFMT_32_32_32_UINT,
851 UFMT_32_32_32_SINT,
852 UFMT_32_32_32_FLOAT,
853 UFMT_32_32_32_32_UINT,
854 UFMT_32_32_32_32_SINT,
855 UFMT_32_32_32_32_FLOAT,
856
857 UFMT_FIRST = UFMT_INVALID,
858 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
859};
860
861} // namespace UfmtGFX11
862
863namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
864
865enum Id : unsigned { // id of symbolic names
866 ID_QUAD_PERM = 0,
867 ID_BITMASK_PERM,
868 ID_SWAP,
869 ID_REVERSE,
870 ID_BROADCAST,
871 ID_FFT,
872 ID_ROTATE
873};
874
875// clang-format off
876enum EncBits : unsigned {
877
878 // swizzle mode encodings
879
880 QUAD_PERM_ENC = 0x8000,
881 QUAD_PERM_ENC_MASK = 0xFF00,
882
883 BITMASK_PERM_ENC = 0x0000,
884 BITMASK_PERM_ENC_MASK = 0x8000,
885
886 FFT_MODE_ENC = 0xE000,
887
888 ROTATE_MODE_ENC = 0xC000,
889 FFT_ROTATE_MODE_MASK = 0xF000,
890
891 ROTATE_MODE_LO = 0xC000,
892 FFT_MODE_LO = 0xE000,
893
894 // QUAD_PERM encodings
895
896 LANE_MASK = 0x3,
897 LANE_MAX = LANE_MASK,
898 LANE_SHIFT = 2,
899 LANE_NUM = 4,
900
901 // BITMASK_PERM encodings
902
903 BITMASK_MASK = 0x1F,
904 BITMASK_MAX = BITMASK_MASK,
905 BITMASK_WIDTH = 5,
906
907 BITMASK_AND_SHIFT = 0,
908 BITMASK_OR_SHIFT = 5,
909 BITMASK_XOR_SHIFT = 10,
910
911 // FFT encodings
912
913 FFT_SWIZZLE_MASK = 0x1F,
914 FFT_SWIZZLE_MAX = 0x1F,
915
916 // ROTATE encodings
917 ROTATE_MAX_SIZE = 0x1F,
918 ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
919 ROTATE_DIR_MASK = 0x1,
920 ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
921 ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
922};
923// clang-format on
924
925} // namespace Swizzle
926
927namespace SDWA {
928
929enum SdwaSel : unsigned {
930 BYTE_0 = 0,
931 BYTE_1 = 1,
932 BYTE_2 = 2,
933 BYTE_3 = 3,
934 WORD_0 = 4,
935 WORD_1 = 5,
936 DWORD = 6,
937};
938
939enum DstUnused : unsigned {
940 UNUSED_PAD = 0,
941 UNUSED_SEXT = 1,
942 UNUSED_PRESERVE = 2,
943};
944
945enum SDWA9EncValues : unsigned {
946 SRC_SGPR_MASK = 0x100,
947 SRC_VGPR_MASK = 0xFF,
948 VOPC_DST_VCC_MASK = 0x80,
949 VOPC_DST_SGPR_MASK = 0x7F,
950
951 SRC_VGPR_MIN = 0,
952 SRC_VGPR_MAX = 255,
953 SRC_SGPR_MIN = 256,
954 SRC_SGPR_MAX_SI = 357,
955 SRC_SGPR_MAX_GFX10 = 361,
956 SRC_TTMP_MIN = 364,
957 SRC_TTMP_MAX = 379,
958};
959
960} // namespace SDWA
961
962namespace DPP {
963
964// clang-format off
965enum DppCtrl : unsigned {
966 QUAD_PERM_FIRST = 0,
967 QUAD_PERM_ID = 0xE4, // identity permutation
968 QUAD_PERM_LAST = 0xFF,
969 DPP_UNUSED1 = 0x100,
970 ROW_SHL0 = 0x100,
971 ROW_SHL_FIRST = 0x101,
972 ROW_SHL_LAST = 0x10F,
973 DPP_UNUSED2 = 0x110,
974 ROW_SHR0 = 0x110,
975 ROW_SHR_FIRST = 0x111,
976 ROW_SHR_LAST = 0x11F,
977 DPP_UNUSED3 = 0x120,
978 ROW_ROR0 = 0x120,
979 ROW_ROR_FIRST = 0x121,
980 ROW_ROR_LAST = 0x12F,
981 WAVE_SHL1 = 0x130,
982 DPP_UNUSED4_FIRST = 0x131,
983 DPP_UNUSED4_LAST = 0x133,
984 WAVE_ROL1 = 0x134,
985 DPP_UNUSED5_FIRST = 0x135,
986 DPP_UNUSED5_LAST = 0x137,
987 WAVE_SHR1 = 0x138,
988 DPP_UNUSED6_FIRST = 0x139,
989 DPP_UNUSED6_LAST = 0x13B,
990 WAVE_ROR1 = 0x13C,
991 DPP_UNUSED7_FIRST = 0x13D,
992 DPP_UNUSED7_LAST = 0x13F,
993 ROW_MIRROR = 0x140,
994 ROW_HALF_MIRROR = 0x141,
995 BCAST15 = 0x142,
996 BCAST31 = 0x143,
997 DPP_UNUSED8_FIRST = 0x144,
998 DPP_UNUSED8_LAST = 0x14F,
999 ROW_NEWBCAST_FIRST= 0x150,
1000 ROW_NEWBCAST_LAST = 0x15F,
1001 ROW_SHARE0 = 0x150,
1002 ROW_SHARE_FIRST = 0x150,
1003 ROW_SHARE_LAST = 0x15F,
1004 ROW_XMASK0 = 0x160,
1005 ROW_XMASK_FIRST = 0x160,
1006 ROW_XMASK_LAST = 0x16F,
1007 DPP_LAST = ROW_XMASK_LAST
1008};
1009// clang-format on
1010
1011enum DppFiMode {
1012 DPP_FI_0 = 0,
1013 DPP_FI_1 = 1,
1014 DPP8_FI_0 = 0xE9,
1015 DPP8_FI_1 = 0xEA,
1016};
1017
1018} // namespace DPP
1019
1020namespace Exp {
1021
1022enum Target : unsigned {
1023 ET_MRT0 = 0,
1024 ET_MRT7 = 7,
1025 ET_MRTZ = 8,
1026 ET_NULL = 9, // Pre-GFX11
1027 ET_POS0 = 12,
1028 ET_POS3 = 15,
1029 ET_POS4 = 16, // GFX10+
1030 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
1031 ET_PRIM = 20, // GFX10+
1032 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
1033 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
1034 ET_PARAM0 = 32, // Pre-GFX11
1035 ET_PARAM31 = 63, // Pre-GFX11
1036
1037 ET_NULL_MAX_IDX = 0,
1038 ET_MRTZ_MAX_IDX = 0,
1039 ET_PRIM_MAX_IDX = 0,
1040 ET_MRT_MAX_IDX = 7,
1041 ET_POS_MAX_IDX = 4,
1042 ET_DUAL_SRC_BLEND_MAX_IDX = 1,
1043 ET_PARAM_MAX_IDX = 31,
1044
1045 ET_INVALID = 255,
1046};
1047
1048} // namespace Exp
1049
1050namespace WMMA {
1051enum MatrixFMT : unsigned {
1052 MATRIX_FMT_FP8 = 0,
1053 MATRIX_FMT_BF8 = 1,
1054 MATRIX_FMT_FP6 = 2,
1055 MATRIX_FMT_BF6 = 3,
1056 MATRIX_FMT_FP4 = 4
1057};
1058
1059enum MatrixScale : unsigned {
1060 MATRIX_SCALE_ROW0 = 0,
1061 MATRIX_SCALE_ROW1 = 1,
1062};
1063
1064enum MatrixScaleFmt : unsigned {
1065 MATRIX_SCALE_FMT_E8 = 0,
1066 MATRIX_SCALE_FMT_E5M3 = 1,
1067 MATRIX_SCALE_FMT_E4M3 = 2
1068};
1069} // namespace WMMA
1070
1071namespace VOP3PEncoding {
1072
1073enum OpSel : uint64_t {
1074 OP_SEL_HI_0 = UINT64_C(1) << 59,
1075 OP_SEL_HI_1 = UINT64_C(1) << 60,
1076 OP_SEL_HI_2 = UINT64_C(1) << 14,
1077};
1078
1079} // namespace VOP3PEncoding
1080
1081namespace ImplicitArg {
1082// Implicit kernel argument offset for code object version 5.
1083enum Offset_COV5 : unsigned {
1084 HOSTCALL_PTR_OFFSET = 80,
1085 MULTIGRID_SYNC_ARG_OFFSET = 88,
1086 HEAP_PTR_OFFSET = 96,
1087
1088 DEFAULT_QUEUE_OFFSET = 104,
1089 COMPLETION_ACTION_OFFSET = 112,
1090
1091 PRIVATE_BASE_OFFSET = 192,
1092 SHARED_BASE_OFFSET = 196,
1093 QUEUE_PTR_OFFSET = 200,
1094};
1095
1096} // namespace ImplicitArg
1097
1098namespace MFMAScaleFormats {
1099// Enum value used in cbsz/blgp for F8F6F4 MFMA operations to select the matrix
1100// format.
1101enum MFMAScaleFormats {
1102 FP8_E4M3 = 0,
1103 FP8_E5M2 = 1,
1104 FP6_E2M3 = 2,
1105 FP6_E3M2 = 3,
1106 FP4_E2M1 = 4
1107};
1108} // namespace MFMAScaleFormats
1109
1110namespace VirtRegFlag {
1111// Virtual register flags used for various target specific handlings during
1112// codegen.
1113enum Register_Flag : uint8_t {
1114 // Register operand in a whole-wave mode operation.
1115 WWM_REG = 1 << 0,
1116};
1117
1118} // namespace VirtRegFlag
1119
1120} // namespace AMDGPU
1121
1122namespace AMDGPU {
1123namespace Barrier {
1124
1125enum Type {
1126 CLUSTER_TRAP = -4,
1127 CLUSTER = -3,
1128 TRAP = -2,
1129 WORKGROUP = -1,
1130 NAMED_BARRIER_FIRST = 1,
1131 NAMED_BARRIER_LAST = 16,
1132};
1133
1134enum {
1135 BARRIER_SCOPE_WORKGROUP = 0,
1136};
1137
1138} // namespace Barrier
1139} // namespace AMDGPU
1140
1141// clang-format off
1142
1143#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1144#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1145#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1146#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1147#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1148#define C_00B028_MEM_ORDERED 0xFDFFFFFF
1149
1150#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1151#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1152#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1153#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1154#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1155#define C_00B128_MEM_ORDERED 0xF7FFFFFF
1156
1157#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1158#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1159#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1160#define C_00B228_WGP_MODE 0xF7FFFFFF
1161#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1162#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1163#define C_00B228_MEM_ORDERED 0xFDFFFFFF
1164
1165#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1166#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1167#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1168#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1169#define C_00B428_WGP_MODE 0xFBFFFFFF
1170#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1171#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1172#define C_00B428_MEM_ORDERED 0xFEFFFFFF
1173
1174#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1175
1176#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1177#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1178#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1179#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1180#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1181#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1182#define C_00B84C_USER_SGPR 0xFFFFFFC1
1183#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1184#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1185#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1186#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1187#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1188#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1189#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1190#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1191#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1192#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1193#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1194#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1195#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1196#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1197#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1198#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1199#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1200#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1201/* CIK */
1202#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1203#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1204#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1205/* */
1206#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1207#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1208#define C_00B84C_LDS_SIZE 0xFF007FFF
1209#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1210#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1211#define C_00B84C_EXCP_EN 0x80FFFFFF
1212
1213#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1214#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1215
1216#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1217#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1218#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1219#define C_00B848_VGPRS 0xFFFFFFC0
1220#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1221#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1222#define C_00B848_SGPRS 0xFFFFFC3F
1223#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1224#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1225#define C_00B848_PRIORITY 0xFFFFF3FF
1226#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1227#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1228#define C_00B848_FLOAT_MODE 0xFFF00FFF
1229#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1230#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1231#define C_00B848_PRIV 0xFFEFFFFF
1232#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1233#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1234#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1235#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1236#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1237#define C_00B848_RR_WG_MODE 0xFFDFFFFF
1238#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1239#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1240#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1241#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1242#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1243#define C_00B848_IEEE_MODE 0xFF7FFFFF
1244#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1245#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1246#define C_00B848_WGP_MODE 0xDFFFFFFF
1247#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1248#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1249#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1250#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1251#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1252#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1253
1254// Helpers for setting FLOAT_MODE
1255#define FP_ROUND_ROUND_TO_NEAREST 0
1256#define FP_ROUND_ROUND_TO_INF 1
1257#define FP_ROUND_ROUND_TO_NEGINF 2
1258#define FP_ROUND_ROUND_TO_ZERO 3
1259
1260// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1261// precision.
1262#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1263#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1264
1265#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1266#define FP_DENORM_FLUSH_OUT 1
1267#define FP_DENORM_FLUSH_IN 2
1268#define FP_DENORM_FLUSH_NONE 3
1269
1270
1271// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1272// precision.
1273#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1274#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1275
1276#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1277#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1278#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1279#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1280
1281#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1282#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1283#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1284#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1285
1286#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1287#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1288#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1289#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1290#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1291#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1292#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1293#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1294
1295#define R_SPILLED_SGPRS 0x4
1296#define R_SPILLED_VGPRS 0x8
1297
1298// clang-format on
1299
1300} // End namespace llvm
1301
1302#endif
1303