1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInst.h"
14#include "llvm/MC/MCInstrDesc.h"
15#include "llvm/MC/MCInstrInfo.h"
16#include "llvm/Support/AMDGPUAddrSpace.h"
17
18namespace llvm {
19
20// This needs to be kept in sync with the field bits in SIRegisterClass.
21enum SIRCFlags : uint8_t {
22 RegTupleAlignUnitsWidth = 2,
23 HasVGPRBit = RegTupleAlignUnitsWidth,
24 HasAGPRBit,
25 HasSGPRbit,
26
27 HasVGPR = 1 << HasVGPRBit,
28 HasAGPR = 1 << HasAGPRBit,
29 HasSGPR = 1 << HasSGPRbit,
30
31 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
32 RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
33}; // enum SIRCFlagsr
34
35namespace SIEncodingFamily {
36// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
37// and the columns of the getMCOpcodeGen table.
38enum {
39 SI = 0,
40 VI = 1,
41 SDWA = 2,
42 SDWA9 = 3,
43 GFX80 = 4,
44 GFX9 = 5,
45 GFX10 = 6,
46 SDWA10 = 7,
47 GFX90A = 8,
48 GFX940 = 9,
49 GFX11 = 10,
50 GFX1170 = 11,
51 GFX12 = 12,
52 GFX1250 = 13,
53 GFX13 = 14,
54};
55}
56
57namespace SIInstrFlags {
58// This needs to be kept in sync with the field bits in InstSI.
59enum : uint64_t {
60 // Low bits - basic encoding information.
61 SALU = 1 << 0,
62 VALU = 1 << 1,
63
64 // SALU instruction formats.
65 SOP1 = 1 << 2,
66 SOP2 = 1 << 3,
67 SOPC = 1 << 4,
68 SOPK = 1 << 5,
69 SOPP = 1 << 6,
70
71 // VALU instruction formats.
72 VOP1 = 1 << 7,
73 VOP2 = 1 << 8,
74 VOPC = 1 << 9,
75
76 // TODO: Should this be spilt into VOP3 a and b?
77 VOP3 = 1 << 10,
78 VOP3P = 1 << 12,
79
80 VINTRP = 1 << 13,
81 SDWA = 1 << 14,
82 DPP = 1 << 15,
83 TRANS = 1 << 16,
84
85 // Memory instruction formats.
86 MUBUF = 1 << 17,
87 MTBUF = 1 << 18,
88 SMRD = 1 << 19,
89 MIMG = 1 << 20,
90 VIMAGE = 1 << 21,
91 VSAMPLE = 1 << 22,
92 EXP = 1 << 23,
93 FLAT = 1 << 24,
94 DS = 1 << 25,
95
96 // Combined SGPR/VGPR Spill bit
97 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill
98 Spill = 1 << 26,
99
100 // LDSDIR instruction format.
101 LDSDIR = 1 << 28,
102
103 // VINTERP instruction format.
104 VINTERP = 1 << 29,
105
106 VOPD3 = 1 << 30,
107
108 // High bits - other information.
109 VM_CNT = UINT64_C(1) << 32,
110 EXP_CNT = UINT64_C(1) << 33,
111 LGKM_CNT = UINT64_C(1) << 34,
112
113 WQM = UINT64_C(1) << 35,
114 DisableWQM = UINT64_C(1) << 36,
115 Gather4 = UINT64_C(1) << 37,
116
117 TENSOR_CNT = UINT64_C(1) << 38,
118
119 SCALAR_STORE = UINT64_C(1) << 39,
120 FIXED_SIZE = UINT64_C(1) << 40,
121
122 ASYNC_CNT = UINT64_C(1) << 41,
123
124 VOP3_OPSEL = UINT64_C(1) << 42,
125 maybeAtomic = UINT64_C(1) << 43,
126 renamedInGFX9 = UINT64_C(1) << 44,
127
128 // Is a clamp on FP type.
129 FPClamp = UINT64_C(1) << 45,
130
131 // Is an integer clamp
132 IntClamp = UINT64_C(1) << 46,
133
134 // Clamps lo component of register.
135 ClampLo = UINT64_C(1) << 47,
136
137 // Clamps hi component of register.
138 // ClampLo and ClampHi set for packed clamp.
139 ClampHi = UINT64_C(1) << 48,
140
141 // Is a packed VOP3P instruction.
142 IsPacked = UINT64_C(1) << 49,
143
144 // Is a D16 buffer instruction.
145 D16Buf = UINT64_C(1) << 50,
146
147 // FLAT instruction accesses FLAT_GLBL segment.
148 FlatGlobal = UINT64_C(1) << 51,
149
150 // Uses floating point double precision rounding mode
151 FPDPRounding = UINT64_C(1) << 52,
152
153 // Instruction is FP atomic.
154 FPAtomic = UINT64_C(1) << 53,
155
156 // Is a MFMA instruction.
157 IsMAI = UINT64_C(1) << 54,
158
159 // Is a DOT instruction.
160 IsDOT = UINT64_C(1) << 55,
161
162 // FLAT instruction accesses FLAT_SCRATCH segment.
163 FlatScratch = UINT64_C(1) << 56,
164
165 // Atomic without return.
166 IsAtomicNoRet = UINT64_C(1) << 57,
167
168 // Atomic with return.
169 IsAtomicRet = UINT64_C(1) << 58,
170
171 // Is a WMMA instruction.
172 IsWMMA = UINT64_C(1) << 59,
173
174 // Whether tied sources will be read.
175 TiedSourceNotRead = UINT64_C(1) << 60,
176
177 // Is never uniform.
178 IsNeverUniform = UINT64_C(1) << 61,
179
180 // ds_gws_* instructions.
181 GWS = UINT64_C(1) << 62,
182
183 // Is a SWMMAC instruction.
184 IsSWMMAC = UINT64_C(1) << 63,
185};
186
187// Predicate functions over TSFlags — the single place where raw TSFlags bit
188// tests are written. All callers (SIInstrInfo methods, MC-layer code) go
189// through these so that bit-layout changes require updating only this file.
190//
191// getTSFlags is overloaded for MCInstrDesc, (MCInstrInfo, Opcode), and
192// (MCInstrInfo, MCInst) here; SIInstrInfo.h adds a MachineInstr overload in
193// namespace llvm so ADL finds it when predicates are instantiated with
194// MachineInstr.
195
196constexpr uint64_t getTSFlags(const MCInstrDesc &Desc) { return Desc.TSFlags; }
197inline uint64_t getTSFlags(const MCInstrInfo &MII, unsigned Opcode) {
198 return MII.get(Opcode).TSFlags;
199}
200inline uint64_t getTSFlags(const MCInstrInfo &MII, const MCInst &Inst) {
201 return MII.get(Opcode: Inst.getOpcode()).TSFlags;
202}
203
204template <typename... T> constexpr bool isSALU(const T &...O) {
205 return getTSFlags(O...) & SALU;
206}
207template <typename... T> constexpr bool isVALU(const T &...O) {
208 return getTSFlags(O...) & VALU;
209}
210template <typename... T> constexpr bool isSOP1(const T &...O) {
211 return getTSFlags(O...) & SOP1;
212}
213template <typename... T> constexpr bool isSOP2(const T &...O) {
214 return getTSFlags(O...) & SOP2;
215}
216template <typename... T> constexpr bool isSOPC(const T &...O) {
217 return getTSFlags(O...) & SOPC;
218}
219template <typename... T> constexpr bool isSOPK(const T &...O) {
220 return getTSFlags(O...) & SOPK;
221}
222template <typename... T> constexpr bool isSOPP(const T &...O) {
223 return getTSFlags(O...) & SOPP;
224}
225template <typename... T> constexpr bool isVOP1(const T &...O) {
226 return getTSFlags(O...) & VOP1;
227}
228template <typename... T> constexpr bool isVOP2(const T &...O) {
229 return getTSFlags(O...) & VOP2;
230}
231template <typename... T> constexpr bool isVOPC(const T &...O) {
232 return getTSFlags(O...) & VOPC;
233}
234template <typename... T> constexpr bool isVOP3(const T &...O) {
235 return getTSFlags(O...) & VOP3;
236}
237template <typename... T> constexpr bool isVOP3P(const T &...O) {
238 return getTSFlags(O...) & VOP3P;
239}
240template <typename... T> constexpr bool isVOP3Like(const T &...O) {
241 return getTSFlags(O...) & (VOP3 | VOP3P);
242}
243template <typename... T> constexpr bool isVINTRP(const T &...O) {
244 return getTSFlags(O...) & VINTRP;
245}
246template <typename... T> constexpr bool isSDWA(const T &...O) {
247 return getTSFlags(O...) & SDWA;
248}
249template <typename... T> constexpr bool isDPP(const T &...O) {
250 return getTSFlags(O...) & DPP;
251}
252template <typename... T> constexpr bool isTRANS(const T &...O) {
253 return getTSFlags(O...) & TRANS;
254}
255template <typename... T> constexpr bool isMUBUF(const T &...O) {
256 return getTSFlags(O...) & MUBUF;
257}
258template <typename... T> constexpr bool isMTBUF(const T &...O) {
259 return getTSFlags(O...) & MTBUF;
260}
261template <typename... T> constexpr bool isBuffer(const T &...O) {
262 return getTSFlags(O...) & (MUBUF | MTBUF);
263}
264template <typename... T> constexpr bool isSMRD(const T &...O) {
265 return getTSFlags(O...) & SMRD;
266}
267template <typename... T> constexpr bool isMIMG(const T &...O) {
268 return getTSFlags(O...) & MIMG;
269}
270template <typename... T> constexpr bool isVIMAGE(const T &...O) {
271 return getTSFlags(O...) & VIMAGE;
272}
273template <typename... T> constexpr bool isVSAMPLE(const T &...O) {
274 return getTSFlags(O...) & VSAMPLE;
275}
276template <typename... T> constexpr bool isEXP(const T &...O) {
277 return getTSFlags(O...) & EXP;
278}
279template <typename... T> constexpr bool isFLAT(const T &...O) {
280 return getTSFlags(O...) & FLAT;
281}
282template <typename... T> constexpr bool isDS(const T &...O) {
283 return getTSFlags(O...) & DS;
284}
285template <typename... T> constexpr bool isSpill(const T &...O) {
286 return getTSFlags(O...) & Spill;
287}
288template <typename... T> constexpr bool isLDSDIR(const T &...O) {
289 return getTSFlags(O...) & LDSDIR;
290}
291template <typename... T> constexpr bool isVINTERP(const T &...O) {
292 return getTSFlags(O...) & VINTERP;
293}
294template <typename... T> constexpr bool isWQM(const T &...O) {
295 return getTSFlags(O...) & WQM;
296}
297template <typename... T> constexpr bool isDisableWQM(const T &...O) {
298 return getTSFlags(O...) & DisableWQM;
299}
300template <typename... T> constexpr bool isGather4(const T &...O) {
301 return getTSFlags(O...) & Gather4;
302}
303template <typename... T> constexpr bool usesTENSOR_CNT(const T &...O) {
304 return getTSFlags(O...) & TENSOR_CNT;
305}
306template <typename... T> constexpr bool isScalarStore(const T &...O) {
307 return getTSFlags(O...) & SCALAR_STORE;
308}
309template <typename... T> constexpr bool isFixedSize(const T &...O) {
310 return getTSFlags(O...) & FIXED_SIZE;
311}
312template <typename... T> constexpr bool usesASYNC_CNT(const T &...O) {
313 return getTSFlags(O...) & ASYNC_CNT;
314}
315template <typename... T> constexpr bool hasVOP3OpSel(const T &...O) {
316 return getTSFlags(O...) & VOP3_OPSEL;
317}
318template <typename... T> constexpr bool isMaybeAtomic(const T &...O) {
319 return getTSFlags(O...) & maybeAtomic;
320}
321template <typename... T> constexpr bool hasFPClamp(const T &...O) {
322 return getTSFlags(O...) & FPClamp;
323}
324template <typename... T> constexpr bool hasIntClamp(const T &...O) {
325 return getTSFlags(O...) & IntClamp;
326}
327template <typename... T> constexpr bool hasClampLo(const T &...O) {
328 return getTSFlags(O...) & ClampLo;
329}
330template <typename... T> constexpr bool hasClampHi(const T &...O) {
331 return getTSFlags(O...) & ClampHi;
332}
333template <typename... T> constexpr bool isPacked(const T &...O) {
334 return getTSFlags(O...) & IsPacked;
335}
336template <typename... T> constexpr bool isD16Buf(const T &...O) {
337 return getTSFlags(O...) & D16Buf;
338}
339template <typename... T> constexpr bool isFlatGlobal(const T &...O) {
340 return getTSFlags(O...) & FlatGlobal;
341}
342template <typename... T> constexpr bool usesFPDPRounding(const T &...O) {
343 return getTSFlags(O...) & FPDPRounding;
344}
345template <typename... T> constexpr bool isFPAtomic(const T &...O) {
346 return getTSFlags(O...) & FPAtomic;
347}
348template <typename... T> constexpr bool isMAI(const T &...O) {
349 return getTSFlags(O...) & IsMAI;
350}
351template <typename... T> constexpr bool isDOT(const T &...O) {
352 return getTSFlags(O...) & IsDOT;
353}
354template <typename... T> constexpr bool isFlatScratch(const T &...O) {
355 return getTSFlags(O...) & FlatScratch;
356}
357template <typename... T> constexpr bool isAtomicNoRet(const T &...O) {
358 return getTSFlags(O...) & IsAtomicNoRet;
359}
360template <typename... T> constexpr bool isAtomicRet(const T &...O) {
361 return getTSFlags(O...) & IsAtomicRet;
362}
363template <typename... T> constexpr bool isWMMA(const T &...O) {
364 return getTSFlags(O...) & IsWMMA;
365}
366template <typename... T> constexpr bool isTiedSourceNotRead(const T &...O) {
367 return getTSFlags(O...) & TiedSourceNotRead;
368}
369template <typename... T> constexpr bool isNeverUniform(const T &...O) {
370 return getTSFlags(O...) & IsNeverUniform;
371}
372template <typename... T> constexpr bool isGWS(const T &...O) {
373 return getTSFlags(O...) & GWS;
374}
375template <typename... T> constexpr bool isSWMMAC(const T &...O) {
376 return getTSFlags(O...) & IsSWMMAC;
377}
378template <typename... T> constexpr bool isVOPD3(const T &...O) {
379 return getTSFlags(O...) & VOPD3;
380}
381template <typename... T> constexpr bool usesVM_CNT(const T &...O) {
382 return getTSFlags(O...) & VM_CNT;
383}
384template <typename... T> constexpr bool usesLGKM_CNT(const T &...O) {
385 return getTSFlags(O...) & LGKM_CNT;
386}
387
388// Compound predicates.
389template <typename... T> constexpr bool isAtomic(const T &...O) {
390 return isAtomicNoRet(O...) || isAtomicRet(O...);
391}
392template <typename... T> constexpr bool isSegmentSpecificFLAT(const T &...O) {
393 return isFlatGlobal(O...) || isFlatScratch(O...);
394}
395// Any image-family instruction: pre-gfx11 MIMG, gfx11+ VIMAGE or VSAMPLE.
396template <typename... T> constexpr bool isImage(const T &...O) {
397 return isMIMG(O...) || isVIMAGE(O...) || isVSAMPLE(O...);
398}
399// Vector memory: buffer + image + flat.
400template <typename... T> constexpr bool isVMEM(const T &...O) {
401 return isMUBUF(O...) || isMTBUF(O...) || isImage(O...) || isFLAT(O...);
402}
403
404// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
405// The result is true if any of these tests are true.
406enum ClassFlags : unsigned {
407 S_NAN = 1 << 0, // Signaling NaN
408 Q_NAN = 1 << 1, // Quiet NaN
409 N_INFINITY = 1 << 2, // Negative infinity
410 N_NORMAL = 1 << 3, // Negative normal
411 N_SUBNORMAL = 1 << 4, // Negative subnormal
412 N_ZERO = 1 << 5, // Negative zero
413 P_ZERO = 1 << 6, // Positive zero
414 P_SUBNORMAL = 1 << 7, // Positive subnormal
415 P_NORMAL = 1 << 8, // Positive normal
416 P_INFINITY = 1 << 9 // Positive infinity
417};
418}
419
420namespace AMDGPU {
421
422enum OperandType : unsigned {
423 /// Operands with register, 32-bit, or 64-bit immediate
424 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
425 OPERAND_REG_IMM_INT64,
426 OPERAND_REG_IMM_INT16,
427 OPERAND_REG_IMM_FP32,
428 OPERAND_REG_IMM_FP64,
429 OPERAND_REG_IMM_BF16,
430 OPERAND_REG_IMM_FP16,
431 OPERAND_REG_IMM_V2BF16,
432 OPERAND_REG_IMM_V2FP16,
433 OPERAND_REG_IMM_V2FP16_SPLAT,
434 OPERAND_REG_IMM_V2INT16,
435 OPERAND_REG_IMM_V2INT64,
436 OPERAND_REG_IMM_NOINLINE_V2FP16,
437 OPERAND_REG_IMM_V2INT32,
438 OPERAND_REG_IMM_V2FP32,
439 OPERAND_REG_IMM_V2FP64,
440
441 /// Operands with register or inline constant
442 OPERAND_REG_INLINE_C_INT16,
443 OPERAND_REG_INLINE_C_INT32,
444 OPERAND_REG_INLINE_C_INT64,
445 OPERAND_REG_INLINE_C_BF16,
446 OPERAND_REG_INLINE_C_FP16,
447 OPERAND_REG_INLINE_C_FP32,
448 OPERAND_REG_INLINE_C_FP64,
449 OPERAND_REG_INLINE_C_V2INT16,
450 OPERAND_REG_INLINE_C_V2BF16,
451 OPERAND_REG_INLINE_C_V2FP16,
452
453 // Operand for split barrier inline constant
454 OPERAND_INLINE_SPLIT_BARRIER_INT32,
455
456 /// Operand with 32-bit immediate that uses the constant bus.
457 OPERAND_KIMM32,
458 OPERAND_KIMM16,
459 OPERAND_KIMM64,
460
461 /// Operands with an AccVGPR register or inline constant
462 OPERAND_REG_INLINE_AC_INT32,
463 OPERAND_REG_INLINE_AC_FP32,
464 OPERAND_REG_INLINE_AC_FP64,
465
466 // Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline
467 // constants. Does not accept registers.
468 OPERAND_INLINE_C_AV64_PSEUDO,
469
470 // Operand for source modifiers for VOP instructions
471 OPERAND_INPUT_MODS,
472
473 // Operand for SDWA instructions
474 OPERAND_SDWA_VOPC_DST,
475
476 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
477 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP64,
478
479 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
480 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,
481
482 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,
483 OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO,
484
485 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
486 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
487
488 OPERAND_KIMM_FIRST = OPERAND_KIMM32,
489 OPERAND_KIMM_LAST = OPERAND_KIMM64
490
491};
492}
493
494// Input operand modifiers bit-masks
495// NEG and SEXT share same bit-mask because they can't be set simultaneously.
496namespace SISrcMods {
497enum : unsigned {
498 NONE = 0,
499 NEG = 1 << 0, // Floating-point negate modifier
500 ABS = 1 << 1, // Floating-point absolute modifier
501 SEXT = 1 << 4, // Integer sign-extend modifier
502 NEG_HI = ABS, // Floating-point negate high packed component modifier.
503 OP_SEL_0 = 1 << 2,
504 OP_SEL_1 = 1 << 3,
505 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
506};
507}
508
509namespace SIOutMods {
510 enum : unsigned {
511 NONE = 0,
512 MUL2 = 1,
513 MUL4 = 2,
514 DIV2 = 3
515 };
516}
517
518namespace AMDGPU {
519namespace VGPRIndexMode {
520
521enum Id : unsigned { // id of symbolic names
522 ID_SRC0 = 0,
523 ID_SRC1,
524 ID_SRC2,
525 ID_DST,
526
527 ID_MIN = ID_SRC0,
528 ID_MAX = ID_DST
529};
530
531enum EncBits : unsigned {
532 OFF = 0,
533 SRC0_ENABLE = 1 << ID_SRC0,
534 SRC1_ENABLE = 1 << ID_SRC1,
535 SRC2_ENABLE = 1 << ID_SRC2,
536 DST_ENABLE = 1 << ID_DST,
537 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
538 UNDEF = 0xFFFF
539};
540
541} // namespace VGPRIndexMode
542} // namespace AMDGPU
543
544namespace AMDGPUAsmVariants {
545 enum : unsigned {
546 DEFAULT = 0,
547 VOP3 = 1,
548 SDWA = 2,
549 SDWA9 = 3,
550 DPP = 4,
551 VOP3_DPP = 5
552 };
553} // namespace AMDGPUAsmVariants
554
555namespace AMDGPU {
556namespace EncValues { // Encoding values of enum9/8/7 operands
557
558enum : unsigned {
559 SGPR_MIN = 0,
560 SGPR_MAX_SI = 101,
561 SGPR_MAX_GFX10 = 105,
562 TTMP_VI_MIN = 112,
563 TTMP_VI_MAX = 123,
564 TTMP_GFX9PLUS_MIN = 108,
565 TTMP_GFX9PLUS_MAX = 123,
566 INLINE_INTEGER_C_MIN = 128,
567 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
568 INLINE_INTEGER_C_MAX = 208,
569 INLINE_FLOATING_C_MIN = 240,
570 INLINE_FLOATING_C_MAX = 248,
571 LITERAL64_CONST = 254,
572 LITERAL_CONST = 255,
573 VGPR_MIN = 256,
574 VGPR_MAX = 511,
575 IS_VGPR = 256, // Indicates VGPR or AGPR
576};
577
578} // namespace EncValues
579
580// Register codes as defined in the TableGen's HWEncoding field.
581namespace HWEncoding {
582enum : unsigned {
583 REG_IDX_MASK = 0x3ff,
584 LO256_REG_IDX_MASK = 0xff,
585 IS_VGPR = 1 << 10,
586 IS_AGPR = 1 << 11,
587 IS_HI16 = 1 << 12,
588};
589} // namespace HWEncoding
590
591namespace CPol {
592
593enum CPol {
594 GLC = 1,
595 SLC = 2,
596 DLC = 4,
597 SCC = 16,
598 SC0 = GLC,
599 SC1 = SCC,
600 NT = SLC,
601 ALL_pregfx12 = GLC | SLC | DLC | SCC,
602 SWZ_pregfx12 = 8,
603
604 // Below are GFX12+ cache policy bits
605
606 // Temporal hint
607 TH = 0x7, // All TH bits
608 TH_RT = 0, // regular
609 TH_NT = 1, // non-temporal
610 TH_HT = 2, // high-temporal
611 TH_LU = 3, // last use
612 TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
613 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
614 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
615 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
616 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)
617 TH_BYPASS = 3, // only to be used with scope = 3
618
619 TH_RESERVED = 7, // unused value for load insts
620
621 // Bits of TH for atomics
622 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
623 TH_ATOMIC_NT = SLC, // Non-temporal vs regular
624 TH_ATOMIC_CASCADE = 4, // Cascading vs regular
625
626 // Scope
627 SCOPE_SHIFT = 3,
628 SCOPE_MASK = 0x3,
629 SCOPE = SCOPE_MASK << SCOPE_SHIFT, // All Scope bits
630 SCOPE_CU = 0 << SCOPE_SHIFT,
631 SCOPE_SE = 1 << SCOPE_SHIFT,
632 SCOPE_DEV = 2 << SCOPE_SHIFT,
633 SCOPE_SYS = 3 << SCOPE_SHIFT,
634
635 NV = 1 << 5, // Non-volatile bit
636
637 SWZ = 1 << 6, // Swizzle bit
638
639 SCAL = 1 << 11, // Scale offset bit
640
641 ALL = TH | SCOPE | NV,
642
643 // Helper bits
644 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy
645 TH_TYPE_STORE = 1 << 8, // TH_STORE policy
646 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy
647 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
648
649 // Volatile (used to preserve/signal operation volatility for buffer
650 // operations not a real instruction bit)
651 VOLATILE = 1 << 31,
652 // The set of "cache policy" bits used for compiler features that
653 // do not correspond to handware features.
654 VIRTUAL_BITS = VOLATILE,
655};
656
657} // namespace CPol
658
659namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
660
661enum Id { // Message ID, width(4) [3:0].
662 ID_INTERRUPT = 1,
663
664 ID_GS_PreGFX11 = 2, // replaced in GFX11
665 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
666
667 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
668 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
669
670 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
671 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12
672 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12
673 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
674 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
675 ID_GS_ALLOC_REQ = 9, // added in GFX9
676 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
677 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
678 ID_SYSMSG = 15,
679
680 ID_RTN_GET_DOORBELL = 128,
681 ID_RTN_GET_DDID = 129,
682 ID_RTN_GET_TMA = 130,
683 ID_RTN_GET_REALTIME = 131,
684 ID_RTN_SAVE_WAVE = 132,
685 ID_RTN_GET_TBA = 133,
686 ID_RTN_GET_TBA_TO_PC = 134,
687 ID_RTN_GET_SE_AID_ID = 135,
688
689 ID_RTN_GET_CLUSTER_BARRIER_STATE = 136, // added in GFX1250
690 ID_RTN_SAVE_WAVE_HAS_TDM = 152, // added in GFX1250
691
692 ID_MASK_PreGFX11_ = 0xF,
693 ID_MASK_GFX11Plus_ = 0xFF
694};
695
696enum Op { // Both GS and SYS operation IDs.
697 OP_SHIFT_ = 4,
698 OP_NONE_ = 0,
699 // Bits used for operation encoding
700 OP_WIDTH_ = 3,
701 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
702 // GS operations are encoded in bits 5:4
703 OP_GS_NOP = 0,
704 OP_GS_CUT = 1,
705 OP_GS_EMIT = 2,
706 OP_GS_EMIT_CUT = 3,
707 OP_GS_FIRST_ = OP_GS_NOP,
708 // SYS operations are encoded in bits 6:4
709 OP_SYS_ECC_ERR_INTERRUPT = 1,
710 OP_SYS_REG_RD = 2,
711 OP_SYS_HOST_TRAP_ACK = 3,
712 OP_SYS_TTRACE_PC = 4,
713 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
714};
715
716enum StreamId : unsigned { // Stream ID, (2) [9:8].
717 STREAM_ID_NONE_ = 0,
718 STREAM_ID_DEFAULT_ = 0,
719 STREAM_ID_LAST_ = 4,
720 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
721 STREAM_ID_SHIFT_ = 8,
722 STREAM_ID_WIDTH_= 2,
723 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
724};
725
726} // namespace SendMsg
727
728namespace WaitEvent { // Encoding of SIMM16 used in s_wait_event
729enum Id {
730 DONT_WAIT_EXPORT_READY = 1 << 0, // Only used in gfx11
731 EXPORT_READY = 1 << 1, // gfx12+
732};
733
734} // namespace WaitEvent
735
736namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
737
738enum Id { // HwRegCode, (6) [5:0]
739 ID_MODE = 1,
740 ID_STATUS = 2,
741 ID_TRAPSTS = 3,
742 ID_HW_ID = 4,
743 ID_GPR_ALLOC = 5,
744 ID_LDS_ALLOC = 6,
745 ID_IB_STS = 7,
746 ID_PERF_SNAPSHOT_DATA_gfx12 = 10,
747 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,
748 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,
749 ID_MEM_BASES = 15,
750 ID_TBA_LO = 16,
751 ID_TBA_HI = 17,
752 ID_TMA_LO = 18,
753 ID_TMA_HI = 19,
754 ID_FLAT_SCR_LO = 20,
755 ID_FLAT_SCR_HI = 21,
756 ID_XNACK_MASK = 22,
757 ID_HW_ID1 = 23,
758 ID_HW_ID2 = 24,
759 ID_POPS_PACKER = 25,
760 ID_SCHED_MODE = 26,
761 ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
762 ID_IB_STS2 = 28,
763 ID_SHADER_CYCLES = 29,
764 ID_SHADER_CYCLES_HI = 30,
765 ID_DVGPR_ALLOC_LO = 31,
766 ID_DVGPR_ALLOC_HI = 32,
767
768 // Register numbers reused in GFX11
769 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,
770 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,
771
772 // Register numbers reused in GFX12+
773 ID_STATE_PRIV = 4,
774 ID_PERF_SNAPSHOT_DATA1 = 15,
775 ID_PERF_SNAPSHOT_DATA2 = 16,
776 ID_EXCP_FLAG_PRIV = 17,
777 ID_EXCP_FLAG_USER = 18,
778 ID_TRAP_CTRL = 19,
779
780 // GFX94* specific registers
781 ID_XCC_ID = 20,
782 ID_SQ_PERF_SNAPSHOT_DATA = 21,
783 ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
784 ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
785 ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
786
787 // GFX1250
788 ID_XNACK_STATE_PRIV = 33,
789 ID_XNACK_MASK_gfx1250 = 34,
790};
791
792enum Offset : unsigned { // Offset, (5) [10:6]
793 OFFSET_MEM_VIOL = 8,
794 OFFSET_ME_ID = 8, // in HW_ID2
795};
796
797enum ModeRegisterMasks : uint32_t {
798 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
799 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
800 DX10_CLAMP_MASK = 1 << 8,
801 IEEE_MODE_MASK = 1 << 9,
802 LOD_CLAMP_MASK = 1 << 10,
803 DEBUG_MASK = 1 << 11,
804
805 // EXCP_EN fields.
806 EXCP_EN_INVALID_MASK = 1 << 12,
807 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
808 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
809 EXCP_EN_OVERFLOW_MASK = 1 << 15,
810 EXCP_EN_UNDERFLOW_MASK = 1 << 16,
811 EXCP_EN_INEXACT_MASK = 1 << 17,
812 EXCP_EN_INT_DIV0_MASK = 1 << 18,
813
814 GPR_IDX_EN_MASK = 1 << 27,
815 VSKIP_MASK = 1 << 28,
816 CSP_MASK = 0x7u << 29, // Bits 29..31
817
818 // GFX1250
819 DST_VGPR_MSB = 0x3 << 12,
820 SRC0_VGPR_MSB = 0x3 << 14,
821 SRC1_VGPR_MSB = 0x3 << 16,
822 SRC2_VGPR_MSB = 0x3 << 18,
823 VGPR_MSB_MASK = 0xff << 12, // Bits 12..19
824
825 REPLAY_MODE = 1 << 25,
826 FLAT_SCRATCH_IS_NV = 1 << 26,
827};
828
829} // namespace Hwreg
830
831namespace MTBUFFormat {
832
833enum DataFormat : int64_t {
834 DFMT_INVALID = 0,
835 DFMT_8,
836 DFMT_16,
837 DFMT_8_8,
838 DFMT_32,
839 DFMT_16_16,
840 DFMT_10_11_11,
841 DFMT_11_11_10,
842 DFMT_10_10_10_2,
843 DFMT_2_10_10_10,
844 DFMT_8_8_8_8,
845 DFMT_32_32,
846 DFMT_16_16_16_16,
847 DFMT_32_32_32,
848 DFMT_32_32_32_32,
849 DFMT_RESERVED_15,
850
851 DFMT_MIN = DFMT_INVALID,
852 DFMT_MAX = DFMT_RESERVED_15,
853
854 DFMT_UNDEF = -1,
855 DFMT_DEFAULT = DFMT_8,
856
857 DFMT_SHIFT = 0,
858 DFMT_MASK = 0xF
859};
860
861enum NumFormat : int64_t {
862 NFMT_UNORM = 0,
863 NFMT_SNORM,
864 NFMT_USCALED,
865 NFMT_SSCALED,
866 NFMT_UINT,
867 NFMT_SINT,
868 NFMT_RESERVED_6, // VI and GFX9
869 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
870 NFMT_FLOAT,
871
872 NFMT_MIN = NFMT_UNORM,
873 NFMT_MAX = NFMT_FLOAT,
874
875 NFMT_UNDEF = -1,
876 NFMT_DEFAULT = NFMT_UNORM,
877
878 NFMT_SHIFT = 4,
879 NFMT_MASK = 7
880};
881
882enum MergedFormat : int64_t {
883 DFMT_NFMT_UNDEF = -1,
884 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
885 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
886
887
888 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
889
890 DFMT_NFMT_MAX = DFMT_NFMT_MASK
891};
892
893enum UnifiedFormatCommon : int64_t {
894 UFMT_MAX = 127,
895 UFMT_UNDEF = -1,
896 UFMT_DEFAULT = 1
897};
898
899} // namespace MTBUFFormat
900
901namespace UfmtGFX10 {
902enum UnifiedFormat : int64_t {
903 UFMT_INVALID = 0,
904
905 UFMT_8_UNORM,
906 UFMT_8_SNORM,
907 UFMT_8_USCALED,
908 UFMT_8_SSCALED,
909 UFMT_8_UINT,
910 UFMT_8_SINT,
911
912 UFMT_16_UNORM,
913 UFMT_16_SNORM,
914 UFMT_16_USCALED,
915 UFMT_16_SSCALED,
916 UFMT_16_UINT,
917 UFMT_16_SINT,
918 UFMT_16_FLOAT,
919
920 UFMT_8_8_UNORM,
921 UFMT_8_8_SNORM,
922 UFMT_8_8_USCALED,
923 UFMT_8_8_SSCALED,
924 UFMT_8_8_UINT,
925 UFMT_8_8_SINT,
926
927 UFMT_32_UINT,
928 UFMT_32_SINT,
929 UFMT_32_FLOAT,
930
931 UFMT_16_16_UNORM,
932 UFMT_16_16_SNORM,
933 UFMT_16_16_USCALED,
934 UFMT_16_16_SSCALED,
935 UFMT_16_16_UINT,
936 UFMT_16_16_SINT,
937 UFMT_16_16_FLOAT,
938
939 UFMT_10_11_11_UNORM,
940 UFMT_10_11_11_SNORM,
941 UFMT_10_11_11_USCALED,
942 UFMT_10_11_11_SSCALED,
943 UFMT_10_11_11_UINT,
944 UFMT_10_11_11_SINT,
945 UFMT_10_11_11_FLOAT,
946
947 UFMT_11_11_10_UNORM,
948 UFMT_11_11_10_SNORM,
949 UFMT_11_11_10_USCALED,
950 UFMT_11_11_10_SSCALED,
951 UFMT_11_11_10_UINT,
952 UFMT_11_11_10_SINT,
953 UFMT_11_11_10_FLOAT,
954
955 UFMT_10_10_10_2_UNORM,
956 UFMT_10_10_10_2_SNORM,
957 UFMT_10_10_10_2_USCALED,
958 UFMT_10_10_10_2_SSCALED,
959 UFMT_10_10_10_2_UINT,
960 UFMT_10_10_10_2_SINT,
961
962 UFMT_2_10_10_10_UNORM,
963 UFMT_2_10_10_10_SNORM,
964 UFMT_2_10_10_10_USCALED,
965 UFMT_2_10_10_10_SSCALED,
966 UFMT_2_10_10_10_UINT,
967 UFMT_2_10_10_10_SINT,
968
969 UFMT_8_8_8_8_UNORM,
970 UFMT_8_8_8_8_SNORM,
971 UFMT_8_8_8_8_USCALED,
972 UFMT_8_8_8_8_SSCALED,
973 UFMT_8_8_8_8_UINT,
974 UFMT_8_8_8_8_SINT,
975
976 UFMT_32_32_UINT,
977 UFMT_32_32_SINT,
978 UFMT_32_32_FLOAT,
979
980 UFMT_16_16_16_16_UNORM,
981 UFMT_16_16_16_16_SNORM,
982 UFMT_16_16_16_16_USCALED,
983 UFMT_16_16_16_16_SSCALED,
984 UFMT_16_16_16_16_UINT,
985 UFMT_16_16_16_16_SINT,
986 UFMT_16_16_16_16_FLOAT,
987
988 UFMT_32_32_32_UINT,
989 UFMT_32_32_32_SINT,
990 UFMT_32_32_32_FLOAT,
991 UFMT_32_32_32_32_UINT,
992 UFMT_32_32_32_32_SINT,
993 UFMT_32_32_32_32_FLOAT,
994
995 UFMT_FIRST = UFMT_INVALID,
996 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
997};
998
999} // namespace UfmtGFX10
1000
1001namespace UfmtGFX11 {
1002enum UnifiedFormat : int64_t {
1003 UFMT_INVALID = 0,
1004
1005 UFMT_8_UNORM,
1006 UFMT_8_SNORM,
1007 UFMT_8_USCALED,
1008 UFMT_8_SSCALED,
1009 UFMT_8_UINT,
1010 UFMT_8_SINT,
1011
1012 UFMT_16_UNORM,
1013 UFMT_16_SNORM,
1014 UFMT_16_USCALED,
1015 UFMT_16_SSCALED,
1016 UFMT_16_UINT,
1017 UFMT_16_SINT,
1018 UFMT_16_FLOAT,
1019
1020 UFMT_8_8_UNORM,
1021 UFMT_8_8_SNORM,
1022 UFMT_8_8_USCALED,
1023 UFMT_8_8_SSCALED,
1024 UFMT_8_8_UINT,
1025 UFMT_8_8_SINT,
1026
1027 UFMT_32_UINT,
1028 UFMT_32_SINT,
1029 UFMT_32_FLOAT,
1030
1031 UFMT_16_16_UNORM,
1032 UFMT_16_16_SNORM,
1033 UFMT_16_16_USCALED,
1034 UFMT_16_16_SSCALED,
1035 UFMT_16_16_UINT,
1036 UFMT_16_16_SINT,
1037 UFMT_16_16_FLOAT,
1038
1039 UFMT_10_11_11_FLOAT,
1040
1041 UFMT_11_11_10_FLOAT,
1042
1043 UFMT_10_10_10_2_UNORM,
1044 UFMT_10_10_10_2_SNORM,
1045 UFMT_10_10_10_2_UINT,
1046 UFMT_10_10_10_2_SINT,
1047
1048 UFMT_2_10_10_10_UNORM,
1049 UFMT_2_10_10_10_SNORM,
1050 UFMT_2_10_10_10_USCALED,
1051 UFMT_2_10_10_10_SSCALED,
1052 UFMT_2_10_10_10_UINT,
1053 UFMT_2_10_10_10_SINT,
1054
1055 UFMT_8_8_8_8_UNORM,
1056 UFMT_8_8_8_8_SNORM,
1057 UFMT_8_8_8_8_USCALED,
1058 UFMT_8_8_8_8_SSCALED,
1059 UFMT_8_8_8_8_UINT,
1060 UFMT_8_8_8_8_SINT,
1061
1062 UFMT_32_32_UINT,
1063 UFMT_32_32_SINT,
1064 UFMT_32_32_FLOAT,
1065
1066 UFMT_16_16_16_16_UNORM,
1067 UFMT_16_16_16_16_SNORM,
1068 UFMT_16_16_16_16_USCALED,
1069 UFMT_16_16_16_16_SSCALED,
1070 UFMT_16_16_16_16_UINT,
1071 UFMT_16_16_16_16_SINT,
1072 UFMT_16_16_16_16_FLOAT,
1073
1074 UFMT_32_32_32_UINT,
1075 UFMT_32_32_32_SINT,
1076 UFMT_32_32_32_FLOAT,
1077 UFMT_32_32_32_32_UINT,
1078 UFMT_32_32_32_32_SINT,
1079 UFMT_32_32_32_32_FLOAT,
1080
1081 UFMT_FIRST = UFMT_INVALID,
1082 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
1083};
1084
1085} // namespace UfmtGFX11
1086
1087namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
1088
1089enum Id : unsigned { // id of symbolic names
1090 ID_QUAD_PERM = 0,
1091 ID_BITMASK_PERM,
1092 ID_SWAP,
1093 ID_REVERSE,
1094 ID_BROADCAST,
1095 ID_FFT,
1096 ID_ROTATE
1097};
1098
1099// clang-format off
1100enum EncBits : unsigned {
1101
1102 // swizzle mode encodings
1103
1104 QUAD_PERM_ENC = 0x8000,
1105 QUAD_PERM_ENC_MASK = 0xFF00,
1106
1107 BITMASK_PERM_ENC = 0x0000,
1108 BITMASK_PERM_ENC_MASK = 0x8000,
1109
1110 FFT_MODE_ENC = 0xE000,
1111
1112 ROTATE_MODE_ENC = 0xC000,
1113 FFT_ROTATE_MODE_MASK = 0xF000,
1114
1115 ROTATE_MODE_LO = 0xC000,
1116 FFT_MODE_LO = 0xE000,
1117
1118 // QUAD_PERM encodings
1119
1120 LANE_MASK = 0x3,
1121 LANE_MAX = LANE_MASK,
1122 LANE_SHIFT = 2,
1123 LANE_NUM = 4,
1124
1125 // BITMASK_PERM encodings
1126
1127 BITMASK_MASK = 0x1F,
1128 BITMASK_MAX = BITMASK_MASK,
1129 BITMASK_WIDTH = 5,
1130
1131 BITMASK_AND_SHIFT = 0,
1132 BITMASK_OR_SHIFT = 5,
1133 BITMASK_XOR_SHIFT = 10,
1134
1135 // FFT encodings
1136
1137 FFT_SWIZZLE_MASK = 0x1F,
1138 FFT_SWIZZLE_MAX = 0x1F,
1139
1140 // ROTATE encodings
1141 ROTATE_MAX_SIZE = 0x1F,
1142 ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
1143 ROTATE_DIR_MASK = 0x1,
1144 ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
1145 ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
1146};
1147// clang-format on
1148
1149} // namespace Swizzle
1150
1151namespace SDWA {
1152
1153enum SdwaSel : unsigned {
1154 BYTE_0 = 0,
1155 BYTE_1 = 1,
1156 BYTE_2 = 2,
1157 BYTE_3 = 3,
1158 WORD_0 = 4,
1159 WORD_1 = 5,
1160 DWORD = 6,
1161};
1162
1163enum DstUnused : unsigned {
1164 UNUSED_PAD = 0,
1165 UNUSED_SEXT = 1,
1166 UNUSED_PRESERVE = 2,
1167};
1168
1169enum SDWA9EncValues : unsigned {
1170 SRC_SGPR_MASK = 0x100,
1171 SRC_VGPR_MASK = 0xFF,
1172 VOPC_DST_VCC_MASK = 0x80,
1173 VOPC_DST_SGPR_MASK = 0x7F,
1174
1175 SRC_VGPR_MIN = 0,
1176 SRC_VGPR_MAX = 255,
1177 SRC_SGPR_MIN = 256,
1178 SRC_SGPR_MAX_SI = 357,
1179 SRC_SGPR_MAX_GFX10 = 361,
1180 SRC_TTMP_MIN = 364,
1181 SRC_TTMP_MAX = 379,
1182};
1183
1184} // namespace SDWA
1185
1186namespace DPP {
1187
1188// clang-format off
1189enum DppCtrl : unsigned {
1190 QUAD_PERM_FIRST = 0,
1191 QUAD_PERM_ID = 0xE4, // identity permutation
1192 QUAD_PERM_LAST = 0xFF,
1193 DPP_UNUSED1 = 0x100,
1194 ROW_SHL0 = 0x100,
1195 ROW_SHL_FIRST = 0x101,
1196 ROW_SHL_LAST = 0x10F,
1197 DPP_UNUSED2 = 0x110,
1198 ROW_SHR0 = 0x110,
1199 ROW_SHR_FIRST = 0x111,
1200 ROW_SHR_LAST = 0x11F,
1201 DPP_UNUSED3 = 0x120,
1202 ROW_ROR0 = 0x120,
1203 ROW_ROR_FIRST = 0x121,
1204 ROW_ROR_LAST = 0x12F,
1205 WAVE_SHL1 = 0x130,
1206 DPP_UNUSED4_FIRST = 0x131,
1207 DPP_UNUSED4_LAST = 0x133,
1208 WAVE_ROL1 = 0x134,
1209 DPP_UNUSED5_FIRST = 0x135,
1210 DPP_UNUSED5_LAST = 0x137,
1211 WAVE_SHR1 = 0x138,
1212 DPP_UNUSED6_FIRST = 0x139,
1213 DPP_UNUSED6_LAST = 0x13B,
1214 WAVE_ROR1 = 0x13C,
1215 DPP_UNUSED7_FIRST = 0x13D,
1216 DPP_UNUSED7_LAST = 0x13F,
1217 ROW_MIRROR = 0x140,
1218 ROW_HALF_MIRROR = 0x141,
1219 BCAST15 = 0x142,
1220 BCAST31 = 0x143,
1221 DPP_UNUSED8_FIRST = 0x144,
1222 DPP_UNUSED8_LAST = 0x14F,
1223 ROW_NEWBCAST_FIRST= 0x150,
1224 ROW_NEWBCAST_LAST = 0x15F,
1225 ROW_SHARE0 = 0x150,
1226 ROW_SHARE_FIRST = 0x150,
1227 ROW_SHARE_LAST = 0x15F,
1228 ROW_XMASK0 = 0x160,
1229 ROW_XMASK_FIRST = 0x160,
1230 ROW_XMASK_LAST = 0x16F,
1231 DPP_LAST = ROW_XMASK_LAST
1232};
1233// clang-format on
1234
1235enum DppFiMode {
1236 DPP_FI_0 = 0,
1237 DPP_FI_1 = 1,
1238 DPP8_FI_0 = 0xE9,
1239 DPP8_FI_1 = 0xEA,
1240};
1241
1242} // namespace DPP
1243
1244namespace Exp {
1245
1246enum Target : unsigned {
1247 ET_MRT0 = 0,
1248 ET_MRT7 = 7,
1249 ET_MRTZ = 8,
1250 ET_NULL = 9, // Pre-GFX11
1251 ET_POS0 = 12,
1252 ET_POS3 = 15,
1253 ET_POS4 = 16, // GFX10+
1254 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
1255 ET_PRIM = 20, // GFX10+
1256 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
1257 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
1258 ET_PARAM0 = 32, // Pre-GFX11
1259 ET_PARAM31 = 63, // Pre-GFX11
1260
1261 ET_NULL_MAX_IDX = 0,
1262 ET_MRTZ_MAX_IDX = 0,
1263 ET_PRIM_MAX_IDX = 0,
1264 ET_MRT_MAX_IDX = 7,
1265 ET_POS_MAX_IDX = 4,
1266 ET_DUAL_SRC_BLEND_MAX_IDX = 1,
1267 ET_PARAM_MAX_IDX = 31,
1268
1269 ET_INVALID = 255,
1270};
1271
1272} // namespace Exp
1273
1274namespace WMMA {
1275enum MatrixFMT : unsigned {
1276 MATRIX_FMT_FP8 = 0,
1277 MATRIX_FMT_BF8 = 1,
1278 MATRIX_FMT_FP6 = 2,
1279 MATRIX_FMT_BF6 = 3,
1280 MATRIX_FMT_FP4 = 4
1281};
1282
1283enum MatrixScale : unsigned {
1284 MATRIX_SCALE_ROW0 = 0,
1285 MATRIX_SCALE_ROW1 = 1,
1286};
1287
1288enum MatrixScaleFmt : unsigned {
1289 MATRIX_SCALE_FMT_E8 = 0,
1290 MATRIX_SCALE_FMT_E5M3 = 1,
1291 MATRIX_SCALE_FMT_E4M3 = 2
1292};
1293} // namespace WMMA
1294
1295namespace VOP3PEncoding {
1296
1297enum OpSel : uint64_t {
1298 OP_SEL_HI_0 = UINT64_C(1) << 59,
1299 OP_SEL_HI_1 = UINT64_C(1) << 60,
1300 OP_SEL_HI_2 = UINT64_C(1) << 14,
1301};
1302
1303} // namespace VOP3PEncoding
1304
1305namespace ImplicitArg {
1306// Implicit kernel argument offset for code object version 5.
1307enum Offset_COV5 : unsigned {
1308 HOSTCALL_PTR_OFFSET = 80,
1309 MULTIGRID_SYNC_ARG_OFFSET = 88,
1310 HEAP_PTR_OFFSET = 96,
1311
1312 DEFAULT_QUEUE_OFFSET = 104,
1313 COMPLETION_ACTION_OFFSET = 112,
1314
1315 PRIVATE_BASE_OFFSET = 192,
1316 SHARED_BASE_OFFSET = 196,
1317 QUEUE_PTR_OFFSET = 200,
1318};
1319
1320} // namespace ImplicitArg
1321
1322namespace MFMAScaleFormats {
1323// Enum value used in cbsz/blgp for F8F6F4 MFMA operations to select the matrix
1324// format.
1325enum MFMAScaleFormats {
1326 FP8_E4M3 = 0,
1327 FP8_E5M2 = 1,
1328 FP6_E2M3 = 2,
1329 FP6_E3M2 = 3,
1330 FP4_E2M1 = 4
1331};
1332} // namespace MFMAScaleFormats
1333
1334namespace VirtRegFlag {
1335// Virtual register flags used for various target specific handlings during
1336// codegen.
1337enum Register_Flag : uint8_t {
1338 // Register operand in a whole-wave mode operation.
1339 WWM_REG = 1 << 0,
1340};
1341
1342} // namespace VirtRegFlag
1343
1344} // namespace AMDGPU
1345
1346namespace AMDGPU {
1347namespace Barrier {
1348
1349enum Type {
1350 CLUSTER_TRAP = -4,
1351 CLUSTER = -3,
1352 TRAP = -2,
1353 WORKGROUP = -1,
1354 NAMED_BARRIER_FIRST = 1,
1355 NAMED_BARRIER_LAST = 16,
1356};
1357
1358enum {
1359 BARRIER_SCOPE_WORKGROUP = 0,
1360};
1361
1362} // namespace Barrier
1363} // namespace AMDGPU
1364
1365// clang-format off
1366
1367#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1368#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1369#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1370#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1371#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1372#define C_00B028_MEM_ORDERED 0xFDFFFFFF
1373
1374#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1375#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1376#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1377#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1378#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1379#define C_00B128_MEM_ORDERED 0xF7FFFFFF
1380
1381#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1382#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1383#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1384#define C_00B228_WGP_MODE 0xF7FFFFFF
1385#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1386#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1387#define C_00B228_MEM_ORDERED 0xFDFFFFFF
1388
1389#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1390#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1391#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1392#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1393#define C_00B428_WGP_MODE 0xFBFFFFFF
1394#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1395#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1396#define C_00B428_MEM_ORDERED 0xFEFFFFFF
1397
1398#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1399
1400#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1401#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1402#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1403#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1404#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1405#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1406#define C_00B84C_USER_SGPR 0xFFFFFFC1
1407#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1408#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1409#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1410#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1411#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1412#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1413#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1414#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1415#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1416#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1417#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1418#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1419#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1420#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1421#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1422#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1423#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1424#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1425/* CIK */
1426#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1427#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1428#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1429/* */
1430#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1431#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1432#define C_00B84C_LDS_SIZE 0xFF007FFF
1433#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1434#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1435#define C_00B84C_EXCP_EN 0x80FFFFFF
1436
1437#define S_00B84C_USER_SGPR_GFX1250(x) (((x) & 0x3F) << 1)
1438#define G_00B84C_USER_SGPR_GFX1250(x) (((x) >> 1) & 0x3F)
1439#define C_00B84C_USER_SGPR_GFX1250 0xFFFFFF81
1440
1441#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1442#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1443
1444#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1445#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1446#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1447#define C_00B848_VGPRS 0xFFFFFFC0
1448#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1449#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1450#define C_00B848_SGPRS 0xFFFFFC3F
1451#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1452#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1453#define C_00B848_PRIORITY 0xFFFFF3FF
1454#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1455#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1456#define C_00B848_FLOAT_MODE 0xFFF00FFF
1457#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1458#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1459#define C_00B848_PRIV 0xFFEFFFFF
1460#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1461#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1462#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1463#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1464#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1465#define C_00B848_RR_WG_MODE 0xFFDFFFFF
1466#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1467#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1468#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1469#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1470#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1471#define C_00B848_IEEE_MODE 0xFF7FFFFF
1472#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1473#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1474#define C_00B848_WGP_MODE 0xDFFFFFFF
1475#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1476#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1477#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1478#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1479#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1480#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1481
1482// Helpers for setting FLOAT_MODE
1483#define FP_ROUND_ROUND_TO_NEAREST 0
1484#define FP_ROUND_ROUND_TO_INF 1
1485#define FP_ROUND_ROUND_TO_NEGINF 2
1486#define FP_ROUND_ROUND_TO_ZERO 3
1487
1488// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1489// precision.
1490#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1491#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1492
1493#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1494#define FP_DENORM_FLUSH_OUT 1
1495#define FP_DENORM_FLUSH_IN 2
1496#define FP_DENORM_FLUSH_NONE 3
1497
1498
1499// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1500// precision.
1501#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1502#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1503
1504#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1505#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1506#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1507#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1508
1509#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1510#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1511#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1512#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1513
1514#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1515#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1516#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1517#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1518#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1519#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1520#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1521#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1522
1523#define R_SPILLED_SGPRS 0x4
1524#define R_SPILLED_VGPRS 0x8
1525
1526// clang-format on
1527
1528} // End namespace llvm
1529
1530#endif
1531