1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInst.h"
14#include "llvm/MC/MCInstrDesc.h"
15#include "llvm/MC/MCInstrInfo.h"
16#include "llvm/Support/AMDGPUAddrSpace.h"
17
18namespace llvm {
19
20// This needs to be kept in sync with the field bits in SIRegisterClass.
21enum SIRCFlags : uint8_t {
22 RegTupleAlignUnitsWidth = 2,
23 HasVGPRBit = RegTupleAlignUnitsWidth,
24 HasAGPRBit,
25 HasSGPRbit,
26
27 HasVGPR = 1 << HasVGPRBit,
28 HasAGPR = 1 << HasAGPRBit,
29 HasSGPR = 1 << HasSGPRbit,
30
31 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
32 RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
33}; // enum SIRCFlagsr
34
35namespace SIEncodingFamily {
36// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
37// and the columns of the getMCOpcodeGen table.
38enum {
39 SI = 0,
40 VI = 1,
41 SDWA = 2,
42 SDWA9 = 3,
43 GFX80 = 4,
44 GFX9 = 5,
45 GFX10 = 6,
46 SDWA10 = 7,
47 GFX90A = 8,
48 GFX940 = 9,
49 GFX11 = 10,
50 GFX1170 = 11,
51 GFX12 = 12,
52 GFX1250 = 13,
53 GFX13 = 14,
54};
55}
56
57namespace SIInstrFlags {
58
59// Raw TSFlags bit constants — use the predicate functions below instead of
60// testing these directly. This namespace makes accidental direct use a
61// compile error outside of SIDefines.h itself.
62namespace DontUseRawTSFlags {
63// This needs to be kept in sync with the field bits in InstSI.
64enum : uint64_t {
65 // Low bits - basic encoding information.
66 SALU = 1 << 0,
67 VALU = 1 << 1,
68
69 // SALU instruction formats.
70 SOP1 = 1 << 2,
71 SOP2 = 1 << 3,
72 SOPC = 1 << 4,
73 SOPK = 1 << 5,
74 SOPP = 1 << 6,
75
76 // VALU instruction formats.
77 VOP1 = 1 << 7,
78 VOP2 = 1 << 8,
79 VOPC = 1 << 9,
80
81 // TODO: Should this be spilt into VOP3 a and b?
82 VOP3 = 1 << 10,
83 VOP3P = 1 << 12,
84
85 VINTRP = 1 << 13,
86 SDWA = 1 << 14,
87 DPP = 1 << 15,
88 TRANS = 1 << 16,
89
90 // Memory instruction formats.
91 MUBUF = 1 << 17,
92 MTBUF = 1 << 18,
93 SMRD = 1 << 19,
94 MIMG = 1 << 20,
95 VIMAGE = 1 << 21,
96 VSAMPLE = 1 << 22,
97 EXP = 1 << 23,
98 FLAT = 1 << 24,
99 DS = 1 << 25,
100
101 // Combined SGPR/VGPR Spill bit
102 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill
103 Spill = 1 << 26,
104
105 // LDSDIR instruction format.
106 LDSDIR = 1 << 28,
107
108 // VINTERP instruction format.
109 VINTERP = 1 << 29,
110
111 VOPD3 = 1 << 30,
112
113 // High bits - other information.
114 VM_CNT = UINT64_C(1) << 32,
115 EXP_CNT = UINT64_C(1) << 33,
116 LGKM_CNT = UINT64_C(1) << 34,
117
118 WQM = UINT64_C(1) << 35,
119 DisableWQM = UINT64_C(1) << 36,
120 Gather4 = UINT64_C(1) << 37,
121
122 TENSOR_CNT = UINT64_C(1) << 38,
123
124 SCALAR_STORE = UINT64_C(1) << 39,
125 FIXED_SIZE = UINT64_C(1) << 40,
126
127 ASYNC_CNT = UINT64_C(1) << 41,
128
129 VOP3_OPSEL = UINT64_C(1) << 42,
130 maybeAtomic = UINT64_C(1) << 43,
131
132 // Is a clamp on FP type.
133 FPClamp = UINT64_C(1) << 45,
134
135 // Is an integer clamp
136 IntClamp = UINT64_C(1) << 46,
137
138 // Clamps lo component of register.
139 ClampLo = UINT64_C(1) << 47,
140
141 // Clamps hi component of register.
142 // ClampLo and ClampHi set for packed clamp.
143 ClampHi = UINT64_C(1) << 48,
144
145 // Is a packed VOP3P instruction.
146 IsPacked = UINT64_C(1) << 49,
147
148 // FLAT instruction accesses FLAT_GLBL segment.
149 FlatGlobal = UINT64_C(1) << 51,
150
151 // Uses floating point double precision rounding mode
152 FPDPRounding = UINT64_C(1) << 52,
153
154 // Instruction is FP atomic.
155 FPAtomic = UINT64_C(1) << 53,
156
157 // Is a MFMA instruction.
158 IsMAI = UINT64_C(1) << 54,
159
160 // Is a DOT instruction.
161 IsDOT = UINT64_C(1) << 55,
162
163 // FLAT instruction accesses FLAT_SCRATCH segment.
164 FlatScratch = UINT64_C(1) << 56,
165
166 // Atomic without return.
167 IsAtomicNoRet = UINT64_C(1) << 57,
168
169 // Atomic with return.
170 IsAtomicRet = UINT64_C(1) << 58,
171
172 // Is a WMMA instruction.
173 IsWMMA = UINT64_C(1) << 59,
174
175 // Whether tied sources will be read.
176 TiedSourceNotRead = UINT64_C(1) << 60,
177
178 // Is never uniform.
179 IsNeverUniform = UINT64_C(1) << 61,
180
181 // ds_gws_* instructions.
182 GWS = UINT64_C(1) << 62,
183
184 // Is a SWMMAC instruction.
185 IsSWMMAC = UINT64_C(1) << 63,
186};
187} // namespace DontUseRawTSFlags
188
189// Predicate functions over TSFlags — the single place where raw TSFlags bit
190// tests are written. All callers (SIInstrInfo methods, MC-layer code) go
191// through these so that bit-layout changes require updating only this file.
192//
193// getTSFlags is overloaded for MCInstrDesc, (MCInstrInfo, Opcode), and
194// (MCInstrInfo, MCInst) here; SIInstrInfo.h adds a MachineInstr overload in
195// namespace llvm so ADL finds it when predicates are instantiated with
196// MachineInstr.
197
198constexpr uint64_t getTSFlags(const MCInstrDesc &Desc) { return Desc.TSFlags; }
199inline uint64_t getTSFlags(const MCInstrInfo &MII, unsigned Opcode) {
200 return MII.get(Opcode).TSFlags;
201}
202inline uint64_t getTSFlags(const MCInstrInfo &MII, const MCInst &Inst) {
203 return MII.get(Opcode: Inst.getOpcode()).TSFlags;
204}
205
206template <typename... T> constexpr bool isSALU(const T &...O) {
207 return getTSFlags(O...) & DontUseRawTSFlags::SALU;
208}
209template <typename... T> constexpr bool isVALU(const T &...O) {
210 return getTSFlags(O...) & DontUseRawTSFlags::VALU;
211}
212template <typename... T> constexpr bool isSOP1(const T &...O) {
213 return getTSFlags(O...) & DontUseRawTSFlags::SOP1;
214}
215template <typename... T> constexpr bool isSOP2(const T &...O) {
216 return getTSFlags(O...) & DontUseRawTSFlags::SOP2;
217}
218template <typename... T> constexpr bool isSOPC(const T &...O) {
219 return getTSFlags(O...) & DontUseRawTSFlags::SOPC;
220}
221template <typename... T> constexpr bool isSOPK(const T &...O) {
222 return getTSFlags(O...) & DontUseRawTSFlags::SOPK;
223}
224template <typename... T> constexpr bool isSOPP(const T &...O) {
225 return getTSFlags(O...) & DontUseRawTSFlags::SOPP;
226}
227template <typename... T> constexpr bool isVOP1(const T &...O) {
228 return getTSFlags(O...) & DontUseRawTSFlags::VOP1;
229}
230template <typename... T> constexpr bool isVOP2(const T &...O) {
231 return getTSFlags(O...) & DontUseRawTSFlags::VOP2;
232}
233template <typename... T> constexpr bool isVOPC(const T &...O) {
234 return getTSFlags(O...) & DontUseRawTSFlags::VOPC;
235}
236template <typename... T> constexpr bool isVOP3(const T &...O) {
237 return getTSFlags(O...) & DontUseRawTSFlags::VOP3;
238}
239template <typename... T> constexpr bool isVOP3P(const T &...O) {
240 return getTSFlags(O...) & DontUseRawTSFlags::VOP3P;
241}
242template <typename... T> constexpr bool isVOP3Like(const T &...O) {
243 return getTSFlags(O...) &
244 (DontUseRawTSFlags::VOP3 | DontUseRawTSFlags::VOP3P);
245}
246template <typename... T> constexpr bool isVINTRP(const T &...O) {
247 return getTSFlags(O...) & DontUseRawTSFlags::VINTRP;
248}
249template <typename... T> constexpr bool isSDWA(const T &...O) {
250 return getTSFlags(O...) & DontUseRawTSFlags::SDWA;
251}
252template <typename... T> constexpr bool isDPP(const T &...O) {
253 return getTSFlags(O...) & DontUseRawTSFlags::DPP;
254}
255template <typename... T> constexpr bool isTRANS(const T &...O) {
256 return getTSFlags(O...) & DontUseRawTSFlags::TRANS;
257}
258template <typename... T> constexpr bool isMUBUF(const T &...O) {
259 return getTSFlags(O...) & DontUseRawTSFlags::MUBUF;
260}
261template <typename... T> constexpr bool isMTBUF(const T &...O) {
262 return getTSFlags(O...) & DontUseRawTSFlags::MTBUF;
263}
264template <typename... T> constexpr bool isBuffer(const T &...O) {
265 return getTSFlags(O...) &
266 (DontUseRawTSFlags::MUBUF | DontUseRawTSFlags::MTBUF);
267}
268template <typename... T> constexpr bool isSMRD(const T &...O) {
269 return getTSFlags(O...) & DontUseRawTSFlags::SMRD;
270}
271template <typename... T> constexpr bool isMIMG(const T &...O) {
272 return getTSFlags(O...) & DontUseRawTSFlags::MIMG;
273}
274template <typename... T> constexpr bool isVIMAGE(const T &...O) {
275 return getTSFlags(O...) & DontUseRawTSFlags::VIMAGE;
276}
277template <typename... T> constexpr bool isVSAMPLE(const T &...O) {
278 return getTSFlags(O...) & DontUseRawTSFlags::VSAMPLE;
279}
280template <typename... T> constexpr bool isEXP(const T &...O) {
281 return getTSFlags(O...) & DontUseRawTSFlags::EXP;
282}
283template <typename... T> constexpr bool isFLAT(const T &...O) {
284 return getTSFlags(O...) & DontUseRawTSFlags::FLAT;
285}
286template <typename... T> constexpr bool isDS(const T &...O) {
287 return getTSFlags(O...) & DontUseRawTSFlags::DS;
288}
289template <typename... T> constexpr bool isSpill(const T &...O) {
290 return getTSFlags(O...) & DontUseRawTSFlags::Spill;
291}
292template <typename... T> constexpr bool isLDSDIR(const T &...O) {
293 return getTSFlags(O...) & DontUseRawTSFlags::LDSDIR;
294}
295template <typename... T> constexpr bool isVINTERP(const T &...O) {
296 return getTSFlags(O...) & DontUseRawTSFlags::VINTERP;
297}
298template <typename... T> constexpr bool isWQM(const T &...O) {
299 return getTSFlags(O...) & DontUseRawTSFlags::WQM;
300}
301template <typename... T> constexpr bool isDisableWQM(const T &...O) {
302 return getTSFlags(O...) & DontUseRawTSFlags::DisableWQM;
303}
304template <typename... T> constexpr bool isGather4(const T &...O) {
305 return getTSFlags(O...) & DontUseRawTSFlags::Gather4;
306}
307template <typename... T> constexpr bool usesTENSOR_CNT(const T &...O) {
308 return getTSFlags(O...) & DontUseRawTSFlags::TENSOR_CNT;
309}
310template <typename... T> constexpr bool isScalarStore(const T &...O) {
311 return getTSFlags(O...) & DontUseRawTSFlags::SCALAR_STORE;
312}
313template <typename... T> constexpr bool isFixedSize(const T &...O) {
314 return getTSFlags(O...) & DontUseRawTSFlags::FIXED_SIZE;
315}
316template <typename... T> constexpr bool usesASYNC_CNT(const T &...O) {
317 return getTSFlags(O...) & DontUseRawTSFlags::ASYNC_CNT;
318}
319template <typename... T> constexpr bool hasVOP3OpSel(const T &...O) {
320 return getTSFlags(O...) & DontUseRawTSFlags::VOP3_OPSEL;
321}
322template <typename... T> constexpr bool isMaybeAtomic(const T &...O) {
323 return getTSFlags(O...) & DontUseRawTSFlags::maybeAtomic;
324}
325template <typename... T> constexpr bool hasFPClamp(const T &...O) {
326 return getTSFlags(O...) & DontUseRawTSFlags::FPClamp;
327}
328template <typename... T> constexpr bool hasIntClamp(const T &...O) {
329 return getTSFlags(O...) & DontUseRawTSFlags::IntClamp;
330}
331template <typename... T> constexpr bool hasClampLo(const T &...O) {
332 return getTSFlags(O...) & DontUseRawTSFlags::ClampLo;
333}
334template <typename... T> constexpr bool hasClampHi(const T &...O) {
335 return getTSFlags(O...) & DontUseRawTSFlags::ClampHi;
336}
337template <typename... T> constexpr bool isPacked(const T &...O) {
338 return getTSFlags(O...) & DontUseRawTSFlags::IsPacked;
339}
340template <typename... T> constexpr bool isFlatGlobal(const T &...O) {
341 return getTSFlags(O...) & DontUseRawTSFlags::FlatGlobal;
342}
343template <typename... T> constexpr bool usesFPDPRounding(const T &...O) {
344 return getTSFlags(O...) & DontUseRawTSFlags::FPDPRounding;
345}
346template <typename... T> constexpr bool isFPAtomic(const T &...O) {
347 return getTSFlags(O...) & DontUseRawTSFlags::FPAtomic;
348}
349template <typename... T> constexpr bool isMAI(const T &...O) {
350 return getTSFlags(O...) & DontUseRawTSFlags::IsMAI;
351}
352template <typename... T> constexpr bool isDOT(const T &...O) {
353 return getTSFlags(O...) & DontUseRawTSFlags::IsDOT;
354}
355template <typename... T> constexpr bool isFlatScratch(const T &...O) {
356 return getTSFlags(O...) & DontUseRawTSFlags::FlatScratch;
357}
358template <typename... T> constexpr bool isAtomicNoRet(const T &...O) {
359 return getTSFlags(O...) & DontUseRawTSFlags::IsAtomicNoRet;
360}
361template <typename... T> constexpr bool isAtomicRet(const T &...O) {
362 return getTSFlags(O...) & DontUseRawTSFlags::IsAtomicRet;
363}
364template <typename... T> constexpr bool isWMMA(const T &...O) {
365 return getTSFlags(O...) & DontUseRawTSFlags::IsWMMA;
366}
367template <typename... T> constexpr bool isTiedSourceNotRead(const T &...O) {
368 return getTSFlags(O...) & DontUseRawTSFlags::TiedSourceNotRead;
369}
370template <typename... T> constexpr bool isNeverUniform(const T &...O) {
371 return getTSFlags(O...) & DontUseRawTSFlags::IsNeverUniform;
372}
373template <typename... T> constexpr bool isGWS(const T &...O) {
374 return getTSFlags(O...) & DontUseRawTSFlags::GWS;
375}
376template <typename... T> constexpr bool isSWMMAC(const T &...O) {
377 return getTSFlags(O...) & DontUseRawTSFlags::IsSWMMAC;
378}
379template <typename... T> constexpr bool isVOPD3(const T &...O) {
380 return getTSFlags(O...) & DontUseRawTSFlags::VOPD3;
381}
382template <typename... T> constexpr bool usesVM_CNT(const T &...O) {
383 return getTSFlags(O...) & DontUseRawTSFlags::VM_CNT;
384}
385template <typename... T> constexpr bool usesLGKM_CNT(const T &...O) {
386 return getTSFlags(O...) & DontUseRawTSFlags::LGKM_CNT;
387}
388
389// Compound predicates.
390template <typename... T> constexpr bool isAtomic(const T &...O) {
391 return isAtomicNoRet(O...) || isAtomicRet(O...);
392}
393template <typename... T> constexpr bool isSegmentSpecificFLAT(const T &...O) {
394 return isFlatGlobal(O...) || isFlatScratch(O...);
395}
396// Any image-family instruction: pre-gfx11 MIMG, gfx11+ VIMAGE or VSAMPLE.
397template <typename... T> constexpr bool isImage(const T &...O) {
398 return isMIMG(O...) || isVIMAGE(O...) || isVSAMPLE(O...);
399}
400// Vector memory: buffer + image + flat.
401template <typename... T> constexpr bool isVMEM(const T &...O) {
402 return isMUBUF(O...) || isMTBUF(O...) || isImage(O...) || isFLAT(O...);
403}
404
405// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
406// The result is true if any of these tests are true.
407enum ClassFlags : unsigned {
408 S_NAN = 1 << 0, // Signaling NaN
409 Q_NAN = 1 << 1, // Quiet NaN
410 N_INFINITY = 1 << 2, // Negative infinity
411 N_NORMAL = 1 << 3, // Negative normal
412 N_SUBNORMAL = 1 << 4, // Negative subnormal
413 N_ZERO = 1 << 5, // Negative zero
414 P_ZERO = 1 << 6, // Positive zero
415 P_SUBNORMAL = 1 << 7, // Positive subnormal
416 P_NORMAL = 1 << 8, // Positive normal
417 P_INFINITY = 1 << 9 // Positive infinity
418};
419}
420
421namespace AMDGPU {
422
423enum OperandType : unsigned {
424 /// Operands with register, 32-bit, or 64-bit immediate
425 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
426 OPERAND_REG_IMM_INT64,
427 OPERAND_REG_IMM_INT16,
428 OPERAND_REG_IMM_FP32,
429 OPERAND_REG_IMM_FP64,
430 OPERAND_REG_IMM_BF16,
431 OPERAND_REG_IMM_FP16,
432 OPERAND_REG_IMM_NOINLINE_FP16,
433 OPERAND_REG_IMM_V2BF16,
434 OPERAND_REG_IMM_V2FP16,
435 OPERAND_REG_IMM_V2FP16_SPLAT,
436 OPERAND_REG_IMM_V2INT16,
437 OPERAND_REG_IMM_V2INT64,
438 OPERAND_REG_IMM_NOINLINE_V2FP16,
439 OPERAND_REG_IMM_V2INT32,
440 OPERAND_REG_IMM_V2FP32,
441 OPERAND_REG_IMM_V2FP64,
442
443 /// Operands with register or inline constant
444 OPERAND_REG_INLINE_C_INT16,
445 OPERAND_REG_INLINE_C_INT32,
446 OPERAND_REG_INLINE_C_INT64,
447 OPERAND_REG_INLINE_C_BF16,
448 OPERAND_REG_INLINE_C_FP16,
449 OPERAND_REG_INLINE_C_FP32,
450 OPERAND_REG_INLINE_C_FP64,
451 OPERAND_REG_INLINE_C_V2INT16,
452 OPERAND_REG_INLINE_C_V2BF16,
453 OPERAND_REG_INLINE_C_V2FP16,
454
455 // Operand for split barrier inline constant
456 OPERAND_INLINE_SPLIT_BARRIER_INT32,
457
458 /// Operand with 32-bit immediate that uses the constant bus.
459 OPERAND_KIMM32,
460 OPERAND_KIMM16,
461 OPERAND_KIMM64,
462
463 /// Operands with an AccVGPR register or inline constant
464 OPERAND_REG_INLINE_AC_INT32,
465 OPERAND_REG_INLINE_AC_FP32,
466 OPERAND_REG_INLINE_AC_FP64,
467
468 // Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline
469 // constants. Does not accept registers.
470 OPERAND_INLINE_C_AV64_PSEUDO,
471
472 // Operand for source modifiers for VOP instructions
473 OPERAND_INPUT_MODS,
474
475 // Operand for SDWA instructions
476 OPERAND_SDWA_VOPC_DST,
477
478 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
479 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP64,
480
481 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
482 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,
483
484 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,
485 OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO,
486
487 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
488 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
489
490 OPERAND_KIMM_FIRST = OPERAND_KIMM32,
491 OPERAND_KIMM_LAST = OPERAND_KIMM64
492
493};
494}
495
496// Input operand modifiers bit-masks
497// NEG and SEXT share same bit-mask because they can't be set simultaneously.
498namespace SISrcMods {
499enum : unsigned {
500 NONE = 0,
501 NEG = 1 << 0, // Floating-point negate modifier
502 ABS = 1 << 1, // Floating-point absolute modifier
503 SEXT = 1 << 4, // Integer sign-extend modifier
504 NEG_HI = ABS, // Floating-point negate high packed component modifier.
505 OP_SEL_0 = 1 << 2,
506 OP_SEL_1 = 1 << 3,
507 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
508};
509}
510
511namespace SIOutMods {
512 enum : unsigned {
513 NONE = 0,
514 MUL2 = 1,
515 MUL4 = 2,
516 DIV2 = 3
517 };
518}
519
520namespace AMDGPU {
521namespace VGPRIndexMode {
522
523enum Id : unsigned { // id of symbolic names
524 ID_SRC0 = 0,
525 ID_SRC1,
526 ID_SRC2,
527 ID_DST,
528
529 ID_MIN = ID_SRC0,
530 ID_MAX = ID_DST
531};
532
533enum EncBits : unsigned {
534 OFF = 0,
535 SRC0_ENABLE = 1 << ID_SRC0,
536 SRC1_ENABLE = 1 << ID_SRC1,
537 SRC2_ENABLE = 1 << ID_SRC2,
538 DST_ENABLE = 1 << ID_DST,
539 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
540 UNDEF = 0xFFFF
541};
542
543} // namespace VGPRIndexMode
544} // namespace AMDGPU
545
546namespace AMDGPUAsmVariants {
547 enum : unsigned {
548 DEFAULT = 0,
549 VOP3 = 1,
550 SDWA = 2,
551 SDWA9 = 3,
552 DPP = 4,
553 VOP3_DPP = 5
554 };
555} // namespace AMDGPUAsmVariants
556
557namespace AMDGPU {
558namespace EncValues { // Encoding values of enum9/8/7 operands
559
560enum : unsigned {
561 SGPR_MIN = 0,
562 SGPR_MAX_SI = 101,
563 SGPR_MAX_GFX10 = 105,
564 TTMP_VI_MIN = 112,
565 TTMP_VI_MAX = 123,
566 TTMP_GFX9PLUS_MIN = 108,
567 TTMP_GFX9PLUS_MAX = 123,
568 INLINE_INTEGER_C_MIN = 128,
569 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
570 INLINE_INTEGER_C_MAX = 208,
571 INLINE_FLOATING_C_MIN = 240,
572 INLINE_FLOATING_C_MAX = 248,
573 LITERAL64_CONST = 254,
574 LITERAL_CONST = 255,
575 VGPR_MIN = 256,
576 VGPR_MAX = 511,
577 IS_VGPR = 256, // Indicates VGPR or AGPR
578};
579
580} // namespace EncValues
581
582// Register codes as defined in the TableGen's HWEncoding field.
583namespace HWEncoding {
584enum : unsigned {
585 REG_IDX_MASK = 0x3ff,
586 LO256_REG_IDX_MASK = 0xff,
587 IS_VGPR = 1 << 10,
588 IS_AGPR = 1 << 11,
589 IS_HI16 = 1 << 12,
590};
591} // namespace HWEncoding
592
593namespace CPol {
594
595enum CPol {
596 GLC = 1,
597 SLC = 2,
598 DLC = 4,
599 SCC = 16,
600 SC0 = GLC,
601 SC1 = SCC,
602 NT = SLC,
603 ALL_pregfx12 = GLC | SLC | DLC | SCC,
604 SWZ_pregfx12 = 8,
605
606 // Below are GFX12+ cache policy bits
607
608 // Temporal hint
609 TH = 0x7, // All TH bits
610 TH_RT = 0, // regular
611 TH_NT = 1, // non-temporal
612 TH_HT = 2, // high-temporal
613 TH_LU = 3, // last use
614 TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
615 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
616 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
617 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
618 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)
619 TH_BYPASS = 3, // only to be used with scope = 3
620
621 TH_RESERVED = 7, // unused value for load insts
622
623 // Bits of TH for atomics
624 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
625 TH_ATOMIC_NT = SLC, // Non-temporal vs regular
626 TH_ATOMIC_CASCADE = 4, // Cascading vs regular
627
628 // Scope
629 SCOPE_SHIFT = 3,
630 SCOPE_MASK = 0x3,
631 SCOPE = SCOPE_MASK << SCOPE_SHIFT, // All Scope bits
632 SCOPE_CU = 0 << SCOPE_SHIFT,
633 SCOPE_SE = 1 << SCOPE_SHIFT,
634 SCOPE_DEV = 2 << SCOPE_SHIFT,
635 SCOPE_SYS = 3 << SCOPE_SHIFT,
636
637 NV = 1 << 5, // Non-volatile bit
638
639 SWZ = 1 << 6, // Swizzle bit
640
641 SCAL = 1 << 11, // Scale offset bit
642
643 ALL = TH | SCOPE | NV,
644
645 // Helper bits
646 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy
647 TH_TYPE_STORE = 1 << 8, // TH_STORE policy
648 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy
649 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
650
651 // Volatile (used to preserve/signal operation volatility for buffer
652 // operations not a real instruction bit)
653 VOLATILE = 1 << 31,
654 // The set of "cache policy" bits used for compiler features that
655 // do not correspond to handware features.
656 VIRTUAL_BITS = VOLATILE,
657};
658
659} // namespace CPol
660
661namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
662
663enum Id { // Message ID, width(4) [3:0].
664 ID_INTERRUPT = 1,
665
666 ID_GS_PreGFX11 = 2, // replaced in GFX11
667 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
668
669 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
670 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
671
672 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
673 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12
674 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12
675 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
676 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
677 ID_GS_ALLOC_REQ = 9, // added in GFX9
678 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
679 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
680 ID_SYSMSG = 15,
681
682 ID_RTN_GET_DOORBELL = 128,
683 ID_RTN_GET_DDID = 129,
684 ID_RTN_GET_TMA = 130,
685 ID_RTN_GET_REALTIME = 131,
686 ID_RTN_SAVE_WAVE = 132,
687 ID_RTN_GET_TBA = 133,
688 ID_RTN_GET_TBA_TO_PC = 134,
689 ID_RTN_GET_SE_AID_ID = 135,
690
691 ID_RTN_GET_CLUSTER_BARRIER_STATE = 136, // added in GFX1250
692 ID_RTN_SAVE_WAVE_HAS_TDM = 152, // added in GFX1250
693
694 ID_MASK_PreGFX11_ = 0xF,
695 ID_MASK_GFX11Plus_ = 0xFF
696};
697
698enum Op { // Both GS and SYS operation IDs.
699 OP_SHIFT_ = 4,
700 OP_NONE_ = 0,
701 // Bits used for operation encoding
702 OP_WIDTH_ = 3,
703 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
704 // GS operations are encoded in bits 5:4
705 OP_GS_NOP = 0,
706 OP_GS_CUT = 1,
707 OP_GS_EMIT = 2,
708 OP_GS_EMIT_CUT = 3,
709 OP_GS_FIRST_ = OP_GS_NOP,
710 // SYS operations are encoded in bits 6:4
711 OP_SYS_ECC_ERR_INTERRUPT = 1,
712 OP_SYS_REG_RD = 2,
713 OP_SYS_HOST_TRAP_ACK = 3,
714 OP_SYS_TTRACE_PC = 4,
715 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
716};
717
718enum StreamId : unsigned { // Stream ID, (2) [9:8].
719 STREAM_ID_NONE_ = 0,
720 STREAM_ID_DEFAULT_ = 0,
721 STREAM_ID_LAST_ = 4,
722 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
723 STREAM_ID_SHIFT_ = 8,
724 STREAM_ID_WIDTH_= 2,
725 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
726};
727
728} // namespace SendMsg
729
730namespace WaitEvent { // Encoding of SIMM16 used in s_wait_event
731enum Id {
732 DONT_WAIT_EXPORT_READY = 1 << 0, // Only used in gfx11
733 EXPORT_READY = 1 << 1, // gfx12+
734};
735
736} // namespace WaitEvent
737
738namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
739
740enum Id { // HwRegCode, (6) [5:0]
741 ID_MODE = 1,
742 ID_STATUS = 2,
743 ID_TRAPSTS = 3,
744 ID_HW_ID = 4,
745 ID_GPR_ALLOC = 5,
746 ID_LDS_ALLOC = 6,
747 ID_IB_STS = 7,
748 ID_PERF_SNAPSHOT_DATA_gfx12 = 10,
749 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,
750 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,
751 ID_MEM_BASES = 15,
752 ID_TBA_LO = 16,
753 ID_TBA_HI = 17,
754 ID_TMA_LO = 18,
755 ID_TMA_HI = 19,
756 ID_FLAT_SCR_LO = 20,
757 ID_FLAT_SCR_HI = 21,
758 ID_XNACK_MASK = 22,
759 ID_HW_ID1 = 23,
760 ID_HW_ID2 = 24,
761 ID_POPS_PACKER = 25,
762 ID_SCHED_MODE = 26,
763 ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
764 ID_IB_STS2 = 28,
765 ID_SHADER_CYCLES = 29,
766 ID_SHADER_CYCLES_HI = 30,
767 ID_DVGPR_ALLOC_LO = 31,
768 ID_DVGPR_ALLOC_HI = 32,
769
770 // Register numbers reused in GFX11
771 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,
772 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,
773
774 // Register numbers reused in GFX12+
775 ID_STATE_PRIV = 4,
776 ID_PERF_SNAPSHOT_DATA1 = 15,
777 ID_PERF_SNAPSHOT_DATA2 = 16,
778 ID_EXCP_FLAG_PRIV = 17,
779 ID_EXCP_FLAG_USER = 18,
780 ID_TRAP_CTRL = 19,
781
782 // GFX94* specific registers
783 ID_XCC_ID = 20,
784 ID_SQ_PERF_SNAPSHOT_DATA = 21,
785 ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
786 ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
787 ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
788
789 // GFX1250
790 ID_XNACK_STATE_PRIV = 33,
791 ID_XNACK_MASK_gfx1250 = 34,
792};
793
794enum Offset : unsigned { // Offset, (5) [10:6]
795 OFFSET_MEM_VIOL = 8,
796 OFFSET_ME_ID = 8, // in HW_ID2
797};
798
799enum ModeRegisterMasks : uint32_t {
800 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
801 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
802 DX10_CLAMP_MASK = 1 << 8,
803 IEEE_MODE_MASK = 1 << 9,
804 LOD_CLAMP_MASK = 1 << 10,
805 DEBUG_MASK = 1 << 11,
806
807 // EXCP_EN fields.
808 EXCP_EN_INVALID_MASK = 1 << 12,
809 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
810 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
811 EXCP_EN_OVERFLOW_MASK = 1 << 15,
812 EXCP_EN_UNDERFLOW_MASK = 1 << 16,
813 EXCP_EN_INEXACT_MASK = 1 << 17,
814 EXCP_EN_INT_DIV0_MASK = 1 << 18,
815
816 GPR_IDX_EN_MASK = 1 << 27,
817 VSKIP_MASK = 1 << 28,
818 CSP_MASK = 0x7u << 29, // Bits 29..31
819
820 // GFX1250
821 DST_VGPR_MSB = 0x3 << 12,
822 SRC0_VGPR_MSB = 0x3 << 14,
823 SRC1_VGPR_MSB = 0x3 << 16,
824 SRC2_VGPR_MSB = 0x3 << 18,
825 VGPR_MSB_MASK = 0xff << 12, // Bits 12..19
826
827 REPLAY_MODE = 1 << 25,
828 FLAT_SCRATCH_IS_NV = 1 << 26,
829};
830
831} // namespace Hwreg
832
833namespace MTBUFFormat {
834
835enum DataFormat : int64_t {
836 DFMT_INVALID = 0,
837 DFMT_8,
838 DFMT_16,
839 DFMT_8_8,
840 DFMT_32,
841 DFMT_16_16,
842 DFMT_10_11_11,
843 DFMT_11_11_10,
844 DFMT_10_10_10_2,
845 DFMT_2_10_10_10,
846 DFMT_8_8_8_8,
847 DFMT_32_32,
848 DFMT_16_16_16_16,
849 DFMT_32_32_32,
850 DFMT_32_32_32_32,
851 DFMT_RESERVED_15,
852
853 DFMT_MIN = DFMT_INVALID,
854 DFMT_MAX = DFMT_RESERVED_15,
855
856 DFMT_UNDEF = -1,
857 DFMT_DEFAULT = DFMT_8,
858
859 DFMT_SHIFT = 0,
860 DFMT_MASK = 0xF
861};
862
863enum NumFormat : int64_t {
864 NFMT_UNORM = 0,
865 NFMT_SNORM,
866 NFMT_USCALED,
867 NFMT_SSCALED,
868 NFMT_UINT,
869 NFMT_SINT,
870 NFMT_RESERVED_6, // VI and GFX9
871 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
872 NFMT_FLOAT,
873
874 NFMT_MIN = NFMT_UNORM,
875 NFMT_MAX = NFMT_FLOAT,
876
877 NFMT_UNDEF = -1,
878 NFMT_DEFAULT = NFMT_UNORM,
879
880 NFMT_SHIFT = 4,
881 NFMT_MASK = 7
882};
883
884enum MergedFormat : int64_t {
885 DFMT_NFMT_UNDEF = -1,
886 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
887 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
888
889
890 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
891
892 DFMT_NFMT_MAX = DFMT_NFMT_MASK
893};
894
895enum UnifiedFormatCommon : int64_t {
896 UFMT_MAX = 127,
897 UFMT_UNDEF = -1,
898 UFMT_DEFAULT = 1
899};
900
901} // namespace MTBUFFormat
902
903namespace UfmtGFX10 {
904enum UnifiedFormat : int64_t {
905 UFMT_INVALID = 0,
906
907 UFMT_8_UNORM,
908 UFMT_8_SNORM,
909 UFMT_8_USCALED,
910 UFMT_8_SSCALED,
911 UFMT_8_UINT,
912 UFMT_8_SINT,
913
914 UFMT_16_UNORM,
915 UFMT_16_SNORM,
916 UFMT_16_USCALED,
917 UFMT_16_SSCALED,
918 UFMT_16_UINT,
919 UFMT_16_SINT,
920 UFMT_16_FLOAT,
921
922 UFMT_8_8_UNORM,
923 UFMT_8_8_SNORM,
924 UFMT_8_8_USCALED,
925 UFMT_8_8_SSCALED,
926 UFMT_8_8_UINT,
927 UFMT_8_8_SINT,
928
929 UFMT_32_UINT,
930 UFMT_32_SINT,
931 UFMT_32_FLOAT,
932
933 UFMT_16_16_UNORM,
934 UFMT_16_16_SNORM,
935 UFMT_16_16_USCALED,
936 UFMT_16_16_SSCALED,
937 UFMT_16_16_UINT,
938 UFMT_16_16_SINT,
939 UFMT_16_16_FLOAT,
940
941 UFMT_10_11_11_UNORM,
942 UFMT_10_11_11_SNORM,
943 UFMT_10_11_11_USCALED,
944 UFMT_10_11_11_SSCALED,
945 UFMT_10_11_11_UINT,
946 UFMT_10_11_11_SINT,
947 UFMT_10_11_11_FLOAT,
948
949 UFMT_11_11_10_UNORM,
950 UFMT_11_11_10_SNORM,
951 UFMT_11_11_10_USCALED,
952 UFMT_11_11_10_SSCALED,
953 UFMT_11_11_10_UINT,
954 UFMT_11_11_10_SINT,
955 UFMT_11_11_10_FLOAT,
956
957 UFMT_10_10_10_2_UNORM,
958 UFMT_10_10_10_2_SNORM,
959 UFMT_10_10_10_2_USCALED,
960 UFMT_10_10_10_2_SSCALED,
961 UFMT_10_10_10_2_UINT,
962 UFMT_10_10_10_2_SINT,
963
964 UFMT_2_10_10_10_UNORM,
965 UFMT_2_10_10_10_SNORM,
966 UFMT_2_10_10_10_USCALED,
967 UFMT_2_10_10_10_SSCALED,
968 UFMT_2_10_10_10_UINT,
969 UFMT_2_10_10_10_SINT,
970
971 UFMT_8_8_8_8_UNORM,
972 UFMT_8_8_8_8_SNORM,
973 UFMT_8_8_8_8_USCALED,
974 UFMT_8_8_8_8_SSCALED,
975 UFMT_8_8_8_8_UINT,
976 UFMT_8_8_8_8_SINT,
977
978 UFMT_32_32_UINT,
979 UFMT_32_32_SINT,
980 UFMT_32_32_FLOAT,
981
982 UFMT_16_16_16_16_UNORM,
983 UFMT_16_16_16_16_SNORM,
984 UFMT_16_16_16_16_USCALED,
985 UFMT_16_16_16_16_SSCALED,
986 UFMT_16_16_16_16_UINT,
987 UFMT_16_16_16_16_SINT,
988 UFMT_16_16_16_16_FLOAT,
989
990 UFMT_32_32_32_UINT,
991 UFMT_32_32_32_SINT,
992 UFMT_32_32_32_FLOAT,
993 UFMT_32_32_32_32_UINT,
994 UFMT_32_32_32_32_SINT,
995 UFMT_32_32_32_32_FLOAT,
996
997 UFMT_FIRST = UFMT_INVALID,
998 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
999};
1000
1001} // namespace UfmtGFX10
1002
1003namespace UfmtGFX11 {
1004enum UnifiedFormat : int64_t {
1005 UFMT_INVALID = 0,
1006
1007 UFMT_8_UNORM,
1008 UFMT_8_SNORM,
1009 UFMT_8_USCALED,
1010 UFMT_8_SSCALED,
1011 UFMT_8_UINT,
1012 UFMT_8_SINT,
1013
1014 UFMT_16_UNORM,
1015 UFMT_16_SNORM,
1016 UFMT_16_USCALED,
1017 UFMT_16_SSCALED,
1018 UFMT_16_UINT,
1019 UFMT_16_SINT,
1020 UFMT_16_FLOAT,
1021
1022 UFMT_8_8_UNORM,
1023 UFMT_8_8_SNORM,
1024 UFMT_8_8_USCALED,
1025 UFMT_8_8_SSCALED,
1026 UFMT_8_8_UINT,
1027 UFMT_8_8_SINT,
1028
1029 UFMT_32_UINT,
1030 UFMT_32_SINT,
1031 UFMT_32_FLOAT,
1032
1033 UFMT_16_16_UNORM,
1034 UFMT_16_16_SNORM,
1035 UFMT_16_16_USCALED,
1036 UFMT_16_16_SSCALED,
1037 UFMT_16_16_UINT,
1038 UFMT_16_16_SINT,
1039 UFMT_16_16_FLOAT,
1040
1041 UFMT_10_11_11_FLOAT,
1042
1043 UFMT_11_11_10_FLOAT,
1044
1045 UFMT_10_10_10_2_UNORM,
1046 UFMT_10_10_10_2_SNORM,
1047 UFMT_10_10_10_2_UINT,
1048 UFMT_10_10_10_2_SINT,
1049
1050 UFMT_2_10_10_10_UNORM,
1051 UFMT_2_10_10_10_SNORM,
1052 UFMT_2_10_10_10_USCALED,
1053 UFMT_2_10_10_10_SSCALED,
1054 UFMT_2_10_10_10_UINT,
1055 UFMT_2_10_10_10_SINT,
1056
1057 UFMT_8_8_8_8_UNORM,
1058 UFMT_8_8_8_8_SNORM,
1059 UFMT_8_8_8_8_USCALED,
1060 UFMT_8_8_8_8_SSCALED,
1061 UFMT_8_8_8_8_UINT,
1062 UFMT_8_8_8_8_SINT,
1063
1064 UFMT_32_32_UINT,
1065 UFMT_32_32_SINT,
1066 UFMT_32_32_FLOAT,
1067
1068 UFMT_16_16_16_16_UNORM,
1069 UFMT_16_16_16_16_SNORM,
1070 UFMT_16_16_16_16_USCALED,
1071 UFMT_16_16_16_16_SSCALED,
1072 UFMT_16_16_16_16_UINT,
1073 UFMT_16_16_16_16_SINT,
1074 UFMT_16_16_16_16_FLOAT,
1075
1076 UFMT_32_32_32_UINT,
1077 UFMT_32_32_32_SINT,
1078 UFMT_32_32_32_FLOAT,
1079 UFMT_32_32_32_32_UINT,
1080 UFMT_32_32_32_32_SINT,
1081 UFMT_32_32_32_32_FLOAT,
1082
1083 UFMT_FIRST = UFMT_INVALID,
1084 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
1085};
1086
1087} // namespace UfmtGFX11
1088
1089namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
1090
1091enum Id : unsigned { // id of symbolic names
1092 ID_QUAD_PERM = 0,
1093 ID_BITMASK_PERM,
1094 ID_SWAP,
1095 ID_REVERSE,
1096 ID_BROADCAST,
1097 ID_FFT,
1098 ID_ROTATE
1099};
1100
1101// clang-format off
1102enum EncBits : unsigned {
1103
1104 // swizzle mode encodings
1105
1106 QUAD_PERM_ENC = 0x8000,
1107 QUAD_PERM_ENC_MASK = 0xFF00,
1108
1109 BITMASK_PERM_ENC = 0x0000,
1110 BITMASK_PERM_ENC_MASK = 0x8000,
1111
1112 FFT_MODE_ENC = 0xE000,
1113
1114 ROTATE_MODE_ENC = 0xC000,
1115 FFT_ROTATE_MODE_MASK = 0xF000,
1116
1117 ROTATE_MODE_LO = 0xC000,
1118 FFT_MODE_LO = 0xE000,
1119
1120 // QUAD_PERM encodings
1121
1122 LANE_MASK = 0x3,
1123 LANE_MAX = LANE_MASK,
1124 LANE_SHIFT = 2,
1125 LANE_NUM = 4,
1126
1127 // BITMASK_PERM encodings
1128
1129 BITMASK_MASK = 0x1F,
1130 BITMASK_MAX = BITMASK_MASK,
1131 BITMASK_WIDTH = 5,
1132
1133 BITMASK_AND_SHIFT = 0,
1134 BITMASK_OR_SHIFT = 5,
1135 BITMASK_XOR_SHIFT = 10,
1136
1137 // FFT encodings
1138
1139 FFT_SWIZZLE_MASK = 0x1F,
1140 FFT_SWIZZLE_MAX = 0x1F,
1141
1142 // ROTATE encodings
1143 ROTATE_MAX_SIZE = 0x1F,
1144 ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
1145 ROTATE_DIR_MASK = 0x1,
1146 ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
1147 ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
1148};
1149// clang-format on
1150
1151} // namespace Swizzle
1152
1153namespace SDWA {
1154
1155enum SdwaSel : unsigned {
1156 BYTE_0 = 0,
1157 BYTE_1 = 1,
1158 BYTE_2 = 2,
1159 BYTE_3 = 3,
1160 WORD_0 = 4,
1161 WORD_1 = 5,
1162 DWORD = 6,
1163};
1164
1165enum DstUnused : unsigned {
1166 UNUSED_PAD = 0,
1167 UNUSED_SEXT = 1,
1168 UNUSED_PRESERVE = 2,
1169};
1170
1171enum SDWA9EncValues : unsigned {
1172 SRC_SGPR_MASK = 0x100,
1173 SRC_VGPR_MASK = 0xFF,
1174 VOPC_DST_VCC_MASK = 0x80,
1175 VOPC_DST_SGPR_MASK = 0x7F,
1176
1177 SRC_VGPR_MIN = 0,
1178 SRC_VGPR_MAX = 255,
1179 SRC_SGPR_MIN = 256,
1180 SRC_SGPR_MAX_SI = 357,
1181 SRC_SGPR_MAX_GFX10 = 361,
1182 SRC_TTMP_MIN = 364,
1183 SRC_TTMP_MAX = 379,
1184};
1185
1186} // namespace SDWA
1187
1188namespace DPP {
1189
1190// clang-format off
1191enum DppCtrl : unsigned {
1192 QUAD_PERM_FIRST = 0,
1193 QUAD_PERM_ID = 0xE4, // identity permutation
1194 QUAD_PERM_LAST = 0xFF,
1195 DPP_UNUSED1 = 0x100,
1196 ROW_SHL0 = 0x100,
1197 ROW_SHL_FIRST = 0x101,
1198 ROW_SHL_LAST = 0x10F,
1199 DPP_UNUSED2 = 0x110,
1200 ROW_SHR0 = 0x110,
1201 ROW_SHR_FIRST = 0x111,
1202 ROW_SHR_LAST = 0x11F,
1203 DPP_UNUSED3 = 0x120,
1204 ROW_ROR0 = 0x120,
1205 ROW_ROR_FIRST = 0x121,
1206 ROW_ROR_LAST = 0x12F,
1207 WAVE_SHL1 = 0x130,
1208 DPP_UNUSED4_FIRST = 0x131,
1209 DPP_UNUSED4_LAST = 0x133,
1210 WAVE_ROL1 = 0x134,
1211 DPP_UNUSED5_FIRST = 0x135,
1212 DPP_UNUSED5_LAST = 0x137,
1213 WAVE_SHR1 = 0x138,
1214 DPP_UNUSED6_FIRST = 0x139,
1215 DPP_UNUSED6_LAST = 0x13B,
1216 WAVE_ROR1 = 0x13C,
1217 DPP_UNUSED7_FIRST = 0x13D,
1218 DPP_UNUSED7_LAST = 0x13F,
1219 ROW_MIRROR = 0x140,
1220 ROW_HALF_MIRROR = 0x141,
1221 BCAST15 = 0x142,
1222 BCAST31 = 0x143,
1223 DPP_UNUSED8_FIRST = 0x144,
1224 DPP_UNUSED8_LAST = 0x14F,
1225 ROW_NEWBCAST_FIRST= 0x150,
1226 ROW_NEWBCAST_LAST = 0x15F,
1227 ROW_SHARE0 = 0x150,
1228 ROW_SHARE_FIRST = 0x150,
1229 ROW_SHARE_LAST = 0x15F,
1230 ROW_XMASK0 = 0x160,
1231 ROW_XMASK_FIRST = 0x160,
1232 ROW_XMASK_LAST = 0x16F,
1233 DPP_LAST = ROW_XMASK_LAST
1234};
1235// clang-format on
1236
1237enum DppFiMode {
1238 DPP_FI_0 = 0,
1239 DPP_FI_1 = 1,
1240 DPP8_FI_0 = 0xE9,
1241 DPP8_FI_1 = 0xEA,
1242};
1243
1244} // namespace DPP
1245
1246namespace Exp {
1247
1248enum Target : unsigned {
1249 ET_MRT0 = 0,
1250 ET_MRT7 = 7,
1251 ET_MRTZ = 8,
1252 ET_NULL = 9, // Pre-GFX11
1253 ET_POS0 = 12,
1254 ET_POS3 = 15,
1255 ET_POS4 = 16, // GFX10+
1256 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
1257 ET_PRIM = 20, // GFX10+
1258 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
1259 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
1260 ET_PARAM0 = 32, // Pre-GFX11
1261 ET_PARAM31 = 63, // Pre-GFX11
1262
1263 ET_NULL_MAX_IDX = 0,
1264 ET_MRTZ_MAX_IDX = 0,
1265 ET_PRIM_MAX_IDX = 0,
1266 ET_MRT_MAX_IDX = 7,
1267 ET_POS_MAX_IDX = 4,
1268 ET_DUAL_SRC_BLEND_MAX_IDX = 1,
1269 ET_PARAM_MAX_IDX = 31,
1270
1271 ET_INVALID = 255,
1272};
1273
1274} // namespace Exp
1275
1276namespace WMMA {
1277enum MatrixFMT : unsigned {
1278 MATRIX_FMT_FP8 = 0,
1279 MATRIX_FMT_BF8 = 1,
1280 MATRIX_FMT_FP6 = 2,
1281 MATRIX_FMT_BF6 = 3,
1282 MATRIX_FMT_FP4 = 4
1283};
1284
1285enum MatrixScale : unsigned {
1286 MATRIX_SCALE_ROW0 = 0,
1287 MATRIX_SCALE_ROW1 = 1,
1288};
1289
1290enum MatrixScaleFmt : unsigned {
1291 MATRIX_SCALE_FMT_E8 = 0,
1292 MATRIX_SCALE_FMT_E5M3 = 1,
1293 MATRIX_SCALE_FMT_E4M3 = 2
1294};
1295} // namespace WMMA
1296
1297namespace VOP3PEncoding {
1298
1299enum OpSel : uint64_t {
1300 OP_SEL_HI_0 = UINT64_C(1) << 59,
1301 OP_SEL_HI_1 = UINT64_C(1) << 60,
1302 OP_SEL_HI_2 = UINT64_C(1) << 14,
1303};
1304
1305} // namespace VOP3PEncoding
1306
1307namespace ImplicitArg {
1308// Implicit kernel argument offset for code object version 5.
1309enum Offset_COV5 : unsigned {
1310 HOSTCALL_PTR_OFFSET = 80,
1311 MULTIGRID_SYNC_ARG_OFFSET = 88,
1312 HEAP_PTR_OFFSET = 96,
1313
1314 DEFAULT_QUEUE_OFFSET = 104,
1315 COMPLETION_ACTION_OFFSET = 112,
1316
1317 PRIVATE_BASE_OFFSET = 192,
1318 SHARED_BASE_OFFSET = 196,
1319 QUEUE_PTR_OFFSET = 200,
1320};
1321
1322} // namespace ImplicitArg
1323
1324namespace MFMAScaleFormats {
1325// Enum value used in cbsz/blgp for F8F6F4 MFMA operations to select the matrix
1326// format.
1327enum MFMAScaleFormats {
1328 FP8_E4M3 = 0,
1329 FP8_E5M2 = 1,
1330 FP6_E2M3 = 2,
1331 FP6_E3M2 = 3,
1332 FP4_E2M1 = 4
1333};
1334} // namespace MFMAScaleFormats
1335
1336namespace VirtRegFlag {
1337// Virtual register flags used for various target specific handlings during
1338// codegen.
1339enum Register_Flag : uint8_t {
1340 // Register operand in a whole-wave mode operation.
1341 WWM_REG = 1 << 0,
1342};
1343
1344} // namespace VirtRegFlag
1345
1346} // namespace AMDGPU
1347
1348namespace AMDGPU {
1349namespace Barrier {
1350
1351enum Type {
1352 CLUSTER_TRAP = -4,
1353 CLUSTER = -3,
1354 TRAP = -2,
1355 WORKGROUP = -1,
1356 NAMED_BARRIER_FIRST = 1,
1357 NAMED_BARRIER_LAST = 16,
1358};
1359
1360} // namespace Barrier
1361
1362namespace SyntheticAperture {
1363/// Synthetic aperture numbers. This is OR'd with the high
1364/// bits of the LDS aperture pointer.
1365///
1366/// NOTE: This is also documented in AMDGPUUsage.
1367enum SyntheticAperture {
1368 None = 0x00000000,
1369
1370 BARRIER = 0x00000001,
1371};
1372} // namespace SyntheticAperture
1373
1374} // namespace AMDGPU
1375
1376// clang-format off
1377
1378#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1379#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1380#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1381#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1382#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1383#define C_00B028_MEM_ORDERED 0xFDFFFFFF
1384
1385#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1386#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1387#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1388#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1389#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1390#define C_00B128_MEM_ORDERED 0xF7FFFFFF
1391
1392#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1393#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1394#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1395#define C_00B228_WGP_MODE 0xF7FFFFFF
1396#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1397#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1398#define C_00B228_MEM_ORDERED 0xFDFFFFFF
1399
1400#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1401#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1402#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1403#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1404#define C_00B428_WGP_MODE 0xFBFFFFFF
1405#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1406#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1407#define C_00B428_MEM_ORDERED 0xFEFFFFFF
1408
1409#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1410
1411#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1412#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1413#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1414#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1415#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1416#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1417#define C_00B84C_USER_SGPR 0xFFFFFFC1
1418#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1419#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1420#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1421#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1422#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1423#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1424#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1425#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1426#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1427#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1428#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1429#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1430#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1431#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1432#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1433#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1434#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1435#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1436/* CIK */
1437#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1438#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1439#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1440/* */
1441#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1442#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1443#define C_00B84C_LDS_SIZE 0xFF007FFF
1444#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1445#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1446#define C_00B84C_EXCP_EN 0x80FFFFFF
1447
1448#define S_00B84C_USER_SGPR_GFX1250(x) (((x) & 0x3F) << 1)
1449#define G_00B84C_USER_SGPR_GFX1250(x) (((x) >> 1) & 0x3F)
1450#define C_00B84C_USER_SGPR_GFX1250 0xFFFFFF81
1451
1452#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1453#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1454
1455#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1456#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1457#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1458#define C_00B848_VGPRS 0xFFFFFFC0
1459#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1460#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1461#define C_00B848_SGPRS 0xFFFFFC3F
1462#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1463#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1464#define C_00B848_PRIORITY 0xFFFFF3FF
1465#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1466#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1467#define C_00B848_FLOAT_MODE 0xFFF00FFF
1468#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1469#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1470#define C_00B848_PRIV 0xFFEFFFFF
1471#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1472#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1473#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1474#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1475#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1476#define C_00B848_RR_WG_MODE 0xFFDFFFFF
1477#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1478#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1479#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1480#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1481#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1482#define C_00B848_IEEE_MODE 0xFF7FFFFF
1483#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1484#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1485#define C_00B848_WGP_MODE 0xDFFFFFFF
1486#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1487#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1488#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1489#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1490#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1491#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1492
1493// Helpers for setting FLOAT_MODE
1494#define FP_ROUND_ROUND_TO_NEAREST 0
1495#define FP_ROUND_ROUND_TO_INF 1
1496#define FP_ROUND_ROUND_TO_NEGINF 2
1497#define FP_ROUND_ROUND_TO_ZERO 3
1498
1499// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1500// precision.
1501#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1502#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1503
1504#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1505#define FP_DENORM_FLUSH_OUT 1
1506#define FP_DENORM_FLUSH_IN 2
1507#define FP_DENORM_FLUSH_NONE 3
1508
1509
1510// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1511// precision.
1512#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1513#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1514
1515#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1516#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1517#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1518#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1519
1520#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1521#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1522#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1523#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1524
1525#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1526#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1527#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1528#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1529#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1530#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1531#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1532#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1533
1534#define R_SPILLED_SGPRS 0x4
1535#define R_SPILLED_VGPRS 0x8
1536
1537// clang-format on
1538
1539} // End namespace llvm
1540
1541#endif
1542