1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInst.h"
14#include "llvm/MC/MCInstrDesc.h"
15#include "llvm/MC/MCInstrInfo.h"
16#include "llvm/Support/AMDGPUAddrSpace.h"
17
18namespace llvm {
19
20// This needs to be kept in sync with the field bits in SIRegisterClass.
21enum SIRCFlags : uint8_t {
22 RegTupleAlignUnitsWidth = 2,
23 HasVGPRBit = RegTupleAlignUnitsWidth,
24 HasAGPRBit,
25 HasSGPRbit,
26
27 HasVGPR = 1 << HasVGPRBit,
28 HasAGPR = 1 << HasAGPRBit,
29 HasSGPR = 1 << HasSGPRbit,
30
31 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
32 RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
33}; // enum SIRCFlagsr
34
35namespace SIEncodingFamily {
36// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
37// and the columns of the getMCOpcodeGen table.
38enum {
39 SI = 0,
40 VI = 1,
41 SDWA = 2,
42 SDWA9 = 3,
43 GFX80 = 4,
44 GFX9 = 5,
45 GFX10 = 6,
46 SDWA10 = 7,
47 GFX90A = 8,
48 GFX940 = 9,
49 GFX11 = 10,
50 GFX1170 = 11,
51 GFX12 = 12,
52 GFX1250 = 13,
53 GFX13 = 14,
54};
55}
56
57namespace SIInstrFlags {
58
59// Raw TSFlags bit constants — use the predicate functions below instead of
60// testing these directly. This namespace makes accidental direct use a
61// compile error outside of SIDefines.h itself.
62namespace DontUseRawTSFlags {
63// This needs to be kept in sync with the field bits in InstSI.
64enum : uint64_t {
65 // Low bits - basic encoding information.
66 SALU = 1 << 0,
67 VALU = 1 << 1,
68
69 // SALU instruction formats.
70 SOP1 = 1 << 2,
71 SOP2 = 1 << 3,
72 SOPC = 1 << 4,
73 SOPK = 1 << 5,
74 SOPP = 1 << 6,
75
76 // VALU instruction formats.
77 VOP1 = 1 << 7,
78 VOP2 = 1 << 8,
79 VOPC = 1 << 9,
80
81 // TODO: Should this be spilt into VOP3 a and b?
82 VOP3 = 1 << 10,
83 VOP3P = 1 << 12,
84
85 VINTRP = 1 << 13,
86 SDWA = 1 << 14,
87 DPP = 1 << 15,
88 TRANS = 1 << 16,
89
90 // Memory instruction formats.
91 MUBUF = 1 << 17,
92 MTBUF = 1 << 18,
93 SMRD = 1 << 19,
94 MIMG = 1 << 20,
95 VIMAGE = 1 << 21,
96 VSAMPLE = 1 << 22,
97 EXP = 1 << 23,
98 FLAT = 1 << 24,
99 DS = 1 << 25,
100
101 // Combined SGPR/VGPR Spill bit
102 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill
103 Spill = 1 << 26,
104
105 // LDSDIR instruction format.
106 LDSDIR = 1 << 28,
107
108 // VINTERP instruction format.
109 VINTERP = 1 << 29,
110
111 VOPD3 = 1 << 30,
112
113 // High bits - other information.
114 VM_CNT = UINT64_C(1) << 32,
115 EXP_CNT = UINT64_C(1) << 33,
116 LGKM_CNT = UINT64_C(1) << 34,
117
118 WQM = UINT64_C(1) << 35,
119 DisableWQM = UINT64_C(1) << 36,
120 Gather4 = UINT64_C(1) << 37,
121
122 TENSOR_CNT = UINT64_C(1) << 38,
123
124 SCALAR_STORE = UINT64_C(1) << 39,
125 FIXED_SIZE = UINT64_C(1) << 40,
126
127 ASYNC_CNT = UINT64_C(1) << 41,
128
129 VOP3_OPSEL = UINT64_C(1) << 42,
130 maybeAtomic = UINT64_C(1) << 43,
131
132 // Is a clamp on FP type.
133 FPClamp = UINT64_C(1) << 45,
134
135 // Is an integer clamp
136 IntClamp = UINT64_C(1) << 46,
137
138 // Clamps lo component of register.
139 ClampLo = UINT64_C(1) << 47,
140
141 // Clamps hi component of register.
142 // ClampLo and ClampHi set for packed clamp.
143 ClampHi = UINT64_C(1) << 48,
144
145 // Is a packed VOP3P instruction.
146 IsPacked = UINT64_C(1) << 49,
147
148 // Is a D16 buffer instruction.
149 D16Buf = UINT64_C(1) << 50,
150
151 // FLAT instruction accesses FLAT_GLBL segment.
152 FlatGlobal = UINT64_C(1) << 51,
153
154 // Uses floating point double precision rounding mode
155 FPDPRounding = UINT64_C(1) << 52,
156
157 // Instruction is FP atomic.
158 FPAtomic = UINT64_C(1) << 53,
159
160 // Is a MFMA instruction.
161 IsMAI = UINT64_C(1) << 54,
162
163 // Is a DOT instruction.
164 IsDOT = UINT64_C(1) << 55,
165
166 // FLAT instruction accesses FLAT_SCRATCH segment.
167 FlatScratch = UINT64_C(1) << 56,
168
169 // Atomic without return.
170 IsAtomicNoRet = UINT64_C(1) << 57,
171
172 // Atomic with return.
173 IsAtomicRet = UINT64_C(1) << 58,
174
175 // Is a WMMA instruction.
176 IsWMMA = UINT64_C(1) << 59,
177
178 // Whether tied sources will be read.
179 TiedSourceNotRead = UINT64_C(1) << 60,
180
181 // Is never uniform.
182 IsNeverUniform = UINT64_C(1) << 61,
183
184 // ds_gws_* instructions.
185 GWS = UINT64_C(1) << 62,
186
187 // Is a SWMMAC instruction.
188 IsSWMMAC = UINT64_C(1) << 63,
189};
190} // namespace DontUseRawTSFlags
191
192// Predicate functions over TSFlags — the single place where raw TSFlags bit
193// tests are written. All callers (SIInstrInfo methods, MC-layer code) go
194// through these so that bit-layout changes require updating only this file.
195//
196// getTSFlags is overloaded for MCInstrDesc, (MCInstrInfo, Opcode), and
197// (MCInstrInfo, MCInst) here; SIInstrInfo.h adds a MachineInstr overload in
198// namespace llvm so ADL finds it when predicates are instantiated with
199// MachineInstr.
200
201constexpr uint64_t getTSFlags(const MCInstrDesc &Desc) { return Desc.TSFlags; }
202inline uint64_t getTSFlags(const MCInstrInfo &MII, unsigned Opcode) {
203 return MII.get(Opcode).TSFlags;
204}
205inline uint64_t getTSFlags(const MCInstrInfo &MII, const MCInst &Inst) {
206 return MII.get(Opcode: Inst.getOpcode()).TSFlags;
207}
208
209template <typename... T> constexpr bool isSALU(const T &...O) {
210 return getTSFlags(O...) & DontUseRawTSFlags::SALU;
211}
212template <typename... T> constexpr bool isVALU(const T &...O) {
213 return getTSFlags(O...) & DontUseRawTSFlags::VALU;
214}
215template <typename... T> constexpr bool isSOP1(const T &...O) {
216 return getTSFlags(O...) & DontUseRawTSFlags::SOP1;
217}
218template <typename... T> constexpr bool isSOP2(const T &...O) {
219 return getTSFlags(O...) & DontUseRawTSFlags::SOP2;
220}
221template <typename... T> constexpr bool isSOPC(const T &...O) {
222 return getTSFlags(O...) & DontUseRawTSFlags::SOPC;
223}
224template <typename... T> constexpr bool isSOPK(const T &...O) {
225 return getTSFlags(O...) & DontUseRawTSFlags::SOPK;
226}
227template <typename... T> constexpr bool isSOPP(const T &...O) {
228 return getTSFlags(O...) & DontUseRawTSFlags::SOPP;
229}
230template <typename... T> constexpr bool isVOP1(const T &...O) {
231 return getTSFlags(O...) & DontUseRawTSFlags::VOP1;
232}
233template <typename... T> constexpr bool isVOP2(const T &...O) {
234 return getTSFlags(O...) & DontUseRawTSFlags::VOP2;
235}
236template <typename... T> constexpr bool isVOPC(const T &...O) {
237 return getTSFlags(O...) & DontUseRawTSFlags::VOPC;
238}
239template <typename... T> constexpr bool isVOP3(const T &...O) {
240 return getTSFlags(O...) & DontUseRawTSFlags::VOP3;
241}
242template <typename... T> constexpr bool isVOP3P(const T &...O) {
243 return getTSFlags(O...) & DontUseRawTSFlags::VOP3P;
244}
245template <typename... T> constexpr bool isVOP3Like(const T &...O) {
246 return getTSFlags(O...) &
247 (DontUseRawTSFlags::VOP3 | DontUseRawTSFlags::VOP3P);
248}
249template <typename... T> constexpr bool isVINTRP(const T &...O) {
250 return getTSFlags(O...) & DontUseRawTSFlags::VINTRP;
251}
252template <typename... T> constexpr bool isSDWA(const T &...O) {
253 return getTSFlags(O...) & DontUseRawTSFlags::SDWA;
254}
255template <typename... T> constexpr bool isDPP(const T &...O) {
256 return getTSFlags(O...) & DontUseRawTSFlags::DPP;
257}
258template <typename... T> constexpr bool isTRANS(const T &...O) {
259 return getTSFlags(O...) & DontUseRawTSFlags::TRANS;
260}
261template <typename... T> constexpr bool isMUBUF(const T &...O) {
262 return getTSFlags(O...) & DontUseRawTSFlags::MUBUF;
263}
264template <typename... T> constexpr bool isMTBUF(const T &...O) {
265 return getTSFlags(O...) & DontUseRawTSFlags::MTBUF;
266}
267template <typename... T> constexpr bool isBuffer(const T &...O) {
268 return getTSFlags(O...) &
269 (DontUseRawTSFlags::MUBUF | DontUseRawTSFlags::MTBUF);
270}
271template <typename... T> constexpr bool isSMRD(const T &...O) {
272 return getTSFlags(O...) & DontUseRawTSFlags::SMRD;
273}
274template <typename... T> constexpr bool isMIMG(const T &...O) {
275 return getTSFlags(O...) & DontUseRawTSFlags::MIMG;
276}
277template <typename... T> constexpr bool isVIMAGE(const T &...O) {
278 return getTSFlags(O...) & DontUseRawTSFlags::VIMAGE;
279}
280template <typename... T> constexpr bool isVSAMPLE(const T &...O) {
281 return getTSFlags(O...) & DontUseRawTSFlags::VSAMPLE;
282}
283template <typename... T> constexpr bool isEXP(const T &...O) {
284 return getTSFlags(O...) & DontUseRawTSFlags::EXP;
285}
286template <typename... T> constexpr bool isFLAT(const T &...O) {
287 return getTSFlags(O...) & DontUseRawTSFlags::FLAT;
288}
289template <typename... T> constexpr bool isDS(const T &...O) {
290 return getTSFlags(O...) & DontUseRawTSFlags::DS;
291}
292template <typename... T> constexpr bool isSpill(const T &...O) {
293 return getTSFlags(O...) & DontUseRawTSFlags::Spill;
294}
295template <typename... T> constexpr bool isLDSDIR(const T &...O) {
296 return getTSFlags(O...) & DontUseRawTSFlags::LDSDIR;
297}
298template <typename... T> constexpr bool isVINTERP(const T &...O) {
299 return getTSFlags(O...) & DontUseRawTSFlags::VINTERP;
300}
301template <typename... T> constexpr bool isWQM(const T &...O) {
302 return getTSFlags(O...) & DontUseRawTSFlags::WQM;
303}
304template <typename... T> constexpr bool isDisableWQM(const T &...O) {
305 return getTSFlags(O...) & DontUseRawTSFlags::DisableWQM;
306}
307template <typename... T> constexpr bool isGather4(const T &...O) {
308 return getTSFlags(O...) & DontUseRawTSFlags::Gather4;
309}
310template <typename... T> constexpr bool usesTENSOR_CNT(const T &...O) {
311 return getTSFlags(O...) & DontUseRawTSFlags::TENSOR_CNT;
312}
313template <typename... T> constexpr bool isScalarStore(const T &...O) {
314 return getTSFlags(O...) & DontUseRawTSFlags::SCALAR_STORE;
315}
316template <typename... T> constexpr bool isFixedSize(const T &...O) {
317 return getTSFlags(O...) & DontUseRawTSFlags::FIXED_SIZE;
318}
319template <typename... T> constexpr bool usesASYNC_CNT(const T &...O) {
320 return getTSFlags(O...) & DontUseRawTSFlags::ASYNC_CNT;
321}
322template <typename... T> constexpr bool hasVOP3OpSel(const T &...O) {
323 return getTSFlags(O...) & DontUseRawTSFlags::VOP3_OPSEL;
324}
325template <typename... T> constexpr bool isMaybeAtomic(const T &...O) {
326 return getTSFlags(O...) & DontUseRawTSFlags::maybeAtomic;
327}
328template <typename... T> constexpr bool hasFPClamp(const T &...O) {
329 return getTSFlags(O...) & DontUseRawTSFlags::FPClamp;
330}
331template <typename... T> constexpr bool hasIntClamp(const T &...O) {
332 return getTSFlags(O...) & DontUseRawTSFlags::IntClamp;
333}
334template <typename... T> constexpr bool hasClampLo(const T &...O) {
335 return getTSFlags(O...) & DontUseRawTSFlags::ClampLo;
336}
337template <typename... T> constexpr bool hasClampHi(const T &...O) {
338 return getTSFlags(O...) & DontUseRawTSFlags::ClampHi;
339}
340template <typename... T> constexpr bool isPacked(const T &...O) {
341 return getTSFlags(O...) & DontUseRawTSFlags::IsPacked;
342}
343template <typename... T> constexpr bool isD16Buf(const T &...O) {
344 return getTSFlags(O...) & DontUseRawTSFlags::D16Buf;
345}
346template <typename... T> constexpr bool isFlatGlobal(const T &...O) {
347 return getTSFlags(O...) & DontUseRawTSFlags::FlatGlobal;
348}
349template <typename... T> constexpr bool usesFPDPRounding(const T &...O) {
350 return getTSFlags(O...) & DontUseRawTSFlags::FPDPRounding;
351}
352template <typename... T> constexpr bool isFPAtomic(const T &...O) {
353 return getTSFlags(O...) & DontUseRawTSFlags::FPAtomic;
354}
355template <typename... T> constexpr bool isMAI(const T &...O) {
356 return getTSFlags(O...) & DontUseRawTSFlags::IsMAI;
357}
358template <typename... T> constexpr bool isDOT(const T &...O) {
359 return getTSFlags(O...) & DontUseRawTSFlags::IsDOT;
360}
361template <typename... T> constexpr bool isFlatScratch(const T &...O) {
362 return getTSFlags(O...) & DontUseRawTSFlags::FlatScratch;
363}
364template <typename... T> constexpr bool isAtomicNoRet(const T &...O) {
365 return getTSFlags(O...) & DontUseRawTSFlags::IsAtomicNoRet;
366}
367template <typename... T> constexpr bool isAtomicRet(const T &...O) {
368 return getTSFlags(O...) & DontUseRawTSFlags::IsAtomicRet;
369}
370template <typename... T> constexpr bool isWMMA(const T &...O) {
371 return getTSFlags(O...) & DontUseRawTSFlags::IsWMMA;
372}
373template <typename... T> constexpr bool isTiedSourceNotRead(const T &...O) {
374 return getTSFlags(O...) & DontUseRawTSFlags::TiedSourceNotRead;
375}
376template <typename... T> constexpr bool isNeverUniform(const T &...O) {
377 return getTSFlags(O...) & DontUseRawTSFlags::IsNeverUniform;
378}
379template <typename... T> constexpr bool isGWS(const T &...O) {
380 return getTSFlags(O...) & DontUseRawTSFlags::GWS;
381}
382template <typename... T> constexpr bool isSWMMAC(const T &...O) {
383 return getTSFlags(O...) & DontUseRawTSFlags::IsSWMMAC;
384}
385template <typename... T> constexpr bool isVOPD3(const T &...O) {
386 return getTSFlags(O...) & DontUseRawTSFlags::VOPD3;
387}
388template <typename... T> constexpr bool usesVM_CNT(const T &...O) {
389 return getTSFlags(O...) & DontUseRawTSFlags::VM_CNT;
390}
391template <typename... T> constexpr bool usesLGKM_CNT(const T &...O) {
392 return getTSFlags(O...) & DontUseRawTSFlags::LGKM_CNT;
393}
394
395// Compound predicates.
396template <typename... T> constexpr bool isAtomic(const T &...O) {
397 return isAtomicNoRet(O...) || isAtomicRet(O...);
398}
399template <typename... T> constexpr bool isSegmentSpecificFLAT(const T &...O) {
400 return isFlatGlobal(O...) || isFlatScratch(O...);
401}
402// Any image-family instruction: pre-gfx11 MIMG, gfx11+ VIMAGE or VSAMPLE.
403template <typename... T> constexpr bool isImage(const T &...O) {
404 return isMIMG(O...) || isVIMAGE(O...) || isVSAMPLE(O...);
405}
406// Vector memory: buffer + image + flat.
407template <typename... T> constexpr bool isVMEM(const T &...O) {
408 return isMUBUF(O...) || isMTBUF(O...) || isImage(O...) || isFLAT(O...);
409}
410
411// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
412// The result is true if any of these tests are true.
413enum ClassFlags : unsigned {
414 S_NAN = 1 << 0, // Signaling NaN
415 Q_NAN = 1 << 1, // Quiet NaN
416 N_INFINITY = 1 << 2, // Negative infinity
417 N_NORMAL = 1 << 3, // Negative normal
418 N_SUBNORMAL = 1 << 4, // Negative subnormal
419 N_ZERO = 1 << 5, // Negative zero
420 P_ZERO = 1 << 6, // Positive zero
421 P_SUBNORMAL = 1 << 7, // Positive subnormal
422 P_NORMAL = 1 << 8, // Positive normal
423 P_INFINITY = 1 << 9 // Positive infinity
424};
425}
426
427namespace AMDGPU {
428
429enum OperandType : unsigned {
430 /// Operands with register, 32-bit, or 64-bit immediate
431 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
432 OPERAND_REG_IMM_INT64,
433 OPERAND_REG_IMM_INT16,
434 OPERAND_REG_IMM_FP32,
435 OPERAND_REG_IMM_FP64,
436 OPERAND_REG_IMM_BF16,
437 OPERAND_REG_IMM_FP16,
438 OPERAND_REG_IMM_V2BF16,
439 OPERAND_REG_IMM_V2FP16,
440 OPERAND_REG_IMM_V2FP16_SPLAT,
441 OPERAND_REG_IMM_V2INT16,
442 OPERAND_REG_IMM_V2INT64,
443 OPERAND_REG_IMM_NOINLINE_V2FP16,
444 OPERAND_REG_IMM_V2INT32,
445 OPERAND_REG_IMM_V2FP32,
446 OPERAND_REG_IMM_V2FP64,
447
448 /// Operands with register or inline constant
449 OPERAND_REG_INLINE_C_INT16,
450 OPERAND_REG_INLINE_C_INT32,
451 OPERAND_REG_INLINE_C_INT64,
452 OPERAND_REG_INLINE_C_BF16,
453 OPERAND_REG_INLINE_C_FP16,
454 OPERAND_REG_INLINE_C_FP32,
455 OPERAND_REG_INLINE_C_FP64,
456 OPERAND_REG_INLINE_C_V2INT16,
457 OPERAND_REG_INLINE_C_V2BF16,
458 OPERAND_REG_INLINE_C_V2FP16,
459
460 // Operand for split barrier inline constant
461 OPERAND_INLINE_SPLIT_BARRIER_INT32,
462
463 /// Operand with 32-bit immediate that uses the constant bus.
464 OPERAND_KIMM32,
465 OPERAND_KIMM16,
466 OPERAND_KIMM64,
467
468 /// Operands with an AccVGPR register or inline constant
469 OPERAND_REG_INLINE_AC_INT32,
470 OPERAND_REG_INLINE_AC_FP32,
471 OPERAND_REG_INLINE_AC_FP64,
472
473 // Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline
474 // constants. Does not accept registers.
475 OPERAND_INLINE_C_AV64_PSEUDO,
476
477 // Operand for source modifiers for VOP instructions
478 OPERAND_INPUT_MODS,
479
480 // Operand for SDWA instructions
481 OPERAND_SDWA_VOPC_DST,
482
483 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
484 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP64,
485
486 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
487 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,
488
489 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,
490 OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO,
491
492 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
493 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
494
495 OPERAND_KIMM_FIRST = OPERAND_KIMM32,
496 OPERAND_KIMM_LAST = OPERAND_KIMM64
497
498};
499}
500
501// Input operand modifiers bit-masks
502// NEG and SEXT share same bit-mask because they can't be set simultaneously.
503namespace SISrcMods {
504enum : unsigned {
505 NONE = 0,
506 NEG = 1 << 0, // Floating-point negate modifier
507 ABS = 1 << 1, // Floating-point absolute modifier
508 SEXT = 1 << 4, // Integer sign-extend modifier
509 NEG_HI = ABS, // Floating-point negate high packed component modifier.
510 OP_SEL_0 = 1 << 2,
511 OP_SEL_1 = 1 << 3,
512 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
513};
514}
515
516namespace SIOutMods {
517 enum : unsigned {
518 NONE = 0,
519 MUL2 = 1,
520 MUL4 = 2,
521 DIV2 = 3
522 };
523}
524
525namespace AMDGPU {
526namespace VGPRIndexMode {
527
528enum Id : unsigned { // id of symbolic names
529 ID_SRC0 = 0,
530 ID_SRC1,
531 ID_SRC2,
532 ID_DST,
533
534 ID_MIN = ID_SRC0,
535 ID_MAX = ID_DST
536};
537
538enum EncBits : unsigned {
539 OFF = 0,
540 SRC0_ENABLE = 1 << ID_SRC0,
541 SRC1_ENABLE = 1 << ID_SRC1,
542 SRC2_ENABLE = 1 << ID_SRC2,
543 DST_ENABLE = 1 << ID_DST,
544 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
545 UNDEF = 0xFFFF
546};
547
548} // namespace VGPRIndexMode
549} // namespace AMDGPU
550
551namespace AMDGPUAsmVariants {
552 enum : unsigned {
553 DEFAULT = 0,
554 VOP3 = 1,
555 SDWA = 2,
556 SDWA9 = 3,
557 DPP = 4,
558 VOP3_DPP = 5
559 };
560} // namespace AMDGPUAsmVariants
561
562namespace AMDGPU {
563namespace EncValues { // Encoding values of enum9/8/7 operands
564
565enum : unsigned {
566 SGPR_MIN = 0,
567 SGPR_MAX_SI = 101,
568 SGPR_MAX_GFX10 = 105,
569 TTMP_VI_MIN = 112,
570 TTMP_VI_MAX = 123,
571 TTMP_GFX9PLUS_MIN = 108,
572 TTMP_GFX9PLUS_MAX = 123,
573 INLINE_INTEGER_C_MIN = 128,
574 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
575 INLINE_INTEGER_C_MAX = 208,
576 INLINE_FLOATING_C_MIN = 240,
577 INLINE_FLOATING_C_MAX = 248,
578 LITERAL64_CONST = 254,
579 LITERAL_CONST = 255,
580 VGPR_MIN = 256,
581 VGPR_MAX = 511,
582 IS_VGPR = 256, // Indicates VGPR or AGPR
583};
584
585} // namespace EncValues
586
587// Register codes as defined in the TableGen's HWEncoding field.
588namespace HWEncoding {
589enum : unsigned {
590 REG_IDX_MASK = 0x3ff,
591 LO256_REG_IDX_MASK = 0xff,
592 IS_VGPR = 1 << 10,
593 IS_AGPR = 1 << 11,
594 IS_HI16 = 1 << 12,
595};
596} // namespace HWEncoding
597
598namespace CPol {
599
600enum CPol {
601 GLC = 1,
602 SLC = 2,
603 DLC = 4,
604 SCC = 16,
605 SC0 = GLC,
606 SC1 = SCC,
607 NT = SLC,
608 ALL_pregfx12 = GLC | SLC | DLC | SCC,
609 SWZ_pregfx12 = 8,
610
611 // Below are GFX12+ cache policy bits
612
613 // Temporal hint
614 TH = 0x7, // All TH bits
615 TH_RT = 0, // regular
616 TH_NT = 1, // non-temporal
617 TH_HT = 2, // high-temporal
618 TH_LU = 3, // last use
619 TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
620 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
621 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
622 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
623 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)
624 TH_BYPASS = 3, // only to be used with scope = 3
625
626 TH_RESERVED = 7, // unused value for load insts
627
628 // Bits of TH for atomics
629 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
630 TH_ATOMIC_NT = SLC, // Non-temporal vs regular
631 TH_ATOMIC_CASCADE = 4, // Cascading vs regular
632
633 // Scope
634 SCOPE_SHIFT = 3,
635 SCOPE_MASK = 0x3,
636 SCOPE = SCOPE_MASK << SCOPE_SHIFT, // All Scope bits
637 SCOPE_CU = 0 << SCOPE_SHIFT,
638 SCOPE_SE = 1 << SCOPE_SHIFT,
639 SCOPE_DEV = 2 << SCOPE_SHIFT,
640 SCOPE_SYS = 3 << SCOPE_SHIFT,
641
642 NV = 1 << 5, // Non-volatile bit
643
644 SWZ = 1 << 6, // Swizzle bit
645
646 SCAL = 1 << 11, // Scale offset bit
647
648 ALL = TH | SCOPE | NV,
649
650 // Helper bits
651 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy
652 TH_TYPE_STORE = 1 << 8, // TH_STORE policy
653 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy
654 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
655
656 // Volatile (used to preserve/signal operation volatility for buffer
657 // operations not a real instruction bit)
658 VOLATILE = 1 << 31,
659 // The set of "cache policy" bits used for compiler features that
660 // do not correspond to handware features.
661 VIRTUAL_BITS = VOLATILE,
662};
663
664} // namespace CPol
665
666namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
667
668enum Id { // Message ID, width(4) [3:0].
669 ID_INTERRUPT = 1,
670
671 ID_GS_PreGFX11 = 2, // replaced in GFX11
672 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
673
674 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
675 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
676
677 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
678 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12
679 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12
680 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
681 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
682 ID_GS_ALLOC_REQ = 9, // added in GFX9
683 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
684 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
685 ID_SYSMSG = 15,
686
687 ID_RTN_GET_DOORBELL = 128,
688 ID_RTN_GET_DDID = 129,
689 ID_RTN_GET_TMA = 130,
690 ID_RTN_GET_REALTIME = 131,
691 ID_RTN_SAVE_WAVE = 132,
692 ID_RTN_GET_TBA = 133,
693 ID_RTN_GET_TBA_TO_PC = 134,
694 ID_RTN_GET_SE_AID_ID = 135,
695
696 ID_RTN_GET_CLUSTER_BARRIER_STATE = 136, // added in GFX1250
697 ID_RTN_SAVE_WAVE_HAS_TDM = 152, // added in GFX1250
698
699 ID_MASK_PreGFX11_ = 0xF,
700 ID_MASK_GFX11Plus_ = 0xFF
701};
702
703enum Op { // Both GS and SYS operation IDs.
704 OP_SHIFT_ = 4,
705 OP_NONE_ = 0,
706 // Bits used for operation encoding
707 OP_WIDTH_ = 3,
708 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
709 // GS operations are encoded in bits 5:4
710 OP_GS_NOP = 0,
711 OP_GS_CUT = 1,
712 OP_GS_EMIT = 2,
713 OP_GS_EMIT_CUT = 3,
714 OP_GS_FIRST_ = OP_GS_NOP,
715 // SYS operations are encoded in bits 6:4
716 OP_SYS_ECC_ERR_INTERRUPT = 1,
717 OP_SYS_REG_RD = 2,
718 OP_SYS_HOST_TRAP_ACK = 3,
719 OP_SYS_TTRACE_PC = 4,
720 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
721};
722
723enum StreamId : unsigned { // Stream ID, (2) [9:8].
724 STREAM_ID_NONE_ = 0,
725 STREAM_ID_DEFAULT_ = 0,
726 STREAM_ID_LAST_ = 4,
727 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
728 STREAM_ID_SHIFT_ = 8,
729 STREAM_ID_WIDTH_= 2,
730 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
731};
732
733} // namespace SendMsg
734
735namespace WaitEvent { // Encoding of SIMM16 used in s_wait_event
736enum Id {
737 DONT_WAIT_EXPORT_READY = 1 << 0, // Only used in gfx11
738 EXPORT_READY = 1 << 1, // gfx12+
739};
740
741} // namespace WaitEvent
742
743namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
744
745enum Id { // HwRegCode, (6) [5:0]
746 ID_MODE = 1,
747 ID_STATUS = 2,
748 ID_TRAPSTS = 3,
749 ID_HW_ID = 4,
750 ID_GPR_ALLOC = 5,
751 ID_LDS_ALLOC = 6,
752 ID_IB_STS = 7,
753 ID_PERF_SNAPSHOT_DATA_gfx12 = 10,
754 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,
755 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,
756 ID_MEM_BASES = 15,
757 ID_TBA_LO = 16,
758 ID_TBA_HI = 17,
759 ID_TMA_LO = 18,
760 ID_TMA_HI = 19,
761 ID_FLAT_SCR_LO = 20,
762 ID_FLAT_SCR_HI = 21,
763 ID_XNACK_MASK = 22,
764 ID_HW_ID1 = 23,
765 ID_HW_ID2 = 24,
766 ID_POPS_PACKER = 25,
767 ID_SCHED_MODE = 26,
768 ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
769 ID_IB_STS2 = 28,
770 ID_SHADER_CYCLES = 29,
771 ID_SHADER_CYCLES_HI = 30,
772 ID_DVGPR_ALLOC_LO = 31,
773 ID_DVGPR_ALLOC_HI = 32,
774
775 // Register numbers reused in GFX11
776 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,
777 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,
778
779 // Register numbers reused in GFX12+
780 ID_STATE_PRIV = 4,
781 ID_PERF_SNAPSHOT_DATA1 = 15,
782 ID_PERF_SNAPSHOT_DATA2 = 16,
783 ID_EXCP_FLAG_PRIV = 17,
784 ID_EXCP_FLAG_USER = 18,
785 ID_TRAP_CTRL = 19,
786
787 // GFX94* specific registers
788 ID_XCC_ID = 20,
789 ID_SQ_PERF_SNAPSHOT_DATA = 21,
790 ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
791 ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
792 ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
793
794 // GFX1250
795 ID_XNACK_STATE_PRIV = 33,
796 ID_XNACK_MASK_gfx1250 = 34,
797};
798
799enum Offset : unsigned { // Offset, (5) [10:6]
800 OFFSET_MEM_VIOL = 8,
801 OFFSET_ME_ID = 8, // in HW_ID2
802};
803
804enum ModeRegisterMasks : uint32_t {
805 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
806 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
807 DX10_CLAMP_MASK = 1 << 8,
808 IEEE_MODE_MASK = 1 << 9,
809 LOD_CLAMP_MASK = 1 << 10,
810 DEBUG_MASK = 1 << 11,
811
812 // EXCP_EN fields.
813 EXCP_EN_INVALID_MASK = 1 << 12,
814 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
815 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
816 EXCP_EN_OVERFLOW_MASK = 1 << 15,
817 EXCP_EN_UNDERFLOW_MASK = 1 << 16,
818 EXCP_EN_INEXACT_MASK = 1 << 17,
819 EXCP_EN_INT_DIV0_MASK = 1 << 18,
820
821 GPR_IDX_EN_MASK = 1 << 27,
822 VSKIP_MASK = 1 << 28,
823 CSP_MASK = 0x7u << 29, // Bits 29..31
824
825 // GFX1250
826 DST_VGPR_MSB = 0x3 << 12,
827 SRC0_VGPR_MSB = 0x3 << 14,
828 SRC1_VGPR_MSB = 0x3 << 16,
829 SRC2_VGPR_MSB = 0x3 << 18,
830 VGPR_MSB_MASK = 0xff << 12, // Bits 12..19
831
832 REPLAY_MODE = 1 << 25,
833 FLAT_SCRATCH_IS_NV = 1 << 26,
834};
835
836} // namespace Hwreg
837
838namespace MTBUFFormat {
839
840enum DataFormat : int64_t {
841 DFMT_INVALID = 0,
842 DFMT_8,
843 DFMT_16,
844 DFMT_8_8,
845 DFMT_32,
846 DFMT_16_16,
847 DFMT_10_11_11,
848 DFMT_11_11_10,
849 DFMT_10_10_10_2,
850 DFMT_2_10_10_10,
851 DFMT_8_8_8_8,
852 DFMT_32_32,
853 DFMT_16_16_16_16,
854 DFMT_32_32_32,
855 DFMT_32_32_32_32,
856 DFMT_RESERVED_15,
857
858 DFMT_MIN = DFMT_INVALID,
859 DFMT_MAX = DFMT_RESERVED_15,
860
861 DFMT_UNDEF = -1,
862 DFMT_DEFAULT = DFMT_8,
863
864 DFMT_SHIFT = 0,
865 DFMT_MASK = 0xF
866};
867
868enum NumFormat : int64_t {
869 NFMT_UNORM = 0,
870 NFMT_SNORM,
871 NFMT_USCALED,
872 NFMT_SSCALED,
873 NFMT_UINT,
874 NFMT_SINT,
875 NFMT_RESERVED_6, // VI and GFX9
876 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
877 NFMT_FLOAT,
878
879 NFMT_MIN = NFMT_UNORM,
880 NFMT_MAX = NFMT_FLOAT,
881
882 NFMT_UNDEF = -1,
883 NFMT_DEFAULT = NFMT_UNORM,
884
885 NFMT_SHIFT = 4,
886 NFMT_MASK = 7
887};
888
889enum MergedFormat : int64_t {
890 DFMT_NFMT_UNDEF = -1,
891 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
892 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
893
894
895 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
896
897 DFMT_NFMT_MAX = DFMT_NFMT_MASK
898};
899
900enum UnifiedFormatCommon : int64_t {
901 UFMT_MAX = 127,
902 UFMT_UNDEF = -1,
903 UFMT_DEFAULT = 1
904};
905
906} // namespace MTBUFFormat
907
908namespace UfmtGFX10 {
909enum UnifiedFormat : int64_t {
910 UFMT_INVALID = 0,
911
912 UFMT_8_UNORM,
913 UFMT_8_SNORM,
914 UFMT_8_USCALED,
915 UFMT_8_SSCALED,
916 UFMT_8_UINT,
917 UFMT_8_SINT,
918
919 UFMT_16_UNORM,
920 UFMT_16_SNORM,
921 UFMT_16_USCALED,
922 UFMT_16_SSCALED,
923 UFMT_16_UINT,
924 UFMT_16_SINT,
925 UFMT_16_FLOAT,
926
927 UFMT_8_8_UNORM,
928 UFMT_8_8_SNORM,
929 UFMT_8_8_USCALED,
930 UFMT_8_8_SSCALED,
931 UFMT_8_8_UINT,
932 UFMT_8_8_SINT,
933
934 UFMT_32_UINT,
935 UFMT_32_SINT,
936 UFMT_32_FLOAT,
937
938 UFMT_16_16_UNORM,
939 UFMT_16_16_SNORM,
940 UFMT_16_16_USCALED,
941 UFMT_16_16_SSCALED,
942 UFMT_16_16_UINT,
943 UFMT_16_16_SINT,
944 UFMT_16_16_FLOAT,
945
946 UFMT_10_11_11_UNORM,
947 UFMT_10_11_11_SNORM,
948 UFMT_10_11_11_USCALED,
949 UFMT_10_11_11_SSCALED,
950 UFMT_10_11_11_UINT,
951 UFMT_10_11_11_SINT,
952 UFMT_10_11_11_FLOAT,
953
954 UFMT_11_11_10_UNORM,
955 UFMT_11_11_10_SNORM,
956 UFMT_11_11_10_USCALED,
957 UFMT_11_11_10_SSCALED,
958 UFMT_11_11_10_UINT,
959 UFMT_11_11_10_SINT,
960 UFMT_11_11_10_FLOAT,
961
962 UFMT_10_10_10_2_UNORM,
963 UFMT_10_10_10_2_SNORM,
964 UFMT_10_10_10_2_USCALED,
965 UFMT_10_10_10_2_SSCALED,
966 UFMT_10_10_10_2_UINT,
967 UFMT_10_10_10_2_SINT,
968
969 UFMT_2_10_10_10_UNORM,
970 UFMT_2_10_10_10_SNORM,
971 UFMT_2_10_10_10_USCALED,
972 UFMT_2_10_10_10_SSCALED,
973 UFMT_2_10_10_10_UINT,
974 UFMT_2_10_10_10_SINT,
975
976 UFMT_8_8_8_8_UNORM,
977 UFMT_8_8_8_8_SNORM,
978 UFMT_8_8_8_8_USCALED,
979 UFMT_8_8_8_8_SSCALED,
980 UFMT_8_8_8_8_UINT,
981 UFMT_8_8_8_8_SINT,
982
983 UFMT_32_32_UINT,
984 UFMT_32_32_SINT,
985 UFMT_32_32_FLOAT,
986
987 UFMT_16_16_16_16_UNORM,
988 UFMT_16_16_16_16_SNORM,
989 UFMT_16_16_16_16_USCALED,
990 UFMT_16_16_16_16_SSCALED,
991 UFMT_16_16_16_16_UINT,
992 UFMT_16_16_16_16_SINT,
993 UFMT_16_16_16_16_FLOAT,
994
995 UFMT_32_32_32_UINT,
996 UFMT_32_32_32_SINT,
997 UFMT_32_32_32_FLOAT,
998 UFMT_32_32_32_32_UINT,
999 UFMT_32_32_32_32_SINT,
1000 UFMT_32_32_32_32_FLOAT,
1001
1002 UFMT_FIRST = UFMT_INVALID,
1003 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
1004};
1005
1006} // namespace UfmtGFX10
1007
1008namespace UfmtGFX11 {
1009enum UnifiedFormat : int64_t {
1010 UFMT_INVALID = 0,
1011
1012 UFMT_8_UNORM,
1013 UFMT_8_SNORM,
1014 UFMT_8_USCALED,
1015 UFMT_8_SSCALED,
1016 UFMT_8_UINT,
1017 UFMT_8_SINT,
1018
1019 UFMT_16_UNORM,
1020 UFMT_16_SNORM,
1021 UFMT_16_USCALED,
1022 UFMT_16_SSCALED,
1023 UFMT_16_UINT,
1024 UFMT_16_SINT,
1025 UFMT_16_FLOAT,
1026
1027 UFMT_8_8_UNORM,
1028 UFMT_8_8_SNORM,
1029 UFMT_8_8_USCALED,
1030 UFMT_8_8_SSCALED,
1031 UFMT_8_8_UINT,
1032 UFMT_8_8_SINT,
1033
1034 UFMT_32_UINT,
1035 UFMT_32_SINT,
1036 UFMT_32_FLOAT,
1037
1038 UFMT_16_16_UNORM,
1039 UFMT_16_16_SNORM,
1040 UFMT_16_16_USCALED,
1041 UFMT_16_16_SSCALED,
1042 UFMT_16_16_UINT,
1043 UFMT_16_16_SINT,
1044 UFMT_16_16_FLOAT,
1045
1046 UFMT_10_11_11_FLOAT,
1047
1048 UFMT_11_11_10_FLOAT,
1049
1050 UFMT_10_10_10_2_UNORM,
1051 UFMT_10_10_10_2_SNORM,
1052 UFMT_10_10_10_2_UINT,
1053 UFMT_10_10_10_2_SINT,
1054
1055 UFMT_2_10_10_10_UNORM,
1056 UFMT_2_10_10_10_SNORM,
1057 UFMT_2_10_10_10_USCALED,
1058 UFMT_2_10_10_10_SSCALED,
1059 UFMT_2_10_10_10_UINT,
1060 UFMT_2_10_10_10_SINT,
1061
1062 UFMT_8_8_8_8_UNORM,
1063 UFMT_8_8_8_8_SNORM,
1064 UFMT_8_8_8_8_USCALED,
1065 UFMT_8_8_8_8_SSCALED,
1066 UFMT_8_8_8_8_UINT,
1067 UFMT_8_8_8_8_SINT,
1068
1069 UFMT_32_32_UINT,
1070 UFMT_32_32_SINT,
1071 UFMT_32_32_FLOAT,
1072
1073 UFMT_16_16_16_16_UNORM,
1074 UFMT_16_16_16_16_SNORM,
1075 UFMT_16_16_16_16_USCALED,
1076 UFMT_16_16_16_16_SSCALED,
1077 UFMT_16_16_16_16_UINT,
1078 UFMT_16_16_16_16_SINT,
1079 UFMT_16_16_16_16_FLOAT,
1080
1081 UFMT_32_32_32_UINT,
1082 UFMT_32_32_32_SINT,
1083 UFMT_32_32_32_FLOAT,
1084 UFMT_32_32_32_32_UINT,
1085 UFMT_32_32_32_32_SINT,
1086 UFMT_32_32_32_32_FLOAT,
1087
1088 UFMT_FIRST = UFMT_INVALID,
1089 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
1090};
1091
1092} // namespace UfmtGFX11
1093
1094namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
1095
1096enum Id : unsigned { // id of symbolic names
1097 ID_QUAD_PERM = 0,
1098 ID_BITMASK_PERM,
1099 ID_SWAP,
1100 ID_REVERSE,
1101 ID_BROADCAST,
1102 ID_FFT,
1103 ID_ROTATE
1104};
1105
1106// clang-format off
1107enum EncBits : unsigned {
1108
1109 // swizzle mode encodings
1110
1111 QUAD_PERM_ENC = 0x8000,
1112 QUAD_PERM_ENC_MASK = 0xFF00,
1113
1114 BITMASK_PERM_ENC = 0x0000,
1115 BITMASK_PERM_ENC_MASK = 0x8000,
1116
1117 FFT_MODE_ENC = 0xE000,
1118
1119 ROTATE_MODE_ENC = 0xC000,
1120 FFT_ROTATE_MODE_MASK = 0xF000,
1121
1122 ROTATE_MODE_LO = 0xC000,
1123 FFT_MODE_LO = 0xE000,
1124
1125 // QUAD_PERM encodings
1126
1127 LANE_MASK = 0x3,
1128 LANE_MAX = LANE_MASK,
1129 LANE_SHIFT = 2,
1130 LANE_NUM = 4,
1131
1132 // BITMASK_PERM encodings
1133
1134 BITMASK_MASK = 0x1F,
1135 BITMASK_MAX = BITMASK_MASK,
1136 BITMASK_WIDTH = 5,
1137
1138 BITMASK_AND_SHIFT = 0,
1139 BITMASK_OR_SHIFT = 5,
1140 BITMASK_XOR_SHIFT = 10,
1141
1142 // FFT encodings
1143
1144 FFT_SWIZZLE_MASK = 0x1F,
1145 FFT_SWIZZLE_MAX = 0x1F,
1146
1147 // ROTATE encodings
1148 ROTATE_MAX_SIZE = 0x1F,
1149 ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
1150 ROTATE_DIR_MASK = 0x1,
1151 ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
1152 ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
1153};
1154// clang-format on
1155
1156} // namespace Swizzle
1157
1158namespace SDWA {
1159
1160enum SdwaSel : unsigned {
1161 BYTE_0 = 0,
1162 BYTE_1 = 1,
1163 BYTE_2 = 2,
1164 BYTE_3 = 3,
1165 WORD_0 = 4,
1166 WORD_1 = 5,
1167 DWORD = 6,
1168};
1169
1170enum DstUnused : unsigned {
1171 UNUSED_PAD = 0,
1172 UNUSED_SEXT = 1,
1173 UNUSED_PRESERVE = 2,
1174};
1175
1176enum SDWA9EncValues : unsigned {
1177 SRC_SGPR_MASK = 0x100,
1178 SRC_VGPR_MASK = 0xFF,
1179 VOPC_DST_VCC_MASK = 0x80,
1180 VOPC_DST_SGPR_MASK = 0x7F,
1181
1182 SRC_VGPR_MIN = 0,
1183 SRC_VGPR_MAX = 255,
1184 SRC_SGPR_MIN = 256,
1185 SRC_SGPR_MAX_SI = 357,
1186 SRC_SGPR_MAX_GFX10 = 361,
1187 SRC_TTMP_MIN = 364,
1188 SRC_TTMP_MAX = 379,
1189};
1190
1191} // namespace SDWA
1192
1193namespace DPP {
1194
1195// clang-format off
1196enum DppCtrl : unsigned {
1197 QUAD_PERM_FIRST = 0,
1198 QUAD_PERM_ID = 0xE4, // identity permutation
1199 QUAD_PERM_LAST = 0xFF,
1200 DPP_UNUSED1 = 0x100,
1201 ROW_SHL0 = 0x100,
1202 ROW_SHL_FIRST = 0x101,
1203 ROW_SHL_LAST = 0x10F,
1204 DPP_UNUSED2 = 0x110,
1205 ROW_SHR0 = 0x110,
1206 ROW_SHR_FIRST = 0x111,
1207 ROW_SHR_LAST = 0x11F,
1208 DPP_UNUSED3 = 0x120,
1209 ROW_ROR0 = 0x120,
1210 ROW_ROR_FIRST = 0x121,
1211 ROW_ROR_LAST = 0x12F,
1212 WAVE_SHL1 = 0x130,
1213 DPP_UNUSED4_FIRST = 0x131,
1214 DPP_UNUSED4_LAST = 0x133,
1215 WAVE_ROL1 = 0x134,
1216 DPP_UNUSED5_FIRST = 0x135,
1217 DPP_UNUSED5_LAST = 0x137,
1218 WAVE_SHR1 = 0x138,
1219 DPP_UNUSED6_FIRST = 0x139,
1220 DPP_UNUSED6_LAST = 0x13B,
1221 WAVE_ROR1 = 0x13C,
1222 DPP_UNUSED7_FIRST = 0x13D,
1223 DPP_UNUSED7_LAST = 0x13F,
1224 ROW_MIRROR = 0x140,
1225 ROW_HALF_MIRROR = 0x141,
1226 BCAST15 = 0x142,
1227 BCAST31 = 0x143,
1228 DPP_UNUSED8_FIRST = 0x144,
1229 DPP_UNUSED8_LAST = 0x14F,
1230 ROW_NEWBCAST_FIRST= 0x150,
1231 ROW_NEWBCAST_LAST = 0x15F,
1232 ROW_SHARE0 = 0x150,
1233 ROW_SHARE_FIRST = 0x150,
1234 ROW_SHARE_LAST = 0x15F,
1235 ROW_XMASK0 = 0x160,
1236 ROW_XMASK_FIRST = 0x160,
1237 ROW_XMASK_LAST = 0x16F,
1238 DPP_LAST = ROW_XMASK_LAST
1239};
1240// clang-format on
1241
1242enum DppFiMode {
1243 DPP_FI_0 = 0,
1244 DPP_FI_1 = 1,
1245 DPP8_FI_0 = 0xE9,
1246 DPP8_FI_1 = 0xEA,
1247};
1248
1249} // namespace DPP
1250
1251namespace Exp {
1252
1253enum Target : unsigned {
1254 ET_MRT0 = 0,
1255 ET_MRT7 = 7,
1256 ET_MRTZ = 8,
1257 ET_NULL = 9, // Pre-GFX11
1258 ET_POS0 = 12,
1259 ET_POS3 = 15,
1260 ET_POS4 = 16, // GFX10+
1261 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
1262 ET_PRIM = 20, // GFX10+
1263 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
1264 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
1265 ET_PARAM0 = 32, // Pre-GFX11
1266 ET_PARAM31 = 63, // Pre-GFX11
1267
1268 ET_NULL_MAX_IDX = 0,
1269 ET_MRTZ_MAX_IDX = 0,
1270 ET_PRIM_MAX_IDX = 0,
1271 ET_MRT_MAX_IDX = 7,
1272 ET_POS_MAX_IDX = 4,
1273 ET_DUAL_SRC_BLEND_MAX_IDX = 1,
1274 ET_PARAM_MAX_IDX = 31,
1275
1276 ET_INVALID = 255,
1277};
1278
1279} // namespace Exp
1280
1281namespace WMMA {
1282enum MatrixFMT : unsigned {
1283 MATRIX_FMT_FP8 = 0,
1284 MATRIX_FMT_BF8 = 1,
1285 MATRIX_FMT_FP6 = 2,
1286 MATRIX_FMT_BF6 = 3,
1287 MATRIX_FMT_FP4 = 4
1288};
1289
1290enum MatrixScale : unsigned {
1291 MATRIX_SCALE_ROW0 = 0,
1292 MATRIX_SCALE_ROW1 = 1,
1293};
1294
1295enum MatrixScaleFmt : unsigned {
1296 MATRIX_SCALE_FMT_E8 = 0,
1297 MATRIX_SCALE_FMT_E5M3 = 1,
1298 MATRIX_SCALE_FMT_E4M3 = 2
1299};
1300} // namespace WMMA
1301
1302namespace VOP3PEncoding {
1303
1304enum OpSel : uint64_t {
1305 OP_SEL_HI_0 = UINT64_C(1) << 59,
1306 OP_SEL_HI_1 = UINT64_C(1) << 60,
1307 OP_SEL_HI_2 = UINT64_C(1) << 14,
1308};
1309
1310} // namespace VOP3PEncoding
1311
1312namespace ImplicitArg {
1313// Implicit kernel argument offset for code object version 5.
1314enum Offset_COV5 : unsigned {
1315 HOSTCALL_PTR_OFFSET = 80,
1316 MULTIGRID_SYNC_ARG_OFFSET = 88,
1317 HEAP_PTR_OFFSET = 96,
1318
1319 DEFAULT_QUEUE_OFFSET = 104,
1320 COMPLETION_ACTION_OFFSET = 112,
1321
1322 PRIVATE_BASE_OFFSET = 192,
1323 SHARED_BASE_OFFSET = 196,
1324 QUEUE_PTR_OFFSET = 200,
1325};
1326
1327} // namespace ImplicitArg
1328
1329namespace MFMAScaleFormats {
1330// Enum value used in cbsz/blgp for F8F6F4 MFMA operations to select the matrix
1331// format.
1332enum MFMAScaleFormats {
1333 FP8_E4M3 = 0,
1334 FP8_E5M2 = 1,
1335 FP6_E2M3 = 2,
1336 FP6_E3M2 = 3,
1337 FP4_E2M1 = 4
1338};
1339} // namespace MFMAScaleFormats
1340
1341namespace VirtRegFlag {
1342// Virtual register flags used for various target specific handlings during
1343// codegen.
1344enum Register_Flag : uint8_t {
1345 // Register operand in a whole-wave mode operation.
1346 WWM_REG = 1 << 0,
1347};
1348
1349} // namespace VirtRegFlag
1350
1351} // namespace AMDGPU
1352
1353namespace AMDGPU {
1354namespace Barrier {
1355
1356enum Type {
1357 CLUSTER_TRAP = -4,
1358 CLUSTER = -3,
1359 TRAP = -2,
1360 WORKGROUP = -1,
1361 NAMED_BARRIER_FIRST = 1,
1362 NAMED_BARRIER_LAST = 16,
1363};
1364
1365enum {
1366 BARRIER_SCOPE_WORKGROUP = 0,
1367};
1368
1369} // namespace Barrier
1370} // namespace AMDGPU
1371
1372// clang-format off
1373
1374#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1375#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1376#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1377#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1378#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1379#define C_00B028_MEM_ORDERED 0xFDFFFFFF
1380
1381#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1382#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1383#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1384#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1385#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1386#define C_00B128_MEM_ORDERED 0xF7FFFFFF
1387
1388#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1389#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1390#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1391#define C_00B228_WGP_MODE 0xF7FFFFFF
1392#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1393#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1394#define C_00B228_MEM_ORDERED 0xFDFFFFFF
1395
1396#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1397#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1398#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1399#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1400#define C_00B428_WGP_MODE 0xFBFFFFFF
1401#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1402#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1403#define C_00B428_MEM_ORDERED 0xFEFFFFFF
1404
1405#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1406
1407#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1408#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1409#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1410#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1411#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1412#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1413#define C_00B84C_USER_SGPR 0xFFFFFFC1
1414#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1415#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1416#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1417#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1418#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1419#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1420#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1421#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1422#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1423#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1424#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1425#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1426#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1427#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1428#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1429#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1430#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1431#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1432/* CIK */
1433#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1434#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1435#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1436/* */
1437#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1438#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1439#define C_00B84C_LDS_SIZE 0xFF007FFF
1440#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1441#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1442#define C_00B84C_EXCP_EN 0x80FFFFFF
1443
1444#define S_00B84C_USER_SGPR_GFX1250(x) (((x) & 0x3F) << 1)
1445#define G_00B84C_USER_SGPR_GFX1250(x) (((x) >> 1) & 0x3F)
1446#define C_00B84C_USER_SGPR_GFX1250 0xFFFFFF81
1447
1448#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1449#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1450
1451#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1452#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1453#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1454#define C_00B848_VGPRS 0xFFFFFFC0
1455#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1456#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1457#define C_00B848_SGPRS 0xFFFFFC3F
1458#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1459#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1460#define C_00B848_PRIORITY 0xFFFFF3FF
1461#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1462#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1463#define C_00B848_FLOAT_MODE 0xFFF00FFF
1464#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1465#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1466#define C_00B848_PRIV 0xFFEFFFFF
1467#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1468#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1469#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1470#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1471#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1472#define C_00B848_RR_WG_MODE 0xFFDFFFFF
1473#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1474#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1475#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1476#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1477#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1478#define C_00B848_IEEE_MODE 0xFF7FFFFF
1479#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1480#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1481#define C_00B848_WGP_MODE 0xDFFFFFFF
1482#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1483#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1484#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1485#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1486#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1487#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1488
1489// Helpers for setting FLOAT_MODE
1490#define FP_ROUND_ROUND_TO_NEAREST 0
1491#define FP_ROUND_ROUND_TO_INF 1
1492#define FP_ROUND_ROUND_TO_NEGINF 2
1493#define FP_ROUND_ROUND_TO_ZERO 3
1494
1495// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1496// precision.
1497#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1498#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1499
1500#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1501#define FP_DENORM_FLUSH_OUT 1
1502#define FP_DENORM_FLUSH_IN 2
1503#define FP_DENORM_FLUSH_NONE 3
1504
1505
1506// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1507// precision.
1508#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1509#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1510
1511#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1512#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1513#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1514#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1515
1516#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1517#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1518#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1519#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1520
1521#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1522#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1523#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1524#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1525#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1526#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1527#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1528#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1529
1530#define R_SPILLED_SGPRS 0x4
1531#define R_SPILLED_VGPRS 0x8
1532
1533// clang-format on
1534
1535} // End namespace llvm
1536
1537#endif
1538