1//===-- LoongArchAsmBackend.cpp - LoongArch Assembler Backend -*- C++ -*---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LoongArchAsmBackend class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchAsmBackend.h"
14#include "LoongArchFixupKinds.h"
15#include "llvm/BinaryFormat/ELF.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCAssembler.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCELFObjectWriter.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCSection.h"
22#include "llvm/MC/MCValue.h"
23#include "llvm/Support/EndianStream.h"
24#include "llvm/Support/LEB128.h"
25#include "llvm/Support/MathExtras.h"
26
27#define DEBUG_TYPE "loongarch-asmbackend"
28
29using namespace llvm;
30
31LoongArchAsmBackend::LoongArchAsmBackend(const MCSubtargetInfo &STI,
32 uint8_t OSABI, bool Is64Bit,
33 const MCTargetOptions &Options)
34 : MCAsmBackend(llvm::endianness::little), STI(STI), OSABI(OSABI),
35 Is64Bit(Is64Bit), TargetOptions(Options) {}
36
37std::optional<MCFixupKind>
38LoongArchAsmBackend::getFixupKind(StringRef Name) const {
39 if (STI.getTargetTriple().isOSBinFormatELF()) {
40 auto Type = llvm::StringSwitch<unsigned>(Name)
41#define ELF_RELOC(X, Y) .Case(#X, Y)
42#include "llvm/BinaryFormat/ELFRelocs/LoongArch.def"
43#undef ELF_RELOC
44 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_LARCH_NONE)
45 .Case(S: "BFD_RELOC_32", Value: ELF::R_LARCH_32)
46 .Case(S: "BFD_RELOC_64", Value: ELF::R_LARCH_64)
47 .Default(Value: -1u);
48 if (Type != -1u)
49 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
50 }
51 return std::nullopt;
52}
53
54MCFixupKindInfo LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
55 const static MCFixupKindInfo Infos[] = {
56 // This table *must* be in the order that the fixup_* kinds are defined in
57 // LoongArchFixupKinds.h.
58 //
59 // {name, offset, bits, flags}
60 {.Name: "fixup_loongarch_b16", .TargetOffset: 10, .TargetSize: 16, .Flags: 0},
61 {.Name: "fixup_loongarch_b21", .TargetOffset: 0, .TargetSize: 26, .Flags: 0},
62 {.Name: "fixup_loongarch_b26", .TargetOffset: 0, .TargetSize: 26, .Flags: 0},
63 {.Name: "fixup_loongarch_abs_hi20", .TargetOffset: 5, .TargetSize: 20, .Flags: 0},
64 {.Name: "fixup_loongarch_abs_lo12", .TargetOffset: 10, .TargetSize: 12, .Flags: 0},
65 {.Name: "fixup_loongarch_abs64_lo20", .TargetOffset: 5, .TargetSize: 20, .Flags: 0},
66 {.Name: "fixup_loongarch_abs64_hi12", .TargetOffset: 10, .TargetSize: 12, .Flags: 0},
67 {.Name: "fixup_loongarch_dtprel32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
68 {.Name: "fixup_loongarch_dtprel64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0},
69 };
70
71 static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds,
72 "Not all fixup kinds added to Infos array");
73
74 // Fixup kinds from .reloc directive are like R_LARCH_NONE. They
75 // do not require any extra processing.
76 if (mc::isRelocation(FixupKind: Kind))
77 return {};
78
79 if (Kind < FirstTargetFixupKind)
80 return MCAsmBackend::getFixupKindInfo(Kind);
81
82 assert(unsigned(Kind - FirstTargetFixupKind) <
83 LoongArch::NumTargetFixupKinds &&
84 "Invalid kind!");
85 return Infos[Kind - FirstTargetFixupKind];
86}
87
88static void reportOutOfRangeError(MCContext &Ctx, SMLoc Loc, unsigned N) {
89 Ctx.reportError(L: Loc, Msg: "fixup value out of range [" + Twine(llvm::minIntN(N)) +
90 ", " + Twine(llvm::maxIntN(N)) + "]");
91}
92
93static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
94 MCContext &Ctx) {
95 switch (Fixup.getKind()) {
96 default:
97 llvm_unreachable("Unknown fixup kind");
98 case FK_Data_1:
99 case FK_Data_2:
100 case FK_Data_4:
101 case FK_Data_8:
102 case FK_Data_leb128:
103 case LoongArch::fixup_loongarch_dtprel32:
104 case LoongArch::fixup_loongarch_dtprel64:
105 return Value;
106 case LoongArch::fixup_loongarch_b16: {
107 if (!isInt<18>(x: Value))
108 reportOutOfRangeError(Ctx, Loc: Fixup.getLoc(), N: 18);
109 if (Value % 4)
110 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 4-byte aligned");
111 return (Value >> 2) & 0xffff;
112 }
113 case LoongArch::fixup_loongarch_b21: {
114 if (!isInt<23>(x: Value))
115 reportOutOfRangeError(Ctx, Loc: Fixup.getLoc(), N: 23);
116 if (Value % 4)
117 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 4-byte aligned");
118 return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x1f);
119 }
120 case LoongArch::fixup_loongarch_b26: {
121 if (!isInt<28>(x: Value))
122 reportOutOfRangeError(Ctx, Loc: Fixup.getLoc(), N: 28);
123 if (Value % 4)
124 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 4-byte aligned");
125 return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x3ff);
126 }
127 case LoongArch::fixup_loongarch_abs_hi20:
128 return (Value >> 12) & 0xfffff;
129 case LoongArch::fixup_loongarch_abs_lo12:
130 return Value & 0xfff;
131 case LoongArch::fixup_loongarch_abs64_lo20:
132 return (Value >> 32) & 0xfffff;
133 case LoongArch::fixup_loongarch_abs64_hi12:
134 return (Value >> 52) & 0xfff;
135 }
136}
137
138static void fixupLeb128(MCContext &Ctx, const MCFixup &Fixup, uint8_t *Data,
139 uint64_t Value) {
140 unsigned I;
141 for (I = 0; Value; ++I, Value >>= 7)
142 Data[I] |= uint8_t(Value & 0x7f);
143}
144
145void LoongArchAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
146 const MCValue &Target, uint8_t *Data,
147 uint64_t Value, bool IsResolved) {
148 IsResolved = addReloc(F, Fixup, Target, FixedValue&: Value, IsResolved);
149 if (!Value)
150 return; // Doesn't change encoding.
151
152 auto Kind = Fixup.getKind();
153 if (mc::isRelocation(FixupKind: Kind))
154 return;
155 MCFixupKindInfo Info = getFixupKindInfo(Kind);
156 MCContext &Ctx = getContext();
157
158 // Fixup leb128 separately.
159 if (Fixup.getKind() == FK_Data_leb128)
160 return fixupLeb128(Ctx, Fixup, Data, Value);
161
162 // Apply any target-specific value adjustments.
163 Value = adjustFixupValue(Fixup, Value, Ctx);
164
165 // Shift the value into position.
166 Value <<= Info.TargetOffset;
167
168 unsigned NumBytes = alignTo(Value: Info.TargetSize + Info.TargetOffset, Align: 8) / 8;
169
170 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&
171 "Invalid fixup offset!");
172 // For each byte of the fragment that the fixup touches, mask in the
173 // bits from the fixup value.
174 for (unsigned I = 0; I != NumBytes; ++I) {
175 Data[I] |= uint8_t((Value >> (I * 8)) & 0xff);
176 }
177}
178
179static inline std::pair<MCFixupKind, MCFixupKind>
180getRelocPairForSize(unsigned Size) {
181 switch (Size) {
182 default:
183 llvm_unreachable("unsupported fixup size");
184 case 6:
185 return std::make_pair(x: ELF::R_LARCH_ADD6, y: ELF::R_LARCH_SUB6);
186 case 8:
187 return std::make_pair(x: ELF::R_LARCH_ADD8, y: ELF::R_LARCH_SUB8);
188 case 16:
189 return std::make_pair(x: ELF::R_LARCH_ADD16, y: ELF::R_LARCH_SUB16);
190 case 32:
191 return std::make_pair(x: ELF::R_LARCH_ADD32, y: ELF::R_LARCH_SUB32);
192 case 64:
193 return std::make_pair(x: ELF::R_LARCH_ADD64, y: ELF::R_LARCH_SUB64);
194 case 128:
195 return std::make_pair(x: ELF::R_LARCH_ADD_ULEB128, y: ELF::R_LARCH_SUB_ULEB128);
196 }
197}
198
199// Check if an R_LARCH_ALIGN relocation is needed for an alignment directive.
200// If conditions are met, compute the padding size and create a fixup encoding
201// the padding size in the addend. If MaxBytesToEmit is smaller than the padding
202// size, the fixup encodes MaxBytesToEmit in the higher bits and references a
203// per-section marker symbol.
204bool LoongArchAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) {
205 // Alignments before the first linker-relaxable instruction have fixed sizes
206 // and do not require relocations. Alignments after a linker-relaxable
207 // instruction require a relocation, even if the STI specifies norelax.
208 //
209 // firstLinkerRelaxable is the layout order within the subsection, which may
210 // be smaller than the section's order. Therefore, alignments in a
211 // lower-numbered subsection may be unnecessarily treated as linker-relaxable.
212 auto *Sec = F.getParent();
213 if (F.getLayoutOrder() <= Sec->firstLinkerRelaxable())
214 return false;
215
216 // Use default handling unless linker relaxation is enabled and the
217 // MaxBytesToEmit >= the nop size.
218 const unsigned MinNopLen = 4;
219 unsigned MaxBytesToEmit = F.getAlignMaxBytesToEmit();
220 if (MaxBytesToEmit < MinNopLen)
221 return false;
222
223 Size = F.getAlignment().value() - MinNopLen;
224 if (F.getAlignment() <= MinNopLen)
225 return false;
226
227 MCContext &Ctx = getContext();
228 const MCExpr *Expr = nullptr;
229 if (MaxBytesToEmit >= Size) {
230 Expr = MCConstantExpr::create(Value: Size, Ctx&: getContext());
231 } else {
232 MCSection *Sec = F.getParent();
233 const MCSymbolRefExpr *SymRef = getSecToAlignSym()[Sec];
234 if (SymRef == nullptr) {
235 // Define a marker symbol at the section with an offset of 0.
236 MCSymbol *Sym = Ctx.createNamedTempSymbol(Name: "la-relax-align");
237 Sym->setFragment(&*Sec->getBeginSymbol()->getFragment());
238 Asm->registerSymbol(Symbol: *Sym);
239 SymRef = MCSymbolRefExpr::create(Symbol: Sym, Ctx);
240 getSecToAlignSym()[Sec] = SymRef;
241 }
242 Expr = MCBinaryExpr::createAdd(
243 LHS: SymRef,
244 RHS: MCConstantExpr::create(Value: (MaxBytesToEmit << 8) | Log2(A: F.getAlignment()),
245 Ctx),
246 Ctx);
247 }
248 MCFixup Fixup =
249 MCFixup::create(Offset: 0, Value: Expr, Kind: FirstLiteralRelocationKind + ELF::R_LARCH_ALIGN);
250 F.setVarFixups({Fixup});
251 F.setLinkerRelaxable();
252 return true;
253}
254
255std::pair<bool, bool> LoongArchAsmBackend::relaxLEB128(MCFragment &F,
256 int64_t &Value) const {
257 const MCExpr &Expr = F.getLEBValue();
258 if (F.isLEBSigned() || !Expr.evaluateKnownAbsolute(Res&: Value, Asm: *Asm))
259 return std::make_pair(x: false, y: false);
260 F.setVarFixups({MCFixup::create(Offset: 0, Value: &Expr, Kind: FK_Data_leb128)});
261 return std::make_pair(x: true, y: true);
262}
263
264bool LoongArchAsmBackend::relaxDwarfLineAddr(MCFragment &F) const {
265 MCContext &C = getContext();
266 int64_t LineDelta = F.getDwarfLineDelta();
267 const MCExpr &AddrDelta = F.getDwarfAddrDelta();
268 int64_t Value;
269 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm: *Asm))
270 return false;
271 [[maybe_unused]] bool IsAbsolute =
272 AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm: *Asm);
273 assert(IsAbsolute);
274
275 SmallVector<char> Data;
276 raw_svector_ostream OS(Data);
277
278 // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
279 if (LineDelta != INT64_MAX) {
280 OS << uint8_t(dwarf::DW_LNS_advance_line);
281 encodeSLEB128(Value: LineDelta, OS);
282 }
283
284 // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
285 // takes a single unsigned half (unencoded) operand. The maximum encodable
286 // value is therefore 65535. Set a conservative upper bound for relaxation.
287 unsigned PCBytes;
288 if (Value > 60000) {
289 unsigned PtrSize = C.getAsmInfo().getCodePointerSize();
290 assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size");
291 PCBytes = PtrSize;
292 OS << uint8_t(dwarf::DW_LNS_extended_op) << uint8_t(PtrSize + 1)
293 << uint8_t(dwarf::DW_LNE_set_address);
294 OS.write_zeros(NumZeros: PtrSize);
295 } else {
296 PCBytes = 2;
297 OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
298 support::endian::write<uint16_t>(os&: OS, value: 0, endian: llvm::endianness::little);
299 }
300 auto Offset = OS.tell() - PCBytes;
301
302 if (LineDelta == INT64_MAX) {
303 OS << uint8_t(dwarf::DW_LNS_extended_op);
304 OS << uint8_t(1);
305 OS << uint8_t(dwarf::DW_LNE_end_sequence);
306 } else {
307 OS << uint8_t(dwarf::DW_LNS_copy);
308 }
309
310 F.setVarContents(Data);
311 F.setVarFixups({MCFixup::create(Offset, Value: &AddrDelta,
312 Kind: MCFixup::getDataKindForSize(Size: PCBytes))});
313 return true;
314}
315
316bool LoongArchAsmBackend::relaxDwarfCFA(MCFragment &F) const {
317 const MCExpr &AddrDelta = F.getDwarfAddrDelta();
318 SmallVector<MCFixup, 2> Fixups;
319 int64_t Value;
320 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm: *Asm))
321 return false;
322 bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm: *Asm);
323 assert(IsAbsolute && "CFA with invalid expression");
324 (void)IsAbsolute;
325
326 assert(getContext().getAsmInfo().getMinInstAlignment() == 1 &&
327 "expected 1-byte alignment");
328 if (Value == 0) {
329 F.clearVarContents();
330 F.clearVarFixups();
331 return true;
332 }
333
334 auto AddFixups = [&Fixups,
335 &AddrDelta](unsigned Offset,
336 std::pair<MCFixupKind, MCFixupKind> FK) {
337 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(Val: AddrDelta);
338 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getLHS(), Kind: std::get<0>(in&: FK)));
339 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getRHS(), Kind: std::get<1>(in&: FK)));
340 };
341
342 SmallVector<char, 8> Data;
343 raw_svector_ostream OS(Data);
344 if (isUIntN(N: 6, x: Value)) {
345 OS << uint8_t(dwarf::DW_CFA_advance_loc);
346 AddFixups(0, getRelocPairForSize(Size: 6));
347 } else if (isUInt<8>(x: Value)) {
348 OS << uint8_t(dwarf::DW_CFA_advance_loc1);
349 support::endian::write<uint8_t>(os&: OS, value: 0, endian: llvm::endianness::little);
350 AddFixups(1, getRelocPairForSize(Size: 8));
351 } else if (isUInt<16>(x: Value)) {
352 OS << uint8_t(dwarf::DW_CFA_advance_loc2);
353 support::endian::write<uint16_t>(os&: OS, value: 0, endian: llvm::endianness::little);
354 AddFixups(1, getRelocPairForSize(Size: 16));
355 } else if (isUInt<32>(x: Value)) {
356 OS << uint8_t(dwarf::DW_CFA_advance_loc4);
357 support::endian::write<uint32_t>(os&: OS, value: 0, endian: llvm::endianness::little);
358 AddFixups(1, getRelocPairForSize(Size: 32));
359 } else {
360 llvm_unreachable("unsupported CFA encoding");
361 }
362 F.setVarContents(Data);
363 F.setVarFixups(Fixups);
364 return true;
365}
366
367bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
368 const MCSubtargetInfo *STI) const {
369 // We mostly follow binutils' convention here: align to 4-byte boundary with a
370 // 0-fill padding.
371 OS.write_zeros(NumZeros: Count % 4);
372
373 // The remainder is now padded with 4-byte nops.
374 // nop: andi r0, r0, 0
375 for (; Count >= 4; Count -= 4)
376 OS.write(Ptr: "\0\0\x40\x03", Size: 4);
377
378 return true;
379}
380
381bool LoongArchAsmBackend::isPCRelFixupResolved(const MCSymbol *SymA,
382 const MCFragment &F) {
383 // If the section does not contain linker-relaxable fragments, PC-relative
384 // fixups can be resolved.
385 if (!F.getParent()->isLinkerRelaxable())
386 return true;
387
388 // Otherwise, check if the offset between the symbol and fragment is fully
389 // resolved, unaffected by linker-relaxable fragments (e.g. instructions or
390 // offset-affected FT_Align fragments). Complements the generic
391 // isSymbolRefDifferenceFullyResolvedImpl.
392 if (!PCRelTemp)
393 PCRelTemp = getContext().createTempSymbol();
394 PCRelTemp->setFragment(const_cast<MCFragment *>(&F));
395 MCValue Res;
396 MCExpr::evaluateSymbolicAdd(Asm, false, MCValue::get(SymA),
397 MCValue::get(SymA: nullptr, SymB: PCRelTemp), Res);
398 return !Res.getSubSym();
399}
400
401bool LoongArchAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
402 const MCValue &Target, uint64_t &FixedValue,
403 bool IsResolved) {
404 auto Fallback = [&]() {
405 MCAsmBackend::maybeAddReloc(F, Fixup, Target, Value&: FixedValue, IsResolved);
406 return true;
407 };
408 uint64_t FixedValueA, FixedValueB;
409 if (Target.getSubSym()) {
410 // It's possible for Target to have (SymB != nullptr && SymA == nullptr).
411 // Go to the fallback path when we encounter this. See also #196927.
412 if (!Target.getAddSym())
413 return Fallback();
414
415 assert(Target.getSpecifier() == 0 &&
416 "relocatable SymA-SymB cannot have relocation specifier");
417 std::pair<MCFixupKind, MCFixupKind> FK;
418 const MCSymbol &SA = *Target.getAddSym();
419 const MCSymbol &SB = *Target.getSubSym();
420
421 bool force = !SA.isInSection() || !SB.isInSection();
422 if (!force) {
423 const MCSection &SecA = SA.getSection();
424 const MCSection &SecB = SB.getSection();
425 const MCSection &SecCur = *F.getParent();
426
427 // To handle the case of A - B which B is same section with the current,
428 // generate PCRel relocations is better than ADD/SUB relocation pair.
429 // We can resolve it as A - PC + PC - B. The A - PC will be resolved
430 // as a PCRel relocation, while PC - B will serve as the addend.
431 // If the linker relaxation is disabled, it can be done directly since
432 // PC - B is constant. Otherwise, we should evaluate whether PC - B
433 // is constant. If it can be resolved as PCRel, use Fallback which
434 // generates R_LARCH_{32,64}_PCREL relocation later.
435 if (&SecA != &SecB && &SecB == &SecCur &&
436 isPCRelFixupResolved(SymA: Target.getSubSym(), F))
437 return Fallback();
438
439 if (&SecA == &SecB) {
440 // If the section is not linker-relaxable, or if the fixup is in a .dwo
441 // section (where relocations are forbidden), we must resolve the
442 // difference directly. The computed Value in evaluateFixup is correct
443 // based on the current layout.
444 if (!SecA.isLinkerRelaxable() || SecCur.getName().ends_with(Suffix: ".dwo"))
445 return true;
446 }
447 }
448
449 switch (Fixup.getKind()) {
450 case llvm::FK_Data_1:
451 FK = getRelocPairForSize(Size: 8);
452 break;
453 case llvm::FK_Data_2:
454 FK = getRelocPairForSize(Size: 16);
455 break;
456 case llvm::FK_Data_4:
457 FK = getRelocPairForSize(Size: 32);
458 break;
459 case llvm::FK_Data_8:
460 FK = getRelocPairForSize(Size: 64);
461 break;
462 case llvm::FK_Data_leb128:
463 FK = getRelocPairForSize(Size: 128);
464 break;
465 default:
466 llvm_unreachable("unsupported fixup size");
467 }
468 MCValue A = MCValue::get(SymA: Target.getAddSym(), SymB: nullptr, Val: Target.getConstant());
469 MCValue B = MCValue::get(SymA: Target.getSubSym());
470 auto FA = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: std::get<0>(in&: FK));
471 auto FB = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: std::get<1>(in&: FK));
472 Asm->getWriter().recordRelocation(F, Fixup: FA, Target: A, FixedValue&: FixedValueA);
473 Asm->getWriter().recordRelocation(F, Fixup: FB, Target: B, FixedValue&: FixedValueB);
474 FixedValue = FixedValueA - FixedValueB;
475 return false;
476 }
477
478 // If linker relaxation is enabled and supported by the current relocation,
479 // generate a relocation and then append a RELAX.
480 if (Fixup.isLinkerRelaxable())
481 IsResolved = false;
482 if (IsResolved && Fixup.isPCRel())
483 IsResolved = isPCRelFixupResolved(SymA: Target.getAddSym(), F);
484
485 if (!IsResolved)
486 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
487
488 if (Fixup.isLinkerRelaxable()) {
489 auto FA = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: ELF::R_LARCH_RELAX);
490 Asm->getWriter().recordRelocation(F, Fixup: FA, Target: MCValue::get(SymA: nullptr),
491 FixedValue&: FixedValueA);
492 }
493
494 return true;
495}
496
497std::unique_ptr<MCObjectTargetWriter>
498LoongArchAsmBackend::createObjectTargetWriter() const {
499 return createLoongArchELFObjectWriter(OSABI, Is64Bit);
500}
501
502MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T,
503 const MCSubtargetInfo &STI,
504 const MCRegisterInfo &MRI,
505 const MCTargetOptions &Options) {
506 const Triple &TT = STI.getTargetTriple();
507 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TT.getOS());
508 return new LoongArchAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
509}
510