1//===-- LoongArchAsmBackend.cpp - LoongArch Assembler Backend -*- C++ -*---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LoongArchAsmBackend class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchAsmBackend.h"
14#include "LoongArchFixupKinds.h"
15#include "llvm/BinaryFormat/ELF.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCAssembler.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCELFObjectWriter.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCSection.h"
22#include "llvm/MC/MCValue.h"
23#include "llvm/Support/EndianStream.h"
24#include "llvm/Support/LEB128.h"
25#include "llvm/Support/MathExtras.h"
26
27#define DEBUG_TYPE "loongarch-asmbackend"
28
29using namespace llvm;
30
31LoongArchAsmBackend::LoongArchAsmBackend(const MCSubtargetInfo &STI,
32 uint8_t OSABI, bool Is64Bit,
33 const MCTargetOptions &Options)
34 : MCAsmBackend(llvm::endianness::little), STI(STI), OSABI(OSABI),
35 Is64Bit(Is64Bit), TargetOptions(Options) {}
36
37std::optional<MCFixupKind>
38LoongArchAsmBackend::getFixupKind(StringRef Name) const {
39 if (STI.getTargetTriple().isOSBinFormatELF()) {
40 auto Type = llvm::StringSwitch<unsigned>(Name)
41#define ELF_RELOC(X, Y) .Case(#X, Y)
42#include "llvm/BinaryFormat/ELFRelocs/LoongArch.def"
43#undef ELF_RELOC
44 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_LARCH_NONE)
45 .Case(S: "BFD_RELOC_32", Value: ELF::R_LARCH_32)
46 .Case(S: "BFD_RELOC_64", Value: ELF::R_LARCH_64)
47 .Default(Value: -1u);
48 if (Type != -1u)
49 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
50 }
51 return std::nullopt;
52}
53
54MCFixupKindInfo LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
55 const static MCFixupKindInfo Infos[] = {
56 // This table *must* be in the order that the fixup_* kinds are defined in
57 // LoongArchFixupKinds.h.
58 //
59 // {name, offset, bits, flags}
60 {.Name: "fixup_loongarch_b16", .TargetOffset: 10, .TargetSize: 16, .Flags: 0},
61 {.Name: "fixup_loongarch_b21", .TargetOffset: 0, .TargetSize: 26, .Flags: 0},
62 {.Name: "fixup_loongarch_b26", .TargetOffset: 0, .TargetSize: 26, .Flags: 0},
63 {.Name: "fixup_loongarch_abs_hi20", .TargetOffset: 5, .TargetSize: 20, .Flags: 0},
64 {.Name: "fixup_loongarch_abs_lo12", .TargetOffset: 10, .TargetSize: 12, .Flags: 0},
65 {.Name: "fixup_loongarch_abs64_lo20", .TargetOffset: 5, .TargetSize: 20, .Flags: 0},
66 {.Name: "fixup_loongarch_abs64_hi12", .TargetOffset: 10, .TargetSize: 12, .Flags: 0},
67 {.Name: "fixup_loongarch_dtprel32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
68 {.Name: "fixup_loongarch_dtprel64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0},
69 };
70
71 static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds,
72 "Not all fixup kinds added to Infos array");
73
74 // Fixup kinds from .reloc directive are like R_LARCH_NONE. They
75 // do not require any extra processing.
76 if (mc::isRelocation(FixupKind: Kind))
77 return {};
78
79 if (Kind < FirstTargetFixupKind)
80 return MCAsmBackend::getFixupKindInfo(Kind);
81
82 assert(unsigned(Kind - FirstTargetFixupKind) <
83 LoongArch::NumTargetFixupKinds &&
84 "Invalid kind!");
85 return Infos[Kind - FirstTargetFixupKind];
86}
87
88static void reportOutOfRangeError(MCContext &Ctx, SMLoc Loc, unsigned N) {
89 Ctx.reportError(L: Loc, Msg: "fixup value out of range [" + Twine(llvm::minIntN(N)) +
90 ", " + Twine(llvm::maxIntN(N)) + "]");
91}
92
93static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
94 MCContext &Ctx) {
95 switch (Fixup.getKind()) {
96 default:
97 llvm_unreachable("Unknown fixup kind");
98 case FK_Data_1:
99 case FK_Data_2:
100 case FK_Data_4:
101 case FK_Data_8:
102 case FK_Data_leb128:
103 case LoongArch::fixup_loongarch_dtprel32:
104 case LoongArch::fixup_loongarch_dtprel64:
105 return Value;
106 case LoongArch::fixup_loongarch_b16: {
107 if (!isInt<18>(x: Value))
108 reportOutOfRangeError(Ctx, Loc: Fixup.getLoc(), N: 18);
109 if (Value % 4)
110 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 4-byte aligned");
111 return (Value >> 2) & 0xffff;
112 }
113 case LoongArch::fixup_loongarch_b21: {
114 if (!isInt<23>(x: Value))
115 reportOutOfRangeError(Ctx, Loc: Fixup.getLoc(), N: 23);
116 if (Value % 4)
117 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 4-byte aligned");
118 return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x1f);
119 }
120 case LoongArch::fixup_loongarch_b26: {
121 if (!isInt<28>(x: Value))
122 reportOutOfRangeError(Ctx, Loc: Fixup.getLoc(), N: 28);
123 if (Value % 4)
124 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 4-byte aligned");
125 return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x3ff);
126 }
127 case LoongArch::fixup_loongarch_abs_hi20:
128 return (Value >> 12) & 0xfffff;
129 case LoongArch::fixup_loongarch_abs_lo12:
130 return Value & 0xfff;
131 case LoongArch::fixup_loongarch_abs64_lo20:
132 return (Value >> 32) & 0xfffff;
133 case LoongArch::fixup_loongarch_abs64_hi12:
134 return (Value >> 52) & 0xfff;
135 }
136}
137
138static void fixupLeb128(MCContext &Ctx, const MCFixup &Fixup, uint8_t *Data,
139 uint64_t Value) {
140 unsigned I;
141 for (I = 0; Value; ++I, Value >>= 7)
142 Data[I] |= uint8_t(Value & 0x7f);
143}
144
145void LoongArchAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
146 const MCValue &Target, uint8_t *Data,
147 uint64_t Value, bool IsResolved) {
148 addReloc(F, Fixup, Target, FixedValue&: Value, IsResolved);
149 if (!Value)
150 return; // Doesn't change encoding.
151
152 auto Kind = Fixup.getKind();
153 if (mc::isRelocation(FixupKind: Kind))
154 return;
155 MCFixupKindInfo Info = getFixupKindInfo(Kind);
156 MCContext &Ctx = getContext();
157
158 // Fixup leb128 separately.
159 if (Fixup.getKind() == FK_Data_leb128)
160 return fixupLeb128(Ctx, Fixup, Data, Value);
161
162 // Apply any target-specific value adjustments.
163 Value = adjustFixupValue(Fixup, Value, Ctx);
164
165 // Shift the value into position.
166 Value <<= Info.TargetOffset;
167
168 unsigned NumBytes = alignTo(Value: Info.TargetSize + Info.TargetOffset, Align: 8) / 8;
169
170 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&
171 "Invalid fixup offset!");
172 // For each byte of the fragment that the fixup touches, mask in the
173 // bits from the fixup value.
174 for (unsigned I = 0; I != NumBytes; ++I) {
175 Data[I] |= uint8_t((Value >> (I * 8)) & 0xff);
176 }
177}
178
179static inline std::pair<MCFixupKind, MCFixupKind>
180getRelocPairForSize(unsigned Size) {
181 switch (Size) {
182 default:
183 llvm_unreachable("unsupported fixup size");
184 case 6:
185 return std::make_pair(x: ELF::R_LARCH_ADD6, y: ELF::R_LARCH_SUB6);
186 case 8:
187 return std::make_pair(x: ELF::R_LARCH_ADD8, y: ELF::R_LARCH_SUB8);
188 case 16:
189 return std::make_pair(x: ELF::R_LARCH_ADD16, y: ELF::R_LARCH_SUB16);
190 case 32:
191 return std::make_pair(x: ELF::R_LARCH_ADD32, y: ELF::R_LARCH_SUB32);
192 case 64:
193 return std::make_pair(x: ELF::R_LARCH_ADD64, y: ELF::R_LARCH_SUB64);
194 case 128:
195 return std::make_pair(x: ELF::R_LARCH_ADD_ULEB128, y: ELF::R_LARCH_SUB_ULEB128);
196 }
197}
198
199// Check whether an alignment fragment needs linker relaxation.
200bool LoongArchAsmBackend::shouldRelaxAlign(const MCFragment &F) {
201 // Alignments before the first linker-relaxable instruction have fixed sizes
202 // and do not require relocations. Alignments after a linker-relaxable
203 // instruction require a relocation, even if the STI specifies norelax.
204 //
205 // firstLinkerRelaxable is the layout order within the subsection, which may
206 // be smaller than the section's order. Therefore, alignments in a
207 // lower-numbered subsection may be unnecessarily treated as linker-relaxable.
208 auto *Sec = F.getParent();
209 if (F.getLayoutOrder() <= Sec->firstLinkerRelaxable())
210 return false;
211
212 const unsigned MinNopLen = 4;
213 if (F.getAlignMaxBytesToEmit() < MinNopLen)
214 return false;
215 if (F.getAlignment() <= MinNopLen)
216 return false;
217
218 return true;
219}
220
221// Check if an R_LARCH_ALIGN relocation is needed for an alignment directive.
222// If conditions are met, compute the padding size and create a fixup encoding
223// the padding size in the addend. If MaxBytesToEmit is smaller than the padding
224// size, the fixup encodes MaxBytesToEmit in the higher bits and references a
225// per-section marker symbol.
226bool LoongArchAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) {
227 if (!shouldRelaxAlign(F))
228 return false;
229
230 Size = F.getAlignment().value() - 4;
231 unsigned MaxBytesToEmit = F.getAlignMaxBytesToEmit();
232
233 MCContext &Ctx = getContext();
234 const MCExpr *Expr = nullptr;
235 if (MaxBytesToEmit >= Size) {
236 Expr = MCConstantExpr::create(Value: Size, Ctx&: getContext());
237 } else {
238 MCSection *Sec = F.getParent();
239 const MCSymbolRefExpr *SymRef = getSecToAlignSym()[Sec];
240 if (SymRef == nullptr) {
241 // Define a marker symbol at the section with an offset of 0.
242 MCSymbol *Sym = Ctx.createNamedTempSymbol(Name: "la-relax-align");
243 Sym->setFragment(&*Sec->getBeginSymbol()->getFragment());
244 Asm->registerSymbol(Symbol: *Sym);
245 SymRef = MCSymbolRefExpr::create(Symbol: Sym, Ctx);
246 getSecToAlignSym()[Sec] = SymRef;
247 }
248 Expr = MCBinaryExpr::createAdd(
249 LHS: SymRef,
250 RHS: MCConstantExpr::create(Value: (MaxBytesToEmit << 8) | Log2(A: F.getAlignment()),
251 Ctx),
252 Ctx);
253 }
254 MCFixup Fixup =
255 MCFixup::create(Offset: 0, Value: Expr, Kind: FirstLiteralRelocationKind + ELF::R_LARCH_ALIGN);
256 F.setVarFixups({Fixup});
257 F.setLinkerRelaxable();
258 return true;
259}
260
261std::pair<bool, bool> LoongArchAsmBackend::relaxLEB128(MCFragment &F,
262 int64_t &Value) const {
263 const MCExpr &Expr = F.getLEBValue();
264 if (F.isLEBSigned() || !Expr.evaluateKnownAbsolute(Res&: Value, Asm: *Asm))
265 return std::make_pair(x: false, y: false);
266 F.setVarFixups({MCFixup::create(Offset: 0, Value: &Expr, Kind: FK_Data_leb128)});
267 return std::make_pair(x: true, y: true);
268}
269
270bool LoongArchAsmBackend::relaxDwarfLineAddr(MCFragment &F) const {
271 MCContext &C = getContext();
272 int64_t LineDelta = F.getDwarfLineDelta();
273 const MCExpr &AddrDelta = F.getDwarfAddrDelta();
274 int64_t Value;
275 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm: *Asm))
276 return false;
277 [[maybe_unused]] bool IsAbsolute =
278 AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm: *Asm);
279 assert(IsAbsolute);
280
281 SmallVector<char> Data;
282 raw_svector_ostream OS(Data);
283
284 // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
285 if (LineDelta != INT64_MAX) {
286 OS << uint8_t(dwarf::DW_LNS_advance_line);
287 encodeSLEB128(Value: LineDelta, OS);
288 }
289
290 // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
291 // takes a single unsigned half (unencoded) operand. The maximum encodable
292 // value is therefore 65535. Set a conservative upper bound for relaxation.
293 unsigned PCBytes;
294 if (Value > 60000) {
295 unsigned PtrSize = C.getAsmInfo().getCodePointerSize();
296 assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size");
297 PCBytes = PtrSize;
298 OS << uint8_t(dwarf::DW_LNS_extended_op) << uint8_t(PtrSize + 1)
299 << uint8_t(dwarf::DW_LNE_set_address);
300 OS.write_zeros(NumZeros: PtrSize);
301 } else {
302 PCBytes = 2;
303 OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
304 support::endian::write<uint16_t>(os&: OS, value: 0, endian: llvm::endianness::little);
305 }
306 auto Offset = OS.tell() - PCBytes;
307
308 if (LineDelta == INT64_MAX) {
309 OS << uint8_t(dwarf::DW_LNS_extended_op);
310 OS << uint8_t(1);
311 OS << uint8_t(dwarf::DW_LNE_end_sequence);
312 } else {
313 OS << uint8_t(dwarf::DW_LNS_copy);
314 }
315
316 F.setVarContents(Data);
317 F.setVarFixups({MCFixup::create(Offset, Value: &AddrDelta,
318 Kind: MCFixup::getDataKindForSize(Size: PCBytes))});
319 return true;
320}
321
322bool LoongArchAsmBackend::relaxDwarfCFA(MCFragment &F) const {
323 const MCExpr &AddrDelta = F.getDwarfAddrDelta();
324 SmallVector<MCFixup, 2> Fixups;
325 int64_t Value;
326 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm: *Asm))
327 return false;
328 bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm: *Asm);
329 assert(IsAbsolute && "CFA with invalid expression");
330 (void)IsAbsolute;
331
332 assert(getContext().getAsmInfo().getMinInstAlignment() == 1 &&
333 "expected 1-byte alignment");
334 if (Value == 0) {
335 F.clearVarContents();
336 F.clearVarFixups();
337 return true;
338 }
339
340 auto AddFixups = [&Fixups,
341 &AddrDelta](unsigned Offset,
342 std::pair<MCFixupKind, MCFixupKind> FK) {
343 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(Val: AddrDelta);
344 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getLHS(), Kind: std::get<0>(in&: FK)));
345 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getRHS(), Kind: std::get<1>(in&: FK)));
346 };
347
348 SmallVector<char, 8> Data;
349 raw_svector_ostream OS(Data);
350 if (isUIntN(N: 6, x: Value)) {
351 OS << uint8_t(dwarf::DW_CFA_advance_loc);
352 AddFixups(0, getRelocPairForSize(Size: 6));
353 } else if (isUInt<8>(x: Value)) {
354 OS << uint8_t(dwarf::DW_CFA_advance_loc1);
355 support::endian::write<uint8_t>(os&: OS, value: 0, endian: llvm::endianness::little);
356 AddFixups(1, getRelocPairForSize(Size: 8));
357 } else if (isUInt<16>(x: Value)) {
358 OS << uint8_t(dwarf::DW_CFA_advance_loc2);
359 support::endian::write<uint16_t>(os&: OS, value: 0, endian: llvm::endianness::little);
360 AddFixups(1, getRelocPairForSize(Size: 16));
361 } else if (isUInt<32>(x: Value)) {
362 OS << uint8_t(dwarf::DW_CFA_advance_loc4);
363 support::endian::write<uint32_t>(os&: OS, value: 0, endian: llvm::endianness::little);
364 AddFixups(1, getRelocPairForSize(Size: 32));
365 } else {
366 llvm_unreachable("unsupported CFA encoding");
367 }
368 F.setVarContents(Data);
369 F.setVarFixups(Fixups);
370 return true;
371}
372
373bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
374 const MCSubtargetInfo *STI) const {
375 // We mostly follow binutils' convention here: align to 4-byte boundary with a
376 // 0-fill padding.
377 OS.write_zeros(NumZeros: Count % 4);
378
379 // The remainder is now padded with 4-byte nops.
380 // nop: andi r0, r0, 0
381 for (; Count >= 4; Count -= 4)
382 OS.write(Ptr: "\0\0\x40\x03", Size: 4);
383
384 return true;
385}
386
387bool LoongArchAsmBackend::isPCRelFixupResolved(const MCSymbol *SymA,
388 const MCFragment &F) {
389 // If the section does not contain linker-relaxable fragments, PC-relative
390 // fixups can be resolved.
391 if (!F.getParent()->isLinkerRelaxable())
392 return true;
393
394 // Otherwise, check if the offset between the symbol and fragment is fully
395 // resolved, unaffected by linker-relaxable fragments (e.g. instructions or
396 // offset-affected FT_Align fragments). Complements the generic
397 // isSymbolRefDifferenceFullyResolvedImpl.
398 if (!PCRelTemp)
399 PCRelTemp = getContext().createTempSymbol();
400 PCRelTemp->setFragment(const_cast<MCFragment *>(&F));
401 MCValue Res;
402 MCExpr::evaluateSymbolicAdd(Asm, false, MCValue::get(SymA),
403 MCValue::get(SymA: nullptr, SymB: PCRelTemp), Res);
404 return !Res.getSubSym();
405}
406
407void LoongArchAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
408 const MCValue &Target, uint64_t &FixedValue,
409 bool IsResolved) {
410 auto Fallback = [&]() {
411 MCAsmBackend::maybeAddReloc(F, Fixup, Target, Value&: FixedValue, IsResolved);
412 return;
413 };
414 uint64_t FixedValueA, FixedValueB;
415 if (Target.getSubSym()) {
416 // It's possible for Target to have (SymB != nullptr && SymA == nullptr).
417 // Go to the fallback path when we encounter this. See also #196927.
418 if (!Target.getAddSym())
419 return Fallback();
420
421 assert(Target.getSpecifier() == 0 &&
422 "relocatable SymA-SymB cannot have relocation specifier");
423 std::pair<MCFixupKind, MCFixupKind> FK;
424 const MCSymbol &SA = *Target.getAddSym();
425 const MCSymbol &SB = *Target.getSubSym();
426
427 bool force = !SA.isInSection() || !SB.isInSection();
428 if (!force) {
429 const MCSection &SecA = SA.getSection();
430 const MCSection &SecB = SB.getSection();
431 const MCSection &SecCur = *F.getParent();
432
433 // To handle the case of A - B which B is same section with the current,
434 // generate PCRel relocations is better than ADD/SUB relocation pair.
435 // We can resolve it as A - PC + PC - B. The A - PC will be resolved
436 // as a PCRel relocation, while PC - B will serve as the addend.
437 // If the linker relaxation is disabled, it can be done directly since
438 // PC - B is constant. Otherwise, we should evaluate whether PC - B
439 // is constant. If it can be resolved as PCRel, use Fallback which
440 // generates R_LARCH_{32,64}_PCREL relocation later.
441 if (&SecA != &SecB && &SecB == &SecCur &&
442 isPCRelFixupResolved(SymA: Target.getSubSym(), F))
443 return Fallback();
444
445 // In SecA == SecB case. If the section is not linker-relaxable, the
446 // FixedValue has already been calculated out in evaluateFixup,
447 // return true and avoid record relocations.
448 if (&SecA == &SecB && !SecA.isLinkerRelaxable())
449 return;
450 }
451
452 switch (Fixup.getKind()) {
453 case FK_Data_1:
454 FK = getRelocPairForSize(Size: 8);
455 break;
456 case FK_Data_2:
457 FK = getRelocPairForSize(Size: 16);
458 break;
459 case FK_Data_4:
460 FK = getRelocPairForSize(Size: 32);
461 break;
462 case FK_Data_8:
463 FK = getRelocPairForSize(Size: 64);
464 break;
465 case FK_Data_leb128:
466 FK = getRelocPairForSize(Size: 128);
467 break;
468 default:
469 llvm_unreachable("unsupported fixup size");
470 }
471 MCValue A = MCValue::get(SymA: Target.getAddSym(), SymB: nullptr, Val: Target.getConstant());
472 MCValue B = MCValue::get(SymA: Target.getSubSym());
473 auto FA = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: std::get<0>(in&: FK));
474 auto FB = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: std::get<1>(in&: FK));
475 Asm->getWriter().recordRelocation(F, Fixup: FA, Target: A, FixedValue&: FixedValueA);
476 Asm->getWriter().recordRelocation(F, Fixup: FB, Target: B, FixedValue&: FixedValueB);
477 FixedValue = FixedValueA - FixedValueB;
478 return;
479 }
480
481 // If linker relaxation is enabled and supported by the current relocation,
482 // generate a relocation and then append a RELAX.
483 if (Fixup.isLinkerRelaxable()) {
484 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
485 auto FA = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: ELF::R_LARCH_RELAX);
486 Asm->getWriter().recordRelocation(F, Fixup: FA, Target: MCValue::get(SymA: nullptr),
487 FixedValue&: FixedValueA);
488 return;
489 }
490
491 if (!IsResolved) {
492 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
493 return;
494 }
495
496 if (Fixup.isPCRel() && !isPCRelFixupResolved(SymA: Target.getAddSym(), F))
497 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
498}
499
500std::unique_ptr<MCObjectTargetWriter>
501LoongArchAsmBackend::createObjectTargetWriter() const {
502 return createLoongArchELFObjectWriter(OSABI, Is64Bit);
503}
504
505MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T,
506 const MCSubtargetInfo &STI,
507 const MCRegisterInfo &MRI,
508 const MCTargetOptions &Options) {
509 const Triple &TT = STI.getTargetTriple();
510 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TT.getOS());
511 return new LoongArchAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
512}
513