1//===-- PPCCallLowering.h - Call lowering for GlobalISel -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
12///
13//===----------------------------------------------------------------------===//
14
15#include "PPCCallLowering.h"
16#include "PPCCallingConv.h"
17#include "PPCISelLowering.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/GlobalISel/CallLowering.h"
20#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/TargetCallingConv.h"
23
24#define DEBUG_TYPE "ppc-call-lowering"
25
26using namespace llvm;
27
28namespace {
29
30struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
31 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
32 MachineInstrBuilder MIB)
33 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
34
35 void assignValueToReg(Register ValVReg, Register PhysReg,
36 const CCValAssign &VA,
37 ISD::ArgFlagsTy Flags = {}) override;
38 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
39 const MachinePointerInfo &MPO,
40 const CCValAssign &VA) override;
41 Register getStackAddress(uint64_t Size, int64_t Offset,
42 MachinePointerInfo &MPO,
43 ISD::ArgFlagsTy Flags) override;
44
45 MachineInstrBuilder MIB;
46};
47} // namespace
48
49void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,
50 const CCValAssign &VA,
51 ISD::ArgFlagsTy Flags) {
52 MIB.addUse(RegNo: PhysReg, Flags: RegState::Implicit);
53 Register ExtReg = extendRegister(ValReg: ValVReg, VA);
54 MIRBuilder.buildCopy(Res: PhysReg, Op: ExtReg);
55}
56
57void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr,
58 LLT MemTy,
59 const MachinePointerInfo &MPO,
60 const CCValAssign &VA) {
61 llvm_unreachable("unimplemented");
62}
63
64Register OutgoingArgHandler::getStackAddress(uint64_t Size, int64_t Offset,
65 MachinePointerInfo &MPO,
66 ISD::ArgFlagsTy Flags) {
67 llvm_unreachable("unimplemented");
68}
69
70PPCCallLowering::PPCCallLowering(const PPCTargetLowering &TLI)
71 : CallLowering(&TLI) {}
72
73bool PPCCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
74 const Value *Val, ArrayRef<Register> VRegs,
75 FunctionLoweringInfo &FLI,
76 Register SwiftErrorVReg) const {
77 auto MIB = MIRBuilder.buildInstrNoInsert(Opcode: PPC::BLR8);
78 bool Success = true;
79 MachineFunction &MF = MIRBuilder.getMF();
80 const Function &F = MF.getFunction();
81 MachineRegisterInfo &MRI = MF.getRegInfo();
82 auto &DL = F.getDataLayout();
83 if (!VRegs.empty()) {
84 // Setup the information about the return value.
85 ArgInfo OrigArg{VRegs, Val->getType(), 0};
86 setArgFlags(Arg&: OrigArg, OpIdx: AttributeList::ReturnIndex, DL, FuncInfo: F);
87
88 // Split the return value into consecutive registers if needed.
89 SmallVector<ArgInfo, 8> SplitArgs;
90 splitToValueTypes(OrigArgInfo: OrigArg, SplitArgs, DL, CallConv: F.getCallingConv());
91
92 // Use the calling convention callback to determine type and location of
93 // return value.
94 OutgoingValueAssigner ArgAssigner(RetCC_PPC);
95
96 // Handler to move the return value into the correct location.
97 OutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
98
99 // Iterate over all return values, and move them to the assigned location.
100 Success = determineAndHandleAssignments(Handler&: ArgHandler, Assigner&: ArgAssigner, Args&: SplitArgs,
101 MIRBuilder, CallConv: F.getCallingConv(),
102 IsVarArg: F.isVarArg());
103 }
104 MIRBuilder.insertInstr(MIB);
105 return Success;
106}
107
108bool PPCCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
109 CallLoweringInfo &Info) const {
110 return false;
111}
112
113bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
114 const Function &F,
115 ArrayRef<ArrayRef<Register>> VRegs,
116 FunctionLoweringInfo &FLI) const {
117 MachineFunction &MF = MIRBuilder.getMF();
118 MachineRegisterInfo &MRI = MF.getRegInfo();
119 const auto &DL = F.getDataLayout();
120 auto &TLI = *getTLI<PPCTargetLowering>();
121
122 // Loop over each arg, set flags and split to single value types
123 SmallVector<ArgInfo, 8> SplitArgs;
124 unsigned I = 0;
125 for (const auto &Arg : F.args()) {
126 if (DL.getTypeStoreSize(Ty: Arg.getType()).isZero())
127 continue;
128
129 ArgInfo OrigArg{VRegs[I], Arg, I};
130 setArgFlags(Arg&: OrigArg, OpIdx: I + AttributeList::FirstArgIndex, DL, FuncInfo: F);
131 splitToValueTypes(OrigArgInfo: OrigArg, SplitArgs, DL, CallConv: F.getCallingConv());
132 ++I;
133 }
134
135 CCAssignFn *AssignFn =
136 TLI.ccAssignFnForCall(CC: F.getCallingConv(), Return: false, IsVarArg: F.isVarArg());
137 IncomingValueAssigner ArgAssigner(AssignFn);
138 FormalArgHandler ArgHandler(MIRBuilder, MRI);
139 return determineAndHandleAssignments(Handler&: ArgHandler, Assigner&: ArgAssigner, Args&: SplitArgs,
140 MIRBuilder, CallConv: F.getCallingConv(),
141 IsVarArg: F.isVarArg());
142}
143
144void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
145 Register PhysReg,
146 const CCValAssign &VA,
147 ISD::ArgFlagsTy Flags) {
148 markPhysRegUsed(PhysReg);
149 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
150}
151
152void PPCIncomingValueHandler::assignValueToAddress(
153 Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
154 const CCValAssign &VA) {
155 // define a lambda expression to load value
156 auto BuildLoad = [](MachineIRBuilder &MIRBuilder,
157 const MachinePointerInfo &MPO, LLT MemTy,
158 const DstOp &Res, Register Addr) {
159 MachineFunction &MF = MIRBuilder.getMF();
160 auto *MMO = MF.getMachineMemOperand(PtrInfo: MPO, f: MachineMemOperand::MOLoad, MemTy,
161 base_alignment: inferAlignFromPtrInfo(MF, MPO));
162 return MIRBuilder.buildLoad(Res, Addr, MMO&: *MMO);
163 };
164
165 BuildLoad(MIRBuilder, MPO, MemTy, ValVReg, Addr);
166}
167
168Register PPCIncomingValueHandler::getStackAddress(uint64_t Size, int64_t Offset,
169 MachinePointerInfo &MPO,
170 ISD::ArgFlagsTy Flags) {
171 auto &MFI = MIRBuilder.getMF().getFrameInfo();
172 const bool IsImmutable = !Flags.isByVal();
173 int FI = MFI.CreateFixedObject(Size, SPOffset: Offset, IsImmutable);
174 MPO = MachinePointerInfo::getFixedStack(MF&: MIRBuilder.getMF(), FI);
175
176 // Build Frame Index based on whether the machine is 32-bit or 64-bit
177 llvm::LLT FramePtr = LLT::pointer(
178 AddressSpace: 0, SizeInBits: MIRBuilder.getMF().getDataLayout().getPointerSizeInBits());
179 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(Res: FramePtr, Idx: FI);
180 StackUsed = std::max(a: StackUsed, b: Size + Offset);
181 return AddrReg.getReg(Idx: 0);
182}
183
184void FormalArgHandler::markPhysRegUsed(unsigned PhysReg) {
185 MIRBuilder.getMRI()->addLiveIn(Reg: PhysReg);
186 MIRBuilder.getMBB().addLiveIn(PhysReg);
187}
188