1//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCMCCodeEmitter.h"
14#include "MCTargetDesc/PPCFixupKinds.h"
15#include "PPCMCAsmInfo.h"
16#include "PPCMCTargetDesc.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/Statistic.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCFixup.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/Support/Casting.h"
24#include "llvm/Support/EndianStream.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/TargetParser/Triple.h"
27#include <cassert>
28#include <cstdint>
29
30using namespace llvm;
31
32#define DEBUG_TYPE "mccodeemitter"
33
34STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35
36MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37 MCContext &Ctx) {
38 return new PPCMCCodeEmitter(MCII, Ctx);
39}
40
41static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
42 const MCExpr *Value, uint16_t Kind) {
43 bool PCRel = false;
44 switch (Kind) {
45 case PPC::fixup_ppc_br24:
46 case PPC::fixup_ppc_br24_notoc:
47 case PPC::fixup_ppc_brcond14:
48 case PPC::fixup_ppc_pcrel34:
49 case PPC::fixup_ppc_pcrel32:
50 PCRel = true;
51 }
52 Fixups.push_back(Elt: MCFixup::create(Offset, Value, Kind, PCRel));
53}
54
55unsigned PPCMCCodeEmitter::
56getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
57 SmallVectorImpl<MCFixup> &Fixups,
58 const MCSubtargetInfo &STI) const {
59 const MCOperand &MO = MI.getOperand(i: OpNo);
60
61 if (MO.isReg() || MO.isImm())
62 return getMachineOpValue(MI, MO, Fixups, STI);
63
64 // Add a fixup for the branch target.
65 addFixup(
66 Fixups, Offset: 0, Value: MO.getExpr(),
67 Kind: (isNoTOCCallInstr(MI) ? PPC::fixup_ppc_br24_notoc : PPC::fixup_ppc_br24));
68 return 0;
69}
70
71/// Check if Opcode corresponds to a call instruction that should be marked
72/// with the NOTOC relocation.
73bool PPCMCCodeEmitter::isNoTOCCallInstr(const MCInst &MI) const {
74 unsigned Opcode = MI.getOpcode();
75 if (!MCII.get(Opcode).isCall())
76 return false;
77
78 switch (Opcode) {
79 default:
80#ifndef NDEBUG
81 llvm_unreachable("Unknown call opcode");
82#endif
83 return false;
84 case PPC::BL8_NOTOC:
85 case PPC::BL8_NOTOC_TLS:
86 case PPC::BL8_NOTOC_RM:
87 return true;
88#ifndef NDEBUG
89 case PPC::BL8:
90 case PPC::BL:
91 case PPC::BL8_TLS:
92 case PPC::BL_TLS:
93 case PPC::BLA8:
94 case PPC::BLA:
95 case PPC::BCCL:
96 case PPC::BCCLA:
97 case PPC::BCL:
98 case PPC::BCLn:
99 case PPC::BL8_NOP:
100 case PPC::BL_NOP:
101 case PPC::BL8_NOP_TLS:
102 case PPC::BLA8_NOP:
103 case PPC::BCTRL8:
104 case PPC::BCTRL:
105 case PPC::BCCCTRL8:
106 case PPC::BCCCTRL:
107 case PPC::BCCTRL8:
108 case PPC::BCCTRL:
109 case PPC::BCCTRL8n:
110 case PPC::BCCTRLn:
111 case PPC::BL8_RM:
112 case PPC::BLA8_RM:
113 case PPC::BL8_NOP_RM:
114 case PPC::BLA8_NOP_RM:
115 case PPC::BCTRL8_RM:
116 case PPC::BCTRL8_LDinto_toc:
117 case PPC::BCTRL8_LDinto_toc_RM:
118 case PPC::BL8_TLS_:
119 case PPC::TCRETURNdi8:
120 case PPC::TCRETURNai8:
121 case PPC::TCRETURNri8:
122 case PPC::TAILBCTR8:
123 case PPC::TAILB8:
124 case PPC::TAILBA8:
125 case PPC::BCLalways:
126 case PPC::BLRL:
127 case PPC::BCCLRL:
128 case PPC::BCLRL:
129 case PPC::BCLRLn:
130 case PPC::BDZL:
131 case PPC::BDNZL:
132 case PPC::BDZLA:
133 case PPC::BDNZLA:
134 case PPC::BDZLp:
135 case PPC::BDNZLp:
136 case PPC::BDZLAp:
137 case PPC::BDNZLAp:
138 case PPC::BDZLm:
139 case PPC::BDNZLm:
140 case PPC::BDZLAm:
141 case PPC::BDNZLAm:
142 case PPC::BDZLRL:
143 case PPC::BDNZLRL:
144 case PPC::BDZLRLp:
145 case PPC::BDNZLRLp:
146 case PPC::BDZLRLm:
147 case PPC::BDNZLRLm:
148 case PPC::BL_RM:
149 case PPC::BLA_RM:
150 case PPC::BL_NOP_RM:
151 case PPC::BCTRL_RM:
152 case PPC::TCRETURNdi:
153 case PPC::TCRETURNai:
154 case PPC::TCRETURNri:
155 case PPC::BCTRL_LWZinto_toc:
156 case PPC::BCTRL_LWZinto_toc_RM:
157 case PPC::BL_LWZinto_toc:
158 case PPC::BL_LWZinto_toc_RM:
159 case PPC::BL8_LDinto_toc:
160 case PPC::BL8_LDinto_toc_RM:
161 case PPC::TAILBCTR:
162 case PPC::TAILB:
163 case PPC::TAILBA:
164 return false;
165#endif
166 }
167}
168
169unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
170 SmallVectorImpl<MCFixup> &Fixups,
171 const MCSubtargetInfo &STI) const {
172 const MCOperand &MO = MI.getOperand(i: OpNo);
173 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
174
175 // Add a fixup for the branch target.
176 addFixup(Fixups, Offset: 0, Value: MO.getExpr(), Kind: PPC::fixup_ppc_brcond14);
177 return 0;
178}
179
180unsigned PPCMCCodeEmitter::
181getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
182 SmallVectorImpl<MCFixup> &Fixups,
183 const MCSubtargetInfo &STI) const {
184 const MCOperand &MO = MI.getOperand(i: OpNo);
185 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
186
187 // Add a fixup for the branch target.
188 addFixup(Fixups, Offset: 0, Value: MO.getExpr(), Kind: PPC::fixup_ppc_br24abs);
189 return 0;
190}
191
192unsigned PPCMCCodeEmitter::
193getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
194 SmallVectorImpl<MCFixup> &Fixups,
195 const MCSubtargetInfo &STI) const {
196 const MCOperand &MO = MI.getOperand(i: OpNo);
197 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
198
199 // Add a fixup for the branch target.
200 addFixup(Fixups, Offset: 0, Value: MO.getExpr(), Kind: PPC::fixup_ppc_brcond14abs);
201 return 0;
202}
203
204unsigned
205PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
206 SmallVectorImpl<MCFixup> &Fixups,
207 const MCSubtargetInfo &STI) const {
208 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
209 unsigned RegBits = getMachineOpValue(MI, MO: MI.getOperand(i: OpNo), Fixups, STI)
210 << 1;
211 return RegBits;
212}
213
214template <MCFixupKind Fixup>
215uint64_t PPCMCCodeEmitter::getImmEncoding(const MCInst &MI, unsigned OpNo,
216 SmallVectorImpl<MCFixup> &Fixups,
217 const MCSubtargetInfo &STI) const {
218 const MCOperand &MO = MI.getOperand(i: OpNo);
219 assert(!MO.isReg() && "Not expecting a register for this operand.");
220 if (MO.isImm())
221 return getMachineOpValue(MI, MO, Fixups, STI);
222
223 uint32_t Offset = 0;
224 if (Fixup == PPC::fixup_ppc_half16)
225 Offset = IsLittleEndian ? 0 : 2;
226
227 // Add a fixup for the immediate field.
228 addFixup(Fixups, Offset, Value: MO.getExpr(), Kind: Fixup);
229 return 0;
230}
231
232unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
233 SmallVectorImpl<MCFixup> &Fixups,
234 const MCSubtargetInfo &STI) const {
235 const MCOperand &MO = MI.getOperand(i: OpNo);
236 if (MO.isImm())
237 return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
238
239 // Add a fixup for the displacement field.
240 addFixup(Fixups, Offset: IsLittleEndian ? 0 : 2, Value: MO.getExpr(), Kind: PPC::fixup_ppc_half16);
241 return 0;
242}
243
244unsigned
245PPCMCCodeEmitter::getDispRIXEncoding(const MCInst &MI, unsigned OpNo,
246 SmallVectorImpl<MCFixup> &Fixups,
247 const MCSubtargetInfo &STI) const {
248 const MCOperand &MO = MI.getOperand(i: OpNo);
249 if (MO.isImm())
250 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
251
252 // Add a fixup for the displacement field.
253 addFixup(Fixups, Offset: IsLittleEndian ? 0 : 2, Value: MO.getExpr(),
254 Kind: PPC::fixup_ppc_half16ds);
255 return 0;
256}
257
258unsigned
259PPCMCCodeEmitter::getDispRIX16Encoding(const MCInst &MI, unsigned OpNo,
260 SmallVectorImpl<MCFixup> &Fixups,
261 const MCSubtargetInfo &STI) const {
262 const MCOperand &MO = MI.getOperand(i: OpNo);
263 if (MO.isImm()) {
264 assert(!(MO.getImm() % 16) &&
265 "Expecting an immediate that is a multiple of 16");
266 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF);
267 }
268
269 // Otherwise add a fixup for the displacement field.
270 addFixup(Fixups, Offset: IsLittleEndian ? 0 : 2, Value: MO.getExpr(),
271 Kind: PPC::fixup_ppc_half16dq);
272 return 0;
273}
274
275unsigned
276PPCMCCodeEmitter::getDispRIHashEncoding(const MCInst &MI, unsigned OpNo,
277 SmallVectorImpl<MCFixup> &Fixups,
278 const MCSubtargetInfo &STI) const {
279 // Encode imm for the hash load/store to stack for the ROP Protection
280 // instructions.
281 const MCOperand &MO = MI.getOperand(i: OpNo);
282
283 assert(MO.isImm() && "Expecting an immediate operand.");
284 assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
285
286 unsigned DX = (MO.getImm() >> 3) & 0x3F;
287 return DX;
288}
289
290uint64_t
291PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
292 SmallVectorImpl<MCFixup> &Fixups,
293 const MCSubtargetInfo &STI) const {
294 // Encode the displacement part of pc-relative memri34, which is an imm34.
295 // The 34 bit immediate can fall into one of three cases:
296 // 1) It is a relocation to be filled in by the linker represented as:
297 // (MCExpr::SymbolRef)
298 // 2) It is a relocation + SignedOffset represented as:
299 // (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant))
300 // 3) It is a known value at compile time.
301
302 // If this is not a MCExpr then we are in case 3) and we are dealing with
303 // a value known at compile time, not a relocation.
304 const MCOperand &MO = MI.getOperand(i: OpNo);
305 if (!MO.isExpr())
306 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
307
308 // At this point in the function it is known that MO is of type MCExpr.
309 // Therefore we are dealing with either case 1) a symbol ref or
310 // case 2) a symbol ref plus a constant.
311 const MCExpr *Expr = MO.getExpr();
312 switch (Expr->getKind()) {
313 default:
314 llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
315 case MCExpr::SymbolRef: {
316 // Relocation alone.
317 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Val: Expr);
318 (void)SRE;
319 // Currently these are the only valid PCRelative Relocations.
320 assert(is_contained({PPC::S_PCREL, PPC::S_GOT_PCREL, PPC::S_GOT_TLSGD_PCREL,
321 PPC::S_GOT_TLSLD_PCREL, PPC::S_GOT_TPREL_PCREL},
322 SRE->getSpecifier()) &&
323 "specifier must be S_PCREL, S_GOT_PCREL, S_GOT_TLSGD_PCREL, "
324 "S_GOT_TLSLD_PCREL, or S_GOT_TPREL_PCREL");
325 // Generate the fixup for the relocation.
326 addFixup(Fixups, Offset: 0, Value: Expr, Kind: PPC::fixup_ppc_pcrel34);
327 // Put zero in the location of the immediate. The linker will fill in the
328 // correct value based on the relocation.
329 return 0;
330 }
331 case MCExpr::Binary: {
332 // Relocation plus some offset.
333 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Val: Expr);
334 assert(BE->getOpcode() == MCBinaryExpr::Add &&
335 "Binary expression opcode must be an add.");
336
337 const MCExpr *LHS = BE->getLHS();
338 const MCExpr *RHS = BE->getRHS();
339
340 // Need to check in both directions. Reloc+Offset and Offset+Reloc.
341 if (LHS->getKind() != MCExpr::SymbolRef)
342 std::swap(a&: LHS, b&: RHS);
343
344 if (LHS->getKind() != MCExpr::SymbolRef ||
345 RHS->getKind() != MCExpr::Constant)
346 llvm_unreachable("Expecting to have one constant and one relocation.");
347
348 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Val: LHS);
349 (void)SRE;
350 assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) &&
351 "Value must fit in 34 bits.");
352
353 // Currently these are the only valid PCRelative Relocations.
354 assert((getSpecifier(SRE) == PPC::S_PCREL ||
355 getSpecifier(SRE) == PPC::S_GOT_PCREL) &&
356 "VariantKind must be VK_PCREL or VK_GOT_PCREL");
357 // Generate the fixup for the relocation.
358 addFixup(Fixups, Offset: 0, Value: Expr, Kind: PPC::fixup_ppc_pcrel34);
359 // Put zero in the location of the immediate. The linker will fill in the
360 // correct value based on the relocation.
361 return 0;
362 }
363 }
364}
365
366uint64_t
367PPCMCCodeEmitter::getDispRI34Encoding(const MCInst &MI, unsigned OpNo,
368 SmallVectorImpl<MCFixup> &Fixups,
369 const MCSubtargetInfo &STI) const {
370 // Encode the displacement part of a memri34.
371 const MCOperand &MO = MI.getOperand(i: OpNo);
372 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
373}
374
375unsigned
376PPCMCCodeEmitter::getDispSPE8Encoding(const MCInst &MI, unsigned OpNo,
377 SmallVectorImpl<MCFixup> &Fixups,
378 const MCSubtargetInfo &STI) const {
379 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 8).
380 const MCOperand &MO = MI.getOperand(i: OpNo);
381 assert(MO.isImm());
382 return getMachineOpValue(MI, MO, Fixups, STI) >> 3;
383}
384
385unsigned
386PPCMCCodeEmitter::getDispSPE4Encoding(const MCInst &MI, unsigned OpNo,
387 SmallVectorImpl<MCFixup> &Fixups,
388 const MCSubtargetInfo &STI) const {
389 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 4).
390 const MCOperand &MO = MI.getOperand(i: OpNo);
391 assert(MO.isImm());
392 return getMachineOpValue(MI, MO, Fixups, STI) >> 2;
393}
394
395unsigned
396PPCMCCodeEmitter::getDispSPE2Encoding(const MCInst &MI, unsigned OpNo,
397 SmallVectorImpl<MCFixup> &Fixups,
398 const MCSubtargetInfo &STI) const {
399 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 2).
400 const MCOperand &MO = MI.getOperand(i: OpNo);
401 assert(MO.isImm());
402 return getMachineOpValue(MI, MO, Fixups, STI) >> 1;
403}
404
405unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
406 SmallVectorImpl<MCFixup> &Fixups,
407 const MCSubtargetInfo &STI) const {
408 const MCOperand &MO = MI.getOperand(i: OpNo);
409 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
410
411 // Add a fixup for the TLS register, which simply provides a relocation
412 // hint to the linker that this statement is part of a relocation sequence.
413 // Return the thread-pointer register's encoding. Add a one byte displacement
414 // if using PC relative memops.
415 const MCExpr *Expr = MO.getExpr();
416 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Val: Expr);
417 bool IsPCRel = getSpecifier(SRE) == PPC::S_TLS_PCREL;
418 addFixup(Fixups, Offset: IsPCRel ? 1 : 0, Value: Expr, Kind: PPC::fixup_ppc_nofixup);
419 const Triple &TT = STI.getTargetTriple();
420 bool isPPC64 = TT.isPPC64();
421 return CTX.getRegisterInfo()->getEncodingValue(Reg: isPPC64 ? PPC::X13 : PPC::R2);
422}
423
424unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
425 SmallVectorImpl<MCFixup> &Fixups,
426 const MCSubtargetInfo &STI) const {
427 // For special TLS calls, we need two fixups; one for the branch target
428 // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
429 // and one for the TLSGD or TLSLD symbol, which is emitted here.
430 const MCOperand &MO = MI.getOperand(i: OpNo+1);
431 addFixup(Fixups, Offset: 0, Value: MO.getExpr(), Kind: PPC::fixup_ppc_nofixup);
432 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
433}
434
435unsigned PPCMCCodeEmitter::
436get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
437 SmallVectorImpl<MCFixup> &Fixups,
438 const MCSubtargetInfo &STI) const {
439 const MCOperand &MO = MI.getOperand(i: OpNo);
440 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
441 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
442 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
443 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
444}
445
446// Get the index for this operand in this instruction. This is needed for
447// computing the register number in PPC::getRegNumForOperand() for
448// any instructions that use a different numbering scheme for registers in
449// different operands.
450static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
451 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
452 const MCOperand &Op = MI.getOperand(i);
453 if (&Op == &MO)
454 return i;
455 }
456 llvm_unreachable("This operand is not part of this instruction");
457 return ~0U; // Silence any warnings about no return.
458}
459
460uint64_t PPCMCCodeEmitter::
461getMachineOpValue(const MCInst &MI, const MCOperand &MO,
462 SmallVectorImpl<MCFixup> &Fixups,
463 const MCSubtargetInfo &STI) const {
464 if (MO.isReg()) {
465 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
466 // The GPR operand should come through here though.
467 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
468 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
469 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
470 unsigned OpNo = getOpIdxForMO(MI, MO);
471 MCRegister Reg =
472 PPC::getRegNumForOperand(Desc: MCII.get(Opcode: MI.getOpcode()), Reg: MO.getReg(), OpNo);
473 return CTX.getRegisterInfo()->getEncodingValue(Reg);
474 }
475
476 assert(MO.isImm() &&
477 "Relocation required in an instruction that we cannot encode!");
478 return MO.getImm();
479}
480
481void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI,
482 SmallVectorImpl<char> &CB,
483 SmallVectorImpl<MCFixup> &Fixups,
484 const MCSubtargetInfo &STI) const {
485 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
486
487 // Output the constant in big/little endian byte order.
488 unsigned Size = getInstSizeInBytes(MI);
489 llvm::endianness E =
490 IsLittleEndian ? llvm::endianness::little : llvm::endianness::big;
491 switch (Size) {
492 case 0:
493 break;
494 case 4:
495 support::endian::write<uint32_t>(Out&: CB, V: Bits, E);
496 break;
497 case 8:
498 // If we emit a pair of instructions, the first one is
499 // always in the top 32 bits, even on little-endian.
500 support::endian::write<uint32_t>(Out&: CB, V: Bits >> 32, E);
501 support::endian::write<uint32_t>(Out&: CB, V: Bits, E);
502 break;
503 default:
504 llvm_unreachable("Invalid instruction size");
505 }
506
507 ++MCNumEmitted; // Keep track of the # of mi's emitted.
508}
509
510// Get the number of bytes used to encode the given MCInst.
511unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
512 unsigned Opcode = MI.getOpcode();
513 const MCInstrDesc &Desc = MCII.get(Opcode);
514 return Desc.getSize();
515}
516
517bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const {
518 return MCII.get(Opcode: MI.getOpcode()).TSFlags & PPCII::Prefixed;
519}
520
521#include "PPCGenMCCodeEmitter.inc"
522